forked from xuos/xiuos
support i2c and fixed no shell bug
This commit is contained in:
wlyu
parent
9b83bc586e
commit
4edf73254e
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@ -71,6 +71,5 @@ int hc32_bringup(void)
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}
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#endif
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printf("start %s\n", __func__);
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return ret;
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}
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@ -86,8 +86,8 @@ extern "C"
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#define NR_IRQS (144 + 15)
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#define NVIC_SYSH_PRIORITY_MIN 0xf0
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
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#define NVIC_SYSH_PRIORITY_MIN 0U// 0xf0
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#define NVIC_SYSH_PRIORITY_DEFAULT 0U //0x80
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#define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT
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#define ARMV7M_PERIPHERAL_INTERRUPTS NR_IRQS
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@ -181,10 +181,27 @@ config HC32_SPI1
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config HC32_SPI2
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bool "SPI2"
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default n
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depends on HC32_HAVE_SPI2
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select SPI
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select HC32_SPI
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config HC32_I2C1
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bool "I2C1"
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default n
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select I2C
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select HC32_I2C
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config HC32_I2C2
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bool "I2C2"
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default n
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select I2C
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select HC32_I2C
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config HC32_I2C3
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bool "I2C3"
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default n
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select I2C
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select HC32_I2C
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config HC32_SPI
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bool
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@ -86,9 +86,11 @@ CHIP_CSRCS += hc32_console.c
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CHIP_CSRCS += hc32f4a0_clk.c hc32f4a0_efm.c hc32f4a0_gpio.c
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CHIP_CSRCS += hc32f4a0_interrupts.c hc32f4a0_usart.c hc32f4a0_utility.c
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CHIP_CSRCS += hc32f4a0_sram.c hc32f4a0_pwc.c
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CHIP_CSRCS += hc32f4a0_sram.c hc32f4a0_pwc.c hc32f4a0_i2c.c
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CHIP_CSRCS += hc32f4a0_spi.c
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CHIP_CSRCS += hc32_spiflash.c hc32_spi.c
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CHIP_CSRCS += hc32_i2c.c
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@ -18,6 +18,9 @@
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#include "hc32_uart.h"
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#include "hc32_spi.h"
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#define CMP_STR(_tar, _str) (strncmp(_tar, _str, strlen(_str)) == 0)
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extern int hc32_i2c_test(void);
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void hc32_test_console(void)
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{
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char *dev_str = "/dev/console";
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@ -31,16 +34,44 @@ void hc32_test_console(void)
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close(fd);
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}
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void hc32_bmp180_test(void)
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{
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char *bmp_dev = "/dev/bmp180";
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char write_arr[] = {0xF4, 0x2E};
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int fd = 0, ret;
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fd = open(bmp_dev, 0x6);
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ret = write(fd, write_arr, 2);
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hc32_print("%s: write attr ret %x\n", __func__, ret);
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close(fd);
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}
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void hc32_console_handle(char *buf)
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{
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if(strncmp(buf, "console", 7) == 0)
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if(CMP_STR(buf, "console"))
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{
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hc32_test_console();
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}
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else if(strncmp(buf, "spi", 7) == 0)
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else if(CMP_STR(buf, "spi"))
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{
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hc32_print("start flash test ...\n");
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hc32_print("start flash test %d ...\n", g_system_timer);
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hc32_spiflash_test();
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}
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else if(CMP_STR(buf, "i2c"))
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{
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hc32_print("start i2c test %d ...\n", g_system_timer);
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hc32_i2c_test();
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}
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else if(CMP_STR(buf, "bmp"))
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{
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hc32_print("start bmp180 test ...\n");
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hc32_bmp180_test();
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}
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else if(CMP_STR(buf, "pr"))
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{
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printf("z\n");
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hc32_print("start pr test %d ...\n", g_system_timer);
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printf("b\n");
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}
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}
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@ -39,6 +39,8 @@
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/****************************************************************************
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* Pre-Processor Declarations
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****************************************************************************/
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typedef uint32_t gpio_pinset_t;
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#define GPIO_OUTPUT_SET (1 << 25) /* Bit 8: If output, initial value of output */
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#define GPIO_OUTPUT_CLEAR (0)
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844
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_i2c.c
Executable file
844
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_i2c.c
Executable file
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@ -0,0 +1,844 @@
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/**
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*******************************************************************************
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* @file i2c/i2c_master_polling/source/main.c
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* @brief Main program of I2C master polling for the Device Driver Library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Hexiao First version
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2020-08-31 Hexiao Modify I2C init flow
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2020-09-04 Hexiao Modify compile warning
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2021-01-21 Hexiao Replace PWC_FCG1_IIC1 with PWC_FCG1_I2C1
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <nuttx/clock.h>
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#include <nuttx/semaphore.h>
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#include <nuttx/i2c/i2c_master.h>
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#include "hc32_ddl.h"
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#include "hc32_gpio.h"
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#include "hc32_uart.h"
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/**
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* @addtogroup HC32F4A0_DDL_Examples
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* @{
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*/
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/**
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* @addtogroup I2C_Master_Polling
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* @{
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*/
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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/* Define slave device address for example */
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#define DEVICE_ADDRESS (0x77U) //bmp180
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/* Define port and pin for SDA and SCL */
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#define I2C_SCL_PORT (GPIO_PORT_D)
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#define I2C_SCL_PIN (GPIO_PIN_03)
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#define I2C_SDA_PORT (GPIO_PORT_F)
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#define I2C_SDA_PIN (GPIO_PIN_10)
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#define I2C_RET_OK (0U)
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#define I2C_RET_ERROR (1U)
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#define GENERATE_START (0x00U)
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#define GENERATE_RESTART (0x01U)
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#define ADDRESS_W (0x00U)
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#define ADDRESS_R (0x01U)
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/* Define Write and read data length for the example */
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#define TEST_DATA_LEN (1U)
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/* Define i2c baudrate */
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#define I2C_BAUDRATE (400000UL)
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//#define LED_GREEN_PORT (GPIO_PORT_I)
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//#define LED_GREEN_PIN (GPIO_PIN_03)
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#define I2C_MASTER 1
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#define I2C_SLAVE 2
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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/* I2C Device hardware configuration */
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struct hc32_i2c_config_s
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{
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M4_I2C_TypeDef *base; /* I2C base address */
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gpio_pinset_t scl_pin; /* GPIO configuration for SCL as SCL */
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gpio_pinset_t sda_pin; /* GPIO configuration for SDA as SDA */
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uint8_t mode; /* Master or Slave mode */
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#ifndef CONFIG_I2C_POLLED
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uint32_t irq; /* Event IRQ */
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#endif
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};
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/* I2C Device Private Data */
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struct hc32_i2c_priv_s
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{
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/* Standard I2C operations */
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const struct i2c_ops_s *ops;
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/* Port configuration */
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const struct hc32_i2c_config_s *config;
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int refs; /* Reference count */
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sem_t sem_excl; /* Mutual exclusion semaphore */
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#ifndef CONFIG_I2C_POLLED
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sem_t sem_isr; /* Interrupt wait semaphore */
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#endif
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volatile uint8_t intstate; /* Interrupt handshake (see enum hc32_intstate_e) */
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uint8_t msgc; /* Message count */
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struct i2c_msg_s *msgv; /* Message list */
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uint8_t *ptr; /* Current message buffer */
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uint32_t frequency; /* Current I2C frequency */
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int dcnt; /* Current message length */
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uint16_t flags; /* Current message flags */
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uint32_t status; /* End of transfer SR2|SR1 status */
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};
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static int hc32_i2c_init(FAR struct hc32_i2c_priv_s *priv);
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static int hc32_i2c_deinit(FAR struct hc32_i2c_priv_s *priv);
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static int hc32_i2c_transfer(FAR struct i2c_master_s *dev,
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FAR struct i2c_msg_s *msgs, int count);
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#ifdef CONFIG_I2C_RESET
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static int hc32_i2c_reset(FAR struct i2c_master_s *dev);
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#endif
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/* I2C interface */
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static const struct i2c_ops_s hc32_i2c_ops =
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{
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.transfer = hc32_i2c_transfer
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#ifdef CONFIG_I2C_RESET
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, .reset = hc32_i2c_reset
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#endif
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};
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/* I2C device structures */
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#ifdef CONFIG_HC32_I2C1
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static const struct hc32_i2c_config_s hc32_i2c1_config =
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{
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.base = M4_I2C1,
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.scl_pin = GPIO_PINSET(I2C_SCL_PORT, I2C_SCL_PIN),
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.sda_pin = GPIO_PINSET(I2C_SDA_PORT, I2C_SDA_PIN),
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#ifndef CONFIG_I2C_SLAVE
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.mode = I2C_MASTER,
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#else
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.mode = I2C_SLAVE,
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#endif
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#ifndef CONFIG_I2C_POLLED
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.irq = EVT_I2C1_RXI,
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#endif
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};
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static struct hc32_i2c_priv_s hc32_i2c1_priv =
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{
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.ops = &hc32_i2c_ops,
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.config = &hc32_i2c1_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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.msgv = NULL,
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.ptr = NULL,
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.dcnt = 0,
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.flags = 0,
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.status = 0
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};
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#endif
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#ifdef CONFIG_HC32_I2C2
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static const struct hc32_i2c_config_s hc32_i2c2_config =
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{
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.base = M4_I2C2,
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.scl_pin = GPIO_PINSET(I2C_SCL_PORT, I2C_SCL_PIN),
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.sda_pin = GPIO_PINSET(I2C_SDA_PORT, I2C_SDA_PIN),
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#ifndef CONFIG_I2C_SLAVE
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.mode = I2C_MASTER,
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#else
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.mode = I2C_SLAVE,
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#endif
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#ifndef CONFIG_I2C_POLLED
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.irq = EVT_I2C2_RXI,
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#endif
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};
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static struct hc32_i2c_priv_s hc32_i2c2_priv =
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{
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.ops = &hc32_i2c_ops,
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.config = &hc32_i2c2_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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.msgv = NULL,
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.ptr = NULL,
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.dcnt = 0,
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.flags = 0,
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.status = 0
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};
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#endif
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#ifdef CONFIG_HC32_I2C3
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static const struct hc32_i2c_config_s hc32_i2c3_config =
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{
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.base = M4_I2C3,
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.scl_pin = GPIO_PINSET(I2C_SCL_PORT, I2C_SCL_PIN),
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.sda_pin = GPIO_PINSET(I2C_SDA_PORT, I2C_SDA_PIN),
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#ifndef CONFIG_I2C_SLAVE
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.mode = I2C_MASTER,
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#else
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.mode = I2C_SLAVE,
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#endif
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#ifndef CONFIG_I2C_POLLED
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.irq = EVT_I2C3_RXI,
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#endif
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};
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static struct hc32_i2c_priv_s hc32_i2c3_priv =
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{
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.ops = &hc32_i2c_ops,
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.config = &hc32_i2c3_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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.msgv = NULL,
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.ptr = NULL,
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.dcnt = 0,
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.flags = 0,
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.status = 0
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};
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#endif
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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#define I2C_TIMEOUT (0x24000U)
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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* @brief MCU Peripheral registers write unprotected.
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* @param None
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* @retval None
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* @note Comment/uncomment each API depending on APP requires.
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*/
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static void Peripheral_WE(void)
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{
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/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
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GPIO_Unlock();
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/* Unlock PWC register: FCG0 */
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PWC_FCG0_Unlock();
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/* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
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PWC_Unlock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1 | PWC_UNLOCK_CODE_2);
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/* Unlock SRAM register: WTCR */
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SRAM_WTCR_Unlock();
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/* Unlock SRAM register: CKCR */
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SRAM_CKCR_Unlock();
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/* Unlock all EFM registers */
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EFM_Unlock();
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/* Unlock EFM register: FWMC */
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//EFM_FWMC_Unlock();
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/* Unlock EFM OTP write protect registers */
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//EFM_OTP_WP_Unlock();
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/* Unlock all MPU registers */
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// MPU_Unlock();
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}
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/**
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* @brief MCU Peripheral registers write protected.
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* @param None
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* @retval None
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* @note Comment/uncomment each API depending on APP requires.
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*/
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static __attribute__((unused)) void Peripheral_WP(void)
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{
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/* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
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GPIO_Lock();
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/* Lock PWC register: FCG0 */
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PWC_FCG0_Lock();
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/* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
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PWC_Lock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1 | PWC_UNLOCK_CODE_2);
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/* Lock SRAM register: WTCR */
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SRAM_WTCR_Lock();
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/* Lock SRAM register: CKCR */
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SRAM_CKCR_Lock();
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/* Lock EFM OTP write protect registers */
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//EFM_OTP_WP_Lock();
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/* Lock EFM register: FWMC */
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//EFM_FWMC_Lock();
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/* Lock all EFM registers */
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EFM_Lock();
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/* Lock all MPU registers */
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// MPU_Lock();
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}
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//static void Master_LedInit(void)
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//{
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// stc_gpio_init_t stcGpioInit;
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//
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// /* RGB LED initialize */
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// (void)GPIO_StructInit(&stcGpioInit);
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// (void)GPIO_Init(LED_GREEN_PORT, LED_GREEN_PIN, &stcGpioInit);
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//
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// /* "Turn off" LED before set to output */
|
||||
// GPIO_ResetPins(LED_GREEN_PORT, LED_GREEN_PIN);
|
||||
//
|
||||
// /* Output enable */
|
||||
// GPIO_OE(LED_GREEN_PORT, LED_GREEN_PIN, Enable);
|
||||
//}
|
||||
|
||||
//static void Master_LedOn(void)
|
||||
//{
|
||||
// GPIO_SetPins(LED_GREEN_PORT, LED_GREEN_PIN);
|
||||
//}
|
||||
|
||||
/**
|
||||
* @brief Send start or restart condition
|
||||
* @param [in] u8Start Indicate the start mode, start or restart
|
||||
* @retval Process result
|
||||
* - I2C_RET_ERROR Send start or restart failed
|
||||
* - I2C_RET_OK Send start or restart success
|
||||
*/
|
||||
static en_result_t Master_StartOrRestart(uint8_t u8Start)
|
||||
{
|
||||
en_result_t enRet;
|
||||
|
||||
/* generate start or restart signal */
|
||||
if(GENERATE_START == u8Start)
|
||||
{
|
||||
enRet = I2C_Start(M4_I2C1,I2C_TIMEOUT);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear start status flag */
|
||||
enRet = I2C_Restart(M4_I2C1,I2C_TIMEOUT);
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send slave address
|
||||
* @param [in] u8Adr The slave address
|
||||
* @param [in] u8Dir The transfer direction @ref I2C_Transfer_Direction
|
||||
* @retval Process result
|
||||
* - I2C_RET_ERROR Send failed
|
||||
* - I2C_RET_OK Send success
|
||||
*/
|
||||
static en_result_t Master_SendAdr(uint8_t u8Adr, uint8_t u8Dir)
|
||||
{
|
||||
return I2C_TransAddr(M4_I2C1,u8Adr,u8Dir,I2C_TIMEOUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send data to slave
|
||||
* @param [in] pTxData Pointer to the data buffer
|
||||
* @param [in] u32Size Data size
|
||||
* @retval Process result
|
||||
* - I2C_RET_ERROR Send failed
|
||||
* - I2C_RET_OK Send success
|
||||
*/
|
||||
static en_result_t Master_WriteData(uint8_t const pTxData[], uint32_t u32Size)
|
||||
{
|
||||
return I2C_TransData(M4_I2C1, pTxData, u32Size,I2C_TIMEOUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write address and receive data from slave
|
||||
* @param [in] pRxData Pointer to the data buffer
|
||||
* @param [in] u32Size Data size
|
||||
* @retval Process result
|
||||
* - I2C_RET_ERROR Process failed
|
||||
* - I2C_RET_OK Process success
|
||||
*/
|
||||
static en_result_t Master_ReceiveAndStop(uint8_t pRxData[], uint32_t u32Size)
|
||||
{
|
||||
return I2C_MasterReceiveAndStop(M4_I2C1,pRxData, u32Size,I2C_TIMEOUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief General stop condition to slave
|
||||
* @param None
|
||||
* @retval Process result
|
||||
* - I2C_RET_ERROR Process failed
|
||||
* - I2C_RET_OK Process success
|
||||
*/
|
||||
static en_result_t Master_Stop(void)
|
||||
{
|
||||
return I2C_Stop(M4_I2C1,I2C_TIMEOUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the I2C peripheral for master
|
||||
* @param None
|
||||
* @retval Process result
|
||||
* - I2C_RET_ERROR Process failed
|
||||
* - I2C_RET_OK Process success
|
||||
*/
|
||||
static en_result_t Master_Initialize(void)
|
||||
{
|
||||
stc_i2c_init_t stcI2cInit;
|
||||
float32_t fErr;
|
||||
|
||||
I2C_DeInit(M4_I2C1);
|
||||
|
||||
(void)I2C_StructInit(&stcI2cInit);
|
||||
stcI2cInit.u32Baudrate = I2C_BAUDRATE;
|
||||
stcI2cInit.u32SclTime = 5U;
|
||||
stcI2cInit.u32ClkDiv = I2C_CLK_DIV4;
|
||||
en_result_t enRet = I2C_Init(M4_I2C1, &stcI2cInit, &fErr);
|
||||
I2C_BusWaitCmd(M4_I2C1, Enable);
|
||||
|
||||
if(enRet == Ok)
|
||||
{
|
||||
I2C_Cmd(M4_I2C1, Enable);
|
||||
}
|
||||
|
||||
return enRet;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Judge the result. LED0 toggle when result is error status.
|
||||
* @param [in] enRet Result to be judged
|
||||
* @retval None
|
||||
*/
|
||||
static void JudgeResult(en_result_t enRet)
|
||||
{
|
||||
if(Ok != enRet)
|
||||
{
|
||||
for(;;)
|
||||
{
|
||||
DDL_DelayMS(500U);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int hc32_i2c_init(FAR struct hc32_i2c_priv_s *priv)
|
||||
{
|
||||
return OK;
|
||||
}
|
||||
|
||||
static int hc32_i2c_deinit(FAR struct hc32_i2c_priv_s *priv)
|
||||
{
|
||||
return OK;
|
||||
}
|
||||
|
||||
static inline void hc32_i2c_sem_init(FAR struct hc32_i2c_priv_s *priv)
|
||||
{
|
||||
nxsem_init(&priv->sem_excl, 0, 1);
|
||||
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
/* This semaphore is used for signaling and, hence, should not have
|
||||
* priority inheritance enabled.
|
||||
*/
|
||||
|
||||
nxsem_init(&priv->sem_isr, 0, 0);
|
||||
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static inline void hc32_i2c_sem_destroy(FAR struct hc32_i2c_priv_s *priv)
|
||||
{
|
||||
nxsem_destroy(&priv->sem_excl);
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
nxsem_destroy(&priv->sem_isr);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hc32_i2c_sem_post
|
||||
*
|
||||
* Description:
|
||||
* Release the mutual exclusion semaphore
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void hc32_i2c_sem_post(struct hc32_i2c_priv_s *priv)
|
||||
{
|
||||
nxsem_post(&priv->sem_excl);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int hc32_i2c_transfer1(FAR struct i2c_master_s *dev,
|
||||
FAR struct i2c_msg_s *msgs, int count)
|
||||
{
|
||||
FAR struct hc32_i2c_priv_s *priv = (struct hc32_i2c_priv_s *)dev;
|
||||
uint32_t status = 0;
|
||||
#ifdef I2C1_FSMC_CONFLICT
|
||||
uint32_t ahbenr;
|
||||
#endif
|
||||
int ret;
|
||||
|
||||
DEBUGASSERT(count);
|
||||
|
||||
/* Ensure that address or flags don't change meanwhile */
|
||||
|
||||
ret = nxsem_wait(&priv->sem_excl);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
//
|
||||
//
|
||||
|
||||
/* Ensure that any ISR happening after we finish can't overwrite any user
|
||||
* data
|
||||
*/
|
||||
|
||||
priv->dcnt = 0;
|
||||
priv->ptr = NULL;
|
||||
|
||||
hc32_i2c_sem_post(priv);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int hc32_i2c_transfer(FAR struct i2c_master_s *dev,
|
||||
FAR struct i2c_msg_s *msgs, int count)
|
||||
{
|
||||
en_result_t ret;
|
||||
FAR struct hc32_i2c_priv_s *priv = (struct hc32_i2c_priv_s *)dev;
|
||||
|
||||
/* Initialize I2C peripheral and enable function*/
|
||||
ret = Master_Initialize();
|
||||
JudgeResult(ret);
|
||||
|
||||
/* I2C master data write*/
|
||||
ret = Master_StartOrRestart(GENERATE_START);
|
||||
JudgeResult(ret);
|
||||
ret = Master_SendAdr(msgs->addr, I2C_DIR_TX);
|
||||
JudgeResult(ret);
|
||||
ret = Master_WriteData(msgs->buffer, msgs->length);
|
||||
JudgeResult(ret);
|
||||
ret = Master_Stop();
|
||||
JudgeResult(ret);
|
||||
|
||||
/* 5mS delay for device*/
|
||||
DDL_DelayMS(5U);
|
||||
|
||||
/* I2C master data read*/
|
||||
ret = Master_StartOrRestart(GENERATE_START);
|
||||
if(1UL == msgs->length)
|
||||
{
|
||||
I2C_AckConfig(priv->config->base, I2C_NACK);
|
||||
}
|
||||
JudgeResult(ret);
|
||||
ret = Master_SendAdr(msgs->addr, I2C_DIR_RX);
|
||||
JudgeResult(ret);
|
||||
ret = Master_ReceiveAndStop(msgs->buffer, msgs->length);
|
||||
JudgeResult(ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int hc32_i2c_config(void)
|
||||
{
|
||||
/* Initialize I2C port*/
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
Peripheral_WE();
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
(void)GPIO_Init(I2C_SCL_PORT, I2C_SCL_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(I2C_SDA_PORT, I2C_SDA_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(I2C_SCL_PORT, I2C_SCL_PIN, GPIO_FUNC_49_I2C1_SCL, PIN_SUBFUNC_DISABLE);
|
||||
GPIO_SetFunc(I2C_SDA_PORT, I2C_SDA_PIN, GPIO_FUNC_48_I2C1_SDA, PIN_SUBFUNC_DISABLE);
|
||||
|
||||
/* Enable peripheral clock */
|
||||
PWC_Fcg1PeriphClockCmd(PWC_FCG1_I2C1, Enable);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief BSP clock initialize.
|
||||
* Set board system clock to PLLH@240MHz
|
||||
* Flash: 5 wait
|
||||
* SRAM_HS: 1 wait
|
||||
* SRAM1_2_3_4_B: 2 wait
|
||||
* PCLK0: 240MHz
|
||||
* PCLK1: 120MHz
|
||||
* PCLK2: 60MHz
|
||||
* PCLK3: 60MHz
|
||||
* PCLK4: 120MHz
|
||||
* EXCLK: 120MHz
|
||||
* HCLK: 240MHz
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_CLK_Init(void)
|
||||
{
|
||||
stc_clk_xtal_init_t stcXtalInit;
|
||||
stc_clk_pllh_init_t stcPLLHInit;
|
||||
|
||||
/* PCLK0, HCLK Max 240MHz */
|
||||
/* PCLK1, PCLK4 Max 120MHz */
|
||||
/* PCLK2, PCLK3 Max 60MHz */
|
||||
/* EX BUS Max 120MHz */
|
||||
CLK_ClkDiv(CLK_CATE_ALL, \
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
|
||||
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
|
||||
CLK_HCLK_DIV1));
|
||||
|
||||
CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8XtalMode = CLK_XTALMODE_OSC;
|
||||
stcXtalInit.u8XtalDrv = CLK_XTALDRV_LOW;
|
||||
stcXtalInit.u8XtalState = CLK_XTAL_ON;
|
||||
stcXtalInit.u8XtalStb = CLK_XTALSTB_2MS;
|
||||
CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLHStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*120 = 960MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLLH_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL;
|
||||
(void)CLK_PLLHInit(&stcPLLHInit);
|
||||
|
||||
/* Highspeed SRAM set to 1 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1);
|
||||
|
||||
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2);
|
||||
|
||||
/* 0-wait @ 40MHz */
|
||||
EFM_SetWaitCycle(EFM_WAIT_CYCLE_5);
|
||||
|
||||
/* 4 cycles for 200 ~ 250MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_READ_WAIT_4);
|
||||
|
||||
CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Main function of i2c_master_polling project
|
||||
* @param None
|
||||
* @retval int32_t return value, if needed
|
||||
*/
|
||||
int hc32_i2c_test(void)
|
||||
{
|
||||
en_result_t enRet;
|
||||
uint8_t u8TxBuf[TEST_DATA_LEN] = {0xD0};
|
||||
uint8_t u8RxBuf[TEST_DATA_LEN] = {0U};
|
||||
|
||||
hc32_i2c_config();
|
||||
|
||||
hc32_print("%s: %d start ...\n", __func__, __LINE__);
|
||||
|
||||
/* Initialize I2C peripheral and enable function*/
|
||||
enRet = Master_Initialize();
|
||||
JudgeResult(enRet);
|
||||
|
||||
hc32_print("%s: %d ret %d\n", __func__, __LINE__, enRet);
|
||||
|
||||
/* I2C master data write*/
|
||||
enRet = Master_StartOrRestart(GENERATE_START);
|
||||
JudgeResult(enRet);
|
||||
enRet = Master_SendAdr(DEVICE_ADDRESS, I2C_DIR_TX);
|
||||
JudgeResult(enRet);
|
||||
enRet = Master_WriteData(u8TxBuf, TEST_DATA_LEN);
|
||||
JudgeResult(enRet);
|
||||
enRet = Master_Stop();
|
||||
JudgeResult(enRet);
|
||||
|
||||
/* 5mS delay for device*/
|
||||
DDL_DelayMS(5U);
|
||||
|
||||
/* I2C master data read*/
|
||||
enRet = Master_StartOrRestart(GENERATE_START);
|
||||
if(1UL == TEST_DATA_LEN)
|
||||
{
|
||||
I2C_AckConfig(M4_I2C1, I2C_NACK);
|
||||
}
|
||||
|
||||
JudgeResult(enRet);
|
||||
enRet = Master_SendAdr(DEVICE_ADDRESS,I2C_DIR_RX);
|
||||
JudgeResult(enRet);
|
||||
enRet = Master_ReceiveAndStop(u8RxBuf, TEST_DATA_LEN);
|
||||
JudgeResult(enRet);
|
||||
|
||||
hc32_print("%s: i2c device id = %x\n", __func__, u8RxBuf[0]);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hc32_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize one I2C bus
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *hc32_i2cbus_initialize(int port)
|
||||
{
|
||||
struct hc32_i2c_priv_s * priv = NULL;
|
||||
irqstate_t flags;
|
||||
|
||||
/* Get I2C private structure */
|
||||
|
||||
switch (port)
|
||||
{
|
||||
#ifdef CONFIG_HC32_I2C1
|
||||
case 0:
|
||||
priv = (struct hc32_i2c_priv_s *)&hc32_i2c1_priv;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HC32_I2C2
|
||||
case 1:
|
||||
priv = (struct hc32_i2c_priv_s *)&hc32_i2c2_priv;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_HC32_I2C3
|
||||
case 2:
|
||||
priv = (struct hc32_i2c_priv_s *)&hc32_i2c3_priv;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Initialize private data for the first time, increment reference count,
|
||||
* power-up hardware and configure GPIOs.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
if ((volatile int)priv->refs++ == 0)
|
||||
{
|
||||
hc32_i2c_sem_init(priv);
|
||||
hc32_i2c_init(priv);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
return (struct i2c_master_s *)priv;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hc32_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* Uninitialize an I2C bus
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int hc32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
|
||||
{
|
||||
FAR struct hc32_i2c_priv_s *priv = (struct hc32_i2c_priv_s *)dev;
|
||||
irqstate_t flags;
|
||||
|
||||
DEBUGASSERT(dev);
|
||||
|
||||
/* Decrement reference count and check for underflow */
|
||||
|
||||
if (priv->refs == 0)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
if (--priv->refs > 0)
|
||||
{
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Disable power and other HW resource (GPIO's) */
|
||||
|
||||
hc32_i2c_deinit(priv);
|
||||
|
||||
/* Release unused resources */
|
||||
|
||||
hc32_i2c_sem_destroy(priv);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static void hc32_i2c_register(int bus)
|
||||
{
|
||||
FAR struct i2c_master_s *i2c;
|
||||
int ret;
|
||||
|
||||
i2c = hc32_i2cbus_initialize(bus);
|
||||
if (i2c == NULL)
|
||||
{
|
||||
syslog(LOG_ERR, "Failed to get I2C%d interface\n", bus);
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = i2c_register(i2c, bus);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "Failed to register I2C%d driver: %d\n", bus, ret);
|
||||
hc32_i2cbus_uninitialize(i2c);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
|
@ -153,11 +153,6 @@ static void up_idlepm(void)
|
|||
void up_idle(void)
|
||||
{
|
||||
|
||||
#if defined (CONFIG_HC32F4A0_BOARD)
|
||||
extern void hc32_uart_handle(void);
|
||||
hc32_uart_handle();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -64,49 +64,7 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define USART_CR1_USED_INTS (USART_CR1_RIE | USART_CR1_TXEIE | USART_CR1_PCE | USART_CR1_TCIE)
|
||||
|
||||
|
||||
/* Some sanity checks *******************************************************/
|
||||
|
||||
/* DMA configuration */
|
||||
|
||||
/* If DMA is enabled on any USART, then very that other pre-requisites
|
||||
* have also been selected.
|
||||
*/
|
||||
|
||||
/* Power management definitions */
|
||||
|
||||
#if defined(CONFIG_PM) && !defined(CONFIG_HC32_PM_SERIAL_ACTIVITY)
|
||||
# define CONFIG_HC32_PM_SERIAL_ACTIVITY 10
|
||||
#endif
|
||||
#if defined(CONFIG_PM)
|
||||
# define PM_IDLE_DOMAIN 0 /* Revisit */
|
||||
#endif
|
||||
|
||||
/* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART.
|
||||
* We need runtime detection in up_dma_setup and up_dma_shutdown
|
||||
* We use the default struct default init value of 0 which maps to
|
||||
* HC32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) which is not a U[S]ART.
|
||||
*/
|
||||
|
||||
#define INVALID_SERIAL_DMA_CHANNEL 0
|
||||
|
||||
/* Keep track if a Break was set
|
||||
*
|
||||
* Note:
|
||||
*
|
||||
* 1) This value is set in the priv->ie but never written to the control
|
||||
* register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
|
||||
* 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
|
||||
*
|
||||
* See up_restoreusartint where the masking is done.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_HC32_SERIALBRK_BSDCOMPAT
|
||||
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
|
||||
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
|
||||
#endif
|
||||
#define USART_CR1_USED_INTS (USART_CR1_RIE | USART_CR1_RTOIE | USART_CR1_TXEIE | USART_CR1_PCE | USART_CR1_TCIE)
|
||||
|
||||
#ifdef USE_SERIALDRIVER
|
||||
#ifdef HAVE_SERIALDRIVER
|
||||
|
|
@ -705,6 +663,10 @@ static struct up_dev_s * const g_uart_devs[HC32_NUSART] =
|
|||
|
||||
static inline uint32_t up_serialin(struct up_dev_s *priv, int offset);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
void hc32_rx_irq_cb(void)
|
||||
{
|
||||
up_interrupt(g_uart_rx_dev->rx_irq, NULL, g_uart_rx_dev);
|
||||
|
|
@ -725,54 +687,34 @@ void hc32_err_irq_cb(void)
|
|||
up_interrupt(g_uart_rx_dev->err_irq, NULL, g_uart_rx_dev);
|
||||
}
|
||||
|
||||
void hc32_handle_recv_buf(void)
|
||||
{
|
||||
struct up_dev_s *priv = g_uart_rx_dev;
|
||||
struct uart_buffer_s *recv = &priv->dev.recv;
|
||||
char recv_buf[255] = {0};
|
||||
int i, j = 0;
|
||||
static int cnt = 0;
|
||||
static int last_tail = 0;
|
||||
|
||||
if((recv->head != recv->tail) && (cnt ++ > 30))
|
||||
{
|
||||
last_tail = recv->tail;
|
||||
for(i = recv->tail; i < recv->head; i ++)
|
||||
{
|
||||
recv_buf[j++] = recv->buffer[last_tail++];
|
||||
}
|
||||
hc32_console_handle(recv_buf);
|
||||
hc32_print("nsh>%s\n", recv_buf);
|
||||
recv->tail = recv->head;
|
||||
cnt = 0;
|
||||
last_tail = 0;
|
||||
}
|
||||
static int hc32_err_irq_handler(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
IRQ011_Handler();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void hc32_handle_xmit_buf(void)
|
||||
static int hc32_rx_irq_handler(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
struct up_dev_s *priv = g_uart_rx_dev;
|
||||
int i, j = 0;
|
||||
char xmit_buf[255] = {0};
|
||||
|
||||
if(priv->dev.xmit.tail != priv->dev.xmit.head)
|
||||
{
|
||||
for(i = priv->dev.xmit.tail; i < priv->dev.xmit.head; i ++)
|
||||
{
|
||||
xmit_buf[j++] = priv->dev.xmit.buffer[i++];
|
||||
}
|
||||
hc32_print("nsh>%s", xmit_buf);
|
||||
}
|
||||
up_irq_save();
|
||||
IRQ012_Handler();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void hc32_uart_handle(void)
|
||||
static int hc32_tx_irq_handler(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
hc32_handle_recv_buf();
|
||||
up_irq_save();
|
||||
IRQ013_Handler();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
static int hc32_tci_irq_handler(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
IRQ014_Handler();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hc32_print(const char *fmt, ...)
|
||||
{
|
||||
|
|
@ -802,7 +744,7 @@ int hc32_print(const char *fmt, ...)
|
|||
* @param [in] u32Priority Interrupt priority
|
||||
* @retval None
|
||||
*/
|
||||
static void hc32_enable_irq(const stc_irq_signin_config_t *pstcConfig,
|
||||
static void hc32_serial_enableirq(const stc_irq_signin_config_t *pstcConfig,
|
||||
uint32_t u32Priority)
|
||||
{
|
||||
if (NULL != pstcConfig)
|
||||
|
|
@ -919,45 +861,6 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
|
|||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
static int hc32_enable_serialirq(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
stc_irq_signin_config_t cfg;
|
||||
|
||||
{
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->rx_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->rxint_src;
|
||||
cfg.pfnCallback = &hc32_rx_irq_cb;
|
||||
hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
}
|
||||
|
||||
{
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->tx_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->txint_src;
|
||||
cfg.pfnCallback = &hc32_tx_irq_cb;
|
||||
hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
}
|
||||
|
||||
{
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->txc_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->txcint_src;
|
||||
cfg.pfnCallback = &hc32_txc_irq_cb;
|
||||
hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
}
|
||||
|
||||
{
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->err_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->errint_src;
|
||||
cfg.pfnCallback = &hc32_err_irq_cb;
|
||||
hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_setup
|
||||
|
|
@ -971,6 +874,102 @@ static int up_setup(struct uart_dev_s *dev)
|
|||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_UART_CONFIG
|
||||
uint32_t regval;
|
||||
|
||||
/* Note: The logic here depends on the fact that that the USART module
|
||||
* was enabled in stm32_lowsetup().
|
||||
*/
|
||||
|
||||
/* Enable USART APB1/2 clock */
|
||||
|
||||
// up_set_apb_clock(dev, true);
|
||||
|
||||
/* Configure pins for USART use */
|
||||
|
||||
hc32_configgpio(priv->tx_gpio);
|
||||
hc32_configgpio(priv->rx_gpio);
|
||||
|
||||
#ifdef CONFIG_SERIAL_OFLOWCONTROL
|
||||
if (priv->cts_gpio != 0)
|
||||
{
|
||||
hc32_configgpio(priv->cts_gpio);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
||||
if (priv->rts_gpio != 0)
|
||||
{
|
||||
uint32_t config = priv->rts_gpio;
|
||||
|
||||
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
|
||||
/* Instead of letting hw manage this pin, we will bitbang */
|
||||
|
||||
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
|
||||
#endif
|
||||
hc32_configgpio(config);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_RS485
|
||||
if (priv->rs485_dir_gpio != 0)
|
||||
{
|
||||
hc32_configgpio(priv->rs485_dir_gpio);
|
||||
hc32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure CR2
|
||||
* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits
|
||||
*/
|
||||
|
||||
regval = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR2));
|
||||
regval &= ~(USART_CR2_STOP | USART_CR2_CLKC | USART_CR2_WKUPIE |
|
||||
USART_CR2_BEIE | USART_CR2_LBDIE | USART_CR2_LBDIE);
|
||||
|
||||
/* Configure STOP bits */
|
||||
|
||||
if (priv->stopbits2)
|
||||
{
|
||||
regval |= USART_CR2_STOP;
|
||||
}
|
||||
|
||||
up_serialout(priv, offsetof(M4_USART_TypeDef, _CR2), regval);
|
||||
|
||||
/* Configure CR1
|
||||
* Clear TE, REm and all interrupt enable bits
|
||||
*/
|
||||
|
||||
regval = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1));
|
||||
regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_RTOE);
|
||||
|
||||
up_serialout(priv, offsetof(M4_USART_TypeDef, _CR1), regval);
|
||||
|
||||
/* Configure CR3
|
||||
* Clear CTSE, RTSE, and all interrupt enable bits
|
||||
*/
|
||||
|
||||
regval = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR3));
|
||||
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE );
|
||||
|
||||
up_serialout(priv, offsetof(M4_USART_TypeDef, _CR3), regval);
|
||||
|
||||
/* Configure the USART line format and speed. */
|
||||
|
||||
// up_set_format(dev);
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
regval = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1));
|
||||
|
||||
regval |= (USART_CR1_RTOE | USART_CR1_RTOIE | USART_CR1_TE |
|
||||
USART_CR1_RE | USART_CR1_RIE | USART_CR1_TXEIE | USART_CR1_TCIE);
|
||||
|
||||
up_serialout(priv, offsetof(M4_USART_TypeDef, _CR1), regval);
|
||||
|
||||
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
|
||||
|
||||
|
||||
/* Set up the cached interrupt enables value */
|
||||
|
||||
priv->ie = 0;
|
||||
|
|
@ -1062,13 +1061,39 @@ static void up_shutdown(struct uart_dev_s *dev)
|
|||
static int up_attach(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
int ret = 0;
|
||||
stc_irq_signin_config_t cfg;
|
||||
|
||||
hc32_print("%s: attach irq rx %d %d tx %d %d\n", __func__, priv->rx_irq, priv->rxint_src,
|
||||
priv->tx_irq, priv->txint_src);
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->rx_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->rxint_src;
|
||||
cfg.pfnCallback = &hc32_rx_irq_cb;
|
||||
hc32_serial_enableirq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
|
||||
ret = hc32_enable_serialirq(dev);
|
||||
return ret;
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->tx_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->txint_src;
|
||||
cfg.pfnCallback = &hc32_tx_irq_cb;
|
||||
hc32_serial_enableirq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->txc_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->txcint_src;
|
||||
cfg.pfnCallback = &hc32_txc_irq_cb;
|
||||
hc32_serial_enableirq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
|
||||
memset(&cfg, 0, sizeof(cfg));
|
||||
cfg.enIRQn = priv->err_irq - HC32_IRQ_FIRST;
|
||||
cfg.enIntSrc = priv->errint_src;
|
||||
cfg.pfnCallback = &hc32_err_irq_cb;
|
||||
hc32_serial_enableirq(&cfg, DDL_IRQ_PRIORITY_DEFAULT);
|
||||
|
||||
irq_attach(HC32_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(HC32_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
irq_attach(USART_UNIT_ERR_INT_IRQn, hc32_err_irq_handler, NULL);
|
||||
irq_attach(USART_UNIT_RX_INT_IRQn, hc32_rx_irq_handler, NULL);
|
||||
irq_attach(USART_UNIT_TX_INT_IRQn, hc32_tx_irq_handler, NULL);
|
||||
irq_attach(USART_UNIT_TCI_INT_IRQn, hc32_tci_irq_handler, NULL);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1084,10 +1109,14 @@ static int up_attach(struct uart_dev_s *dev)
|
|||
static void up_detach(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
up_disable_irq(priv->irq);
|
||||
irq_detach(priv->irq);
|
||||
|
||||
hc32_print("check %s line %d irq %d\n", __func__, __LINE__, priv->irq);
|
||||
up_disable_irq(priv->rx_irq);
|
||||
irq_detach(priv->rx_irq);
|
||||
up_disable_irq(priv->tx_irq);
|
||||
irq_detach(priv->tx_irq);
|
||||
up_disable_irq(priv->txc_irq);
|
||||
irq_detach(priv->txc_irq);
|
||||
up_disable_irq(priv->err_irq);
|
||||
irq_detach(priv->err_irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1535,24 +1564,14 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
|||
* (or an Rx timeout occurs).
|
||||
*/
|
||||
|
||||
ie |= USART_CR1_RIE;
|
||||
ie |= USART_CR1_RIE | USART_CR1_RTOIE | USART_CR1_RTOE | USART_CR1_TE | USART_CR1_RE;
|
||||
|
||||
up_enable_irq(priv->irq);
|
||||
|
||||
/* Enable TX && RX && RX interrupt function */
|
||||
USART_FuncCmd((M4_USART_TypeDef *)priv->usartbase,
|
||||
(USART_RX | USART_INT_RX | USART_TX | \
|
||||
USART_RTO | USART_INT_RTO), Enable);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
ie &= ~(USART_CR1_RIE);
|
||||
ie &= ~(USART_CR1_RIE | USART_CR1_RTOIE | USART_CR1_RTOE);
|
||||
up_disable_irq(priv->irq);
|
||||
|
||||
USART_FuncCmd((M4_USART_TypeDef *)priv->usartbase,
|
||||
(USART_RX | USART_INT_RX | USART_TX | \
|
||||
USART_RTO | USART_INT_RTO), Disable);
|
||||
}
|
||||
|
||||
/* Then set the new interrupt state */
|
||||
|
|
@ -1560,8 +1579,6 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
|||
up_restoreusartint(priv, ie);
|
||||
leave_critical_section(flags);
|
||||
|
||||
hc32_print("%s: opened %d irq %d %s ie %x\n", __func__, dev->open_count, priv->irq,
|
||||
enable ? "enable" : "disable", ie);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1740,11 +1757,11 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
|||
|
||||
static bool up_txready(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase;
|
||||
|
||||
return((Set == USART_GetStatus(base, USART_FLAG_TXE))
|
||||
|| (Set == USART_GetStatus(base, USART_FLAG_TC)));
|
||||
// struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
// M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase;
|
||||
// return((Set == USART_GetStatus(base, USART_FLAG_TXE))
|
||||
// || (Set == USART_GetStatus(base, USART_FLAG_TC)));
|
||||
return Set;
|
||||
}
|
||||
|
||||
#endif /* HAVE_SERIALDRIVER */
|
||||
|
|
@ -1834,30 +1851,19 @@ void arm_serialinit(void)
|
|||
char devname[16];
|
||||
unsigned i;
|
||||
unsigned minor = 0;
|
||||
int ret;
|
||||
|
||||
/* Register to receive power management callbacks */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
ret = pm_register(&g_serialcb);
|
||||
DEBUGASSERT(ret == OK);
|
||||
UNUSED(ret);
|
||||
#endif
|
||||
|
||||
/* Register the console */
|
||||
|
||||
#if CONSOLE_UART > 0
|
||||
ret = uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
|
||||
uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
|
||||
|
||||
#ifndef CONFIG_HC32_SERIAL_DISABLE_REORDERING
|
||||
/* If not disabled, register the console UART to ttyS0 and exclude
|
||||
* it from initializing it further down
|
||||
*/
|
||||
|
||||
ret = uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev);
|
||||
uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev);
|
||||
minor = 1;
|
||||
|
||||
hc32_print("register /dev/ttyS0 %d = %d\n", CONSOLE_UART - 1, ret);
|
||||
#endif
|
||||
|
||||
#endif /* CONSOLE_UART > 0 */
|
||||
|
|
|
|||
|
|
@ -95,6 +95,11 @@ static int hc32_timerisr(int irq, uint32_t *regs, void *arg)
|
|||
}
|
||||
#endif
|
||||
|
||||
void SysTick_IrqHandler(void)
|
||||
{
|
||||
nxsched_process_timer();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -77,7 +77,6 @@ extern void exception_common(void);
|
|||
* Note that the [ ... ] designated initializer is a GCC extension.
|
||||
*/
|
||||
|
||||
#if 0
|
||||
unsigned _vectors[] locate_data(".vectors") =
|
||||
{
|
||||
/* Initial stack */
|
||||
|
|
@ -92,175 +91,3 @@ unsigned _vectors[] locate_data(".vectors") =
|
|||
|
||||
[2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
|
||||
};
|
||||
#else
|
||||
unsigned _vectors[] locate_data(".vectors") =
|
||||
{
|
||||
/* Initial stack */
|
||||
|
||||
IDLE_STACK,
|
||||
|
||||
/* Reset exception handler */
|
||||
|
||||
(unsigned)&__start,
|
||||
(unsigned)&NMI_Handler,
|
||||
(unsigned)&HardFault_Handler,
|
||||
(unsigned)&MemManage_Handler,
|
||||
(unsigned)&BusFault_Handler,
|
||||
(unsigned)&UsageFault_Handler,
|
||||
(unsigned)&exception_common,
|
||||
(unsigned)&exception_common,
|
||||
(unsigned)&exception_common,
|
||||
(unsigned)&exception_common,
|
||||
(unsigned)&SVC_Handler, /* SVC */
|
||||
(unsigned)&DebugMon_Handler, /* DebugMon */
|
||||
(unsigned)&exception_common,
|
||||
(unsigned)&PendSV_Handler,
|
||||
(unsigned)&SysTick_Handler, /* SysTick */
|
||||
(unsigned)&IRQ000_Handler,
|
||||
(unsigned)&IRQ001_Handler,
|
||||
(unsigned)&IRQ002_Handler,
|
||||
(unsigned)&IRQ003_Handler,
|
||||
(unsigned)&IRQ004_Handler,
|
||||
(unsigned)&IRQ005_Handler,
|
||||
(unsigned)&IRQ006_Handler,
|
||||
(unsigned)&IRQ007_Handler,
|
||||
(unsigned)&IRQ008_Handler,
|
||||
(unsigned)&IRQ009_Handler,
|
||||
(unsigned)&IRQ010_Handler,
|
||||
(unsigned)&IRQ011_Handler,
|
||||
(unsigned)&IRQ012_Handler,
|
||||
(unsigned)&IRQ013_Handler,
|
||||
(unsigned)&IRQ014_Handler,
|
||||
(unsigned)&IRQ015_Handler,
|
||||
(unsigned)&IRQ016_Handler,
|
||||
(unsigned)&IRQ017_Handler,
|
||||
(unsigned)&IRQ018_Handler,
|
||||
(unsigned)&IRQ019_Handler,
|
||||
(unsigned)&IRQ020_Handler,
|
||||
(unsigned)&IRQ021_Handler,
|
||||
(unsigned)&IRQ022_Handler,
|
||||
(unsigned)&IRQ023_Handler,
|
||||
(unsigned)&IRQ024_Handler,
|
||||
(unsigned)&IRQ025_Handler,
|
||||
(unsigned)&IRQ026_Handler,
|
||||
(unsigned)&IRQ027_Handler,
|
||||
(unsigned)&IRQ028_Handler,
|
||||
(unsigned)&IRQ029_Handler,
|
||||
(unsigned)&IRQ030_Handler,
|
||||
(unsigned)&IRQ031_Handler,
|
||||
(unsigned)&IRQ032_Handler,
|
||||
(unsigned)&IRQ033_Handler,
|
||||
(unsigned)&IRQ034_Handler,
|
||||
(unsigned)&IRQ035_Handler,
|
||||
(unsigned)&IRQ036_Handler,
|
||||
(unsigned)&IRQ037_Handler,
|
||||
(unsigned)&IRQ038_Handler,
|
||||
(unsigned)&IRQ039_Handler,
|
||||
(unsigned)&IRQ040_Handler,
|
||||
(unsigned)&IRQ041_Handler,
|
||||
(unsigned)&IRQ042_Handler,
|
||||
(unsigned)&IRQ043_Handler,
|
||||
(unsigned)&IRQ044_Handler,
|
||||
(unsigned)&IRQ045_Handler,
|
||||
(unsigned)&IRQ046_Handler,
|
||||
(unsigned)&IRQ047_Handler,
|
||||
(unsigned)&IRQ048_Handler,
|
||||
(unsigned)&IRQ049_Handler,
|
||||
(unsigned)&IRQ050_Handler,
|
||||
(unsigned)&IRQ051_Handler,
|
||||
(unsigned)&IRQ052_Handler,
|
||||
(unsigned)&IRQ053_Handler,
|
||||
(unsigned)&IRQ054_Handler,
|
||||
(unsigned)&IRQ055_Handler,
|
||||
(unsigned)&IRQ056_Handler,
|
||||
(unsigned)&IRQ057_Handler,
|
||||
(unsigned)&IRQ058_Handler,
|
||||
(unsigned)&IRQ059_Handler,
|
||||
(unsigned)&IRQ060_Handler,
|
||||
(unsigned)&IRQ061_Handler,
|
||||
(unsigned)&IRQ062_Handler,
|
||||
(unsigned)&IRQ063_Handler,
|
||||
(unsigned)&IRQ064_Handler,
|
||||
(unsigned)&IRQ065_Handler,
|
||||
(unsigned)&IRQ066_Handler,
|
||||
(unsigned)&IRQ067_Handler,
|
||||
(unsigned)&IRQ068_Handler,
|
||||
(unsigned)&IRQ069_Handler,
|
||||
(unsigned)&IRQ070_Handler,
|
||||
(unsigned)&IRQ071_Handler,
|
||||
(unsigned)&IRQ072_Handler,
|
||||
(unsigned)&IRQ073_Handler,
|
||||
(unsigned)&IRQ074_Handler,
|
||||
(unsigned)&IRQ075_Handler,
|
||||
(unsigned)&IRQ076_Handler,
|
||||
(unsigned)&IRQ077_Handler,
|
||||
(unsigned)&IRQ078_Handler,
|
||||
(unsigned)&IRQ079_Handler,
|
||||
(unsigned)&IRQ080_Handler,
|
||||
(unsigned)&IRQ081_Handler,
|
||||
(unsigned)&IRQ082_Handler,
|
||||
(unsigned)&IRQ083_Handler,
|
||||
(unsigned)&IRQ084_Handler,
|
||||
(unsigned)&IRQ085_Handler,
|
||||
(unsigned)&IRQ086_Handler,
|
||||
(unsigned)&IRQ087_Handler,
|
||||
(unsigned)&IRQ088_Handler,
|
||||
(unsigned)&IRQ089_Handler,
|
||||
(unsigned)&IRQ090_Handler,
|
||||
(unsigned)&IRQ091_Handler,
|
||||
(unsigned)&IRQ092_Handler,
|
||||
(unsigned)&IRQ093_Handler,
|
||||
(unsigned)&IRQ094_Handler,
|
||||
(unsigned)&IRQ095_Handler,
|
||||
(unsigned)&IRQ096_Handler,
|
||||
(unsigned)&IRQ097_Handler,
|
||||
(unsigned)&IRQ098_Handler,
|
||||
(unsigned)&IRQ099_Handler,
|
||||
(unsigned)&IRQ100_Handler,
|
||||
(unsigned)&IRQ101_Handler,
|
||||
(unsigned)&IRQ102_Handler,
|
||||
(unsigned)&IRQ103_Handler,
|
||||
(unsigned)&IRQ104_Handler,
|
||||
(unsigned)&IRQ105_Handler,
|
||||
(unsigned)&IRQ106_Handler,
|
||||
(unsigned)&IRQ107_Handler,
|
||||
(unsigned)&IRQ108_Handler,
|
||||
(unsigned)&IRQ109_Handler,
|
||||
(unsigned)&IRQ110_Handler,
|
||||
(unsigned)&IRQ111_Handler,
|
||||
(unsigned)&IRQ112_Handler,
|
||||
(unsigned)&IRQ113_Handler,
|
||||
(unsigned)&IRQ114_Handler,
|
||||
(unsigned)&IRQ115_Handler,
|
||||
(unsigned)&IRQ116_Handler,
|
||||
(unsigned)&IRQ117_Handler,
|
||||
(unsigned)&IRQ118_Handler,
|
||||
(unsigned)&IRQ119_Handler,
|
||||
(unsigned)&IRQ120_Handler,
|
||||
(unsigned)&IRQ121_Handler,
|
||||
(unsigned)&IRQ122_Handler,
|
||||
(unsigned)&IRQ123_Handler,
|
||||
(unsigned)&IRQ124_Handler,
|
||||
(unsigned)&IRQ125_Handler,
|
||||
(unsigned)&IRQ126_Handler,
|
||||
(unsigned)&IRQ127_Handler,
|
||||
(unsigned)&IRQ128_Handler,
|
||||
(unsigned)&IRQ129_Handler,
|
||||
(unsigned)&IRQ130_Handler,
|
||||
(unsigned)&IRQ131_Handler,
|
||||
(unsigned)&IRQ132_Handler,
|
||||
(unsigned)&IRQ133_Handler,
|
||||
(unsigned)&IRQ134_Handler,
|
||||
(unsigned)&IRQ135_Handler,
|
||||
(unsigned)&IRQ136_Handler,
|
||||
(unsigned)&IRQ137_Handler,
|
||||
(unsigned)&IRQ138_Handler,
|
||||
(unsigned)&IRQ139_Handler,
|
||||
(unsigned)&IRQ140_Handler,
|
||||
(unsigned)&IRQ141_Handler,
|
||||
(unsigned)&IRQ142_Handler,
|
||||
(unsigned)&IRQ143_Handler
|
||||
|
||||
// [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@ extern "C"
|
|||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
#include <arch/irq.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
|
|
|
|||
Loading…
Reference in New Issue