1、add rv32m1_vega board for xiuos;2、repair the float number printf bug
it is OK
|
@ -158,7 +158,6 @@ int statfs(const char *path, struct statfs *buf);
|
|||
|
||||
/* NOTE!!!: when cutting out file system, the 'printf' function can not output angthing */
|
||||
int Userprintf(const char *fmt, ...);
|
||||
#define printf Userprintf
|
||||
|
||||
#endif
|
||||
|
||||
|
@ -242,7 +241,6 @@ uint8_t UserGetTaskPriority(int32_t id);
|
|||
#endif
|
||||
|
||||
#define UserPrintf KPrintf
|
||||
#define printf KPrintf
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
|
|||
.PHONY:COMPILE_APP COMPILE_KERNEL
|
||||
|
||||
|
||||
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103_rvstar cortex-m0-emulator
|
||||
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103_rvstar cortex-m0-emulator rv32m1_vega
|
||||
SRC_DIR:=
|
||||
|
||||
export BOARD ?=kd233
|
||||
|
|
|
@ -24,4 +24,8 @@ ifeq ($(CONFIG_BOARD_GD32VF103RVSTAR),y)
|
|||
SRC_DIR +=gd32vf103_rvstar
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_RV32M1_VEGA),y)
|
||||
SRC_DIR +=rv32m1_vega
|
||||
endif
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := startup_RV32M1_ri5cy.S interrupt_gcc.S system_RV32M1_ri5cy.c interrupt.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef ARCH_INTERRUPT_H__
|
||||
#define ARCH_INTERRUPT_H__
|
||||
|
||||
#include <RV32M1_ri5cy.h>
|
||||
|
||||
#define ARCH_MAX_IRQ_NUM NUMBER_OF_INT_VECTORS
|
||||
#define ARCH_IRQ_NUM_OFFSET 0
|
||||
|
||||
int ArchEnableHwIrq(uint32_t irq_num);
|
||||
int ArchDisableHwIrq(uint32_t irq_num);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @file core_riscv32.h
|
||||
* @brief support interrupt
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-16
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: core_riscv32.h
|
||||
Description: support gap8 interrupt and startup
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#ifndef __CORE_RISCV32_H__
|
||||
#define __CORE_RISCV32_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RISCV32
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
|
||||
#define __BKPT(x) __ASM("ebreak")
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("csrsi mstatus, 8");
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("csrci mstatus, 8");
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
return __builtin_bswap32(value);
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
return __builtin_bswap16(value);
|
||||
}
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_RISCV32_H__ */
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_device_registers.h
|
||||
* @brief support fsl device
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-16
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: fsl_device_registers.h
|
||||
Description: support fsl device
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
#define CPU_RV32M1_ri5cy
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if defined(CPU_RV32M1_cm0plus)
|
||||
|
||||
#define RV32M1_cm0plus_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "RV32M1_cm0plus.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "RV32M1_cm0plus_features.h"
|
||||
|
||||
#elif defined(CPU_RV32M1_cm4)
|
||||
|
||||
#define RV32M1_cm4_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "RV32M1_cm4.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "RV32M1_cm4_features.h"
|
||||
|
||||
#elif defined(CPU_RV32M1_zero_riscy)
|
||||
|
||||
#define RV32M1_zero_riscy_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "RV32M1_zero_riscy.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "RV32M1_zero_riscy_features.h"
|
||||
|
||||
#elif defined(CPU_RV32M1_ri5cy)
|
||||
|
||||
#define RV32M1_ri5cy_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "RV32M1_ri5cy.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "RV32M1_ri5cy_features.h"
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
|
@ -0,0 +1,69 @@
|
|||
/**
|
||||
* @file interrupt.c
|
||||
* @brief support interrupt
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-09-02
|
||||
*/
|
||||
|
||||
|
||||
#include <arch_interrupt.h>
|
||||
#include <xs_base.h>
|
||||
#include <xs_isr.h>
|
||||
#include "fsl_common.h"
|
||||
#include <RV32M1_ri5cy.h>
|
||||
|
||||
int ArchDisableHwIrq(uint32_t irq_num)
|
||||
{
|
||||
DisableIRQ(irq_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ArchEnableHwIrq(uint32_t irq_num)
|
||||
{
|
||||
EnableIRQ(irq_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
x_base DisableLocalInterrupt(void)
|
||||
{
|
||||
__disable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: EnableLocalInterrupt
|
||||
*
|
||||
* Description:
|
||||
* Return the current interrupt state and enable interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void EnableLocalInterrupt(x_base oldstat)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
typedef void (*irq_handler_t)(void);
|
||||
extern const irq_handler_t isrTable[];
|
||||
|
||||
void SystemIrqHandler(uint32_t mcause)
|
||||
{
|
||||
uint32_t intNum;
|
||||
|
||||
if (mcause & 0x80000000) /* For external interrupt. */
|
||||
{
|
||||
intNum = mcause & 0x1FUL;
|
||||
|
||||
/* Clear pending flag in EVENT unit .*/
|
||||
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
|
||||
|
||||
/* Now call the real irq handler for intNum */
|
||||
isrManager.done->incCounter();
|
||||
isrTable[intNum]();
|
||||
isrManager.done->decCounter();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/**
|
||||
* @file interrupt_gcc.S
|
||||
* @brief support vega interrupt
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-16
|
||||
*/
|
||||
|
||||
#include "boot.h"
|
||||
|
||||
.section .text.entry
|
||||
.align 2
|
||||
.global IRQ_Handler
|
||||
IRQ_Handler:
|
||||
|
||||
SAVE_X_REGISTERS
|
||||
|
||||
mv fp, sp
|
||||
|
||||
/* switch to interrupt stack */
|
||||
# la sp, __stack
|
||||
|
||||
/* interrupt handle */
|
||||
|
||||
csrr a0, mcause
|
||||
csrr a1, mepc
|
||||
mv a2, sp
|
||||
call SystemIrqHandler
|
||||
|
||||
/* switch to from thread stack */
|
||||
|
||||
mv sp, fp
|
||||
mv a0, fp
|
||||
call KTaskOsAssignAfterIrq
|
||||
j SwitchKTaskContextExit
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
/* ------------------------------------------------------------------------- */
|
||||
/* @file: startup_RV32M1_ri5cy.s */
|
||||
/* @purpose: RI5CY Core Device Startup File */
|
||||
/* RV32M1_ri5cy */
|
||||
/* @version: 1.0 */
|
||||
/* @date: 2018-10-2 */
|
||||
/* @build: b180926 */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* */
|
||||
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
|
||||
/* Copyright 2016-2018 NXP */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
|
||||
|
||||
// Copyright 2017 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the "License"); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
/*************************************************
|
||||
File name: startup_RV32M1_ri5cy.s
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
.extern Rv32m1VgeaStart
|
||||
#define EXCEPTION_STACK_SIZE 0x58
|
||||
|
||||
.text
|
||||
.section .vectors, "ax"
|
||||
.option norvc;
|
||||
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
|
||||
// reset vector
|
||||
jal x0, Reset_Handler
|
||||
|
||||
// Illegal instrution exception
|
||||
jal x0, IllegalInstruction_Handler
|
||||
|
||||
// ecall handler
|
||||
jal x0, Ecall_Handler
|
||||
|
||||
// LSU error
|
||||
jal x0, LSU_Handler
|
||||
|
||||
.section .startup
|
||||
|
||||
/* Reset Handler */
|
||||
Reset_Handler:
|
||||
|
||||
# Disable global interrupt. */
|
||||
csrci mstatus, 8
|
||||
|
||||
# initialize stack pointer
|
||||
la sp, __StackTop
|
||||
|
||||
# initialize global pointer
|
||||
la gp, __global_pointer
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
jal SystemInit
|
||||
#endif
|
||||
|
||||
# call __libc_init_array
|
||||
|
||||
# Enable global interrupt. */
|
||||
# csrsi mstatus, 8
|
||||
|
||||
jal Rv32m1VgeaStart
|
||||
ebreak
|
||||
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.global _init
|
||||
.global _fini
|
||||
_init:
|
||||
_fini:
|
||||
ret
|
||||
|
||||
// saves all caller-saved registers (except return address)
|
||||
store_regs:
|
||||
sw x3, 0x00(x2) // gp
|
||||
sw x4, 0x04(x2) // tp
|
||||
sw x5, 0x08(x2) // t0
|
||||
sw x6, 0x0c(x2) // t1
|
||||
sw x7, 0x10(x2) // t2
|
||||
sw x10, 0x14(x2) // a0
|
||||
sw x11, 0x18(x2) // a1
|
||||
sw x12, 0x1c(x2) // a2
|
||||
sw x13, 0x20(x2) // a3
|
||||
sw x14, 0x24(x2) // a4
|
||||
sw x15, 0x28(x2) // a5
|
||||
sw x16, 0x2c(x2) // a6
|
||||
sw x17, 0x30(x2) // a7
|
||||
|
||||
csrr a0, 0x7B0
|
||||
csrr a1, 0x7B1
|
||||
csrr a2, 0x7B2
|
||||
sw a0, 0x34(x2) // lpstart[0]
|
||||
sw a1, 0x38(x2) // lpend[0]
|
||||
sw a2, 0x3c(x2) // lpcount[0]
|
||||
csrr a0, 0x7B4
|
||||
csrr a1, 0x7B5
|
||||
csrr a2, 0x7B6
|
||||
sw a0, 0x40(x2) // lpstart[1]
|
||||
sw a1, 0x44(x2) // lpend[1]
|
||||
sw a2, 0x48(x2) // lpcount[1]
|
||||
|
||||
csrr a0, 0x341
|
||||
sw a0, 0x4c(x2) // mepc
|
||||
csrr a1, 0x300
|
||||
sw a1, 0x50(x2) // mstatus
|
||||
jalr x0, x1
|
||||
|
||||
// load back registers from stack
|
||||
end_except:
|
||||
lw a1, 0x50(x2) // mstatus
|
||||
csrrw x0, 0x300, a1
|
||||
lw a0, 0x4c(x2) // mepc
|
||||
csrrw x0, 0x341, a0
|
||||
|
||||
lw a0, 0x40(x2) // lpstart[1]
|
||||
lw a1, 0x44(x2) // lpend[1]
|
||||
lw a2, 0x48(x2) // lpcount[1]
|
||||
csrrw x0, 0x7B4, a0
|
||||
csrrw x0, 0x7B5, a1
|
||||
csrrw x0, 0x7B6, a2
|
||||
lw a0, 0x34(x2) // lpstart[0]
|
||||
lw a1, 0x38(x2) // lpend[0]
|
||||
lw a2, 0x3c(x2) // lpcount[0]
|
||||
csrrw x0, 0x7B0, a0
|
||||
csrrw x0, 0x7B1, a1
|
||||
csrrw x0, 0x7B2, a2
|
||||
|
||||
lw x3, 0x00(x2) // gp
|
||||
lw x4, 0x04(x2) // tp
|
||||
lw x5, 0x08(x2) // t0
|
||||
lw x6, 0x0c(x2) // t1
|
||||
lw x7, 0x10(x2) // t2
|
||||
lw x10, 0x14(x2) // a0
|
||||
lw x11, 0x18(x2) // a1
|
||||
lw x12, 0x1c(x2) // a2
|
||||
lw x13, 0x20(x2) // a3
|
||||
lw x14, 0x24(x2) // a4
|
||||
lw x15, 0x28(x2) // a5
|
||||
lw x16, 0x2c(x2) // a6
|
||||
lw x17, 0x30(x2) // a7
|
||||
|
||||
lw x1, 0x54(x2)
|
||||
addi x2, x2, EXCEPTION_STACK_SIZE
|
||||
mret
|
||||
|
||||
.weak IRQ_Handler
|
||||
.type IRQ_Handler, %function
|
||||
IRQ_Handler:
|
||||
addi x2, x2, -EXCEPTION_STACK_SIZE
|
||||
sw x1, 0x54(x2)
|
||||
jal x1, store_regs
|
||||
la x1, end_except
|
||||
csrr a0, mcause
|
||||
jal x0, SystemIrqHandler
|
||||
.size IRQ_Handler, . - IRQ_Handler
|
||||
|
||||
.macro define_exception_entry entry_name handler_name
|
||||
.weak \entry_name
|
||||
\entry_name:
|
||||
addi x2, x2, -EXCEPTION_STACK_SIZE
|
||||
sw x1, 0x54(x2)
|
||||
jal x1, store_regs
|
||||
la x1, end_except
|
||||
jal x0, \handler_name
|
||||
.endm
|
||||
|
||||
define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
|
||||
define_exception_entry Ecall_Handler Ecall_HandlerFunc
|
||||
define_exception_entry LSU_Handler LSU_HandlerFunc
|
||||
|
||||
.weak IllegalInstruction_HandlerFunc
|
||||
.type IllegalInstruction_HandlerFunc, %function
|
||||
IllegalInstruction_HandlerFunc:
|
||||
j .
|
||||
.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
|
||||
|
||||
.weak Ecall_HandlerFunc
|
||||
.type Ecall_HandlerFunc, %function
|
||||
Ecall_HandlerFunc:
|
||||
j .
|
||||
.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
|
||||
|
||||
.weak LSU_HandlerFunc
|
||||
.type LSU_HandlerFunc, %function
|
||||
LSU_HandlerFunc:
|
||||
j .
|
||||
.size LSU_HandlerFunc, . - LSU_HandlerFunc
|
|
@ -0,0 +1,236 @@
|
|||
/* ------------------------------------------------------------------------- */
|
||||
/* @file: startup_RV32M1_zero_riscy.s */
|
||||
/* @purpose: ZERO_RISCY Core Device Startup File */
|
||||
/* RV32M1_zero_riscy */
|
||||
/* @version: 1.0 */
|
||||
/* @date: 2018-10-2 */
|
||||
/* @build: b180926 */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* */
|
||||
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
|
||||
/* Copyright 2016-2018 NXP */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
|
||||
// Copyright 2017 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the "License"); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
/*************************************************
|
||||
File name: startup_RV32M1_zero_ri5cy.s
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#define EXCEPTION_STACK_SIZE 0x58
|
||||
|
||||
.text
|
||||
.section .vectors, "ax"
|
||||
.option norvc;
|
||||
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
jal x0, IRQ_Handler
|
||||
|
||||
// reset vector
|
||||
jal x0, Reset_Handler
|
||||
|
||||
// Illegal instrution exception
|
||||
jal x0, IllegalInstruction_Handler
|
||||
|
||||
// ecall handler
|
||||
jal x0, Ecall_Handler
|
||||
|
||||
// LSU error
|
||||
jal x0, LSU_Handler
|
||||
|
||||
.section .startup
|
||||
|
||||
/* Reset Handler */
|
||||
Reset_Handler:
|
||||
|
||||
# Disable global interrupt. */
|
||||
csrci mstatus, 8
|
||||
|
||||
# initialize stack pointer
|
||||
la sp, __StackTop
|
||||
|
||||
# initialize global pointer
|
||||
la gp, __global_pointer
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
jal SystemInit
|
||||
#endif
|
||||
|
||||
call __libc_init_array
|
||||
|
||||
# Enable global interrupt. */
|
||||
csrsi mstatus, 8
|
||||
|
||||
jal main
|
||||
ebreak
|
||||
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.global _init
|
||||
.global _fini
|
||||
_init:
|
||||
_fini:
|
||||
ret
|
||||
|
||||
// saves all caller-saved registers (except return address)
|
||||
store_regs:
|
||||
sw x3, 0x00(x2) // gp
|
||||
sw x4, 0x04(x2) // tp
|
||||
sw x5, 0x08(x2) // t0
|
||||
sw x6, 0x0c(x2) // t1
|
||||
sw x7, 0x10(x2) // t2
|
||||
sw x10, 0x14(x2) // a0
|
||||
sw x11, 0x18(x2) // a1
|
||||
sw x12, 0x1c(x2) // a2
|
||||
sw x13, 0x20(x2) // a3
|
||||
sw x14, 0x24(x2) // a4
|
||||
sw x15, 0x28(x2) // a5
|
||||
sw x16, 0x2c(x2) // a6
|
||||
sw x17, 0x30(x2) // a7
|
||||
|
||||
csrr a0, 0x7B0
|
||||
csrr a1, 0x7B1
|
||||
csrr a2, 0x7B2
|
||||
sw a0, 0x34(x2) // lpstart[0]
|
||||
sw a1, 0x38(x2) // lpend[0]
|
||||
sw a2, 0x3c(x2) // lpcount[0]
|
||||
csrr a0, 0x7B4
|
||||
csrr a1, 0x7B5
|
||||
csrr a2, 0x7B6
|
||||
sw a0, 0x40(x2) // lpstart[1]
|
||||
sw a1, 0x44(x2) // lpend[1]
|
||||
sw a2, 0x48(x2) // lpcount[1]
|
||||
|
||||
csrr a0, 0x341
|
||||
sw a0, 0x4c(x2) // mepc
|
||||
csrr a1, 0x300
|
||||
sw a1, 0x50(x2) // mstatus
|
||||
jalr x0, x1
|
||||
|
||||
// load back registers from stack
|
||||
end_except:
|
||||
lw a1, 0x50(x2) // mstatus
|
||||
csrrw x0, 0x300, a1
|
||||
lw a0, 0x4c(x2) // mepc
|
||||
csrrw x0, 0x341, a0
|
||||
|
||||
lw a0, 0x40(x2) // lpstart[1]
|
||||
lw a1, 0x44(x2) // lpend[1]
|
||||
lw a2, 0x48(x2) // lpcount[1]
|
||||
csrrw x0, 0x7B4, a0
|
||||
csrrw x0, 0x7B5, a1
|
||||
csrrw x0, 0x7B6, a2
|
||||
lw a0, 0x34(x2) // lpstart[0]
|
||||
lw a1, 0x38(x2) // lpend[0]
|
||||
lw a2, 0x3c(x2) // lpcount[0]
|
||||
csrrw x0, 0x7B0, a0
|
||||
csrrw x0, 0x7B1, a1
|
||||
csrrw x0, 0x7B2, a2
|
||||
|
||||
lw x3, 0x00(x2) // gp
|
||||
lw x4, 0x04(x2) // tp
|
||||
lw x5, 0x08(x2) // t0
|
||||
lw x6, 0x0c(x2) // t1
|
||||
lw x7, 0x10(x2) // t2
|
||||
lw x10, 0x14(x2) // a0
|
||||
lw x11, 0x18(x2) // a1
|
||||
lw x12, 0x1c(x2) // a2
|
||||
lw x13, 0x20(x2) // a3
|
||||
lw x14, 0x24(x2) // a4
|
||||
lw x15, 0x28(x2) // a5
|
||||
lw x16, 0x2c(x2) // a6
|
||||
lw x17, 0x30(x2) // a7
|
||||
|
||||
lw x1, 0x54(x2)
|
||||
addi x2, x2, EXCEPTION_STACK_SIZE
|
||||
mret
|
||||
|
||||
.weak IRQ_Handler
|
||||
.type IRQ_Handler, %function
|
||||
IRQ_Handler:
|
||||
addi x2, x2, -EXCEPTION_STACK_SIZE
|
||||
sw x1, 0x54(x2)
|
||||
jal x1, store_regs
|
||||
la x1, end_except
|
||||
csrr a0, mcause
|
||||
jal x0, SystemIrqHandler
|
||||
.size IRQ_Handler, . - IRQ_Handler
|
||||
|
||||
.macro define_exception_entry entry_name handler_name
|
||||
.weak \entry_name
|
||||
\entry_name:
|
||||
addi x2, x2, -EXCEPTION_STACK_SIZE
|
||||
sw x1, 0x54(x2)
|
||||
jal x1, store_regs
|
||||
la x1, end_except
|
||||
jal x0, \handler_name
|
||||
.endm
|
||||
|
||||
define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
|
||||
define_exception_entry Ecall_Handler Ecall_HandlerFunc
|
||||
define_exception_entry LSU_Handler LSU_HandlerFunc
|
||||
|
||||
.weak IllegalInstruction_HandlerFunc
|
||||
.type IllegalInstruction_HandlerFunc, %function
|
||||
IllegalInstruction_HandlerFunc:
|
||||
j .
|
||||
.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
|
||||
|
||||
.weak Ecall_HandlerFunc
|
||||
.type Ecall_HandlerFunc, %function
|
||||
Ecall_HandlerFunc:
|
||||
j .
|
||||
.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
|
||||
|
||||
.weak LSU_HandlerFunc
|
||||
.type LSU_HandlerFunc, %function
|
||||
LSU_HandlerFunc:
|
||||
j .
|
||||
.size LSU_HandlerFunc, . - LSU_HandlerFunc
|
|
@ -0,0 +1,567 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: RV32M1_ri5cy
|
||||
** RV32M1_ri5cy
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
|
||||
** Version: rev. 1.0, 2018-10-02
|
||||
** Build: b180926
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2018-10-02)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file RV32M1_ri5cy
|
||||
* @version 1.0
|
||||
* @date 2018-10-02
|
||||
* @brief Device specific configuration file for RV32M1_ri5cy
|
||||
* (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: RV32M1_ri5cy
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_common.h"
|
||||
|
||||
typedef void (*irq_handler_t)(void);
|
||||
|
||||
extern void DMA0_0_4_8_12_DriverIRQHandler(void);
|
||||
extern void DMA0_1_5_9_13_DriverIRQHandler(void);
|
||||
extern void DMA0_2_6_10_14_DriverIRQHandler(void);
|
||||
extern void DMA0_3_7_11_15_DriverIRQHandler(void);
|
||||
extern void DMA0_Error_IRQHandler(void);
|
||||
extern void CMC0_IRQHandler(void);
|
||||
extern void EWM_IRQHandler(void);
|
||||
extern void FTFE_Command_Complete_IRQHandler(void);
|
||||
extern void FTFE_Read_Collision_IRQHandler(void);
|
||||
extern void LLWU0_IRQHandler(void);
|
||||
extern void MUA_IRQHandler(void);
|
||||
extern void SPM_IRQHandler(void);
|
||||
extern void WDOG0_IRQHandler(void);
|
||||
extern void SCG_IRQHandler(void);
|
||||
extern void LPIT0_IRQHandler(void);
|
||||
extern void RTC_IRQHandler(void);
|
||||
extern void LPTMR0_IRQHandler(void);
|
||||
extern void LPTMR1_IRQHandler(void);
|
||||
extern void TPM0_IRQHandler(void);
|
||||
extern void TPM1_IRQHandler(void);
|
||||
extern void TPM2_IRQHandler(void);
|
||||
extern void EMVSIM0_IRQHandler(void);
|
||||
extern void FLEXIO0_DriverIRQHandler(void);
|
||||
extern void LPI2C0_DriverIRQHandler(void);
|
||||
extern void LPI2C1_DriverIRQHandler(void);
|
||||
extern void LPI2C2_DriverIRQHandler(void);
|
||||
extern void I2S0_DriverIRQHandler(void);
|
||||
extern void USDHC0_DriverIRQHandler(void);
|
||||
extern void LPSPI0_DriverIRQHandler(void);
|
||||
extern void LPSPI1_DriverIRQHandler(void);
|
||||
extern void LPSPI2_DriverIRQHandler(void);
|
||||
extern void LPUART0_DriverIRQHandler(void);
|
||||
extern void LPUART1_DriverIRQHandler(void);
|
||||
extern void LPUART2_DriverIRQHandler(void);
|
||||
extern void USB0_IRQHandler(void);
|
||||
extern void PORTA_IRQHandler(void);
|
||||
extern void PORTB_IRQHandler(void);
|
||||
extern void PORTC_IRQHandler(void);
|
||||
extern void PORTD_IRQHandler(void);
|
||||
extern void ADC0_IRQHandler(void);
|
||||
extern void LPCMP0_IRQHandler(void);
|
||||
extern void LPDAC0_IRQHandler(void);
|
||||
extern void CAU3_Task_Complete_IRQHandler(void);
|
||||
extern void CAU3_Security_Violation_IRQHandler(void);
|
||||
extern void TRNG_IRQHandler(void);
|
||||
extern void LPIT1_IRQHandler(void);
|
||||
extern void LPTMR2_IRQHandler(void);
|
||||
extern void TPM3_IRQHandler(void);
|
||||
extern void LPI2C3_DriverIRQHandler(void);
|
||||
extern void LPSPI3_DriverIRQHandler(void);
|
||||
extern void LPUART3_DriverIRQHandler(void);
|
||||
extern void PORTE_IRQHandler(void);
|
||||
extern void LPCMP1_IRQHandler(void);
|
||||
extern void RF0_0_IRQHandler(void);
|
||||
extern void RF0_1_IRQHandler(void);
|
||||
extern void INTMUX0_0_DriverIRQHandler(void);
|
||||
extern void INTMUX0_1_DriverIRQHandler(void);
|
||||
extern void INTMUX0_2_DriverIRQHandler(void);
|
||||
extern void INTMUX0_3_DriverIRQHandler(void);
|
||||
extern void INTMUX0_4_DriverIRQHandler(void);
|
||||
extern void INTMUX0_5_DriverIRQHandler(void);
|
||||
extern void INTMUX0_6_DriverIRQHandler(void);
|
||||
extern void INTMUX0_7_DriverIRQHandler(void);
|
||||
extern void INTMUX0_8_DriverIRQHandler(void);
|
||||
extern void DMA0_0_4_8_12_IRQHandler(void);
|
||||
extern void DMA0_1_5_9_13_IRQHandler(void);
|
||||
extern void DMA0_2_6_10_14_IRQHandler(void);
|
||||
extern void DMA0_3_7_11_15_IRQHandler(void);
|
||||
extern void FLEXIO0_IRQHandler(void);
|
||||
extern void LPI2C0_IRQHandler(void);
|
||||
extern void LPI2C1_IRQHandler(void);
|
||||
extern void LPI2C2_IRQHandler(void);
|
||||
extern void I2S0_IRQHandler(void);
|
||||
extern void USDHC0_IRQHandler(void);
|
||||
extern void LPSPI0_IRQHandler(void);
|
||||
extern void LPSPI1_IRQHandler(void);
|
||||
extern void LPSPI2_IRQHandler(void);
|
||||
extern void LPUART0_IRQHandler(void);
|
||||
extern void LPUART1_IRQHandler(void);
|
||||
extern void LPUART2_IRQHandler(void);
|
||||
extern void LPI2C3_IRQHandler(void);
|
||||
extern void LPSPI3_IRQHandler(void);
|
||||
extern void LPUART3_IRQHandler(void);
|
||||
extern void INTMUX0_0_IRQHandler(void);
|
||||
extern void INTMUX0_1_IRQHandler(void);
|
||||
extern void INTMUX0_2_IRQHandler(void);
|
||||
extern void INTMUX0_3_IRQHandler(void);
|
||||
extern void INTMUX0_4_IRQHandler(void);
|
||||
extern void INTMUX0_5_IRQHandler(void);
|
||||
extern void INTMUX0_6_IRQHandler(void);
|
||||
extern void INTMUX0_7_IRQHandler(void);
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
extern uint32_t __etext;
|
||||
extern uint32_t __data_start__;
|
||||
extern uint32_t __data_end__;
|
||||
|
||||
extern uint32_t __bss_start__;
|
||||
extern uint32_t __bss_end__;
|
||||
|
||||
static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
|
||||
{
|
||||
while(p_vma <= p_vma_end)
|
||||
{
|
||||
*p_vma = *p_load;
|
||||
++p_load;
|
||||
++p_vma;
|
||||
}
|
||||
}
|
||||
|
||||
static void zero_section(uint32_t * start, uint32_t * end)
|
||||
{
|
||||
uint32_t * p_zero = start;
|
||||
|
||||
while(p_zero <= end)
|
||||
{
|
||||
*p_zero = 0;
|
||||
++p_zero;
|
||||
}
|
||||
}
|
||||
|
||||
#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
|
||||
void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
|
||||
|
||||
#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
|
||||
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_0_4_8_12_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_1_5_9_13_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_2_6_10_14_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_3_7_11_15_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_Error_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CMC0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LLWU0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(MUA_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(WDOG0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_4_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_5_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_6_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_7_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_8_DriverIRQHandler);
|
||||
|
||||
DEFINE_IRQ_HANDLER(DMA0_0_4_8_12_IRQHandler, DMA0_0_4_8_12_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA0_1_5_9_13_IRQHandler, DMA0_1_5_9_13_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA0_2_6_10_14_IRQHandler, DMA0_2_6_10_14_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA0_3_7_11_15_IRQHandler, DMA0_3_7_11_15_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_0_IRQHandler, INTMUX0_0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_1_IRQHandler, INTMUX0_1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_2_IRQHandler, INTMUX0_2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_3_IRQHandler, INTMUX0_3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_4_IRQHandler, INTMUX0_4_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_5_IRQHandler, INTMUX0_5_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_6_IRQHandler, INTMUX0_6_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX0_7_IRQHandler, INTMUX0_7_DriverIRQHandler);
|
||||
|
||||
__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
|
||||
{
|
||||
DMA0_0_4_8_12_IRQHandler,
|
||||
DMA0_1_5_9_13_IRQHandler,
|
||||
DMA0_2_6_10_14_IRQHandler,
|
||||
DMA0_3_7_11_15_IRQHandler,
|
||||
DMA0_Error_IRQHandler,
|
||||
CMC0_IRQHandler,
|
||||
MUA_IRQHandler,
|
||||
USB0_IRQHandler,
|
||||
USDHC0_IRQHandler,
|
||||
I2S0_IRQHandler,
|
||||
FLEXIO0_IRQHandler,
|
||||
EMVSIM0_IRQHandler,
|
||||
LPIT0_IRQHandler,
|
||||
LPSPI0_IRQHandler,
|
||||
LPSPI1_IRQHandler,
|
||||
LPI2C0_IRQHandler,
|
||||
LPI2C1_IRQHandler,
|
||||
LPUART0_IRQHandler,
|
||||
PORTA_IRQHandler,
|
||||
TPM0_IRQHandler,
|
||||
LPDAC0_IRQHandler,
|
||||
ADC0_IRQHandler,
|
||||
LPCMP0_IRQHandler,
|
||||
RTC_IRQHandler,
|
||||
INTMUX0_0_IRQHandler,
|
||||
INTMUX0_1_IRQHandler,
|
||||
INTMUX0_2_IRQHandler,
|
||||
INTMUX0_3_IRQHandler,
|
||||
INTMUX0_4_IRQHandler,
|
||||
INTMUX0_5_IRQHandler,
|
||||
INTMUX0_6_IRQHandler,
|
||||
INTMUX0_7_IRQHandler,
|
||||
EWM_IRQHandler,
|
||||
FTFE_Command_Complete_IRQHandler,
|
||||
FTFE_Read_Collision_IRQHandler,
|
||||
LLWU0_IRQHandler,
|
||||
SPM_IRQHandler,
|
||||
WDOG0_IRQHandler,
|
||||
SCG_IRQHandler,
|
||||
LPTMR0_IRQHandler,
|
||||
LPTMR1_IRQHandler,
|
||||
TPM1_IRQHandler,
|
||||
TPM2_IRQHandler,
|
||||
LPI2C2_IRQHandler,
|
||||
LPSPI2_IRQHandler,
|
||||
LPUART1_IRQHandler,
|
||||
LPUART2_IRQHandler,
|
||||
PORTB_IRQHandler,
|
||||
PORTC_IRQHandler,
|
||||
PORTD_IRQHandler,
|
||||
CAU3_Task_Complete_IRQHandler,
|
||||
CAU3_Security_Violation_IRQHandler,
|
||||
TRNG_IRQHandler,
|
||||
LPIT1_IRQHandler,
|
||||
LPTMR2_IRQHandler,
|
||||
TPM3_IRQHandler,
|
||||
LPI2C3_IRQHandler,
|
||||
LPSPI3_IRQHandler,
|
||||
LPUART3_IRQHandler,
|
||||
PORTE_IRQHandler,
|
||||
LPCMP1_IRQHandler,
|
||||
RF0_0_IRQHandler,
|
||||
RF0_1_IRQHandler,
|
||||
};
|
||||
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
|
||||
static uint32_t irqNesting = 0;
|
||||
|
||||
static void DefaultIRQHandler(void)
|
||||
{
|
||||
for (;;)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if (DISABLE_WDOG)
|
||||
WDOG0->CNT = 0xD928C520U;
|
||||
WDOG0->TOVAL = 0xFFFF;
|
||||
WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
SystemInitHook();
|
||||
|
||||
copy_section(&__etext, &__data_start__, &__data_end__);
|
||||
zero_section(&__bss_start__, &__bss_end__);
|
||||
|
||||
/* Setup the vector table address. */
|
||||
irqNesting = 0;
|
||||
|
||||
__ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
|
||||
__ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
|
||||
|
||||
/* Clear all pending flags. */
|
||||
EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
|
||||
EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
|
||||
/* Set all interrupt as secure interrupt. */
|
||||
EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
|
||||
uint16_t Divider;
|
||||
Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
|
||||
|
||||
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
|
||||
case 0x1:
|
||||
/* System OSC */
|
||||
SCGOUTClock = CPU_XTAL_CLK_HZ;
|
||||
break;
|
||||
case 0x2:
|
||||
/* Slow IRC */
|
||||
SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
|
||||
break;
|
||||
case 0x3:
|
||||
/* Fast IRC */
|
||||
SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
|
||||
break;
|
||||
case 0x5:
|
||||
/* Low Power FLL */
|
||||
SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
SystemCoreClock = (SCGOUTClock / Divider);
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInitHook()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||
/* Void implementation of the weak function. */
|
||||
}
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__)
|
||||
#pragma weak SystemIrqHandler
|
||||
void SystemIrqHandler(uint32_t mcause) {
|
||||
#elif defined(__GNUC__)
|
||||
__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
|
||||
#else
|
||||
#error Not supported compiler type
|
||||
#endif
|
||||
uint32_t intNum;
|
||||
|
||||
if (mcause & 0x80000000) /* For external interrupt. */
|
||||
{
|
||||
intNum = mcause & 0x1FUL;
|
||||
|
||||
irqNesting++;
|
||||
|
||||
/* Clear pending flag in EVENT unit .*/
|
||||
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
|
||||
|
||||
/* Read back to make sure write finished. */
|
||||
(void)(EVENT_UNIT->INTPTPENDCLEAR);
|
||||
|
||||
__enable_irq(); /* Support nesting interrupt */
|
||||
|
||||
/* Now call the real irq handler for intNum */
|
||||
isrTable[intNum]();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
irqNesting--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Use LIPT0 channel 0 for systick. */
|
||||
#define SYSTICK_LPIT LPIT0
|
||||
#define SYSTICK_LPIT_CH 0
|
||||
#define SYSTICK_LPIT_IRQn LPIT0_IRQn
|
||||
|
||||
/* Leverage LPIT0 to provide Systick */
|
||||
void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
|
||||
{
|
||||
/* Init pit module */
|
||||
CLOCK_EnableClock(kCLOCK_Lpit0);
|
||||
|
||||
/* Reset the timer channels and registers except the MCR register */
|
||||
SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
|
||||
SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
|
||||
|
||||
/* Setup timer operation in debug and doze modes and enable the module */
|
||||
SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
|
||||
|
||||
/* Set timer period for channel 0 */
|
||||
SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
|
||||
|
||||
/* Enable timer interrupts for channel 0 */
|
||||
SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
|
||||
|
||||
/* Set interrupt priority. */
|
||||
EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
|
||||
|
||||
/* Enable interrupt at the EVENT unit */
|
||||
EnableIRQ(SYSTICK_LPIT_IRQn);
|
||||
|
||||
/* Start channel 0 */
|
||||
SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
|
||||
}
|
||||
|
||||
uint32_t SystemGetIRQNestingLevel(void)
|
||||
{
|
||||
return irqNesting;
|
||||
}
|
||||
|
||||
void SystemClearSystickFlag(void)
|
||||
{
|
||||
/* Channel 0. */
|
||||
SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
|
||||
}
|
||||
|
||||
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
|
||||
{
|
||||
uint8_t regIdx;
|
||||
uint8_t regOffset;
|
||||
|
||||
if ((IRQn < 32) && (intPriority < 8))
|
||||
{
|
||||
/*
|
||||
* 4 priority control registers, each register controls 8 interrupts.
|
||||
* Bit 0-2: interrupt 0
|
||||
* Bit 4-7: interrupt 1
|
||||
* ...
|
||||
* Bit 28-30: interrupt 7
|
||||
*/
|
||||
regIdx = IRQn >> 3U;
|
||||
regOffset = (IRQn & 0x07U) * 4U;
|
||||
|
||||
EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn)
|
||||
{
|
||||
uint8_t regIdx;
|
||||
uint8_t regOffset;
|
||||
int32_t intPriority;
|
||||
|
||||
if ((IRQn < 32))
|
||||
{
|
||||
/*
|
||||
* 4 priority control registers, each register controls 8 interrupts.
|
||||
* Bit 0-2: interrupt 0
|
||||
* Bit 4-7: interrupt 1
|
||||
* ...
|
||||
* Bit 28-30: interrupt 7
|
||||
*/
|
||||
regIdx = IRQn >> 3U;
|
||||
regOffset = (IRQn & 0x07U) << 2U;
|
||||
|
||||
intPriority = (EVENT_UNIT->INTPTPRI[regIdx] >> regOffset) & 0xF;
|
||||
return (uint8_t)intPriority;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool SystemInISR(void)
|
||||
{
|
||||
return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
|
||||
}
|
||||
|
||||
void EVENT_SystemReset(void)
|
||||
{
|
||||
EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
|
||||
}
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: RV32M1_ri5cy
|
||||
** RV32M1_ri5cy
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
|
||||
** Version: rev. 1.0, 2018-10-02
|
||||
** Build: b180926
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2018-10-02)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file RV32M1_ri5cy
|
||||
* @version 1.0
|
||||
* @date 2018-10-02
|
||||
* @brief Device specific configuration file for RV32M1_ri5cy (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
/*************************************************
|
||||
File name: RV32M1_ri5cy
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#ifndef _SYSTEM_RV32M1_ri5cy_H_
|
||||
#define _SYSTEM_RV32M1_ri5cy_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* Define clock source values */
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
* @brief SystemInit function hook.
|
||||
*
|
||||
* This weak function allows to call specific initialization code during the
|
||||
* SystemInit() execution.This can be used when an application specific code needs
|
||||
* to be called as close to the reset entry as possible (for example the Multicore
|
||||
* Manager MCMGR_EarlyInit() function call).
|
||||
* NOTE: No global r/w variables can be used in this hook function because the
|
||||
* initialization of these variables happens after this function.
|
||||
*/
|
||||
void SystemInitHook (void);
|
||||
|
||||
/**
|
||||
* @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
|
||||
*
|
||||
* It is called from IRQ exception context and dispatches to registered handler according to
|
||||
* MCAUSE interrupt number.
|
||||
*
|
||||
* @param mcause IRQ acknowledge value read from MCAUSE
|
||||
*/
|
||||
void SystemIrqHandler(uint32_t mcause);
|
||||
|
||||
/**
|
||||
* @brief Get IRQ nesting level of current context.
|
||||
*
|
||||
* If the return value is 0, then the context is not ISR, otherwise the context is ISR.
|
||||
*
|
||||
* @return IRQ nesting level
|
||||
*/
|
||||
uint32_t SystemGetIRQNestingLevel (void);
|
||||
|
||||
/**
|
||||
* @brief Setup systick for RTOS system.
|
||||
*
|
||||
* @param tickRateHz Tick number per second
|
||||
* @param intPriority IRQ interrupt priority (the smaller, the higher priority)
|
||||
*/
|
||||
void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
|
||||
|
||||
/**
|
||||
* @brief Clear systick flag status so that next tick interrupt may occur.
|
||||
*/
|
||||
void SystemClearSystickFlag (void);
|
||||
|
||||
/**
|
||||
* @brief Sysem is in ISR or not.
|
||||
*/
|
||||
bool SystemInISR(void);
|
||||
|
||||
#define SysTick_Handler LPIT0_IRQHandler
|
||||
|
||||
/**
|
||||
* @brief Set interrupt priority in Event unit.
|
||||
*/
|
||||
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
|
||||
|
||||
/**
|
||||
* @brief Get interrupt priority in Event unit.
|
||||
*/
|
||||
uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
* @brief Reset the system.
|
||||
*/
|
||||
void EVENT_SystemReset(void);
|
||||
|
||||
#define NVIC_SystemReset EVENT_SystemReset
|
||||
|
||||
/* Priority setting macro remap. */
|
||||
#define NVIC_SetPriority EVENT_SetIRQPriority
|
||||
|
||||
/* Priority getting macro remap. */
|
||||
#define NVIC_GetPriority EVENT_GetIRQPriority
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_RV32M1_ri5cy_H_ */
|
|
@ -0,0 +1,546 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: RV32M1_zero_riscy
|
||||
** RV32M1_zero_riscy
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
|
||||
** Version: rev. 1.0, 2018-10-02
|
||||
** Build: b180926
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2018-10-02)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file RV32M1_zero_riscy
|
||||
* @version 1.0
|
||||
* @date 2018-10-02
|
||||
* @brief Device specific configuration file for RV32M1_zero_riscy
|
||||
* (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: RV32M1_zero_riscy
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_common.h"
|
||||
|
||||
typedef void (*irq_handler_t)(void);
|
||||
|
||||
extern void CTI1_IRQHandler(void);
|
||||
extern void DMA1_04_DriverIRQHandler(void);
|
||||
extern void DMA1_15_DriverIRQHandler(void);
|
||||
extern void DMA1_26_DriverIRQHandler(void);
|
||||
extern void DMA1_37_DriverIRQHandler(void);
|
||||
extern void DMA1_Error_DriverIRQHandler(void);
|
||||
extern void CMC1_IRQHandler(void);
|
||||
extern void LLWU1_IRQHandler(void);
|
||||
extern void MUB_IRQHandler(void);
|
||||
extern void WDOG1_IRQHandler(void);
|
||||
extern void CAU3_Task_Complete_IRQHandler(void);
|
||||
extern void CAU3_Security_Violation_IRQHandler(void);
|
||||
extern void TRNG_IRQHandler(void);
|
||||
extern void LPIT1_IRQHandler(void);
|
||||
extern void LPTMR2_IRQHandler(void);
|
||||
extern void TPM3_IRQHandler(void);
|
||||
extern void LPI2C3_DriverIRQHandler(void);
|
||||
extern void RF0_0_IRQHandler(void);
|
||||
extern void RF0_1_IRQHandler(void);
|
||||
extern void LPSPI3_DriverIRQHandler(void);
|
||||
extern void LPUART3_DriverIRQHandler(void);
|
||||
extern void PORTE_IRQHandler(void);
|
||||
extern void LPCMP1_IRQHandler(void);
|
||||
extern void RTC_IRQHandler(void);
|
||||
extern void INTMUX1_0_DriverIRQHandler(void);
|
||||
extern void INTMUX1_1_DriverIRQHandler(void);
|
||||
extern void INTMUX1_2_DriverIRQHandler(void);
|
||||
extern void INTMUX1_3_DriverIRQHandler(void);
|
||||
extern void INTMUX1_4_DriverIRQHandler(void);
|
||||
extern void INTMUX1_5_DriverIRQHandler(void);
|
||||
extern void INTMUX1_6_DriverIRQHandler(void);
|
||||
extern void INTMUX1_7_DriverIRQHandler(void);
|
||||
extern void EWM_IRQHandler(void);
|
||||
extern void FTFE_Command_Complete_IRQHandler(void);
|
||||
extern void FTFE_Read_Collision_IRQHandler(void);
|
||||
extern void SPM_IRQHandler(void);
|
||||
extern void SCG_IRQHandler(void);
|
||||
extern void LPIT0_IRQHandler(void);
|
||||
extern void LPTMR0_IRQHandler(void);
|
||||
extern void LPTMR1_IRQHandler(void);
|
||||
extern void TPM0_IRQHandler(void);
|
||||
extern void TPM1_IRQHandler(void);
|
||||
extern void TPM2_IRQHandler(void);
|
||||
extern void EMVSIM0_IRQHandler(void);
|
||||
extern void FLEXIO0_DriverIRQHandler(void);
|
||||
extern void LPI2C0_DriverIRQHandler(void);
|
||||
extern void LPI2C1_DriverIRQHandler(void);
|
||||
extern void LPI2C2_DriverIRQHandler(void);
|
||||
extern void I2S0_DriverIRQHandler(void);
|
||||
extern void USDHC0_DriverIRQHandler(void);
|
||||
extern void LPSPI0_DriverIRQHandler(void);
|
||||
extern void LPSPI1_DriverIRQHandler(void);
|
||||
extern void LPSPI2_DriverIRQHandler(void);
|
||||
extern void LPUART0_DriverIRQHandler(void);
|
||||
extern void LPUART1_DriverIRQHandler(void);
|
||||
extern void LPUART2_DriverIRQHandler(void);
|
||||
extern void USB0_IRQHandler(void);
|
||||
extern void PORTA_IRQHandler(void);
|
||||
extern void PORTB_IRQHandler(void);
|
||||
extern void PORTC_IRQHandler(void);
|
||||
extern void PORTD_IRQHandler(void);
|
||||
extern void ADC0_IRQHandler(void);
|
||||
extern void LPCMP0_IRQHandler(void);
|
||||
extern void LPDAC0_IRQHandler(void);
|
||||
extern void DMA1_15_IRQHandler(void);
|
||||
extern void DMA1_26_IRQHandler(void);
|
||||
extern void DMA1_37_IRQHandler(void);
|
||||
extern void DMA1_Error_IRQHandler(void);
|
||||
extern void LPI2C3_IRQHandler(void);
|
||||
extern void LPSPI3_IRQHandler(void);
|
||||
extern void LPUART3_IRQHandler(void);
|
||||
extern void INTMUX1_0_IRQHandler(void);
|
||||
extern void INTMUX1_1_IRQHandler(void);
|
||||
extern void INTMUX1_2_IRQHandler(void);
|
||||
extern void INTMUX1_3_IRQHandler(void);
|
||||
extern void INTMUX1_4_IRQHandler(void);
|
||||
extern void INTMUX1_5_IRQHandler(void);
|
||||
extern void INTMUX1_6_IRQHandler(void);
|
||||
extern void INTMUX1_7_IRQHandler(void);
|
||||
extern void FLEXIO0_IRQHandler(void);
|
||||
extern void LPI2C0_IRQHandler(void);
|
||||
extern void LPI2C1_IRQHandler(void);
|
||||
extern void LPI2C2_IRQHandler(void);
|
||||
extern void I2S0_IRQHandler(void);
|
||||
extern void USDHC0_IRQHandler(void);
|
||||
extern void LPSPI0_IRQHandler(void);
|
||||
extern void LPSPI1_IRQHandler(void);
|
||||
extern void LPSPI2_IRQHandler(void);
|
||||
extern void LPUART0_IRQHandler(void);
|
||||
extern void LPUART1_IRQHandler(void);
|
||||
extern void LPUART2_IRQHandler(void);
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
extern uint32_t __etext;
|
||||
extern uint32_t __data_start__;
|
||||
extern uint32_t __data_end__;
|
||||
|
||||
extern uint32_t __bss_start__;
|
||||
extern uint32_t __bss_end__;
|
||||
|
||||
static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
|
||||
{
|
||||
while(p_vma <= p_vma_end)
|
||||
{
|
||||
*p_vma = *p_load;
|
||||
++p_load;
|
||||
++p_vma;
|
||||
}
|
||||
}
|
||||
|
||||
static void zero_section(uint32_t * start, uint32_t * end)
|
||||
{
|
||||
uint32_t * p_zero = start;
|
||||
|
||||
while(p_zero <= end)
|
||||
{
|
||||
*p_zero = 0;
|
||||
++p_zero;
|
||||
}
|
||||
}
|
||||
|
||||
#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
|
||||
void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
|
||||
|
||||
#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
|
||||
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CTI1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_04_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_15_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_26_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_37_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_Error_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CMC1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LLWU1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(MUB_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(WDOG1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_3_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_4_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_5_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_6_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_7_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
|
||||
DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
|
||||
|
||||
DEFINE_IRQ_HANDLER(DMA1_04_IRQHandler, DMA1_04_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA1_15_IRQHandler, DMA1_15_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA1_26_IRQHandler, DMA1_26_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA1_37_IRQHandler, DMA1_37_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(DMA1_Error_IRQHandler, DMA1_Error_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_0_IRQHandler, INTMUX1_0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_1_IRQHandler, INTMUX1_1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_2_IRQHandler, INTMUX1_2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_3_IRQHandler, INTMUX1_3_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_4_IRQHandler, INTMUX1_4_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_5_IRQHandler, INTMUX1_5_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_6_IRQHandler, INTMUX1_6_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(INTMUX1_7_IRQHandler, INTMUX1_7_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
|
||||
DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
|
||||
|
||||
__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
|
||||
{
|
||||
CTI1_IRQHandler,
|
||||
DMA1_04_IRQHandler,
|
||||
DMA1_15_IRQHandler,
|
||||
DMA1_26_IRQHandler,
|
||||
DMA1_37_IRQHandler,
|
||||
DMA1_Error_IRQHandler,
|
||||
CMC1_IRQHandler,
|
||||
LLWU1_IRQHandler,
|
||||
MUB_IRQHandler,
|
||||
WDOG1_IRQHandler,
|
||||
CAU3_Task_Complete_IRQHandler,
|
||||
CAU3_Security_Violation_IRQHandler,
|
||||
TRNG_IRQHandler,
|
||||
LPIT1_IRQHandler,
|
||||
LPTMR2_IRQHandler,
|
||||
TPM3_IRQHandler,
|
||||
LPI2C3_IRQHandler,
|
||||
RF0_0_IRQHandler,
|
||||
RF0_1_IRQHandler,
|
||||
LPSPI3_IRQHandler,
|
||||
LPUART3_IRQHandler,
|
||||
PORTE_IRQHandler,
|
||||
LPCMP1_IRQHandler,
|
||||
RTC_IRQHandler,
|
||||
INTMUX1_0_IRQHandler,
|
||||
INTMUX1_1_IRQHandler,
|
||||
INTMUX1_2_IRQHandler,
|
||||
INTMUX1_3_IRQHandler,
|
||||
INTMUX1_4_IRQHandler,
|
||||
INTMUX1_5_IRQHandler,
|
||||
INTMUX1_6_IRQHandler,
|
||||
INTMUX1_7_IRQHandler,
|
||||
EWM_IRQHandler,
|
||||
FTFE_Command_Complete_IRQHandler,
|
||||
FTFE_Read_Collision_IRQHandler,
|
||||
SPM_IRQHandler,
|
||||
SCG_IRQHandler,
|
||||
LPIT0_IRQHandler,
|
||||
LPTMR0_IRQHandler,
|
||||
LPTMR1_IRQHandler,
|
||||
TPM0_IRQHandler,
|
||||
TPM1_IRQHandler,
|
||||
TPM2_IRQHandler,
|
||||
EMVSIM0_IRQHandler,
|
||||
FLEXIO0_IRQHandler,
|
||||
LPI2C0_IRQHandler,
|
||||
LPI2C1_IRQHandler,
|
||||
LPI2C2_IRQHandler,
|
||||
I2S0_IRQHandler,
|
||||
USDHC0_IRQHandler,
|
||||
LPSPI0_IRQHandler,
|
||||
LPSPI1_IRQHandler,
|
||||
LPSPI2_IRQHandler,
|
||||
LPUART0_IRQHandler,
|
||||
LPUART1_IRQHandler,
|
||||
LPUART2_IRQHandler,
|
||||
USB0_IRQHandler,
|
||||
PORTA_IRQHandler,
|
||||
PORTB_IRQHandler,
|
||||
PORTC_IRQHandler,
|
||||
PORTD_IRQHandler,
|
||||
ADC0_IRQHandler,
|
||||
LPCMP0_IRQHandler,
|
||||
LPDAC0_IRQHandler,
|
||||
};
|
||||
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
|
||||
static uint32_t irqNesting = 0;
|
||||
|
||||
static void DefaultIRQHandler(void)
|
||||
{
|
||||
for (;;)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if (DISABLE_WDOG)
|
||||
WDOG1->CNT = 0xD928C520U;
|
||||
WDOG1->TOVAL = 0xFFFF;
|
||||
WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
SystemInitHook();
|
||||
|
||||
copy_section(&__etext, &__data_start__, &__data_end__);
|
||||
zero_section(&__bss_start__, &__bss_end__);
|
||||
|
||||
/* Setup the vector table address. */
|
||||
irqNesting = 0;
|
||||
|
||||
__ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
|
||||
__ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
|
||||
|
||||
/* Clear all pending flags. */
|
||||
EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
|
||||
EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
|
||||
/* Set all interrupt as secure interrupt. */
|
||||
EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
|
||||
uint16_t Divider;
|
||||
Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
|
||||
|
||||
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
|
||||
case 0x1:
|
||||
/* System OSC */
|
||||
SCGOUTClock = CPU_XTAL_CLK_HZ;
|
||||
break;
|
||||
case 0x2:
|
||||
/* Slow IRC */
|
||||
SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
|
||||
break;
|
||||
case 0x3:
|
||||
/* Fast IRC */
|
||||
SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
|
||||
break;
|
||||
case 0x5:
|
||||
/* Low Power FLL */
|
||||
SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
SystemCoreClock = (SCGOUTClock / Divider);
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInitHook()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||
/* Void implementation of the weak function. */
|
||||
}
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__)
|
||||
#pragma weak SystemIrqHandler
|
||||
void SystemIrqHandler(uint32_t mcause) {
|
||||
#elif defined(__GNUC__)
|
||||
__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
|
||||
#else
|
||||
#error Not supported compiler type
|
||||
#endif
|
||||
uint32_t intNum;
|
||||
|
||||
if (mcause & 0x80000000) /* For external interrupt. */
|
||||
{
|
||||
intNum = mcause & 0x1FUL;
|
||||
|
||||
irqNesting++;
|
||||
|
||||
/* Clear pending flag in EVENT unit .*/
|
||||
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
|
||||
|
||||
/* Read back to make sure write finished. */
|
||||
(void)(EVENT_UNIT->INTPTPENDCLEAR);
|
||||
|
||||
__enable_irq(); /* Support nesting interrupt */
|
||||
|
||||
/* Now call the real irq handler for intNum */
|
||||
isrTable[intNum]();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
irqNesting--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Use LIPT1 channel 0 for systick. */
|
||||
#define SYSTICK_LPIT LPIT1
|
||||
#define SYSTICK_LPIT_CH 0
|
||||
#define SYSTICK_LPIT_IRQn LPIT1_IRQn
|
||||
|
||||
/* Leverage LPIT0 to provide Systick */
|
||||
void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
|
||||
{
|
||||
/* Init pit module */
|
||||
CLOCK_EnableClock(kCLOCK_Lpit1);
|
||||
|
||||
/* Reset the timer channels and registers except the MCR register */
|
||||
SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
|
||||
SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
|
||||
|
||||
/* Setup timer operation in debug and doze modes and enable the module */
|
||||
SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
|
||||
|
||||
/* Set timer period for channel 0 */
|
||||
SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
|
||||
|
||||
/* Enable timer interrupts for channel 0 */
|
||||
SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
|
||||
|
||||
/* Set interrupt priority. */
|
||||
EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
|
||||
|
||||
/* Enable interrupt at the EVENT unit */
|
||||
EnableIRQ(SYSTICK_LPIT_IRQn);
|
||||
|
||||
/* Start channel 0 */
|
||||
SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
|
||||
}
|
||||
|
||||
uint32_t SystemGetIRQNestingLevel(void)
|
||||
{
|
||||
return irqNesting;
|
||||
}
|
||||
|
||||
void SystemClearSystickFlag(void)
|
||||
{
|
||||
/* Channel 0. */
|
||||
SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
|
||||
}
|
||||
|
||||
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
|
||||
{
|
||||
uint8_t regIdx;
|
||||
uint8_t regOffset;
|
||||
|
||||
if ((IRQn < 32) && (intPriority < 8))
|
||||
{
|
||||
/*
|
||||
* 4 priority control registers, each register controls 8 interrupts.
|
||||
* Bit 0-2: interrupt 0
|
||||
* Bit 4-7: interrupt 1
|
||||
* ...
|
||||
* Bit 28-30: interrupt 7
|
||||
*/
|
||||
regIdx = IRQn >> 3U;
|
||||
regOffset = (IRQn & 0x07U) * 4U;
|
||||
|
||||
EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
|
||||
}
|
||||
}
|
||||
|
||||
bool SystemInISR(void)
|
||||
{
|
||||
return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
|
||||
}
|
||||
|
||||
void EVENT_SystemReset(void)
|
||||
{
|
||||
EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
|
||||
}
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: RV32M1_zero_riscy
|
||||
** RV32M1_zero_riscy
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
|
||||
** Version: rev. 1.0, 2018-10-02
|
||||
** Build: b180926
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2018-10-02)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file RV32M1_zero_riscy
|
||||
* @version 1.0
|
||||
* @date 2018-10-02
|
||||
* @brief Device specific configuration file for RV32M1_zero_riscy (header
|
||||
* file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: RV32M1_zero_riscy
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#ifndef _SYSTEM_RV32M1_zero_riscy_H_
|
||||
#define _SYSTEM_RV32M1_zero_riscy_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* Define clock source values */
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */
|
||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
* @brief SystemInit function hook.
|
||||
*
|
||||
* This weak function allows to call specific initialization code during the
|
||||
* SystemInit() execution.This can be used when an application specific code needs
|
||||
* to be called as close to the reset entry as possible (for example the Multicore
|
||||
* Manager MCMGR_EarlyInit() function call).
|
||||
* NOTE: No global r/w variables can be used in this hook function because the
|
||||
* initialization of these variables happens after this function.
|
||||
*/
|
||||
void SystemInitHook (void);
|
||||
|
||||
/**
|
||||
* @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
|
||||
*
|
||||
* It is called from IRQ exception context and dispatches to registered handler according to
|
||||
* MCAUSE interrupt number.
|
||||
*
|
||||
* @param mcause IRQ acknowledge value read from MCAUSE
|
||||
*/
|
||||
void SystemIrqHandler(uint32_t mcause);
|
||||
|
||||
/**
|
||||
* @brief Get IRQ nesting level of current context.
|
||||
*
|
||||
* If the return value is 0, then the context is not ISR, otherwise the context is ISR.
|
||||
*
|
||||
* @return IRQ nesting level
|
||||
*/
|
||||
uint32_t SystemGetIRQNestingLevel (void);
|
||||
|
||||
/**
|
||||
* @brief Setup systick for RTOS system.
|
||||
*
|
||||
* @param tickRateHz Tick number per second
|
||||
* @param intPriority IRQ interrupt priority (the smaller, the higher priority)
|
||||
*/
|
||||
void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
|
||||
|
||||
/**
|
||||
* @brief Clear systick flag status so that next tick interrupt may occur.
|
||||
*/
|
||||
void SystemClearSystickFlag (void);
|
||||
|
||||
#define SysTick_Handler LPIT1_IRQHandler
|
||||
|
||||
/**
|
||||
* @brief Sysem is in ISR or not.
|
||||
*/
|
||||
bool SystemInISR(void);
|
||||
|
||||
/**
|
||||
* @brief Set interrupt priority in Event unit.
|
||||
*/
|
||||
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
|
||||
|
||||
/* Priority setting macro remap. */
|
||||
#define NVIC_SetPriority EVENT_SetIRQPriority
|
||||
|
||||
/**
|
||||
* @brief Reset the system.
|
||||
*/
|
||||
void EVENT_SystemReset(void);
|
||||
|
||||
#define NVIC_SystemReset EVENT_SystemReset
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_RV32M1_zero_riscy_H_ */
|
|
@ -0,0 +1,31 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_RV32M1_VEGA
|
||||
bool
|
||||
select ARCH_RISCV
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "rv32m1_vega feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
SRC_FILES := board.c
|
||||
|
||||
SRC_DIR := third_party_driver
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
|
@ -0,0 +1,185 @@
|
|||
# 从零开始构建矽璓工业物联操作系统:使用risc-v架构的rv32m1_vega 开发板
|
||||
|
||||
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统,来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems),是支持互联网时代人机物融合泛在计算应用模式的新型操作系统,是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中,不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS,XiUOS即是面向工业物联场景的一种UOS,主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成,支持工业物联网(IIoT: Industrial Internet of Things)应用。
|
||||
|
||||
|
||||
## 开发环境搭建
|
||||
|
||||
### 推荐使用:
|
||||
|
||||
**操作系统:** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
|
||||
|
||||
**开发工具推荐使用 VSCode ,VScode下载地址为:** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/),推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
|
||||
|
||||
### 依赖包安装:
|
||||
|
||||
```
|
||||
$ sudo apt install build-essential pkg-config
|
||||
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git
|
||||
```
|
||||
|
||||
**源码下载:** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
|
||||
|
||||
新建一个空文件夹并进入文件夹中,并下载源码,具体命令如下:
|
||||
|
||||
```c
|
||||
mkdir test && cd test
|
||||
git clone https://git.trustie.net/xuos/xiuos.git
|
||||
```
|
||||
|
||||
打开源码文件包可以看到以下目录:
|
||||
| 名称 | 说明 |
|
||||
| -- | -- |
|
||||
| application | 应用代码 |
|
||||
| board | 板级支持包 |
|
||||
| framework | 应用框架 |
|
||||
| fs | 文件系统 |
|
||||
| kernel | 内核源码 |
|
||||
| resources | 驱动文件 |
|
||||
| tool | 系统工具 |
|
||||
|
||||
使用VScode打开代码,具体操作步骤为:在源码文件夹下打开系统终端,输入`code .`即可打开VScode开发环境,如下图所示:
|
||||
|
||||

|
||||
|
||||
### 裁减配置工具的下载
|
||||
|
||||
裁减配置工具:
|
||||
|
||||
**工具地址:** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
|
||||
|
||||
```c
|
||||
mkdir kfrontends && cd kfrontends
|
||||
git clone https://git.trustie.net/xuos/kconfig-frontends.git
|
||||
```
|
||||
|
||||
下载源码后按以下步骤执行软件安装:
|
||||
|
||||
```c
|
||||
cd kconfig-frontends
|
||||
./xs_build.sh
|
||||
```
|
||||
|
||||
### 编译工具链:
|
||||
|
||||
RISC-V: riscv-none-embed-,默认安装到Ubuntu的/opt/,下载并解压。[下载网址 https://open-isa.org/downloads/]
|
||||

|
||||
|
||||
|
||||
|
||||
将上述解压的编译工具链的路径添加到board/rv32m1_vega/config.mk文件当中,例如:
|
||||
|
||||
```
|
||||
export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed-
|
||||
```
|
||||
|
||||
若已存在`export CROSS_COMPILE ?=xxxx` 应该将原有的语句注释,再写入上面的语句。
|
||||
|
||||
# 在rv32m1_vega board 上创建第一个应用
|
||||
|
||||
## 1.rv32m1_vega board 简介
|
||||
|
||||
| 硬件 | 描述 |
|
||||
| -- | -- |
|
||||
|芯片型号| RV32M1 |
|
||||
|架构| RV32IMAC |
|
||||
|主频| 48MHz |
|
||||
|片内SRAM| 1.25 MB Flash 384 KB SRAM |
|
||||
| 外设 | BLK FSK/GFSK |
|
||||
|
||||
XiUOS板级当前支持使用UART。
|
||||
|
||||
## 2. 代码编写与编译说明
|
||||
|
||||
编辑环境:`VScode`
|
||||
|
||||
编译工具链:`riscv-none-embed-gcc`
|
||||
|
||||
使用`VScode`打开工程的方法有多种,本文介绍一种快捷键,在项目目录下将`code .`输入终端即可打开目标项目
|
||||
|
||||
修改`applications`文件夹下`main.c`
|
||||
|
||||
在输出函数中写入 Hello, world! \n 完成代码编辑。
|
||||
|
||||
|
||||
编译步骤:
|
||||
|
||||
1.在VScode终端下执行以下命令,生成配置文件
|
||||
|
||||
```
|
||||
make BOARD=rm32v1_vega menuconfig
|
||||
```
|
||||
|
||||
2.在menuconfig界面配置需要关闭和开启的功能,按回车键进入下级菜单,按Y键选中需要开启的功能,按N键选中需要关闭的功能,配置结束后选择Exit保存并退出
|
||||
|
||||

|
||||
|
||||
3.继续执行以下命令,进行编译
|
||||
|
||||
```
|
||||
make BOARD=rv32m1_vega
|
||||
```
|
||||
|
||||
4.如果编译正确无误,build文件夹下会产生XiUOS_rv32m1_vega.elf、XiUOS_rv32m1_vega.bin文件。
|
||||
|
||||
>注:最后可以执行以下命令,清除配置文件和编译生成的文件
|
||||
|
||||
```
|
||||
make BOARD=rv32m1_vega distclean
|
||||
```
|
||||
|
||||
## 3. 烧写及调试执行
|
||||
rv32m1_vega开发板启动模式说明:参考文档[RV32M1_VEGA_Quick_Start_Guide.pdf](./doc/RV32M1_VEGA_Board_User_Guide.pdf)
|
||||

|
||||
|
||||
|
||||
### 3.1 openocd gdb 调试方法
|
||||
请使用JLink接入到RV32M1_VEGA开发板的RISC-V核的JTAG接口上,同时把JLink在PC上的驱动更改为WinUSB模式。JTAG接口位于RV32M1芯片和天线座子旁边,小的20pin JTAG接口。
|
||||
参考文档:[RV32M1_VEGA_Quick_Start_Guide.pdf](./doc/RV32M1_VEGA_Quick_Start_Guide.pdf)
|
||||
|
||||
rv32m1_vega支持openocd,可以通过openocd和gdb进行调试。
|
||||
调试需要下载openocd和sdk,下载配置方法参见以下文档:
|
||||
https://github.com/open-isa-org/open-isa.org/blob/master/RV32M1_Vega_Develop_Environment_Setup.pdf
|
||||
|
||||
openocd安装完成以后,按照如下步骤进行调试:
|
||||
|
||||
1、进入xiuos目录路径下
|
||||
```
|
||||
cd ~/xiuos/Ubiquitous/XiUOS
|
||||
```
|
||||
|
||||
2、编译生成elf文件
|
||||
|
||||
|
||||
3、使用USB先和串口连接好开发板,进入openocd目录下,再在当前终端输入
|
||||
```
|
||||
cd /vega_rv32/sdk
|
||||
|
||||
Openocd -f <install_dir>\boards\rv32m1_vega\vega_ri5cy.cfg
|
||||
```
|
||||
在当前终端连接openocd,连接如下图所示:
|
||||

|
||||
|
||||
4、打开一个新的终端,输入以下命令打开终端串口:
|
||||
```
|
||||
sudo apt install screen
|
||||
screen /dev/ttyUSB0 115200
|
||||
```
|
||||
|
||||
5、打开一个新的终端,进入编译生成的elf路径,输入例如:
|
||||
```
|
||||
riscv-none-embed-gdb build/XiUOS_rv32m1_vega.elf -ex "target remote localhost:3333"
|
||||
```
|
||||
结果如下图所示:
|
||||

|
||||
|
||||
6、再输入load,最后输入continue命令即可在串口终端看到系统运行界面,如下图所示:
|
||||

|
||||
|
||||
|
||||
### 3.2 板载的串口调试
|
||||
1、Windows 需要安装jlink驱动
|
||||
2、开发板需要修改固件为RISCV启动,具体参考:
|
||||
https://www.cnblogs.com/whik/p/10952292.html
|
||||
|
||||
https://open-isa.cn/community/topic/%E7%BB%87%E5%A5%B3%E6%98%9F%E5%BC%80%E5%8F%91%E6%9D%BF%E8%B0%83%E8%AF%95%E5%99%A8%E5%8D%87%E7%BA%A7%E4%B8%BAJlink%E5%9B%BA%E4%BB%B6/
|
|
@ -0,0 +1,73 @@
|
|||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support vega init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-16
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <xiuos.h>
|
||||
#include <device.h>
|
||||
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
#include <fsl_clock.h>
|
||||
#include <fsl_intmux.h>
|
||||
|
||||
extern int InitHwUart();
|
||||
extern void entry(void);
|
||||
|
||||
void Rv32m1VgeaStart(void)
|
||||
{
|
||||
entry();
|
||||
}
|
||||
|
||||
void LPIT0_IRQHandler(void)
|
||||
{
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
SystemClearSystickFlag();
|
||||
}
|
||||
|
||||
int InitHwTick(void)
|
||||
{
|
||||
CLOCK_SetIpSrc(kCLOCK_Lpit0, kCLOCK_IpSrcFircAsync);
|
||||
|
||||
SystemSetupSystick (TICK_PER_SECOND, 0);
|
||||
SystemClearSystickFlag();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const scg_lpfll_config_t g_appScgLpFllConfig_BOARD_BootClockRUN = {
|
||||
.enableMode = kSCG_LpFllEnable, /* LPFLL clock disabled */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
|
||||
void InitBoardHardware(void)
|
||||
{
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
/* Init LPFLL */
|
||||
CLOCK_InitLpFll(&g_appScgLpFllConfig_BOARD_BootClockRUN);
|
||||
|
||||
INTMUX_Init(INTMUX0);
|
||||
INTMUX_EnableInterrupt(INTMUX0, 0, PORTC_IRQn);
|
||||
|
||||
InitHwUart();
|
||||
InitHwTick();
|
||||
InstallConsole("uart0", "uart0_drv", "uart0_dev0");
|
||||
KPrintf("console init completed.\n");
|
||||
|
||||
InitBoardMemory(MEMORY_START_ADDRESS, MEMORY_END_ADDRESS);
|
||||
KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, RV32M1VEGA_SRAM_SIZE);
|
||||
KPrintf("board init done.\n");
|
||||
KPrintf("start kernel...\n");
|
||||
}
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define rvstar-board init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-09-02
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.h
|
||||
Description: define vega-board init configure and start-up function
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. define rvstar-board InitBoardHardware
|
||||
2. define rvstar-board data and bss struct
|
||||
*************************************************/
|
||||
#ifndef BOARD_H__
|
||||
#define BOARD_H__
|
||||
|
||||
#include <xsconfig.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
extern unsigned int __bss_start__;
|
||||
extern unsigned int __bss_end__;
|
||||
extern unsigned int _end;
|
||||
extern unsigned int __stack_end__;
|
||||
|
||||
#define MEMORY_START_ADDRESS (void*)(&_end)
|
||||
#define RV32M1VEGA_SRAM_SIZE 0x00030000 - 0x1800
|
||||
#define MEMORY_END_ADDRESS (void*)(0x20000000 + RV32M1VEGA_SRAM_SIZE)
|
||||
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -0,0 +1,16 @@
|
|||
|
||||
export CFLAGS := -march=rv32imac -mabi=ilp32 -fno-builtin -fno-exceptions -ffunction-sections -O0 -ggdb -Werror
|
||||
export AFLAGS := -c -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb
|
||||
export LFLAGS := -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_rv32m1_vega.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
|
||||
export CXXFLAGS := -march=rv32imac -mabi=ilp32 -fno-builtin -fno-exceptions -ffunction-sections -O0 -ggdb -Werror
|
||||
|
||||
export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed-
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO
|
||||
|
||||
export ARCH = risc-v
|
||||
export MCU = RV32M1_VEGA
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: fsl_host
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#include "fsl_host.h"
|
||||
#include "board.h"
|
||||
#include "fsl_gpio.h"
|
||||
#ifdef BOARD_USDHC_CD_PORT_BASE
|
||||
#include "fsl_port.h"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief host controller error recovery.
|
||||
* @param host base address.
|
||||
*/
|
||||
static void Host_ErrorRecovery(HOST_TYPE *hostBase);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* DMA descriptor should allocate at non-cached memory */
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN);
|
||||
extern volatile uint32_t g_timeMilliseconds;
|
||||
static volatile bool g_sdInsertedFlag;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/* Card detect. */
|
||||
status_t CardInsertDetect(HOST_TYPE *hostBase)
|
||||
{
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/* User defined transfer function. */
|
||||
static status_t USDHC_TransferFunction(USDHC_Type *base, usdhc_transfer_t *content)
|
||||
{
|
||||
status_t error = kStatus_Success;
|
||||
|
||||
usdhc_adma_config_t dmaConfig;
|
||||
|
||||
if (content->data != NULL)
|
||||
{
|
||||
memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
|
||||
/* config adma */
|
||||
dmaConfig.dmaMode = USDHC_DMA_MODE;
|
||||
dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
|
||||
dmaConfig.admaTable = g_usdhcAdma2Table;
|
||||
dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
|
||||
}
|
||||
|
||||
error = USDHC_TransferBlocking(base, &dmaConfig, content);
|
||||
|
||||
if (error == kStatus_Fail)
|
||||
{
|
||||
/* host error recovery */
|
||||
Host_ErrorRecovery(base);
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
static void Host_ErrorRecovery(HOST_TYPE *hostBase)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
/* get host present status */
|
||||
status = USDHC_GetPresentStatusFlags(hostBase);
|
||||
/* check command inhibit status flag */
|
||||
if ((status & kUSDHC_CommandInhibitFlag) != 0U)
|
||||
{
|
||||
/* reset command line */
|
||||
USDHC_Reset(hostBase, kUSDHC_ResetCommand, 100U);
|
||||
}
|
||||
/* check data inhibit status flag */
|
||||
if ((status & kUSDHC_DataInhibitFlag) != 0U)
|
||||
{
|
||||
/* reset data line */
|
||||
USDHC_Reset(hostBase, kUSDHC_ResetData, 100U);
|
||||
}
|
||||
}
|
||||
|
||||
status_t HOST_Init(void *host)
|
||||
{
|
||||
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
|
||||
|
||||
/* init card power control */
|
||||
HOST_INIT_SD_POWER();
|
||||
HOST_INIT_MMC_POWER();
|
||||
|
||||
/* Initializes USDHC. */
|
||||
usdhcHost->config.dataTimeout = USDHC_DATA_TIMEOUT;
|
||||
usdhcHost->config.endianMode = USDHC_ENDIAN_MODE;
|
||||
usdhcHost->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
|
||||
usdhcHost->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
|
||||
usdhcHost->config.readBurstLen = USDHC_READ_BURST_LEN;
|
||||
usdhcHost->config.writeBurstLen = USDHC_WRITE_BURST_LEN;
|
||||
|
||||
USDHC_Init(usdhcHost->base, &(usdhcHost->config));
|
||||
|
||||
/* Define transfer function. */
|
||||
usdhcHost->transfer = USDHC_TransferFunction;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void HOST_Reset(HOST_TYPE *hostBase)
|
||||
{
|
||||
/* voltage switch to normal but not 1.8V */
|
||||
HOST_SWITCH_VOLTAGE180V(hostBase, false);
|
||||
/* Disable DDR mode */
|
||||
HOST_ENABLE_DDR_MODE(hostBase, false);
|
||||
/* disable tuning */
|
||||
HOST_EXECUTE_STANDARD_TUNING_ENABLE(hostBase, false);
|
||||
/* Disable HS400 mode */
|
||||
HOST_ENABLE_HS400_MODE(hostBase, false);
|
||||
/* Disable DLL */
|
||||
HOST_ENABLE_STROBE_DLL(hostBase, false);
|
||||
}
|
||||
|
||||
void HOST_Deinit(void *host)
|
||||
{
|
||||
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
|
||||
USDHC_Deinit(usdhcHost->base);
|
||||
}
|
After Width: | Height: | Size: 80 KiB |
After Width: | Height: | Size: 42 KiB |
After Width: | Height: | Size: 44 KiB |
After Width: | Height: | Size: 60 KiB |
After Width: | Height: | Size: 21 KiB |
After Width: | Height: | Size: 50 KiB |
After Width: | Height: | Size: 56 KiB |
|
@ -0,0 +1,142 @@
|
|||
/* Entry Point */
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_vector (RX) : ORIGIN = 0x000FFF00, LENGTH = 0x00000100
|
||||
m_text (RX) : ORIGIN = 0x00000000, LENGTH = 0x000FFF00
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - 0x1800
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
.vectors : ALIGN(4)
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
KEEP(*(.vectors))
|
||||
} > m_vector
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.startup))
|
||||
. = ALIGN(4);
|
||||
__user_vector = .;
|
||||
KEEP(*(user_vectors))
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.srodata .srodata.*)
|
||||
*(.eh_frame)
|
||||
*(.init)
|
||||
*(.fini)
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
_shell_command_start = .;
|
||||
KEEP (*(shellCommand))
|
||||
_shell_command_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__isrtbl_idx_start = .;
|
||||
KEEP(*(.isrtbl.idx))
|
||||
__isrtbl_start = .;
|
||||
KEEP(*(.isrtbl))
|
||||
__isrtbl_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||
KEEP(*(.g_service_table))
|
||||
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||
. = ALIGN(4);
|
||||
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__global_pointer = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.sdata .sdata.*)
|
||||
*(.heapsram*) /* This is only for the pulpino official test code. */
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable)
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
_edata = .;
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
. += STACK_SIZE;
|
||||
__StackTop = .;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(.sbss)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
/* End of uninitalized data segement */
|
||||
_end = .;
|
||||
PROVIDE(end = .);
|
||||
}
|
|
@ -0,0 +1,25 @@
|
|||
menuconfig BSP_USING_GPIO
|
||||
bool "Using GPIO device"
|
||||
default y
|
||||
select RESOURCES_PIN
|
||||
if BSP_USING_GPIO
|
||||
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SYSCLOCK
|
||||
bool "Using SYSCLOCK device"
|
||||
default y
|
||||
if BSP_USING_SYSCLOCK
|
||||
source "$BSP_DIR/third_party_driver/sys_clock/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Using UART device"
|
||||
default y
|
||||
select RESOURCES_SERIAL
|
||||
if BSP_USING_UART
|
||||
source "$BSP_DIR/third_party_driver/uart/Kconfig"
|
||||
endif
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
SRC_FILES := fsl_intmux.c fsl_clock.c
|
||||
SRC_DIR :=
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_GPIO),y)
|
||||
SRC_DIR += gpio
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y)
|
||||
SRC_DIR += sys_clock
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_UART),y)
|
||||
SRC_DIR += uart
|
||||
endif
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
|
@ -0,0 +1,805 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright (c) 2016 - 2017 , NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: fsl_clock
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define SCG_SIRC_LOW_RANGE_FREQ 2000000U /* Slow IRC low range clock frequency. */
|
||||
#define SCG_SIRC_HIGH_RANGE_FREQ 8000000U /* Slow IRC high range clock frequency. */
|
||||
|
||||
#define SCG_FIRC_FREQ0 48000000U /* Fast IRC trimed clock frequency(48MHz). */
|
||||
#define SCG_FIRC_FREQ1 52000000U /* Fast IRC trimed clock frequency(52MHz). */
|
||||
#define SCG_FIRC_FREQ2 56000000U /* Fast IRC trimed clock frequency(56MHz). */
|
||||
#define SCG_FIRC_FREQ3 60000000U /* Fast IRC trimed clock frequency(60MHz). */
|
||||
|
||||
#define SCG_LPFLL_FREQ0 48000000U /* LPFLL trimed clock frequency(48MHz). */
|
||||
#define SCG_LPFLL_FREQ1 72000000U /* LPFLL trimed clock frequency(72MHz). */
|
||||
#define SCG_LPFLL_FREQ2 96000000U /* LPFLL trimed clock frequency(96MHz). */
|
||||
#define SCG_LPFLL_FREQ3 120000000U /* LPFLL trimed clock frequency(120MHz). */
|
||||
|
||||
#define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
|
||||
#define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT)
|
||||
#define SCG_SOSCDIV_SOSCDIV2_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT)
|
||||
#define SCG_SOSCDIV_SOSCDIV3_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV3_MASK) >> SCG_SOSCDIV_SOSCDIV3_SHIFT)
|
||||
#define SCG_SIRCDIV_SIRCDIV1_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT)
|
||||
#define SCG_SIRCDIV_SIRCDIV2_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT)
|
||||
#define SCG_SIRCDIV_SIRCDIV3_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV3_MASK) >> SCG_SIRCDIV_SIRCDIV3_SHIFT)
|
||||
#define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT)
|
||||
#define SCG_FIRCDIV_FIRCDIV2_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT)
|
||||
#define SCG_FIRCDIV_FIRCDIV3_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV3_MASK) >> SCG_FIRCDIV_FIRCDIV3_SHIFT)
|
||||
|
||||
#define SCG_LPFLLDIV_LPFLLDIV1_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV1_MASK) >> SCG_LPFLLDIV_LPFLLDIV1_SHIFT)
|
||||
#define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_LPFLLDIV2_SHIFT)
|
||||
#define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_LPFLLDIV3_SHIFT)
|
||||
|
||||
#define SCG_SIRCCFG_RANGE_VAL ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT)
|
||||
#define SCG_FIRCCFG_RANGE_VAL ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT)
|
||||
|
||||
#define SCG_LPFLLCFG_FSEL_VAL ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT)
|
||||
|
||||
/* Get the value of each field in PCC register. */
|
||||
#define PCC_PCS_VAL(reg) ((reg & PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)
|
||||
#define PCC_FRAC_VAL(reg) ((reg & PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT)
|
||||
#define PCC_PCD_VAL(reg) ((reg & PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT)
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/* External XTAL0 (OSC0) clock frequency. */
|
||||
uint32_t g_xtal0Freq;
|
||||
/* External XTAL32K clock frequency. */
|
||||
uint32_t g_xtal32Freq;
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
uint32_t CLOCK_GetOsc32kClkFreq(void)
|
||||
{
|
||||
assert(g_xtal32Freq);
|
||||
return g_xtal32Freq;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetFlashClkFreq(void)
|
||||
{
|
||||
return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetBusClkFreq(void)
|
||||
{
|
||||
return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetPlatClkFreq(void)
|
||||
{
|
||||
return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetCoreSysClkFreq(void)
|
||||
{
|
||||
return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetExtClkFreq(void)
|
||||
{
|
||||
return CLOCK_GetSysClkFreq(kSCG_SysClkExt);
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetFreq(clock_name_t clockName)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
switch (clockName)
|
||||
{
|
||||
/* System layer clock. */
|
||||
case kCLOCK_CoreSysClk:
|
||||
case kCLOCK_PlatClk:
|
||||
freq = CLOCK_GetSysClkFreq(kSCG_SysClkCore);
|
||||
break;
|
||||
case kCLOCK_BusClk:
|
||||
freq = CLOCK_GetSysClkFreq(kSCG_SysClkBus);
|
||||
break;
|
||||
case kCLOCK_FlashClk:
|
||||
freq = CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
|
||||
break;
|
||||
case kCLOCK_ExtClk:
|
||||
freq = CLOCK_GetSysClkFreq(kSCG_SysClkExt);
|
||||
break;
|
||||
/* Original clock source. */
|
||||
case kCLOCK_ScgSysOscClk:
|
||||
freq = CLOCK_GetSysOscFreq();
|
||||
break;
|
||||
case kCLOCK_ScgSircClk:
|
||||
freq = CLOCK_GetSircFreq();
|
||||
break;
|
||||
case kCLOCK_ScgFircClk:
|
||||
freq = CLOCK_GetFircFreq();
|
||||
break;
|
||||
case kCLOCK_ScgLpFllClk:
|
||||
freq = CLOCK_GetLpFllFreq();
|
||||
break;
|
||||
|
||||
/* SOSC div clock. */
|
||||
case kCLOCK_ScgSysOscAsyncDiv1Clk:
|
||||
freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv1Clk);
|
||||
break;
|
||||
case kCLOCK_ScgSysOscAsyncDiv2Clk:
|
||||
freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv2Clk);
|
||||
break;
|
||||
case kCLOCK_ScgSysOscAsyncDiv3Clk:
|
||||
freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv3Clk);
|
||||
break;
|
||||
|
||||
/* SIRC div clock. */
|
||||
case kCLOCK_ScgSircAsyncDiv1Clk:
|
||||
freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv1Clk);
|
||||
break;
|
||||
case kCLOCK_ScgSircAsyncDiv2Clk:
|
||||
freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv2Clk);
|
||||
break;
|
||||
case kCLOCK_ScgSircAsyncDiv3Clk:
|
||||
freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv3Clk);
|
||||
break;
|
||||
|
||||
/* FIRC div clock. */
|
||||
case kCLOCK_ScgFircAsyncDiv1Clk:
|
||||
freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv1Clk);
|
||||
break;
|
||||
case kCLOCK_ScgFircAsyncDiv2Clk:
|
||||
freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv2Clk);
|
||||
break;
|
||||
case kCLOCK_ScgFircAsyncDiv3Clk:
|
||||
freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv3Clk);
|
||||
break;
|
||||
|
||||
/* LPFLL div clock. */
|
||||
case kCLOCK_ScgSysLpFllAsyncDiv1Clk:
|
||||
freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv1Clk);
|
||||
break;
|
||||
case kCLOCK_ScgSysLpFllAsyncDiv2Clk:
|
||||
freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv2Clk);
|
||||
break;
|
||||
case kCLOCK_ScgSysLpFllAsyncDiv3Clk:
|
||||
freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv3Clk);
|
||||
break;
|
||||
|
||||
/* Other clocks. */
|
||||
case kCLOCK_LpoClk:
|
||||
freq = CLOCK_GetLpoClkFreq();
|
||||
break;
|
||||
case kCLOCK_Osc32kClk:
|
||||
freq = CLOCK_GetOsc32kClkFreq();
|
||||
break;
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetIpFreq(clock_ip_name_t name)
|
||||
{
|
||||
uint32_t reg = (*(volatile uint32_t *)name);
|
||||
|
||||
scg_async_clk_t asycClk;
|
||||
uint32_t freq;
|
||||
|
||||
assert(reg & PCC_CLKCFG_PR_MASK);
|
||||
|
||||
switch (name)
|
||||
{
|
||||
case kCLOCK_Lpit0:
|
||||
case kCLOCK_Lpit1:
|
||||
asycClk = kSCG_AsyncDiv3Clk;
|
||||
break;
|
||||
case kCLOCK_Sdhc0:
|
||||
case kCLOCK_Usb0:
|
||||
asycClk = kSCG_AsyncDiv1Clk;
|
||||
break;
|
||||
default:
|
||||
asycClk = kSCG_AsyncDiv2Clk;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (PCC_PCS_VAL(reg))
|
||||
{
|
||||
case kCLOCK_IpSrcSysOscAsync:
|
||||
freq = CLOCK_GetSysOscAsyncFreq(asycClk);
|
||||
break;
|
||||
case kCLOCK_IpSrcSircAsync:
|
||||
freq = CLOCK_GetSircAsyncFreq(asycClk);
|
||||
break;
|
||||
case kCLOCK_IpSrcFircAsync:
|
||||
freq = CLOCK_GetFircAsyncFreq(asycClk);
|
||||
break;
|
||||
case kCLOCK_IpSrcLpFllAsync:
|
||||
freq = CLOCK_GetLpFllAsyncFreq(asycClk);
|
||||
break;
|
||||
default: /* kCLOCK_IpSrcNoneOrExt. */
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK)))
|
||||
{
|
||||
return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
return freq;
|
||||
}
|
||||
}
|
||||
|
||||
bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
|
||||
{
|
||||
bool ret = true;
|
||||
|
||||
CLOCK_SetIpSrc(kCLOCK_Usb0, kCLOCK_IpSrcFircAsync);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable clock gate. */
|
||||
CLOCK_EnableClock(kCLOCK_Usb0);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
USBVREG->CTRL |= USBVREG_CTRL_EN_MASK;
|
||||
USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
|
||||
|
||||
if (kCLOCK_UsbSrcIrc48M == src)
|
||||
{
|
||||
USB0->CLK_RECOVER_IRC_EN = 0x03U;
|
||||
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
|
||||
USB0->CLK_RECOVER_INT_EN = 0x00U;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
scg_sys_clk_config_t sysClkConfig;
|
||||
|
||||
CLOCK_GetCurSysClkConfig(&sysClkConfig); /* Get the main clock for SoC platform. */
|
||||
|
||||
switch (sysClkConfig.src)
|
||||
{
|
||||
case kSCG_SysClkSrcSysOsc:
|
||||
freq = CLOCK_GetSysOscFreq();
|
||||
break;
|
||||
case kSCG_SysClkSrcSirc:
|
||||
freq = CLOCK_GetSircFreq();
|
||||
break;
|
||||
case kSCG_SysClkSrcFirc:
|
||||
freq = CLOCK_GetFircFreq();
|
||||
break;
|
||||
case kSCG_SysClkSrcRosc:
|
||||
freq = CLOCK_GetRtcOscFreq();
|
||||
break;
|
||||
case kSCG_SysClkSrcLpFll:
|
||||
freq = CLOCK_GetLpFllFreq();
|
||||
break;
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */
|
||||
|
||||
if (kSCG_SysClkSlow == type)
|
||||
{
|
||||
freq /= (sysClkConfig.divSlow + 1U);
|
||||
}
|
||||
else if (kSCG_SysClkBus == type)
|
||||
{
|
||||
freq /= (sysClkConfig.divBus + 1U);
|
||||
}
|
||||
else if (kSCG_SysClkExt == type)
|
||||
{
|
||||
freq /= (sysClkConfig.divExt + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
status_t status;
|
||||
uint8_t tmp8;
|
||||
|
||||
/* De-init the SOSC first. */
|
||||
status = CLOCK_DeinitSysOsc();
|
||||
|
||||
if (kStatus_Success != status)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Now start to set up OSC clock. */
|
||||
/* Step 1. Setup dividers. */
|
||||
SCG->SOSCDIV =
|
||||
SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3);
|
||||
|
||||
/* Step 2. Set OSC configuration. */
|
||||
|
||||
/* Step 3. Enable clock. */
|
||||
/* SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK | (config->enableMode); */
|
||||
tmp8 = config->enableMode;
|
||||
tmp8 |= SCG_SOSCCSR_SOSCEN_MASK;
|
||||
SCG->SOSCCSR = tmp8;
|
||||
|
||||
/* Step 4. Wait for OSC clock to be valid. */
|
||||
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
|
||||
{
|
||||
}
|
||||
|
||||
/* Step 5. Enabe monitor. */
|
||||
SCG->SOSCCSR |= (uint32_t)config->monitorMode;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t CLOCK_DeinitSysOsc(void)
|
||||
{
|
||||
uint32_t reg = SCG->SOSCCSR;
|
||||
|
||||
/* If clock is used by system, return error. */
|
||||
if (reg & SCG_SOSCCSR_SOSCSEL_MASK)
|
||||
{
|
||||
return kStatus_SCG_Busy;
|
||||
}
|
||||
|
||||
/* If configure register is locked, return error. */
|
||||
if (reg & SCG_SOSCCSR_LK_MASK)
|
||||
{
|
||||
return kStatus_ReadOnly;
|
||||
}
|
||||
|
||||
SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetSysOscFreq(void)
|
||||
{
|
||||
if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */
|
||||
{
|
||||
/* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
|
||||
assert(g_xtal0Freq);
|
||||
return g_xtal0Freq;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type)
|
||||
{
|
||||
uint32_t oscFreq = CLOCK_GetSysOscFreq();
|
||||
uint32_t divider = 0U;
|
||||
|
||||
/* Get divider. */
|
||||
if (oscFreq)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
case kSCG_AsyncDiv3Clk: /* SOSCDIV3_CLK. */
|
||||
divider = SCG_SOSCDIV_SOSCDIV3_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv2Clk: /* SOSCDIV2_CLK. */
|
||||
divider = SCG_SOSCDIV_SOSCDIV2_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv1Clk: /* SOSCDIV1_CLK. */
|
||||
divider = SCG_SOSCDIV_SOSCDIV1_VAL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (divider)
|
||||
{
|
||||
return oscFreq >> (divider - 1U);
|
||||
}
|
||||
else /* Output disabled. */
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
status_t CLOCK_InitSirc(const scg_sirc_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
status_t status;
|
||||
|
||||
/* De-init the SIRC first. */
|
||||
status = CLOCK_DeinitSirc();
|
||||
|
||||
if (kStatus_Success != status)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Now start to set up SIRC clock. */
|
||||
/* Step 1. Setup dividers. */
|
||||
SCG->SIRCDIV =
|
||||
SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3);
|
||||
|
||||
/* Step 2. Set SIRC configuration. */
|
||||
SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range);
|
||||
|
||||
/* Step 3. Enable clock. */
|
||||
SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode;
|
||||
|
||||
/* Step 4. Wait for SIRC clock to be valid. */
|
||||
while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK))
|
||||
{
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t CLOCK_DeinitSirc(void)
|
||||
{
|
||||
uint32_t reg = SCG->SIRCCSR;
|
||||
|
||||
/* If clock is used by system, return error. */
|
||||
if (reg & SCG_SIRCCSR_SIRCSEL_MASK)
|
||||
{
|
||||
return kStatus_SCG_Busy;
|
||||
}
|
||||
|
||||
/* If configure register is locked, return error. */
|
||||
if (reg & SCG_SIRCCSR_LK_MASK)
|
||||
{
|
||||
return kStatus_ReadOnly;
|
||||
}
|
||||
|
||||
SCG->SIRCCSR = 0U;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetSircFreq(void)
|
||||
{
|
||||
static const uint32_t sircFreq[] = {SCG_SIRC_LOW_RANGE_FREQ, SCG_SIRC_HIGH_RANGE_FREQ};
|
||||
|
||||
if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */
|
||||
{
|
||||
return sircFreq[SCG_SIRCCFG_RANGE_VAL];
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type)
|
||||
{
|
||||
uint32_t sircFreq = CLOCK_GetSircFreq();
|
||||
uint32_t divider = 0U;
|
||||
|
||||
/* Get divider. */
|
||||
if (sircFreq)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
case kSCG_AsyncDiv3Clk: /* SIRCDIV3_CLK. */
|
||||
divider = SCG_SIRCDIV_SIRCDIV3_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv2Clk: /* SIRCDIV2_CLK. */
|
||||
divider = SCG_SIRCDIV_SIRCDIV2_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv1Clk: /* SIRCDIV2_CLK. */
|
||||
divider = SCG_SIRCDIV_SIRCDIV1_VAL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (divider)
|
||||
{
|
||||
return sircFreq >> (divider - 1U);
|
||||
}
|
||||
else /* Output disabled. */
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
status_t CLOCK_InitFirc(const scg_firc_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
status_t status;
|
||||
|
||||
/* De-init the FIRC first. */
|
||||
status = CLOCK_DeinitFirc();
|
||||
|
||||
if (kStatus_Success != status)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Now start to set up FIRC clock. */
|
||||
/* Step 1. Setup dividers. */
|
||||
SCG->FIRCDIV =
|
||||
SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3);
|
||||
|
||||
/* Step 2. Set FIRC configuration. */
|
||||
SCG->FIRCCFG = SCG_FIRCCFG_RANGE(config->range);
|
||||
|
||||
/* Step 3. Set trimming configuration. */
|
||||
if (config->trimConfig)
|
||||
{
|
||||
SCG->FIRCTCFG =
|
||||
SCG_FIRCTCFG_TRIMDIV(config->trimConfig->trimDiv) | SCG_FIRCTCFG_TRIMSRC(config->trimConfig->trimSrc);
|
||||
|
||||
/* TODO: Write FIRCSTAT cause bus error: TKT266932. */
|
||||
if (kSCG_FircTrimNonUpdate == config->trimConfig->trimMode)
|
||||
{
|
||||
SCG->FIRCSTAT = SCG_FIRCSTAT_TRIMCOAR(config->trimConfig->trimCoar) |
|
||||
SCG_FIRCSTAT_TRIMFINE(config->trimConfig->trimFine);
|
||||
}
|
||||
|
||||
/* trim mode. */
|
||||
SCG->FIRCCSR = config->trimConfig->trimMode;
|
||||
|
||||
if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
}
|
||||
|
||||
/* Step 4. Enable clock. */
|
||||
SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode);
|
||||
|
||||
/* Step 5. Wait for FIRC clock to be valid. */
|
||||
while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
|
||||
{
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t CLOCK_DeinitFirc(void)
|
||||
{
|
||||
uint32_t reg = SCG->FIRCCSR;
|
||||
|
||||
/* If clock is used by system, return error. */
|
||||
if (reg & SCG_FIRCCSR_FIRCSEL_MASK)
|
||||
{
|
||||
return kStatus_SCG_Busy;
|
||||
}
|
||||
|
||||
/* If configure register is locked, return error. */
|
||||
if (reg & SCG_FIRCCSR_LK_MASK)
|
||||
{
|
||||
return kStatus_ReadOnly;
|
||||
}
|
||||
|
||||
SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetFircFreq(void)
|
||||
{
|
||||
static const uint32_t fircFreq[] = {
|
||||
SCG_FIRC_FREQ0, SCG_FIRC_FREQ1, SCG_FIRC_FREQ2, SCG_FIRC_FREQ3,
|
||||
};
|
||||
|
||||
if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is valid. */
|
||||
{
|
||||
return fircFreq[SCG_FIRCCFG_RANGE_VAL];
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type)
|
||||
{
|
||||
uint32_t fircFreq = CLOCK_GetFircFreq();
|
||||
uint32_t divider = 0U;
|
||||
|
||||
/* Get divider. */
|
||||
if (fircFreq)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
case kSCG_AsyncDiv3Clk: /* FIRCDIV3_CLK. */
|
||||
divider = SCG_FIRCDIV_FIRCDIV3_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv2Clk: /* FIRCDIV2_CLK. */
|
||||
divider = SCG_FIRCDIV_FIRCDIV2_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv1Clk: /* FIRCDIV1_CLK. */
|
||||
divider = SCG_FIRCDIV_FIRCDIV1_VAL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (divider)
|
||||
{
|
||||
return fircFreq >> (divider - 1U);
|
||||
}
|
||||
else /* Output disabled. */
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetRtcOscFreq(void)
|
||||
{
|
||||
if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */
|
||||
{
|
||||
/* Please call CLOCK_SetXtal32Freq base on board setting before using RTC OSC clock. */
|
||||
assert(g_xtal32Freq);
|
||||
return g_xtal32Freq;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
status_t status;
|
||||
|
||||
/* De-init the LPFLL first. */
|
||||
status = CLOCK_DeinitLpFll();
|
||||
|
||||
if (kStatus_Success != status)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Now start to set up LPFLL clock. */
|
||||
/* Step 1. Setup dividers. */
|
||||
SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) |
|
||||
SCG_LPFLLDIV_LPFLLDIV3(config->div3);
|
||||
|
||||
/* Step 2. Set LPFLL configuration. */
|
||||
SCG->LPFLLCFG = SCG_LPFLLCFG_FSEL(config->range);
|
||||
|
||||
/* Step 3. Set trimming configuration. */
|
||||
if (config->trimConfig)
|
||||
{
|
||||
SCG->LPFLLTCFG = SCG_LPFLLTCFG_TRIMDIV(config->trimConfig->trimDiv) |
|
||||
SCG_LPFLLTCFG_TRIMSRC(config->trimConfig->trimSrc) |
|
||||
SCG_LPFLLTCFG_LOCKW2LSB(config->trimConfig->lockMode);
|
||||
|
||||
if (kSCG_LpFllTrimNonUpdate == config->trimConfig->trimMode)
|
||||
{
|
||||
SCG->LPFLLSTAT = config->trimConfig->trimValue;
|
||||
}
|
||||
|
||||
/* Trim mode. */
|
||||
SCG->LPFLLCSR = config->trimConfig->trimMode;
|
||||
|
||||
if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
}
|
||||
|
||||
/* Step 4. Enable clock. */
|
||||
SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode);
|
||||
|
||||
/* Step 5. Wait for LPFLL clock to be valid. */
|
||||
while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK))
|
||||
{
|
||||
}
|
||||
|
||||
/* Step 6. Wait for LPFLL trim lock. */
|
||||
if ((config->trimConfig) && (kSCG_LpFllTrimUpdate == config->trimConfig->trimMode))
|
||||
{
|
||||
while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t CLOCK_DeinitLpFll(void)
|
||||
{
|
||||
uint32_t reg = SCG->LPFLLCSR;
|
||||
|
||||
/* If clock is used by system, return error. */
|
||||
if (reg & SCG_LPFLLCSR_LPFLLSEL_MASK)
|
||||
{
|
||||
return kStatus_SCG_Busy;
|
||||
}
|
||||
|
||||
/* If configure register is locked, return error. */
|
||||
if (reg & SCG_LPFLLCSR_LK_MASK)
|
||||
{
|
||||
return kStatus_ReadOnly;
|
||||
}
|
||||
|
||||
SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetLpFllFreq(void)
|
||||
{
|
||||
static const uint32_t lpfllFreq[] = {
|
||||
SCG_LPFLL_FREQ0, SCG_LPFLL_FREQ1, SCG_LPFLL_FREQ2, SCG_LPFLL_FREQ3,
|
||||
};
|
||||
|
||||
if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */
|
||||
{
|
||||
return lpfllFreq[SCG_LPFLLCFG_FSEL_VAL];
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type)
|
||||
{
|
||||
uint32_t lpfllFreq = CLOCK_GetLpFllFreq();
|
||||
uint32_t divider = 0U;
|
||||
|
||||
/* Get divider. */
|
||||
if (lpfllFreq)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
case kSCG_AsyncDiv2Clk: /* LPFLLDIV2_CLK. */
|
||||
divider = SCG_LPFLLDIV_LPFLLDIV2_VAL;
|
||||
break;
|
||||
case kSCG_AsyncDiv1Clk: /* LPFLLDIV1_CLK. */
|
||||
divider = SCG_LPFLLDIV_LPFLLDIV1_VAL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (divider)
|
||||
{
|
||||
return lpfllFreq >> (divider - 1U);
|
||||
}
|
||||
else /* Output disabled. */
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*************************************************
|
||||
File name: fsl_common
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#include "fsl_common.h"
|
||||
// #include "fsl_debug_console.h"
|
||||
|
||||
#ifndef NDEBUG
|
||||
#if (defined(__CC_ARM)) || (defined(__ICCARM__))
|
||||
void __aeabi_assert(const char *failedExpr, const char *file, int line)
|
||||
{
|
||||
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
|
||||
for (;;)
|
||||
{
|
||||
__BKPT(0);
|
||||
}
|
||||
}
|
||||
#elif(defined(__GNUC__))
|
||||
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
|
||||
{
|
||||
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
|
||||
for (;;)
|
||||
{
|
||||
__BKPT(0);
|
||||
}
|
||||
}
|
||||
#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
|
||||
#endif /* NDEBUG */
|
||||
|
||||
#ifndef __GIC_PRIO_BITS
|
||||
#ifndef __riscv
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||
{
|
||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||
#if defined(__CC_ARM)
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
extern uint32_t Image$$RW_m_data$$Base[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) */
|
||||
uint32_t n;
|
||||
uint32_t ret;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* Copy the vector table from ROM to RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* Point the VTOR to the position of vector table */
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
ret = __VECTOR_RAM[irq + 16];
|
||||
/* make sure the __VECTOR_RAM is noncachable */
|
||||
__VECTOR_RAM[irq + 16] = irqHandler;
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef QN908XC_SERIES
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERSET[index] = 1u << intNumber;
|
||||
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||
}
|
||||
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||
SYSCON->STARTERCLR[index] = 1u << intNumber;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#endif /* QN908XC_SERIES */
|
|
@ -0,0 +1,235 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*************************************************
|
||||
File name: fsl_intmux
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#include "fsl_intmux.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Get instance number for INTMUX.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
*/
|
||||
static uint32_t INTMUX_GetInstance(INTMUX_Type *base);
|
||||
|
||||
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
|
||||
/*!
|
||||
* @brief Handle INTMUX all channels IRQ.
|
||||
*
|
||||
* The handler reads the INTMUX channel's active vector register. This returns the offset
|
||||
* from the start of the vector table to the vector for the INTMUX channel's highest priority
|
||||
* pending source interrupt. After a check for spurious interrupts (an offset of 0), the
|
||||
* function address at the vector offset is read and jumped to.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
* @param channel INTMUX channel number.
|
||||
*/
|
||||
static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel);
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Array to map INTMUX instance number to base pointer. */
|
||||
static INTMUX_Type *const s_intmuxBases[] = INTMUX_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Array to map INTMUX instance number to clock name. */
|
||||
static const clock_ip_name_t s_intmuxClockName[] = INTMUX_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
|
||||
/*! @brief Array to map INTMUX instance number to IRQ number. */
|
||||
static const IRQn_Type s_intmuxIRQNumber[][FSL_FEATURE_INTMUX_CHANNEL_COUNT] = INTMUX_IRQS;
|
||||
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t INTMUX_GetInstance(INTMUX_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_intmuxBases); instance++)
|
||||
{
|
||||
if (s_intmuxBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_intmuxBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
|
||||
static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel)
|
||||
{
|
||||
uint32_t pendingIrqOffset;
|
||||
|
||||
pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC;
|
||||
|
||||
if (pendingIrqOffset)
|
||||
{
|
||||
#if defined(__riscv)
|
||||
extern uint32_t __user_vector[];
|
||||
uint32_t isr = __user_vector[pendingIrqOffset / 4 - 48 + 32];
|
||||
#else
|
||||
uint32_t isr = *(uint32_t *)(SCB->VTOR + pendingIrqOffset);
|
||||
#endif
|
||||
((void (*)(void))isr)();
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
|
||||
|
||||
void INTMUX_Init(INTMUX_Type *base)
|
||||
{
|
||||
uint32_t channel;
|
||||
uint32_t instance = INTMUX_GetInstance(base);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable clock gate. */
|
||||
CLOCK_EnableClock(s_intmuxClockName[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/* Reset all channels and enable NVIC vectors for all INTMUX channels. */
|
||||
for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
|
||||
{
|
||||
INTMUX_ResetChannel(base, channel);
|
||||
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
|
||||
EnableIRQ(s_intmuxIRQNumber[instance][channel]);
|
||||
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
|
||||
}
|
||||
}
|
||||
|
||||
void INTMUX_Deinit(INTMUX_Type *base)
|
||||
{
|
||||
uint32_t channel;
|
||||
uint32_t instance = INTMUX_GetInstance(base);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable clock gate. */
|
||||
CLOCK_DisableClock(s_intmuxClockName[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/* Disable NVIC vectors for all of the INTMUX channels. */
|
||||
for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
|
||||
{
|
||||
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
|
||||
DisableIRQ(s_intmuxIRQNumber[instance][channel]);
|
||||
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
|
||||
}
|
||||
}
|
||||
|
||||
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
|
||||
#if defined(INTMUX0)
|
||||
void INTMUX0_0_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 0);
|
||||
}
|
||||
|
||||
void INTMUX0_1_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 1);
|
||||
}
|
||||
|
||||
void INTMUX0_2_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 2);
|
||||
}
|
||||
|
||||
void INTMUX0_3_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 3);
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_INTMUX_CHANNEL_COUNT) && (FSL_FEATURE_INTMUX_CHANNEL_COUNT > 4U)
|
||||
void INTMUX0_4_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 4);
|
||||
}
|
||||
|
||||
void INTMUX0_5_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 5);
|
||||
}
|
||||
|
||||
void INTMUX0_6_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 6);
|
||||
}
|
||||
|
||||
void INTMUX0_7_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX0, 7);
|
||||
}
|
||||
#endif /* FSL_FEATURE_INTMUX_CHANNEL_COUNT */
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(INTMUX1)
|
||||
void INTMUX1_0_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 0);
|
||||
}
|
||||
|
||||
void INTMUX1_1_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 1);
|
||||
}
|
||||
|
||||
void INTMUX1_2_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 2);
|
||||
}
|
||||
|
||||
void INTMUX1_3_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 3);
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_INTMUX_CHANNEL_COUNT) && (FSL_FEATURE_INTMUX_CHANNEL_COUNT > 4U)
|
||||
void INTMUX1_4_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 4);
|
||||
}
|
||||
|
||||
void INTMUX1_5_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 5);
|
||||
}
|
||||
|
||||
void INTMUX1_6_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 6);
|
||||
}
|
||||
|
||||
void INTMUX1_7_DriverIRQHandler(void)
|
||||
{
|
||||
INTMUX_CommonIRQHandler(INTMUX1, 7);
|
||||
}
|
||||
#endif /* FSL_FEATURE_INTMUX_CHANNEL_COUNT */
|
||||
#endif /* INTMUX1 */
|
||||
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
|
|
@ -0,0 +1,11 @@
|
|||
config PIN_BUS_NAME
|
||||
string "pin bus name"
|
||||
default "pin"
|
||||
|
||||
config PIN_DRIVER_NAME
|
||||
string "pin driver name"
|
||||
default "pin_drv"
|
||||
|
||||
config PIN_DEVICE_NAME
|
||||
string "pin device name"
|
||||
default "pin_dev"
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := pin_mux.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v3.0
|
||||
processor: RV32M1
|
||||
package_id: RV32M1
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: pin_mux
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
#define PIN6_IDX 6u /*!< Pin number for pin 6 in a port */
|
||||
#define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
|
||||
#define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
|
||||
#define PIN9_IDX 9u /*!< Pin number for pin 9 in a port */
|
||||
#define PIN10_IDX 10u /*!< Pin number for pin 10 in a port */
|
||||
#define PIN11_IDX 11u /*!< Pin number for pin 11 in a port */
|
||||
#define PIN22_IDX 22u /*!< Pin number for pin 22 in a port */
|
||||
#define PIN23_IDX 23u /*!< Pin number for pin 23 in a port */
|
||||
#define PIN24_IDX 24u /*!< Pin number for pin 24 in a port */
|
||||
#define PIN25_IDX 25u /*!< Pin number for pin 25 in a port */
|
||||
#define PIN26_IDX 26u /*!< Pin number for pin 26 in a port */
|
||||
#define PIN27_IDX 27u /*!< Pin number for pin 27 in a port */
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
|
||||
- {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
|
||||
- {pin_num: B5, peripheral: LPUART1, signal: RX, pin_signal: PTA25/LPUART1_RX/LPSPI3_SOUT/LPI2C2_SDAS/FB_AD31}
|
||||
- {pin_num: A5, peripheral: LPUART1, signal: TX, pin_signal: PTA26/LPUART1_TX/LPSPI3_PCS2/LPI2C2_SCLS/FB_AD30}
|
||||
- {pin_num: U11, peripheral: SDHC0, signal: CMD, pin_signal: ADC0_SE12/PTD9/SDHC0_CMD/LPSPI2_SIN/LPI2C1_SCLS/TRACE_DATA0/TPM2_CH2/FXIO0_D29, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: up, pull_enable: enable}
|
||||
- {pin_num: P10, peripheral: SDHC0, signal: 'DATA, 0', pin_signal: ADC0_SE10/PTD7/SDHC0_D0/LPSPI2_SOUT/EMVSIM0_PD/TRACE_DATA2/TPM2_CH4/FXIO0_D27, slew_rate: fast,
|
||||
open_drain: disable, pull_select: up, pull_enable: enable}
|
||||
- {pin_num: U9, peripheral: SDHC0, signal: 'DATA, 1', pin_signal: ADC0_SE9/PTD6/SDHC0_D1/LPSPI2_SCK/EMVSIM0_IO/TRACE_DATA3/TPM2_CH5/FXIO0_D26, slew_rate: fast,
|
||||
open_drain: disable, pull_select: up, pull_enable: enable}
|
||||
- {pin_num: R11, peripheral: SDHC0, signal: 'DATA, 2', pin_signal: ADC0_SE14/PTD11/SDHC0_D2/USB0_SOF_OUT/LPI2C1_SCL/CLKOUT/TPM2_CH0/FXIO0_D31, slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
|
||||
- {pin_num: P11, peripheral: SDHC0, signal: 'DATA, 3', pin_signal: ADC0_SE13/PTD10/LLWU_P20/SDHC0_D3/LPSPI2_PCS0/LPI2C1_SDA/TRACE_CLK_OUT/TPM2_CH1/FXIO0_D30, slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
|
||||
- {pin_num: T9, peripheral: SDHC0, signal: DCLK, pin_signal: ADC0_SE11/PTD8/LLWU_P19/SDHC0_DCLK/LPSPI2_PCS2/LPI2C1_SDAS/TRACE_DATA1/TPM2_CH3/FXIO0_D28, slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
|
||||
- {pin_num: P6, peripheral: GPIOC, signal: 'GPIO, 27', pin_signal: PTC27/TPM0_CH4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: 0x01u */
|
||||
CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
|
||||
CLOCK_EnableClock(kCLOCK_PortD); /* Clock Gate Control: 0x01u */
|
||||
|
||||
const port_pin_config_t portc27_pinP6_config = {
|
||||
kPORT_PullDisable, /* Internal pull-up/down resistor is disabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAsGpio, /* Pin is configured as PTC27 */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTC, PIN27_IDX, &portc27_pinP6_config); /* PORTC27 (pin P6) is configured as PTC27 */
|
||||
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
|
||||
PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
|
||||
|
||||
const port_pin_config_t portd10_pinP11_config = {
|
||||
kPORT_PullUp, /* Internal pull-up resistor is enabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D3 */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTD, PIN10_IDX, &portd10_pinP11_config); /* PORTD10 (pin P11) is configured as SDHC0_D3 */
|
||||
const port_pin_config_t portd11_pinR11_config = {
|
||||
kPORT_PullUp, /* Internal pull-up resistor is enabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D2 */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTD, PIN11_IDX, &portd11_pinR11_config); /* PORTD11 (pin R11) is configured as SDHC0_D2 */
|
||||
const port_pin_config_t portd6_pinU9_config = {
|
||||
kPORT_PullUp, /* Internal pull-up resistor is enabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D1 */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTD, PIN6_IDX, &portd6_pinU9_config); /* PORTD6 (pin U9) is configured as SDHC0_D1 */
|
||||
const port_pin_config_t portd7_pinP10_config = {
|
||||
kPORT_PullUp, /* Internal pull-up resistor is enabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D0 */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTD, PIN7_IDX, &portd7_pinP10_config); /* PORTD7 (pin P10) is configured as SDHC0_D0 */
|
||||
const port_pin_config_t portd8_pinT9_config = {
|
||||
kPORT_PullUp, /* Internal pull-up resistor is enabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAlt2, /* Pin is configured as SDHC0_DCLK */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTD, PIN8_IDX, &portd8_pinT9_config); /* PORTD8 (pin T9) is configured as SDHC0_DCLK */
|
||||
const port_pin_config_t portd9_pinU11_config = {
|
||||
kPORT_PullUp, /* Internal pull-up resistor is enabled */
|
||||
kPORT_FastSlewRate, /* Fast slew rate is configured */
|
||||
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
|
||||
kPORT_OpenDrainDisable, /* Open drain is disabled */
|
||||
kPORT_LowDriveStrength, /* Low drive strength is configured */
|
||||
kPORT_MuxAlt2, /* Pin is configured as SDHC0_CMD */
|
||||
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
|
||||
};
|
||||
PORT_SetPinConfig(PORTD, PIN9_IDX, &portd9_pinU11_config); /* PORTD9 (pin U11) is configured as SDHC0_CMD */
|
||||
|
||||
PORT_SetPinMux(PORTA, PIN22_IDX, kPORT_MuxAsGpio); /* PORTA22 (pin D6) is configured as PTA24 */
|
||||
PORT_SetPinMux(PORTA, PIN23_IDX, kPORT_MuxAsGpio); /* PORTA23 (pin D6) is configured as PTA24 */
|
||||
PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio); /* PORTA24 (pin D6) is configured as PTA24 */
|
||||
PORT_SetPinMux(PORTA, PIN25_IDX, kPORT_MuxAlt2); /* PORTA25 (pin B5) is configured as LPUART1_RX */
|
||||
PORT_SetPinMux(PORTA, PIN26_IDX, kPORT_MuxAlt2); /* PORTA26 (pin A5) is configured as LPUART1_TX */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*************************************************
|
||||
File name: clock_config
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 72000000U /*!< Core clock frequency: 72000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockHSRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockHSRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockVLPR;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_uart.h
|
||||
* @brief define vega uart function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-16
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_UART_H
|
||||
#define CONNECT_UART_H
|
||||
|
||||
#include <device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
int InitHwUart(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -0,0 +1,494 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*************************************************
|
||||
File name: fsl_common
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#ifndef _FSL_COMMON_H_
|
||||
#define _FSL_COMMON_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Construct a status code value from a group and code number. */
|
||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
||||
|
||||
/*! @brief Construct the version number for drivers. */
|
||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version 2.0.0. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
|
||||
|
||||
/*! @brief Status group numbers. */
|
||||
enum _status_groups
|
||||
{
|
||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||
kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
|
||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
|
||||
};
|
||||
|
||||
/*! @brief Generic status return codes. */
|
||||
enum _generic_status
|
||||
{
|
||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
|
||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
|
||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
|
||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
|
||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
|
||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
|
||||
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
|
||||
};
|
||||
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*! @name Min/max macros */
|
||||
/* @{ */
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @brief Computes the number of elements in an array. */
|
||||
#if !defined(ARRAY_SIZE)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||
/* @{ */
|
||||
#if !defined(UINT16_MAX)
|
||||
#define UINT16_MAX ((uint16_t)-1)
|
||||
#endif
|
||||
|
||||
#if !defined(UINT32_MAX)
|
||||
#define UINT32_MAX ((uint32_t)-1)
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Timer utilities */
|
||||
/* @{ */
|
||||
/*! Macro to convert a microsecond period to raw count value */
|
||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
|
||||
/*! Macro to convert a raw count value to microsecond */
|
||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
|
||||
|
||||
/*! Macro to convert a millisecond period to raw count value */
|
||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
|
||||
/*! Macro to convert a raw count value to millisecond */
|
||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
|
||||
/* @} */
|
||||
|
||||
/*! @name Alignment variable definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
/**
|
||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||
* http://supp.iar.com/Support/?note=24725
|
||||
*/
|
||||
_Pragma("diag_suppress=Pm120")
|
||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||
_Pragma("diag_error=Pm120")
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__CC_ARM)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__GNUC__)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported
|
||||
#define SDK_ALIGN(var, alignbytes) var
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! Macro to change a value to a given size aligned value */
|
||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
|
||||
/* @} */
|
||||
|
||||
/*! @name Non-cacheable region definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
|
||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__CC_ARM))
|
||||
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__GNUC__))
|
||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||
*/
|
||||
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Enable specific interrupt.
|
||||
*
|
||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt enabled successfully
|
||||
* @retval kStatus_Fail Failed to enable the interrupt
|
||||
*/
|
||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
|
||||
EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt);
|
||||
/* Read back to make sure write finished. */
|
||||
(void)EVENT_UNIT->INTPTEN;
|
||||
#else
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt.
|
||||
*
|
||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt disabled successfully
|
||||
* @retval kStatus_Fail Failed to disable the interrupt
|
||||
*/
|
||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
|
||||
EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt);
|
||||
/* Read back to make sure write finished. */
|
||||
(void)EVENT_UNIT->INTPTEN;
|
||||
#else
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_DisableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_DisableIRQ(interrupt);
|
||||
#endif
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the global IRQ
|
||||
*
|
||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||
* register for the EnableGlobalIRQ().
|
||||
*
|
||||
* @return Current primask value.
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
#ifndef __riscv
|
||||
#if defined(CPSR_I_Msk)
|
||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return cpsr;
|
||||
#else
|
||||
uint32_t regPrimask = __get_PRIMASK();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return regPrimask;
|
||||
#endif
|
||||
#else
|
||||
uint32_t mstatus;
|
||||
|
||||
__ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus));
|
||||
|
||||
return mstatus;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enaable the global IRQ
|
||||
*
|
||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||
*
|
||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||
* DisableGlobalIRQ().
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#ifndef __riscv
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
#else
|
||||
__ASM volatile ("csrw mstatus, %0" : : "r"(primask));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief install IRQ handler
|
||||
*
|
||||
* @param irq IRQ number
|
||||
* @param irqHandler IRQ handler address
|
||||
* @return The old IRQ handler address
|
||||
*/
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
/*!
|
||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Enable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Disable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_COMMON_H_ */
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*************************************************
|
||||
File name: fsl_intmux
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#ifndef _FSL_INTMUX_H_
|
||||
#define _FSL_INTMUX_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup intmux
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*!< Version 2.0.1. */
|
||||
#define FSL_INTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief INTMUX channel logic mode. */
|
||||
typedef enum _intmux_channel_logic_mode
|
||||
{
|
||||
kINTMUX_ChannelLogicOR = 0x0U, /*!< Logic OR all enabled interrupt inputs */
|
||||
kINTMUX_ChannelLogicAND, /*!< Logic AND all enabled interrupt inputs */
|
||||
} intmux_channel_logic_mode_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*! @name Initialization and deinitialization */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the INTMUX module.
|
||||
*
|
||||
* This function enables the clock gate for the specified INTMUX. It then resets all channels, so that no
|
||||
* interrupt sources are routed and the logic mode is set to default of #kINTMUX_ChannelLogicOR.
|
||||
* Finally, the NVIC vectors for all the INTMUX output channels are enabled.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
*/
|
||||
void INTMUX_Init(INTMUX_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes an INTMUX instance for operation.
|
||||
*
|
||||
* The clock gate for the specified INTMUX is disabled and the NVIC vectors for all channels are disabled.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
*/
|
||||
void INTMUX_Deinit(INTMUX_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Resets an INTMUX channel.
|
||||
*
|
||||
* Sets all register values in the specified channel to their reset value. This function disables all interrupt
|
||||
* sources for the channel.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
* @param channel The INTMUX channel number.
|
||||
*/
|
||||
static inline void INTMUX_ResetChannel(INTMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
|
||||
|
||||
base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the logic mode for an INTMUX channel.
|
||||
*
|
||||
* INTMUX channels can be configured to use one of the two logic modes that control how pending interrupt sources
|
||||
* on the channel trigger the output interrupt.
|
||||
* - #kINTMUX_ChannelLogicOR means any source pending triggers the output interrupt.
|
||||
* - #kINTMUX_ChannelLogicAND means all selected sources on the channel must be pending before the channel
|
||||
* output interrupt triggers.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
* @param channel The INTMUX channel number.
|
||||
* @param logic The INTMUX channel logic mode.
|
||||
*/
|
||||
static inline void INTMUX_SetChannelMode(INTMUX_Type *base, uint32_t channel, intmux_channel_logic_mode_t logic)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
|
||||
|
||||
base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/*! @name Sources */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Enables an interrupt source on an INTMUX channel.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
* @param channel Index of the INTMUX channel on which the specified interrupt is enabled.
|
||||
* @param irq Interrupt to route to the specified INTMUX channel. The interrupt must be an INTMUX source.
|
||||
*/
|
||||
static inline void INTMUX_EnableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
|
||||
assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
|
||||
|
||||
base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables an interrupt source on an INTMUX channel.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
* @param channel Index of the INTMUX channel on which the specified interrupt is disabled.
|
||||
* @param irq Interrupt number. The interrupt must be an INTMUX source.
|
||||
*/
|
||||
static inline void INTMUX_DisableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
|
||||
assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
|
||||
|
||||
base->CHANNEL[channel].CHn_IER_31_0 &= ~(1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/*! @name Status */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Gets INTMUX pending interrupt sources for a specific channel.
|
||||
*
|
||||
* @param base INTMUX peripheral base address.
|
||||
* @param channel The INTMUX channel number.
|
||||
* @return The mask of pending interrupt bits. Bit[n] set means INTMUX source n is pending.
|
||||
*/
|
||||
static inline uint32_t INTMUX_GetChannelPendingSources(INTMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
|
||||
|
||||
return base->CHANNEL[channel].CHn_IPR_31_0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_INTMUX_H_ */
|
|
@ -0,0 +1,853 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: fsl_lpuart
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#ifndef _FSL_LPUART_H_
|
||||
#define _FSL_LPUART_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup lpuart_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief LPUART driver version 2.2.3. */
|
||||
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 4))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Error codes for the LPUART driver. */
|
||||
enum _lpuart_status
|
||||
{
|
||||
kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
|
||||
kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
|
||||
kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
|
||||
kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
|
||||
kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */
|
||||
kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */
|
||||
kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
|
||||
kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
|
||||
kStatus_LPUART_RxRingBufferOverrun =
|
||||
MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
|
||||
kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
|
||||
kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
|
||||
kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
|
||||
kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
|
||||
kStatus_LPUART_BaudrateNotSupport =
|
||||
MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
|
||||
kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
|
||||
};
|
||||
|
||||
/*! @brief LPUART parity mode. */
|
||||
typedef enum _lpuart_parity_mode
|
||||
{
|
||||
kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
|
||||
kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
|
||||
} lpuart_parity_mode_t;
|
||||
|
||||
/*! @brief LPUART data bits count. */
|
||||
typedef enum _lpuart_data_bits
|
||||
{
|
||||
kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
|
||||
#endif
|
||||
} lpuart_data_bits_t;
|
||||
|
||||
/*! @brief LPUART stop bit count. */
|
||||
typedef enum _lpuart_stop_bit_count
|
||||
{
|
||||
kLPUART_OneStopBit = 0U, /*!< One stop bit */
|
||||
kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
|
||||
} lpuart_stop_bit_count_t;
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
|
||||
/*! @brief LPUART transmit CTS source. */
|
||||
typedef enum _lpuart_transmit_cts_source
|
||||
{
|
||||
kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */
|
||||
kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
|
||||
} lpuart_transmit_cts_source_t;
|
||||
|
||||
/*! @brief LPUART transmit CTS configure. */
|
||||
typedef enum _lpuart_transmit_cts_config
|
||||
{
|
||||
kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
|
||||
kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */
|
||||
} lpuart_transmit_cts_config_t;
|
||||
#endif
|
||||
|
||||
/*! @brief LPUART idle flag type defines when the receiver starts counting. */
|
||||
typedef enum _lpuart_idle_type_select
|
||||
{
|
||||
kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
|
||||
kLPUART_IdleTypeStopBit = 1U, /*!< Start conuting after a stop bit. */
|
||||
} lpuart_idle_type_select_t;
|
||||
|
||||
/*! @brief LPUART idle detected configuration.
|
||||
* This structure defines the number of idle characters that must be received before
|
||||
* the IDLE flag is set.
|
||||
*/
|
||||
typedef enum _lpuart_idle_config
|
||||
{
|
||||
kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
|
||||
} lpuart_idle_config_t;
|
||||
|
||||
/*!
|
||||
* @brief LPUART interrupt configuration structure, default settings all disabled.
|
||||
*
|
||||
* This structure contains the settings for all LPUART interrupt configurations.
|
||||
*/
|
||||
enum _lpuart_interrupt_enable
|
||||
{
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
|
||||
kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
|
||||
#endif
|
||||
kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
|
||||
kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */
|
||||
kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
|
||||
kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */
|
||||
kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */
|
||||
kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */
|
||||
kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */
|
||||
kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */
|
||||
kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
||||
kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */
|
||||
kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief LPUART status flags.
|
||||
*
|
||||
* This provides constants for the LPUART status flags for use in the LPUART functions.
|
||||
*/
|
||||
enum _lpuart_flags
|
||||
{
|
||||
kLPUART_TxDataRegEmptyFlag =
|
||||
(LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
|
||||
kLPUART_TransmissionCompleteFlag =
|
||||
(LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
|
||||
kLPUART_RxDataRegFullFlag =
|
||||
(LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
|
||||
kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
|
||||
kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is
|
||||
read from receive register */
|
||||
kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these
|
||||
samples differ, noise flag sets */
|
||||
kLPUART_FramingErrorFlag =
|
||||
(LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
|
||||
kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
|
||||
kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
|
||||
detected and LIN circuit enabled */
|
||||
#endif
|
||||
kLPUART_RxActiveEdgeFlag =
|
||||
(LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
|
||||
kLPUART_RxActiveFlag =
|
||||
(LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
|
||||
kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
|
||||
kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
|
||||
kLPUART_NoiseErrorInRxDataRegFlag =
|
||||
(LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
|
||||
kLPUART_ParityErrorInRxDataRegFlag =
|
||||
(LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
||||
kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
|
||||
kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
|
||||
kLPUART_TxFifoOverflowFlag =
|
||||
(LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
|
||||
kLPUART_RxFifoUnderflowFlag =
|
||||
(LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*! @brief LPUART configuration structure. */
|
||||
typedef struct _lpuart_config
|
||||
{
|
||||
uint32_t baudRate_Bps; /*!< LPUART baud rate */
|
||||
lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
|
||||
bool isMsb; /*!< Data bits order, LSB (default), MSB */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
|
||||
lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
||||
uint8_t txFifoWatermark; /*!< TX FIFO watermark */
|
||||
uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
|
||||
bool enableRxRTS; /*!< RX RTS enable */
|
||||
bool enableTxCTS; /*!< TX CTS enable */
|
||||
lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
|
||||
lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
|
||||
#endif
|
||||
lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */
|
||||
lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */
|
||||
bool enableTx; /*!< Enable TX */
|
||||
bool enableRx; /*!< Enable RX */
|
||||
} lpuart_config_t;
|
||||
|
||||
/*! @brief LPUART transfer structure. */
|
||||
typedef struct _lpuart_transfer
|
||||
{
|
||||
uint8_t *data; /*!< The buffer of data to be transfer.*/
|
||||
size_t dataSize; /*!< The byte count to be transfer. */
|
||||
} lpuart_transfer_t;
|
||||
|
||||
/* Forward declaration of the handle typedef. */
|
||||
typedef struct _lpuart_handle lpuart_handle_t;
|
||||
|
||||
/*! @brief LPUART transfer callback function. */
|
||||
typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief LPUART handle structure. */
|
||||
struct _lpuart_handle
|
||||
{
|
||||
uint8_t *volatile txData; /*!< Address of remaining data to send. */
|
||||
volatile size_t txDataSize; /*!< Size of the remaining data to send. */
|
||||
size_t txDataSizeAll; /*!< Size of the data to send out. */
|
||||
uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
|
||||
volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
|
||||
size_t rxDataSizeAll; /*!< Size of the data to receive. */
|
||||
|
||||
uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
|
||||
size_t rxRingBufferSize; /*!< Size of the ring buffer. */
|
||||
volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
|
||||
volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
|
||||
|
||||
lpuart_transfer_callback_t callback; /*!< Callback function. */
|
||||
void *userData; /*!< LPUART callback function parameter.*/
|
||||
|
||||
volatile uint8_t txState; /*!< TX transfer state. */
|
||||
volatile uint8_t rxState; /*!< RX transfer state. */
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
bool isSevenDataBits; /*!< Seven data bits flag. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
|
||||
|
||||
/*!
|
||||
* @name Software Reset
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Resets the LPUART using software.
|
||||
*
|
||||
* This function resets all internal logic and registers except the Global Register.
|
||||
* Remains set until cleared by software.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
*/
|
||||
static inline void LPUART_SoftwareReset(LPUART_Type *base)
|
||||
{
|
||||
base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
|
||||
base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
}
|
||||
/* @} */
|
||||
#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
|
||||
*
|
||||
* This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
|
||||
* to configure the configuration structure and get the default configuration.
|
||||
* The example below shows how to use this API to configure the LPUART.
|
||||
* @code
|
||||
* lpuart_config_t lpuartConfig;
|
||||
* lpuartConfig.baudRate_Bps = 115200U;
|
||||
* lpuartConfig.parityMode = kLPUART_ParityDisabled;
|
||||
* lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
|
||||
* lpuartConfig.isMsb = false;
|
||||
* lpuartConfig.stopBitCount = kLPUART_OneStopBit;
|
||||
* lpuartConfig.txFifoWatermark = 0;
|
||||
* lpuartConfig.rxFifoWatermark = 1;
|
||||
* LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param config Pointer to a user-defined configuration structure.
|
||||
* @param srcClock_Hz LPUART clock source frequency in HZ.
|
||||
* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
|
||||
* @retval kStatus_Success LPUART initialize succeed
|
||||
*/
|
||||
status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a LPUART instance.
|
||||
*
|
||||
* This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
*/
|
||||
void LPUART_Deinit(LPUART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets the default configuration structure.
|
||||
*
|
||||
* This function initializes the LPUART configuration structure to a default value. The default
|
||||
* values are:
|
||||
* lpuartConfig->baudRate_Bps = 115200U;
|
||||
* lpuartConfig->parityMode = kLPUART_ParityDisabled;
|
||||
* lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
|
||||
* lpuartConfig->isMsb = false;
|
||||
* lpuartConfig->stopBitCount = kLPUART_OneStopBit;
|
||||
* lpuartConfig->txFifoWatermark = 0;
|
||||
* lpuartConfig->rxFifoWatermark = 1;
|
||||
* lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
|
||||
* lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
|
||||
* lpuartConfig->enableTx = false;
|
||||
* lpuartConfig->enableRx = false;
|
||||
*
|
||||
* @param config Pointer to a configuration structure.
|
||||
*/
|
||||
void LPUART_GetDefaultConfig(lpuart_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Sets the LPUART instance baudrate.
|
||||
*
|
||||
* This function configures the LPUART module baudrate. This function is used to update
|
||||
* the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
|
||||
* @code
|
||||
* LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param baudRate_Bps LPUART baudrate to be set.
|
||||
* @param srcClock_Hz LPUART clock source frequency in HZ.
|
||||
* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
|
||||
* @retval kStatus_Success Set baudrate succeeded.
|
||||
*/
|
||||
status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets LPUART status flags.
|
||||
*
|
||||
* This function gets all LPUART status flags. The flags are returned as the logical
|
||||
* OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
|
||||
* compare the return value with enumerators in the @ref _lpuart_flags.
|
||||
* For example, to check whether the TX is empty:
|
||||
* @code
|
||||
* if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
|
||||
* {
|
||||
* ...
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
|
||||
*/
|
||||
uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clears status flags with a provided mask.
|
||||
*
|
||||
* This function clears LPUART status flags with a provided mask. Automatically cleared flags
|
||||
* can't be cleared by this function.
|
||||
* Flags that can only cleared or set by hardware are:
|
||||
* kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
|
||||
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
|
||||
* kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
|
||||
* Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param mask the status flags to be cleared. The user can use the enumerators in the
|
||||
* _lpuart_status_flag_t to do the OR operation and get the mask.
|
||||
* @return 0 succeed, others failed.
|
||||
* @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
|
||||
* it is cleared automatically by hardware.
|
||||
* @retval kStatus_Success Status in the mask are cleared.
|
||||
*/
|
||||
status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables LPUART interrupts according to a provided mask.
|
||||
*
|
||||
* This function enables the LPUART interrupts according to a provided mask. The mask
|
||||
* is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
|
||||
* This examples shows how to enable TX empty interrupt and RX full interrupt:
|
||||
* @code
|
||||
* LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
|
||||
*/
|
||||
void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Disables LPUART interrupts according to a provided mask.
|
||||
*
|
||||
* This function disables the LPUART interrupts according to a provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
|
||||
* This example shows how to disable the TX empty interrupt and RX full interrupt:
|
||||
* @code
|
||||
* LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
|
||||
*/
|
||||
void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Gets enabled LPUART interrupts.
|
||||
*
|
||||
* This function gets the enabled LPUART interrupts. The enabled interrupts are returned
|
||||
* as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
|
||||
* a specific interrupt enable status, compare the return value with enumerators
|
||||
* in @ref _lpuart_interrupt_enable.
|
||||
* For example, to check whether the TX empty interrupt is enabled:
|
||||
* @code
|
||||
* uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
|
||||
*
|
||||
* if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
|
||||
* {
|
||||
* ...
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
|
||||
*/
|
||||
uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
|
||||
/*!
|
||||
* @brief Gets the LPUART data register address.
|
||||
*
|
||||
* This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART data register addresses which are used both by the transmitter and receiver.
|
||||
*/
|
||||
static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
|
||||
{
|
||||
return (uint32_t) & (base->DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART transmitter DMA request.
|
||||
*
|
||||
* This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BAUD |= LPUART_BAUD_TDMAE_MASK;
|
||||
base->CTRL |= LPUART_CTRL_TIE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
|
||||
base->CTRL &= ~LPUART_CTRL_TIE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART receiver DMA.
|
||||
*
|
||||
* This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BAUD |= LPUART_BAUD_RDMAE_MASK;
|
||||
base->CTRL |= LPUART_CTRL_RIE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
|
||||
base->CTRL &= ~LPUART_CTRL_RIE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/* @} */
|
||||
#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
|
||||
|
||||
/*!
|
||||
* @name Bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART transmitter.
|
||||
*
|
||||
* This function enables or disables the LPUART transmitter.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= LPUART_CTRL_TE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~LPUART_CTRL_TE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART receiver.
|
||||
*
|
||||
* This function enables or disables the LPUART receiver.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Writes to the transmitter register.
|
||||
*
|
||||
* This function writes data to the transmitter register directly. The upper layer must
|
||||
* ensure that the TX register is empty or that the TX FIFO has room before calling this function.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param data Data write to the TX register.
|
||||
*/
|
||||
static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
|
||||
{
|
||||
base->DATA = data;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the receiver register.
|
||||
*
|
||||
* This function reads data from the receiver register directly. The upper layer must
|
||||
* ensure that the receiver register is full or that the RX FIFO has data before calling this function.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return Data read from data register.
|
||||
*/
|
||||
static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
|
||||
{
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
uint32_t ctrl = base->CTRL;
|
||||
bool isSevenDataBits =
|
||||
((ctrl & LPUART_CTRL_M7_MASK) ||
|
||||
((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
|
||||
|
||||
if (isSevenDataBits)
|
||||
{
|
||||
return (base->DATA & 0x7F);
|
||||
}
|
||||
else
|
||||
{
|
||||
return base->DATA;
|
||||
}
|
||||
#else
|
||||
return base->DATA;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Writes to the transmitter register using a blocking method.
|
||||
*
|
||||
* This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have
|
||||
* room, and writes data to the transmitter buffer.
|
||||
*
|
||||
* @note This function does not check whether all data has been sent out to the bus.
|
||||
* Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
|
||||
* finished.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
*/
|
||||
void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads the receiver data register using a blocking method.
|
||||
*
|
||||
* This function polls the receiver register, waits for the receiver register full or receiver FIFO
|
||||
* has data, and reads data from the TX register.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
|
||||
* @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
|
||||
* @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
|
||||
* @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
|
||||
* @retval kStatus_Success Successfully received all data.
|
||||
*/
|
||||
status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the LPUART handle.
|
||||
*
|
||||
* This function initializes the LPUART handle, which can be used for other LPUART
|
||||
* transactional APIs. Usually, for a specified LPUART instance,
|
||||
* call this API once to get the initialized handle.
|
||||
*
|
||||
* The LPUART driver supports the "background" receiving, which means that user can set up
|
||||
* an RX ring buffer optionally. Data received is stored into the ring buffer even when the
|
||||
* user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
|
||||
* in the ring buffer, the user can get the received data from the ring buffer directly.
|
||||
* The ring buffer is disabled if passing NULL as @p ringBuffer.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param callback Callback function.
|
||||
* @param userData User data.
|
||||
*/
|
||||
void LPUART_TransferCreateHandle(LPUART_Type *base,
|
||||
lpuart_handle_t *handle,
|
||||
lpuart_transfer_callback_t callback,
|
||||
void *userData);
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function send data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data written to the transmitter register. When
|
||||
* all data is written to the TX register in the ISR, the LPUART driver calls the callback
|
||||
* function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
|
||||
*
|
||||
* @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
|
||||
* to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
|
||||
* check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param xfer LPUART transfer structure, see #lpuart_transfer_t.
|
||||
* @retval kStatus_Success Successfully start the data transmission.
|
||||
* @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Sets up the RX ring buffer.
|
||||
*
|
||||
* This function sets up the RX ring buffer to a specific UART handle.
|
||||
*
|
||||
* When the RX ring buffer is used, data received is stored into the ring buffer even when
|
||||
* the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
|
||||
* in the ring buffer, the user can get the received data from the ring buffer directly.
|
||||
*
|
||||
* @note When using RX ring buffer, one byte is reserved for internal use. In other
|
||||
* words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
|
||||
* @param ringBufferSize size of the ring buffer.
|
||||
*/
|
||||
void LPUART_TransferStartRingBuffer(LPUART_Type *base,
|
||||
lpuart_handle_t *handle,
|
||||
uint8_t *ringBuffer,
|
||||
size_t ringBufferSize);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the background transfer and uninstalls the ring buffer.
|
||||
*
|
||||
* This function aborts the background transfer and uninstalls the ring buffer.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data transmit.
|
||||
*
|
||||
* This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
|
||||
* how many bytes are not sent out.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been written to the LPUART transmitter register.
|
||||
*
|
||||
* This function gets the number of bytes that have been written to LPUART TX
|
||||
* register by an interrupt method.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param count Send bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No send in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function
|
||||
* which returns without waiting to ensure that all data are received.
|
||||
* If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
|
||||
* the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
|
||||
* After copying, if the data in the ring buffer is not enough for read, the receive
|
||||
* request is saved by the LPUART driver. When the new data arrives, the receive request
|
||||
* is serviced first. When all data is received, the LPUART driver notifies the upper layer
|
||||
* through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
|
||||
* For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
|
||||
* The 5 bytes are copied to xfer->data, which returns with the
|
||||
* parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
|
||||
* saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
|
||||
* If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
|
||||
* to receive data to xfer->data. When all data is received, the upper layer is notified.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param xfer LPUART transfer structure, see #uart_transfer_t.
|
||||
* @param receivedBytes Bytes received from the ring buffer directly.
|
||||
* @retval kStatus_Success Successfully queue the transfer into the transmit queue.
|
||||
* @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
|
||||
lpuart_handle_t *handle,
|
||||
lpuart_transfer_t *xfer,
|
||||
size_t *receivedBytes);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
|
||||
* how many bytes not received yet.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param count Receive bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No receive in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief LPUART IRQ handle function.
|
||||
*
|
||||
* This function handles the LPUART transmit and receive IRQ request.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief LPUART Error IRQ handle function.
|
||||
*
|
||||
* This function handles the LPUART error IRQ request.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_LPUART_H_ */
|
|
@ -0,0 +1,712 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: fsl_msmc
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
#ifndef _FSL_MSMC_H_
|
||||
#define _FSL_MSMC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @addtogroup msmc */
|
||||
/*! @{*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief MSMC driver version 2.1.0. */
|
||||
#define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Power Modes Protection
|
||||
*/
|
||||
typedef enum _smc_power_mode_protection
|
||||
{
|
||||
kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
|
||||
kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */
|
||||
kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */
|
||||
kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */
|
||||
kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK |
|
||||
SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode. */
|
||||
} smc_power_mode_protection_t;
|
||||
|
||||
/*!
|
||||
* @brief Power Modes in PMSTAT
|
||||
*/
|
||||
typedef enum _smc_power_state
|
||||
{
|
||||
kSMC_PowerStateRun = 1U, /*!< 0000_0001 - Current power mode is RUN */
|
||||
kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode */
|
||||
kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR */
|
||||
kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
|
||||
} smc_power_state_t;
|
||||
|
||||
/*!
|
||||
* @brief Power Stop Entry Status in PMSTAT
|
||||
*/
|
||||
typedef enum _smc_power_stop_entry_status
|
||||
{
|
||||
kSMC_PowerStopEntryAlt0 = 1U, /*!< Indicates a Stop mode entry since this field was last cleared. */
|
||||
kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */
|
||||
kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */
|
||||
kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */
|
||||
kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */
|
||||
kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */
|
||||
} smc_power_stop_entry_status_t;
|
||||
|
||||
/*!
|
||||
* @brief Run mode definition
|
||||
*/
|
||||
typedef enum _smc_run_mode
|
||||
{
|
||||
kSMC_RunNormal = 0U, /*!< normal RUN mode. */
|
||||
kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */
|
||||
kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
|
||||
} smc_run_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Stop mode definition
|
||||
*/
|
||||
typedef enum _smc_stop_mode
|
||||
{
|
||||
kSMC_StopNormal = 0U, /*!< Normal STOP mode. */
|
||||
kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */
|
||||
kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
|
||||
kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
|
||||
kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
|
||||
#else
|
||||
kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
|
||||
} smc_stop_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Partial STOP option
|
||||
*/
|
||||
typedef enum _smc_partial_stop_mode
|
||||
{
|
||||
kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/
|
||||
kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
|
||||
kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
|
||||
kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/
|
||||
} smc_partial_stop_option_t;
|
||||
|
||||
/*!
|
||||
* @brief SMC configuration status
|
||||
*/
|
||||
enum _smc_status
|
||||
{
|
||||
kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief System Reset Source Name definitions
|
||||
*/
|
||||
typedef enum _smc_reset_source
|
||||
{
|
||||
kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */
|
||||
kSMC_SourcePor = SMC_SRS_POR_MASK, /*!< Power on reset */
|
||||
kSMC_SourceLvd = SMC_SRS_LVD_MASK, /*!< Low-voltage detect reset */
|
||||
kSMC_SourceHvd = SMC_SRS_HVD_MASK, /*!< High-voltage detect reset */
|
||||
kSMC_SourceWarm = SMC_SRS_WARM_MASK, /*!< Warm reset. Warm Reset flag will assert if any of the system reset
|
||||
sources in this register assert (SRS[31:8]) */
|
||||
kSMC_SourceFatal = SMC_SRS_FATAL_MASK, /*!< Fatal reset */
|
||||
kSMC_SourceCore =
|
||||
SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */
|
||||
kSMC_SourcePin = SMC_SRS_PIN_MASK, /*!< RESET_B pin reset. */
|
||||
kSMC_SourceMdm = SMC_SRS_MDM_MASK, /*!< MDM reset. */
|
||||
kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK, /*!< Reset Controller timeout reset. */
|
||||
kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */
|
||||
kSMC_SourceScg = SMC_SRS_SCG_MASK, /*!< SCG loss of lock or loss of clock */
|
||||
kSMC_SourceWdog = SMC_SRS_WDOG_MASK, /*!< Watchdog reset */
|
||||
kSMC_SourceSoftware = SMC_SRS_SW_MASK, /*!< Software reset */
|
||||
kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK, /*!< Lockup reset. Core lockup or exception. */
|
||||
kSMC_SourceJtag = SMC_SRS_JTAG_MASK, /*!< JTAG system reset */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
|
||||
kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
|
||||
kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
|
||||
kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
|
||||
kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
|
||||
/* Source All. */
|
||||
kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK |
|
||||
SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK |
|
||||
SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
|
||||
SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
|
||||
|
|
||||
SMC_SRS_SECVIO_MASK
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
|
||||
|
|
||||
SMC_SRS_TAMPER_MASK
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
|
||||
|
|
||||
SMC_SRS_CORE0_MASK
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
|
||||
|
|
||||
SMC_SRS_CORE1_MASK
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
|
||||
,
|
||||
} smc_reset_source_t;
|
||||
|
||||
/*!
|
||||
* @brief System reset interrupt enable bit definitions.
|
||||
*/
|
||||
typedef enum _smc_interrupt_enable
|
||||
{
|
||||
kSMC_IntNone = 0U, /*!< No interrupt enabled. */
|
||||
kSMC_IntPin = SMC_SRIE_PIN_MASK, /*!< Pin reset interrupt. */
|
||||
kSMC_IntMdm = SMC_SRIE_MDM_MASK, /*!< MDM reset interrupt. */
|
||||
kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt. */
|
||||
kSMC_IntWdog = SMC_SRIE_WDOG_MASK, /*!< Watchdog interrupt. */
|
||||
kSMC_IntSoftware = SMC_SRIE_SW_MASK, /*!< Software reset interrupts. */
|
||||
kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK, /*!< Lock up interrupt. */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
|
||||
kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
|
||||
kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
|
||||
kSMC_IntAll = SMC_SRIE_PIN_MASK | /*!< All system reset interrupts. */
|
||||
SMC_SRIE_MDM_MASK |
|
||||
SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK | SMC_SRIE_LOCKUP_MASK
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
|
||||
|
|
||||
SMC_SRIE_CORE0_MASK
|
||||
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
|
||||
|
|
||||
SMC_SRIE_CORE1_MASK
|
||||
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
|
||||
} smc_interrupt_enable_t;
|
||||
|
||||
/*!
|
||||
* @brief Reset pin filter configuration
|
||||
*/
|
||||
typedef struct _smc_reset_pin_filter_config
|
||||
{
|
||||
uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles. */
|
||||
bool enableFilter; /*!< Reset pin filter enable/disable. */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
|
||||
bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */
|
||||
#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
|
||||
} smc_reset_pin_filter_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*! @name System mode controller APIs*/
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Configures all power mode protection settings.
|
||||
*
|
||||
* This function configures the power mode protection settings for
|
||||
* supported power modes in the specified chip family. The available power modes
|
||||
* are defined in the smc_power_mode_protection_t. This should be done at an early
|
||||
* system level initialization stage. See the reference manual for details.
|
||||
* This register can only write once after the power reset.
|
||||
*
|
||||
* The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
|
||||
* use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls).
|
||||
* To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
|
||||
*
|
||||
* @param allowedModes Bitmap of the allowed power modes.
|
||||
*/
|
||||
static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
|
||||
{
|
||||
base->PMPROT = allowedModes;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the current power mode status.
|
||||
*
|
||||
* This function returns the current power mode stat. Once application
|
||||
* switches the power mode, it should always check the stat to check whether it
|
||||
* runs into the specified mode or not. An application should check
|
||||
* this mode before switching to a different mode. The system requires that
|
||||
* only certain modes can switch to other specific modes. See the
|
||||
* reference manual for details and the smc_power_state_t for information about
|
||||
* the power stat.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return Current power mode status.
|
||||
*/
|
||||
static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
|
||||
{
|
||||
return (smc_power_state_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT);
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT)
|
||||
/*!
|
||||
* @brief Gets the result of the previous stop mode entry.
|
||||
*
|
||||
* This function returns the result of the previous stop mode entry.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return Current power stop entry status.
|
||||
*/
|
||||
static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base)
|
||||
{
|
||||
return (smc_power_stop_entry_status_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >> SMC_PMSTAT_STOPSTAT_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears all the result of the previous stop mode entry.
|
||||
*
|
||||
* This function clears all the result of the previous stop mode entry.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return Current power stop entry status.
|
||||
*/
|
||||
static inline void SMC_ClearStopEntryStatus(SMC_Type *base)
|
||||
{
|
||||
/* Only write 0x01 to clear this field, all other writes are ignored. */
|
||||
base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01);
|
||||
}
|
||||
|
||||
#endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */
|
||||
|
||||
/*!
|
||||
* @brief Prepare to enter stop modes
|
||||
*
|
||||
* This function should be called before entering STOP/VLPS/LLS/VLLS modes.
|
||||
*/
|
||||
static inline void SMC_PreEnterStopModes(void)
|
||||
{
|
||||
__disable_irq();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Recovering after wake up from stop modes
|
||||
*
|
||||
* This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
|
||||
* It is used together with @ref SMC_PreEnterStopModes.
|
||||
*/
|
||||
static inline void SMC_PostExitStopModes(void)
|
||||
{
|
||||
__enable_irq();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Prepare to enter wait modes
|
||||
*
|
||||
* This function should be called before entering WAIT/VLPW modes..
|
||||
*/
|
||||
static inline void SMC_PreEnterWaitModes(void)
|
||||
{
|
||||
__disable_irq();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Recovering after wake up from stop modes
|
||||
*
|
||||
* This function should be called after wake up from WAIT/VLPW modes.
|
||||
* It is used together with @ref SMC_PreEnterWaitModes.
|
||||
*/
|
||||
static inline void SMC_PostExitWaitModes(void)
|
||||
{
|
||||
__enable_irq();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to RUN power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeRun(SMC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to HSRUN power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeHsrun(SMC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to WAIT power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeWait(SMC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to Stop power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param option Partial Stop mode option.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to VLPR power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeVlpr(SMC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to VLPW power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeVlpw(SMC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configure the system to VLPS power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeVlps(SMC_Type *base);
|
||||
/*!
|
||||
* @brief Configure the system to LLS power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeLls(SMC_Type *base);
|
||||
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
|
||||
/*!
|
||||
* @brief Configure the system to VLLS0 power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeVlls0(SMC_Type *base);
|
||||
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
|
||||
/*!
|
||||
* @brief Configure the system to VLLS2 power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeVlls2(SMC_Type *base);
|
||||
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
|
||||
#else
|
||||
/*!
|
||||
* @brief Configure the system to VLLS power mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return SMC configuration error code.
|
||||
*/
|
||||
status_t SMC_SetPowerModeVlls(SMC_Type *base);
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
|
||||
|
||||
/*!
|
||||
* @brief Gets the reset source status which caused a previous reset.
|
||||
*
|
||||
* This function gets the current reset source status. Use source masks
|
||||
* defined in the smc_reset_source_t to get the desired source status.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
uint32_t resetStatus;
|
||||
|
||||
// To get all reset source statuses.
|
||||
resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll;
|
||||
|
||||
// To test whether the MCU is reset using Watchdog.
|
||||
resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog;
|
||||
|
||||
// To test multiple reset sources.
|
||||
resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
|
||||
@endcode
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return All reset source status bit map.
|
||||
*/
|
||||
static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base)
|
||||
{
|
||||
return base->SRS;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the sticky reset source status.
|
||||
*
|
||||
* This function gets the current reset source status that has not been cleared
|
||||
* by software for some specific source.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
uint32_t resetStatus;
|
||||
|
||||
// To get all reset source statuses.
|
||||
resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll;
|
||||
|
||||
// To test whether the MCU is reset using Watchdog.
|
||||
resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog;
|
||||
|
||||
// To test multiple reset sources.
|
||||
resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
|
||||
@endcode
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return All reset source status bit map.
|
||||
*/
|
||||
static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base)
|
||||
{
|
||||
return base->SSRS;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the sticky reset source status.
|
||||
*
|
||||
* This function clears the sticky system reset flags indicated by source masks.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
// Clears multiple reset sources.
|
||||
SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin));
|
||||
@endcode
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param sourceMasks reset source status bit map
|
||||
*/
|
||||
static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks)
|
||||
{
|
||||
base->SSRS = sourceMasks;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configures the reset pin filter.
|
||||
*
|
||||
* This function sets the reset pin filter including the enablement/disablement and filter width.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Sets the system reset interrupt configuration.
|
||||
*
|
||||
* For a graceful shut down, the MSMC supports delaying the assertion of the system
|
||||
* reset for a period of time when the reset interrupt is generated. This function
|
||||
* can be used to enable the interrupt.
|
||||
* The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
|
||||
* For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows:
|
||||
* SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param intMask Bit mask of the system reset interrupts to enable. See
|
||||
* smc_interrupt_enable_t for details.
|
||||
*/
|
||||
static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask)
|
||||
{
|
||||
base->SRIE = intMask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the source status of the system reset interrupt.
|
||||
*
|
||||
* This function gets the source status of the reset interrupt. Use source masks
|
||||
* defined in the smc_interrupt_enable_t to get the desired source status.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
uint32_t interruptStatus;
|
||||
|
||||
// To get all reset interrupt source statuses.
|
||||
interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll;
|
||||
|
||||
// To test whether the reset interrupt of Watchdog is pending.
|
||||
interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog;
|
||||
|
||||
// To test multiple reset interrupt sources.
|
||||
interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin);
|
||||
@endcode
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return All reset interrupt source status bit map.
|
||||
*/
|
||||
static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base)
|
||||
{
|
||||
return base->SRIF;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the source status of the system reset interrupt.
|
||||
*
|
||||
* This function clears the source status of the reset interrupt. Use source masks
|
||||
* defined in the smc_interrupt_enable_t to get the desired source status.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
uint32_t interruptStatus;
|
||||
|
||||
// To clear all reset interrupt source statuses.
|
||||
MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll);
|
||||
|
||||
// To clear the reset interrupt of Watchdog.
|
||||
SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog);
|
||||
|
||||
// To clear multiple reset interrupt sources status.
|
||||
SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin));
|
||||
@endcode
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param All reset interrupt source status bit map to clear.
|
||||
*/
|
||||
static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask)
|
||||
{
|
||||
base->SRIF = intMask;
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE)
|
||||
/*!
|
||||
* @brief Sets the core software reset feature configuration.
|
||||
*
|
||||
* The MSMC supports delaying the assertion of the system reset for a period of time while a core
|
||||
* software reset is generated. This allows software to recover without reseting the entire system.
|
||||
* This function can be used to enable/disable the core software reset feature.
|
||||
* The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
|
||||
* For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows:
|
||||
* SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param intMask Bit mask of the core software reset to enable. See
|
||||
* smc_interrupt_enable_t for details.
|
||||
*/
|
||||
static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask)
|
||||
{
|
||||
base->CSRE = intMask;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SMC_HAS_CSRE */
|
||||
|
||||
/*!
|
||||
* @brief Gets the boot option configuration.
|
||||
*
|
||||
* This function gets the boot option configuration of MSMC.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @return The boot option configuration. 1 means boot option enabled. 0 means not.
|
||||
*/
|
||||
static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base)
|
||||
{
|
||||
return base->MR;
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM)
|
||||
/*!
|
||||
* @brief Sets the force boot option configuration.
|
||||
*
|
||||
* This function sets the focus boot option configuration of MSMC. It can force the corresponding
|
||||
* boot option config to assert on next system reset.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not.
|
||||
*/
|
||||
static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val)
|
||||
{
|
||||
base->FM = val;
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR)
|
||||
/*!
|
||||
* @brief Enables the conresponding SRAM array in low power retention mode.
|
||||
*
|
||||
* This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is
|
||||
* disabled, and only in RUN mode.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param arrayIdx Index of responding SRAM array.
|
||||
* @param enable Enable the SRAM array in low power retention mode.
|
||||
*/
|
||||
static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */
|
||||
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR)
|
||||
/*!
|
||||
* @brief Enables the conresponding SRAM array in STOP mode.
|
||||
*
|
||||
* This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes.
|
||||
* When disabled, the corresponding SRAM array is powered off in STOP modes.
|
||||
*
|
||||
* @param base SMC peripheral base address.
|
||||
* @param arrayIdx Index of responding SRAM array.
|
||||
* @param enable Enable the SRAM array in STOP modes.
|
||||
*/
|
||||
static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */
|
||||
|
||||
#endif /* FSL_FEATURE_SMC_HAS_FM */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_MSMC_H_ */
|
|
@ -0,0 +1,476 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: fsl_port
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#ifndef _FSL_PORT_H_
|
||||
#define _FSL_PORT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup port
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! Version 2.0.2. */
|
||||
#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
|
||||
/*! @brief Internal resistor pull feature selection */
|
||||
enum _port_pull
|
||||
{
|
||||
kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
|
||||
kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
|
||||
kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
|
||||
/*! @brief Slew rate selection */
|
||||
enum _port_slew_rate
|
||||
{
|
||||
kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
|
||||
kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
|
||||
/*! @brief Open Drain feature enable/disable */
|
||||
enum _port_open_drain_enable
|
||||
{
|
||||
kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
|
||||
kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
|
||||
/*! @brief Passive filter feature enable/disable */
|
||||
enum _port_passive_filter_enable
|
||||
{
|
||||
kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
|
||||
kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
/*! @brief Configures the drive strength. */
|
||||
enum _port_drive_strength
|
||||
{
|
||||
kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
|
||||
kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
|
||||
/*! @brief Unlock/lock the pin control register field[15:0] */
|
||||
enum _port_lock_register
|
||||
{
|
||||
kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
|
||||
kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @brief Pin mux selection */
|
||||
typedef enum _port_mux
|
||||
{
|
||||
kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
|
||||
kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
|
||||
kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
|
||||
} port_mux_t;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
/*! @brief Configures the interrupt generation condition. */
|
||||
typedef enum _port_interrupt
|
||||
{
|
||||
kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
|
||||
kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
|
||||
kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
|
||||
kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
|
||||
kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
|
||||
kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
|
||||
kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
|
||||
#endif
|
||||
kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
|
||||
kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
|
||||
kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
|
||||
kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
|
||||
kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
|
||||
#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
|
||||
kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
|
||||
kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
|
||||
#endif
|
||||
} port_interrupt_t;
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
|
||||
/*! @brief Digital filter clock source selection */
|
||||
typedef enum _port_digital_filter_clock_source
|
||||
{
|
||||
kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
|
||||
kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
|
||||
} port_digital_filter_clock_source_t;
|
||||
|
||||
/*! @brief PORT digital filter feature configuration definition */
|
||||
typedef struct _port_digital_filter_config
|
||||
{
|
||||
uint32_t digitalFilterWidth; /*!< Set digital filter width */
|
||||
port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
|
||||
} port_digital_filter_config_t;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @brief PORT pin configuration structure */
|
||||
typedef struct _port_pin_config
|
||||
{
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
|
||||
uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
|
||||
#else
|
||||
uint16_t : 2;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
|
||||
uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
|
||||
|
||||
uint16_t : 1;
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
|
||||
uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
|
||||
uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif
|
||||
|
||||
uint16_t : 1;
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
|
||||
uint16_t mux : 3; /*!< Pin mux Configure */
|
||||
uint16_t : 4;
|
||||
#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
|
||||
uint16_t mux : 4; /*!< Pin mux Configure */
|
||||
uint16_t : 3;
|
||||
#else
|
||||
uint16_t : 7,
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
|
||||
uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
|
||||
} port_pin_config_t;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @name Configuration */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the port PCR register.
|
||||
*
|
||||
* This is an example to define an input pin or output pin PCR configuration.
|
||||
* @code
|
||||
* // Define a digital input pin PCR configuration
|
||||
* port_pin_config_t config = {
|
||||
* kPORT_PullUp,
|
||||
* kPORT_FastSlewRate,
|
||||
* kPORT_PassiveFilterDisable,
|
||||
* kPORT_OpenDrainDisable,
|
||||
* kPORT_LowDriveStrength,
|
||||
* kPORT_MuxAsGpio,
|
||||
* kPORT_UnLockRegister,
|
||||
* };
|
||||
* @endcode
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT PCR register configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint32_t addr = (uint32_t)&base->PCR[pin];
|
||||
*(volatile uint16_t *)(addr) = *((const uint16_t *)config);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the port PCR register for multiple pins.
|
||||
*
|
||||
* This is an example to define input pins or output pins PCR configuration.
|
||||
* @code
|
||||
* // Define a digital input pin PCR configuration
|
||||
* port_pin_config_t config = {
|
||||
* kPORT_PullUp ,
|
||||
* kPORT_PullEnable,
|
||||
* kPORT_FastSlewRate,
|
||||
* kPORT_PassiveFilterDisable,
|
||||
* kPORT_OpenDrainDisable,
|
||||
* kPORT_LowDriveStrength,
|
||||
* kPORT_MuxAsGpio,
|
||||
* kPORT_UnlockRegister,
|
||||
* };
|
||||
* @endcode
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param config PORT PCR register configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
uint16_t pcrl = *((const uint16_t *)config);
|
||||
|
||||
if (mask & 0xffffU)
|
||||
{
|
||||
base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
|
||||
}
|
||||
if (mask >> 16)
|
||||
{
|
||||
base->GPCHR = (mask & 0xffff0000U) | pcrl;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
|
||||
/*!
|
||||
* @brief Sets the port interrupt configuration in PCR register for multiple pins.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param config PORT pin interrupt configuration.
|
||||
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
|
||||
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
|
||||
*/
|
||||
static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
if (mask & 0xffffU)
|
||||
{
|
||||
base->GICLR = (config << 16) | (mask & 0xffffU);
|
||||
}
|
||||
if (mask >> 16)
|
||||
{
|
||||
base->GICHR = (config << 16) | (mask & 0xffff0000U);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Configures the pin muxing.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param mux pin muxing slot selection.
|
||||
* - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
|
||||
* - #kPORT_MuxAsGpio : Set as GPIO.
|
||||
* - #kPORT_MuxAlt2 : chip-specific.
|
||||
* - #kPORT_MuxAlt3 : chip-specific.
|
||||
* - #kPORT_MuxAlt4 : chip-specific.
|
||||
* - #kPORT_MuxAlt5 : chip-specific.
|
||||
* - #kPORT_MuxAlt6 : chip-specific.
|
||||
* - #kPORT_MuxAlt7 : chip-specific.
|
||||
* @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
|
||||
* the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
|
||||
* reset to zero : kPORT_PinDisabledOrAnalog).
|
||||
* This function is recommended to use to reset the pin mux
|
||||
*
|
||||
*/
|
||||
static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
|
||||
|
||||
/*!
|
||||
* @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
*/
|
||||
static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable == true)
|
||||
{
|
||||
base->DFER |= mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->DFER &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param config PORT digital filter configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
base->DFCR = PORT_DFCR_CS(config->clockSource);
|
||||
base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
|
||||
}
|
||||
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name Interrupt */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Configures the port pin interrupt/DMA request.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT pin interrupt configuration.
|
||||
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
|
||||
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
|
||||
*/
|
||||
static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
/*!
|
||||
* @brief Configures the port pin drive strength.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT pin drive strength
|
||||
* - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
|
||||
* - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
|
||||
*/
|
||||
static inline void PORT_SetPinDriveStrength(PORT_Type* base, uint32_t pin, uint8_t strength)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Reads the whole port status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @return Current port interrupt status flags, for example, 0x00010001 means the
|
||||
* pin 0 and 16 have the interrupt.
|
||||
*/
|
||||
static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
|
||||
{
|
||||
return base->ISFR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the multiple pin interrupt status flag.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
*/
|
||||
static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ISFR = mask;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_PORT_H_ */
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: pin_mux
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
|
@ -0,0 +1 @@
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := clock_config.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
|
@ -0,0 +1,447 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
|
||||
* Note: The clock could not be set when it is being used as system clock.
|
||||
* In default out of reset, the CPU is clocked from FIRC(IRC48M),
|
||||
* so before setting FIRC, change to use another avaliable clock source.
|
||||
*
|
||||
* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
|
||||
*
|
||||
* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
|
||||
* Wait until the system clock source is changed to target source.
|
||||
*
|
||||
* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
|
||||
* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
|
||||
* Supported run mode and clock restrictions could be found in Reference Manual.
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v3.0
|
||||
processor: RV32M1
|
||||
package_id: RV32M1
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.0
|
||||
board: RV32M1_VEGA
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*************************************************
|
||||
File name: clock_config
|
||||
Description:
|
||||
Others: take for references
|
||||
https://github.com/open-isa-org/open-isa.org
|
||||
History:
|
||||
1. Date: 2022-02-16
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
*************************************************/
|
||||
|
||||
#include "fsl_msmc.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
|
||||
#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_CONFIG_FircSafeConfig
|
||||
* Description : This function is used to safely configure FIRC clock.
|
||||
* In default out of reset, the CPU is clocked from FIRC(IRC48M).
|
||||
* Before setting FIRC, change to use SIRC as system clock,
|
||||
* then configure FIRC.
|
||||
* Param fircConfig : FIRC configuration.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
|
||||
{
|
||||
scg_sys_clk_config_t curConfig;
|
||||
const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
|
||||
.div1 = kSCG_AsyncClkDisable,
|
||||
.div2 = kSCG_AsyncClkDivBy2,
|
||||
.range = kSCG_SircRangeHigh};
|
||||
scg_sys_clk_config_t sysClkSafeConfigSource = {
|
||||
.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
|
||||
.divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
|
||||
.src = kSCG_SysClkSrcSirc /* System clock source. */
|
||||
};
|
||||
/* Init Sirc */
|
||||
CLOCK_InitSirc(&scgSircConfig);
|
||||
/* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
|
||||
CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
|
||||
/* Wait for clock source switch finished */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != sysClkSafeConfigSource.src);
|
||||
|
||||
/* Init Firc */
|
||||
CLOCK_InitFirc(fircConfig);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 48 MHz}
|
||||
- {id: Core_clock.outFreq, value: 48 MHz}
|
||||
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
|
||||
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
|
||||
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
|
||||
- {id: LPO_CLK.outFreq, value: 1 kHz}
|
||||
- {id: Platform_clock.outFreq, value: 48 MHz}
|
||||
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 24 MHz}
|
||||
- {id: System_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
|
||||
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
|
||||
- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
|
||||
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
|
||||
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
|
||||
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
|
||||
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
|
||||
.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
|
||||
};
|
||||
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.freq = 0U, /* System Oscillator frequency: 0Hz */
|
||||
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||||
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
|
||||
};
|
||||
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||||
};
|
||||
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
|
||||
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
scg_sys_clk_config_t curConfig;
|
||||
|
||||
/* Init FIRC */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
|
||||
/* Set SCG to FIRC mode. */
|
||||
CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
|
||||
/* Wait for clock source switch finished */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
|
||||
/* Init SIRC */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
|
||||
/* Init LPFLL */
|
||||
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockHSRUN
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 72 MHz}
|
||||
- {id: Core_clock.outFreq, value: 72 MHz}
|
||||
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
|
||||
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
|
||||
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
|
||||
- {id: LPO_CLK.outFreq, value: 1 kHz}
|
||||
- {id: Platform_clock.outFreq, value: 72 MHz}
|
||||
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 8 MHz}
|
||||
- {id: System_clock.outFreq, value: 72 MHz}
|
||||
settings:
|
||||
- {id: SCGMode, value: LPFLL}
|
||||
- {id: powerMode, value: HSRUN}
|
||||
- {id: SCG.DIVCORE.scale, value: '1', locked: true}
|
||||
- {id: SCG.DIVSLOW.scale, value: '9'}
|
||||
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
|
||||
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
|
||||
- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
|
||||
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.TRIMDIV.scale, value: '24'}
|
||||
- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
|
||||
- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
|
||||
- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
|
||||
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
|
||||
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
|
||||
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
|
||||
.src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
|
||||
};
|
||||
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.freq = 0U, /* System Oscillator frequency: 0Hz */
|
||||
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||||
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
|
||||
};
|
||||
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||||
};
|
||||
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
|
||||
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockHSRUN(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
scg_sys_clk_config_t curConfig;
|
||||
|
||||
/* Init FIRC */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
|
||||
/* Init LPFLL */
|
||||
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
|
||||
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
|
||||
/* Set HSRUN power mode */
|
||||
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeHsrun(SMC0);
|
||||
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
|
||||
{
|
||||
}
|
||||
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
|
||||
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeHsrun(SMC1);
|
||||
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
/* Set SCG to LPFLL mode. */
|
||||
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
|
||||
/* Wait for clock source switch finished */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
|
||||
/* Init SIRC */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 2 MHz}
|
||||
- {id: Core_clock.outFreq, value: 4 MHz}
|
||||
- {id: LPO_CLK.outFreq, value: 1 kHz}
|
||||
- {id: Platform_clock.outFreq, value: 4 MHz}
|
||||
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
|
||||
- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
|
||||
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 4000/9 kHz}
|
||||
- {id: System_clock.outFreq, value: 4 MHz}
|
||||
settings:
|
||||
- {id: SCGMode, value: SIRC}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: SCG.DIVBUS.scale, value: '2', locked: true}
|
||||
- {id: SCG.DIVCORE.scale, value: '2', locked: true}
|
||||
- {id: SCG.DIVSLOW.scale, value: '9'}
|
||||
- {id: SCG.FIRCDIV1.scale, value: '1'}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
|
||||
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
|
||||
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
|
||||
.divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
|
||||
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
|
||||
.divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
|
||||
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
|
||||
};
|
||||
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* System Oscillator frequency: 0Hz */
|
||||
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||||
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
|
||||
};
|
||||
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
|
||||
.div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||||
};
|
||||
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
|
||||
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
|
||||
.trimConfig = NULL,
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
scg_sys_clk_config_t curConfig;
|
||||
|
||||
/* Init SIRC */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
|
||||
/* Set SCG to SIRC mode. */
|
||||
CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
|
||||
/* Init FIRC */
|
||||
CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
|
||||
/* Init LPFLL */
|
||||
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
|
||||
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeVlpr(SMC0);
|
||||
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeVlpr(SMC1);
|
||||
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
/* Wait for clock source switch finished */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
menuconfig BSP_USING_UART0
|
||||
bool "Enable UART0"
|
||||
default y
|
||||
if BSP_USING_UART0
|
||||
config SERIAL_BUS_NAME_0
|
||||
string "serial bus name"
|
||||
default "uart0"
|
||||
config SERIAL_DRV_NAME_0
|
||||
string "serial bus driver name"
|
||||
default "uart0_drv"
|
||||
config SERIAL_0_DEVICE_NAME_0
|
||||
string "serial bus device name"
|
||||
default "uart0_dev0"
|
||||
endif
|
|
@ -0,0 +1,4 @@
|
|||
SRC_FILES := connect_uart.c fsl_lpuart.c
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usart.c
|
||||
* @brief support vega-board uart function and register to bus framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-16
|
||||
*/
|
||||
|
||||
#include <xiuos.h>
|
||||
#include <device.h>
|
||||
#include <board.h>
|
||||
#include "connect_uart.h"
|
||||
#include "fsl_lpuart.h"
|
||||
|
||||
|
||||
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||
{
|
||||
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||
|
||||
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||
}
|
||||
}
|
||||
|
||||
static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.serial_register_base;
|
||||
|
||||
/* UART in mode Receiver */
|
||||
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag)
|
||||
{
|
||||
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
|
||||
/* If RX overrun. */
|
||||
if (LPUART_STAT_OR_MASK & uart_base->STAT)
|
||||
{
|
||||
/* Clear overrun flag, otherwise the RX does not work. */
|
||||
uart_base->STAT = ((uart_base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
lpuart_config_t config;
|
||||
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
|
||||
LPUART_GetDefaultConfig(&config);
|
||||
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
|
||||
|
||||
switch (serial_cfg->data_cfg.serial_data_bits)
|
||||
{
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
case DATA_BITS_7:
|
||||
config.dataBitsCount = kLPUART_SevenDataBits;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
config.dataBitsCount = kLPUART_EightDataBits;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (serial_cfg->data_cfg.serial_stop_bits)
|
||||
{
|
||||
case STOP_BITS_2:
|
||||
config.stopBitCount = kLPUART_TwoStopBit;
|
||||
break;
|
||||
default:
|
||||
config.stopBitCount = kLPUART_OneStopBit;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (serial_cfg->data_cfg.serial_parity_mode)
|
||||
{
|
||||
case PARITY_ODD:
|
||||
config.parityMode = kLPUART_ParityOdd;
|
||||
break;
|
||||
case PARITY_EVEN:
|
||||
config.parityMode = kLPUART_ParityEven;
|
||||
break;
|
||||
default:
|
||||
config.parityMode = kLPUART_ParityDisabled;
|
||||
break;
|
||||
}
|
||||
|
||||
config.enableTx = 1;
|
||||
config.enableRx = 1;
|
||||
|
||||
CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
|
||||
|
||||
uint32_t uartClkSrcFreq0 = CLOCK_GetIpFreq(kCLOCK_Lpuart0);
|
||||
LPUART_Init((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, &config, uartClkSrcFreq0);
|
||||
LPUART_EnableInterrupts((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, kLPUART_RxDataRegFullInterruptEnable);
|
||||
|
||||
CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFircAsync);
|
||||
|
||||
uint32_t uartClkSrcFreq1 = CLOCK_GetIpFreq(kCLOCK_Lpuart1);
|
||||
LPUART_Init((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, &config, uartClkSrcFreq1);
|
||||
LPUART_EnableInterrupts((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, kLPUART_RxDataRegFullInterruptEnable);
|
||||
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
|
||||
switch (serial_operation_cmd)
|
||||
{
|
||||
case OPER_CLR_INT:
|
||||
DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
|
||||
break;
|
||||
case OPER_SET_INT:
|
||||
EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
|
||||
break;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
int serial_operation_cmd;
|
||||
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = SerialInit(serial_drv, configure_info);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||
ret = SerialConfigure(serial_drv, serial_operation_cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
|
||||
LPUART_WriteByte((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, (uint8_t) c);
|
||||
while (!(LPUART_GetStatusFlags((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base) & kLPUART_TxDataRegEmptyFlag));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int SerialGetChar(struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
int ch = -1;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
|
||||
if (LPUART_GetStatusFlags((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base) & kLPUART_RxDataRegFullFlag)
|
||||
ch = LPUART_ReadByte((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base);
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct SerialDataCfg data_cfg_init =
|
||||
{
|
||||
.serial_baud_rate = BAUD_RATE_115200,
|
||||
.serial_data_bits = DATA_BITS_8,
|
||||
.serial_stop_bits = STOP_BITS_1,
|
||||
.serial_parity_mode = PARITY_NONE,
|
||||
.serial_bit_order = BIT_ORDER_LSB,
|
||||
.serial_invert_mode = NRZ_NORMAL,
|
||||
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*manage the serial device operations*/
|
||||
static const struct SerialDrvDone drv_done =
|
||||
{
|
||||
.init = SerialInit,
|
||||
.configure = SerialConfigure,
|
||||
};
|
||||
|
||||
/*manage the serial device hal operations*/
|
||||
static struct SerialHwDevDone hwdev_done =
|
||||
{
|
||||
.put_char = SerialPutChar,
|
||||
.get_char = SerialGetChar,
|
||||
};
|
||||
|
||||
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the serial bus */
|
||||
ret = SerialBusInit(serial_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialBusInit error %d\n", ret);
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
/*Init the serial driver*/
|
||||
ret = SerialDriverInit(serial_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
/*Attach the serial driver to the serial bus*/
|
||||
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the serial device to the serial bus*/
|
||||
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#ifdef BSP_USING_UART0
|
||||
struct SerialDriver serial_driver_0;
|
||||
struct SerialHardwareDevice serial_device_0;
|
||||
|
||||
void LPUART0_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
UartIsr(&serial_driver_0, &serial_device_0);
|
||||
}
|
||||
#endif
|
||||
|
||||
int InitHwUart(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
#ifdef BSP_USING_UART0
|
||||
static struct SerialBus serial_bus;
|
||||
memset(&serial_bus, 0, sizeof(struct SerialBus));
|
||||
|
||||
memset(&serial_driver_0, 0, sizeof(struct SerialDriver));
|
||||
|
||||
memset(&serial_device_0, 0, sizeof(struct SerialHardwareDevice));
|
||||
|
||||
static struct SerialCfgParam serial_cfg;
|
||||
memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct SerialDevParam serial_dev_param;
|
||||
memset(&serial_dev_param, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_driver_0.drv_done = &drv_done;
|
||||
serial_driver_0.configure = &SerialDrvConfigure;
|
||||
serial_device_0.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg.data_cfg = data_cfg_init;
|
||||
|
||||
serial_cfg.hw_cfg.serial_register_base = (uint32)LPUART0;
|
||||
serial_cfg.hw_cfg.serial_irq_interrupt = LPUART0_IRQn;
|
||||
|
||||
serial_driver_0.private_data = (void *)&serial_cfg;
|
||||
|
||||
serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_0.haldev.private_data = (void *)&serial_dev_param;
|
||||
|
||||
ret = BoardSerialBusInit(&serial_bus, &serial_driver_0, SERIAL_BUS_NAME_0, SERIAL_DRV_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart uarths error ret %u\n", ret);
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_0, (void *)&serial_cfg, SERIAL_BUS_NAME_0, SERIAL_0_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart uarths error ret %u\n", ret);
|
||||
return -ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
|
@ -240,7 +240,7 @@ uint8_t UserGetTaskPriority(int32_t id);
|
|||
#endif
|
||||
|
||||
#define UserPrintf KPrintf
|
||||
#define printf KPrintf
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -214,6 +214,7 @@ x_err_t LinklistResume(DoubleLinklistType *list);
|
|||
x_err_t LinklistResumeAll(DoubleLinklistType *list);
|
||||
void HwSendIpi(int ipi_vector, unsigned int cpu_mask);
|
||||
void KTaskIdDelete(int32 id);
|
||||
struct TaskDescriptor *GetTaskWithIdnodeInfo(int32 id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#ifdef TASK_ISOLATION
|
||||
#include <xs_isolation.h>
|
||||
#endif
|
||||
extern inline struct TaskDescriptor *GetTaskWithIdnodeInfo(int32 id);
|
||||
|
||||
#ifdef SEPARATE_COMPILE
|
||||
extern long ShowTask(void);
|
||||
extern void ShowMemory(void);
|
||||
|
|
|
@ -1222,8 +1222,9 @@ void ShowBuddy(void)
|
|||
};
|
||||
}
|
||||
|
||||
KPrintf("\n\033[41;1mlist extern memory information\033[0m\n");
|
||||
|
||||
#ifdef MEM_EXTERN_SRAM
|
||||
KPrintf("\n\033[41;1mlist extern memory information\033[0m\n");
|
||||
for(i = 0; i < EXTSRAM_MAX_NUM; i++) {
|
||||
if(NONE != ExtByteManager[i].done){
|
||||
KPrintf("\nlist extern sram[%d] memory information\n\n",i);
|
||||
|
|
|
@ -74,7 +74,9 @@ void TickAndTaskTimesliceUpdate(void)
|
|||
RoundRobinTaskTimesliceUpdate(task);
|
||||
#elif defined (SCHED_POLICY_RR_REMAINSLICE)
|
||||
task = GetKTaskDescriptor();
|
||||
RoundRobinRemainTaskTimesliceUpdate(task);
|
||||
if(task){
|
||||
RoundRobinRemainTaskTimesliceUpdate(task);
|
||||
}
|
||||
#endif
|
||||
CheckTaskDelay();
|
||||
#ifdef KERNEL_SOFTTIMER
|
||||
|
|
|
@ -87,6 +87,15 @@ KERNELPATHS :=-I$(BSP_ROOT) \
|
|||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/rv32m1_vega)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/risc-v/rv32m1_vega \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/include \
|
||||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/hifive1-rev-B)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
|
|
|
@ -100,6 +100,7 @@ static inline int SerialDevIntWrite(struct SerialHardwareDevice *serial_dev, str
|
|||
struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done;
|
||||
const uint8 *write_data = (const uint8 *)write_param->buffer;
|
||||
x_size_t write_length = write_param->size;
|
||||
x_size_t len_result = 0;
|
||||
|
||||
while (write_length)
|
||||
{
|
||||
|
@ -109,12 +110,12 @@ static inline int SerialDevIntWrite(struct SerialHardwareDevice *serial_dev, str
|
|||
}
|
||||
|
||||
KPrintf("SerialDevIntWrite data %d write_length %u\n", *(char *)write_data, write_length);
|
||||
|
||||
len_result++;
|
||||
write_data++;
|
||||
write_length--;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
return len_result;
|
||||
}
|
||||
|
||||
static inline int SerialDevIntRead(struct SerialHardwareDevice *serial_dev, struct BusBlockReadParam *read_param)
|
||||
|
@ -201,7 +202,7 @@ static inline int SerialDevDMAWrite(struct SerialHardwareDevice *serial_dev, str
|
|||
CriticalAreaUnLock(lock);
|
||||
}
|
||||
|
||||
return EOK;
|
||||
return write_length;
|
||||
}
|
||||
|
||||
static x_size_t SerialGetRxFifoLength(struct SerialHardwareDevice *serial_dev)
|
||||
|
@ -329,7 +330,7 @@ static inline int SerialDevPollingWrite(struct SerialHardwareDevice *serial_dev,
|
|||
struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done;
|
||||
const uint8 *write_data = (const uint8 *)write_param->buffer;
|
||||
x_size_t write_length = write_param->size;
|
||||
|
||||
x_size_t len_result = 0;
|
||||
while (write_length)
|
||||
{
|
||||
if ((*write_data == '\n') && (SIGN_OPER_STREAM == serial_stream_mode)) {
|
||||
|
@ -337,12 +338,12 @@ static inline int SerialDevPollingWrite(struct SerialHardwareDevice *serial_dev,
|
|||
}
|
||||
|
||||
hwdev_done->put_char(serial_dev, *write_data);
|
||||
|
||||
len_result++;
|
||||
++write_data;
|
||||
--write_length;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
return len_result;
|
||||
}
|
||||
|
||||
static inline int SerialDevPollingRead(struct SerialHardwareDevice *serial_dev, struct BusBlockReadParam *read_param)
|
||||
|
@ -604,7 +605,7 @@ static uint32 SerialDevWrite(void *dev, struct BusBlockWriteParam *write_param)
|
|||
|
||||
if (serial_dev_param->serial_work_mode & SIGN_OPER_INT_TX) {
|
||||
ret = SerialDevIntWrite(serial_dev, write_param);
|
||||
if (EOK != ret) {
|
||||
if (ret < 0) {
|
||||
KPrintf("SerialDevIntWrite error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
@ -612,7 +613,7 @@ static uint32 SerialDevWrite(void *dev, struct BusBlockWriteParam *write_param)
|
|||
#ifdef SERIAL_USING_DMA
|
||||
else if (serial_dev_param->serial_work_mode & SIGN_OPER_DMA_TX) {
|
||||
ret = SerialDevDMAWrite(serial_dev, write_param);
|
||||
if (EOK != ret) {
|
||||
if (ret < 0) {
|
||||
KPrintf("SerialDevDMAWrite error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
@ -620,13 +621,13 @@ static uint32 SerialDevWrite(void *dev, struct BusBlockWriteParam *write_param)
|
|||
#endif
|
||||
else {
|
||||
ret = SerialDevPollingWrite(serial_dev, write_param, serial_dev_param->serial_stream_mode);
|
||||
if (EOK != ret) {
|
||||
if (ret < 0) {
|
||||
KPrintf("SerialDevPollingWrite error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return EOK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uint32 SerialDevRead(void *dev, struct BusBlockReadParam *read_param)
|
||||
|
|