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Merge branch 'smp' of https://gitlink.org.cn/tuyuyang/xiuos into smp

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This commit is contained in:
liuqh
2024-05-08 15:36:46 +08:00
parent 6b91caac18 3b011500f1
commit 361ea2b53e
181 changed files with 10418 additions and 1429 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h
+2 -1
View File
@@ -56,10 +56,11 @@ Modification:
#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
/* User memory layout */
#define USER_STACK_SIZE PAGE_SIZE
#define USER_STACK_SIZE MODE_STACK_SIZE
#define USER_MEM_BASE (0x00000000)
#define USER_MEM_TOP DEV_VRTMEM_BASE
#define USER_IPC_SPACE_BASE (0x70000000)
#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x70010000)
#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
/* Deivce memory layout */
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/mmu.c
-19
View File
@@ -38,24 +38,6 @@ Modification:
// extern struct MmuCommonDone mmu_common_done;
static struct MmuDriverRightGroup right_group;
void load_pgdir_critical(uintptr_t pgdir_paddr, struct TraceTag* intr_driver_tag)
{
/* get cache driver */
struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag);
struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
/* get intr driver */
struct XiziTrapDriver* p_intr_driver = AchieveResource(intr_driver_tag);
p_intr_driver->cpu_irq_disable();
TTBR0_W((uint32_t)pgdir_paddr);
CLEARTLB(0);
p_icache_done->invalidateall();
p_dcache_done->flushall();
p_intr_driver->cpu_irq_enable();
}
void load_pgdir(uintptr_t pgdir_paddr)
{
/* get cache driver */
@@ -94,7 +76,6 @@ static struct MmuCommonDone mmu_common_done = {
.MmuUsrDevPteAttr = GetUsrDevPteAttr,
.MmuKernPteAttr = GetKernPteAttr,
.LoadPgdirCrit = load_pgdir_critical,
.LoadPgdir = load_pgdir,
.TlbFlushAll = tlb_flush_all,
.TlbFlush = tlb_flush_range,
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h
+3 -2
View File
@@ -53,13 +53,14 @@ Modification:
#define NUM_TOPLEVEL_PDE NUM_LEVEL3_PDE
#define PAGE_SIZE LEVEL4_PTE_SIZE
#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
#define MAX_NR_FREE_PAGES ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
/* User memory layout */
#define USER_STACK_SIZE PAGE_SIZE
#define USER_STACK_SIZE MODE_STACK_SIZE
#define USER_MEM_BASE (0x00000000)
#define USER_MEM_TOP DEV_VRTMEM_BASE
#define USER_IPC_SPACE_BASE (0x70000000)
#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x70010000)
#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
/* Deivce memory layout */