cortex-m4-emulator

Ubiquitous/XiUOS/Makefile

@@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
 .PHONY:COMPILE_APP COMPILE_KERNEL
 
 
-support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c gapuino
+support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino
 SRC_DIR:=
 
 export BOARD ?=kd233

Ubiquitous/XiUOS/arch/arm/Makefile

@@ -9,6 +9,10 @@ ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
 SRC_DIR +=cortex-m4
 endif
 
+ifeq ($(CONFIG_BOARD_CORTEX_M4_EVB),y)
+SRC_DIR +=cortex-m4
+endif
+
 ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y)
 SRC_DIR +=cortex-m7
 endif

Ubiquitous/XiUOS/arch/arm/cortex-m4/boot.S

@@ -105,6 +105,7 @@ BSSInit:
 
 BSSInitEnd:
   bl  SystemInit
-  bl  stm32f407_start
+
+  bl  entry
   bx  lr
 .size  Reset_Handler, .-Reset_Handler

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210730193816

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_STM32F407_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "stm32f407-st-discovery feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_stm32f407-st-discovery_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134238

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "stm32f407-st-discovery feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_stm32f407-st-discovery_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134239

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "stm32f407-st-discovery feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_stm32f407-st-discovery_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134303

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_stm32f407-st-discovery_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134324

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134546

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134553

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134554

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134556

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134557

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134558

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134605

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134606

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134607

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134608

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825135732

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140237

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140238

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140304

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140305

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "//XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140911

@@ -0,0 +1,63 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825111355.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	Stm32HwUsartInit();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825132137.h

@@ -0,0 +1,78 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define stm32f407-st-discovery-board init configure and start-up function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.h
+Description: define stm32f407-st-discovery-board board init function and struct
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. define stm32f407-st-discovery-board InitBoardHardware
+2. define stm32f407-st-discovery-board data and bss struct
+*************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include <stdint.h>
+
+extern int __stack_end__;
+extern unsigned int g_service_table_start;
+extern unsigned int g_service_table_end;
+
+#define SURPORT_MPU
+
+#define MEMORY_START_ADDRESS (&__stack_end__)
+#define MEM_OFFSET         128
+#define MEMORY_END_ADDRESS      (0x20000000 + MEM_OFFSET * 1024)
+
+
+#ifdef SEPARATE_COMPILE
+typedef int (*main_t)(int argc, char *argv[]);
+typedef void (*exit_t)(void);
+struct userspace_s
+{
+  main_t    us_entrypoint;
+  exit_t    us_taskquit;
+  uintptr_t us_textstart;
+  uintptr_t us_textend;
+  uintptr_t us_datasource;
+  uintptr_t us_datastart;
+  uintptr_t us_dataend;
+  uintptr_t us_bssstart;
+  uintptr_t us_bssend;
+  uintptr_t us_heapend;
+};
+#define USERSPACE (( struct userspace_s *)(0x08080000))
+
+#ifndef SERVICE_TABLE_ADDRESS
+#define SERVICE_TABLE_ADDRESS    (0x20000000)
+#endif
+
+#define USER_SRAM_SIZE         64
+#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
+#define USER_MEMORY_END_ADDRESS   (0x10000000 + USER_SRAM_SIZE * 1024)
+#endif
+
+void InitBoardHardware(void);
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135326.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	InitHwUsart();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135622.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	InitHwUsart();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135623.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	InitHwUsart();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825140908.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	InitHwUsart();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825210606.h

@@ -0,0 +1,78 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define stm32f407-st-discovery-board init configure and start-up function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.h
+Description: define stm32f407-st-discovery-board board init function and struct
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. define stm32f407-st-discovery-board InitBoardHardware
+2. define stm32f407-st-discovery-board data and bss struct
+*************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include <stdint.h>
+
+extern int __stack_end__;
+extern unsigned int g_service_table_start;
+extern unsigned int g_service_table_end;
+
+#define SURPORT_MPU
+
+#define MEMORY_START_ADDRESS (&__stack_end__)
+#define MEM_OFFSET         128
+#define MEMORY_END_ADDRESS      (0x20000000 + MEM_OFFSET * 1024)
+
+
+#ifdef SEPARATE_COMPILE
+typedef int (*main_t)(int argc, char *argv[]);
+typedef void (*exit_t)(void);
+struct userspace_s
+{
+  main_t    us_entrypoint;
+  exit_t    us_taskquit;
+  uintptr_t us_textstart;
+  uintptr_t us_textend;
+  uintptr_t us_datasource;
+  uintptr_t us_datastart;
+  uintptr_t us_dataend;
+  uintptr_t us_bssstart;
+  uintptr_t us_bssend;
+  uintptr_t us_heapend;
+};
+#define USERSPACE (( struct userspace_s *)(0x08080000))
+
+#ifndef SERVICE_TABLE_ADDRESS
+#define SERVICE_TABLE_ADDRESS    (0x20000000)
+#endif
+
+#define USER_SRAM_SIZE         64
+#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
+#define USER_MEMORY_END_ADDRESS   (0x10000000 + USER_SRAM_SIZE * 1024)
+#endif
+
+void InitBoardHardware(void);
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182559.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	Stm32HwUsartInit();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182600.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	Stm32HwUsartInit();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182601.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f407-st-discovery-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.c
+Description: support stm32f407-st-discovery-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	Stm32HwUsartInit();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210824125750.mk

@@ -0,0 +1,17 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
+export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
+
+export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
+
+export USING_NEWLIB =1
+export USING_VFS = 1
+export USING_SPI = 1
+export ARCH = arm
+export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140049.mk

@@ -0,0 +1,14 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
+export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
+
+export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
+
+export ARCH = arm
+export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140050.mk

@@ -0,0 +1,14 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
+export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
+
+export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
+
+export ARCH = arm
+export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140057.mk

@@ -0,0 +1,14 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
+export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
+
+export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  
+
+export ARCH = arm
+export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140058.mk

@@ -0,0 +1,14 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
+export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
+
+export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  
+
+export ARCH = arm
+export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/include/connect_usart_20210730193816.h

@@ -0,0 +1,63 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_usart.h
+* @brief define stm32f407-st-discovery-board usart function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_USART_H
+#define CONNECT_USART_H
+
+#include <device.h>
+#include "hardware_usart.h"
+#include "hardware_dma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_1
+#define KERNEL_CONSOLE_DRV_NAME       SERIAL_DRV_NAME_1
+#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
+
+struct UsartHwCfg
+{
+    USART_TypeDef *uart_device;
+    IRQn_Type irq;
+};
+
+struct Stm32Usart
+{
+    struct Stm32UsartDma
+    {
+        DMA_Stream_TypeDef *RxStream;
+        uint32 RxCh;
+        uint32 RxFlag;
+        uint8 RxIrqCh;
+        x_size_t SettingRecvLen;
+        x_size_t LastRecvIndex;
+    } dma;
+
+    struct SerialBus serial_bus;
+};
+
+int Stm32HwUsartInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/include/connect_usart_20210825135326.h

@@ -0,0 +1,63 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_usart.h
+* @brief define stm32f407-st-discovery-board usart function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_USART_H
+#define CONNECT_USART_H
+
+#include <device.h>
+#include "hardware_usart.h"
+#include "hardware_dma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_1
+#define KERNEL_CONSOLE_DRV_NAME       SERIAL_DRV_NAME_1
+#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
+
+struct UsartHwCfg
+{
+    USART_TypeDef *uart_device;
+    IRQn_Type irq;
+};
+
+struct Stm32Usart
+{
+    struct Stm32UsartDma
+    {
+        DMA_Stream_TypeDef *RxStream;
+        uint32 RxCh;
+        uint32 RxFlag;
+        uint8 RxIrqCh;
+        x_size_t SettingRecvLen;
+        x_size_t LastRecvIndex;
+    } dma;
+
+    struct SerialBus serial_bus;
+};
+
+int InitHwUsart(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210730193816.c

@@ -0,0 +1,858 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+/**
+* @file connect_usart.c
+* @brief support stm32f407-st-discovery-board usart function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_uart.c
+Description: support stm32f407-st-discovery-board usart configure and uart bus register function
+Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board usart configure, write and read
+2. support stm32f407-st-discovery-board usart bus device and driver register
+*************************************************/
+
+#include "stm32f4xx.h"
+#include "board.h"
+#include "misc.h"
+#include "connect_usart.h"
+#include "hardware_gpio.h"
+#include "hardware_rcc.h"
+
+/* UART GPIO define. */
+#define UART1_GPIO_TX       GPIO_Pin_6
+#define UART1_TX_PIN_SOURCE GPIO_PinSource6
+#define UART1_GPIO_RX       GPIO_Pin_7
+#define UART1_RX_PIN_SOURCE GPIO_PinSource7
+#define UART1_GPIO          GPIOB
+#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOB
+#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
+
+#define UART2_GPIO_TX       GPIO_Pin_2
+#define UART2_TX_PIN_SOURCE GPIO_PinSource2
+#define UART2_GPIO_RX       GPIO_Pin_3
+#define UART2_RX_PIN_SOURCE GPIO_PinSource3
+#define UART2_GPIO          GPIOA
+#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
+#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
+
+#define UART3_GPIO_TX       GPIO_Pin_8
+#define UART3_TX_PIN_SOURCE GPIO_PinSource8
+#define UART3_GPIO_RX       GPIO_Pin_9
+#define UART3_RX_PIN_SOURCE GPIO_PinSource9
+#define UART3_GPIO          GPIOD
+#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
+
+#define UART4_GPIO_TX       GPIO_Pin_10
+#define UART4_TX_PIN_SOURCE GPIO_PinSource10
+#define UART4_GPIO_RX       GPIO_Pin_11
+#define UART4_RX_PIN_SOURCE GPIO_PinSource11
+#define UART4_GPIO          GPIOC
+#define UART4_GPIO_RCC      RCC_AHB1Periph_GPIOC
+#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
+
+#define UART5_GPIO_TX       GPIO_Pin_12
+#define UART5_TX_PIN_SOURCE GPIO_PinSource12
+#define UART5_GPIO_RX       GPIO_Pin_2
+#define UART5_RX_PIN_SOURCE GPIO_PinSource2
+#define UART5_TX            GPIOC
+#define UART5_RX            GPIOD
+#define UART5_GPIO_RCC_TX   RCC_AHB1Periph_GPIOC
+#define UART5_GPIO_RCC_RX   RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
+
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+static void RCCConfiguration(void)
+{
+#ifdef BSP_USING_USART1
+    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
+#endif
+
+#ifdef BSP_USING_USART2
+    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
+#endif
+
+#ifdef BSP_USING_USART3
+    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
+#endif
+
+#ifdef BSP_USING_UART4
+    RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
+#endif
+
+#ifdef BSP_USING_UART5
+    RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
+#endif
+}
+
+static void GPIOConfiguration(void)
+{
+    GPIO_InitTypeDef gpio_initstructure;
+
+    gpio_initstructure.GPIO_Mode  = GPIO_Mode_AF;
+    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
+    gpio_initstructure.GPIO_PuPd  = GPIO_PuPd_UP;
+    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
+
+#ifdef BSP_USING_USART1
+    gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
+    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
+    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);    
+    
+    GPIO_Init(UART1_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_USART2
+    gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
+    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
+    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
+    
+    GPIO_Init(UART2_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_USART3
+    gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
+    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
+    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
+    
+    GPIO_Init(UART3_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_UART4
+    gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
+    GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
+    GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
+    
+    GPIO_Init(UART4_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_UART5
+    gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
+    GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); 
+    GPIO_Init(UART5_TX, &gpio_initstructure);
+    
+    gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
+    GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
+    GPIO_Init(UART5_RX, &gpio_initstructure);
+#endif
+}
+
+static void NVIC_Configuration(IRQn_Type irq)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    NVIC_InitStructure.NVIC_IRQChannel = irq;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
+{   
+    DMA_InitTypeDef DMA_InitStructure;
+
+    dma->SettingRecvLen = SettingRecvLen;
+    DMA_DeInit(dma->RxStream);
+    while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
+    DMA_InitStructure.DMA_Channel = dma->RxCh;
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
+    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
+    DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
+    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
+    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
+    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
+    DMA_Init(dma->RxStream, &DMA_InitStructure);
+}
+
+static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
+{
+    struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
+
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
+
+    DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
+
+    DMA_ClearFlag(dma->RxStream, dma->RxFlag);
+    DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
+    USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
+    DMA_Cmd(dma->RxStream, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
+{
+    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
+    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
+
+    if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
+        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
+    }
+
+    if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
+        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
+    }
+
+    if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
+        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
+    }
+
+    if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
+        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
+    }
+
+    if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
+        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
+    }
+
+    if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
+        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
+    }
+
+    if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
+        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
+    }
+}
+
+static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (configure_info->private_data) {
+        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
+        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
+    }
+
+    USART_InitTypeDef USART_InitStructure;
+
+    USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
+
+    if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
+        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+    }
+
+    if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
+        USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
+        USART_InitStructure.USART_StopBits = USART_StopBits_2;
+    }
+
+    if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
+        USART_InitStructure.USART_Parity = USART_Parity_No;
+    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
+        USART_InitStructure.USART_Parity = USART_Parity_Odd;
+    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
+        USART_InitStructure.USART_Parity = USART_Parity_Even;
+    }
+
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
+
+    USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
+
+    return EOK;
+}
+
+static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+    switch (serial_operation_cmd)
+    {
+        case OPER_CLR_INT:
+            UART_DISABLE_IRQ(serial_hw_cfg->irq);
+            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
+            break;
+        case OPER_SET_INT:
+            UART_ENABLE_IRQ(serial_hw_cfg->irq);
+            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
+            break;
+        case OPER_CONFIG :
+            if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
+                DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
+            }
+    }
+
+    return EOK;
+}
+
+static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
+    serial_hw_cfg->uart_device->DR = c;
+
+    return EOK;
+}
+
+static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    int ch = -1;
+    if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
+        ch = serial_hw_cfg->uart_device->DR & 0xff;
+    }
+
+    return ch;
+}
+
+static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
+{
+    x_base level = CriticalAreaLock();
+
+    x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
+    x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
+    dma->LastRecvIndex = recv_total_index;
+    CriticalAreaUnLock(level);
+
+    if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+
+    USART_ReceiveData(uart_device);
+}
+
+static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
+{
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
+        x_base level = CriticalAreaLock();
+
+        x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
+        dma->LastRecvIndex = 0;
+        CriticalAreaUnLock(level);
+
+        if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+
+        DMA_ClearFlag(dma->RxStream, dma->RxFlag);
+    }
+}
+
+static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
+{
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
+        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
+        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
+    }
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
+        DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
+    }
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
+        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
+    }
+    if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
+        USART_ReceiveData(serial_hw_cfg->uart_device);
+    }
+}
+
+#ifdef BSP_USING_USART1
+struct Stm32Usart serial_1;
+struct SerialDriver serial_driver_1;
+struct SerialHardwareDevice serial_device_1;
+
+static const struct Stm32UsartDma usart_dma_1 =
+{
+    DMA2_Stream5,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF5,
+    DMA2_Stream5_IRQn,
+    0,
+    0,
+};
+
+void USART1_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
+}
+DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
+
+void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
+}
+DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_USART2
+struct Stm32Usart serial_2;
+struct SerialDriver serial_driver_2;
+struct SerialHardwareDevice serial_device_2;
+
+static const struct Stm32UsartDma usart_dma_2 =
+{
+    DMA1_Stream5,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF5,
+    DMA1_Stream5_IRQn,
+    0,
+    0,
+};
+
+void USART2_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
+}
+DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
+
+void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
+}
+DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_USART3
+struct Stm32Usart serial_3;
+struct SerialDriver serial_driver_3;
+struct SerialHardwareDevice serial_device_3;
+
+static const struct Stm32UsartDma usart_dma_3 =
+{
+    DMA1_Stream1,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF1,
+    DMA1_Stream1_IRQn,
+    0,
+    0,
+};
+
+void USART3_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
+}
+DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
+
+void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
+}
+DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_UART4
+struct Stm32Usart serial_4;
+struct SerialDriver serial_driver_4;
+struct SerialHardwareDevice serial_device_4;
+
+static const struct Stm32UsartDma uart_dma_4 =
+{
+    DMA1_Stream2,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF2,
+    DMA1_Stream2_IRQn,
+    0,
+    0,
+};
+
+void UART4_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
+}
+DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
+
+void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
+}
+DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_UART5
+struct Stm32Usart serial_5;
+struct SerialDriver serial_driver_5;
+struct SerialHardwareDevice serial_device_5;
+
+static const struct Stm32UsartDma uart_dma_5 =
+{
+    DMA1_Stream0,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF0,
+    DMA1_Stream0_IRQn,
+    0,
+    0,
+};
+
+void UART5_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
+}
+DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
+
+void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
+}
+DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
+#endif
+
+static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    int serial_operation_cmd;
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = Stm32SerialInit(serial_drv, configure_info);
+            break;
+        case OPE_CFG:
+            serial_operation_cmd = *(int *)configure_info->private_data;
+            ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct SerialDataCfg data_cfg_init = 
+{
+    .serial_baud_rate = BAUD_RATE_115200,
+    .serial_data_bits = DATA_BITS_8,
+    .serial_stop_bits = STOP_BITS_1,
+    .serial_parity_mode = PARITY_NONE,
+    .serial_bit_order = BIT_ORDER_LSB,
+    .serial_invert_mode = NRZ_NORMAL,
+    .serial_buffer_size = SERIAL_RB_BUFSZ,
+};
+
+/*manage the serial device operations*/
+static const struct SerialDrvDone drv_done =
+{
+    .init = Stm32SerialInit,
+    .configure = Stm32SerialConfigure,
+};
+
+/*manage the serial device hal operations*/
+static struct SerialHwDevDone hwdev_done =
+{
+    .put_char = Stm32SerialPutchar,
+    .get_char = Stm32SerialGetchar,
+};
+
+static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the serial bus */
+    ret = SerialBusInit(serial_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the serial driver*/
+    ret = SerialDriverInit(serial_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the serial driver to the serial bus*/
+    ret = SerialDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the serial device to the serial bus*/
+static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
+{
+    x_err_t ret = EOK;
+
+    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    ret = SerialDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+int InitHwUsart(void)
+{
+    x_err_t ret = EOK;
+
+    RCCConfiguration();
+    GPIOConfiguration();
+
+#ifdef BSP_USING_USART1
+    static struct SerialCfgParam serial_cfg_1;
+    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_1;
+    memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_1;
+    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
+
+    serial_1.dma = usart_dma_1;
+    
+    serial_driver_1.drv_done = &drv_done;
+    serial_driver_1.configure = &Stm32SerialDrvConfigure;
+    serial_device_1.hwdev_done = &hwdev_done;
+
+    serial_cfg_1.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_1.uart_device = USART1;
+    serial_hw_cfg_1.irq = USART1_IRQn;
+    serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
+    serial_driver_1.private_data = (void *)&serial_cfg_1;
+
+    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
+
+    NVIC_Configuration(serial_hw_cfg_1.irq);
+
+    ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_USART2
+    static struct SerialCfgParam serial_cfg_2;
+    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_2;
+    memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_2;
+    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
+
+    serial_2.dma = usart_dma_2;
+    
+    serial_driver_2.drv_done = &drv_done;
+    serial_driver_2.configure = &Stm32SerialDrvConfigure;
+    serial_device_2.hwdev_done = &hwdev_done;
+
+    serial_cfg_2.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_2.uart_device = USART2;
+    serial_hw_cfg_2.irq = USART2_IRQn;
+    serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
+    serial_driver_2.private_data = (void *)&serial_cfg_2;
+
+    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
+
+    NVIC_Configuration(serial_hw_cfg_2.irq);
+
+    ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_USART3
+    static struct SerialCfgParam serial_cfg_3;
+    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_3;
+    memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_3;
+    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
+
+    serial_3.dma = usart_dma_3;
+    
+    serial_driver_3.drv_done = &drv_done;
+    serial_driver_3.configure = &Stm32SerialDrvConfigure;
+    serial_device_3.hwdev_done = &hwdev_done;
+
+    serial_cfg_3.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_3.uart_device = USART3;
+    serial_hw_cfg_3.irq = USART3_IRQn;
+    serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
+    serial_driver_3.private_data = (void *)&serial_cfg_3;
+
+    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
+
+    NVIC_Configuration(serial_hw_cfg_3.irq);
+
+    ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART4
+    static struct SerialCfgParam serial_cfg_4;
+    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_4;
+    memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_4;
+    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
+
+    serial_4.dma = uart_dma_4;
+    
+    serial_driver_4.drv_done = &drv_done;
+    serial_driver_4.configure = &Stm32SerialDrvConfigure;
+    serial_device_4.hwdev_done = &hwdev_done;
+
+    serial_cfg_4.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_4.uart_device = UART4;
+    serial_hw_cfg_4.irq = UART4_IRQn;
+    serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
+    serial_driver_4.private_data = (void *)&serial_cfg_4;
+
+    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
+
+    NVIC_Configuration(serial_hw_cfg_4.irq);
+
+    ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART5
+    static struct SerialCfgParam serial_cfg_5;
+    memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_5;
+    memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_5;
+    memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
+
+    serial_5.dma = uart_dma_5;
+    
+    serial_driver_5.drv_done = &drv_done;
+    serial_driver_5.configure = &Stm32SerialDrvConfigure;
+    serial_device_5.hwdev_done = &hwdev_done;
+
+    serial_cfg_5.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_5.uart_device = UART5;
+    serial_hw_cfg_5.irq = UART5_IRQn;
+    serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
+    serial_driver_5.private_data = (void *)&serial_cfg_5;
+
+    serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
+
+    NVIC_Configuration(serial_hw_cfg_5.irq);
+
+    ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+    return ret;
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210825135244.c

@@ -0,0 +1,858 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+/**
+* @file connect_usart.c
+* @brief support stm32f407-st-discovery-board usart function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_uart.c
+Description: support stm32f407-st-discovery-board usart configure and uart bus register function
+Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board usart configure, write and read
+2. support stm32f407-st-discovery-board usart bus device and driver register
+*************************************************/
+
+#include "stm32f4xx.h"
+#include "board.h"
+#include "misc.h"
+#include "connect_usart.h"
+#include "hardware_gpio.h"
+#include "hardware_rcc.h"
+
+/* UART GPIO define. */
+#define UART1_GPIO_TX       GPIO_Pin_6
+#define UART1_TX_PIN_SOURCE GPIO_PinSource6
+#define UART1_GPIO_RX       GPIO_Pin_7
+#define UART1_RX_PIN_SOURCE GPIO_PinSource7
+#define UART1_GPIO          GPIOB
+#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOB
+#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
+
+#define UART2_GPIO_TX       GPIO_Pin_2
+#define UART2_TX_PIN_SOURCE GPIO_PinSource2
+#define UART2_GPIO_RX       GPIO_Pin_3
+#define UART2_RX_PIN_SOURCE GPIO_PinSource3
+#define UART2_GPIO          GPIOA
+#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
+#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
+
+#define UART3_GPIO_TX       GPIO_Pin_8
+#define UART3_TX_PIN_SOURCE GPIO_PinSource8
+#define UART3_GPIO_RX       GPIO_Pin_9
+#define UART3_RX_PIN_SOURCE GPIO_PinSource9
+#define UART3_GPIO          GPIOD
+#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
+
+#define UART4_GPIO_TX       GPIO_Pin_10
+#define UART4_TX_PIN_SOURCE GPIO_PinSource10
+#define UART4_GPIO_RX       GPIO_Pin_11
+#define UART4_RX_PIN_SOURCE GPIO_PinSource11
+#define UART4_GPIO          GPIOC
+#define UART4_GPIO_RCC      RCC_AHB1Periph_GPIOC
+#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
+
+#define UART5_GPIO_TX       GPIO_Pin_12
+#define UART5_TX_PIN_SOURCE GPIO_PinSource12
+#define UART5_GPIO_RX       GPIO_Pin_2
+#define UART5_RX_PIN_SOURCE GPIO_PinSource2
+#define UART5_TX            GPIOC
+#define UART5_RX            GPIOD
+#define UART5_GPIO_RCC_TX   RCC_AHB1Periph_GPIOC
+#define UART5_GPIO_RCC_RX   RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
+
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+static void RCCConfiguration(void)
+{
+#ifdef BSP_USING_USART1
+    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
+#endif
+
+#ifdef BSP_USING_USART2
+    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
+#endif
+
+#ifdef BSP_USING_USART3
+    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
+#endif
+
+#ifdef BSP_USING_UART4
+    RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
+#endif
+
+#ifdef BSP_USING_UART5
+    RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
+#endif
+}
+
+static void GPIOConfiguration(void)
+{
+    GPIO_InitTypeDef gpio_initstructure;
+
+    gpio_initstructure.GPIO_Mode  = GPIO_Mode_AF;
+    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
+    gpio_initstructure.GPIO_PuPd  = GPIO_PuPd_UP;
+    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
+
+#ifdef BSP_USING_USART1
+    gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
+    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
+    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);    
+    
+    GPIO_Init(UART1_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_USART2
+    gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
+    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
+    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
+    
+    GPIO_Init(UART2_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_USART3
+    gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
+    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
+    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
+    
+    GPIO_Init(UART3_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_UART4
+    gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
+    GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
+    GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
+    
+    GPIO_Init(UART4_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_UART5
+    gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
+    GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); 
+    GPIO_Init(UART5_TX, &gpio_initstructure);
+    
+    gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
+    GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
+    GPIO_Init(UART5_RX, &gpio_initstructure);
+#endif
+}
+
+static void NVIC_Configuration(IRQn_Type irq)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    NVIC_InitStructure.NVIC_IRQChannel = irq;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
+{   
+    DMA_InitTypeDef DMA_InitStructure;
+
+    dma->SettingRecvLen = SettingRecvLen;
+    DMA_DeInit(dma->RxStream);
+    while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
+    DMA_InitStructure.DMA_Channel = dma->RxCh;
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
+    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
+    DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
+    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
+    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
+    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
+    DMA_Init(dma->RxStream, &DMA_InitStructure);
+}
+
+static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
+{
+    struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
+
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
+
+    DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
+
+    DMA_ClearFlag(dma->RxStream, dma->RxFlag);
+    DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
+    USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
+    DMA_Cmd(dma->RxStream, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
+{
+    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
+    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
+
+    if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
+        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
+    }
+
+    if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
+        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
+    }
+
+    if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
+        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
+    }
+
+    if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
+        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
+    }
+
+    if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
+        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
+    }
+
+    if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
+        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
+    }
+
+    if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
+        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
+    }
+}
+
+static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (configure_info->private_data) {
+        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
+        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
+    }
+
+    USART_InitTypeDef USART_InitStructure;
+
+    USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
+
+    if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
+        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+    }
+
+    if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
+        USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
+        USART_InitStructure.USART_StopBits = USART_StopBits_2;
+    }
+
+    if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
+        USART_InitStructure.USART_Parity = USART_Parity_No;
+    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
+        USART_InitStructure.USART_Parity = USART_Parity_Odd;
+    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
+        USART_InitStructure.USART_Parity = USART_Parity_Even;
+    }
+
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
+
+    USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
+
+    return EOK;
+}
+
+static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+    switch (serial_operation_cmd)
+    {
+        case OPER_CLR_INT:
+            UART_DISABLE_IRQ(serial_hw_cfg->irq);
+            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
+            break;
+        case OPER_SET_INT:
+            UART_ENABLE_IRQ(serial_hw_cfg->irq);
+            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
+            break;
+        case OPER_CONFIG :
+            if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
+                DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
+            }
+    }
+
+    return EOK;
+}
+
+static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
+    serial_hw_cfg->uart_device->DR = c;
+
+    return EOK;
+}
+
+static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    int ch = -1;
+    if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
+        ch = serial_hw_cfg->uart_device->DR & 0xff;
+    }
+
+    return ch;
+}
+
+static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
+{
+    x_base level = CriticalAreaLock();
+
+    x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
+    x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
+    dma->LastRecvIndex = recv_total_index;
+    CriticalAreaUnLock(level);
+
+    if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+
+    USART_ReceiveData(uart_device);
+}
+
+static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
+{
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
+        x_base level = CriticalAreaLock();
+
+        x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
+        dma->LastRecvIndex = 0;
+        CriticalAreaUnLock(level);
+
+        if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+
+        DMA_ClearFlag(dma->RxStream, dma->RxFlag);
+    }
+}
+
+static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
+{
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
+        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
+        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
+    }
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
+        DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
+    }
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
+        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
+    }
+    if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
+        USART_ReceiveData(serial_hw_cfg->uart_device);
+    }
+}
+
+#ifdef BSP_USING_USART1
+struct Stm32Usart serial_1;
+struct SerialDriver serial_driver_1;
+struct SerialHardwareDevice serial_device_1;
+
+static const struct Stm32UsartDma usart_dma_1 =
+{
+    DMA2_Stream5,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF5,
+    DMA2_Stream5_IRQn,
+    0,
+    0,
+};
+
+void USART1_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
+}
+DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
+
+void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
+}
+DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_USART2
+struct Stm32Usart serial_2;
+struct SerialDriver serial_driver_2;
+struct SerialHardwareDevice serial_device_2;
+
+static const struct Stm32UsartDma usart_dma_2 =
+{
+    DMA1_Stream5,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF5,
+    DMA1_Stream5_IRQn,
+    0,
+    0,
+};
+
+void USART2_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
+}
+DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
+
+void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
+}
+DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_USART3
+struct Stm32Usart serial_3;
+struct SerialDriver serial_driver_3;
+struct SerialHardwareDevice serial_device_3;
+
+static const struct Stm32UsartDma usart_dma_3 =
+{
+    DMA1_Stream1,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF1,
+    DMA1_Stream1_IRQn,
+    0,
+    0,
+};
+
+void USART3_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
+}
+DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
+
+void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
+}
+DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_UART4
+struct Stm32Usart serial_4;
+struct SerialDriver serial_driver_4;
+struct SerialHardwareDevice serial_device_4;
+
+static const struct Stm32UsartDma uart_dma_4 =
+{
+    DMA1_Stream2,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF2,
+    DMA1_Stream2_IRQn,
+    0,
+    0,
+};
+
+void UART4_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
+}
+DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
+
+void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
+}
+DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_UART5
+struct Stm32Usart serial_5;
+struct SerialDriver serial_driver_5;
+struct SerialHardwareDevice serial_device_5;
+
+static const struct Stm32UsartDma uart_dma_5 =
+{
+    DMA1_Stream0,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF0,
+    DMA1_Stream0_IRQn,
+    0,
+    0,
+};
+
+void UART5_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
+}
+DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
+
+void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
+}
+DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
+#endif
+
+static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    int serial_operation_cmd;
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = Stm32SerialInit(serial_drv, configure_info);
+            break;
+        case OPE_CFG:
+            serial_operation_cmd = *(int *)configure_info->private_data;
+            ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct SerialDataCfg data_cfg_init = 
+{
+    .serial_baud_rate = BAUD_RATE_115200,
+    .serial_data_bits = DATA_BITS_8,
+    .serial_stop_bits = STOP_BITS_1,
+    .serial_parity_mode = PARITY_NONE,
+    .serial_bit_order = BIT_ORDER_LSB,
+    .serial_invert_mode = NRZ_NORMAL,
+    .serial_buffer_size = SERIAL_RB_BUFSZ,
+};
+
+/*manage the serial device operations*/
+static const struct SerialDrvDone drv_done =
+{
+    .init = Stm32SerialInit,
+    .configure = Stm32SerialConfigure,
+};
+
+/*manage the serial device hal operations*/
+static struct SerialHwDevDone hwdev_done =
+{
+    .put_char = Stm32SerialPutchar,
+    .get_char = Stm32SerialGetchar,
+};
+
+static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the serial bus */
+    ret = SerialBusInit(serial_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the serial driver*/
+    ret = SerialDriverInit(serial_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the serial driver to the serial bus*/
+    ret = SerialDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the serial device to the serial bus*/
+static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
+{
+    x_err_t ret = EOK;
+
+    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    ret = SerialDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+int InitHwUsart(void)
+{
+    x_err_t ret = EOK;
+
+    RCCConfiguration();
+    GPIOConfiguration();
+
+#ifdef BSP_USING_USART1
+    static struct SerialCfgParam serial_cfg_1;
+    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_1;
+    memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_1;
+    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
+
+    serial_1.dma = usart_dma_1;
+    
+    serial_driver_1.drv_done = &drv_done;
+    serial_driver_1.configure = &Stm32SerialDrvConfigure;
+    serial_device_1.hwdev_done = &hwdev_done;
+
+    serial_cfg_1.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_1.uart_device = USART1;
+    serial_hw_cfg_1.irq = USART1_IRQn;
+    serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
+    serial_driver_1.private_data = (void *)&serial_cfg_1;
+
+    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
+
+    NVIC_Configuration(serial_hw_cfg_1.irq);
+
+    ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_USART2
+    static struct SerialCfgParam serial_cfg_2;
+    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_2;
+    memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_2;
+    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
+
+    serial_2.dma = usart_dma_2;
+    
+    serial_driver_2.drv_done = &drv_done;
+    serial_driver_2.configure = &Stm32SerialDrvConfigure;
+    serial_device_2.hwdev_done = &hwdev_done;
+
+    serial_cfg_2.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_2.uart_device = USART2;
+    serial_hw_cfg_2.irq = USART2_IRQn;
+    serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
+    serial_driver_2.private_data = (void *)&serial_cfg_2;
+
+    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
+
+    NVIC_Configuration(serial_hw_cfg_2.irq);
+
+    ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_USART3
+    static struct SerialCfgParam serial_cfg_3;
+    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_3;
+    memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_3;
+    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
+
+    serial_3.dma = usart_dma_3;
+    
+    serial_driver_3.drv_done = &drv_done;
+    serial_driver_3.configure = &Stm32SerialDrvConfigure;
+    serial_device_3.hwdev_done = &hwdev_done;
+
+    serial_cfg_3.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_3.uart_device = USART3;
+    serial_hw_cfg_3.irq = USART3_IRQn;
+    serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
+    serial_driver_3.private_data = (void *)&serial_cfg_3;
+
+    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
+
+    NVIC_Configuration(serial_hw_cfg_3.irq);
+
+    ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART4
+    static struct SerialCfgParam serial_cfg_4;
+    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_4;
+    memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_4;
+    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
+
+    serial_4.dma = uart_dma_4;
+    
+    serial_driver_4.drv_done = &drv_done;
+    serial_driver_4.configure = &Stm32SerialDrvConfigure;
+    serial_device_4.hwdev_done = &hwdev_done;
+
+    serial_cfg_4.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_4.uart_device = UART4;
+    serial_hw_cfg_4.irq = UART4_IRQn;
+    serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
+    serial_driver_4.private_data = (void *)&serial_cfg_4;
+
+    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
+
+    NVIC_Configuration(serial_hw_cfg_4.irq);
+
+    ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART5
+    static struct SerialCfgParam serial_cfg_5;
+    memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_5;
+    memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_5;
+    memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
+
+    serial_5.dma = uart_dma_5;
+    
+    serial_driver_5.drv_done = &drv_done;
+    serial_driver_5.configure = &Stm32SerialDrvConfigure;
+    serial_device_5.hwdev_done = &hwdev_done;
+
+    serial_cfg_5.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_5.uart_device = UART5;
+    serial_hw_cfg_5.irq = UART5_IRQn;
+    serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
+    serial_driver_5.private_data = (void *)&serial_cfg_5;
+
+    serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
+
+    NVIC_Configuration(serial_hw_cfg_5.irq);
+
+    ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+    return ret;
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210825135326.c

@@ -0,0 +1,858 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+/**
+* @file connect_usart.c
+* @brief support stm32f407-st-discovery-board usart function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_uart.c
+Description: support stm32f407-st-discovery-board usart configure and uart bus register function
+Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-st-discovery-board usart configure, write and read
+2. support stm32f407-st-discovery-board usart bus device and driver register
+*************************************************/
+
+#include "stm32f4xx.h"
+#include "board.h"
+#include "misc.h"
+#include "connect_usart.h"
+#include "hardware_gpio.h"
+#include "hardware_rcc.h"
+
+/* UART GPIO define. */
+#define UART1_GPIO_TX       GPIO_Pin_6
+#define UART1_TX_PIN_SOURCE GPIO_PinSource6
+#define UART1_GPIO_RX       GPIO_Pin_7
+#define UART1_RX_PIN_SOURCE GPIO_PinSource7
+#define UART1_GPIO          GPIOB
+#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOB
+#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
+
+#define UART2_GPIO_TX       GPIO_Pin_2
+#define UART2_TX_PIN_SOURCE GPIO_PinSource2
+#define UART2_GPIO_RX       GPIO_Pin_3
+#define UART2_RX_PIN_SOURCE GPIO_PinSource3
+#define UART2_GPIO          GPIOA
+#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
+#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
+
+#define UART3_GPIO_TX       GPIO_Pin_8
+#define UART3_TX_PIN_SOURCE GPIO_PinSource8
+#define UART3_GPIO_RX       GPIO_Pin_9
+#define UART3_RX_PIN_SOURCE GPIO_PinSource9
+#define UART3_GPIO          GPIOD
+#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
+
+#define UART4_GPIO_TX       GPIO_Pin_10
+#define UART4_TX_PIN_SOURCE GPIO_PinSource10
+#define UART4_GPIO_RX       GPIO_Pin_11
+#define UART4_RX_PIN_SOURCE GPIO_PinSource11
+#define UART4_GPIO          GPIOC
+#define UART4_GPIO_RCC      RCC_AHB1Periph_GPIOC
+#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
+
+#define UART5_GPIO_TX       GPIO_Pin_12
+#define UART5_TX_PIN_SOURCE GPIO_PinSource12
+#define UART5_GPIO_RX       GPIO_Pin_2
+#define UART5_RX_PIN_SOURCE GPIO_PinSource2
+#define UART5_TX            GPIOC
+#define UART5_RX            GPIOD
+#define UART5_GPIO_RCC_TX   RCC_AHB1Periph_GPIOC
+#define UART5_GPIO_RCC_RX   RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
+
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+static void RCCConfiguration(void)
+{
+#ifdef BSP_USING_USART1
+    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
+#endif
+
+#ifdef BSP_USING_USART2
+    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
+#endif
+
+#ifdef BSP_USING_USART3
+    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
+#endif
+
+#ifdef BSP_USING_UART4
+    RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
+#endif
+
+#ifdef BSP_USING_UART5
+    RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
+#endif
+}
+
+static void GPIOConfiguration(void)
+{
+    GPIO_InitTypeDef gpio_initstructure;
+
+    gpio_initstructure.GPIO_Mode  = GPIO_Mode_AF;
+    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
+    gpio_initstructure.GPIO_PuPd  = GPIO_PuPd_UP;
+    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
+
+#ifdef BSP_USING_USART1
+    gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
+    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
+    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);    
+    
+    GPIO_Init(UART1_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_USART2
+    gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
+    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
+    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
+    
+    GPIO_Init(UART2_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_USART3
+    gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
+    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
+    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
+    
+    GPIO_Init(UART3_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_UART4
+    gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
+    GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
+    GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
+    
+    GPIO_Init(UART4_GPIO, &gpio_initstructure);
+#endif
+
+#ifdef BSP_USING_UART5
+    gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
+    GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); 
+    GPIO_Init(UART5_TX, &gpio_initstructure);
+    
+    gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
+    GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
+    GPIO_Init(UART5_RX, &gpio_initstructure);
+#endif
+}
+
+static void NVIC_Configuration(IRQn_Type irq)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    NVIC_InitStructure.NVIC_IRQChannel = irq;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
+{   
+    DMA_InitTypeDef DMA_InitStructure;
+
+    dma->SettingRecvLen = SettingRecvLen;
+    DMA_DeInit(dma->RxStream);
+    while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
+    DMA_InitStructure.DMA_Channel = dma->RxCh;
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
+    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
+    DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
+    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
+    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
+    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
+    DMA_Init(dma->RxStream, &DMA_InitStructure);
+}
+
+static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
+{
+    struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
+
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
+
+    DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
+
+    DMA_ClearFlag(dma->RxStream, dma->RxFlag);
+    DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
+    USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
+    DMA_Cmd(dma->RxStream, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
+{
+    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
+    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
+
+    if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
+        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
+    }
+
+    if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
+        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
+    }
+
+    if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
+        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
+    }
+
+    if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
+        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
+    }
+
+    if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
+        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
+    }
+
+    if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
+        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
+    }
+
+    if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
+        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
+    }
+}
+
+static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (configure_info->private_data) {
+        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
+        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
+    }
+
+    USART_InitTypeDef USART_InitStructure;
+
+    USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
+
+    if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
+        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+    }
+
+    if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
+        USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
+        USART_InitStructure.USART_StopBits = USART_StopBits_2;
+    }
+
+    if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
+        USART_InitStructure.USART_Parity = USART_Parity_No;
+    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
+        USART_InitStructure.USART_Parity = USART_Parity_Odd;
+    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
+        USART_InitStructure.USART_Parity = USART_Parity_Even;
+    }
+
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
+
+    USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
+
+    return EOK;
+}
+
+static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+    switch (serial_operation_cmd)
+    {
+        case OPER_CLR_INT:
+            UART_DISABLE_IRQ(serial_hw_cfg->irq);
+            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
+            break;
+        case OPER_SET_INT:
+            UART_ENABLE_IRQ(serial_hw_cfg->irq);
+            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
+            break;
+        case OPER_CONFIG :
+            if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
+                DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
+            }
+    }
+
+    return EOK;
+}
+
+static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
+    serial_hw_cfg->uart_device->DR = c;
+
+    return EOK;
+}
+
+static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    int ch = -1;
+    if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
+        ch = serial_hw_cfg->uart_device->DR & 0xff;
+    }
+
+    return ch;
+}
+
+static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
+{
+    x_base level = CriticalAreaLock();
+
+    x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
+    x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
+    dma->LastRecvIndex = recv_total_index;
+    CriticalAreaUnLock(level);
+
+    if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+
+    USART_ReceiveData(uart_device);
+}
+
+static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
+{
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
+        x_base level = CriticalAreaLock();
+
+        x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
+        dma->LastRecvIndex = 0;
+        CriticalAreaUnLock(level);
+
+        if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+
+        DMA_ClearFlag(dma->RxStream, dma->RxFlag);
+    }
+}
+
+static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
+{
+    struct Stm32UsartDma *dma = &serial->dma; 
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
+
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
+        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
+        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
+    }
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
+        DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
+    }
+    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
+        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
+    }
+    if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
+        USART_ReceiveData(serial_hw_cfg->uart_device);
+    }
+}
+
+#ifdef BSP_USING_USART1
+struct Stm32Usart serial_1;
+struct SerialDriver serial_driver_1;
+struct SerialHardwareDevice serial_device_1;
+
+static const struct Stm32UsartDma usart_dma_1 =
+{
+    DMA2_Stream5,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF5,
+    DMA2_Stream5_IRQn,
+    0,
+    0,
+};
+
+void USART1_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
+}
+DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
+
+void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
+}
+DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_USART2
+struct Stm32Usart serial_2;
+struct SerialDriver serial_driver_2;
+struct SerialHardwareDevice serial_device_2;
+
+static const struct Stm32UsartDma usart_dma_2 =
+{
+    DMA1_Stream5,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF5,
+    DMA1_Stream5_IRQn,
+    0,
+    0,
+};
+
+void USART2_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
+}
+DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
+
+void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
+}
+DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_USART3
+struct Stm32Usart serial_3;
+struct SerialDriver serial_driver_3;
+struct SerialHardwareDevice serial_device_3;
+
+static const struct Stm32UsartDma usart_dma_3 =
+{
+    DMA1_Stream1,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF1,
+    DMA1_Stream1_IRQn,
+    0,
+    0,
+};
+
+void USART3_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
+}
+DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
+
+void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
+}
+DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_UART4
+struct Stm32Usart serial_4;
+struct SerialDriver serial_driver_4;
+struct SerialHardwareDevice serial_device_4;
+
+static const struct Stm32UsartDma uart_dma_4 =
+{
+    DMA1_Stream2,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF2,
+    DMA1_Stream2_IRQn,
+    0,
+    0,
+};
+
+void UART4_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
+}
+DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
+
+void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
+}
+DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
+#endif
+
+#ifdef BSP_USING_UART5
+struct Stm32Usart serial_5;
+struct SerialDriver serial_driver_5;
+struct SerialHardwareDevice serial_device_5;
+
+static const struct Stm32UsartDma uart_dma_5 =
+{
+    DMA1_Stream0,
+    DMA_Channel_4,
+    DMA_FLAG_TCIF0,
+    DMA1_Stream0_IRQn,
+    0,
+    0,
+};
+
+void UART5_IRQHandler(int irq_num, void *arg)
+{
+    UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
+}
+DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
+
+void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
+    DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
+}
+DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
+#endif
+
+static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    int serial_operation_cmd;
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = Stm32SerialInit(serial_drv, configure_info);
+            break;
+        case OPE_CFG:
+            serial_operation_cmd = *(int *)configure_info->private_data;
+            ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct SerialDataCfg data_cfg_init = 
+{
+    .serial_baud_rate = BAUD_RATE_115200,
+    .serial_data_bits = DATA_BITS_8,
+    .serial_stop_bits = STOP_BITS_1,
+    .serial_parity_mode = PARITY_NONE,
+    .serial_bit_order = BIT_ORDER_LSB,
+    .serial_invert_mode = NRZ_NORMAL,
+    .serial_buffer_size = SERIAL_RB_BUFSZ,
+};
+
+/*manage the serial device operations*/
+static const struct SerialDrvDone drv_done =
+{
+    .init = Stm32SerialInit,
+    .configure = Stm32SerialConfigure,
+};
+
+/*manage the serial device hal operations*/
+static struct SerialHwDevDone hwdev_done =
+{
+    .put_char = Stm32SerialPutchar,
+    .get_char = Stm32SerialGetchar,
+};
+
+static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the serial bus */
+    ret = SerialBusInit(serial_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the serial driver*/
+    ret = SerialDriverInit(serial_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the serial driver to the serial bus*/
+    ret = SerialDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the serial device to the serial bus*/
+static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
+{
+    x_err_t ret = EOK;
+
+    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    ret = SerialDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+int InitHwUsart(void)
+{
+    x_err_t ret = EOK;
+
+    RCCConfiguration();
+    GPIOConfiguration();
+
+#ifdef BSP_USING_USART1
+    static struct SerialCfgParam serial_cfg_1;
+    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_1;
+    memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_1;
+    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
+
+    serial_1.dma = usart_dma_1;
+    
+    serial_driver_1.drv_done = &drv_done;
+    serial_driver_1.configure = &Stm32SerialDrvConfigure;
+    serial_device_1.hwdev_done = &hwdev_done;
+
+    serial_cfg_1.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_1.uart_device = USART1;
+    serial_hw_cfg_1.irq = USART1_IRQn;
+    serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
+    serial_driver_1.private_data = (void *)&serial_cfg_1;
+
+    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
+
+    NVIC_Configuration(serial_hw_cfg_1.irq);
+
+    ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_USART2
+    static struct SerialCfgParam serial_cfg_2;
+    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_2;
+    memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_2;
+    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
+
+    serial_2.dma = usart_dma_2;
+    
+    serial_driver_2.drv_done = &drv_done;
+    serial_driver_2.configure = &Stm32SerialDrvConfigure;
+    serial_device_2.hwdev_done = &hwdev_done;
+
+    serial_cfg_2.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_2.uart_device = USART2;
+    serial_hw_cfg_2.irq = USART2_IRQn;
+    serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
+    serial_driver_2.private_data = (void *)&serial_cfg_2;
+
+    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
+
+    NVIC_Configuration(serial_hw_cfg_2.irq);
+
+    ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_USART3
+    static struct SerialCfgParam serial_cfg_3;
+    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_3;
+    memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_3;
+    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
+
+    serial_3.dma = usart_dma_3;
+    
+    serial_driver_3.drv_done = &drv_done;
+    serial_driver_3.configure = &Stm32SerialDrvConfigure;
+    serial_device_3.hwdev_done = &hwdev_done;
+
+    serial_cfg_3.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_3.uart_device = USART3;
+    serial_hw_cfg_3.irq = USART3_IRQn;
+    serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
+    serial_driver_3.private_data = (void *)&serial_cfg_3;
+
+    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
+
+    NVIC_Configuration(serial_hw_cfg_3.irq);
+
+    ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART4
+    static struct SerialCfgParam serial_cfg_4;
+    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_4;
+    memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_4;
+    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
+
+    serial_4.dma = uart_dma_4;
+    
+    serial_driver_4.drv_done = &drv_done;
+    serial_driver_4.configure = &Stm32SerialDrvConfigure;
+    serial_device_4.hwdev_done = &hwdev_done;
+
+    serial_cfg_4.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_4.uart_device = UART4;
+    serial_hw_cfg_4.irq = UART4_IRQn;
+    serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
+    serial_driver_4.private_data = (void *)&serial_cfg_4;
+
+    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
+
+    NVIC_Configuration(serial_hw_cfg_4.irq);
+
+    ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART5
+    static struct SerialCfgParam serial_cfg_5;
+    memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
+
+    static struct UsartHwCfg serial_hw_cfg_5;
+    memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
+
+    static struct SerialDevParam serial_dev_param_5;
+    memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
+
+    serial_5.dma = uart_dma_5;
+    
+    serial_driver_5.drv_done = &drv_done;
+    serial_driver_5.configure = &Stm32SerialDrvConfigure;
+    serial_device_5.hwdev_done = &hwdev_done;
+
+    serial_cfg_5.data_cfg = data_cfg_init;
+
+    serial_hw_cfg_5.uart_device = UART5;
+    serial_hw_cfg_5.irq = UART5_IRQn;
+    serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
+    serial_driver_5.private_data = (void *)&serial_cfg_5;
+
+    serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
+
+    NVIC_Configuration(serial_hw_cfg_5.irq);
+
+    ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+    return ret;
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825132156.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_STM32F407_EVB
+#define ARCH_ARM
+
+/*  stm32f407-st-discovery feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140658.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  stm32f407-st-discovery feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140659.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  stm32f407-st-discovery feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140738.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  stm32f407-st-discovery feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140837.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  stm32f407-st-discovery feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140856.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  BOARD_CORTEX_M4_EVB feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140900.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  BOARD_CORTEX_M4_EVB feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140901.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  BOARD_CORTEX_M4_EVB feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140902.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  BOARD_CORTEX_M4_EVB feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140903.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  BOARD_CORTEX_M4_EVB feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140904.h

@@ -0,0 +1,185 @@
+#ifndef XS_CONFIG_H__
+#define XS_CONFIG_H__
+
+/*  Automatically generated file; DO NOT EDIT. */
+/*  XiUOS Project Configuration */
+
+#define BOARD_CORTEX_M4_EVB
+#define ARCH_ARM
+
+/*  BOARD_CORTEX_M4_EVB feature */
+
+#define BSP_USING_DMA
+#define BSP_USING_GPIO
+#define PIN_BUS_NAME "pin"
+#define PIN_DRIVER_NAME "pin_drv"
+#define PIN_DEVICE_NAME "pin_dev"
+#define BSP_USING_UART
+#define BSP_USING_USART1
+#define SERIAL_BUS_NAME_1 "usart1"
+#define SERIAL_DRV_NAME_1 "usart1_drv"
+#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
+#define BSP_USING_USART2
+#define SERIAL_BUS_NAME_2 "usart2"
+#define SERIAL_DRV_NAME_2 "usart2_drv"
+#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
+#define BSP_USING_USART3
+#define SERIAL_BUS_NAME_3 "usart3"
+#define SERIAL_DRV_NAME_3 "usart3_drv"
+#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
+#define BSP_USING_WDT
+#define WDT_BUS_NAME "wdt"
+#define WDT_DRIVER_NAME "wdt_drv"
+#define WDT_DEVICE_NAME "wdt_dev"
+
+/*  config default board resources */
+
+/*  config board app name */
+
+#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
+
+/*  config board service table */
+
+#define SERVICE_TABLE_ADDRESS 0x20000000
+
+/*  config hardware resources for connection */
+
+/*  Hardware feature */
+
+#define RESOURCES_SERIAL
+#define SERIAL_USING_DMA
+#define SERIAL_RB_BUFSZ 128
+#define RESOURCES_PIN
+#define RESOURCES_WDT
+
+/*  Kernel feature */
+
+/*  separate compile(choose none for compile once) */
+
+#define APP_STARTUP_FROM_FLASH
+
+/*  Memory Management */
+
+#define MEM_ALIGN_SIZE 8
+#define MM_PAGE_SIZE 4096
+
+/*  Using small memory allocator */
+
+#define KERNEL_SMALL_MEM_ALLOC
+#define SMALL_NUMBER_32B 64
+#define SMALL_NUMBER_64B 32
+
+/*  Task feature */
+
+#define USER_APPLICATION
+
+/*  Inter-Task communication */
+
+#define KERNEL_SEMAPHORE
+#define KERNEL_MUTEX
+#define KERNEL_EVENT
+#define KERNEL_MESSAGEQUEUE
+#define KERNEL_SOFTTIMER
+#define SCHED_POLICY_RR_REMAINSLICE
+#define KTASK_PRIORITY_32
+#define KTASK_PRIORITY_MAX 32
+#define TICK_PER_SECOND 1000
+#define KERNEL_STACK_OVERFLOW_CHECK
+#define IDLE_KTASK_STACKSIZE 256
+#define ZOMBIE_KTASK_STACKSIZE 2048
+
+/*  Kernel Console */
+
+#define KERNEL_CONSOLE
+#define KERNEL_BANNER
+#define KERNEL_CONSOLEBUF_SIZE 128
+
+/*  Kernel Hook */
+
+
+/*  Command shell */
+
+#define TOOL_SHELL
+#define SHELL_ENTER_CR
+#define SHELL_ENTER_LF
+#define SHELL_ENTER_CR_AND_LF
+
+/*  Set shell user control */
+
+#define SHELL_DEFAULT_USER "letter"
+#define SHELL_DEFAULT_USER_PASSWORD ""
+#define SHELL_LOCK_TIMEOUT 10000
+
+/*  Set shell config param */
+
+#define SHELL_TASK_STACK_SIZE 4096
+#define SHELL_TASK_PRIORITY 20
+#define SHELL_MAX_NUMBER 5
+#define SHELL_PARAMETER_MAX_NUMBER 8
+#define SHELL_HISTORY_MAX_NUMBER 5
+#define SHELL_PRINT_BUFFER 128
+#define SHELL_HELP_SHOW_PERMISSION
+
+/*  Kernel data structure Manage */
+
+#define KERNEL_QUEUEMANAGE
+#define KERNEL_WORKQUEUE
+#define WORKQUEUE_KTASK_STACKSIZE 512
+#define WORKQUEUE_KTASK_PRIORITY 23
+#define QUEUE_MAX 16
+#define KERNEL_WAITQUEUE
+#define KERNEL_DATAQUEUE
+
+/*  Kernel components init */
+
+#define KERNEL_COMPONENTS_INIT
+#define ENV_INIT_KTASK_STACK_SIZE 8192
+#define KERNEL_USER_MAIN
+#define NAME_NUM_MAX 32
+
+/*  hash table config */
+
+#define ID_HTABLE_SIZE 16
+#define ID_NUM_MAX 128
+
+/*  File system */
+
+#define FS_VFS
+#define VFS_USING_WORKDIR
+#define FS_VFS_DEVFS
+#define FS_VFS_FATFS
+
+/*  APP Framework */
+
+/*  Perception */
+
+
+/*  connection */
+
+
+/*  Intelligence */
+
+
+/*  Control */
+
+/*  Lib */
+
+#define LIB
+#define LIB_POSIX
+
+/*  C++ features */
+
+#define LIB_NEWLIB
+
+/*  Security */
+
+
+/*  Applications */
+
+
+/*  config stack size and priority of main task */
+
+#define MAIN_KTASK_STACK_SIZE 2048
+#define MAIN_KTASK_PRIORITY 10
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/Kconfig

@@ -0,0 +1,59 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M4_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m4-emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+    
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_cortex-m4-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x20000000
+        endmenu
+
+        menu "config hardware resources for connection"
+            if CONNECTION_COMMUNICATION_ETHERNET
+                config ETHERNET_UART_NAME
+                    string "ethernet uart name"
+                    default "/dev/usart3_dev3"
+            endif
+            if CONNECTION_COMMUNICATION_WIFI
+                config WIFI_UART_NAME
+                    string "wifi uart name"
+                    default "/dev/usart3_dev3"
+            endif
+
+        endmenu
+
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/Makefile

@@ -0,0 +1,8 @@
+SRC_FILES := board.c
+
+SRC_DIR := third_party_driver
+
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/cortex-m4-emulator/README.md

@@ -0,0 +1,213 @@
+# 从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F407-discovery开发板
+
+[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。
+
+>注：最新版README请访问[从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F407-discovery开发板](https://blog.csdn.net/AIIT_Ubiquitous/article/details/116209686)，如博客内容与本地文档有差异，以网站内容为准。
+
+## 开发环境搭建
+
+### 推荐使用：
+
+**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
+
+更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
+
+第一步:打开sources.list文件
+
+```c
+sudo vim /etc/apt/sources.list
+```
+
+第二步:将以下内容复制到sources.list文件
+
+```c
+deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+```
+
+第三步:更新源和系统软件
+
+```c
+sudo apt-get update
+sudo apt-get upgrade
+```
+
+**开发工具推荐使用 VSCode   ，VScode下载地址为：** VSCode  [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
+
+### 依赖包安装：
+
+```
+$ sudo apt install build-essential pkg-config  git
+$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
+```
+
+**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+
+新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
+
+```c
+mkdir test  &&  cd test
+git clone https://git.trustie.net/xuos/xiuos.git
+```
+
+打开源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| application | 应用代码 |
+| board | 板级支持包 |
+| framework | 应用框架 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |
+
+使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
+
+<div align= "center"> 
+<img src = img/vscode.jpg  width =1000>
+  </div>
+
+### 裁减配置工具的下载
+
+裁减配置工具：
+
+**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+
+```c
+mkdir kfrontends  && cd kfrontends
+git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+```
+
+下载源码后按以下步骤执行软件安装：
+
+```c
+cd kconfig-frontends
+ ./xs_build.sh
+```
+
+### 编译工具链：
+
+ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
+
+```shell
+$ sudo apt install gcc-arm-none-eabi
+```
+
+# 在STM32F407-DISCOVERY上创建第一个应用 --helloworld
+
+## 1. 简介
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| Stm32F407VGT6|
+|CPU|arm cortex-m|
+|主频| 168MHz |
+|片内SRAM| 192KB |
+|片上FLASH| 1MB |
+| 外设 | -- |
+| | ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、CAN、DMA、MAC、I²C、WDT、Timer等 |
+
+XiUOS板级驱动当前支持使用GPIO、I2C、LCD、USB、RTC、SPI、Timer、UART和WDT等。
+
+## 2. 编译说明
+
+### 编辑环境：`Ubuntu18.04`
+
+### 编译工具链：`arm-none-eabi-gcc`
+使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
+
+修改`applications`文件夹下`main.c`
+在输出函数中写入 `Hello, world!!! \n   Running on stm32f407-st-discovery`完成代码编辑。
+
+![main](img/main.png)
+
+编译步骤：
+
+1.在VScode命令终端中执行以下命令，生成配置文件
+
+```c
+   make BOARD=stm32f407-st-discovery menuconfig
+```
+
+2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
+
+![menuconfig1](img/menuconfig1.png)
+
+退出时选择`yes`保存上面所配置的内容，如下图所示：
+
+![menuconfig2](img/menuconfig2.jpg)
+
+3.继续执行以下命令，进行编译
+
+```c
+make BOARD=stm32f407-st-discovery
+```
+
+4.如果编译正确无误，会产生XiUOS_stm32f407-st-discovery.elf、XiUOS_stm32f407-st-discovery.bin文件。其中XiUOS_stm32f407-st-discovery.bin需要烧写到设备中进行运行。
+
+## 3. 烧写及执行
+
+将 BOARD=stm32f407-st-discovery开发板SWD经 st-link 转接到USB接口，然后使用st-flash工具进行烧写bin文件。
+
+![stm32f407-st-discovery](img/stm32f407-st-discovery.png)
+
+### 烧写工具
+
+ARM：ST-LINK（ST-LINK V2实物如图，可在购物网站搜索关键字购买）
+
+![st-link](img/st-link.png)
+
+下载并以下执行命令以下命令安装st-link工具(本文使用v1.5.1版本)，下载地址为：[http://101.36.126.201:8011/stlink.zip](http://101.36.126.201:8011/stlink.zip)
+
+```
+sudo apt install libusb-dev
+sudo apt install libusb-1.0-0-dev
+sudo apt  install cmake
+cd stlink
+make
+cd build/Release && make install DESTDIR=_install
+```
+
+将生成的st-flash（在stlink/build/Release/bin文件夹下）复制到/usr/bin下就可使用了
+
+代码根目录下执行st-flash工具烧录
+
+```
+sudo st-flash  write  build/XiUOS_stm32f407-st-discovery.bin 0x8000000
+```
+
+此外，推荐用户使用putty作为终端工具，安装命令如下：
+
+```c
+sudo apt install  putty
+```
+
+打开putty配置串口信息
+
+```c
+sudo puty
+```
+
+选择ttyUSB0（这个端口号根据具体情况而定），配置波特率为115200。
+
+![putty](img/putty.png)
+
+注意：选择正确的终端端口号，最后可以执行以下命令，清除配置文件和编译生成的文件
+
+```c
+make  BOARD=stm32f407-st-discovery distclean
+```
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端串口引脚为PB6、PB7)。
+
+![terminal](img/terminal.png)

Ubiquitous/XiUOS/board/cortex-m4-emulator/board.c

@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support cortex-m4-emulator-board init configure and start-up
+* @version 1.0 
+* @author fudan
+* @date 2021-08-26
+*/
+
+/*************************************************
+File name: board.c
+Description: support cortex-m4-emulator-board init configure and driver/task/... init
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support cortex-m4-emulator-board InitBoardHardware
+*************************************************/
+
+#include <xiuos.h>
+#include "hardware_rcc.h"
+#include "board.h"
+#include "connect_usart.h"
+#include "misc.h"
+#include <xs_service.h>
+
+
+
+static void ClockConfiguration()
+{
+    int cr,cfgr,pllcfgr;
+    int cr1,cfgr1,pllcfgr1;
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_VOS;
+    RCC_HSEConfig(RCC_HSE_ON);
+    if (RCC_WaitForHSEStartUp() == SUCCESS)
+    {
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+        RCC_PCLK2Config(RCC_HCLK_Div2);
+        RCC_PCLK1Config(RCC_HCLK_Div4);
+        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
+
+        RCC_PLLCmd(ENABLE);
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
+
+        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    }
+    SystemCoreClockUpdate();
+}
+
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+void  SysTickConfiguration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    uint32         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+
+    TickAndTaskTimesliceUpdate();
+
+}
+DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
+
+
+void InitBoardHardware()
+{
+	int i = 0;
+	int ret = 0;
+    ClockConfiguration();
+
+    NVIC_Configuration();
+
+    SysTickConfiguration();
+#ifdef BSP_USING_UART
+	Stm32HwUsartInit();
+#endif
+#ifdef KERNEL_CONSOLE
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+    RCC_ClocksTypeDef  rcc_clocks;
+    RCC_GetClocksFreq(&rcc_clocks);
+    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
+
+    KPrintf("\nconsole init completed.\n");
+    KPrintf("board initialization......\n");
+#endif
+    
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+	
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/board.h

@@ -0,0 +1,78 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define cortex-m4-emulator-board init configure and start-up function
+* @version 1.0 
+* @author AIIT fudan Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: board.h
+Description: define cortex-m4-emulator-board board init function and struct
+Others: 
+History: 
+1. Date: 2021-08-25
+Author: AIIT fudan Lab
+Modification: 
+1. define cortex-m4-emulator-board InitBoardHardware
+2. define cortex-m4-emulator-board data and bss struct
+*************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include <stdint.h>
+
+extern int __stack_end__;
+extern unsigned int g_service_table_start;
+extern unsigned int g_service_table_end;
+
+#define SURPORT_MPU
+
+#define MEMORY_START_ADDRESS (&__stack_end__)
+#define MEM_OFFSET         128
+#define MEMORY_END_ADDRESS      (0x20000000 + MEM_OFFSET * 1024)
+
+
+#ifdef SEPARATE_COMPILE
+typedef int (*main_t)(int argc, char *argv[]);
+typedef void (*exit_t)(void);
+struct userspace_s
+{
+  main_t    us_entrypoint;
+  exit_t    us_taskquit;
+  uintptr_t us_textstart;
+  uintptr_t us_textend;
+  uintptr_t us_datasource;
+  uintptr_t us_datastart;
+  uintptr_t us_dataend;
+  uintptr_t us_bssstart;
+  uintptr_t us_bssend;
+  uintptr_t us_heapend;
+};
+#define USERSPACE (( struct userspace_s *)(0x08080000))
+
+#ifndef SERVICE_TABLE_ADDRESS
+#define SERVICE_TABLE_ADDRESS    (0x20000000)
+#endif
+
+#define USER_SRAM_SIZE         64
+#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
+#define USER_MEMORY_END_ADDRESS   (0x10000000 + USER_SRAM_SIZE * 1024)
+#endif
+
+void InitBoardHardware(void);
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/config.mk

@@ -0,0 +1,17 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
+export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_cortex-m4-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
+
+export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
+
+export USING_NEWLIB =1
+export USING_VFS = 1
+export USING_SPI = 1
+export ARCH = arm
+export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/arm_common_tables.h

@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/cmsis_armcc.h

@@ -0,0 +1,720 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/cmsis_os.h

@@ -0,0 +1,707 @@
+/* ----------------------------------------------------------------------
+ * $Date:        5. February 2013
+ * $Revision:    V1.02
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h template header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedef's
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+ 
+ 
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+ 
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
+ 
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
+ 
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
+ 
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
+#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
+#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore    30      ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
+ 
+#include <stdint.h>
+#include <stddef.h>
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+// ==== Enumeration, structures, defines ====
+ 
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osPriorityIdle          = -3,          ///< priority: idle (lowest)
+  osPriorityLow           = -2,          ///< priority: low
+  osPriorityBelowNormal   = -1,          ///< priority: below normal
+  osPriorityNormal        =  0,          ///< priority: normal (default)
+  osPriorityAboveNormal   = +1,          ///< priority: above normal
+  osPriorityHigh          = +2,          ///< priority: high
+  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
+  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+ 
+/// Timeout value.
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osOK                    =     0,       ///< function completed; no error or event occurred.
+  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
+  osEventMessage          =  0x10,       ///< function completed; message event occurred.
+  osEventMail             =  0x20,       ///< function completed; mail event occurred.
+  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
+  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
+  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
+  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
+  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
+  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
+} osStatus;
+ 
+ 
+/// Timer type value for the timer definition.
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osTimerOnce             =     0,       ///< one-shot timer
+  osTimerPeriodic         =     1        ///< repeating timer
+} os_timer_type;
+ 
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+ 
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+ 
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+ 
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_cb *osThreadId;
+ 
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_cb *osTimerId;
+ 
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_cb *osMutexId;
+ 
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_cb *osSemaphoreId;
+ 
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+ 
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_cb *osMessageQId;
+ 
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+ 
+ 
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_def  {
+  os_pthread               pthread;    ///< start address of thread function
+  osPriority             tpriority;    ///< initial thread priority
+  uint32_t               instances;    ///< maximum number of instances of that thread function
+  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+ 
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_def  {
+  os_ptimer                 ptimer;    ///< start address of a timer function
+} osTimerDef_t;
+ 
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_def  {
+  uint32_t                   dummy;    ///< dummy value.
+} osMutexDef_t;
+ 
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_def  {
+  uint32_t                   dummy;    ///< dummy value.
+} osSemaphoreDef_t;
+ 
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_def  {
+  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< pointer to memory for pool
+} osPoolDef_t;
+ 
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< memory array for messages
+} osMessageQDef_t;
+ 
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< memory array for mail
+} osMailQDef_t;
+ 
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+///       However the struct may be extended at the end.
+typedef struct  {
+  osStatus                 status;     ///< status code: event or error information
+  union  {
+    uint32_t                    v;     ///< message as 32-bit value
+    void                       *p;     ///< message or mail as void pointer
+    int32_t               signals;     ///< signal flags
+  } value;                             ///< event value
+  union  {
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
+  } def;                               ///< event definition
+} osEvent;
+ 
+ 
+//  ==== Kernel Control Functions ====
+ 
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+osStatus osKernelInitialize (void);
+ 
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (void);
+ 
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+ 
+#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
+ 
+/// Get the RTOS kernel system timer counter 
+/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+/// \return RTOS kernel system timer as 32-bit value 
+uint32_t osKernelSysTick (void);
+ 
+/// The RTOS kernel system timer frequency in Hz
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#define osKernelSysTickFrequency 100000000
+ 
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+ 
+#endif    // System Timer available
+ 
+//  ==== Thread Management ====
+ 
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name         name of the thread function.
+/// \param         priority     initial priority of the thread function.
+/// \param         instances    number of possible thread instances.
+/// \param         stacksz      stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, instances, stacksz)  \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#define osThreadDef(name, priority, instances, stacksz)  \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz)  }
+#endif
+ 
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name)  \
+&os_thread_def_##name
+ 
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+ 
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+ 
+/// Change priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+ 
+/// Get current priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+ 
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
+ 
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+osEvent osWait (uint32_t millisec);
+ 
+#endif  // Generic Wait available
+ 
+ 
+//  ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function)  \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#define osTimerDef(name, function)  \
+const osTimerDef_t os_timer_def_##name = \
+{ (function) }
+#endif
+ 
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+ 
+/// Create a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+ 
+/// Stop the timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+ 
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+osStatus osTimerDelete (osTimerId timer_id);
+ 
+ 
+//  ==== Signal Management ====
+ 
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+ 
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+ 
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+ 
+ 
+//  ==== Mutex Management ====
+ 
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name)  \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#define osMutexDef(name)  \
+const osMutexDef_t os_mutex_def_##name = { 0 }
+#endif
+ 
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name)  \
+&os_mutex_def_##name
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+ 
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+ 
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+ 
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+osStatus osMutexDelete (osMutexId mutex_id);
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
+ 
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name)  \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#define osSemaphoreDef(name)  \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#endif
+ 
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name)  \
+&os_semaphore_def_##name
+ 
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+ 
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+ 
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+ 
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+ 
+#endif     // Semaphore available
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+ 
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
+ 
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type)   \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type)   \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#endif
+ 
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+ 
+/// Create and Initialize a memory pool.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+ 
+/// Allocate a memory block from a memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+ 
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+ 
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+ 
+#endif   // Memory Pool Management available
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
+ 
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type)   \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#define osMessageQDef(name, queue_sz, type)   \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type)  }
+#endif
+ 
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+ 
+/// Create and Initialize a Message Queue.
+/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+ 
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+ 
+#endif     // Message Queues available
+ 
+ 
+//  ==== Mail Queue Management Functions ====
+ 
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
+ 
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \param         queue_sz      maximum number of messages in queue
+/// \param         type          data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof (type) }
+#endif
+ 
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+ 
+/// Create and Initialize mail queue.
+/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Allocate a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Put a mail to a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+ 
+/// Get a mail from a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+ 
+/// Free a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+ 
+#endif  // Mail Queues available
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // _CMSIS_OS_H

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/core_cmFunc.h

@@ -0,0 +1,79 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+
+
+
+/*------------------ GNU Compiler ----------------------*/
+#if defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/core_cmInstr.h

@@ -0,0 +1,78 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+
+
+/*------------------ GNU Compiler ----------------------*/
+#if defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/core_cmSimd.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+
+
+/*------------------ GNU Compiler ----------------------*/
+#if defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

Ubiquitous/XiUOS/board/cortex-m4-emulator/include/system_stm32f4xx.h

@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since system_core_clock
+               variable is updated automatically.
+  */
+extern uint32_t system_core_clock;          /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  ahb_presc_table[16];    /*!< AHB prescalers table values */
+extern const uint8_t  apb_presc_table[8];     /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/cortex-m4-emulator/link.lds

@@ -0,0 +1,109 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+__SYSTEM_STACKSIZE__ = 0x400;
+
+OUTPUT_ARCH(arm)
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
+    sram (rw) : ORIGIN = 0x20001000, LENGTH =  124k  /* 124k sram */
+}
+
+ENTRY(Reset_Handler)
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        PROVIDE(_stext = ABSOLUTE(.));
+        KEEP(*(.isr_vector))                   /* Startup code */
+
+
+        . = ALIGN(4);
+        *(.text .text.*)                        /* Normal code */
+        *(.rodata .rodata*)                     /* read-only data (constants) */
+
+        *(.glue_7)
+        *(.glue_7t)
+
+        /* section information for  shell */
+        . = ALIGN(4);
+        _shell_command_start = .;
+        KEEP (*(shellCommand))
+        _shell_command_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        
+        __isrtbl_idx_start = .;
+        KEEP(*(.isrtbl.idx))
+        __isrtbl_start = .;
+        KEEP(*(.isrtbl))
+        __isrtbl_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(g_service_table_start = ABSOLUTE(.));
+        KEEP(*(.g_service_table))
+        PROVIDE(g_service_table_end = ABSOLUTE(.));
+
+        PROVIDE(_etext =  ABSOLUTE(.));
+    } > flash
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        PROVIDE(__exidx_start = ABSOLUTE(.));
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        _sidata = .;
+        PROVIDE(__exidx_end = ABSOLUTE(.));
+    } > flash
+
+    .data : AT(__exidx_end)
+    {
+        . = ALIGN(4);
+        PROVIDE(_sdata = ABSOLUTE(.));
+        *(.data .data.*)
+        PROVIDE(_edata = ABSOLUTE(.));
+    } > sram
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start = ABSOLUTE(.);
+
+        *(.bss .bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end = ABSOLUTE(.);
+    } > sram
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        PROVIDE(__stack_start__ = ABSOLUTE(.));
+        /* cpu stack */
+        . = . + __SYSTEM_STACKSIZE__;
+        __stack_tp = .;
+        PROVIDE(__stack_end__ = ABSOLUTE(.));
+    } > sram
+
+    _end = ABSOLUTE(.);
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/link_userspace.lds

@@ -0,0 +1,72 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+OUTPUT_ARCH(arm)
+
+MEMORY
+{
+    uflash (rx) : ORIGIN = 0x08080000, LENGTH = 512k /* 512KB uflash */
+    usram (rw)  : ORIGIN = 0x10000000, LENGTH =  64k  /* 64K usram */
+}
+
+SECTIONS
+{
+    .userspace : 
+    {
+        _ustext = ABSOLUTE(.);
+        . = ALIGN(4);
+        KEEP(*(.userspace))
+    } > uflash
+
+    .text : 
+    {
+        *(.text .text.*)
+        *(.rodata .rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        PROVIDE(_uetext = ABSOLUTE(.));
+    } > uflash
+    
+    .init_section : {
+        _sinit = ABSOLUTE(.);
+        KEEP(*(.init_array .init_array.*))
+        _einit = ABSOLUTE(.);
+    } > uflash
+
+    __uexidx_start = ABSOLUTE(.);
+
+    .ARM.exidx :
+    {
+        PROVIDE(__uexidx_start = ABSOLUTE(.));
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__uexidx_end = ABSOLUTE(.));
+    } > uflash
+
+    _ueronly = ABSOLUTE(.);
+
+    .data : AT(_ueronly)
+    {
+        _usdata = ABSOLUTE(.);
+        *(.data .data.*)
+        . = ALIGN(4);
+        _uedata = ABSOLUTE(.);
+    } > usram 
+
+    .bss : {
+        . = ALIGN(4);
+        _usbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.sbss .sbss.*)
+        . = ALIGN(4);
+        _uebss = ABSOLUTE(.);
+    } > usram
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/Kconfig

@@ -0,0 +1,105 @@
+menuconfig BSP_USING_CAN
+bool "Using CAN device"
+default n
+select RESOURCES_CAN
+if BSP_USING_CAN
+source "$BSP_DIR/third_party_driver/can/Kconfig"
+endif
+
+menuconfig BSP_USING_DMA
+bool "Using DMA device"
+default y
+if BSP_USING_DMA
+source "$BSP_DIR/third_party_driver/common/Kconfig"
+endif
+
+menuconfig BSP_USING_GPIO
+bool "Using GPIO device "
+default y
+select RESOURCES_PIN
+if BSP_USING_GPIO
+source "$BSP_DIR/third_party_driver/gpio/Kconfig"
+endif
+
+menuconfig BSP_USING_I2C
+bool "Using I2C device"
+default n
+select RESOURCES_I2C
+if BSP_USING_I2C
+source "$BSP_DIR/third_party_driver/i2c/Kconfig"
+endif
+
+menuconfig BSP_USING_LCD
+bool "Using LCD device"
+default n
+select BSP_USING_SPI1
+select RESOURCES_LCD
+if BSP_USING_LCD
+source "$BSP_DIR/third_party_driver/lcd/Kconfig"
+endif
+
+menuconfig BSP_USING_RTC
+bool "Using RTC device"
+default n
+select RESOURCES_RTC
+if BSP_USING_RTC
+source "$BSP_DIR/third_party_driver/rtc/Kconfig"
+endif
+
+menuconfig BSP_USING_SDIO
+bool "Using SDIO device"
+default n
+select RESOURCES_SDIO
+if BSP_USING_SDIO
+source "$BSP_DIR/third_party_driver/sdio/Kconfig"
+endif
+
+menuconfig BSP_USING_SPI
+bool "Using SPI device"
+default n
+select RESOURCES_SPI
+select BSP_USING_DMA
+if BSP_USING_SPI
+source "$BSP_DIR/third_party_driver/spi/Kconfig"
+endif
+
+menuconfig BSP_USING_HWTIMER
+bool "Using HWTIMER device"
+default n
+select RESOURCES_HWTIMER
+if BSP_USING_HWTIMER
+source "$BSP_DIR/third_party_driver/timer/Kconfig"
+endif
+
+menuconfig BSP_USING_UART
+bool "Using UART device"
+default y
+select RESOURCES_SERIAL
+if BSP_USING_UART
+source "$BSP_DIR/third_party_driver/uart/Kconfig"
+endif
+
+menuconfig BSP_USING_USB
+bool "Using USB device"
+default n
+select BSP_USING_USBH
+select RESOURCES_USB
+select RESOURCES_USB_HOST
+select USBH_MSTORAGE
+select RESOURCES_USB_DEVICE
+if BSP_USING_USB
+source "$BSP_DIR/third_party_driver/usb/Kconfig"
+endif
+
+menuconfig BSP_USING_LWIP
+bool "Using LwIP device"
+default n
+select RESOURCES_LWIP
+
+menuconfig BSP_USING_WDT
+bool "Using WATCHDOG device"
+default y
+select RESOURCES_WDT
+if BSP_USING_WDT
+source "$BSP_DIR/third_party_driver/watchdog/Kconfig"
+endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/Makefile

@@ -0,0 +1,52 @@
+
+SRC_DIR := common 
+
+ifeq ($(CONFIG_BSP_USING_CAN),y)
+  SRC_DIR += can
+endif
+
+ifeq ($(CONFIG_BSP_USING_GPIO),y)
+  SRC_DIR += gpio
+endif
+
+ifeq ($(CONFIG_BSP_USING_I2C),y)
+  SRC_DIR += i2c
+endif
+
+ifeq ($(CONFIG_BSP_USING_LCD),y)
+  SRC_DIR += lcd
+endif
+
+ifeq ($(CONFIG_BSP_USING_RTC),y)
+  SRC_DIR += rtc
+endif
+
+ifeq ($(CONFIG_BSP_USING_SDIO),y)
+  SRC_DIR += sdio
+endif
+
+ifeq ($(CONFIG_BSP_USING_SPI),y)
+  SRC_DIR += spi
+endif
+
+ifeq ($(CONFIG_BSP_USING_HWTIMER),y)
+  SRC_DIR += timer
+endif
+
+ifeq ($(CONFIG_BSP_USING_UART),y)
+  SRC_DIR += uart
+endif
+
+ifeq ($(CONFIG_BSP_USING_USB),y)
+  SRC_DIR += usb
+endif
+
+ifeq ($(CONFIG_BSP_USING_WDT),y)
+  SRC_DIR += watchdog
+endif
+
+ifeq ($(CONFIG_BSP_USING_LWIP),y)
+  SRC_DIR += ethernet
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/can/Kconfig

@@ -0,0 +1,12 @@
+
+config CAN_BUS_NAME_1
+    string "can bus name"
+    default "can1"
+
+config CAN_DRIVER_NAME
+    string "can driver name"
+    default "can1_drv"
+
+config CAN_1_DEVICE_NAME_1
+    string "can bus 1 device 1 name"
+    default "can1_dev1"

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/can/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := hardware_can.c   connect_can.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/can/connect_can.c

@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) Guangzhou Xingyi Electronic  Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date               Author       Notes
+ * 2014-7-4      alientek   first version
+ */
+
+/**
+* @file connect_can.c
+* @brief support stm32f407-discovery-board can function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-22
+*/
+
+/*************************************************
+File name: can.c
+Description: support can configure and spi bus register function
+Others: hardware/can/can.c for references
+History: 
+1. Date: 2021-04-22
+Author: AIIT XUOS Lab
+Modification: 
+1. support stm32f407-discovery-board spi configure, write and read
+2. support stm32f407-discovery-board spi bus device and driver register
+*************************************************/
+
+#include "connect_can.h"
+#include "misc.h"
+#include "hardware_rcc.h"
+#include "hardware_gpio.h"
+
+static struct CanSendConfigure  can_send_deconfig = 
+{
+    .stdid = 0x55,
+    .exdid = 0x00,
+    .ide = 0 ,
+    .rtr = 0,
+    .data_lenth = 8
+};
+
+static  void CanGPIOInit(void)
+{
+    CAN_FilterInitTypeDef can1_filter;
+    GPIO_InitTypeDef gpio_initstructure;
+    CAN_InitTypeDef     can_initstruction;
+ 
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
+
+    gpio_initstructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_8;
+    gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
+    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
+    gpio_initstructure.GPIO_Speed = GPIO_Speed_100MHz;
+    gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
+    GPIO_Init(GPIOB, &gpio_initstructure);
+
+    GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_CAN1);
+    GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_CAN1);
+}
+
+static void Can1NvicConfig(void)
+{
+    NVIC_InitTypeDef can_nvic_config;
+
+    can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
+    can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
+    can_nvic_config.NVIC_IRQChannelSubPriority = 2;
+    can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
+    CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
+    NVIC_Init(&can_nvic_config);
+}
+
+static uint32 CanModeInit(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+    CAN_FilterInitTypeDef can1_filter;
+    CAN_InitTypeDef     can_initstruction;
+
+     struct CanDriverConfigure  * config  = ( struct CanDriverConfigure  *)configure_info->private_data;
+
+    can_initstruction.CAN_TTCM  = DISABLE;
+    can_initstruction.CAN_ABOM = ENABLE;
+    can_initstruction.CAN_AWUM = DISABLE;
+    can_initstruction.CAN_NART   = ENABLE;
+    can_initstruction.CAN_TXFP    = DISABLE;
+    can_initstruction.CAN_Mode   = config->mode;
+    can_initstruction.CAN_RFLM   = DISABLE;
+    can_initstruction.CAN_SJW      = config->tsjw;
+    can_initstruction.CAN_BS1       = config->tbs1;
+    can_initstruction.CAN_BS2       = config->tbs2;
+    can_initstruction.CAN_Prescaler  = config->brp;
+    
+    CAN_Init(CAN1, &can_initstruction);
+
+    can1_filter.CAN_FilterNumber=0;
+    can1_filter.CAN_FilterMode=CAN_FilterMode_IdMask;
+    can1_filter.CAN_FilterScale=CAN_FilterScale_32bit;
+    can1_filter.CAN_FilterIdHigh=0x0000;
+    can1_filter.CAN_FilterIdLow=0x0000;
+    can1_filter.CAN_FilterMaskIdHigh=0x0000;
+    can1_filter.CAN_FilterMaskIdLow=0x0000;
+    can1_filter.CAN_FilterFIFOAssignment=CAN_Filter_FIFO0;
+    can1_filter.CAN_FilterActivation=ENABLE;
+    CAN_FilterInit(&can1_filter);
+
+    #ifdef  CAN_USING_INTERRUPT
+         Can1NvicConfig();
+    #endif
+
+    return 0;
+}
+
+static uint32 CanSendMsg(void * dev , struct BusBlockWriteParam *write_param )
+{
+    NULL_PARAM_CHECK(write_param);
+
+    uint8  *data   = (uint8  * ) write_param->buffer;
+    u8  mbox;
+    u16  i = 0;
+    u16  timer_count = 1000;
+    CanTxMsg  tx_data;
+    tx_data.StdId  = 0x55;
+    tx_data.ExtId   = 0x00;
+    tx_data.IDE      =  0;
+    tx_data.RTR     =  0;
+    tx_data.DLC     =  write_param->size;
+
+    for(i = 0;i<tx_data.DLC;i++) {
+        tx_data.Data[i] = data[i];
+    }
+
+    mbox = CAN_Transmit(CAN1,&tx_data);
+
+    while (CAN_TransmitStatus(CAN1,mbox)==  CAN_TxStatus_Failed &&timer_count) {
+        timer_count--;
+    }
+
+    if (timer_count<=0) {
+        return ERROR;
+    }
+    return EOK;
+}
+
+static uint32 CanRecvMsg(void *dev , struct BusBlockReadParam *databuf)
+{
+    NULL_PARAM_CHECK(dev);
+    int  i;
+    uint8  * buf  = (uint8 *)databuf->buffer;
+    CanRxMsg msg;
+    if(CAN_MessagePending(CAN1, CAN_FIFO0) == 0)
+        return 0;
+    CAN_Receive(CAN1, CAN_FIFO0, &msg);
+    for(i = 0 ;i<msg.DLC ;i++)
+         buf[i] = msg.Data[i];
+    databuf->size  =  msg.DLC ; 
+
+    return msg.DLC;
+}
+
+static struct CanDevDone dev_done = 
+{
+    .open  = NONE,
+    .close  = NONE,
+    .write  = CanSendMsg,
+    .read   = CanRecvMsg
+};
+
+static struct CanHardwareDevice dev;
+
+ #ifdef  CAN_USING_INTERRUPT
+void CAN1_RX0_IRQHandler(void)
+{
+    CanRxMsg   rxmsg;
+    int i = 0;
+    CAN_Receive(CAN1, 0, &rxmsg);
+    for(i = 0;i<8;i++)
+    KPrintf("rxbuf [%d] = :%d",i,rxmsg.Data[i]);
+}
+DECLARE_HW_IRQ(CAN1_RX0_IRQn, CAN1_RX0_IRQHandler, NONE);
+#endif
+
+static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the can bus */
+    ret = CanBusInit(&stm32can_bus->can_bus, stm32can_bus->bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_can_init canBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the can driver*/
+    ret = CanDriverInit(can_driver, CAN_DRIVER_NAME);
+    if (EOK != ret) {
+        KPrintf("Board_can_init canDriverInit error %d\n", ret);
+        return ERROR;
+    }
+    /*Attach the can driver to the can bus*/
+    ret = CanDriverAttachToBus(CAN_DRIVER_NAME, stm32can_bus->bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
+{
+    NULL_PARAM_CHECK(bus_name);
+    NULL_PARAM_CHECK(device_name);
+
+    x_err_t result;
+    struct CanHardwareDevice *can_device;
+
+    /* attach the device to can bus*/
+    can_device = (struct CanHardwareDevice *)x_malloc(sizeof(struct CanHardwareDevice));
+    CHECK(can_device);
+    memset(can_device, 0, sizeof(struct CanHardwareDevice));
+    can_device->dev_done = &dev_done;
+
+     result = CanDeviceRegister(can_device, NONE, device_name);
+    if (EOK != result) {
+        KPrintf("board_can_init canDeviceInit device %s error %d\n", "can1", result);
+        return ERROR;
+    }  
+
+    result = CanDeviceAttachToBus(device_name, bus_name);
+    if (result != EOK) {
+        SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
+    }
+
+    CHECK(result == EOK);
+
+    KPrintf("%s attach to %s done\n", device_name, bus_name);
+
+    return result;
+}
+
+struct Stm32Can  can1;
+
+ int Stm32HwCanBusInit(void)
+{
+    x_err_t ret = EOK;
+    struct Stm32Can *stm32_can_bus;
+
+    static struct CanDriver can_driver;
+    memset(&can_driver, 0, sizeof(struct CanDriver));
+
+    can_driver.configure = CanModeInit;
+
+    CanGPIOInit();
+    stm32_can_bus = &can1;
+    stm32_can_bus->instance = CAN1;
+    stm32_can_bus->bus_name = CAN_BUS_NAME_1;
+    stm32_can_bus->can_bus.private_data = &can1;
+    
+    ret = BoardCanBusInit(stm32_can_bus, &can_driver);
+   
+    if (EOK != ret) {
+      KPrintf(" can_bus_init %s error ret %u\n", stm32_can_bus->bus_name, ret);
+      return ERROR;
+    }
+
+    ret  =  HwCanDeviceAttach(CAN_BUS_NAME_1,CAN_1_DEVICE_NAME_1);  
+    if (EOK != ret) {
+      KPrintf(" HwCanDeviceAttach %s error ret %u\n", stm32_can_bus->bus_name, ret);
+      return ERROR;
+    }
+    return EOK;
+}

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/Kconfig

@@ -0,0 +1 @@
+

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/Makefile

@@ -0,0 +1,8 @@
+SRC_FILES := misc.c  hardware_rcc.c hardware_exti.c \
+	hardware_it.c hardware_pwr.c hardware_syscfg.c  \
+
+ifeq ($(CONFIG_BSP_USING_DMA),y)
+  SRC_FILES +=  hardware_dma.c
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/hardware_exti.c

@@ -0,0 +1,326 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:           
+  *           - Initialization and Configuration
+  *           - Interrupts and flags management
+  *
+  *  @verbatim  
+  *  
+  *          ===================================================================
+  *                                     EXTI features
+  *          ===================================================================
+  *    
+  *          External interrupt/event lines are mapped as following:
+  *            1- All available GPIO pins are connected to the 16 external 
+  *               interrupt/event lines from EXTI0 to EXTI15.
+  *            2- EXTI line 16 is connected to the PVD Output
+  *            3- EXTI line 17 is connected to the RTC Alarm event
+  *            4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event                                    
+  *            5- EXTI line 19 is connected to the Ethernet Wakeup event
+  *            6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event 
+  *            7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events                                               
+  *            8- EXTI line 22 is connected to the RTC Wakeup event
+  *        
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================  
+  *              
+  *          In order to use an I/O pin as an external interrupt source, follow
+  *          steps below:
+  *            1- Configure the I/O in input mode using GPIO_Init()
+  *            2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
+  *            3- Select the mode(interrupt, event) and configure the trigger 
+  *               selection (Rising, falling or both) using EXTI_Init()
+  *            4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
+  *   
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+  *         registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  *          
+  *  @endverbatim                  
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_exti.c
+* @brief: support hardware exti function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_exti.c
+Description: support hardware exti function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_exti.c for XiUOS
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_exti.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x00000000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x007FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *         This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  enablestatus =  EXTI->IMR & EXTI_Line;
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/hardware_it.c

@@ -0,0 +1,137 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_it.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_it.c
+* @brief: support hardware it function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_it.c
+Description: support hardware it function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_it.c for XiUOS
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <board.h>
+#include <stm32f4xx.h>
+#include <xiuos.h>
+
+/** @addtogroup STM32F4_Discovery_Peripheral_Examples
+  * @{
+  */
+
+/** @addtogroup IO_Toggle
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M4 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(int irqn, void *arg)
+{
+}
+DECLARE_HW_IRQ(NonMaskableInt_IRQn, NMI_Handler, NONE);
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+DECLARE_HW_IRQ(MemoryManagement_IRQn, MemManage_Handler, NONE);
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+DECLARE_HW_IRQ(BusFault_IRQn, BusFault_Handler, NONE);
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+DECLARE_HW_IRQ(UsageFault_IRQn, UsageFault_Handler, NONE);
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(int irqn, void *arg)
+{
+}
+DECLARE_HW_IRQ(SVCall_IRQn, SVC_Handler, NONE);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/hardware_pwr.c

@@ -0,0 +1,673 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_pwr.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:           
+  *           - Backup Domain Access
+  *           - PVD configuration
+  *           - WakeUp pin configuration
+  *           - Main and Backup Regulators configuration
+  *           - FLASH Power Down configuration
+  *           - Low Power modes configuration
+  *           - Flags management
+  *               
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/**
+* @file: hardware_pwr.c
+* @brief: support hardware pwr function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_pwr.c
+Description: support hardware pwr function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_pwr.c for XiUOS
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_pwr.h>
+#include <hardware_rcc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of FPDS bit */
+#define FPDS_BitNumber           0x09
+#define CR_FPDS_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BitNumber           0x0E
+#define CR_PMODE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
+
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* Alias word address of BRE bit */
+#define BRE_BitNumber            0x09
+#define CSR_BRE_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 Backup Domain Access function 
+ *  @brief   Backup Domain Access function  
+ *
+@verbatim   
+ ===============================================================================
+                            Backup Domain Access function 
+ ===============================================================================  
+
+  After reset, the backup domain (RTC registers, RTC backup data 
+  registers and backup SRAM) is protected against possible unwanted 
+  write accesses. 
+  To enable access to the RTC Domain and RTC registers, proceed as follows:
+    - Enable the Power Controller (PWR) APB1 interface clock using the
+      RCC_APB1PeriphClockCmd() function.
+    - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.     
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the backup domain.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                           PVD configuration functions
+ ===============================================================================  
+
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold
+   selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+   PVD threshold. This event is internally connected to the EXTI line16
+   and can generate an interrupt if enabled through the EXTI registers.
+ - The PVD is stopped in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *            @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
+  *            @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
+  *            @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
+  *            @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
+  *            @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
+  *            @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
+  *            @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
+  *            @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
+  * @note   Refer to the electrical characteristics of you device datasheet for more details. 
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 WakeUp pin configuration functions
+ *  @brief   WakeUp pin configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    WakeUp pin configuration functions
+ ===============================================================================  
+
+ - WakeUp pin is used to wakeup the system from Standby mode. This pin is 
+   forced in input pull down configuration and is active on rising edges.
+ - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
+ *  @brief   Main and Backup Regulators configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Main and Backup Regulators configuration functions
+ ===============================================================================  
+
+ - The backup domain includes 4 Kbytes of backup SRAM accessible only from the 
+   CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained 
+   even in Standby or VBAT mode when the low power backup regulator is enabled. 
+   It can be considered as an internal EEPROM when VBAT is always present.
+   You can use the PWR_BackupRegulatorCmd() function to enable the low power
+   backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
+   ready or not. 
+
+ - When the backup domain is supplied by VDD (analog switch connected to VDD) 
+   the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+   save battery life.
+
+ - The backup SRAM is not mass erased by an tamper event. It is read protected 
+   to prevent confidential data, such as cryptographic private key, from being 
+   accessed. The backup SRAM can be erased only through the Flash interface when
+   a protection level change from level 1 to level 0 is requested. 
+   Refer to the description of Read protection (RDP) in the Flash programming manual.
+
+ - The main internal regulator can be configured to have a tradeoff between performance
+   and power consumption when the device does not operate at the maximum frequency. 
+   This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit
+   in PWR_CR register: 
+      - When this bit is set (Regulator voltage output Scale 1 mode selected) the System
+        frequency can go up to 168 MHz. 
+      - When this bit is reset (Regulator voltage output Scale 2 mode selected) the System
+        frequency can go up to 144 MHz. 
+   Refer to the datasheets for more details.
+           
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Backup Regulator.
+  * @param  NewState: new state of the Backup Regulator.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupRegulatorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the main internal regulator output voltage.
+  * @param  PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, 
+  *                                                System frequency up to 168 MHz. 
+  *            @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, 
+  *                                                System frequency up to 144 MHz.    
+  * @retval None
+  */
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
+
+  if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
+  {
+    PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
+  }
+  else
+  {    
+    PWR->CR |= PWR_Regulator_Voltage_Scale1;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group5 FLASH Power Down configuration functions
+ *  @brief   FLASH Power Down configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           FLASH Power Down configuration functions
+ ===============================================================================  
+
+ - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
+   function, the Flash memory also enters power down mode when the device enters 
+   Stop mode. When the Flash memory is in power down mode, an additional startup 
+   delay is incurred when waking up from Stop mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Flash Power Down in STOP mode.
+  * @param  NewState: new state of the Flash power mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_FlashPowerDownCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group6 Low Power modes configuration functions
+ *  @brief   Low Power modes configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Low Power modes configuration functions
+ ===============================================================================  
+
+  The devices feature 3 low-power modes:
+   - Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+   - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
+   - Standby mode: 1.2V domain powered off.
+   
+   Sleep mode
+   ===========
+    - Entry:
+      - The Sleep mode is entered by using the __WFI() or __WFE() functions.
+    - Exit:
+      - Any peripheral interrupt acknowledged by the nested vectored interrupt 
+        controller (NVIC) can wake up the device from Sleep mode.
+
+   Stop mode
+   ==========
+   In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+   and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+   are preserved.
+   The voltage regulator can be configured either in normal or low-power mode.
+   To minimize the consumption In Stop mode, FLASH can be powered off before 
+   entering the Stop mode. It can be switched on again by software after exiting 
+   the Stop mode using the PWR_FlashPowerDownCmd() function. 
+   
+    - Entry:
+      - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+        function with regulator in LowPower or with Regulator ON.
+    - Exit:
+      - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+      
+   Standby mode
+   ============
+   The Standby mode allows to achieve the lowest power consumption. It is based 
+   on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. 
+   The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+   the HSE oscillator are also switched off. SRAM and register contents are lost 
+   except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+   circuitry.
+   
+   The voltage regulator is OFF.
+      
+    - Entry:
+      - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+    - Exit:
+      - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+        tamper event, time-stamp event, external reset in NRST pin, IWDG reset.              
+
+   Auto-wakeup (AWU) from low-power mode
+   =====================================
+   The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+   Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+   without depending on an external interrupt (Auto-wakeup mode).
+
+   - RTC auto-wakeup (AWU) from the Stop mode
+     ----------------------------------------
+     
+     - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+       - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
+     - To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
+       - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
+       - Configure the RTC to detect the tamper or time stamp event using the
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+         functions.
+     - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
+       - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+   - RTC auto-wakeup (AWU) from the Standby mode
+     -------------------------------------------
+     - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
+     - To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
+       - Configure the RTC to detect the tamper or time stamp event using the
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+         functions.
+     - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enters STOP mode.
+  *   
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.           
+  *     
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *            @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *            @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wakeup flag */
+  PWR->CR |= PWR_CR_CWUF;
+  
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group7 Flags management functions
+ *  @brief   Flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                           Flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the PWR_PVDCmd() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready. 
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/hardware_syscfg.c

@@ -0,0 +1,217 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the SYSCFG peripheral.
+  *
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *                  
+  *          This driver provides functions for:
+  *          
+  *          1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
+  *              
+  *          2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
+  *            
+  *          3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
+  *
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
+  *         using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  *                 
+  *  @endverbatim
+  *      
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_syscfg.c
+* @brief: support hardware syscfg function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_syscfg.c
+Description: support hardware syscfg function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_syscfg.c for XiUOS
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_syscfg.h>
+#include <hardware_rcc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  PMC Register ---*/ 
+/* Alias word address of MII_RMII_SEL bit */ 
+#define PMC_OFFSET                (SYSCFG_OFFSET + 0x04) 
+#define MII_RMII_SEL_BitNumber    ((uint8_t)0x17) 
+#define PMC_MII_RMII_SEL_BB       (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) 
+
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
+#define CMP_PD_BitNumber          ((uint8_t)0x00) 
+#define CMPCR_CMP_PD_BB           (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Deinitializes the Alternate Functions (remap and EXTI configuration)
+  *   registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SYSCFG_DeInit(void)
+{
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
+}
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  SYSCFG_Memory: selects the memory remapping.
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_MemoryRemap_Flash:       Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_FSMC:        FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_SRAM:        Embedded SRAM (112kB) mapped at 0x00000000
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
+
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
+  *          EXTI lines where x can be (A..I).
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  *           This parameter can be EXTI_PinSourcex where x can be (0..15, except
+  *           for EXTI_PortSourceGPIOI x can be (0..11).
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the ETHERNET media interface 
+  * @param  SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 
+  *          This parameter can be one of the following values: 
+  *            @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
+  *            @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected 
+  * @retval None 
+  */
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) 
+{ 
+  assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); 
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; 
+}
+
+/**
+  * @brief  Enables or disables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @param  NewState: new state of the I/O Compensation Cell.
+  *          This parameter can be one of the following values:
+  *            @arg ENABLE: I/O compensation cell enabled  
+  *            @arg DISABLE: I/O compensation cell power-down mode  
+  * @retval None
+  */
+void SYSCFG_CompensationCellCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Checks whether the I/O Compensation Cell ready flag is set or not.
+  * @param  None
+  * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
+  */
+FlagStatus SYSCFG_GetCompensationCellStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/   

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/common/misc.c

@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  *          
+  *  @verbatim   
+  *                               
+  *          ===================================================================      
+  *                        How to configure Interrupts using driver 
+  *          ===================================================================      
+  * 
+  *            This section provide functions allowing to configure the NVIC interrupts (IRQ).
+  *            The Cortex-M4 exceptions are managed by CMSIS functions.
+  *
+  *            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+  *                function according to the following table.
+ 
+  *  The table below gives the allowed values of the pre-emption priority and subpriority according
+  *  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  *    ==========================================================================================================================
+  *      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+  *    ==========================================================================================================================
+  *     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+  *                           |                                   |                             | 4 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------
+  *     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+  *                           |                                   |                             | 3 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+  *                           |                                   |                             | 2 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+  *                           |                                   |                             | 1 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
+  *                           |                                   |                             | 0 bits for subpriority                       
+  *    ==========================================================================================================================     
+  *
+  *            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
+  *
+  * @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *        The pending IRQ priority will be managed only by the subpriority.
+  *
+  * @note  IRQ priority order (sorted by highest to lowest priority):
+  *         - Lowest pre-emption priority
+  *         - Lowest subpriority
+  *         - Lowest hardware priority (IRQ number)
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: misc.c
+* @brief: support misc function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include <misc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
+        
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
+  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/cortex-m4-emulator/third_party_driver/ethernet/Kconfig

@@ -0,0 +1,12 @@
+
+config CAN_BUS_NAME_1
+    string "can bus name"
+    default "can1"
+
+config CAN_DRIVER_NAME
+    string "can driver name"
+    default "can1_drv"
+
+config CAN_1_DEVICE_NAME_1
+    string "can bus 1 device 1 name"
+    default "can1_dev1"