diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/inc/spi_lora_sx12xx.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/inc/spi_lora_sx12xx.h new file mode 100644 index 000000000..25e647f7e --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/inc/spi_lora_sx12xx.h @@ -0,0 +1,96 @@ +/* + * Original Copyright (c) 2006-2018, RT-Thread Development Team + * Modified Copyright (c) 2020 AIIT XUOS Lab + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + + * http://www.apache.org/licenses/LICENSE-2.0 + + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-02-25 XiaojieFan the first version + */ + +/* + * Modified by: AIIT XUOS Lab + * Modified date: 2020-09-01 + * Description: + */ +/************************************************* +File name: spi_lora_sx12xx.h +Description: support aiit board configure and register function +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. replace original macro and basic date type with AIIT XUOS Lab's own defination +*************************************************/ + + +#ifndef __SPI_LORA_SX12XX_H_ +#define __SPI_LORA_SX12XX_H_ + +#include +#include +#include "type.h" + +/*! + * \brief Gets the SX1272 DIO0 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +rt_uint8_t SX1276ReadDio0(void); + +/*! + * \brief Gets the SX1272 DIO1 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +rt_uint8_t SX1276ReadDio1(void); + +/*! + * \brief Gets the SX1272 DIO2 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +rt_uint8_t SX1276ReadDio2(void); + +/*! + * \brief Gets the SX1272 DIO3 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +rt_uint8_t SX1276ReadDio3(void); + +/*! + * \brief Gets the SX1272 DIO4 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +rt_uint8_t SX1276ReadDio4(void); + +/*! + * \brief Gets the SX1272 DIO5 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +rt_uint8_t SX1276ReadDio5(void); + +void SX1276Write(rt_uint8_t addr, rt_uint8_t data); +void SX1276Read(rt_uint8_t addr, rt_uint8_t *data); +void SX1276WriteBuffer(rt_uint8_t addr, rt_uint8_t *buffer, rt_uint8_t size); +void SX1276ReadBuffer(rt_uint8_t addr, rt_uint8_t *buffer, rt_uint8_t size); +void SX1276WriteFifo(rt_uint8_t *buffer, rt_uint8_t size); +void SX1276ReadFifo(rt_uint8_t *buffer, rt_uint8_t size); +void SX1276SetReset(rt_uint8_t state); +rt_uint8_t SX1276_Spi_Check(void); +void SX1276WriteRxTx(rt_uint8_t txEnable); +#endif \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/inc/type.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/inc/type.h new file mode 100644 index 000000000..eb63cdf41 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/inc/type.h @@ -0,0 +1,33 @@ +/* +File Name : type.h +Author : Yichip +Version : V1.0 +Date : 2018/05/25 +Description : Data type definition. +*/ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#if defined (__CC_ARM) || defined ( __ICCARM__ ) +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +typedef unsigned char byte; +typedef unsigned short word; + +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef signed long long int64_t; +#else +#include "stdio.h" +typedef unsigned char byte; +typedef unsigned short word; +#endif + + + +#endif /*__TYPE_H__*/ + diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/port/spi_sx1278_init.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/port/spi_sx1278_init.c new file mode 100644 index 000000000..fe9e7d65f --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/port/spi_sx1278_init.c @@ -0,0 +1,17 @@ +#include + +#include "drv_spi.h" +#include +#include +#include +#include +#include +#include +#include + +static int sx12xx_spi_device_init(void) +{ + __HAL_RCC_GPIOC_CLK_ENABLE(); + rt_hw_spi_device_attach("spi2","spi20",GPIOC,GPIO_PIN_6); +} +INIT_APP_EXPORT(sx12xx_spi_device_init); \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/Makefile b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/Makefile new file mode 100644 index 000000000..ee5f169e2 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/Makefile @@ -0,0 +1,10 @@ + +SRC_FILES += radio/radio.c \ + radio/sx1276-Fsk.c \ + radio/sx1276-FskMisc.c \ + radio/sx1276-LoRa.c \ + radio/sx1276-LoRaMisc.c \ + radio/sx1276.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/platform.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/platform.h new file mode 100644 index 000000000..aa6a36171 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/platform.h @@ -0,0 +1,88 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file platform.h + * \brief + * + * \version 1.0 + * \date Nov 21 2012 + * \author Miguel Luis + */ +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#ifndef __GNUC__ +#define inline +#endif + +/*! + * Platform definition + */ +#define Bleeper 3 +#define SX1243ska 2 +#define SX12xxEiger 1 +#define SX12000DVK 0 + +/*! + * Platform choice. Please uncoment the PLATFORM define and choose your platform + * or add/change the PLATFORM definition on the compiler Defines option + */ +#define PLATFORM SX12xxEiger + +#if( PLATFORM == SX12xxEiger ) +/*! + * Radio choice. Please uncomment the wanted radio and comment the others + * or add/change wanted radio definition on the compiler Defines option + */ +//#define USE_SX1232_RADIO +//#define USE_SX1272_RADIO +#define USE_SX1276_RADIO +//#define USE_SX1243_RADIO + +/*! + * Module choice. There are three existing module with the SX1276. + * Please set the connected module to the value 1 and set the others to 0 + */ +#ifdef USE_SX1276_RADIO +#define MODULE_SX1276RF1IAS 0 +#define MODULE_SX1276RF1JAS 0 +#define MODULE_SX1276RF1KAS 1 +#endif + + //#include "sx12xxEiger/sx12xxEiger.h" + #include "spi_lora_sx12xx.h" + #define USE_UART 0 + +#elif( PLATFORM == SX12000DVK ) +/*! + * Radio choice. Please uncomment the wanted radio and comment the others + * or add/change wanted radio definition on the compiler Defines option + */ +//#define USE_SX1232_RADIO +#define USE_SX1272_RADIO +//#define USE_SX1276_RADIO +//#define USE_SX1243_RADIO + + #include "sx1200dvk/sx1200dvk.h" + +#elif( PLATFORM == SX1243ska ) + +#elif( PLATFORM == Bleeper ) + #define USE_SX1272_RADIO + + #include "bleeper/bleeper.h" + #define USE_UART 0 + +#else + #error "Missing define: Platform (ie. SX12xxEiger)" +#endif + +#endif // __PLATFORM_H__ diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/radio.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/radio.c new file mode 100644 index 000000000..fb413d915 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/radio.c @@ -0,0 +1,64 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file radio.c + * \brief Generic radio driver ( radio abstraction ) + * + * \version 2.0.0 + * \date Nov 21 2012 + * \author Miguel Luis + * + * Last modified by Gregory Cristian on Apr 25 2013 + */ +#include "platform.h" + +#include "radio.h" + +#if defined( USE_SX1232_RADIO ) + #include "sx1232.h" +#elif defined( USE_SX1272_RADIO ) + #include "sx1272.h" +#elif defined( USE_SX1276_RADIO ) + #include "sx1276.h" +#else + #error "Missing define: USE_XXXXXX_RADIO (ie. USE_SX1272_RADIO)" +#endif + +tRadioDriver RadioDriver; + +tRadioDriver* RadioDriverInit( void ) +{ +#if defined( USE_SX1232_RADIO ) + RadioDriver.Init = SX1232Init; + RadioDriver.Reset = SX1232Reset; + RadioDriver.StartRx = SX1232StartRx; + RadioDriver.GetRxPacket = SX1232GetRxPacket; + RadioDriver.SetTxPacket = SX1232SetTxPacket; + RadioDriver.Process = SX1232Process; +#elif defined( USE_SX1272_RADIO ) + RadioDriver.Init = SX1272Init; + RadioDriver.Reset = SX1272Reset; + RadioDriver.StartRx = SX1272StartRx; + RadioDriver.GetRxPacket = SX1272GetRxPacket; + RadioDriver.SetTxPacket = SX1272SetTxPacket; + RadioDriver.Process = SX1272Process; +#elif defined( USE_SX1276_RADIO ) + RadioDriver.Init = SX1276Init; + RadioDriver.Reset = SX1276Reset; + RadioDriver.StartRx = SX1276StartRx; + RadioDriver.GetRxPacket = SX1276GetRxPacket; + RadioDriver.SetTxPacket = SX1276SetTxPacket; + RadioDriver.Process = SX1276Process; +#else + #error "Missing define: USE_XXXXXX_RADIO (ie. USE_SX1272_RADIO)" +#endif + return &RadioDriver; +} diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/radio.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/radio.h new file mode 100644 index 000000000..65b1a0912 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/radio.h @@ -0,0 +1,66 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file radio.h + * \brief Generic radio driver ( radio abstraction ) + * + * \version 2.0.B2 + * \date Nov 21 2012 + * \author Miguel Luis + * + * Last modified by Gregory Cristian on Apr 25 2013 + */ +#ifndef __RADIO_H__ +#define __RADIO_H__ + +/*! + * SX1272 and SX1276 General parameters definition + */ +#define LORA 1 // [0: OFF, 1: ON] + +/*! + * RF process function return codes + */ +typedef enum +{ + RF_IDLE, + RF_BUSY, + RF_RX_DONE, + RF_RX_TIMEOUT, + RF_TX_DONE, + RF_TX_TIMEOUT, + RF_LEN_ERROR, + RF_CHANNEL_EMPTY, + RF_CHANNEL_ACTIVITY_DETECTED, +}tRFProcessReturnCodes; + +/*! + * Radio driver structure defining the different function pointers + */ +typedef struct sRadioDriver +{ + void ( *Init )( void ); + void ( *Reset )( void ); + void ( *StartRx )( void ); + void ( *GetRxPacket )( void *buffer, uint16_t *size ); + void ( *SetTxPacket )( const void *buffer, uint16_t size ); + uint32_t ( *Process )( void ); +}tRadioDriver; + +/*! + * \brief Initializes the RadioDriver structure with specific radio + * functions. + * + * \retval radioDriver Pointer to the radio driver variable + */ +tRadioDriver* RadioDriverInit( void ); + +#endif // __RADIO_H__ diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Fsk.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Fsk.c new file mode 100644 index 000000000..29906c0fe --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Fsk.c @@ -0,0 +1,606 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276.c + * \brief SX1276 RF chip driver + * + * \version 2.0.0 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#include +#include + +#include "platform.h" + +#if defined( USE_SX1276_RADIO ) + +#include "radio.h" + +#include "sx1276-Hal.h" +#include "sx1276.h" + +#include "sx1276-FskMisc.h" +#include "sx1276-Fsk.h" + +// Default settings +tFskSettings FskSettings = +{ + 870000000, // RFFrequency + 9600, // Bitrate + 50000, // Fdev + 20, // Power + 100000, // RxBw + 150000, // RxBwAfc + true, // CrcOn + true, // AfcOn + 255 // PayloadLength (set payload size to the maximum for variable mode, else set the exact payload length) +}; + +/*! + * SX1276 FSK registers variable + */ +tSX1276* SX1276; + +/*! + * Local RF buffer for communication support + */ +static uint8_t RFBuffer[RF_BUFFER_SIZE]; + +/*! + * Chunk size of data write in buffer + */ +static uint8_t DataChunkSize = 32; + + +/*! + * RF state machine variable + */ +static uint8_t RFState = RF_STATE_IDLE; + +/*! + * Rx management support variables + */ + +/*! + * PacketTimeout holds the RF packet timeout + * SyncSize = [0..8] + * VariableSize = [0;1] + * AddressSize = [0;1] + * PayloadSize = [0..RF_BUFFER_SIZE] + * CrcSize = [0;2] + * PacketTimeout = ( ( 8 * ( VariableSize + AddressSize + PayloadSize + CrcSize ) / BR ) * 1000.0 ) + 1 + * Computed timeout is in miliseconds + */ +static uint32_t PacketTimeout; + +/*! + * Preamble2SyncTimeout + * Preamble2SyncTimeout = ( ( 8 * ( PremableSize + SyncSize ) / RFBitrate ) * 1000.0 ) + 1 + * Computed timeout is in miliseconds + */ +static uint32_t Preamble2SyncTimeout; + +static bool PreambleDetected = false; +static bool SyncWordDetected = false; +static bool PacketDetected = false; +static uint16_t RxPacketSize = 0; +static uint8_t RxBytesRead = 0; +static uint8_t TxBytesSent = 0; +static double RxPacketRssiValue; +static uint32_t RxPacketAfcValue; +static uint8_t RxGain = 1; +static uint32_t RxTimeoutTimer = 0; +static uint32_t Preamble2SyncTimer = 0; + +/*! + * Tx management support variables + */ +static uint16_t TxPacketSize = 0; +static uint32_t TxTimeoutTimer = 0; + +void SX1276FskInit( void ) +{ + RFState = RF_STATE_IDLE; + + SX1276FskSetDefaults( ); + + SX1276ReadBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 ); + + // Set the device in FSK mode and Sleep Mode + SX1276->RegOpMode = RF_OPMODE_MODULATIONTYPE_FSK | RF_OPMODE_SLEEP; + SX1276Write( REG_OPMODE, SX1276->RegOpMode ); + + SX1276->RegPaRamp = RF_PARAMP_MODULATIONSHAPING_01; + SX1276Write( REG_PARAMP, SX1276->RegPaRamp ); + + SX1276->RegLna = RF_LNA_GAIN_G1; + SX1276Write( REG_LNA, SX1276->RegLna ); + + if( FskSettings.AfcOn == true ) + { + SX1276->RegRxConfig = RF_RXCONFIG_RESTARTRXONCOLLISION_OFF | RF_RXCONFIG_AFCAUTO_ON | + RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT; + } + else + { + SX1276->RegRxConfig = RF_RXCONFIG_RESTARTRXONCOLLISION_OFF | RF_RXCONFIG_AFCAUTO_OFF | + RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT; + } + + SX1276->RegPreambleLsb = 8; + + SX1276->RegPreambleDetect = RF_PREAMBLEDETECT_DETECTOR_ON | RF_PREAMBLEDETECT_DETECTORSIZE_2 | + RF_PREAMBLEDETECT_DETECTORTOL_10; + + SX1276->RegRssiThresh = 0xFF; + + SX1276->RegSyncConfig = RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON | RF_SYNCCONFIG_PREAMBLEPOLARITY_AA | + RF_SYNCCONFIG_SYNC_ON | + RF_SYNCCONFIG_SYNCSIZE_4; + + SX1276->RegSyncValue1 = 0x69; + SX1276->RegSyncValue2 = 0x81; + SX1276->RegSyncValue3 = 0x7E; + SX1276->RegSyncValue4 = 0x96; + + SX1276->RegPacketConfig1 = RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE | RF_PACKETCONFIG1_DCFREE_OFF | + ( FskSettings.CrcOn << 4 ) | RF_PACKETCONFIG1_CRCAUTOCLEAR_ON | + RF_PACKETCONFIG1_ADDRSFILTERING_OFF | RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT; + SX1276FskGetPacketCrcOn( ); // Update CrcOn on FskSettings + + SX1276->RegPayloadLength = FskSettings.PayloadLength; + + // we can now update the registers with our configuration + SX1276WriteBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 ); + + // then we need to set the RF settings + SX1276FskSetRFFrequency( FskSettings.RFFrequency ); + SX1276FskSetBitrate( FskSettings.Bitrate ); + SX1276FskSetFdev( FskSettings.Fdev ); + + SX1276FskSetDccBw( &SX1276->RegRxBw, 0, FskSettings.RxBw ); + SX1276FskSetDccBw( &SX1276->RegAfcBw, 0, FskSettings.RxBwAfc ); + SX1276FskSetRssiOffset( 0 ); + +#if( ( MODULE_SX1276RF1IAS == 1 ) || ( MODULE_SX1276RF1KAS == 1 ) ) + if( FskSettings.RFFrequency > 860000000 ) + { + SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_RFO ); + SX1276FskSetPa20dBm( false ); + FskSettings.Power = 14; + SX1276FskSetRFPower( FskSettings.Power ); + } + else + { + SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_PABOOST ); + SX1276FskSetPa20dBm( true ); + FskSettings.Power = 20; + SX1276FskSetRFPower( FskSettings.Power ); + } +#elif( MODULE_SX1276RF1JAS == 1 ) + if( FskSettings.RFFrequency > 860000000 ) + { + SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_PABOOST ); + SX1276FskSetPa20dBm( true ); + FskSettings.Power = 20; + SX1276FskSetRFPower( FskSettings.Power ); + } + else + { + SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_RFO ); + SX1276FskSetPa20dBm( false ); + FskSettings.Power = 14; + SX1276FskSetRFPower( FskSettings.Power ); + } +#endif + + SX1276FskSetOpMode( RF_OPMODE_STANDBY ); + + // Calibrate the HF + SX1276FskRxCalibrate( ); +} + +void SX1276FskSetDefaults( void ) +{ + // REMARK: See SX1276 datasheet for modified default values. + + SX1276Read( REG_VERSION, &SX1276->RegVersion ); +} + +void SX1276FskSetOpMode( uint8_t opMode ) +{ + static uint8_t opModePrev = RF_OPMODE_STANDBY; + static bool antennaSwitchTxOnPrev = true; + bool antennaSwitchTxOn = false; + + opModePrev = SX1276->RegOpMode & ~RF_OPMODE_MASK; + + if( opMode != opModePrev ) + { + if( opMode == RF_OPMODE_TRANSMITTER ) + { + antennaSwitchTxOn = true; + } + else + { + antennaSwitchTxOn = false; + } + if( antennaSwitchTxOn != antennaSwitchTxOnPrev ) + { + antennaSwitchTxOnPrev = antennaSwitchTxOn; + RXTX( antennaSwitchTxOn ); // Antenna switch control + } + SX1276->RegOpMode = ( SX1276->RegOpMode & RF_OPMODE_MASK ) | opMode; + + SX1276Write( REG_OPMODE, SX1276->RegOpMode ); + } +} + +uint8_t SX1276FskGetOpMode( void ) +{ + SX1276Read( REG_OPMODE, &SX1276->RegOpMode ); + + return SX1276->RegOpMode & ~RF_OPMODE_MASK; +} + +int32_t SX1276FskReadFei( void ) +{ + SX1276ReadBuffer( REG_FEIMSB, &SX1276->RegFeiMsb, 2 ); // Reads the FEI value + + return ( int32_t )( double )( ( ( uint16_t )SX1276->RegFeiMsb << 8 ) | ( uint16_t )SX1276->RegFeiLsb ) * ( double )FREQ_STEP; +} + +int32_t SX1276FskReadAfc( void ) +{ + SX1276ReadBuffer( REG_AFCMSB, &SX1276->RegAfcMsb, 2 ); // Reads the AFC value + return ( int32_t )( double )( ( ( uint16_t )SX1276->RegAfcMsb << 8 ) | ( uint16_t )SX1276->RegAfcLsb ) * ( double )FREQ_STEP; +} + +uint8_t SX1276FskReadRxGain( void ) +{ + SX1276Read( REG_LNA, &SX1276->RegLna ); + return( SX1276->RegLna >> 5 ) & 0x07; +} + +double SX1276FskReadRssi( void ) +{ + SX1276Read( REG_RSSIVALUE, &SX1276->RegRssiValue ); // Reads the RSSI value + + return -( double )( ( double )SX1276->RegRssiValue / 2.0 ); +} + +uint8_t SX1276FskGetPacketRxGain( void ) +{ + return RxGain; +} + +double SX1276FskGetPacketRssi( void ) +{ + return RxPacketRssiValue; +} + +uint32_t SX1276FskGetPacketAfc( void ) +{ + return RxPacketAfcValue; +} + +void SX1276FskStartRx( void ) +{ + SX1276FskSetRFState( RF_STATE_RX_INIT ); +} + +void SX1276FskGetRxPacket( void *buffer, uint16_t *size ) +{ + *size = RxPacketSize; + RxPacketSize = 0; + memcpy( ( void * )buffer, ( void * )RFBuffer, ( size_t )*size ); +} + +void SX1276FskSetTxPacket( const void *buffer, uint16_t size ) +{ + TxPacketSize = size; + memcpy( ( void * )RFBuffer, buffer, ( size_t )TxPacketSize ); + + RFState = RF_STATE_TX_INIT; +} + +// Remark: SX1276 must be fully initialized before calling this function +uint16_t SX1276FskGetPacketPayloadSize( void ) +{ + uint16_t syncSize; + uint16_t variableSize; + uint16_t addressSize; + uint16_t payloadSize; + uint16_t crcSize; + + syncSize = ( SX1276->RegSyncConfig & 0x07 ) + 1; + variableSize = ( ( SX1276->RegPacketConfig1 & 0x80 ) == 0x80 ) ? 1 : 0; + addressSize = ( ( SX1276->RegPacketConfig1 & 0x06 ) != 0x00 ) ? 1 : 0; + payloadSize = SX1276->RegPayloadLength; + crcSize = ( ( SX1276->RegPacketConfig1 & 0x10 ) == 0x10 ) ? 2 : 0; + + return syncSize + variableSize + addressSize + payloadSize + crcSize; +} + +// Remark: SX1276 must be fully initialized before calling this function +uint16_t SX1276FskGetPacketHeaderSize( void ) +{ + uint16_t preambleSize; + uint16_t syncSize; + + preambleSize = ( ( uint16_t )SX1276->RegPreambleMsb << 8 ) | ( uint16_t )SX1276->RegPreambleLsb; + syncSize = ( SX1276->RegSyncConfig & 0x07 ) + 1; + + return preambleSize + syncSize; +} + +uint8_t SX1276FskGetRFState( void ) +{ + return RFState; +} + +void SX1276FskSetRFState( uint8_t state ) +{ + RFState = state; +} + +uint32_t SX1276FskProcess( void ) +{ + uint32_t result = RF_BUSY; + + switch( RFState ) + { + case RF_STATE_IDLE: + break; + // Rx management + case RF_STATE_RX_INIT: + // DIO mapping setup + if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_ON ) == RF_PACKETCONFIG1_CRC_ON ) + { + // CrcOk, FifoLevel, SyncAddr, FifoEmpty + SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_01 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 | RF_DIOMAPPING1_DIO3_00; + } + else + { + // PayloadReady, FifoLevel, SyncAddr, FifoEmpty + SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_00 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 | RF_DIOMAPPING1_DIO3_00; + } + // Preamble, Data + SX1276->RegDioMapping2 = RF_DIOMAPPING2_DIO4_11 | RF_DIOMAPPING2_DIO5_10 | RF_DIOMAPPING2_MAP_PREAMBLEDETECT; + SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 ); + + SX1276FskSetOpMode( RF_OPMODE_RECEIVER ); + + memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE ); + + PacketTimeout = ( uint16_t )( round( ( 8.0 * ( ( double )SX1276FskGetPacketPayloadSize( ) ) / ( double )FskSettings.Bitrate ) * 1000.0 ) + 1.0 ); + PacketTimeout = PacketTimeout + ( PacketTimeout >> 1 ); // Set the Packet timeout as 1.5 times the full payload transmission time + + Preamble2SyncTimeout = PacketTimeout; + + Preamble2SyncTimer = RxTimeoutTimer = GET_TICK_COUNT( ); + + SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | 0x20; // 32 bytes of data + SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh ); + + PreambleDetected = false; + SyncWordDetected = false; + PacketDetected = false; + RxBytesRead = 0; + RxPacketSize = 0; + RFState = RF_STATE_RX_SYNC; + break; + case RF_STATE_RX_SYNC: + if( ( DIO4 == 1 ) && ( PreambleDetected == false ) )// Preamble + { + PreambleDetected = true; + Preamble2SyncTimer = GET_TICK_COUNT( ); + } + if( ( DIO2 == 1 ) && ( PreambleDetected == true ) && ( SyncWordDetected == false ) ) // SyncAddr + { + SyncWordDetected = true; + + RxPacketRssiValue = SX1276FskReadRssi( ); + + RxPacketAfcValue = SX1276FskReadAfc( ); + RxGain = SX1276FskReadRxGain( ); + + Preamble2SyncTimer = RxTimeoutTimer = GET_TICK_COUNT( ); + + RFState = RF_STATE_RX_RUNNING; + } + + // Preamble 2 SyncAddr timeout + if( ( SyncWordDetected == false ) && ( PreambleDetected == true ) && ( ( GET_TICK_COUNT( ) - Preamble2SyncTimer ) > Preamble2SyncTimeout ) ) + { + RFState = RF_STATE_RX_INIT; + SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK ); + } + if( ( SyncWordDetected == false ) && + ( PreambleDetected == false ) && + ( PacketDetected == false ) && + ( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) ) + { + RFState = RF_STATE_RX_TIMEOUT; + } + break; + case RF_STATE_RX_RUNNING: + if( RxPacketSize > RF_BUFFER_SIZE_MAX ) + { + RFState = RF_STATE_RX_LEN_ERROR; + break; + } +#if 1 + if( DIO1 == 1 ) // FifoLevel + { + if( ( RxPacketSize == 0 ) && ( RxBytesRead == 0 ) ) // Read received packet size + { + if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) + { + SX1276ReadFifo( ( uint8_t* )&RxPacketSize, 1 ); + } + else + { + RxPacketSize = SX1276->RegPayloadLength; + } + } + + if( ( RxPacketSize - RxBytesRead ) > ( SX1276->RegFifoThresh & 0x3F ) ) + { + SX1276ReadFifo( ( RFBuffer + RxBytesRead ), ( SX1276->RegFifoThresh & 0x3F ) ); + RxBytesRead += ( SX1276->RegFifoThresh & 0x3F ); + } + else + { + SX1276ReadFifo( ( RFBuffer + RxBytesRead ), RxPacketSize - RxBytesRead ); + RxBytesRead += ( RxPacketSize - RxBytesRead ); + } + } +#endif + if( DIO0 == 1 ) // PayloadReady/CrcOk + { + RxTimeoutTimer = GET_TICK_COUNT( ); + if( ( RxPacketSize == 0 ) && ( RxBytesRead == 0 ) ) // Read received packet size + { + if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) + { + SX1276ReadFifo( ( uint8_t* )&RxPacketSize, 1 ); + } + else + { + RxPacketSize = SX1276->RegPayloadLength; + } + SX1276ReadFifo( RFBuffer + RxBytesRead, RxPacketSize - RxBytesRead ); + RxBytesRead += ( RxPacketSize - RxBytesRead ); + PacketDetected = true; + RFState = RF_STATE_RX_DONE; + } + else + { + SX1276ReadFifo( RFBuffer + RxBytesRead, RxPacketSize - RxBytesRead ); + RxBytesRead += ( RxPacketSize - RxBytesRead ); + PacketDetected = true; + RFState = RF_STATE_RX_DONE; + } + } + + // Packet timeout + if( ( PacketDetected == false ) && ( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) ) + { + RFState = RF_STATE_RX_TIMEOUT; + } + break; + case RF_STATE_RX_DONE: + RxBytesRead = 0; + RFState = RF_STATE_RX_INIT; + result = RF_RX_DONE; + break; + case RF_STATE_RX_TIMEOUT: + RxBytesRead = 0; + RxPacketSize = 0; + SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK ); + RFState = RF_STATE_RX_INIT; + result = RF_RX_TIMEOUT; + break; + case RF_STATE_RX_LEN_ERROR: + RxBytesRead = 0; + RxPacketSize = 0; + SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK ); + RFState = RF_STATE_RX_INIT; + result = RF_LEN_ERROR; + break; + // Tx management + case RF_STATE_TX_INIT: + // Packet DIO mapping setup + // PacketSent, FifoLevel, FifoFull, TxReady + SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_00 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_00 | RF_DIOMAPPING1_DIO3_01; + // LowBat, Data + SX1276->RegDioMapping2 = RF_DIOMAPPING2_DIO4_00 | RF_DIOMAPPING2_DIO5_10; + SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 ); + + SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | 0x18; // 24 bytes of data + SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh ); + + SX1276FskSetOpMode( RF_OPMODE_TRANSMITTER ); + RFState = RF_STATE_TX_READY_WAIT; + TxBytesSent = 0; + break; + case RF_STATE_TX_READY_WAIT: + if( DIO3 == 1 ) // TxReady + { + if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) + { + SX1276WriteFifo( ( uint8_t* )&TxPacketSize, 1 ); + } + + if( ( TxPacketSize > 0 ) && ( TxPacketSize <= 64 ) ) + { + DataChunkSize = TxPacketSize; + } + else + { + DataChunkSize = 32; + } + + SX1276WriteFifo( RFBuffer, DataChunkSize ); + TxBytesSent += DataChunkSize; + TxTimeoutTimer = GET_TICK_COUNT( ); + RFState = RF_STATE_TX_RUNNING; + } + break; + + case RF_STATE_TX_RUNNING: + if( DIO1 == 0 ) // FifoLevel below thresold + { + if( ( TxPacketSize - TxBytesSent ) > DataChunkSize ) + { + SX1276WriteFifo( ( RFBuffer + TxBytesSent ), DataChunkSize ); + TxBytesSent += DataChunkSize; + } + else + { + // we write the last chunk of data + SX1276WriteFifo( RFBuffer + TxBytesSent, TxPacketSize - TxBytesSent ); + TxBytesSent += TxPacketSize - TxBytesSent; + } + } + + if( DIO0 == 1 ) // PacketSent + { + TxTimeoutTimer = GET_TICK_COUNT( ); + RFState = RF_STATE_TX_DONE; + SX1276FskSetOpMode( RF_OPMODE_STANDBY ); + } + + // Packet timeout + if( ( GET_TICK_COUNT( ) - TxTimeoutTimer ) > TICK_RATE_MS( 1000 ) ) + { + RFState = RF_STATE_TX_TIMEOUT; + } + break; + case RF_STATE_TX_DONE: + RFState = RF_STATE_IDLE; + result = RF_TX_DONE; + break; + case RF_STATE_TX_TIMEOUT: + RFState = RF_STATE_IDLE; + result = RF_TX_TIMEOUT; + break; + default: + break; + } + return result; +} + +#endif // USE_SX1276_RADIO diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Fsk.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Fsk.h new file mode 100644 index 000000000..a8a13c419 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Fsk.h @@ -0,0 +1,1460 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-Fsk.h + * \brief SX1276 RF chip driver mode FSK + * + * \version 2.0.B2 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#ifndef __SX1276_FSK_H__ +#define __SX1276_FSK_H__ + +/*! + * SX1276 FSK General parameters definition + */ + +typedef struct sFskSettings +{ + uint32_t RFFrequency; + uint32_t Bitrate; + uint32_t Fdev; + int8_t Power; + uint32_t RxBw; + uint32_t RxBwAfc; + bool CrcOn; + bool AfcOn; + uint8_t PayloadLength; +}tFskSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 256 +#define RF_BUFFER_SIZE 256 + +/*! + * RF state machine + */ +// FSK +typedef enum +{ + RF_STATE_IDLE, + RF_STATE_RX_INIT, + RF_STATE_RX_SYNC, + RF_STATE_RX_RUNNING, + RF_STATE_RX_DONE, + RF_STATE_RX_TIMEOUT, + RF_STATE_RX_LEN_ERROR, + RF_STATE_TX_INIT, + RF_STATE_TX_READY_WAIT, + RF_STATE_TX_RUNNING, + RF_STATE_TX_DONE, + RF_STATE_TX_TIMEOUT, +}tRFStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_FIFO 0x00 +// Common settings +#define REG_OPMODE 0x01 +#define REG_BITRATEMSB 0x02 +#define REG_BITRATELSB 0x03 +#define REG_FDEVMSB 0x04 +#define REG_FDEVLSB 0x05 +#define REG_FRFMSB 0x06 +#define REG_FRFMID 0x07 +#define REG_FRFLSB 0x08 +// Tx settings +#define REG_PACONFIG 0x09 +#define REG_PARAMP 0x0A +#define REG_OCP 0x0B +// Rx settings +#define REG_LNA 0x0C +#define REG_RXCONFIG 0x0D +#define REG_RSSICONFIG 0x0E +#define REG_RSSICOLLISION 0x0F +#define REG_RSSITHRESH 0x10 +#define REG_RSSIVALUE 0x11 +#define REG_RXBW 0x12 +#define REG_AFCBW 0x13 +#define REG_OOKPEAK 0x14 +#define REG_OOKFIX 0x15 +#define REG_OOKAVG 0x16 +#define REG_RES17 0x17 +#define REG_RES18 0x18 +#define REG_RES19 0x19 +#define REG_AFCFEI 0x1A +#define REG_AFCMSB 0x1B +#define REG_AFCLSB 0x1C +#define REG_FEIMSB 0x1D +#define REG_FEILSB 0x1E +#define REG_PREAMBLEDETECT 0x1F +#define REG_RXTIMEOUT1 0x20 +#define REG_RXTIMEOUT2 0x21 +#define REG_RXTIMEOUT3 0x22 +#define REG_RXDELAY 0x23 +// Oscillator settings +#define REG_OSC 0x24 +// Packet handler settings +#define REG_PREAMBLEMSB 0x25 +#define REG_PREAMBLELSB 0x26 +#define REG_SYNCCONFIG 0x27 +#define REG_SYNCVALUE1 0x28 +#define REG_SYNCVALUE2 0x29 +#define REG_SYNCVALUE3 0x2A +#define REG_SYNCVALUE4 0x2B +#define REG_SYNCVALUE5 0x2C +#define REG_SYNCVALUE6 0x2D +#define REG_SYNCVALUE7 0x2E +#define REG_SYNCVALUE8 0x2F +#define REG_PACKETCONFIG1 0x30 +#define REG_PACKETCONFIG2 0x31 +#define REG_PAYLOADLENGTH 0x32 +#define REG_NODEADRS 0x33 +#define REG_BROADCASTADRS 0x34 +#define REG_FIFOTHRESH 0x35 +// SM settings +#define REG_SEQCONFIG1 0x36 +#define REG_SEQCONFIG2 0x37 +#define REG_TIMERRESOL 0x38 +#define REG_TIMER1COEF 0x39 +#define REG_TIMER2COEF 0x3A +// Service settings +#define REG_IMAGECAL 0x3B +#define REG_TEMP 0x3C +#define REG_LOWBAT 0x3D +// Status +#define REG_IRQFLAGS1 0x3E +#define REG_IRQFLAGS2 0x3F +// I/O settings +#define REG_DIOMAPPING1 0x40 +#define REG_DIOMAPPING2 0x41 +// Version +#define REG_VERSION 0x42 +// Additional settings +#define REG_PLLHOP 0x44 +#define REG_TCXO 0x4B +#define REG_PADAC 0x4D +#define REG_FORMERTEMP 0x5B +#define REG_BITRATEFRAC 0x5D +#define REG_AGCREF 0x61 +#define REG_AGCTHRESH1 0x62 +#define REG_AGCTHRESH2 0x63 +#define REG_AGCTHRESH3 0x64 + + +/*! + * SX1276 FSK bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RF_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RF_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RF_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RF_OPMODE_MODULATIONTYPE_MASK 0x9F +#define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default +#define RF_OPMODE_MODULATIONTYPE_OOK 0x20 + +#define RF_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RF_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RF_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RF_OPMODE_MASK 0xF8 +#define RF_OPMODE_SLEEP 0x00 +#define RF_OPMODE_STANDBY 0x01 // Default +#define RF_OPMODE_SYNTHESIZER_TX 0x02 +#define RF_OPMODE_TRANSMITTER 0x03 +#define RF_OPMODE_SYNTHESIZER_RX 0x04 +#define RF_OPMODE_RECEIVER 0x05 + +/*! + * RegBitRate (bits/sec) + */ +#define RF_BITRATEMSB_1200_BPS 0x68 +#define RF_BITRATELSB_1200_BPS 0x2B +#define RF_BITRATEMSB_2400_BPS 0x34 +#define RF_BITRATELSB_2400_BPS 0x15 +#define RF_BITRATEMSB_4800_BPS 0x1A // Default +#define RF_BITRATELSB_4800_BPS 0x0B // Default +#define RF_BITRATEMSB_9600_BPS 0x0D +#define RF_BITRATELSB_9600_BPS 0x05 +#define RF_BITRATEMSB_15000_BPS 0x08 +#define RF_BITRATELSB_15000_BPS 0x55 +#define RF_BITRATEMSB_19200_BPS 0x06 +#define RF_BITRATELSB_19200_BPS 0x83 +#define RF_BITRATEMSB_38400_BPS 0x03 +#define RF_BITRATELSB_38400_BPS 0x41 +#define RF_BITRATEMSB_76800_BPS 0x01 +#define RF_BITRATELSB_76800_BPS 0xA1 +#define RF_BITRATEMSB_153600_BPS 0x00 +#define RF_BITRATELSB_153600_BPS 0xD0 +#define RF_BITRATEMSB_57600_BPS 0x02 +#define RF_BITRATELSB_57600_BPS 0x2C +#define RF_BITRATEMSB_115200_BPS 0x01 +#define RF_BITRATELSB_115200_BPS 0x16 +#define RF_BITRATEMSB_12500_BPS 0x0A +#define RF_BITRATELSB_12500_BPS 0x00 +#define RF_BITRATEMSB_25000_BPS 0x05 +#define RF_BITRATELSB_25000_BPS 0x00 +#define RF_BITRATEMSB_50000_BPS 0x02 +#define RF_BITRATELSB_50000_BPS 0x80 +#define RF_BITRATEMSB_100000_BPS 0x01 +#define RF_BITRATELSB_100000_BPS 0x40 +#define RF_BITRATEMSB_150000_BPS 0x00 +#define RF_BITRATELSB_150000_BPS 0xD5 +#define RF_BITRATEMSB_200000_BPS 0x00 +#define RF_BITRATELSB_200000_BPS 0xA0 +#define RF_BITRATEMSB_250000_BPS 0x00 +#define RF_BITRATELSB_250000_BPS 0x80 +#define RF_BITRATEMSB_32768_BPS 0x03 +#define RF_BITRATELSB_32768_BPS 0xD1 + +/*! + * RegFdev (Hz) + */ + +#define RF_FDEVMSB_BANDREG_MASK 0x3F +#define RF_FDEVMSB_BANDREG_AUTO 0x00 // Default +#define RF_FDEVMSB_BANDREG_DIV_BY_1 0x40 +#define RF_FDEVMSB_BANDREG_DIV_BY_2 0x80 +#define RF_FDEVMSB_BANDREG_DIV_BY_6 0xC0 + +#define RF_FDEVMSB_FDEV_MASK 0xC0 + +#define RF_FDEVMSB_2000_HZ 0x00 +#define RF_FDEVLSB_2000_HZ 0x21 +#define RF_FDEVMSB_5000_HZ 0x00 // Default +#define RF_FDEVLSB_5000_HZ 0x52 // Default +#define RF_FDEVMSB_10000_HZ 0x00 +#define RF_FDEVLSB_10000_HZ 0xA4 +#define RF_FDEVMSB_15000_HZ 0x00 +#define RF_FDEVLSB_15000_HZ 0xF6 +#define RF_FDEVMSB_20000_HZ 0x01 +#define RF_FDEVLSB_20000_HZ 0x48 +#define RF_FDEVMSB_25000_HZ 0x01 +#define RF_FDEVLSB_25000_HZ 0x9A +#define RF_FDEVMSB_30000_HZ 0x01 +#define RF_FDEVLSB_30000_HZ 0xEC +#define RF_FDEVMSB_35000_HZ 0x02 +#define RF_FDEVLSB_35000_HZ 0x3D +#define RF_FDEVMSB_40000_HZ 0x02 +#define RF_FDEVLSB_40000_HZ 0x8F +#define RF_FDEVMSB_45000_HZ 0x02 +#define RF_FDEVLSB_45000_HZ 0xE1 +#define RF_FDEVMSB_50000_HZ 0x03 +#define RF_FDEVLSB_50000_HZ 0x33 +#define RF_FDEVMSB_55000_HZ 0x03 +#define RF_FDEVLSB_55000_HZ 0x85 +#define RF_FDEVMSB_60000_HZ 0x03 +#define RF_FDEVLSB_60000_HZ 0xD7 +#define RF_FDEVMSB_65000_HZ 0x04 +#define RF_FDEVLSB_65000_HZ 0x29 +#define RF_FDEVMSB_70000_HZ 0x04 +#define RF_FDEVLSB_70000_HZ 0x7B +#define RF_FDEVMSB_75000_HZ 0x04 +#define RF_FDEVLSB_75000_HZ 0xCD +#define RF_FDEVMSB_80000_HZ 0x05 +#define RF_FDEVLSB_80000_HZ 0x1F +#define RF_FDEVMSB_85000_HZ 0x05 +#define RF_FDEVLSB_85000_HZ 0x71 +#define RF_FDEVMSB_90000_HZ 0x05 +#define RF_FDEVLSB_90000_HZ 0xC3 +#define RF_FDEVMSB_95000_HZ 0x06 +#define RF_FDEVLSB_95000_HZ 0x14 +#define RF_FDEVMSB_100000_HZ 0x06 +#define RF_FDEVLSB_100000_HZ 0x66 +#define RF_FDEVMSB_110000_HZ 0x07 +#define RF_FDEVLSB_110000_HZ 0x0A +#define RF_FDEVMSB_120000_HZ 0x07 +#define RF_FDEVLSB_120000_HZ 0xAE +#define RF_FDEVMSB_130000_HZ 0x08 +#define RF_FDEVLSB_130000_HZ 0x52 +#define RF_FDEVMSB_140000_HZ 0x08 +#define RF_FDEVLSB_140000_HZ 0xF6 +#define RF_FDEVMSB_150000_HZ 0x09 +#define RF_FDEVLSB_150000_HZ 0x9A +#define RF_FDEVMSB_160000_HZ 0x0A +#define RF_FDEVLSB_160000_HZ 0x3D +#define RF_FDEVMSB_170000_HZ 0x0A +#define RF_FDEVLSB_170000_HZ 0xE1 +#define RF_FDEVMSB_180000_HZ 0x0B +#define RF_FDEVLSB_180000_HZ 0x85 +#define RF_FDEVMSB_190000_HZ 0x0C +#define RF_FDEVLSB_190000_HZ 0x29 +#define RF_FDEVMSB_200000_HZ 0x0C +#define RF_FDEVLSB_200000_HZ 0xCD + +/*! + * RegFrf (MHz) + */ +#define RF_FRFMSB_863_MHZ 0xD7 +#define RF_FRFMID_863_MHZ 0xC0 +#define RF_FRFLSB_863_MHZ 0x00 +#define RF_FRFMSB_864_MHZ 0xD8 +#define RF_FRFMID_864_MHZ 0x00 +#define RF_FRFLSB_864_MHZ 0x00 +#define RF_FRFMSB_865_MHZ 0xD8 +#define RF_FRFMID_865_MHZ 0x40 +#define RF_FRFLSB_865_MHZ 0x00 +#define RF_FRFMSB_866_MHZ 0xD8 +#define RF_FRFMID_866_MHZ 0x80 +#define RF_FRFLSB_866_MHZ 0x00 +#define RF_FRFMSB_867_MHZ 0xD8 +#define RF_FRFMID_867_MHZ 0xC0 +#define RF_FRFLSB_867_MHZ 0x00 +#define RF_FRFMSB_868_MHZ 0xD9 +#define RF_FRFMID_868_MHZ 0x00 +#define RF_FRFLSB_868_MHZ 0x00 +#define RF_FRFMSB_869_MHZ 0xD9 +#define RF_FRFMID_869_MHZ 0x40 +#define RF_FRFLSB_869_MHZ 0x00 +#define RF_FRFMSB_870_MHZ 0xD9 +#define RF_FRFMID_870_MHZ 0x80 +#define RF_FRFLSB_870_MHZ 0x00 + +#define RF_FRFMSB_902_MHZ 0xE1 +#define RF_FRFMID_902_MHZ 0x80 +#define RF_FRFLSB_902_MHZ 0x00 +#define RF_FRFMSB_903_MHZ 0xE1 +#define RF_FRFMID_903_MHZ 0xC0 +#define RF_FRFLSB_903_MHZ 0x00 +#define RF_FRFMSB_904_MHZ 0xE2 +#define RF_FRFMID_904_MHZ 0x00 +#define RF_FRFLSB_904_MHZ 0x00 +#define RF_FRFMSB_905_MHZ 0xE2 +#define RF_FRFMID_905_MHZ 0x40 +#define RF_FRFLSB_905_MHZ 0x00 +#define RF_FRFMSB_906_MHZ 0xE2 +#define RF_FRFMID_906_MHZ 0x80 +#define RF_FRFLSB_906_MHZ 0x00 +#define RF_FRFMSB_907_MHZ 0xE2 +#define RF_FRFMID_907_MHZ 0xC0 +#define RF_FRFLSB_907_MHZ 0x00 +#define RF_FRFMSB_908_MHZ 0xE3 +#define RF_FRFMID_908_MHZ 0x00 +#define RF_FRFLSB_908_MHZ 0x00 +#define RF_FRFMSB_909_MHZ 0xE3 +#define RF_FRFMID_909_MHZ 0x40 +#define RF_FRFLSB_909_MHZ 0x00 +#define RF_FRFMSB_910_MHZ 0xE3 +#define RF_FRFMID_910_MHZ 0x80 +#define RF_FRFLSB_910_MHZ 0x00 +#define RF_FRFMSB_911_MHZ 0xE3 +#define RF_FRFMID_911_MHZ 0xC0 +#define RF_FRFLSB_911_MHZ 0x00 +#define RF_FRFMSB_912_MHZ 0xE4 +#define RF_FRFMID_912_MHZ 0x00 +#define RF_FRFLSB_912_MHZ 0x00 +#define RF_FRFMSB_913_MHZ 0xE4 +#define RF_FRFMID_913_MHZ 0x40 +#define RF_FRFLSB_913_MHZ 0x00 +#define RF_FRFMSB_914_MHZ 0xE4 +#define RF_FRFMID_914_MHZ 0x80 +#define RF_FRFLSB_914_MHZ 0x00 +#define RF_FRFMSB_915_MHZ 0xE4 // Default +#define RF_FRFMID_915_MHZ 0xC0 // Default +#define RF_FRFLSB_915_MHZ 0x00 // Default +#define RF_FRFMSB_916_MHZ 0xE5 +#define RF_FRFMID_916_MHZ 0x00 +#define RF_FRFLSB_916_MHZ 0x00 +#define RF_FRFMSB_917_MHZ 0xE5 +#define RF_FRFMID_917_MHZ 0x40 +#define RF_FRFLSB_917_MHZ 0x00 +#define RF_FRFMSB_918_MHZ 0xE5 +#define RF_FRFMID_918_MHZ 0x80 +#define RF_FRFLSB_918_MHZ 0x00 +#define RF_FRFMSB_919_MHZ 0xE5 +#define RF_FRFMID_919_MHZ 0xC0 +#define RF_FRFLSB_919_MHZ 0x00 +#define RF_FRFMSB_920_MHZ 0xE6 +#define RF_FRFMID_920_MHZ 0x00 +#define RF_FRFLSB_920_MHZ 0x00 +#define RF_FRFMSB_921_MHZ 0xE6 +#define RF_FRFMID_921_MHZ 0x40 +#define RF_FRFLSB_921_MHZ 0x00 +#define RF_FRFMSB_922_MHZ 0xE6 +#define RF_FRFMID_922_MHZ 0x80 +#define RF_FRFLSB_922_MHZ 0x00 +#define RF_FRFMSB_923_MHZ 0xE6 +#define RF_FRFMID_923_MHZ 0xC0 +#define RF_FRFLSB_923_MHZ 0x00 +#define RF_FRFMSB_924_MHZ 0xE7 +#define RF_FRFMID_924_MHZ 0x00 +#define RF_FRFLSB_924_MHZ 0x00 +#define RF_FRFMSB_925_MHZ 0xE7 +#define RF_FRFMID_925_MHZ 0x40 +#define RF_FRFLSB_925_MHZ 0x00 +#define RF_FRFMSB_926_MHZ 0xE7 +#define RF_FRFMID_926_MHZ 0x80 +#define RF_FRFLSB_926_MHZ 0x00 +#define RF_FRFMSB_927_MHZ 0xE7 +#define RF_FRFMID_927_MHZ 0xC0 +#define RF_FRFLSB_927_MHZ 0x00 +#define RF_FRFMSB_928_MHZ 0xE8 +#define RF_FRFMID_928_MHZ 0x00 +#define RF_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RF_PACONFIG_PASELECT_MASK 0x7F +#define RF_PACONFIG_PASELECT_PABOOST 0x80 +#define RF_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RF_PACONFIG_MAX_POWER_MASK 0x8F + +#define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F +#define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default +#define RF_PARAMP_MODULATIONSHAPING_01 0x20 +#define RF_PARAMP_MODULATIONSHAPING_10 0x40 +#define RF_PARAMP_MODULATIONSHAPING_11 0x60 + +#define RF_PARAMP_TXBANDFORCE_MASK 0xEF +#define RF_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RF_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RF_PARAMP_MASK 0xF0 +#define RF_PARAMP_3400_US 0x00 +#define RF_PARAMP_2000_US 0x01 +#define RF_PARAMP_1000_US 0x02 +#define RF_PARAMP_0500_US 0x03 +#define RF_PARAMP_0250_US 0x04 +#define RF_PARAMP_0125_US 0x05 +#define RF_PARAMP_0100_US 0x06 +#define RF_PARAMP_0062_US 0x07 +#define RF_PARAMP_0050_US 0x08 +#define RF_PARAMP_0040_US 0x09 // Default +#define RF_PARAMP_0031_US 0x0A +#define RF_PARAMP_0025_US 0x0B +#define RF_PARAMP_0020_US 0x0C +#define RF_PARAMP_0015_US 0x0D +#define RF_PARAMP_0012_US 0x0E +#define RF_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RF_OCP_MASK 0xDF +#define RF_OCP_ON 0x20 // Default +#define RF_OCP_OFF 0x00 + +#define RF_OCP_TRIM_MASK 0xE0 +#define RF_OCP_TRIM_045_MA 0x00 +#define RF_OCP_TRIM_050_MA 0x01 +#define RF_OCP_TRIM_055_MA 0x02 +#define RF_OCP_TRIM_060_MA 0x03 +#define RF_OCP_TRIM_065_MA 0x04 +#define RF_OCP_TRIM_070_MA 0x05 +#define RF_OCP_TRIM_075_MA 0x06 +#define RF_OCP_TRIM_080_MA 0x07 +#define RF_OCP_TRIM_085_MA 0x08 +#define RF_OCP_TRIM_090_MA 0x09 +#define RF_OCP_TRIM_095_MA 0x0A +#define RF_OCP_TRIM_100_MA 0x0B // Default +#define RF_OCP_TRIM_105_MA 0x0C +#define RF_OCP_TRIM_110_MA 0x0D +#define RF_OCP_TRIM_115_MA 0x0E +#define RF_OCP_TRIM_120_MA 0x0F +#define RF_OCP_TRIM_130_MA 0x10 +#define RF_OCP_TRIM_140_MA 0x11 +#define RF_OCP_TRIM_150_MA 0x12 +#define RF_OCP_TRIM_160_MA 0x13 +#define RF_OCP_TRIM_170_MA 0x14 +#define RF_OCP_TRIM_180_MA 0x15 +#define RF_OCP_TRIM_190_MA 0x16 +#define RF_OCP_TRIM_200_MA 0x17 +#define RF_OCP_TRIM_210_MA 0x18 +#define RF_OCP_TRIM_220_MA 0x19 +#define RF_OCP_TRIM_230_MA 0x1A +#define RF_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RF_LNA_GAIN_MASK 0x1F +#define RF_LNA_GAIN_G1 0x20 // Default +#define RF_LNA_GAIN_G2 0x40 +#define RF_LNA_GAIN_G3 0x60 +#define RF_LNA_GAIN_G4 0x80 +#define RF_LNA_GAIN_G5 0xA0 +#define RF_LNA_GAIN_G6 0xC0 + +#define RF_LNA_BOOST_LF_MASK 0xE7 +#define RF_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RF_LNA_BOOST_LF_GAIN 0x08 +#define RF_LNA_BOOST_LF_IP3 0x10 +#define RF_LNA_BOOST_LF_BOOST 0x18 + +#define RF_LNA_RXBANDFORCE_MASK 0xFB +#define RF_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RF_LNA_RXBANDFORCE_AUTO 0x00 // Default + +#define RF_LNA_BOOST_HF_MASK 0xFC +#define RF_LNA_BOOST_HF_OFF 0x00 // Default +#define RF_LNA_BOOST_HF_ON 0x03 + +/*! + * RegRxConfig + */ +#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F +#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default + +#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only + +#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only + +#define RF_RXCONFIG_AFCAUTO_MASK 0xEF +#define RF_RXCONFIG_AFCAUTO_ON 0x10 +#define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default + +#define RF_RXCONFIG_AGCAUTO_MASK 0xF7 +#define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default +#define RF_RXCONFIG_AGCAUTO_OFF 0x00 + +#define RF_RXCONFIG_RXTRIGER_MASK 0xF8 +#define RF_RXCONFIG_RXTRIGER_OFF 0x00 +#define RF_RXCONFIG_RXTRIGER_RSSI 0x01 +#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default +#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 + +/*! + * RegRssiConfig + */ +#define RF_RSSICONFIG_OFFSET_MASK 0x07 +#define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default +#define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 +#define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 +#define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 +#define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 +#define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 +#define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 +#define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 +#define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 +#define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 +#define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 +#define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 +#define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 +#define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 +#define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 +#define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 +#define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 +#define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 +#define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 +#define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 +#define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 +#define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 +#define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 +#define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 +#define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 +#define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 +#define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 +#define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 +#define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 +#define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 +#define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 +#define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 + +#define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 +#define RF_RSSICONFIG_SMOOTHING_2 0x00 +#define RF_RSSICONFIG_SMOOTHING_4 0x01 +#define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default +#define RF_RSSICONFIG_SMOOTHING_16 0x03 +#define RF_RSSICONFIG_SMOOTHING_32 0x04 +#define RF_RSSICONFIG_SMOOTHING_64 0x05 +#define RF_RSSICONFIG_SMOOTHING_128 0x06 +#define RF_RSSICONFIG_SMOOTHING_256 0x07 + +/*! + * RegRssiCollision + */ +#define RF_RSSICOLISION_THRESHOLD 0x0A // Default + +/*! + * RegRssiThresh + */ +#define RF_RSSITHRESH_THRESHOLD 0xFF // Default + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegRxBw + */ +#define RF_RXBW_MANT_MASK 0xE7 +#define RF_RXBW_MANT_16 0x00 +#define RF_RXBW_MANT_20 0x08 +#define RF_RXBW_MANT_24 0x10 // Default + +#define RF_RXBW_EXP_MASK 0xF8 +#define RF_RXBW_EXP_0 0x00 +#define RF_RXBW_EXP_1 0x01 +#define RF_RXBW_EXP_2 0x02 +#define RF_RXBW_EXP_3 0x03 +#define RF_RXBW_EXP_4 0x04 +#define RF_RXBW_EXP_5 0x05 // Default +#define RF_RXBW_EXP_6 0x06 +#define RF_RXBW_EXP_7 0x07 + +/*! + * RegAfcBw + */ +#define RF_AFCBW_MANTAFC_MASK 0xE7 +#define RF_AFCBW_MANTAFC_16 0x00 +#define RF_AFCBW_MANTAFC_20 0x08 // Default +#define RF_AFCBW_MANTAFC_24 0x10 + +#define RF_AFCBW_EXPAFC_MASK 0xF8 +#define RF_AFCBW_EXPAFC_0 0x00 +#define RF_AFCBW_EXPAFC_1 0x01 +#define RF_AFCBW_EXPAFC_2 0x02 +#define RF_AFCBW_EXPAFC_3 0x03 // Default +#define RF_AFCBW_EXPAFC_4 0x04 +#define RF_AFCBW_EXPAFC_5 0x05 +#define RF_AFCBW_EXPAFC_6 0x06 +#define RF_AFCBW_EXPAFC_7 0x07 + +/*! + * RegOokPeak + */ +#define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default +#define RF_OOKPEAK_BITSYNC_ON 0x20 // Default +#define RF_OOKPEAK_BITSYNC_OFF 0x00 + +#define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 +#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 +#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default +#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 + +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 + +/*! + * RegOokFix + */ +#define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default + +/*! + * RegOokAvg + */ +#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F +#define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default +#define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 + +#define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 +#define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default +#define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 +#define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 +#define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C + +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 + +/*! + * RegAfcFei + */ +#define RF_AFCFEI_AGCSTART 0x10 + +#define RF_AFCFEI_AFCCLEAR 0x02 + +#define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE +#define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 +#define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default + +/*! + * RegAfcMsb (Read Only) + */ + +/*! + * RegAfcLsb (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegPreambleDetect + */ +#define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F +#define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default +#define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 + +#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F +#define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 +#define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default +#define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 +#define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 + +#define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 +#define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 +#define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 +#define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 +#define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 +#define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 +#define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 +#define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 +#define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 +#define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 +#define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 +#define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default +#define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B +#define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C +#define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D +#define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E +#define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F +#define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 +#define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 +#define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 +#define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 +#define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 +#define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 +#define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 +#define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 +#define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 +#define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 +#define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A +#define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B +#define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C +#define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D +#define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E +#define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F + +/*! + * RegRxTimeout1 + */ +#define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default + +/*! + * RegRxTimeout2 + */ +#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default + +/*! + * RegRxTimeout3 + */ +#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default + +/*! + * RegRxDelay + */ +#define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default + +/*! + * RegOsc + */ +#define RF_OSC_RCCALSTART 0x08 + +#define RF_OSC_CLKOUT_MASK 0xF8 +#define RF_OSC_CLKOUT_32_MHZ 0x00 +#define RF_OSC_CLKOUT_16_MHZ 0x01 +#define RF_OSC_CLKOUT_8_MHZ 0x02 +#define RF_OSC_CLKOUT_4_MHZ 0x03 +#define RF_OSC_CLKOUT_2_MHZ 0x04 +#define RF_OSC_CLKOUT_1_MHZ 0x05 // Default +#define RF_OSC_CLKOUT_RC 0x06 +#define RF_OSC_CLKOUT_OFF 0x07 + +/*! + * RegPreambleMsb/RegPreambleLsb + */ +#define RF_PREAMBLEMSB_SIZE 0x00 // Default +#define RF_PREAMBLELSB_SIZE 0x03 // Default + +/*! + * RegSyncConfig + */ +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 + + +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default + +#define RF_SYNCCONFIG_SYNC_MASK 0xEF +#define RF_SYNCCONFIG_SYNC_ON 0x10 // Default +#define RF_SYNCCONFIG_SYNC_OFF 0x00 + + +#define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 +#define RF_SYNCCONFIG_SYNCSIZE_1 0x00 +#define RF_SYNCCONFIG_SYNCSIZE_2 0x01 +#define RF_SYNCCONFIG_SYNCSIZE_3 0x02 +#define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default +#define RF_SYNCCONFIG_SYNCSIZE_5 0x04 +#define RF_SYNCCONFIG_SYNCSIZE_6 0x05 +#define RF_SYNCCONFIG_SYNCSIZE_7 0x06 +#define RF_SYNCCONFIG_SYNCSIZE_8 0x07 + +/*! + * RegSyncValue1-8 + */ +#define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default + +/*! + * RegPacketConfig1 + */ +#define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F +#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 +#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default + +#define RF_PACKETCONFIG1_DCFREE_MASK 0x9F +#define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default +#define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 +#define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 + +#define RF_PACKETCONFIG1_CRC_MASK 0xEF +#define RF_PACKETCONFIG1_CRC_ON 0x10 // Default +#define RF_PACKETCONFIG1_CRC_OFF 0x00 + +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 + +#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 +#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 + +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 + +/*! + * RegPacketConfig2 + */ + +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80 +#define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default + +#define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF +#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 +#define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default + +#define RF_PACKETCONFIG2_IOHOME_MASK 0xDF +#define RF_PACKETCONFIG2_IOHOME_ON 0x20 +#define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_BEACON_MASK 0xF7 +#define RF_PACKETCONFIG2_BEACON_ON 0x08 +#define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 + +/*! + * RegPayloadLength + */ +#define RF_PAYLOADLENGTH_LENGTH 0x40 // Default + +/*! + * RegNodeAdrs + */ +#define RF_NODEADDRESS_ADDRESS 0x00 + +/*! + * RegBroadcastAdrs + */ +#define RF_BROADCASTADDRESS_ADDRESS 0x00 + +/*! + * RegFifoThresh + */ +#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 + +#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default + +/*! + * RegSeqConfig1 + */ +#define RF_SEQCONFIG1_SEQUENCER_START 0x80 + +#define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 + +#define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF +#define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 +#define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default + +#define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 +#define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMSTART_TORX 0x08 +#define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 +#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 + +#define RF_SEQCONFIG1_LPS_MASK 0xFB +#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default +#define RF_SEQCONFIG1_LPS_IDLE 0x04 + +#define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD +#define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default +#define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 + +#define RF_SEQCONFIG1_FROMTX_MASK 0xFE +#define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMTX_TORX 0x01 + +/*! + * RegSeqConfig2 + */ +#define RF_SEQCONFIG2_FROMRX_MASK 0x1F +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 +#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 + +#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 + +#define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 +#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default +#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 +#define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 +#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 +#define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 + +/*! + * RegTimerResol + */ +#define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 +#define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 +#define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 +#define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C + +#define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC +#define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 +#define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 +#define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 + +/*! + * RegTimer1Coef + */ +#define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default + +/*! + * RegTimer2Coef + */ +#define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default + +/*! + * RegImageCal + */ +#define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F +#define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 +#define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default + +#define RF_IMAGECAL_IMAGECAL_MASK 0xBF +#define RF_IMAGECAL_IMAGECAL_START 0x40 + +#define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 +#define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default + +#define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 +#define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 + +#define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 +#define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 +#define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default +#define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 +#define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 + +#define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE +#define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default +#define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 + +/*! + * RegTemp (Read Only) + */ + +/*! + * RegLowBat + */ +#define RF_LOWBAT_MASK 0xF7 +#define RF_LOWBAT_ON 0x08 +#define RF_LOWBAT_OFF 0x00 // Default + +#define RF_LOWBAT_TRIM_MASK 0xF8 +#define RF_LOWBAT_TRIM_1695 0x00 +#define RF_LOWBAT_TRIM_1764 0x01 +#define RF_LOWBAT_TRIM_1835 0x02 // Default +#define RF_LOWBAT_TRIM_1905 0x03 +#define RF_LOWBAT_TRIM_1976 0x04 +#define RF_LOWBAT_TRIM_2045 0x05 +#define RF_LOWBAT_TRIM_2116 0x06 +#define RF_LOWBAT_TRIM_2185 0x07 + +/*! + * RegIrqFlags1 + */ +#define RF_IRQFLAGS1_MODEREADY 0x80 + +#define RF_IRQFLAGS1_RXREADY 0x40 + +#define RF_IRQFLAGS1_TXREADY 0x20 + +#define RF_IRQFLAGS1_PLLLOCK 0x10 + +#define RF_IRQFLAGS1_RSSI 0x08 + +#define RF_IRQFLAGS1_TIMEOUT 0x04 + +#define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 + +#define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 + +/*! + * RegIrqFlags2 + */ +#define RF_IRQFLAGS2_FIFOFULL 0x80 + +#define RF_IRQFLAGS2_FIFOEMPTY 0x40 + +#define RF_IRQFLAGS2_FIFOLEVEL 0x20 + +#define RF_IRQFLAGS2_FIFOOVERRUN 0x10 + +#define RF_IRQFLAGS2_PACKETSENT 0x08 + +#define RF_IRQFLAGS2_PAYLOADREADY 0x04 + +#define RF_IRQFLAGS2_CRCOK 0x02 + +#define RF_IRQFLAGS2_LOWBAT 0x01 + +/*! + * RegDioMapping1 + */ +#define RF_DIOMAPPING1_DIO0_MASK 0x3F +#define RF_DIOMAPPING1_DIO0_00 0x00 // Default +#define RF_DIOMAPPING1_DIO0_01 0x40 +#define RF_DIOMAPPING1_DIO0_10 0x80 +#define RF_DIOMAPPING1_DIO0_11 0xC0 + +#define RF_DIOMAPPING1_DIO1_MASK 0xCF +#define RF_DIOMAPPING1_DIO1_00 0x00 // Default +#define RF_DIOMAPPING1_DIO1_01 0x10 +#define RF_DIOMAPPING1_DIO1_10 0x20 +#define RF_DIOMAPPING1_DIO1_11 0x30 + +#define RF_DIOMAPPING1_DIO2_MASK 0xF3 +#define RF_DIOMAPPING1_DIO2_00 0x00 // Default +#define RF_DIOMAPPING1_DIO2_01 0x04 +#define RF_DIOMAPPING1_DIO2_10 0x08 +#define RF_DIOMAPPING1_DIO2_11 0x0C + +#define RF_DIOMAPPING1_DIO3_MASK 0xFC +#define RF_DIOMAPPING1_DIO3_00 0x00 // Default +#define RF_DIOMAPPING1_DIO3_01 0x01 +#define RF_DIOMAPPING1_DIO3_10 0x02 +#define RF_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RF_DIOMAPPING2_DIO4_MASK 0x3F +#define RF_DIOMAPPING2_DIO4_00 0x00 // Default +#define RF_DIOMAPPING2_DIO4_01 0x40 +#define RF_DIOMAPPING2_DIO4_10 0x80 +#define RF_DIOMAPPING2_DIO4_11 0xC0 + +#define RF_DIOMAPPING2_DIO5_MASK 0xCF +#define RF_DIOMAPPING2_DIO5_00 0x00 // Default +#define RF_DIOMAPPING2_DIO5_01 0x10 +#define RF_DIOMAPPING2_DIO5_10 0x20 +#define RF_DIOMAPPING2_DIO5_11 0x30 + +#define RF_DIOMAPPING2_MAP_MASK 0xFE +#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPllHop + */ +#define RF_PLLHOP_FASTHOP_MASK 0x7F +#define RF_PLLHOP_FASTHOP_ON 0x80 +#define RF_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RF_TCXO_TCXOINPUT_MASK 0xEF +#define RF_TCXO_TCXOINPUT_ON 0x10 +#define RF_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RF_PADAC_20DBM_MASK 0xF8 +#define RF_PADAC_20DBM_ON 0x07 +#define RF_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RF_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RF_PLLLOWPN_BANDWIDTH_75 0x00 +#define RF_PLLLOWPN_BANDWIDTH_150 0x40 +#define RF_PLLLOWPN_BANDWIDTH_225 0x80 +#define RF_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +typedef struct sSX1276 +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + uint8_t RegBitrateMsb; // 0x02 + uint8_t RegBitrateLsb; // 0x03 + uint8_t RegFdevMsb; // 0x04 + uint8_t RegFdevLsb; // 0x05 + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + uint8_t RegRxConfig; // 0x0D + uint8_t RegRssiConfig; // 0x0E + uint8_t RegRssiCollision; // 0x0F + uint8_t RegRssiThresh; // 0x10 + uint8_t RegRssiValue; // 0x11 + uint8_t RegRxBw; // 0x12 + uint8_t RegAfcBw; // 0x13 + uint8_t RegOokPeak; // 0x14 + uint8_t RegOokFix; // 0x15 + uint8_t RegOokAvg; // 0x16 + uint8_t RegRes17; // 0x17 + uint8_t RegRes18; // 0x18 + uint8_t RegRes19; // 0x19 + uint8_t RegAfcFei; // 0x1A + uint8_t RegAfcMsb; // 0x1B + uint8_t RegAfcLsb; // 0x1C + uint8_t RegFeiMsb; // 0x1D + uint8_t RegFeiLsb; // 0x1E + uint8_t RegPreambleDetect; // 0x1F + uint8_t RegRxTimeout1; // 0x20 + uint8_t RegRxTimeout2; // 0x21 + uint8_t RegRxTimeout3; // 0x22 + uint8_t RegRxDelay; // 0x23 + // Oscillator settings + uint8_t RegOsc; // 0x24 + // Packet handler settings + uint8_t RegPreambleMsb; // 0x25 + uint8_t RegPreambleLsb; // 0x26 + uint8_t RegSyncConfig; // 0x27 + uint8_t RegSyncValue1; // 0x28 + uint8_t RegSyncValue2; // 0x29 + uint8_t RegSyncValue3; // 0x2A + uint8_t RegSyncValue4; // 0x2B + uint8_t RegSyncValue5; // 0x2C + uint8_t RegSyncValue6; // 0x2D + uint8_t RegSyncValue7; // 0x2E + uint8_t RegSyncValue8; // 0x2F + uint8_t RegPacketConfig1; // 0x30 + uint8_t RegPacketConfig2; // 0x31 + uint8_t RegPayloadLength; // 0x32 + uint8_t RegNodeAdrs; // 0x33 + uint8_t RegBroadcastAdrs; // 0x34 + uint8_t RegFifoThresh; // 0x35 + // Sequencer settings + uint8_t RegSeqConfig1; // 0x36 + uint8_t RegSeqConfig2; // 0x37 + uint8_t RegTimerResol; // 0x38 + uint8_t RegTimer1Coef; // 0x39 + uint8_t RegTimer2Coef; // 0x3A + // Service settings + uint8_t RegImageCal; // 0x3B + uint8_t RegTemp; // 0x3C + uint8_t RegLowBat; // 0x3D + // Status + uint8_t RegIrqFlags1; // 0x3E + uint8_t RegIrqFlags2; // 0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + // Additional settings + uint8_t RegAgcRef; // 0x43 + uint8_t RegAgcThresh1; // 0x44 + uint8_t RegAgcThresh2; // 0x45 + uint8_t RegAgcThresh3; // 0x46 + // Test + uint8_t RegTestReserved47[0x4B - 0x47]; // 0x47-0x4A + // Additional settings + uint8_t RegPllHop; // 0x4B + uint8_t RegTestReserved4C; // 0x4C + uint8_t RegPaDac; // 0x4D + // Test + uint8_t RegTestReserved4E[0x58-0x4E]; // 0x4E-0x57 + // Additional settings + uint8_t RegTcxo; // 0x58 + // Test + uint8_t RegTestReserved59; // 0x59 + // Test + uint8_t RegTestReserved5B; // 0x5B + // Additional settings + uint8_t RegPll; // 0x5C + // Test + uint8_t RegTestReserved5D; // 0x5D + // Additional settings + uint8_t RegPllLowPn; // 0x5E + // Test + uint8_t RegTestReserved5F[0x6C - 0x5F]; // 0x5F-0x6B + // Additional settings + uint8_t RegFormerTemp; // 0x6C + // Test + uint8_t RegTestReserved6D[0x70 - 0x6D]; // 0x6D-0x6F + // Additional settings + uint8_t RegBitrateFrac; // 0x70 +}tSX1276; + +extern tSX1276* SX1276; + +/*! + * \brief Initializes the SX1276 + */ +void SX1276FskInit( void ); + +/*! + * \brief Sets the SX1276 to datasheet default values + */ +void SX1276FskSetDefaults( void ); + +/*! + * \brief Resets the SX1276 + */ +void SX1276FskReset( void ); + +/*! + * \brief Enables/Disables the LoRa modem + * + * \param [IN]: enable [true, false] + */ +void SX1276FskSetLoRaOn( bool enable ); + +/*! + * \brief Sets the SX1276 operating mode + * + * \param [IN] opMode New operating mode + */ +void SX1276FskSetOpMode( uint8_t opMode ); + +/*! + * \brief Gets the SX1276 operating mode + * + * \retval opMode Current operating mode + */ +uint8_t SX1276FskGetOpMode( void ); + +/*! + * \brief Trigs and reads the FEI + * + * \retval feiValue Frequency error value. + */ +int32_t SX1276FskReadFei( void ); + +/*! + * \brief Reads the current AFC value + * + * \retval afcValue Frequency offset value. + */ +int32_t SX1276FskReadAfc( void ); + +/*! + * \brief Reads the current Rx gain setting + * + * \retval rxGain Current gain setting + */ +uint8_t SX1276FskReadRxGain( void ); + +/*! + * \brief Trigs and reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276FskReadRssi( void ); + +/*! + * \brief Gets the Rx gain value measured while receiving the packet + * + * \retval rxGainValue Current Rx gain value + */ +uint8_t SX1276FskGetPacketRxGain( void ); + +/*! + * \brief Gets the RSSI value measured while receiving the packet + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276FskGetPacketRssi( void ); + +/*! + * \brief Gets the AFC value measured while receiving the packet + * + * \retval afcValue Current AFC value in [Hz] + */ +uint32_t SX1276FskGetPacketAfc( void ); + +/*! + * \brief Sets the radio in Rx mode. Waiting for a packet + */ +void SX1276FskStartRx( void ); + +/*! + * \brief Gets a copy of the current received buffer + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276FskGetRxPacket( void *buffer, uint16_t *size ); + +/*! + * \brief Sets a copy of the buffer to be transmitted and starts the + * transmission + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276FskSetTxPacket( const void *buffer, uint16_t size ); + +/*! + * \brief Gets the current RFState + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint8_t SX1276FskGetRFState( void ); + +/*! + * \brief Sets the new state of the RF state machine + * + * \param [IN]: state New RF state machine state + */ +void SX1276FskSetRFState( uint8_t state ); + +/*! + * \brief Process the FSK modem Rx and Tx state machines depending on the + * SX1276 operating mode. + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint32_t SX1276FskProcess( void ); + +#endif //__SX1276_FSK_H__ \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-FskMisc.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-FskMisc.c new file mode 100644 index 000000000..d98aa49c8 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-FskMisc.c @@ -0,0 +1,521 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-FskMisc.c + * \brief SX1276 RF chip high level functions driver + * + * \remark Optional support functions. + * These functions are defined only to easy the change of the + * parameters. + * For a final firmware the radio parameters will be known so + * there is no need to support all possible parameters. + * Removing these functions will greatly reduce the final firmware + * size. + * + * \version 2.0.0 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#include + +#include "platform.h" + +#if defined( USE_SX1276_RADIO ) + +#include "sx1276-Hal.h" +#include "sx1276.h" + +#include "sx1276-Fsk.h" +#include "sx1276-FskMisc.h" + +extern tFskSettings FskSettings; + +void SX1276FskSetRFFrequency( uint32_t freq ) +{ + FskSettings.RFFrequency = freq; + + freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP ); + SX1276->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF ); + SX1276->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF ); + SX1276->RegFrfLsb = ( uint8_t )( freq & 0xFF ); + SX1276WriteBuffer( REG_FRFMSB, &SX1276->RegFrfMsb, 3 ); +} + +uint32_t SX1276FskGetRFFrequency( void ) +{ + SX1276ReadBuffer( REG_FRFMSB, &SX1276->RegFrfMsb, 3 ); + FskSettings.RFFrequency = ( ( uint32_t )SX1276->RegFrfMsb << 16 ) | ( ( uint32_t )SX1276->RegFrfMid << 8 ) | ( ( uint32_t )SX1276->RegFrfLsb ); + FskSettings.RFFrequency = ( uint32_t )( ( double )FskSettings.RFFrequency * ( double )FREQ_STEP ); + + return FskSettings.RFFrequency; +} + +void SX1276FskRxCalibrate( void ) +{ + // the function RadioRxCalibrate is called just after the reset so all register are at their default values + uint8_t regPaConfigInitVal; + uint32_t initialFreq; + + // save register values; + SX1276Read( REG_PACONFIG, ®PaConfigInitVal ); + initialFreq = SX1276FskGetRFFrequency( ); + + // Cut the PA just in case + SX1276->RegPaConfig = 0x00; // RFO output, power = -1 dBm + SX1276Write( REG_PACONFIG, SX1276->RegPaConfig ); + + // Set Frequency in HF band + SX1276FskSetRFFrequency( 860000000 ); + + // Rx chain re-calibration workaround + SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal ); + SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START; + SX1276Write( REG_IMAGECAL, SX1276->RegImageCal ); + + SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal ); + // rx_cal_run goes low when calibration in finished + while( ( SX1276->RegImageCal & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING ) + { + SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal ); + } + + // reload saved values into the registers + SX1276->RegPaConfig = regPaConfigInitVal; + SX1276Write( REG_PACONFIG, SX1276->RegPaConfig ); + + SX1276FskSetRFFrequency( initialFreq ); + +} + +void SX1276FskSetBitrate( uint32_t bitrate ) +{ + FskSettings.Bitrate = bitrate; + + bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )bitrate ); + SX1276->RegBitrateMsb = ( uint8_t )( bitrate >> 8 ); + SX1276->RegBitrateLsb = ( uint8_t )( bitrate & 0xFF ); + SX1276WriteBuffer( REG_BITRATEMSB, &SX1276->RegBitrateMsb, 2 ); +} + +uint32_t SX1276FskGetBitrate( void ) +{ + SX1276ReadBuffer( REG_BITRATEMSB, &SX1276->RegBitrateMsb, 2 ); + FskSettings.Bitrate = ( ( ( uint32_t )SX1276->RegBitrateMsb << 8 ) | ( ( uint32_t )SX1276->RegBitrateLsb ) ); + FskSettings.Bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )FskSettings.Bitrate ); + + return FskSettings.Bitrate; +} + +void SX1276FskSetFdev( uint32_t fdev ) +{ + FskSettings.Fdev = fdev; + + SX1276Read( REG_FDEVMSB, &SX1276->RegFdevMsb ); + + fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP ); + SX1276->RegFdevMsb = ( ( SX1276->RegFdevMsb & RF_FDEVMSB_FDEV_MASK ) | ( ( ( uint8_t )( fdev >> 8 ) ) & ~RF_FDEVMSB_FDEV_MASK ) ); + SX1276->RegFdevLsb = ( uint8_t )( fdev & 0xFF ); + SX1276WriteBuffer( REG_FDEVMSB, &SX1276->RegFdevMsb, 2 ); +} + +uint32_t SX1276FskGetFdev( void ) +{ + SX1276ReadBuffer( REG_FDEVMSB, &SX1276->RegFdevMsb, 2 ); + FskSettings.Fdev = ( ( ( uint32_t )( ( SX1276->RegFdevMsb << 8 ) & ~RF_FDEVMSB_FDEV_MASK ) ) | ( ( uint32_t )SX1276->RegFdevLsb ) ); + FskSettings.Fdev = ( uint16_t )( ( double )FskSettings.Fdev * ( double )FREQ_STEP ); + + return FskSettings.Fdev; +} + +void SX1276FskSetRFPower( int8_t power ) +{ + SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig ); + SX1276Read( REG_PADAC, &SX1276->RegPaDac ); + + if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) + { + if( ( SX1276->RegPaDac & 0x87 ) == 0x87 ) + { + if( power < 5 ) + { + power = 5; + } + if( power > 20 ) + { + power = 20; + } + SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70; + SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F ); + } + else + { + if( power < 2 ) + { + power = 2; + } + if( power > 17 ) + { + power = 17; + } + SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70; + SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F ); + } + } + else + { + if( power < -1 ) + { + power = -1; + } + if( power > 14 ) + { + power = 14; + } + SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70; + SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F ); + } + SX1276Write( REG_PACONFIG, SX1276->RegPaConfig ); + FskSettings.Power = power; +} + +int8_t SX1276FskGetRFPower( void ) +{ + SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig ); + SX1276Read( REG_PADAC, &SX1276->RegPaDac ); + + if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) + { + if( ( SX1276->RegPaDac & 0x07 ) == 0x07 ) + { + FskSettings.Power = 5 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK ); + } + else + { + FskSettings.Power = 2 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK ); + } + } + else + { + FskSettings.Power = -1 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK ); + } + return FskSettings.Power; +} + +/*! + * \brief Computes the Rx bandwidth with the mantisse and exponent + * + * \param [IN] mantisse Mantisse of the bandwidth value + * \param [IN] exponent Exponent of the bandwidth value + * \retval bandwidth Computed bandwidth + */ +static uint32_t SX1276FskComputeRxBw( uint8_t mantisse, uint8_t exponent ) +{ + // rxBw + if( ( SX1276->RegOpMode & RF_OPMODE_MODULATIONTYPE_FSK ) == RF_OPMODE_MODULATIONTYPE_FSK ) + { + return ( uint32_t )( ( double )XTAL_FREQ / ( mantisse * ( double )pow( 2, exponent + 2 ) ) ); + } + else + { + return ( uint32_t )( ( double )XTAL_FREQ / ( mantisse * ( double )pow( 2, exponent + 3 ) ) ); + } +} + +/*! + * \brief Computes the mantisse and exponent from the bandwitdh value + * + * \param [IN] rxBwValue Bandwidth value + * \param [OUT] mantisse Mantisse of the bandwidth value + * \param [OUT] exponent Exponent of the bandwidth value + */ +static void SX1276FskComputeRxBwMantExp( uint32_t rxBwValue, uint8_t* mantisse, uint8_t* exponent ) +{ + uint8_t tmpExp = 0; + uint8_t tmpMant = 0; + + double tmpRxBw = 0; + double rxBwMin = 10e6; + + for( tmpExp = 0; tmpExp < 8; tmpExp++ ) + { + for( tmpMant = 16; tmpMant <= 24; tmpMant += 4 ) + { + if( ( SX1276->RegOpMode & RF_OPMODE_MODULATIONTYPE_FSK ) == RF_OPMODE_MODULATIONTYPE_FSK ) + { + tmpRxBw = ( double )XTAL_FREQ / ( tmpMant * ( double )pow( 2, tmpExp + 2 ) ); + } + else + { + tmpRxBw = ( double )XTAL_FREQ / ( tmpMant * ( double )pow( 2, tmpExp + 3 ) ); + } + if( fabs( tmpRxBw - rxBwValue ) < rxBwMin ) + { + rxBwMin = fabs( tmpRxBw - rxBwValue ); + *mantisse = tmpMant; + *exponent = tmpExp; + } + } + } +} + +void SX1276FskSetDccBw( uint8_t* reg, uint32_t dccValue, uint32_t rxBwValue ) +{ + uint8_t mantisse = 0; + uint8_t exponent = 0; + + if( reg == &SX1276->RegRxBw ) + { + *reg = ( uint8_t )dccValue & 0x60; + } + else + { + *reg = 0; + } + + SX1276FskComputeRxBwMantExp( rxBwValue, &mantisse, &exponent ); + + switch( mantisse ) + { + case 16: + *reg |= ( uint8_t )( 0x00 | ( exponent & 0x07 ) ); + break; + case 20: + *reg |= ( uint8_t )( 0x08 | ( exponent & 0x07 ) ); + break; + case 24: + *reg |= ( uint8_t )( 0x10 | ( exponent & 0x07 ) ); + break; + default: + // Something went terribely wrong + break; + } + + if( reg == &SX1276->RegRxBw ) + { + SX1276Write( REG_RXBW, *reg ); + FskSettings.RxBw = rxBwValue; + } + else + { + SX1276Write( REG_AFCBW, *reg ); + FskSettings.RxBwAfc = rxBwValue; + } +} + +uint32_t SX1276FskGetBw( uint8_t* reg ) +{ + uint32_t rxBwValue = 0; + uint8_t mantisse = 0; + switch( ( *reg & 0x18 ) >> 3 ) + { + case 0: + mantisse = 16; + break; + case 1: + mantisse = 20; + break; + case 2: + mantisse = 24; + break; + default: + break; + } + rxBwValue = SX1276FskComputeRxBw( mantisse, ( uint8_t )*reg & 0x07 ); + if( reg == &SX1276->RegRxBw ) + { + return FskSettings.RxBw = rxBwValue; + } + else + { + return FskSettings.RxBwAfc = rxBwValue; + } +} + +void SX1276FskSetPacketCrcOn( bool enable ) +{ + SX1276Read( REG_PACKETCONFIG1, &SX1276->RegPacketConfig1 ); + SX1276->RegPacketConfig1 = ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_MASK ) | ( enable << 4 ); + SX1276Write( REG_PACKETCONFIG1, SX1276->RegPacketConfig1 ); + FskSettings.CrcOn = enable; +} + +bool SX1276FskGetPacketCrcOn( void ) +{ + SX1276Read( REG_PACKETCONFIG1, &SX1276->RegPacketConfig1 ); + FskSettings.CrcOn = ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_ON ) >> 4; + return FskSettings.CrcOn; +} + +void SX1276FskSetAfcOn( bool enable ) +{ + SX1276Read( REG_RXCONFIG, &SX1276->RegRxConfig ); + SX1276->RegRxConfig = ( SX1276->RegRxConfig & RF_RXCONFIG_AFCAUTO_MASK ) | ( enable << 4 ); + SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig ); + FskSettings.AfcOn = enable; +} + +bool SX1276FskGetAfcOn( void ) +{ + SX1276Read( REG_RXCONFIG, &SX1276->RegRxConfig ); + FskSettings.AfcOn = ( SX1276->RegRxConfig & RF_RXCONFIG_AFCAUTO_ON ) >> 4; + return FskSettings.AfcOn; +} + +void SX1276FskSetPayloadLength( uint8_t value ) +{ + SX1276->RegPayloadLength = value; + SX1276Write( REG_PAYLOADLENGTH, SX1276->RegPayloadLength ); + FskSettings.PayloadLength = value; +} + +uint8_t SX1276FskGetPayloadLength( void ) +{ + SX1276Read( REG_PAYLOADLENGTH, &SX1276->RegPayloadLength ); + FskSettings.PayloadLength = SX1276->RegPayloadLength; + return FskSettings.PayloadLength; +} + +void SX1276FskSetPa20dBm( bool enale ) +{ + SX1276Read( REG_PADAC, &SX1276->RegPaDac ); + SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig ); + + if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) + { + if( enale == true ) + { + SX1276->RegPaDac = 0x87; + } + } + else + { + SX1276->RegPaDac = 0x84; + } + SX1276Write( REG_PADAC, SX1276->RegPaDac ); +} + +bool SX1276FskGetPa20dBm( void ) +{ + SX1276Read( REG_PADAC, &SX1276->RegPaDac ); + + return ( ( SX1276->RegPaDac & 0x07 ) == 0x07 ) ? true : false; +} + +void SX1276FskSetPAOutput( uint8_t outputPin ) +{ + SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig ); + SX1276->RegPaConfig = (SX1276->RegPaConfig & RF_PACONFIG_PASELECT_MASK ) | outputPin; + SX1276Write( REG_PACONFIG, SX1276->RegPaConfig ); +} + +uint8_t SX1276FskGetPAOutput( void ) +{ + SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig ); + return SX1276->RegPaConfig & ~RF_PACONFIG_PASELECT_MASK; +} + + +void SX1276FskSetPaRamp( uint8_t value ) +{ + SX1276Read( REG_PARAMP, &SX1276->RegPaRamp ); + SX1276->RegPaRamp = ( SX1276->RegPaRamp & RF_PARAMP_MASK ) | ( value & ~RF_PARAMP_MASK ); + SX1276Write( REG_PARAMP, SX1276->RegPaRamp ); +} + +uint8_t SX1276FskGetPaRamp( void ) +{ + SX1276Read( REG_PARAMP, &SX1276->RegPaRamp ); + return SX1276->RegPaRamp & ~RF_PARAMP_MASK; +} + +void SX1276FskSetRssiOffset( int8_t offset ) +{ + SX1276Read( REG_RSSICONFIG, &SX1276->RegRssiConfig ); + if( offset < 0 ) + { + offset = ( ~offset & 0x1F ); + offset += 1; + offset = -offset; + } + SX1276->RegRssiConfig |= ( uint8_t )( ( offset & 0x1F ) << 3 ); + SX1276Write( REG_RSSICONFIG, SX1276->RegRssiConfig ); +} + +int8_t SX1276FskGetRssiOffset( void ) +{ + SX1276Read( REG_RSSICONFIG, &SX1276->RegRssiConfig ); + int8_t offset = SX1276->RegRssiConfig >> 3; + if( ( offset & 0x10 ) == 0x10 ) + { + offset = ( ~offset & 0x1F ); + offset += 1; + offset = -offset; + } + return offset; +} + +int8_t SX1276FskGetRawTemp( void ) +{ + int8_t temp = 0; + uint8_t previousOpMode; + uint32_t startTick; + + // Enable Temperature reading + SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal ); + SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_TEMPMONITOR_MASK ) | RF_IMAGECAL_TEMPMONITOR_ON; + SX1276Write( REG_IMAGECAL, SX1276->RegImageCal ); + + // save current Op Mode + SX1276Read( REG_OPMODE, &SX1276->RegOpMode ); + previousOpMode = SX1276->RegOpMode; + + // put device in FSK RxSynth + SX1276->RegOpMode = RF_OPMODE_SYNTHESIZER_RX; + SX1276Write( REG_OPMODE, SX1276->RegOpMode ); + + // Wait 1ms + startTick = GET_TICK_COUNT( ); + while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) ); + + // Disable Temperature reading + SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal ); + SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_TEMPMONITOR_MASK ) | RF_IMAGECAL_TEMPMONITOR_OFF; + SX1276Write( REG_IMAGECAL, SX1276->RegImageCal ); + + // Read temperature + SX1276Read( REG_TEMP, &SX1276->RegTemp ); + + temp = SX1276->RegTemp & 0x7F; + + if( ( SX1276->RegTemp & 0x80 ) == 0x80 ) + { + temp *= -1; + } + + // Reload previous Op Mode + SX1276Write( REG_OPMODE, previousOpMode ); + + return temp; +} + +int8_t SX1276FskCalibreateTemp( int8_t actualTemp ) +{ + return actualTemp - SX1276FskGetRawTemp( ); +} + +int8_t SX1276FskGetTemp( int8_t compensationFactor ) +{ + return SX1276FskGetRawTemp( ) + compensationFactor; +} + +#endif // USE_SX1276_RADIO diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-FskMisc.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-FskMisc.h new file mode 100644 index 000000000..7ada359a0 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-FskMisc.h @@ -0,0 +1,241 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-FskMisc.h + * \brief SX1276 RF chip high level functions driver + * + * \remark Optional support functions. + * These functions are defined only to easy the change of the + * parameters. + * For a final firmware the radio parameters will be known so + * there is no need to support all possible parameters. + * Removing these functions will greatly reduce the final firmware + * size. + * + * \version 2.0.B2 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#ifndef __SX1276_FSK_MISC_H__ +#define __SX1276_FSK_MISC_H__ + +/*! + * \brief Writes the new RF frequency value + * + * \param [IN] freq New RF frequency value in [Hz] + */ +void SX1276FskSetRFFrequency( uint32_t freq ); + +/*! + * \brief Reads the current RF frequency value + * + * \retval freq Current RF frequency value in [Hz] + */ +uint32_t SX1276FskGetRFFrequency( void ); + +/*! + * \brief Calibrate RSSI and I/Q mismatch for HF + * + * \retval none + */ +void SX1276FskRxCalibrate( void ); + +/*! + * \brief Writes the new bitrate value + * + * \param [IN] bitrate New bitrate value in [bps] + */ +void SX1276FskSetBitrate( uint32_t bitrate ); + +/*! + * \brief Reads the current bitrate value + * + * \retval bitrate Current bitrate value in [bps] + */ +uint32_t SX1276FskGetBitrate( void ); + +/*! + * \brief Writes the new frequency deviation value + * + * \param [IN] fdev New frequency deviation value in [Hz] + */ +void SX1276FskSetFdev( uint32_t fdev ); + +/*! + * \brief Reads the current frequency deviation value + * + * \retval fdev Current frequency deviation value in [Hz] + */ +uint32_t SX1276FskGetFdev( void ); + +/*! + * \brief Writes the new RF output power value + * + * \param [IN] power New output power value in [dBm] + */ +void SX1276FskSetRFPower( int8_t power ); + +/*! + * \brief Reads the current RF output power value + * + * \retval power Current output power value in [dBm] + */ +int8_t SX1276FskGetRFPower( void ); + +/*! + * \brief Writes the DC offset canceller and Rx bandwidth values + * + * \remark For SX1276 there is no DCC setting. dccValue should be 0 + * ie: SX1276SetDccBw( &SX1276.RegRxBw, 0, 62500 ); + * + * \param [IN] reg Register pointer to either SX1231.RegRxBw or SX1231.RegAfcBw + * \param [IN] dccValue New DC offset canceller value in [Hz] ( SX1231 only ) + * \param [IN] rxBwValue New Rx bandwidth value in [Hz] + */ +void SX1276FskSetDccBw( uint8_t* reg, uint32_t dccValue, uint32_t rxBwValue ); + +/*! + * \brief Reads the current bandwidth setting + * + * \param [IN] reg Register pointer to either SX1231.RegRxBw or SX1231.RegAfcBw + * + * \retval bandwidth Bandwidth value + */ +uint32_t SX1276FskGetBw( uint8_t* reg ); + +/*! + * \brief Enables/Disables CRC + * + * \param [IN] enable CRC enable/disable + */ +void SX1276FskSetPacketCrcOn( bool enable ); + +/*! + * \brief Reads the current CRC Enable/Disbale value + * + * \retval enable Current CRC Enable/Disbale value + */ +bool SX1276FskGetPacketCrcOn( void ); + +/*! + * \brief Enables/Disables AFC + * + * \param [IN] enable AFC enable/disable + */ +void SX1276FskSetAfcOn( bool enable ); + +/*! + * \brief Reads the current AFC Enable/Disbale value + * + * \retval enable Current AFC Enable/Disbale value + */ +bool SX1276FskGetAfcOn( void ); + +/*! + * \brief Writes the new payload length value + * + * \param [IN] value New payload length value + */ +void SX1276FskSetPayloadLength( uint8_t value ); + +/*! + * \brief Reads the current payload length value + * + * \retval value Current payload length value + */ +uint8_t SX1276FskGetPayloadLength( void ); + +/*! + * \brief Enables/Disables the 20 dBm PA + * + * \param [IN] enable [true, false] + */ +void SX1276FskSetPa20dBm( bool enale ); + +/*! + * \brief Gets the current 20 dBm PA status + * + * \retval enable [true, false] + */ +bool SX1276FskGetPa20dBm( void ); + +/*! + * \brief Set the RF Output pin + * + * \param [IN] RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO + */ +void SX1276FskSetPAOutput( uint8_t outputPin ); + +/*! + * \brief Gets the used RF Ouptu pin + * + * \retval RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO + */ +uint8_t SX1276FskGetPAOutput( void ); + +/*! + * \brief Writes the new PA rise/fall time of ramp up/down value + * + * \param [IN] value New PaRamp value + */ +void SX1276FskSetPaRamp( uint8_t value ); + +/*! + * \brief Reads the current PA rise/fall time of ramp up/down value + * + * \retval value Current PaRamp value + */ +uint8_t SX1276FskGetPaRamp( void ); + +/*! + * \brief Applies an offset to the RSSI. Compensates board components + * + * \param [IN] offset Offset to be applied (+/-) + */ +void SX1276FskSetRssiOffset( int8_t offset ); + +/*! + * \brief Gets the current RSSI offset. + * + * \retval offset Current offset (+/-) + */ +int8_t SX1276FskGetRssiOffset( void ); + +/*! + * \brief Writes the new value for the preamble size + * + * \param [IN] size New value of pramble size + */ +void SX1276FskSetPreambleSize( uint16_t size ); + +/*! + * Reads the raw temperature + * \retval temperature New raw temperature reading in 2's complement format + */ +int8_t SX1276FskGetRawTemp( void ); + +/*! + * Computes the temperature compensation factor + * \param [IN] actualTemp Actual temperature measured by an external device + * \retval compensationFactor Computed compensation factor + */ +int8_t SX1276FskCalibreateTemp( int8_t actualTemp ); + +/*! + * Gets the actual compensated temperature + * \param [IN] compensationFactor Return value of the calibration function + * \retval New compensated temperature value + */ +int8_t SX1276FskGetTemp( int8_t compensationFactor ); + +#endif //__SX1276_FSK_MISC_H__ \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Hal.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Hal.h new file mode 100644 index 000000000..43cdcc471 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-Hal.h @@ -0,0 +1,162 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-Hal.h + * \brief SX1276 Hardware Abstraction Layer + * + * \version 2.0.B2 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#ifndef __SX1276_HAL_H__ +#define __SX1276_HAL_H__ + +//#include "ioe.h" +#include "platform.h" + +/*! + * DIO state read functions mapping + */ +#define DIO0 SX1276ReadDio0( ) +#define DIO1 SX1276ReadDio1( ) +#define DIO2 SX1276ReadDio2( ) +#define DIO3 SX1276ReadDio3( ) +#define DIO4 SX1276ReadDio4( ) +#define DIO5 SX1276ReadDio5( ) + +// RXTX pin control see errata note +#define RXTX( txEnable ) SX1276WriteRxTx( txEnable ); + +#define GET_TICK_COUNT( ) rt_tick_get()//( TickCounter ) +#define TICK_RATE_MS( ms ) ( ms ) + +typedef enum +{ + RADIO_RESET_OFF, + RADIO_RESET_ON, +}tRadioResetState; + +/*! + * \brief Initializes the radio interface I/Os + */ +void SX1276InitIo( void ); + +/*! + * \brief Set the radio reset pin state + * + * \param state New reset pin state + */ +void SX1276SetReset( rt_uint8_t state ); + +/*! + * \brief Writes the radio register at the specified address + * + * \param [IN]: addr Register address + * \param [IN]: data New register value + */ +void SX1276Write( rt_uint8_t addr, rt_uint8_t data ); + +/*! + * \brief Reads the radio register at the specified address + * + * \param [IN]: addr Register address + * \param [OUT]: data Register value + */ +void SX1276Read( rt_uint8_t addr, rt_uint8_t *data ); + +/*! + * \brief Writes multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [IN] buffer Buffer containing the new register's values + * \param [IN] size Number of registers to be written + */ +void SX1276WriteBuffer( rt_uint8_t addr, rt_uint8_t *buffer, rt_uint8_t size ); + +/*! + * \brief Reads multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [OUT] buffer Buffer where to copy the registers data + * \param [IN] size Number of registers to be read + */ +void SX1276ReadBuffer( rt_uint8_t addr, rt_uint8_t *buffer, rt_uint8_t size ); + +/*! + * \brief Writes the buffer contents to the radio FIFO + * + * \param [IN] buffer Buffer containing data to be put on the FIFO. + * \param [IN] size Number of bytes to be written to the FIFO + */ +void SX1276WriteFifo( rt_uint8_t *buffer, rt_uint8_t size ); + +/*! + * \brief Reads the contents of the radio FIFO + * + * \param [OUT] buffer Buffer where to copy the FIFO read data. + * \param [IN] size Number of bytes to be read from the FIFO + */ +void SX1276ReadFifo( rt_uint8_t *buffer, rt_uint8_t size ); + +/*! + * \brief Gets the SX1276 DIO0 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +inline rt_uint8_t SX1276ReadDio0( void ); + +/*! + * \brief Gets the SX1276 DIO1 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +inline rt_uint8_t SX1276ReadDio1( void ); + +/*! + * \brief Gets the SX1276 DIO2 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +inline rt_uint8_t SX1276ReadDio2( void ); + +/*! + * \brief Gets the SX1276 DIO3 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +inline rt_uint8_t SX1276ReadDio3( void ); + +/*! + * \brief Gets the SX1276 DIO4 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +inline rt_uint8_t SX1276ReadDio4( void ); + +/*! + * \brief Gets the SX1276 DIO5 hardware pin status + * + * \retval status Current hardware pin status [1, 0] + */ +inline rt_uint8_t SX1276ReadDio5( void ); + +/*! + * \brief Writes the external RxTx pin value + * + * \remark see errata note + * + * \param [IN] txEnable [1: Tx, 0: Rx] + */ +inline void SX1276WriteRxTx( rt_uint8_t txEnable ); + +#endif //__SX1276_HAL_H__ \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRa.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRa.c new file mode 100644 index 000000000..9ef4985c9 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRa.c @@ -0,0 +1,797 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Original Copyright (C) SEMTECH S.A. + * Modified Copyright (C) 2020 AIIT XUOS Lab + */ +/*! + * \file sx1276-LoRa.c + * \brief SX1276 RF chip driver mode LoRa + * + * \version 2.0.0 + * \date Nov 21 2012 + * \author Miguel Luis + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +/************************************************* +File name: sx1276-LoRa.c +Description: support aiit board configure and register function +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. replace original macro and basic date type with AIIT XUOS Lab's own defination +*************************************************/ + +#include + +#include "platform.h" + +#if defined( USE_SX1276_RADIO ) +#include "radio.h" +#include "sx1276-Hal.h" +#include "sx1276.h" +#include "sx1276-LoRaMisc.h" +#include "sx1276-LoRa.h" + +#define LoRa_FREQENCY 433000000 + +#define RSSI_OFFSET_LF -155.0 +#define RSSI_OFFSET_HF -150.0 + +#define NOISE_ABSOLUTE_ZERO -174.0 +#define NOISE_FIGURE_LF 4.0 +#define NOISE_FIGURE_HF 6.0 +typedef unsigned int uint32; +volatile uint32 TickCounter = 0; + +uint32 Tx_Time_Start,Tx_Time_End; +uint32 Rx_Time_Start,Rx_Time_End; +//Signal bandwidth, used to calculate RSSI +const double SignalBwLog[] = +{ + 3.8927900303521316335038277369285, // 7.8 kHz + 4.0177301567005500940384239336392, // 10.4 kHz + 4.193820026016112828717566631653, // 15.6 kHz + 4.31875866931372901183597627752391, // 20.8 kHz + 4.4948500216800940239313055263775, // 31.2 kHz + 4.6197891057238405255051280399961, // 41.6 kHz + 4.795880017344075219145044421102, // 62.5 kHz + 5.0969100130080564143587833158265, // 125 kHz + 5.397940008672037609572522210551, // 250 kHz + 5.6989700043360188047862611052755 // 500 kHz +}; + +//These values need testing +const double RssiOffsetLF[] = +{ + -155.0, + -155.0, + -155.0, + -155.0, + -155.0, + -155.0, + -155.0, + -155.0, + -155.0, + -155.0, +}; + +//These values need testing +const double RssiOffsetHF[] = +{ + -150.0, + -150.0, + -150.0, + -150.0, + -150.0, + -150.0, + -150.0, + -150.0, + -150.0, + -150.0, +}; + +/*! + * Frequency hopping frequencies table + */ +const int32_t HoppingFrequencies[] = +{ + 916500000, + 923500000, + 906500000, + 917500000, + 917500000, + 909000000, + 903000000, + 916000000, + 912500000, + 926000000, + 925000000, + 909500000, + 913000000, + 918500000, + 918500000, + 902500000, + 911500000, + 926500000, + 902500000, + 922000000, + 924000000, + 903500000, + 913000000, + 922000000, + 926000000, + 910000000, + 920000000, + 922500000, + 911000000, + 922000000, + 909500000, + 926000000, + 922000000, + 918000000, + 925500000, + 908000000, + 917500000, + 926500000, + 908500000, + 916000000, + 905500000, + 916000000, + 903000000, + 905000000, + 915000000, + 913000000, + 907000000, + 910000000, + 926500000, + 925500000, + 911000000, +}; + +// Default settings +tLoRaSettings LoRaSettings = +{ + LoRa_FREQENCY , // RFFrequency + 20, // Power + 9, // SignalBw [0: 125 kHz, 1: 250 kHz, 2: 500 kHz, 3: Reserved] + 12, // SpreadingFactor [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + 2, // ErrorCoding [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + true, // CrcOn [0: OFF, 1: ON] + false, // ImplicitHeaderOn [0: OFF, 1: ON] + 0, // RxSingleOn [0: Continuous, 1 Single] + 0, // FreqHopOn [0: OFF, 1: ON] + 4, // HopPeriod Hops every frequency hopping period symbols + 1000, // TxPacketTimeout + 1000, // RxPacketTimeout + 128, // PayloadLength (used for implicit header mode) +}; + +/*! + * SX1276 LoRa registers variable + */ +tSX1276LR* SX1276LR; + +/*! + * Local RF buffer for communication support + */ +static uint8_t RFBuffer[RF_BUFFER_SIZE]; +static uint8_t TFBuffer[RF_BUFFER_SIZE]; + +/*! + * RF state machine variable + */ +static uint8_t RFLRState = RFLR_STATE_IDLE; + +/*! + * Rx management support variables + */ +static uint16_t RxPacketSize = 0; +static int8_t RxPacketSnrEstimate; +static double RxPacketRssiValue; +static uint8_t RxGain = 1; +static uint32_t RxTimeoutTimer = 0; + +/*! + * PacketTimeout Stores the Rx window time value for packet reception + */ +static uint32_t PacketTimeout; + +/*! + * Tx management support variables + */ +static uint16_t TxPacketSize = 0; + + +void SX1276LoRaInit( void ) +{ + RFLRState = RFLR_STATE_IDLE; + + SX1276LoRaSetDefaults(); + + + SX1276ReadBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 ); + + + //SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP ); + + SX1276LR->RegLna = RFLR_LNA_GAIN_G1; + SX1276WriteBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 ); + + // set the RF settings + SX1276LoRaSetRFFrequency( LoRaSettings.RFFrequency ); + SX1276LoRaSetSpreadingFactor( LoRaSettings.SpreadingFactor ); + SX1276LoRaSetErrorCoding( LoRaSettings.ErrorCoding ); + SX1276LoRaSetPacketCrcOn( LoRaSettings.CrcOn ); + SX1276LoRaSetSignalBandwidth( LoRaSettings.SignalBw ); + SX1276LoRaSetImplicitHeaderOn( LoRaSettings.ImplicitHeaderOn ); + + SX1276LoRaSetSymbTimeout(0x3FF); + SX1276LoRaSetPayloadLength( LoRaSettings.PayloadLength ); + SX1276LoRaSetLowDatarateOptimize( true ); + + #if( ( MODULE_SX1276RF1IAS == 1 ) || ( MODULE_SX1276RF1KAS == 1 ) ) + if( LoRaSettings.RFFrequency > 860000000 ) + { + SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_RFO ); + SX1276LoRaSetPa20dBm( false ); + LoRaSettings.Power = 14; + SX1276LoRaSetRFPower( LoRaSettings.Power ); + } + else + { + //SX1276Write( REG_LR_OCP, 0x3f ); + SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_PABOOST ); + SX1276LoRaSetPa20dBm( true ); + LoRaSettings.Power = 20; + SX1276LoRaSetRFPower( LoRaSettings.Power ); + } + #elif( MODULE_SX1276RF1JAS == 1 ) + if( LoRaSettings.RFFrequency > 380000000 ) + { + SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_PABOOST ); + SX1276LoRaSetPa20dBm( true ); + LoRaSettings.Power = 20; + SX1276LoRaSetRFPower( LoRaSettings.Power ); + } + else + { + SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_RFO ); + SX1276LoRaSetPa20dBm( false ); + LoRaSettings.Power = 14; + SX1276LoRaSetRFPower( LoRaSettings.Power ); + } + #endif + SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY ); +} + + +void SX1276LoRaSetDefaults( void ) +{ + // REMARK: See SX1276 datasheet for modified default values. + + // Sets IF frequency selection manual + SX1276Read( REG_LR_VERSION, &SX1276LR->RegVersion ); +} + + + +void SX1276LoRaReset( void ) +{ + uint32_t startTick; + + SX1276SetReset( RADIO_RESET_ON ); + + // Wait 1ms + startTick = GET_TICK_COUNT( ); + while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) ); + + SX1276SetReset( RADIO_RESET_OFF ); + + // Wait 6ms + startTick = GET_TICK_COUNT( ); + while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 6 ) ); +} + +void SX1276LoRaSetOpMode( uint8_t opMode ) +{ + static uint8_t opModePrev = RFLR_OPMODE_STANDBY; + static bool antennaSwitchTxOnPrev = true; + bool antennaSwitchTxOn = false; + opModePrev = SX1276LR->RegOpMode & ~RFLR_OPMODE_MASK; + if( opMode != opModePrev ) + { + if( opMode == RFLR_OPMODE_TRANSMITTER ) + { + antennaSwitchTxOn = true; + } + else + { + antennaSwitchTxOn = false; + } + if( antennaSwitchTxOn != antennaSwitchTxOnPrev ) + { + antennaSwitchTxOnPrev = antennaSwitchTxOn; // Antenna switch control + RXTX( antennaSwitchTxOn ); + } + SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_MASK ) | opMode; + + SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode ); + } +} + + +uint8_t SX1276LoRaGetOpMode( void ) +{ + SX1276Read( REG_LR_OPMODE, &SX1276LR->RegOpMode ); + + return SX1276LR->RegOpMode & ~RFLR_OPMODE_MASK; +} + + +uint8_t SX1276LoRaReadRxGain( void ) +{ + + SX1276Read( REG_LR_LNA, &SX1276LR->RegLna ); + return( SX1276LR->RegLna >> 5 ) & 0x07; +} + + +double SX1276LoRaReadRssi( void ) +{ + // Reads the RSSI value + SX1276Read( REG_LR_RSSIVALUE, &SX1276LR->RegRssiValue ); + + if( LoRaSettings.RFFrequency < 860000000 ) + { + return RssiOffsetLF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegRssiValue; + } + else + { + return RssiOffsetHF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegRssiValue; + } +} + + +uint8_t SX1276LoRaGetPacketRxGain( void ) +{ + return RxGain; +} + + +int8_t SX1276LoRaGetPacketSnr( void ) +{ + return RxPacketSnrEstimate; +} + + +double SX1276LoRaGetPacketRssi( void ) +{ + return RxPacketRssiValue; +} + + +void SX1276LoRaStartRx( void ) +{ + SX1276LoRaSetRFState( RFLR_STATE_RX_INIT ); +} + + +void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size ) +{ + *size = RxPacketSize; + RxPacketSize = 0; + memcpy( (void*)buffer, (void*)RFBuffer, (size_t)*size ); +} + + +void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size ) +{ + if( LoRaSettings.FreqHopOn == false ) + { + TxPacketSize = size; + } + else + { + TxPacketSize = 255; + } + memcpy( ( void * )TFBuffer, buffer, ( size_t )TxPacketSize ); + + RFLRState = RFLR_STATE_TX_INIT; +} + + +uint8_t SX1276LoRaGetRFState( void ) +{ + return RFLRState; +} + + +void SX1276LoRaSetRFState( uint8_t state ) +{ + RFLRState = state; +} + +/*! + * \brief Process the LoRa modem Rx and Tx state machines depending on the + * SX1276 operating mode. + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint32_t SX1276LoRaProcess( void ) +{ + uint32_t result = RF_BUSY; + uint8_t regValue=0; + switch( RFLRState ) + { + case RFLR_STATE_IDLE: + break; + case RFLR_STATE_RX_INIT: + SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY); + + SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | + + RFLR_IRQFLAGS_PAYLOADCRCERROR | + RFLR_IRQFLAGS_VALIDHEADER | + RFLR_IRQFLAGS_TXDONE | + RFLR_IRQFLAGS_CADDONE | + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + RFLR_IRQFLAGS_CADDETECTED; + SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask ); + + if(LoRaSettings.FreqHopOn == true ) + { + SX1276LR->RegHopPeriod = LoRaSettings.HopPeriod; + + SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel ); + SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] ); + } + else + { + SX1276LR->RegHopPeriod = 255; + } + + SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod ); + + + // RxDone + SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00; + // CadDetected + SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_10 | RFLR_DIOMAPPING2_DIO5_00; + + SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 ); + + if( LoRaSettings.RxSingleOn == true ) // Rx single mode + { + SX1276LoRaSetOpMode( RFLR_OPMODE_RECEIVER_SINGLE ); + } + else // Rx continuous mode + { + SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxBaseAddr; + + SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr ); + SX1276LoRaSetOpMode( RFLR_OPMODE_RECEIVER ); + + } + memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE ); + Rx_Time_Start=TickCounter; + PacketTimeout = LoRaSettings.RxPacketTimeout; + RxTimeoutTimer = GET_TICK_COUNT( ); + RFLRState = RFLR_STATE_RX_RUNNING; + break; + case RFLR_STATE_RX_RUNNING: + SX1276Read(0x12,®Value); + //if( DIO0 == 1 ) // RxDone + if(regValue & (1<<6)) + { + + RxTimeoutTimer = GET_TICK_COUNT( ); + if( LoRaSettings.FreqHopOn == true ) + { + SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel ); + SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] ); + } + // Clear Irq + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE ); + RFLRState = RFLR_STATE_RX_DONE; + } + //if( DIO2 == 1 ) // FHSS Changed Channel + if(regValue & (1<<1)) + { + RxTimeoutTimer = GET_TICK_COUNT( ); + if( LoRaSettings.FreqHopOn == true ) + { + SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel ); + SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] ); + } + // Clear Irq + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); + //RxGain = SX1276LoRaReadRxGain( ); + } + if( LoRaSettings.RxSingleOn == true ) // Rx single mode + { + if( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) + { + RFLRState = RFLR_STATE_RX_TIMEOUT; + } + } + break; + case RFLR_STATE_RX_DONE: + + + SX1276Read( REG_LR_IRQFLAGS, &SX1276LR->RegIrqFlags ); + if( ( SX1276LR->RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR ) + { + // Clear Irq + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR ); + if( LoRaSettings.RxSingleOn == true ) // Rx single mode + { + RFLRState = RFLR_STATE_RX_INIT; + } + else + { + RFLRState = RFLR_STATE_RX_RUNNING; + } + break; + } + +/* { + uint8_t rxSnrEstimate; + + SX1276Read( REG_LR_PKTSNRVALUE, &rxSnrEstimate ); + if( rxSnrEstimate & 0x80 ) + { + + RxPacketSnrEstimate = ( ( ~rxSnrEstimate + 1 ) & 0xFF ) >> 2; + RxPacketSnrEstimate = -RxPacketSnrEstimate; + } + else + { + RxPacketSnrEstimate = ( rxSnrEstimate & 0xFF ) >> 2; + } + } + if( LoRaSettings.RFFrequency < 860000000 ) + { + if( RxPacketSnrEstimate < 0 ) + { + + RxPacketRssiValue = NOISE_ABSOLUTE_ZERO + 10.0 * SignalBwLog[LoRaSettings.SignalBw] + NOISE_FIGURE_LF + ( double )RxPacketSnrEstimate; + } + else + { + SX1276Read( REG_LR_PKTRSSIVALUE, &SX1276LR->RegPktRssiValue ); + RxPacketRssiValue = RssiOffsetLF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegPktRssiValue; + } + } + else + { + if( RxPacketSnrEstimate < 0 ) + { + RxPacketRssiValue = NOISE_ABSOLUTE_ZERO + 10.0 * SignalBwLog[LoRaSettings.SignalBw] + NOISE_FIGURE_HF + ( double )RxPacketSnrEstimate; + } + else + { + SX1276Read( REG_LR_PKTRSSIVALUE, &SX1276LR->RegPktRssiValue ); + RxPacketRssiValue = RssiOffsetHF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegPktRssiValue; + } + }*/ + if( LoRaSettings.RxSingleOn == true ) // Rx single mode + { + SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxBaseAddr; + SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr ); + if( LoRaSettings.ImplicitHeaderOn == true ) + { + RxPacketSize = SX1276LR->RegPayloadLength; + SX1276ReadFifo( RFBuffer, SX1276LR->RegPayloadLength ); + } + else + { + + SX1276Read( REG_LR_NBRXBYTES, &SX1276LR->RegNbRxBytes ); + RxPacketSize = SX1276LR->RegNbRxBytes; + SX1276ReadFifo( RFBuffer, SX1276LR->RegNbRxBytes ); + } + } + else // Rx continuous mode + { + + SX1276Read( REG_LR_FIFORXCURRENTADDR, &SX1276LR->RegFifoRxCurrentAddr ); + if( LoRaSettings.ImplicitHeaderOn == true ) + { + RxPacketSize = SX1276LR->RegPayloadLength; + SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxCurrentAddr; + SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr ); + SX1276ReadFifo( RFBuffer, SX1276LR->RegPayloadLength ); + } + else + { + SX1276Read( REG_LR_NBRXBYTES, &SX1276LR->RegNbRxBytes ); + RxPacketSize = SX1276LR->RegNbRxBytes; + SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxCurrentAddr; + SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr ); + SX1276ReadFifo( RFBuffer, SX1276LR->RegNbRxBytes ); + } + } + if( LoRaSettings.RxSingleOn == true ) // Rx single mode + { + RFLRState = RFLR_STATE_RX_INIT; + } + else // Rx continuous mode + { + RFLRState = RFLR_STATE_RX_RUNNING; + } + Rx_Time_End=TickCounter; + result = RF_RX_DONE; + break; + case RFLR_STATE_RX_TIMEOUT: + RFLRState = RFLR_STATE_RX_INIT; + result = RF_RX_TIMEOUT; + break; + case RFLR_STATE_TX_INIT: + Tx_Time_Start=TickCounter; + SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY ); + if( LoRaSettings.FreqHopOn == true ) + { + SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | + RFLR_IRQFLAGS_RXDONE | + RFLR_IRQFLAGS_PAYLOADCRCERROR | + RFLR_IRQFLAGS_VALIDHEADER | + //RFLR_IRQFLAGS_TXDONE | + RFLR_IRQFLAGS_CADDONE | + //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + RFLR_IRQFLAGS_CADDETECTED; + SX1276LR->RegHopPeriod = LoRaSettings.HopPeriod; + SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel ); + SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] ); + } + else + { + + SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | + RFLR_IRQFLAGS_RXDONE | + RFLR_IRQFLAGS_PAYLOADCRCERROR | + RFLR_IRQFLAGS_VALIDHEADER | + //RFLR_IRQFLAGS_TXDONE | + RFLR_IRQFLAGS_CADDONE | + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | + RFLR_IRQFLAGS_CADDETECTED; + SX1276LR->RegHopPeriod = 0; + } + SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod ); + SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask ); + // Initializes the payload size + SX1276LR->RegPayloadLength = TxPacketSize; + SX1276Write( REG_LR_PAYLOADLENGTH, SX1276LR->RegPayloadLength ); + + SX1276LR->RegFifoTxBaseAddr = 0x00; // Full buffer used for Tx + SX1276Write( REG_LR_FIFOTXBASEADDR, SX1276LR->RegFifoTxBaseAddr ); + + SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoTxBaseAddr; + SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr ); + // Write payload buffer to LORA modem + SX1276WriteFifo( TFBuffer, SX1276LR->RegPayloadLength ); + // TxDone RxTimeout FhssChangeChannel ValidHeader + SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01; + // PllLock Mode Ready + SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_01 | RFLR_DIOMAPPING2_DIO5_00; + + SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 ); + + SX1276LoRaSetOpMode( RFLR_OPMODE_TRANSMITTER ); + + RFLRState = RFLR_STATE_TX_RUNNING; + break; + case RFLR_STATE_TX_RUNNING: + if( DIO0 == 1 ) // TxDone + { + // Clear Irq + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE ); + RFLRState = RFLR_STATE_TX_DONE; + } + if( DIO2 == 1 ) // FHSS Changed Channel + { + if( LoRaSettings.FreqHopOn == true ) + { + SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel ); + SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] ); + } + // Clear Irq + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); + } + break; + case RFLR_STATE_TX_DONE: + Tx_Time_End=TickCounter; + SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY ); + RFLRState = RFLR_STATE_IDLE; + result = RF_TX_DONE; + break; + case RFLR_STATE_CAD_INIT: + // optimize the power consumption by switching off the transmitter as soon as the packet has been sent + SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY ); + SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT | + RFLR_IRQFLAGS_RXDONE | + RFLR_IRQFLAGS_PAYLOADCRCERROR | + RFLR_IRQFLAGS_VALIDHEADER | + RFLR_IRQFLAGS_TXDONE | + //RFLR_IRQFLAGS_CADDONE | + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL; + //RFLR_IRQFLAGS_CADDETECTED; + SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask ); + + // RxDone RxTimeout FhssChangeChannel CadDone + SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00; + // CAD Detected ModeReady + SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 ); + + + SX1276LoRaSetOpMode( RFLR_OPMODE_CAD ); + RFLRState = RFLR_STATE_CAD_RUNNING; + + break; + case RFLR_STATE_CAD_RUNNING: + SX1276Read(0x12,®Value); + int cad_done = regValue & (1<<2); + int cad_detected = regValue & (1<<0); + + if( cad_done ) //CAD Done interrupt + { + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); + if( cad_detected ) // CAD Detected interrupt + { + SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED ); + //CAD detected, we have a LoRa preamble + RFLRState = RFLR_STATE_RX_INIT; + result = RF_CHANNEL_ACTIVITY_DETECTED; + } + else + { + // The device goes in Standby Mode automatically + RFLRState = RFLR_STATE_IDLE; + result = RF_CHANNEL_EMPTY; + } + } + break; + default: + break; + } + return result; +} + +uint32_t SX1276LoraChannelEmpty( void ) +{ + uint32_t result = 0; + RFLRState = RFLR_STATE_CAD_INIT; + SX1276LoRaProcess(); + while(RFLRState == RFLR_STATE_CAD_RUNNING) + { + //KPrintf("\nLora--SX1276LoRaProcess()"); + result = SX1276LoRaProcess(); + } + + if(result == RF_CHANNEL_EMPTY) + { + KPrintf("\nLora--信道可用（RF_CHANNEL_EMPTY）\n"); + return 0; + } + else if(result == RF_CHANNEL_ACTIVITY_DETECTED) + { + KPrintf("\nLora--信道正被占用（RF_CHANNEL_ACTIVITY_DETECTED）\n"); + return 1; + } + else + { + return 2; + } +} + +#endif // USE_SX1276_RADIO \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRa.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRa.h new file mode 100644 index 000000000..eea3f332e --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRa.h @@ -0,0 +1,922 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-LoRa.h + * \brief SX1276 RF chip driver mode LoRa + * + * \version 2.0.B2 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#ifndef __SX1276_LORA_H__ +#define __SX1276_LORA_H__ + +/*! + * SX1276 LoRa General parameters definition + */ +typedef struct sLoRaSettings +{ + uint32_t RFFrequency; + int8_t Power; + uint8_t SignalBw; // LORA [0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz, + // 5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved] + uint8_t SpreadingFactor; // LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096 chips] + uint8_t ErrorCoding; // LORA [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + bool CrcOn; // [0: OFF, 1: ON] + bool ImplicitHeaderOn; // [0: OFF, 1: ON] + bool RxSingleOn; // [0: Continuous, 1 Single] + bool FreqHopOn; // [0: OFF, 1: ON] + uint8_t HopPeriod; // Hops every frequency hopping period symbols + uint32_t TxPacketTimeout; + uint32_t RxPacketTimeout; + uint8_t PayloadLength; +}tLoRaSettings; + +/*! + * RF packet definition + */ +#define RF_BUFFER_SIZE_MAX 256 +#define RF_BUFFER_SIZE 256 + +/*! + * RF state machine + */ +//LoRa +typedef enum +{ + RFLR_STATE_IDLE, + RFLR_STATE_RX_INIT, + RFLR_STATE_RX_RUNNING, + RFLR_STATE_RX_DONE, + RFLR_STATE_RX_TIMEOUT, + RFLR_STATE_TX_INIT, + RFLR_STATE_TX_RUNNING, + RFLR_STATE_TX_DONE, + RFLR_STATE_TX_TIMEOUT, + RFLR_STATE_CAD_INIT, + RFLR_STATE_CAD_RUNNING, +}tRFLRStates; + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +/*! + * SX1276 Internal registers Address + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_BANDSETTING 0x04 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_NBRXBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +#define REG_LR_FEIMSB 0x28 +#define REG_LR_FEIMIB 0x29 +#define REG_LR_FEILSB 0x2A +#define REG_LR_LORADETECTOPTIMIZE 0x31 +#define REG_LR_INVERTIQ 0x33 +#define REG_LR_DETECTIONTHRESHOLD 0x37 +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 + + +/*! + * SX1276 LoRa bit control definition + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegBandSetting + */ +#define RFLR_BANDSETTING_MASK 0x3F +#define RFLR_BANDSETTING_AUTO 0x00 // Default +#define RFLR_BANDSETTING_DIV_BY_1 0x40 +#define RFLR_BANDSETTING_DIV_BY_2 0x80 +#define RFLR_BANDSETTING_DIV_BY_6 0xC0 + +/*! + * RegFrf (MHz) + */ + +#define RFLR_FRFMSB_434_MHZ 0x6C // Default +#define RFLR_FRFMID_434_MHZ 0x80 // Default +#define RFLR_FRFLSB_434_MHZ 0x00 // Default + +#define RFLR_FRFMSB_863_MHZ 0xD7 +#define RFLR_FRFMID_863_MHZ 0xC0 +#define RFLR_FRFLSB_863_MHZ 0x00 +#define RFLR_FRFMSB_864_MHZ 0xD8 +#define RFLR_FRFMID_864_MHZ 0x00 +#define RFLR_FRFLSB_864_MHZ 0x00 +#define RFLR_FRFMSB_865_MHZ 0xD8 +#define RFLR_FRFMID_865_MHZ 0x40 +#define RFLR_FRFLSB_865_MHZ 0x00 +#define RFLR_FRFMSB_866_MHZ 0xD8 +#define RFLR_FRFMID_866_MHZ 0x80 +#define RFLR_FRFLSB_866_MHZ 0x00 +#define RFLR_FRFMSB_867_MHZ 0xD8 +#define RFLR_FRFMID_867_MHZ 0xC0 +#define RFLR_FRFLSB_867_MHZ 0x00 +#define RFLR_FRFMSB_868_MHZ 0xD9 +#define RFLR_FRFMID_868_MHZ 0x00 +#define RFLR_FRFLSB_868_MHZ 0x00 +#define RFLR_FRFMSB_869_MHZ 0xD9 +#define RFLR_FRFMID_869_MHZ 0x40 +#define RFLR_FRFLSB_869_MHZ 0x00 +#define RFLR_FRFMSB_870_MHZ 0xD9 +#define RFLR_FRFMID_870_MHZ 0x80 +#define RFLR_FRFLSB_870_MHZ 0x00 + +#define RFLR_FRFMSB_902_MHZ 0xE1 +#define RFLR_FRFMID_902_MHZ 0x80 +#define RFLR_FRFLSB_902_MHZ 0x00 +#define RFLR_FRFMSB_903_MHZ 0xE1 +#define RFLR_FRFMID_903_MHZ 0xC0 +#define RFLR_FRFLSB_903_MHZ 0x00 +#define RFLR_FRFMSB_904_MHZ 0xE2 +#define RFLR_FRFMID_904_MHZ 0x00 +#define RFLR_FRFLSB_904_MHZ 0x00 +#define RFLR_FRFMSB_905_MHZ 0xE2 +#define RFLR_FRFMID_905_MHZ 0x40 +#define RFLR_FRFLSB_905_MHZ 0x00 +#define RFLR_FRFMSB_906_MHZ 0xE2 +#define RFLR_FRFMID_906_MHZ 0x80 +#define RFLR_FRFLSB_906_MHZ 0x00 +#define RFLR_FRFMSB_907_MHZ 0xE2 +#define RFLR_FRFMID_907_MHZ 0xC0 +#define RFLR_FRFLSB_907_MHZ 0x00 +#define RFLR_FRFMSB_908_MHZ 0xE3 +#define RFLR_FRFMID_908_MHZ 0x00 +#define RFLR_FRFLSB_908_MHZ 0x00 +#define RFLR_FRFMSB_909_MHZ 0xE3 +#define RFLR_FRFMID_909_MHZ 0x40 +#define RFLR_FRFLSB_909_MHZ 0x00 +#define RFLR_FRFMSB_910_MHZ 0xE3 +#define RFLR_FRFMID_910_MHZ 0x80 +#define RFLR_FRFLSB_910_MHZ 0x00 +#define RFLR_FRFMSB_911_MHZ 0xE3 +#define RFLR_FRFMID_911_MHZ 0xC0 +#define RFLR_FRFLSB_911_MHZ 0x00 +#define RFLR_FRFMSB_912_MHZ 0xE4 +#define RFLR_FRFMID_912_MHZ 0x00 +#define RFLR_FRFLSB_912_MHZ 0x00 +#define RFLR_FRFMSB_913_MHZ 0xE4 +#define RFLR_FRFMID_913_MHZ 0x40 +#define RFLR_FRFLSB_913_MHZ 0x00 +#define RFLR_FRFMSB_914_MHZ 0xE4 +#define RFLR_FRFMID_914_MHZ 0x80 +#define RFLR_FRFLSB_914_MHZ 0x00 +#define RFLR_FRFMSB_915_MHZ 0xE4 // Default +#define RFLR_FRFMID_915_MHZ 0xC0 // Default +#define RFLR_FRFLSB_915_MHZ 0x00 // Default +#define RFLR_FRFMSB_916_MHZ 0xE5 +#define RFLR_FRFMID_916_MHZ 0x00 +#define RFLR_FRFLSB_916_MHZ 0x00 +#define RFLR_FRFMSB_917_MHZ 0xE5 +#define RFLR_FRFMID_917_MHZ 0x40 +#define RFLR_FRFLSB_917_MHZ 0x00 +#define RFLR_FRFMSB_918_MHZ 0xE5 +#define RFLR_FRFMID_918_MHZ 0x80 +#define RFLR_FRFLSB_918_MHZ 0x00 +#define RFLR_FRFMSB_919_MHZ 0xE5 +#define RFLR_FRFMID_919_MHZ 0xC0 +#define RFLR_FRFLSB_919_MHZ 0x00 +#define RFLR_FRFMSB_920_MHZ 0xE6 +#define RFLR_FRFMID_920_MHZ 0x00 +#define RFLR_FRFLSB_920_MHZ 0x00 +#define RFLR_FRFMSB_921_MHZ 0xE6 +#define RFLR_FRFMID_921_MHZ 0x40 +#define RFLR_FRFLSB_921_MHZ 0x00 +#define RFLR_FRFMSB_922_MHZ 0xE6 +#define RFLR_FRFMID_922_MHZ 0x80 +#define RFLR_FRFLSB_922_MHZ 0x00 +#define RFLR_FRFMSB_923_MHZ 0xE6 +#define RFLR_FRFMID_923_MHZ 0xC0 +#define RFLR_FRFLSB_923_MHZ 0x00 +#define RFLR_FRFMSB_924_MHZ 0xE7 +#define RFLR_FRFMID_924_MHZ 0x00 +#define RFLR_FRFLSB_924_MHZ 0x00 +#define RFLR_FRFMSB_925_MHZ 0xE7 +#define RFLR_FRFMID_925_MHZ 0x40 +#define RFLR_FRFLSB_925_MHZ 0x00 +#define RFLR_FRFMSB_926_MHZ 0xE7 +#define RFLR_FRFMID_926_MHZ 0x80 +#define RFLR_FRFLSB_926_MHZ 0x00 +#define RFLR_FRFMSB_927_MHZ 0xE7 +#define RFLR_FRFMID_927_MHZ 0xC0 +#define RFLR_FRFLSB_927_MHZ 0x00 +#define RFLR_FRFMSB_928_MHZ 0xE8 +#define RFLR_FRFMID_928_MHZ 0x00 +#define RFLR_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 + +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default +#define RFLR_LNA_BOOST_LF_GAIN 0x08 +#define RFLR_LNA_BOOST_LF_IP3 0x10 +#define RFLR_LNA_BOOST_LF_BOOST 0x18 + +#define RFLR_LNA_RXBANDFORCE_MASK 0xFB +#define RFLR_LNA_RXBANDFORCE_BAND_SEL 0x04 +#define RFLR_LNA_RXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + + + +/*! + * RegFifoRxNbBytes (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueMsb (Read Only) // + */ + + + /*! + * RegRxHeaderCntValueLsb (Read Only) // + */ + + +/*! + * RegRxPacketCntValueMsb (Read Only) // + */ + + + /*! + * RegRxPacketCntValueLsb (Read Only) // + */ + + + /*! + * RegModemStat (Read Only) // + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) // + */ + + + /*! + * RegPktRssiValue (Read Only) // + */ + + +/*! + * RegRssiValue (Read Only) // + */ + +/*! + * RegHopChannel (Read Only) // + */ +#define RFLR_HOP_CHANNEL_PAYLOAD_CRC_ON_MASK 0xBF +#define RFLR_HOP_CHANNEL_PAYLOAD_CRC_ON 0x40 +#define RFLR_HOP_CHANNEL_PAYLOAD_CRC_OFF 0x00 + + /*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F + +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 + +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 + +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + + /*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + + +/*! + * RegHopChannel (Read Only) + */ +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default + +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK 0xBF +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON 0x40 +#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF 0x00 // Default + +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFormerTemp + */ + +typedef struct sSX1276LR +{ + uint8_t RegFifo; // 0x00 + // Common settings + uint8_t RegOpMode; // 0x01 + uint8_t RegRes02; // 0x02 + uint8_t RegRes03; // 0x03 + uint8_t RegBandSetting; // 0x04 + uint8_t RegRes05; // 0x05 + uint8_t RegFrfMsb; // 0x06 + uint8_t RegFrfMid; // 0x07 + uint8_t RegFrfLsb; // 0x08 + // Tx settings + uint8_t RegPaConfig; // 0x09 + uint8_t RegPaRamp; // 0x0A + uint8_t RegOcp; // 0x0B + // Rx settings + uint8_t RegLna; // 0x0C + // LoRa registers + uint8_t RegFifoAddrPtr; // 0x0D + uint8_t RegFifoTxBaseAddr; // 0x0E + uint8_t RegFifoRxBaseAddr; // 0x0F + uint8_t RegFifoRxCurrentAddr; // 0x10 + uint8_t RegIrqFlagsMask; // 0x11 + uint8_t RegIrqFlags; // 0x12 + uint8_t RegNbRxBytes; // 0x13 + uint8_t RegRxHeaderCntValueMsb; // 0x14 + uint8_t RegRxHeaderCntValueLsb; // 0x15 + uint8_t RegRxPacketCntValueMsb; // 0x16 + uint8_t RegRxPacketCntValueLsb; // 0x17 + uint8_t RegModemStat; // 0x18 + uint8_t RegPktSnrValue; // 0x19 + uint8_t RegPktRssiValue; // 0x1A + uint8_t RegRssiValue; // 0x1B + uint8_t RegHopChannel; // 0x1C + uint8_t RegModemConfig1; // 0x1D + uint8_t RegModemConfig2; // 0x1E + uint8_t RegSymbTimeoutLsb; // 0x1F + uint8_t RegPreambleMsb; // 0x20 + uint8_t RegPreambleLsb; // 0x21 + uint8_t RegPayloadLength; // 0x22 + uint8_t RegMaxPayloadLength; // 0x23 + uint8_t RegHopPeriod; // 0x24 + uint8_t RegFifoRxByteAddr; // 0x25 + uint8_t RegModemConfig3; // 0x26 + uint8_t RegTestReserved27; // 0x27 + uint8_t RegFeiMsb; // 0x28 + uint8_t RegFeiMib; // 0x29 + uint8_t RegFeiLsb; // 0x2A + uint8_t RegTestReserved2B[0x30 - 0x2B]; // 0x2B-0x30 + uint8_t RegDetectOptimize; // 0x31 + uint8_t RegTestReserved32; // 0x32 + uint8_t RegInvertIQ; // 0x33 + uint8_t RegTestReserved34[0x36 - 0x34]; // 0x34-0x36 + uint8_t RegDetectionThreshold; // 0x37 + uint8_t RegTestReserved38[0x3F - 0x38]; // 0x38-0x3F + // I/O settings + uint8_t RegDioMapping1; // 0x40 + uint8_t RegDioMapping2; // 0x41 + // Version + uint8_t RegVersion; // 0x42 + // Test + uint8_t RegTestReserved43; // 0x43 + // Additional settings + uint8_t RegPllHop; // 0x44 + // Test + uint8_t RegTestReserved45[0x4A - 0x45]; // 0x45-0x4A + // Additional settings + uint8_t RegTcxo; // 0x4B + // Test + uint8_t RegTestReserved4C; // 0x4C + // Additional settings + uint8_t RegPaDac; // 0x4D + // Test + uint8_t RegTestReserved4E[0x5A - 0x4E]; // 0x4E-0x5A + // Additional settings + uint8_t RegFormerTemp; // 0x5B + // Test + uint8_t RegTestReserved5C; // 0x5C + // Additional settings + uint8_t RegBitrateFrac; // 0x5D + // Additional settings + uint8_t RegTestReserved5E[0x60 - 0x5E]; // 0x5E-0x60 + // Additional settings + uint8_t RegAgcRef; // 0x60 + uint8_t RegAgcThresh1; // 0x61 + uint8_t RegAgcThresh2; // 0x62 + uint8_t RegAgcThresh3; // 0x63 + // Test + uint8_t RegTestReserved64[0x70 - 0x64]; // 0x64-0x70 +}tSX1276LR; + +extern tSX1276LR* SX1276LR; + +/*! + * \brief Initializes the SX1276 + */ +void SX1276LoRaInit( void ); + +/*! + * \brief Sets the SX1276 to datasheet default values + */ +void SX1276LoRaSetDefaults( void ); + +/*! + * \brief Enables/Disables the LoRa modem + * + * \param [IN]: enable [true, false] + */ +void SX1276LoRaSetLoRaOn( bool enable ); + +/*! + * \brief Sets the SX1276 operating mode + * + * \param [IN] opMode New operating mode + */ +void SX1276LoRaSetOpMode( uint8_t opMode ); + +/*! + * \brief Gets the SX1276 operating mode + * + * \retval opMode Current operating mode + */ +uint8_t SX1276LoRaGetOpMode( void ); + +/*! + * \brief Reads the current Rx gain setting + * + * \retval rxGain Current gain setting + */ +uint8_t SX1276LoRaReadRxGain( void ); + +/*! + * \brief Trigs and reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276LoRaReadRssi( void ); + +/*! + * \brief Gets the Rx gain value measured while receiving the packet + * + * \retval rxGainValue Current Rx gain value + */ +uint8_t SX1276LoRaGetPacketRxGain( void ); + +/*! + * \brief Gets the SNR value measured while receiving the packet + * + * \retval snrValue Current SNR value in [dB] + */ +int8_t SX1276LoRaGetPacketSnr( void ); + +/*! + * \brief Gets the RSSI value measured while receiving the packet + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276LoRaGetPacketRssi( void ); + +/*! + * \brief Sets the radio in Rx mode. Waiting for a packet + */ +void SX1276LoRaStartRx( void ); + +/*! + * \brief Gets a copy of the current received buffer + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size ); + +/*! + * \brief Sets a copy of the buffer to be transmitted + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size ); + +/*! + * \brief Gets the current RFState + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint8_t SX1276LoRaGetRFState( void ); + +/*! + * \brief Sets the new state of the RF state machine + * + * \param [IN]: state New RF state machine state + */ +void SX1276LoRaSetRFState( uint8_t state ); + +/*! + * \brief Process the LoRa modem Rx and Tx state machines depending on the + * SX1276 operating mode. + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint32_t SX1276LoRaProcess( void ); + +#endif //__SX1276_LORA_H__ \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRaMisc.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRaMisc.c new file mode 100644 index 000000000..96b1e28d0 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRaMisc.c @@ -0,0 +1,411 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-LoRaMisc.c + * \brief SX1276 RF chip high level functions driver + * + * \remark Optional support functions. + * These functions are defined only to easy the change of the + * parameters. + * For a final firmware the radio parameters will be known so + * there is no need to support all possible parameters. + * Removing these functions will greatly reduce the final firmware + * size. + * + * \version 2.0.0 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#include "platform.h" + +#if defined( USE_SX1276_RADIO ) + +#include "sx1276-Hal.h" +#include "sx1276.h" + +#include "sx1276-LoRa.h" +#include "sx1276-LoRaMisc.h" + +/*! + * SX1276 definitions + */ +#define XTAL_FREQ 32000000 +#define FREQ_STEP 61.03515625 + +extern tLoRaSettings LoRaSettings; + +void SX1276LoRaSetRFFrequency( uint32_t freq ) +{ + LoRaSettings.RFFrequency = freq; + + freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP ); + SX1276LR->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF ); + SX1276LR->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF ); + SX1276LR->RegFrfLsb = ( uint8_t )( freq & 0xFF ); + SX1276WriteBuffer( REG_LR_FRFMSB, &SX1276LR->RegFrfMsb, 3 ); +} + +uint32_t SX1276LoRaGetRFFrequency( void ) +{ + SX1276ReadBuffer( REG_LR_FRFMSB, &SX1276LR->RegFrfMsb, 3 ); + LoRaSettings.RFFrequency = ( ( uint32_t )SX1276LR->RegFrfMsb << 16 ) | ( ( uint32_t )SX1276LR->RegFrfMid << 8 ) | ( ( uint32_t )SX1276LR->RegFrfLsb ); + LoRaSettings.RFFrequency = ( uint32_t )( ( double )LoRaSettings.RFFrequency * ( double )FREQ_STEP ); + + return LoRaSettings.RFFrequency; +} + +void SX1276LoRaSetRFPower( int8_t power ) +{ + SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig ); + SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac ); + + if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) + { + if( ( SX1276LR->RegPaDac & 0x87 ) == 0x87 ) + { + if( power < 5 ) + { + power = 5; + } + if( power > 20 ) + { + power = 20; + } + SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F ); + } + else + { + if( power < 2 ) + { + power = 2; + } + if( power > 17 ) + { + power = 17; + } + SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F ); + } + } + else + { + if( power < -1 ) + { + power = -1; + } + if( power > 14 ) + { + power = 14; + } + SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70; + SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F ); + } + SX1276Write( REG_LR_PACONFIG, SX1276LR->RegPaConfig ); + LoRaSettings.Power = power; +} + +int8_t SX1276LoRaGetRFPower( void ) +{ + SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig ); + SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac ); + + if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) + { + if( ( SX1276LR->RegPaDac & 0x07 ) == 0x07 ) + { + LoRaSettings.Power = 5 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK ); + } + else + { + LoRaSettings.Power = 2 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK ); + } + } + else + { + LoRaSettings.Power = -1 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK ); + } + return LoRaSettings.Power; +} + +void SX1276LoRaSetSignalBandwidth( uint8_t bw ) +{ + SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 ); + SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | ( bw << 4 ); + SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 ); + LoRaSettings.SignalBw = bw; +} + +uint8_t SX1276LoRaGetSignalBandwidth( void ) +{ + SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 ); + LoRaSettings.SignalBw = ( SX1276LR->RegModemConfig1 & ~RFLR_MODEMCONFIG1_BW_MASK ) >> 4; + return LoRaSettings.SignalBw; +} + +void SX1276LoRaSetSpreadingFactor( uint8_t factor ) +{ + + if( factor > 12 ) + { + factor = 12; + } + else if( factor < 6 ) + { + factor = 6; + } + + if( factor == 6 ) + { + SX1276LoRaSetNbTrigPeaks( 5 ); + } + else + { + SX1276LoRaSetNbTrigPeaks( 3 ); + } + + SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 ); + SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | ( factor << 4 ); + SX1276Write( REG_LR_MODEMCONFIG2, SX1276LR->RegModemConfig2 ); + LoRaSettings.SpreadingFactor = factor; +} + +uint8_t SX1276LoRaGetSpreadingFactor( void ) +{ + SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 ); + LoRaSettings.SpreadingFactor = ( SX1276LR->RegModemConfig2 & ~RFLR_MODEMCONFIG2_SF_MASK ) >> 4; + return LoRaSettings.SpreadingFactor; +} + +void SX1276LoRaSetErrorCoding( uint8_t value ) +{ + SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 ); + SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | ( value << 1 ); + SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 ); + LoRaSettings.ErrorCoding = value; +} + +uint8_t SX1276LoRaGetErrorCoding( void ) +{ + SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 ); + LoRaSettings.ErrorCoding = ( SX1276LR->RegModemConfig1 & ~RFLR_MODEMCONFIG1_CODINGRATE_MASK ) >> 1; + return LoRaSettings.ErrorCoding; +} + +void SX1276LoRaSetPacketCrcOn( bool enable ) +{ + SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 ); + SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | ( enable << 2 ); + SX1276Write( REG_LR_MODEMCONFIG2, SX1276LR->RegModemConfig2 ); + LoRaSettings.CrcOn = enable; +} + +void SX1276LoRaSetPreambleLength( uint16_t value ) +{ + SX1276ReadBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 ); + + SX1276LR->RegPreambleMsb = ( value >> 8 ) & 0x00FF; + SX1276LR->RegPreambleLsb = value & 0xFF; + SX1276WriteBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 ); +} + +uint16_t SX1276LoRaGetPreambleLength( void ) +{ + SX1276ReadBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 ); + return ( ( SX1276LR->RegPreambleMsb & 0x00FF ) << 8 ) | SX1276LR->RegPreambleLsb; +} + +bool SX1276LoRaGetPacketCrcOn( void ) +{ + SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 ); + LoRaSettings.CrcOn = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON ) >> 1; + return LoRaSettings.CrcOn; +} + +void SX1276LoRaSetImplicitHeaderOn( bool enable ) +{ + SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 ); + SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | ( enable ); + SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 ); + LoRaSettings.ImplicitHeaderOn = enable; +} + +bool SX1276LoRaGetImplicitHeaderOn( void ) +{ + SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 ); + LoRaSettings.ImplicitHeaderOn = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_IMPLICITHEADER_ON ); + return LoRaSettings.ImplicitHeaderOn; +} + +void SX1276LoRaSetRxSingleOn( bool enable ) +{ + LoRaSettings.RxSingleOn = enable; +} + +bool SX1276LoRaGetRxSingleOn( void ) +{ + return LoRaSettings.RxSingleOn; +} + +void SX1276LoRaSetFreqHopOn( bool enable ) +{ + LoRaSettings.FreqHopOn = enable; +} + +bool SX1276LoRaGetFreqHopOn( void ) +{ + return LoRaSettings.FreqHopOn; +} + +void SX1276LoRaSetHopPeriod( uint8_t value ) +{ + SX1276LR->RegHopPeriod = value; + SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod ); + LoRaSettings.HopPeriod = value; +} + +uint8_t SX1276LoRaGetHopPeriod( void ) +{ + SX1276Read( REG_LR_HOPPERIOD, &SX1276LR->RegHopPeriod ); + LoRaSettings.HopPeriod = SX1276LR->RegHopPeriod; + return LoRaSettings.HopPeriod; +} + +void SX1276LoRaSetTxPacketTimeout( uint32_t value ) +{ + LoRaSettings.TxPacketTimeout = value; +} + +uint32_t SX1276LoRaGetTxPacketTimeout( void ) +{ + return LoRaSettings.TxPacketTimeout; +} + +void SX1276LoRaSetRxPacketTimeout( uint32_t value ) +{ + LoRaSettings.RxPacketTimeout = value; +} + +uint32_t SX1276LoRaGetRxPacketTimeout( void ) +{ + return LoRaSettings.RxPacketTimeout; +} + +void SX1276LoRaSetPayloadLength( uint8_t value ) +{ + SX1276LR->RegPayloadLength = value; + SX1276Write( REG_LR_PAYLOADLENGTH, SX1276LR->RegPayloadLength ); + LoRaSettings.PayloadLength = value; +} + +uint8_t SX1276LoRaGetPayloadLength( void ) +{ + SX1276Read( REG_LR_PAYLOADLENGTH, &SX1276LR->RegPayloadLength ); + LoRaSettings.PayloadLength = SX1276LR->RegPayloadLength; + return LoRaSettings.PayloadLength; +} + +void SX1276LoRaSetPa20dBm( bool enale ) +{ + SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac ); + SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig ); + + if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST ) + { + if( enale == true ) + { + SX1276LR->RegPaDac = 0x87; + } + } + else + { + SX1276LR->RegPaDac = 0x84; + } + SX1276Write( REG_LR_PADAC, SX1276LR->RegPaDac ); +} + +bool SX1276LoRaGetPa20dBm( void ) +{ + SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac ); + + return ( ( SX1276LR->RegPaDac & 0x07 ) == 0x07 ) ? true : false; +} + +void SX1276LoRaSetPAOutput( uint8_t outputPin ) +{ + SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig ); + SX1276LR->RegPaConfig = (SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | outputPin; + SX1276Write( REG_LR_PACONFIG, SX1276LR->RegPaConfig ); +} + +uint8_t SX1276LoRaGetPAOutput( void ) +{ + SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig ); + return SX1276LR->RegPaConfig & ~RFLR_PACONFIG_PASELECT_MASK; +} + +void SX1276LoRaSetPaRamp( uint8_t value ) +{ + SX1276Read( REG_LR_PARAMP, &SX1276LR->RegPaRamp ); + SX1276LR->RegPaRamp = ( SX1276LR->RegPaRamp & RFLR_PARAMP_MASK ) | ( value & ~RFLR_PARAMP_MASK ); + SX1276Write( REG_LR_PARAMP, SX1276LR->RegPaRamp ); +} + +uint8_t SX1276LoRaGetPaRamp( void ) +{ + SX1276Read( REG_LR_PARAMP, &SX1276LR->RegPaRamp ); + return SX1276LR->RegPaRamp & ~RFLR_PARAMP_MASK; +} + +void SX1276LoRaSetSymbTimeout( uint16_t value ) +{ + SX1276ReadBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 ); + + SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | ( ( value >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ); + SX1276LR->RegSymbTimeoutLsb = value & 0xFF; + SX1276WriteBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 ); +} + +uint16_t SX1276LoRaGetSymbTimeout( void ) +{ + SX1276ReadBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 ); + return ( ( SX1276LR->RegModemConfig2 & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) << 8 ) | SX1276LR->RegSymbTimeoutLsb; +} + +void SX1276LoRaSetLowDatarateOptimize( bool enable ) +{ + SX1276Read( REG_LR_MODEMCONFIG3, &SX1276LR->RegModemConfig3 ); + SX1276LR->RegModemConfig3 = ( SX1276LR->RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( enable << 3 ); + SX1276Write( REG_LR_MODEMCONFIG3, SX1276LR->RegModemConfig3 ); +} + +bool SX1276LoRaGetLowDatarateOptimize( void ) +{ + SX1276Read( REG_LR_MODEMCONFIG3, &SX1276LR->RegModemConfig3 ); + return ( ( SX1276LR->RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON ) >> 3 ); +} + +void SX1276LoRaSetNbTrigPeaks( uint8_t value ) +{ + SX1276Read( 0x31, &SX1276LR->RegDetectOptimize ); + SX1276LR->RegDetectOptimize = ( SX1276LR->RegDetectOptimize & 0xF8 ) | value; + SX1276Write( 0x31, SX1276LR->RegDetectOptimize ); +} + +uint8_t SX1276LoRaGetNbTrigPeaks( void ) +{ + SX1276Read( 0x31, &SX1276LR->RegDetectOptimize ); + return ( SX1276LR->RegDetectOptimize & 0x07 ); +} + +#endif // USE_SX1276_RADIO diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRaMisc.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRaMisc.h new file mode 100644 index 000000000..3f5d7e5fa --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276-LoRaMisc.h @@ -0,0 +1,315 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276-LoRaMisc.h + * \brief SX1276 RF chip high level functions driver + * + * \remark Optional support functions. + * These functions are defined only to easy the change of the + * parameters. + * For a final firmware the radio parameters will be known so + * there is no need to support all possible parameters. + * Removing these functions will greatly reduce the final firmware + * size. + * + * \version 2.0.B2 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#ifndef __SX1276_LORA_MISC_H__ +#define __SX1276_LORA_MISC_H__ + + +/*! + * \brief Writes the new RF frequency value + * + * \param [IN] freq New RF frequency value in [Hz] + */ +void SX1276LoRaSetRFFrequency( uint32_t freq ); + +/*! + * \brief Reads the current RF frequency value + * + * \retval freq Current RF frequency value in [Hz] + */ +uint32_t SX1276LoRaGetRFFrequency( void ); + +/*! + * \brief Writes the new RF output power value + * + * \param [IN] power New output power value in [dBm] + */ +void SX1276LoRaSetRFPower( int8_t power ); + +/*! + * \brief Reads the current RF output power value + * + * \retval power Current output power value in [dBm] + */ +int8_t SX1276LoRaGetRFPower( void ); + +/*! + * \brief Writes the new Signal Bandwidth value + * + * \remark This function sets the IF frequency according to the datasheet + * + * \param [IN] factor New Signal Bandwidth value [0: 125 kHz, 1: 250 kHz, 2: 500 kHz] + */ +void SX1276LoRaSetSignalBandwidth( uint8_t bw ); + +/*! + * \brief Reads the current Signal Bandwidth value + * + * \retval factor Current Signal Bandwidth value [0: 125 kHz, 1: 250 kHz, 2: 500 kHz] + */ +uint8_t SX1276LoRaGetSignalBandwidth( void ); + +/*! + * \brief Writes the new Spreading Factor value + * + * \param [IN] factor New Spreading Factor value [7, 8, 9, 10, 11, 12] + */ +void SX1276LoRaSetSpreadingFactor( uint8_t factor ); + +/*! + * \brief Reads the current Spreading Factor value + * + * \retval factor Current Spreading Factor value [7, 8, 9, 10, 11, 12] + */ +uint8_t SX1276LoRaGetSpreadingFactor( void ); + +/*! + * \brief Writes the new Error Coding value + * + * \param [IN] value New Error Coding value [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + */ +void SX1276LoRaSetErrorCoding( uint8_t value ); + +/*! + * \brief Reads the current Error Coding value + * + * \retval value Current Error Coding value [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + */ +uint8_t SX1276LoRaGetErrorCoding( void ); + +/*! + * \brief Enables/Disables the packet CRC generation + * + * \param [IN] enaable [true, false] + */ +void SX1276LoRaSetPacketCrcOn( bool enable ); + +/*! + * \brief Reads the current packet CRC generation status + * + * \retval enable [true, false] + */ +bool SX1276LoRaGetPacketCrcOn( void ); + +/*! + * \brief Enables/Disables the Implicit Header mode in LoRa + * + * \param [IN] enable [true, false] + */ +void SX1276LoRaSetImplicitHeaderOn( bool enable ); + +/*! + * \brief Check if implicit header mode in LoRa in enabled or disabled + * + * \retval enable [true, false] + */ +bool SX1276LoRaGetImplicitHeaderOn( void ); + +/*! + * \brief Enables/Disables Rx single instead of Rx continuous + * + * \param [IN] enable [true, false] + */ +void SX1276LoRaSetRxSingleOn( bool enable ); + +/*! + * \brief Check if LoRa is in Rx Single mode + * + * \retval enable [true, false] + */ +bool SX1276LoRaGetRxSingleOn( void ); + +/*! + * \brief Enables/Disables the frequency hopping + * + * \param [IN] enable [true, false] + */ + +void SX1276LoRaSetFreqHopOn( bool enable ); + +/*! + * \brief Get the frequency hopping status + * + * \param [IN] enable [true, false] + */ +bool SX1276LoRaGetFreqHopOn( void ); + +/*! + * \brief Set symbol period between frequency hops + * + * \param [IN] value + */ +void SX1276LoRaSetHopPeriod( uint8_t value ); + +/*! + * \brief Get symbol period between frequency hops + * + * \retval value symbol period between frequency hops + */ +uint8_t SX1276LoRaGetHopPeriod( void ); + +/*! + * \brief Set timeout Tx packet (based on MCU timer, timeout between Tx Mode entry Tx Done IRQ) + * + * \param [IN] value timeout (ms) + */ +void SX1276LoRaSetTxPacketTimeout( uint32_t value ); + +/*! + * \brief Get timeout between Tx packet (based on MCU timer, timeout between Tx Mode entry Tx Done IRQ) + * + * \retval value timeout (ms) + */ +uint32_t SX1276LoRaGetTxPacketTimeout( void ); + +/*! + * \brief Set timeout Rx packet (based on MCU timer, timeout between Rx Mode entry and Rx Done IRQ) + * + * \param [IN] value timeout (ms) + */ +void SX1276LoRaSetRxPacketTimeout( uint32_t value ); + +/*! + * \brief Get timeout Rx packet (based on MCU timer, timeout between Rx Mode entry and Rx Done IRQ) + * + * \retval value timeout (ms) + */ +uint32_t SX1276LoRaGetRxPacketTimeout( void ); + +/*! + * \brief Set payload length + * + * \param [IN] value payload length + */ +void SX1276LoRaSetPayloadLength( uint8_t value ); + +/*! + * \brief Get payload length + * + * \retval value payload length + */ +uint8_t SX1276LoRaGetPayloadLength( void ); + +/*! + * \brief Enables/Disables the 20 dBm PA + * + * \param [IN] enable [true, false] + */ +void SX1276LoRaSetPa20dBm( bool enale ); + +/*! + * \brief Gets the current 20 dBm PA status + * + * \retval enable [true, false] + */ +bool SX1276LoRaGetPa20dBm( void ); + +/*! + * \brief Set the RF Output pin + * + * \param [IN] RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO + */ +void SX1276LoRaSetPAOutput( uint8_t outputPin ); + +/*! + * \brief Gets the used RF Ouptut pin + * + * \retval RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO + */ +uint8_t SX1276LoRaGetPAOutput( void ); + +/*! + * \brief Writes the new PA rise/fall time of ramp up/down value + * + * \param [IN] value New PaRamp value + */ +void SX1276LoRaSetPaRamp( uint8_t value ); + +/*! + * \brief Reads the current PA rise/fall time of ramp up/down value + * + * \retval freq Current PaRamp value + */ +uint8_t SX1276LoRaGetPaRamp( void ); + +/*! + * \brief Set Symbol Timeout based on symbol length + * + * \param [IN] value number of symbol + */ +void SX1276LoRaSetSymbTimeout( uint16_t value ); + +/*! + * \brief Get Symbol Timeout based on symbol length + * + * \retval value number of symbol + */ +uint16_t SX1276LoRaGetSymbTimeout( void ); + +/*! + * \brief Configure the device to optimize low datarate transfers + * + * \param [IN] enable Enables/Disables the low datarate optimization + */ +void SX1276LoRaSetLowDatarateOptimize( bool enable ); + +/*! + * \brief Get the status of optimize low datarate transfers + * + * \retval LowDatarateOptimize enable or disable + */ +bool SX1276LoRaGetLowDatarateOptimize( void ); + +/*! + * \brief Get the preamble length + * + * \retval value preamble length + */ +uint16_t SX1276LoRaGetPreambleLength( void ); + +/*! + * \brief Set the preamble length + * + * \param [IN] value preamble length + */ +void SX1276LoRaSetPreambleLength( uint16_t value ); + +/*! + * \brief Set the number or rolling preamble symbol needed for detection + * + * \param [IN] value number of preamble symbol + */ +void SX1276LoRaSetNbTrigPeaks( uint8_t value ); + +/*! + * \brief Get the number or rolling preamble symbol needed for detection + * + * \retval value number of preamble symbol + */ +uint8_t SX1276LoRaGetNbTrigPeaks( void ); +#endif //__SX1276_LORA_MISC_H__ \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276.c new file mode 100644 index 000000000..903afe843 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276.c @@ -0,0 +1,304 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276.c + * \brief SX1276 RF chip driver + * + * \version 2.0.0 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#include "platform.h" +#include "radio.h" + +#if defined( USE_SX1276_RADIO ) + +#include "sx1276.h" + +#include "sx1276-Hal.h" +#include "sx1276-Fsk.h" +#include "sx1276-LoRa.h" + +/*! + * SX1276 registers variable + */ +uint8_t SX1276Regs[0x70]; + +static bool LoRaOn = true; +static bool LoRaOnState = false; + +void SX1276Init( void ) +{ + // Initialize FSK and LoRa registers structure + SX1276 = ( tSX1276* )SX1276Regs; + SX1276LR = ( tSX1276LR* )SX1276Regs; + + SX1276InitIo( ); + + SX1276Reset( ); + + // REMARK: After radio reset the default modem is FSK + +#if ( LORA == 0 ) + + LoRaOn = false; + SX1276SetLoRaOn( LoRaOn ); + // Initialize FSK modem + SX1276FskInit( ); + +#else + + LoRaOn = true; + SX1276SetLoRaOn( LoRaOn ); + // Initialize LoRa modem + SX1276LoRaInit( ); + +#endif + +} + +void SX1276Reset( void ) +{ + SX1276SetReset( RADIO_RESET_ON ); + + // Wait 1ms + uint32_t startTick = GET_TICK_COUNT( ); + while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) ); + + SX1276SetReset( RADIO_RESET_OFF ); + + // Wait 6ms + startTick = GET_TICK_COUNT( ); + while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 6 ) ); +} + +void SX1276SetLoRaOn( bool enable ) +{ + if( LoRaOnState == enable ) + { + return; + } + LoRaOnState = enable; + LoRaOn = enable; + + if( LoRaOn == true ) + { + SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP ); + + SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON; + SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode ); + + SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY ); + // RxDone RxTimeout FhssChangeChannel CadDone + SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00; + // CadDetected ModeReady + SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00; + SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 ); + + SX1276ReadBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 ); + } + else + { + SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP ); + + SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF; + SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode ); + + SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY ); + + SX1276ReadBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 ); + } +} + +bool SX1276GetLoRaOn( void ) +{ + return LoRaOn; +} + +void SX1276SetOpMode( uint8_t opMode ) +{ + if( LoRaOn == false ) + { + SX1276FskSetOpMode( opMode ); + } + else + { + SX1276LoRaSetOpMode( opMode ); + } +} + +uint8_t SX1276GetOpMode( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskGetOpMode( ); + } + else + { + return SX1276LoRaGetOpMode( ); + } +} + +double SX1276ReadRssi( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskReadRssi( ); + } + else + { + return SX1276LoRaReadRssi( ); + } +} + +uint8_t SX1276ReadRxGain( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskReadRxGain( ); + } + else + { + return SX1276LoRaReadRxGain( ); + } +} + +uint8_t SX1276GetPacketRxGain( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskGetPacketRxGain( ); + } + else + { + return SX1276LoRaGetPacketRxGain( ); + } +} + +int8_t SX1276GetPacketSnr( void ) +{ + if( LoRaOn == false ) + { + while( 1 ) + { + // Useless in FSK mode + // Block program here + } + } + else + { + return SX1276LoRaGetPacketSnr( ); + } +} + +double SX1276GetPacketRssi( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskGetPacketRssi( ); + } + else + { + return SX1276LoRaGetPacketRssi( ); + } +} + +uint32_t SX1276GetPacketAfc( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskGetPacketAfc( ); + } + else + { + while( 1 ) + { + // Useless in LoRa mode + // Block program here + } + } +} + +void SX1276StartRx( void ) +{ + if( LoRaOn == false ) + { + SX1276FskSetRFState( RF_STATE_RX_INIT ); + } + else + { + SX1276LoRaSetRFState( RFLR_STATE_RX_INIT ); + } +} + +void SX1276GetRxPacket( void *buffer, uint16_t *size ) +{ + if( LoRaOn == false ) + { + SX1276FskGetRxPacket( buffer, size ); + } + else + { + SX1276LoRaGetRxPacket( buffer, size ); + } +} + +void SX1276SetTxPacket( const void *buffer, uint16_t size ) +{ + if( LoRaOn == false ) + { + SX1276FskSetTxPacket( buffer, size ); + } + else + { + SX1276LoRaSetTxPacket( buffer, size ); + } +} + +uint8_t SX1276GetRFState( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskGetRFState( ); + } + else + { + return SX1276LoRaGetRFState( ); + } +} + +void SX1276SetRFState( uint8_t state ) +{ + if( LoRaOn == false ) + { + SX1276FskSetRFState( state ); + } + else + { + SX1276LoRaSetRFState( state ); + } +} + +uint32_t SX1276Process( void ) +{ + if( LoRaOn == false ) + { + return SX1276FskProcess( ); + } + else + { + return SX1276LoRaProcess( ); + } +} + +#endif // USE_SX1276_RADIO diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276.h new file mode 100644 index 000000000..45cd0c8ca --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/sx1278/sx1278_source/src/radio/sx1276.h @@ -0,0 +1,157 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) SEMTECH S.A. + */ +/*! + * \file sx1276.h + * \brief SX1276 RF chip driver + * + * \version 2.0.B2 + * \date May 6 2013 + * \author Gregory Cristian + * + * Last modified by Miguel Luis on Jun 19 2013 + */ +#ifndef __SX1276_H__ +#define __SX1276_H__ + +/*! + * \brief SX1276 registers array + */ +extern uint8_t SX1276Regs[0x70]; + +/*! + * \brief Enables LoRa modem or FSK modem + * + * \param [IN] opMode New operating mode + */ +void SX1276SetLoRaOn( bool enable ); + +/*! + * \brief Gets the LoRa modem state + * + * \retval LoraOn Current LoRa modem mode + */ +bool SX1276GetLoRaOn( void ); + +/*! + * \brief Initializes the SX1276 + */ +void SX1276Init( void ); + +/*! + * \brief Resets the SX1276 + */ +void SX1276Reset( void ); + +/*! + * \brief Sets the SX1276 operating mode + * + * \param [IN] opMode New operating mode + */ +void SX1276SetOpMode( uint8_t opMode ); + +/*! + * \brief Gets the SX1276 operating mode + * + * \retval opMode Current operating mode + */ +uint8_t SX1276GetOpMode( void ); + +/*! + * \brief Reads the current Rx gain setting + * + * \retval rxGain Current gain setting + */ +uint8_t SX1276ReadRxGain( void ); + +/*! + * \brief Trigs and reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276ReadRssi( void ); + +/*! + * \brief Gets the Rx gain value measured while receiving the packet + * + * \retval rxGainValue Current Rx gain value + */ +uint8_t SX1276GetPacketRxGain( void ); + +/*! + * \brief Gets the SNR value measured while receiving the packet + * + * \retval snrValue Current SNR value in [dB] + */ +int8_t SX1276GetPacketSnr( void ); + +/*! + * \brief Gets the RSSI value measured while receiving the packet + * + * \retval rssiValue Current RSSI value in [dBm] + */ +double SX1276GetPacketRssi( void ); + +/*! + * \brief Gets the AFC value measured while receiving the packet + * + * \retval afcValue Current AFC value in [Hz] + */ +uint32_t SX1276GetPacketAfc( void ); + +/*! + * \brief Sets the radio in Rx mode. Waiting for a packet + */ +void SX1276StartRx( void ); + +/*! + * \brief Gets a copy of the current received buffer + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276GetRxPacket( void *buffer, uint16_t *size ); + +/*! + * \brief Sets a copy of the buffer to be transmitted and starts the + * transmission + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void SX1276SetTxPacket( const void *buffer, uint16_t size ); + +/*! + * \brief Gets the current RFState + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint8_t SX1276GetRFState( void ); + +/*! + * \brief Sets the new state of the RF state machine + * + * \param [IN]: state New RF state machine state + */ +void SX1276SetRFState( uint8_t state ); + +/*! + * \brief Process the Rx and Tx state machines depending on the + * SX1276 operating mode. + * + * \retval rfState Current RF state [RF_IDLE, RF_BUSY, + * RF_RX_DONE, RF_RX_TIMEOUT, + * RF_TX_DONE, RF_TX_TIMEOUT] + */ +uint32_t SX1276Process( void ); + +#endif //__SX1276_H__ \ No newline at end of file