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feat support ADC driver for aiit-arm32-board and stm32f407-st-discovery

This commit is contained in:
Liu_Weichao 2022-01-10 14:08:58 +08:00
parent cb8c68659c
commit 2e8383397b
36 changed files with 6526 additions and 6 deletions
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10
APP_Framework/Applications/app_test/Kconfig
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@ -8,5 +8,15 @@ menu "test app"
bool "Config test spi flash"
default n
menuconfig USER_TEST_ADC
bool "Config test adc"
default n
if USER_TEST_ADC
if ADD_XIUOS_FETURES
config ADC_DEV_DRIVER
string "Set ADC dev path"
default "/dev/adc1_dev"
endif
endif
endif
endmenu

4
APP_Framework/Applications/app_test/Makefile
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@ -4,4 +4,8 @@ ifeq ($(CONFIG_USER_TEST_SPI_FLASH),y)
SRC_FILES += test_spi_flash.c
endif
ifeq ($(CONFIG_USER_TEST_ADC),y)
SRC_FILES += test_adc.c
endif
include $(KERNEL_ROOT)/compiler.mk

58
APP_Framework/Applications/app_test/test_adc.c Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file: test_adc.c
* @brief: a application of adc function
* @version: 1.1
* @author: AIIT XUOS Lab
* @date: 2022/1/7
*/
#include <stdio.h>
#include <string.h>
#include <transform.h>
void test_adc()
{
int adc_fd;
uint8 adc_channel = 0x0;
uint16 adc_sample, adc_value_decimal = 0;
float adc_value;
adc_fd = PrivOpen(ADC_DEV_DRIVER, O_RDWR);
if (adc_fd < 0) {
KPrintf("open adc fd error %d\n", adc_fd);
return;
}
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = ADC_TYPE;
ioctl_cfg.args = &adc_channel;
if (0 != PrivIoctl(adc_fd, OPE_CFG, &ioctl_cfg)) {
KPrintf("ioctl adc fd error %d\n", adc_fd);
PrivClose(adc_fd);
return;
}
PrivRead(adc_fd, &adc_sample, 2);
adc_value = (float)adc_sample * (3.3 / 4096);
adc_value_decimal = (adc_value - (uint16)adc_value) * 1000;
printf("adc sample %u value integer %u decimal %u\n", adc_sample, (uint16)adc_value, adc_value_decimal);
return;
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
test_adc, test_adc, read 3.3 voltage data from adc);

3
APP_Framework/Framework/transform_layer/xiuos/transform.c
View File

@ -154,6 +154,9 @@ int PrivIoctl(int fd, int cmd, void *args)
case I2C_TYPE:
ret = ioctl(fd, cmd, ioctl_cfg->args);
break;
case ADC_TYPE:
ret = ioctl(fd, cmd, ioctl_cfg->args);
break;
default:
break;
}

1
APP_Framework/Framework/transform_layer/xiuos/transform.h
View File

@ -138,6 +138,7 @@ enum IoctlDriverType
SPI_TYPE,
I2C_TYPE,
PIN_TYPE,
ADC_TYPE,
DEFAULT_TYPE,
};

2
APP_Framework/Kconfig
View File

@ -5,8 +5,8 @@ menu "APP_Framework"
option env="SRC_APP_DIR"
default "."
source "$APP_DIR/Applications/Kconfig"
source "$APP_DIR/Framework/Kconfig"
source "$APP_DIR/Applications/Kconfig"
source "$APP_DIR/lib/Kconfig"

4
Ubiquitous/XiUOS/board/aiit-arm32-board/board.c
View File

@ -48,6 +48,7 @@ extern int Stm32HwTouchBusInit(void);
extern int Stm32HwCanBusInit(void);
extern int HwSdioInit();
extern int HwSramInit(void);
extern int Stm32HwAdcInit(void);
static void ClockConfiguration()
{
@ -146,6 +147,9 @@ struct InitSequenceDesc _board_init[] =
#endif
#ifdef BSP_USING_EXTMEM
{ "hw extern sram", HwSramInit },
#endif
#ifdef BSP_USING_ADC
{"hw adc init", Stm32HwAdcInit},
#endif
{ " NONE ",NONE },
};

9
Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/Kconfig
View File

@ -94,8 +94,13 @@ if BSP_USING_UART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif
menuconfig BSP_USING_ADC
bool "Using ADC device"
default n
select RESOURCES_ADC
if BSP_USING_ADC
source "$BSP_DIR/third_party_driver/adc/Kconfig"
endif
menuconfig BSP_USING_CAN
bool "Using CAN device"

5
Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/Makefile
View File

@ -4,7 +4,6 @@ ifeq ($(CONFIG_BSP_USING_CH438),y)
SRC_DIR += ch438
endif
ifeq ($(CONFIG_BSP_USING_EXTMEM),y)
SRC_DIR += extmem
endif
@ -57,4 +56,8 @@ ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_DIR += can
endif
ifeq ($(CONFIG_BSP_USING_ADC),y)
SRC_DIR += adc
endif
include $(KERNEL_ROOT)/compiler.mk

76
Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/adc/Kconfig Normal file
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@ -0,0 +1,76 @@
menuconfig BSP_USING_ADC1
bool "Enable ADC1"
default n
if BSP_USING_ADC1
config ADC1_BUS_NAME
string "adc 1 bus name"
default "adc1"
config ADC1_DRIVER_NAME
string "adc 1 driver name"
default "adc1_drv"
config ADC1_DEVICE_NAME
string "adc 1 bus device name"
default "adc1_dev"
config ADC1_GPIO_NUM
int "adc 1 gpio pin num"
default "0"
config ADC1_GPIO_DEF
string "adc 1 gpio define type"
default "A"
endif
menuconfig BSP_USING_ADC2
bool "Enable ADC2"
default n
if BSP_USING_ADC2
config ADC2_BUS_NAME
string "adc 2 bus name"
default "adc2"
config ADC2_DRIVER_NAME
string "adc 2 driver name"
default "adc2_drv"
config ADC2_DEVICE_NAME
string "adc 2 bus device name"
default "adc2_dev"
config ADC2_GPIO_NUM
int "adc 2 gpio pin num"
default "6"
config ADC2_GPIO_DEF
string "adc 2 gpio define type"
default "A"
endif
menuconfig BSP_USING_ADC3
bool "Enable ADC3"
default n
if BSP_USING_ADC3
config ADC3_BUS_NAME
string "adc 3 bus name"
default "adc3"
config ADC3_DRIVER_NAME
string "adc 3 driver name"
default "adc3_drv"
config ADC3_DEVICE_NAME
string "adc 3 bus device name"
default "adc3_dev"
config ADC3_GPIO_NUM
int "adc 3 gpio pin num"
default "0"
config ADC3_GPIO_DEF
string "adc 3 gpio define type"
default "A"
endif

3
Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/adc/Makefile Normal file
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@ -0,0 +1,3 @@
SRC_FILES := connect_adc.c hardware_adc.c
include $(KERNEL_ROOT)/compiler.mk

422
Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/adc/connect_adc.c Normal file
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@ -0,0 +1,422 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_adc.c
* @brief support to register ADC pointer and function
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#include <connect_adc.h>
#define _ADC_CONS(string1, string2) string1##string2
#define ADC_CONS(string1, string2) _ADC_CONS(string1, string2)
#ifdef BSP_USING_ADC1
#define ADC1_GPIO ADC_CONS(GPIO_Pin_, ADC1_GPIO_NUM)
#endif
#ifdef BSP_USING_ADC2
#define ADC2_GPIO ADC_CONS(GPIO_Pin_, ADC2_GPIO_NUM)
#endif
#ifdef BSP_USING_ADC3
#define ADC3_GPIO ADC_CONS(GPIO_Pin_, ADC3_GPIO_NUM)
#endif
static int Stm32AdcUdelay(uint32 us)
{
uint32 ticks;
uint32 told, tnow, tcnt = 0;
uint32 reload = SysTick->LOAD;
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
tcnt += told - tnow;
} else {
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks) {
return 0;
break;
}
}
}
}
static GPIO_TypeDef* AdcGetGpioType(char *adc_gpio_def)
{
if (0 == strncmp(adc_gpio_def, "A", 2)) {
return GPIOA;
} else if (0 == strncmp(adc_gpio_def, "B", 2)) {
return GPIOB;
} else if (0 == strncmp(adc_gpio_def, "C", 2)) {
return GPIOC;
} else if (0 == strncmp(adc_gpio_def, "F", 2)) {
return GPIOF;
} else {
printf("AdcGetGpioType do not support %s GPIO\n", adc_gpio_def);
return GPIOA;
}
}
static uint32 AdcGetGpioRcc(char *adc_gpio_def)
{
if (0 == strncmp(adc_gpio_def, "A", 2)) {
return RCC_AHB1Periph_GPIOA;
} else if (0 == strncmp(adc_gpio_def, "B", 2)) {
return RCC_AHB1Periph_GPIOB;
} else if (0 == strncmp(adc_gpio_def, "C", 2)) {
return RCC_AHB1Periph_GPIOC;
} else if (0 == strncmp(adc_gpio_def, "F", 2)) {
return RCC_AHB1Periph_GPIOF;
} else {
printf("AdcGetGpioRcc do not support %s GPIO\n", adc_gpio_def);
return RCC_AHB1Periph_GPIOA;
}
}
static void AdcInit(struct AdcHardwareDevice *adc_dev)
{
GPIO_InitTypeDef GPIO_InitStructure;
ADC_CommonInitTypeDef ADC_CommonInitStructure;
ADC_InitTypeDef ADC_InitStructure;
uint32_t RCC_AHB1Periph;
GPIO_TypeDef* GPIOx;
#ifdef BSP_USING_ADC1
if (0 == strncmp(adc_dev->haldev.dev_name, ADC1_DEVICE_NAME, NAME_NUM_MAX)) {
GPIOx = AdcGetGpioType(ADC1_GPIO_DEF);
RCC_AHB1Periph = AdcGetGpioRcc(ADC1_GPIO_DEF);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);//enable ADC1 clock
GPIO_InitStructure.GPIO_Pin = ADC1_GPIO;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOx, &GPIO_InitStructure);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC1, &ADC_InitStructure);
ADC_Cmd(ADC1, ENABLE);
}
#endif
#ifdef BSP_USING_ADC2
if (0 == strncmp(adc_dev->haldev.dev_name, ADC2_DEVICE_NAME, NAME_NUM_MAX)) {
GPIOx = AdcGetGpioType(ADC2_GPIO_DEF);
RCC_AHB1Periph = AdcGetGpioRcc(ADC2_GPIO_DEF);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);//enable ADC2 clock
GPIO_InitStructure.GPIO_Pin = ADC2_GPIO;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOx, &GPIO_InitStructure);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC2, &ADC_InitStructure);
ADC_Cmd(ADC2, ENABLE);
}
#endif
#ifdef BSP_USING_ADC3
if (0 == strncmp(adc_dev->haldev.dev_name, ADC3_DEVICE_NAME, NAME_NUM_MAX)) {
GPIOx = AdcGetGpioType(ADC3_GPIO_DEF);
RCC_AHB1Periph = AdcGetGpioRcc(ADC3_GPIO_DEF);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE);//enable ADC3 clock
GPIO_InitStructure.GPIO_Pin = ADC3_GPIO;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOx, &GPIO_InitStructure);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC3, &ADC_InitStructure);
ADC_Cmd(ADC3, ENABLE);
}
#endif
}
static uint16 GetAdcValue(ADC_TypeDef *ADCx, uint8 channel)
{
//set ADCx channel, rank, sampletime
ADC_RegularChannelConfig(ADCx, channel, 1, ADC_SampleTime_480Cycles);
ADC_SoftwareStartConv(ADCx);
while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC));
return ADC_GetConversionValue(ADCx);
}
static uint16 GetAdcAverageValue(ADC_TypeDef *ADCx, uint8 channel, uint8 times)
{
uint32 temp_val = 0;
int i;
for(i = 0;i < times;i ++) {
temp_val += GetAdcValue(ADCx, channel) & 0x0FFF;
KPrintf("GetAdcAverageValue val %u\n", GetAdcValue(ADCx, channel));
Stm32AdcUdelay(5000);
}
return temp_val / times;
}
static uint32 Stm32AdcOpen(void *dev)
{
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
AdcInit(adc_dev);
return EOK;
}
static uint32 Stm32AdcRead(void *dev, struct BusBlockReadParam *read_param)
{
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data;
uint16 adc_average_value = 0;
uint8 times = 20;
adc_average_value = GetAdcAverageValue(adc_cfg->ADCx, adc_cfg->adc_channel, times);
*(uint16 *)read_param->buffer = adc_average_value;
read_param->read_length = 2;
return read_param->read_length;
}
static uint32 Stm32AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
uint8 adc_channel;
struct AdcDriver *adc_drv = (struct AdcDriver *)drv;
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev;
struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data;
switch (configure_info->configure_cmd)
{
case OPE_CFG:
adc_cfg->adc_channel = *(uint8 *)configure_info->private_data;
if (adc_cfg->adc_channel > 18) {
KPrintf("Stm32AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel);
adc_cfg->adc_channel = 0;
ret = ERROR;
}
break;
default:
break;
}
return ret;
}
static const struct AdcDevDone dev_done =
{
Stm32AdcOpen,
NONE,
NONE,
Stm32AdcRead,
};
int Stm32HwAdcInit(void)
{
x_err_t ret = EOK;
#ifdef BSP_USING_ADC1
static struct AdcBus adc1_bus;
static struct AdcDriver adc1_drv;
static struct AdcHardwareDevice adc1_dev;
static struct Stm32HwAdc adc1_cfg;
adc1_drv.configure = Stm32AdcDrvConfigure;
ret = AdcBusInit(&adc1_bus, ADC1_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC1 bus init error %d\n", ret);
return ERROR;
}
ret = AdcDriverInit(&adc1_drv, ADC1_DRIVER_NAME);
if (ret != EOK) {
KPrintf("ADC1 driver init error %d\n", ret);
return ERROR;
}
ret = AdcDriverAttachToBus(ADC1_DRIVER_NAME, ADC1_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC1 driver attach error %d\n", ret);
return ERROR;
}
adc1_dev.adc_dev_done = &dev_done;
adc1_cfg.ADCx = ADC1;
adc1_cfg.adc_channel = 0;
ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME);
if (ret != EOK) {
KPrintf("ADC1 device register error %d\n", ret);
return ERROR;
}
ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC1_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC1 device register error %d\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_ADC2
static struct AdcBus adc2_bus;
static struct AdcDriver adc2_drv;
static struct AdcHardwareDevice adc2_dev;
static struct Stm32HwAdc adc2_cfg;
adc2_drv.configure = Stm32AdcDrvConfigure;
ret = AdcBusInit(&adc2_bus, ADC2_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC2 bus init error %d\n", ret);
return ERROR;
}
ret = AdcDriverInit(&adc2_drv, ADC2_DRIVER_NAME);
if (ret != EOK) {
KPrintf("ADC2 driver init error %d\n", ret);
return ERROR;
}
ret = AdcDriverAttachToBus(ADC2_DRIVER_NAME, ADC2_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC2 driver attach error %d\n", ret);
return ERROR;
}
adc2_dev.adc_dev_done = &dev_done;
adc2_cfg.ADCx = ADC2;
adc2_cfg.adc_channel = 0;
ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC2_DEVICE_NAME);
if (ret != EOK) {
KPrintf("ADC2 device register error %d\n", ret);
return ERROR;
}
ret = AdcDeviceAttachToBus(ADC2_DEVICE_NAME, ADC2_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC2 device register error %d\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_ADC3
static struct AdcBus adc3_bus;
static struct AdcDriver adc3_drv;
static struct AdcHardwareDevice adc3_dev;
static struct Stm32HwAdc adc3_cfg;
adc3_drv.configure = Stm32AdcDrvConfigure;
ret = AdcBusInit(&adc3_bus, ADC3_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC3 bus init error %d\n", ret);
return ERROR;
}
ret = AdcDriverInit(&adc3_drv, ADC3_DRIVER_NAME);
if (ret != EOK) {
KPrintf("ADC3 driver init error %d\n", ret);
return ERROR;
}
ret = AdcDriverAttachToBus(ADC3_DRIVER_NAME, ADC3_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC3 driver attach error %d\n", ret);
return ERROR;
}
adc3_dev.adc_dev_done = &dev_done;
adc3_cfg.ADCx = ADC3;
adc3_cfg.adc_channel = 0;
ret = AdcDeviceRegister(&adc3_dev, (void *)&adc3_cfg, ADC3_DEVICE_NAME);
if (ret != EOK) {
KPrintf("ADC3 device register error %d\n", ret);
return ERROR;
}
ret = AdcDeviceAttachToBus(ADC3_DEVICE_NAME, ADC3_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC3 device register error %d\n", ret);
return ERROR;
}
#endif
}

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Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/adc/hardware_adc.c Normal file
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37
Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/include/connect_adc.h Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_adc.h
* @brief define aiit-arm32-board adc function and struct
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#ifndef CONNECT_ADC_H
#define CONNECT_ADC_H
#include <device.h>
#include <hardware_adc.h>
#include <hardware_rcc.h>
#include <hardware_gpio.h>
struct Stm32HwAdc
{
ADC_TypeDef *ADCx;
uint8 adc_channel;
};
int Stm32HwAdcInit(void);
#endif

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Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/include/hardware_adc.h Normal file
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/**
******************************************************************************
* @file stm32f4xx_adc.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/**
* @file: hardware_adc.h
* @brief: define hardware adc function
* @version: 1.1
* @author: AIIT XUOS Lab
* @date: 2021/12/28
*/
/*************************************************
File name: hardware_adc.h
Description: define hardware adc function
Others:
History:
1. Date: 2021-12-28
Author: AIIT XUOS Lab
Modification:
1. rename stm32f4xx_adc.h for XiUOS
*************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HARDWARE_ADC_H__
#define __HARDWARE_ADC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stm32f4xx.h>
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
This parameter can be a value of @ref ADC_resolution */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
is performed in Scan (multichannels)
or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
is performed in Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
enable the trigger of a regular group.
This parameter can be a value of
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
the start of conversion of a regular group.
This parameter can be a value of
@ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
is left or right. This parameter can be
a value of @ref ADC_data_align */
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
that will be done using the sequencer for
regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/**
* @brief ADC Common Init structure definition
*/
typedef struct
{
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
independent or multi mode.
This parameter can be a value of @ref ADC_Common_mode */
uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
to the ADC. The clock is common for all the ADCs.
This parameter can be a value of @ref ADC_Prescaler */
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
mode for multi ADC mode.
This parameter can be a value of
@ref ADC_Direct_memory_access_mode_for_multi_mode */
uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of
@ref ADC_delay_between_2_sampling_phases */
}ADC_CommonInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC2) || \
((PERIPH) == ADC3))
/** @defgroup ADC_Common_mode
* @{
*/
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
#define ADC_DualMode_Interl ((uint32_t)0x00000007)
#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
((MODE) == ADC_DualMode_InjecSimult) || \
((MODE) == ADC_DualMode_RegSimult) || \
((MODE) == ADC_DualMode_Interl) || \
((MODE) == ADC_DualMode_AlterTrig) || \
((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
((MODE) == ADC_TripleMode_InjecSimult) || \
((MODE) == ADC_TripleMode_RegSimult) || \
((MODE) == ADC_TripleMode_Interl) || \
((MODE) == ADC_TripleMode_AlterTrig))
/**
* @}
*/
/** @defgroup ADC_Prescaler
* @{
*/
#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
((PRESCALER) == ADC_Prescaler_Div4) || \
((PRESCALER) == ADC_Prescaler_Div6) || \
((PRESCALER) == ADC_Prescaler_Div8))
/**
* @}
*/
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
* @{
*/
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
((MODE) == ADC_DMAAccessMode_1) || \
((MODE) == ADC_DMAAccessMode_2) || \
((MODE) == ADC_DMAAccessMode_3))
/**
* @}
*/
/** @defgroup ADC_delay_between_2_sampling_phases
* @{
*/
#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_20Cycles))
/**
* @}
*/
/** @defgroup ADC_resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x00000000)
#define ADC_Resolution_10b ((uint32_t)0x01000000)
#define ADC_Resolution_8b ((uint32_t)0x02000000)
#define ADC_Resolution_6b ((uint32_t)0x03000000)
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_6b))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_18 ((uint8_t)0x12)
#if defined (STM32F40_41xxx)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || \
((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || \
((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || \
((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || \
((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || \
((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || \
((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || \
((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || \
((CHANNEL) == ADC_Channel_17) || \
((CHANNEL) == ADC_Channel_18))
/**
* @}
*/
/** @defgroup ADC_sampling_times
* @{
*/
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
((TIME) == ADC_SampleTime_15Cycles) || \
((TIME) == ADC_SampleTime_28Cycles) || \
((TIME) == ADC_SampleTime_56Cycles) || \
((TIME) == ADC_SampleTime_84Cycles) || \
((TIME) == ADC_SampleTime_112Cycles) || \
((TIME) == ADC_SampleTime_144Cycles) || \
((TIME) == ADC_SampleTime_480Cycles))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
/**
* @}
*/
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_EOC ((uint16_t)0x0205)
#define ADC_IT_AWD ((uint16_t)0x0106)
#define ADC_IT_JEOC ((uint16_t)0x0407)
#define ADC_IT_OVR ((uint16_t)0x201A)
#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
#define ADC_FLAG_OVR ((uint8_t)0x20)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || \
((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT) || \
((FLAG)== ADC_FLAG_OVR))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(void);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Analog Watchdog configuration functions ************************************/
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
/* Temperature Sensor, Vrefint and VBAT management functions ******************/
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
void ADC_VBATCmd(FunctionalState NewState);
/* Regular Channels Configuration functions ***********************************/
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetMultiModeConversionValue(void);
/* Regular Channels DMA Configuration functions *******************************/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
/* Injected channels Configuration functions **********************************/
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F4xx_ADC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
Ubiquitous/XiUOS/board/stm32f407-st-discovery/board.c
View File

@ -48,6 +48,7 @@ extern int Stm32HwI2cInit(void);
extern int Stm32HwUsartInit();
extern int Stm32HwRtcInit();
extern int HwSdioInit();
extern int Stm32HwAdcInit(void);
static void ClockConfiguration()
{
@ -132,7 +133,10 @@ struct InitSequenceDesc _board_init[] =
{ "hw rtc", Stm32HwRtcInit},
#endif
#ifdef BSP_USING_SDIO
{"hw sdcard init",HwSdioInit},
{"hw sdcard init", HwSdioInit},
#endif
#ifdef BSP_USING_ADC
{"hw adc init", Stm32HwAdcInit},
#endif
{ " NONE ",NONE },
};

8
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/Kconfig
View File

@ -1,3 +1,11 @@
menuconfig BSP_USING_ADC
bool "Using ADC device"
default n
select RESOURCES_ADC
if BSP_USING_ADC
source "$BSP_DIR/third_party_driver/adc/Kconfig"
endif
menuconfig BSP_USING_CAN
bool "Using CAN device"
default n

4
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/Makefile
View File

@ -1,6 +1,10 @@
SRC_DIR := common
ifeq ($(CONFIG_BSP_USING_ADC),y)
SRC_DIR += adc
endif
ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_DIR += can
endif

76
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/adc/Kconfig Normal file
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@ -0,0 +1,76 @@
menuconfig BSP_USING_ADC1
bool "Enable ADC1"
default n
if BSP_USING_ADC1
config ADC1_BUS_NAME
string "adc 1 bus name"
default "adc1"
config ADC1_DRIVER_NAME
string "adc 1 driver name"
default "adc1_drv"
config ADC1_DEVICE_NAME
string "adc 1 bus device name"
default "adc1_dev"
config ADC1_GPIO_NUM
int "adc 1 gpio pin num"
default "0"
config ADC1_GPIO_DEF
string "adc 1 gpio define type"
default "A"
endif
menuconfig BSP_USING_ADC2
bool "Enable ADC2"
default n
if BSP_USING_ADC2
config ADC2_BUS_NAME
string "adc 2 bus name"
default "adc2"
config ADC2_DRIVER_NAME
string "adc 2 driver name"
default "adc2_drv"
config ADC2_DEVICE_NAME
string "adc 2 bus device name"
default "adc2_dev"
config ADC2_GPIO_NUM
int "adc 2 gpio pin num"
default "6"
config ADC2_GPIO_DEF
string "adc 2 gpio define type"
default "A"
endif
menuconfig BSP_USING_ADC3
bool "Enable ADC3"
default n
if BSP_USING_ADC3
config ADC3_BUS_NAME
string "adc 3 bus name"
default "adc3"
config ADC3_DRIVER_NAME
string "adc 3 driver name"
default "adc3_drv"
config ADC3_DEVICE_NAME
string "adc 3 bus device name"
default "adc3_dev"
config ADC3_GPIO_NUM
int "adc 3 gpio pin num"
default "0"
config ADC3_GPIO_DEF
string "adc 3 gpio define type"
default "A"
endif

3
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/adc/Makefile Normal file
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@ -0,0 +1,3 @@
SRC_FILES := connect_adc.c hardware_adc.c
include $(KERNEL_ROOT)/compiler.mk

422
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/adc/connect_adc.c Normal file
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@ -0,0 +1,422 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_adc.c
* @brief support to register ADC pointer and function
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#include <connect_adc.h>
#define _ADC_CONS(string1, string2) string1##string2
#define ADC_CONS(string1, string2) _ADC_CONS(string1, string2)
#ifdef BSP_USING_ADC1
#define ADC1_GPIO ADC_CONS(GPIO_Pin_, ADC1_GPIO_NUM)
#endif
#ifdef BSP_USING_ADC2
#define ADC2_GPIO ADC_CONS(GPIO_Pin_, ADC2_GPIO_NUM)
#endif
#ifdef BSP_USING_ADC3
#define ADC3_GPIO ADC_CONS(GPIO_Pin_, ADC3_GPIO_NUM)
#endif
static int Stm32AdcUdelay(uint32 us)
{
uint32 ticks;
uint32 told, tnow, tcnt = 0;
uint32 reload = SysTick->LOAD;
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
tcnt += told - tnow;
} else {
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks) {
return 0;
break;
}
}
}
}
static GPIO_TypeDef* AdcGetGpioType(char *adc_gpio_def)
{
if (0 == strncmp(adc_gpio_def, "A", 2)) {
return GPIOA;
} else if (0 == strncmp(adc_gpio_def, "B", 2)) {
return GPIOB;
} else if (0 == strncmp(adc_gpio_def, "C", 2)) {
return GPIOC;
} else if (0 == strncmp(adc_gpio_def, "F", 2)) {
return GPIOF;
} else {
printf("AdcGetGpioType do not support %s GPIO\n", adc_gpio_def);
return GPIOA;
}
}
static uint32 AdcGetGpioRcc(char *adc_gpio_def)
{
if (0 == strncmp(adc_gpio_def, "A", 2)) {
return RCC_AHB1Periph_GPIOA;
} else if (0 == strncmp(adc_gpio_def, "B", 2)) {
return RCC_AHB1Periph_GPIOB;
} else if (0 == strncmp(adc_gpio_def, "C", 2)) {
return RCC_AHB1Periph_GPIOC;
} else if (0 == strncmp(adc_gpio_def, "F", 2)) {
return RCC_AHB1Periph_GPIOF;
} else {
printf("AdcGetGpioRcc do not support %s GPIO\n", adc_gpio_def);
return RCC_AHB1Periph_GPIOA;
}
}
static void AdcInit(struct AdcHardwareDevice *adc_dev)
{
GPIO_InitTypeDef GPIO_InitStructure;
ADC_CommonInitTypeDef ADC_CommonInitStructure;
ADC_InitTypeDef ADC_InitStructure;
uint32_t RCC_AHB1Periph;
GPIO_TypeDef* GPIOx;
#ifdef BSP_USING_ADC1
if (0 == strncmp(adc_dev->haldev.dev_name, ADC1_DEVICE_NAME, NAME_NUM_MAX)) {
GPIOx = AdcGetGpioType(ADC1_GPIO_DEF);
RCC_AHB1Periph = AdcGetGpioRcc(ADC1_GPIO_DEF);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);//enable ADC1 clock
GPIO_InitStructure.GPIO_Pin = ADC1_GPIO;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOx, &GPIO_InitStructure);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC1, &ADC_InitStructure);
ADC_Cmd(ADC1, ENABLE);
}
#endif
#ifdef BSP_USING_ADC2
if (0 == strncmp(adc_dev->haldev.dev_name, ADC2_DEVICE_NAME, NAME_NUM_MAX)) {
GPIOx = AdcGetGpioType(ADC2_GPIO_DEF);
RCC_AHB1Periph = AdcGetGpioRcc(ADC2_GPIO_DEF);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);//enable ADC2 clock
GPIO_InitStructure.GPIO_Pin = ADC2_GPIO;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOx, &GPIO_InitStructure);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC2, &ADC_InitStructure);
ADC_Cmd(ADC2, ENABLE);
}
#endif
#ifdef BSP_USING_ADC3
if (0 == strncmp(adc_dev->haldev.dev_name, ADC3_DEVICE_NAME, NAME_NUM_MAX)) {
GPIOx = AdcGetGpioType(ADC3_GPIO_DEF);
RCC_AHB1Periph = AdcGetGpioRcc(ADC3_GPIO_DEF);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE);//enable ADC3 clock
GPIO_InitStructure.GPIO_Pin = ADC3_GPIO;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOx, &GPIO_InitStructure);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC3, &ADC_InitStructure);
ADC_Cmd(ADC3, ENABLE);
}
#endif
}
static uint16 GetAdcValue(ADC_TypeDef *ADCx, uint8 channel)
{
//set ADCx channel, rank, sampletime
ADC_RegularChannelConfig(ADCx, channel, 1, ADC_SampleTime_480Cycles);
ADC_SoftwareStartConv(ADCx);
while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC));
return ADC_GetConversionValue(ADCx);
}
static uint16 GetAdcAverageValue(ADC_TypeDef *ADCx, uint8 channel, uint8 times)
{
uint32 temp_val = 0;
int i;
for(i = 0;i < times;i ++) {
temp_val += GetAdcValue(ADCx, channel) & 0x0FFF;
KPrintf("GetAdcAverageValue val %u\n", GetAdcValue(ADCx, channel));
Stm32AdcUdelay(5000);
}
return temp_val / times;
}
static uint32 Stm32AdcOpen(void *dev)
{
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
AdcInit(adc_dev);
return EOK;
}
static uint32 Stm32AdcRead(void *dev, struct BusBlockReadParam *read_param)
{
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data;
uint16 adc_average_value = 0;
uint8 times = 20;
adc_average_value = GetAdcAverageValue(adc_cfg->ADCx, adc_cfg->adc_channel, times);
*(uint16 *)read_param->buffer = adc_average_value;
read_param->read_length = 2;
return read_param->read_length;
}
static uint32 Stm32AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
uint8 adc_channel;
struct AdcDriver *adc_drv = (struct AdcDriver *)drv;
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev;
struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data;
switch (configure_info->configure_cmd)
{
case OPE_CFG:
adc_cfg->adc_channel = *(uint8 *)configure_info->private_data;
if (adc_cfg->adc_channel > 18) {
KPrintf("Stm32AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel);
adc_cfg->adc_channel = 0;
ret = ERROR;
}
break;
default:
break;
}
return ret;
}
static const struct AdcDevDone dev_done =
{
Stm32AdcOpen,
NONE,
NONE,
Stm32AdcRead,
};
int Stm32HwAdcInit(void)
{
x_err_t ret = EOK;
#ifdef BSP_USING_ADC1
static struct AdcBus adc1_bus;
static struct AdcDriver adc1_drv;
static struct AdcHardwareDevice adc1_dev;
static struct Stm32HwAdc adc1_cfg;
adc1_drv.configure = Stm32AdcDrvConfigure;
ret = AdcBusInit(&adc1_bus, ADC1_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC1 bus init error %d\n", ret);
return ERROR;
}
ret = AdcDriverInit(&adc1_drv, ADC1_DRIVER_NAME);
if (ret != EOK) {
KPrintf("ADC1 driver init error %d\n", ret);
return ERROR;
}
ret = AdcDriverAttachToBus(ADC1_DRIVER_NAME, ADC1_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC1 driver attach error %d\n", ret);
return ERROR;
}
adc1_dev.adc_dev_done = &dev_done;
adc1_cfg.ADCx = ADC1;
adc1_cfg.adc_channel = 0;
ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME);
if (ret != EOK) {
KPrintf("ADC1 device register error %d\n", ret);
return ERROR;
}
ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC1_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC1 device register error %d\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_ADC2
static struct AdcBus adc2_bus;
static struct AdcDriver adc2_drv;
static struct AdcHardwareDevice adc2_dev;
static struct Stm32HwAdc adc2_cfg;
adc2_drv.configure = Stm32AdcDrvConfigure;
ret = AdcBusInit(&adc2_bus, ADC2_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC2 bus init error %d\n", ret);
return ERROR;
}
ret = AdcDriverInit(&adc2_drv, ADC2_DRIVER_NAME);
if (ret != EOK) {
KPrintf("ADC2 driver init error %d\n", ret);
return ERROR;
}
ret = AdcDriverAttachToBus(ADC2_DRIVER_NAME, ADC2_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC2 driver attach error %d\n", ret);
return ERROR;
}
adc2_dev.adc_dev_done = &dev_done;
adc2_cfg.ADCx = ADC2;
adc2_cfg.adc_channel = 0;
ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC2_DEVICE_NAME);
if (ret != EOK) {
KPrintf("ADC2 device register error %d\n", ret);
return ERROR;
}
ret = AdcDeviceAttachToBus(ADC2_DEVICE_NAME, ADC2_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC2 device register error %d\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_ADC3
static struct AdcBus adc3_bus;
static struct AdcDriver adc3_drv;
static struct AdcHardwareDevice adc3_dev;
static struct Stm32HwAdc adc3_cfg;
adc3_drv.configure = Stm32AdcDrvConfigure;
ret = AdcBusInit(&adc3_bus, ADC3_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC3 bus init error %d\n", ret);
return ERROR;
}
ret = AdcDriverInit(&adc3_drv, ADC3_DRIVER_NAME);
if (ret != EOK) {
KPrintf("ADC3 driver init error %d\n", ret);
return ERROR;
}
ret = AdcDriverAttachToBus(ADC3_DRIVER_NAME, ADC3_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC3 driver attach error %d\n", ret);
return ERROR;
}
adc3_dev.adc_dev_done = &dev_done;
adc3_cfg.ADCx = ADC3;
adc3_cfg.adc_channel = 0;
ret = AdcDeviceRegister(&adc3_dev, (void *)&adc3_cfg, ADC3_DEVICE_NAME);
if (ret != EOK) {
KPrintf("ADC3 device register error %d\n", ret);
return ERROR;
}
ret = AdcDeviceAttachToBus(ADC3_DEVICE_NAME, ADC3_BUS_NAME);
if (ret != EOK) {
KPrintf("ADC3 device register error %d\n", ret);
return ERROR;
}
#endif
}

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Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/adc/hardware_adc.c Normal file
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File diff suppressed because it is too large Load Diff

37
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/include/connect_adc.h Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_adc.h
* @brief define stm32f407-st-discovery adc function and struct
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#ifndef CONNECT_ADC_H
#define CONNECT_ADC_H
#include <device.h>
#include <hardware_adc.h>
#include <hardware_rcc.h>
#include <hardware_gpio.h>
struct Stm32HwAdc
{
ADC_TypeDef *ADCx;
uint8 adc_channel;
};
int Stm32HwAdcInit(void);
#endif

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/**
******************************************************************************
* @file stm32f4xx_adc.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/**
* @file: hardware_adc.h
* @brief: define hardware adc function
* @version: 1.1
* @author: AIIT XUOS Lab
* @date: 2021/12/28
*/
/*************************************************
File name: hardware_adc.h
Description: define hardware adc function
Others:
History:
1. Date: 2021-12-28
Author: AIIT XUOS Lab
Modification:
1. rename stm32f4xx_adc.h for XiUOS
*************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HARDWARE_ADC_H__
#define __HARDWARE_ADC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stm32f4xx.h>
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
This parameter can be a value of @ref ADC_resolution */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
is performed in Scan (multichannels)
or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
is performed in Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
enable the trigger of a regular group.
This parameter can be a value of
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
the start of conversion of a regular group.
This parameter can be a value of
@ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
is left or right. This parameter can be
a value of @ref ADC_data_align */
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
that will be done using the sequencer for
regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/**
* @brief ADC Common Init structure definition
*/
typedef struct
{
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
independent or multi mode.
This parameter can be a value of @ref ADC_Common_mode */
uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
to the ADC. The clock is common for all the ADCs.
This parameter can be a value of @ref ADC_Prescaler */
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
mode for multi ADC mode.
This parameter can be a value of
@ref ADC_Direct_memory_access_mode_for_multi_mode */
uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of
@ref ADC_delay_between_2_sampling_phases */
}ADC_CommonInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC2) || \
((PERIPH) == ADC3))
/** @defgroup ADC_Common_mode
* @{
*/
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
#define ADC_DualMode_Interl ((uint32_t)0x00000007)
#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
((MODE) == ADC_DualMode_InjecSimult) || \
((MODE) == ADC_DualMode_RegSimult) || \
((MODE) == ADC_DualMode_Interl) || \
((MODE) == ADC_DualMode_AlterTrig) || \
((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
((MODE) == ADC_TripleMode_InjecSimult) || \
((MODE) == ADC_TripleMode_RegSimult) || \
((MODE) == ADC_TripleMode_Interl) || \
((MODE) == ADC_TripleMode_AlterTrig))
/**
* @}
*/
/** @defgroup ADC_Prescaler
* @{
*/
#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
((PRESCALER) == ADC_Prescaler_Div4) || \
((PRESCALER) == ADC_Prescaler_Div6) || \
((PRESCALER) == ADC_Prescaler_Div8))
/**
* @}
*/
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
* @{
*/
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
((MODE) == ADC_DMAAccessMode_1) || \
((MODE) == ADC_DMAAccessMode_2) || \
((MODE) == ADC_DMAAccessMode_3))
/**
* @}
*/
/** @defgroup ADC_delay_between_2_sampling_phases
* @{
*/
#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
((DELAY) == ADC_TwoSamplingDelay_20Cycles))
/**
* @}
*/
/** @defgroup ADC_resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x00000000)
#define ADC_Resolution_10b ((uint32_t)0x01000000)
#define ADC_Resolution_8b ((uint32_t)0x02000000)
#define ADC_Resolution_6b ((uint32_t)0x03000000)
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_6b))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_18 ((uint8_t)0x12)
#if defined (STM32F40_41xxx)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || \
((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || \
((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || \
((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || \
((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || \
((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || \
((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || \
((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || \
((CHANNEL) == ADC_Channel_17) || \
((CHANNEL) == ADC_Channel_18))
/**
* @}
*/
/** @defgroup ADC_sampling_times
* @{
*/
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
((TIME) == ADC_SampleTime_15Cycles) || \
((TIME) == ADC_SampleTime_28Cycles) || \
((TIME) == ADC_SampleTime_56Cycles) || \
((TIME) == ADC_SampleTime_84Cycles) || \
((TIME) == ADC_SampleTime_112Cycles) || \
((TIME) == ADC_SampleTime_144Cycles) || \
((TIME) == ADC_SampleTime_480Cycles))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
/**
* @}
*/
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_EOC ((uint16_t)0x0205)
#define ADC_IT_AWD ((uint16_t)0x0106)
#define ADC_IT_JEOC ((uint16_t)0x0407)
#define ADC_IT_OVR ((uint16_t)0x201A)
#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
#define ADC_FLAG_OVR ((uint8_t)0x20)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || \
((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT) || \
((FLAG)== ADC_FLAG_OVR))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(void);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Analog Watchdog configuration functions ************************************/
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
/* Temperature Sensor, Vrefint and VBAT management functions ******************/
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
void ADC_VBATCmd(FunctionalState NewState);
/* Regular Channels Configuration functions ***********************************/
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetMultiModeConversionValue(void);
/* Regular Channels DMA Configuration functions *******************************/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
/* Injected channels Configuration functions **********************************/
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F4xx_ADC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/include/hardware_conf.h
View File

@ -80,7 +80,7 @@ Modification:
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
#define USE_FULL_ASSERT 1
// #define USE_FULL_ASSERT 1
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT

6
Ubiquitous/XiUOS/resources/Kconfig
View File

@ -151,3 +151,9 @@ if BSP_USING_WDT
bool "Using Watch Dog bus drivers"
default n
endif
if BSP_USING_ADC
config RESOURCES_ADC
bool "Using ADC bus drivers"
default n
endif

4
Ubiquitous/XiUOS/resources/Makefile
View File

@ -57,4 +57,8 @@ ifeq ($(CONFIG_RESOURCES_WDT),y)
SRC_DIR += watchdog
endif
ifeq ($(CONFIG_RESOURCES_ADC),y)
SRC_DIR += adc
endif
include $(KERNEL_ROOT)/compiler.mk

3
Ubiquitous/XiUOS/resources/adc/Makefile Normal file
View File

@ -0,0 +1,3 @@
SRC_FILES += dev_adc.c drv_adc.c bus_adc.c
include $(KERNEL_ROOT)/compiler.mk

122
Ubiquitous/XiUOS/resources/adc/bus_adc.c Normal file
View File

@ -0,0 +1,122 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You adc use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file bus_adc.c
* @brief register adc bus function using bus driver framework
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#include <bus_adc.h>
#include <dev_adc.h>
/*Register the ADC BUS*/
int AdcBusInit(struct AdcBus *adc_bus, const char *bus_name)
{
NULL_PARAM_CHECK(adc_bus);
NULL_PARAM_CHECK(bus_name);
x_err_t ret = EOK;
if (BUS_INSTALL != adc_bus->bus.bus_state) {
strncpy(adc_bus->bus.bus_name, bus_name, NAME_NUM_MAX);
adc_bus->bus.bus_type = TYPE_ADC_BUS;
adc_bus->bus.bus_state = BUS_INSTALL;
adc_bus->bus.private_data = adc_bus->private_data;
ret = BusRegister(&adc_bus->bus);
if (EOK != ret) {
KPrintf("AdcBusInit BusRegister error %u\n", ret);
return ret;
}
} else {
KPrintf("AdcBusInit BusRegister bus has been register state%u\n", adc_bus->bus.bus_state);
}
return ret;
}
/*Register the ADC Driver*/
int AdcDriverInit(struct AdcDriver *adc_driver, const char *driver_name)
{
NULL_PARAM_CHECK(adc_driver);
NULL_PARAM_CHECK(driver_name);
x_err_t ret = EOK;
if (DRV_INSTALL != adc_driver->driver.driver_state) {
adc_driver->driver.driver_type = TYPE_ADC_DRV;
adc_driver->driver.driver_state = DRV_INSTALL;
strncpy(adc_driver->driver.drv_name, driver_name, NAME_NUM_MAX);
adc_driver->driver.configure = adc_driver->configure;
adc_driver->driver.private_data = adc_driver->private_data;
ret = AdcDriverRegister(&adc_driver->driver);
if (EOK != ret) {
KPrintf("AdcDriverInit DriverRegister error %u\n", ret);
return ret;
}
} else {
KPrintf("AdcDriverInit DriverRegister driver has been register state%u\n", adc_driver->driver.driver_state);
}
return ret;
}
/*Release the ADC device*/
int AdcReleaseBus(struct AdcBus *adc_bus)
{
NULL_PARAM_CHECK(adc_bus);
return BusRelease(&adc_bus->bus);
}
/*Register the ADC Driver to the ADC BUS*/
int AdcDriverAttachToBus(const char *drv_name, const char *bus_name)
{
NULL_PARAM_CHECK(drv_name);
NULL_PARAM_CHECK(bus_name);
x_err_t ret = EOK;
struct Bus *bus;
struct Driver *driver;
bus = BusFind(bus_name);
if (NONE == bus) {
KPrintf("AdcDriverAttachToBus find adc bus error!name %s\n", bus_name);
return ERROR;
}
if (TYPE_ADC_BUS == bus->bus_type) {
driver = AdcDriverFind(drv_name, TYPE_ADC_DRV);
if (NONE == driver) {
KPrintf("AdcDriverAttachToBus find adc driver error!name %s\n", drv_name);
return ERROR;
}
if (TYPE_ADC_DRV == driver->driver_type) {
ret = DriverRegisterToBus(bus, driver);
if (EOK != ret) {
KPrintf("AdcDriverAttachToBus DriverRegisterToBus error %u\n", ret);
return ERROR;
}
}
}
return ret;
}

119
Ubiquitous/XiUOS/resources/adc/dev_adc.c Normal file
View File

@ -0,0 +1,119 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You adc use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file dev_adc.c
* @brief register adc dev function using bus driver framework
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#include <bus_adc.h>
#include <dev_adc.h>
static DoubleLinklistType adcdev_linklist;
/*Create the ADC device linklist*/
static void AdcDeviceLinkInit()
{
InitDoubleLinkList(&adcdev_linklist);
}
/*Find the register ADC device*/
HardwareDevType AdcDeviceFind(const char *dev_name, enum DevType dev_type)
{
NULL_PARAM_CHECK(dev_name);
struct HardwareDev *device = NONE;
DoubleLinklistType *node = NONE;
DoubleLinklistType *head = &adcdev_linklist;
for (node = head->node_next; node != head; node = node->node_next) {
device = SYS_DOUBLE_LINKLIST_ENTRY(node, struct HardwareDev, dev_link);
if ((!strcmp(device->dev_name, dev_name)) && (dev_type == device->dev_type)) {
return device;
}
}
KPrintf("AdcDeviceFind adcnot find the %s device.return NULL\n", dev_name);
return NONE;
}
/*Register the ADC device*/
int AdcDeviceRegister(struct AdcHardwareDevice *adc_device, void *adc_param, const char *device_name)
{
NULL_PARAM_CHECK(adc_device);
NULL_PARAM_CHECK(device_name);
x_err_t ret = EOK;
static x_bool dev_link_flag = RET_FALSE;
if (!dev_link_flag) {
AdcDeviceLinkInit();
dev_link_flag = RET_TRUE;
}
if (DEV_INSTALL != adc_device->haldev.dev_state) {
strncpy(adc_device->haldev.dev_name, device_name, NAME_NUM_MAX);
adc_device->haldev.dev_type = TYPE_ADC_DEV;
adc_device->haldev.dev_state = DEV_INSTALL;
adc_device->haldev.dev_done = (struct HalDevDone *)adc_device->adc_dev_done;
adc_device->haldev.private_data = adc_param;
DoubleLinkListInsertNodeAfter(&adcdev_linklist, &(adc_device->haldev.dev_link));
} else {
KPrintf("AdcDeviceRegister device has been register state%u\n", adc_device->haldev.dev_state);
}
return ret;
}
/*Register the ADC Device to the ADC BUS*/
int AdcDeviceAttachToBus(const char *dev_name, const char *bus_name)
{
NULL_PARAM_CHECK(dev_name);
NULL_PARAM_CHECK(bus_name);
x_err_t ret = EOK;
struct Bus *bus;
struct HardwareDev *device;
bus = BusFind(bus_name);
if (NONE == bus) {
KPrintf("AdcDeviceAttachToBus find adc bus error!name %s\n", bus_name);
return ERROR;
}
if (TYPE_ADC_BUS == bus->bus_type) {
device = AdcDeviceFind(dev_name, TYPE_ADC_DEV);
if (NONE == device) {
KPrintf("AdcDeviceAttachToBus find adc device error!name %s\n", dev_name);
return ERROR;
}
if (TYPE_ADC_DEV == device->dev_type) {
ret = DeviceRegisterToBus(bus, device);
if (EOK != ret) {
KPrintf("AdcDeviceAttachToBus DeviceRegisterToBus error %u\n", ret);
return ERROR;
}
}
}
return EOK;
}

69
Ubiquitous/XiUOS/resources/adc/drv_adc.c Normal file
View File

@ -0,0 +1,69 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file drv_adc.c
* @brief register adc drv function using bus driver framework
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#include <bus_adc.h>
#include <dev_adc.h>
static DoubleLinklistType adcdrv_linklist;
/*Create the driver linklist*/
static void AdcDrvLinkInit()
{
InitDoubleLinkList(&adcdrv_linklist);
}
/*Find the regiter driver*/
DriverType AdcDriverFind(const char *drv_name, enum DriverType_e drv_type)
{
NULL_PARAM_CHECK(drv_name);
struct Driver *driver = NONE;
DoubleLinklistType *node = NONE;
DoubleLinklistType *head = &adcdrv_linklist;
for (node = head->node_next; node != head; node = node->node_next) {
driver = SYS_DOUBLE_LINKLIST_ENTRY(node, struct Driver, driver_link);
if ((!strcmp(driver->drv_name, drv_name)) && (drv_type == driver->driver_type)) {
return driver;
}
}
KPrintf("AdcDriverFind cannot find the %s driver.return NULL\n", drv_name);
return NONE;
}
/*Register the Driver, manage with the double linklist*/
int AdcDriverRegister(struct Driver *driver)
{
NULL_PARAM_CHECK(driver);
x_err_t ret = EOK;
static x_bool driver_link_flag = RET_FALSE;
if (!driver_link_flag) {
AdcDrvLinkInit();
driver_link_flag = RET_TRUE;
}
DoubleLinkListInsertNodeAfter(&adcdrv_linklist, &(driver->driver_link));
return ret;
}

3
Ubiquitous/XiUOS/resources/include/bus.h
View File

@ -52,6 +52,7 @@ enum BusType_e
TYPE_PIN_BUS,
TYPE_RTC_BUS,
TYPE_SERIAL_BUS,
TYPE_ADC_BUS,
TYPE_BUS_END,
};
@ -76,6 +77,7 @@ enum DevType
TYPE_PIN_DEV,
TYPE_RTC_DEV,
TYPE_SERIAL_DEV,
TYPE_ADC_DEV,
TYPE_DEV_END,
};
@ -100,6 +102,7 @@ enum DriverType_e
TYPE_PIN_DRV,
TYPE_RTC_DRV,
TYPE_SERIAL_DRV,
TYPE_ADC_DRV,
TYPE_DRV_END,
};

67
Ubiquitous/XiUOS/resources/include/bus_adc.h Normal file
View File

@ -0,0 +1,67 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You adc use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file bus_adc.h
* @brief define adc bus and drv function using bus driver framework
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#ifndef BUS_ADC_H
#define BUS_ADC_H
#include <bus.h>
#ifdef __cplusplus
extern "C" {
#endif
struct AdcDriver
{
struct Driver driver;
uint32 (*configure) (void *drv, struct BusConfigureInfo *configure_info);
void *private_data;
};
struct AdcBus
{
struct Bus bus;
void *private_data;
};
/*Register the ADC bus*/
int AdcBusInit(struct AdcBus *adc_bus, const char *bus_name);
/*Register the ADC driver*/
int AdcDriverInit(struct AdcDriver *adc_driver, const char *driver_name);
/*Release the ADC device*/
int AdcReleaseBus(struct AdcBus *adc_bus);
/*Register the ADC driver to the ADC bus*/
int AdcDriverAttachToBus(const char *drv_name, const char *bus_name);
/*Register the driver, manage with the double linklist*/
int AdcDriverRegister(struct Driver *driver);
/*Find the register driver*/
DriverType AdcDriverFind(const char *drv_name, enum DriverType_e drv_type);
#ifdef __cplusplus
}
#endif
#endif

61
Ubiquitous/XiUOS/resources/include/dev_adc.h Normal file
View File

@ -0,0 +1,61 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file dev_adc.h
* @brief define adc dev function using bus driver framework
* @version 1.1
* @author AIIT XUOS Lab
* @date 2021-12-28
*/
#ifndef DEV_ADC_H
#define DEV_ADC_H
#include <bus.h>
#ifdef __cplusplus
extern "C" {
#endif
struct AdcHardwareDevice;
struct AdcDevDone
{
uint32 (*open) (void *dev);
uint32 (*close) (void *dev);
uint32 (*write) (void *dev,struct BusBlockWriteParam *write_param);
uint32 (*read) (void *dev, struct BusBlockReadParam *read_param);
};
struct AdcHardwareDevice
{
struct HardwareDev haldev;
const struct AdcDevDone *adc_dev_done;
void *private_data;
};
/*Register the ADC device*/
int AdcDeviceRegister(struct AdcHardwareDevice *adc_device, void *adc_param, const char *device_name);
/*Register the ADC device to the ADC bus*/
int AdcDeviceAttachToBus(const char *dev_name, const char *bus_name);
/*Find the register ADC device*/
HardwareDevType AdcDeviceFind(const char *dev_name, enum DevType dev_type);
#ifdef __cplusplus
}
#endif
#endif

5
Ubiquitous/XiUOS/resources/include/device.h
View File

@ -94,4 +94,9 @@ HardwareDevType ObtainConsole(void);
#include <dev_hwtimer.h>
#endif
#ifdef RESOURCES_ADC
#include <bus_adc.h>
#include <dev_adc.h>
#endif
#endif

1
Ubiquitous/XiUOS/tool/shell/letter-shell/cmd.c
View File

@ -382,6 +382,7 @@ static char *const bus_type_str[] =
"PIN_BUS",
"RTC_BUS",
"SERIAL_BUS",
"ADC_BUS",
"Unknown"
};