forked from xuos/xiuos
TODO: Support armv8
This commit is contained in:
liuqh
@@ -28,9 +28,9 @@ Modification:
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*************************************************/
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#include "core.h"
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#include "memlayout.h"
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#include "mmu.h"
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#include "mmio_access.h"
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#include "mmu.h"
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#include "registers.h"
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#include <stdint.h>
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#include <string.h>
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@@ -38,52 +38,117 @@ Modification:
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extern uint64_t kernel_data_end[];
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extern uint64_t kernel_data_begin[];
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#define NR_PDE_ENTRIES 512
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#define L1_TYPE_SEC (2 << 0)
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#define L1_SECT_DEV ((0B00) << 2) // Device memory
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#define L1_SECT_AP0 (1 << 6) // Data Access Permissions
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uint64_t boot_pgdir[NR_PDE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 };
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#define NR_PDE_ENTRIES (1 << 9)
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#define L2_TYPE_TAB 2
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#define L2_PTE_VALID 1
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#define L3_TYPE_TAB 2
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#define L3_PTE_VALID 1
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#define L4_TYPE_PAGE (3 << 0)
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#define L4_PTE_DEV ((0b00) << 2) // Device memory
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#define L4_PTE_AF (1 << 10) // Data Access Permissions
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#define IDX_MASK (0b111111111)
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#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
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uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
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// uint64_t boot_lowspace_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x4000))) = { 0 };
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// uint64_t boot_highspace_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x4000))) = { 0 };
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uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
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// uint64_t boot_identical_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x4000))) = { 0 };
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uint64_t boot_virt_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
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// uint64_t boot_identical_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x4000))) = { 0 };
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uint64_t boot_virt_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
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// uint64_t boot_mem_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
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static void build_boot_pgdir()
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{
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uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
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// dev mem
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uint64_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SZ) >> LEVEL3_PDE_SHIFT;
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for (uint64_t i = DEV_PHYMEM_BASE >> LEVEL3_PDE_SHIFT; i < dev_mem_end_idx; i++) {
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boot_pgdir[i] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0;
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boot_pgdir[MMIO_P2V_WO(i << LEVEL3_PDE_SHIFT) >> LEVEL3_PDE_SHIFT] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0;
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boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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// boot_lowspace_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_identical_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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// boot_highspace_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_identical_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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uint64_t cur_mem_paddr = (uint64_t)DEV_PHYMEM_BASE & ((uint64_t)IDX_MASK << (uint64_t)LEVEL2_PDE_SHIFT);
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for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
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boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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// boot_identical_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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// boot_virt_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
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// boot_dev_l4pgdirs[i][j] = dev_phy_mem_base | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF;
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boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF;
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// dev_phy_mem_base += PAGE_SIZE;
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cur_mem_paddr += PAGE_SIZE;
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}
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}
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// identical mem
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uint64_t idn_mem_start_idx = PHY_MEM_BASE >> LEVEL3_PDE_SHIFT;
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uint64_t idn_mem_end_idx = PHY_MEM_STOP >> LEVEL3_PDE_SHIFT;
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for (uint64_t i = idn_mem_start_idx; i < idn_mem_end_idx; i++) {
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boot_pgdir[i] = i << LEVEL3_PDE_SHIFT | L1_TYPE_SEC | L1_SECT_AP0;
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// uint64_t phy_mem_base = PHY_MEM_BASE;
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boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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// boot_lowspace_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_identical_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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// boot_highspace_l2pgdir[(KERN_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_identical_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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cur_mem_paddr = (uint64_t)PHY_MEM_BASE & ((uint64_t)IDX_MASK << (uint64_t)LEVEL2_PDE_SHIFT);
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for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
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boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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// boot_identical_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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// boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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// boot_virt_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
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boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_AF;
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cur_mem_paddr += PAGE_SIZE;
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}
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}
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// kern mem
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uint64_t kern_mem_start_idx = KERN_MEM_BASE >> LEVEL3_PDE_SHIFT;
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uint64_t kern_mem_end_idx = (KERN_MEM_BASE + (PHY_MEM_STOP - PHY_MEM_BASE)) >> LEVEL3_PDE_SHIFT;
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for (uint64_t i = kern_mem_start_idx; i < kern_mem_end_idx; i++) {
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boot_pgdir[i] = V2P(i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_AP0;
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}
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// dev mem
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// uint64_t dev_mem_end_pgd = PGD_INDEX(DEV_PHYMEM_BASE + DEV_MEM_SZ);
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// for (uint64_t i = PGD_INDEX(DEV_PHYMEM_BASE); i < dev_mem_end_idx; i++) {
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// boot_pgdir[i] = (uint64_t)boot_dev_l3dir[used_boot_dev_l3dir_idx] | L3_TYPE_SEC | L3_SECT_DEV | L3_SECT_AP0;
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// boot_pgdir[PGD_INDEX(MMIO_P2V_WO(PGD_INDEX_TO_PA(i)))] = (uint64_t)boot_dev_l3dir[used_boot_dev_l3dir_idx] | L3_TYPE_SEC | L3_SECT_DEV | L3_SECT_AP0;
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// used_boot_dev_l3dir_idx++;
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// for (int64_t j = 0; j < 0b111111111; j++) {
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// boot_dev_l3dir[i][j] = (uint64_t)boot_dev_l4dir[used_boot_dev_l4dir_idx] | ();
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// // uint64_t dev_mem_end_pmd = PMD_INDEX(DEV_PHYMEM_BASE + DEV_MEM_SZ);
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// // for (uint64_t j = PMD_INDEX(DEV_PHYMEM_BASE); j < dev_mem_end_pmd; j++) {
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// // boot_pmd[j] = PGD_INDEX_TO_PA(j) | L4_TYPE_SEC | L4_SECT_DEV | L4_SECT_AP0;
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// // boot_pmd[PGD_INDEX(MMIO_P2V_WO(PGD_INDEX_TO_PA(j)))] = PGD_INDEX_TO_PA(j) | L4_TYPE_SEC | L4_SECT_DEV | L4_SECT_AP0;
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// // }
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// for (uint64_t k = 0; k < 0b111111111; k++) {
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// boot_dev_l4dir[j][k] = DEV_PHYMEM_BASE
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// }
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// }
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// }
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}
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static void load_boot_pgdir()
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{
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uint64_t val;
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// DACR_W(0x55555555); // set domain access control as client
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// TTBCR_W(0x0);
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// TTBR0_W((uint64_t)boot_pgdir);
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TTBR0_W(0x0);
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TTBR1_W((uint64_t)boot_pgdir);
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// TTBR0_W((uintptr_t)boot_lowspace_l2pgdir);
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// TTBR1_W((uintptr_t)boot_highspace_l2pgdir);
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TTBR0_W((uintptr_t)boot_l2pgdir);
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TTBR1_W(0);
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TCR_W(TCR_VALUE);
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MAIR_W((MT_DEVICE_nGnRnE << (8 * AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC << (8 * AI_NORMAL_NC_IDX)));
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// Enable paging using read/modify/write
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SCTLR_R(val);
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val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
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val |= (1 << 1); // Alignment check enable
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val |= (1 << 2); // Cacheability control, for data caching.
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val |= (1 << 12); // Instruction access Cacheability control
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val |= (1 << 19); // forced to XN for the EL1&0 translation regime.
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SCTLR_W(val);
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@@ -101,9 +166,9 @@ void bootmain()
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load_boot_pgdir();
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__asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_MEM_BASE - PHY_MEM_BASE));
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if (!_bss_inited) {
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memset(&kernel_data_begin, 0x00, (uint64_t)kernel_data_end - (uint64_t)kernel_data_begin);
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memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
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uintptr_t kde = (uintptr_t)kernel_data_end;
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_bss_inited = true;
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}
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main();
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}
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@@ -33,15 +33,18 @@ Modification:
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#include "memlayout.h"
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#include "page_table_entry.h"
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#define TCR_IPS (0 << 32)
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// #define TCR_SH1_INNER (0b11 << 28)
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// #define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24))
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// #define TCR_SH0_INNER (0b11 << 12)
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// #define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8))
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#define TCR_IPS (0 << 0)
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#define TCR_TG1_4K (0b10 << 30)
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#define TCR_SH1_INNER (0b11 << 28)
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#define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24))
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#define TCR_TOSZ (0b11001 << 0)
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#define TCR_T1SZ (0b11001 << 16)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_SH0_INNER (0b11 << 12)
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#define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8))
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#define TCR_VALUE \
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(TCR_IPS | TCR_TG1_4K | TCR_SH1_INNER | TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC | TCR_TG0_4K | TCR_SH0_INNER | TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC)
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(TCR_IPS | TCR_TG1_4K | TCR_TG0_4K | TCR_TOSZ | TCR_T1SZ)
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enum AccessPermission {
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AccessPermission_NoAccess = 0,
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@@ -75,18 +78,13 @@ Read and write mmu pagetable register base addr
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#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val))
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/*
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TTBCR is used for choosing TTBR0 and TTBR1 as page table register.
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When TTBCR is set to 0, TTBR0 is selected by default.
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Translation Control Register（TCR）
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*/
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// #define TTBCR_R(val) __asm__ volatile("mrs %0, ttbcr_el1" : "=r"(val))
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// #define TTBCR_W(val) __asm__ volatile("msr ttbcr_el1, %0" ::"r"(val))
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#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val))
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#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val))
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/*
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DACR registers are used to control memory privilage.
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The domain value is usually 0x01. The memory privilage will be controled by pte AP/APX
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*/
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// #define DACR_R(val) __asm__ volatile("mrs %0, dacr_el1" : "=r"(val))
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// #define DACR_W(val) __asm__ volatile("msr dacr_el1, %0" :: "r"(val))
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#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val))
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#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val))
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/*
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Flush TLB when loading a new page table.
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@@ -34,11 +34,10 @@ Modification:
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#define ARCH_BIT 64
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/* A72 physical memory layout */
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#define PHY_MEM_BASE (0x00000000)
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#define PHY_USER_FREEMEM_BASE (0x30000000)
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#define PHY_USER_FREEMEM_TOP (0x80000000)
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#define PHY_MEM_STOP (0x80000000)
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#define PHY_MEM_BASE (0x0000000040000000ULL)
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#define PHY_USER_FREEMEM_BASE (0x0000000044000000ULL)
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#define PHY_USER_FREEMEM_TOP (0x0000000048000000ULL)
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#define PHY_MEM_STOP (0x0000000048000000ULL)
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/* PTE-PAGE_SIZE */
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#define LEVEL4_PTE_SHIFT 12
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@@ -48,65 +47,42 @@ Modification:
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#define LEVEL3_PDE_SHIFT 21
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#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT)
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#define LEVEL2_PTE_SHIFT 30
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#define LEVEL2_PDE_SHIFT 30
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#define LEVEL2_PDE_SIZE (1 << LEVEL2_PDE_SHIFT)
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#define LEVEL1_PTE_SHIFT 39
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#define NUM_LEVEL3_PDE (1 << (ARCH_BIT - LEVEL3_PDE_SHIFT)) // how many PTE in a PT
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#define NUM_LEVEL2_PDE (1 << (LEVEL1_PTE_SHIFT - LEVEL2_PDE_SHIFT))
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#define NUM_LEVEL3_PDE (1 << (LEVEL2_PDE_SHIFT - LEVEL3_PDE_SHIFT)) // how many PDE in a PT
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#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT
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#define NUM_TOPLEVEL_PDE NUM_LEVEL3_PDE
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#define NUM_TOPLEVEL_PDE NUM_LEVEL2_PDE
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#define PAGE_SIZE LEVEL4_PTE_SIZE
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#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
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/* Deivce memory layout */
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#define DEV_PHYMEM_BASE (0x0000000000000000)
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#define DEV_VRTMEM_BASE (0x0000ffffffffffff)
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#define DEV_MEM_SZ (0x10000000)
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#define DEV_PHYMEM_BASE (0x0000000000000000ULL)
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#define DEV_VRTMEM_BASE (0x0000004000000000ULL)
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#define DEV_MEM_SZ (0x0000000010000000ULL)
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/* User memory layout */
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#define USER_STACK_SIZE PAGE_SIZE
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#define USER_MEM_BASE (0x0000000000000000)
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#define USER_MEM_BASE (0x0000000000000000ULL)
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#define USER_MEM_TOP DEV_VRTMEM_BASE
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#define USER_IPC_SPACE_BASE (0x7000000000000000)
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#define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
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#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL)
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#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
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/* Kernel memory layout */
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#define KERN_MEM_BASE (0xffff000000000000ULL) // First kernel virtual address
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#define KERN_MEM_BASE (0x0000006040000000ULL) // First kernel virtual address
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#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
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#define V2P(a) (((uint64_t)(a)) - KERN_MEM_BASE)
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#define P2V(a) ((void *)(((char *)(a)) + KERN_MEM_BASE))
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#define V2P(a) (((uint64_t)(a)) - KERN_OFFSET)
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#define P2V(a) ((void *)(((char *)(a)) + KERN_OFFSET))
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#define V2P_WO(x) ((x) - KERN_MEM_BASE) // same as V2P, but without casts
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#define P2V_WO(x) ((x) + KERN_MEM_BASE) // same as P2V, but without casts
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// one beyond the highest possible virtual address.
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#define MAXVA (KERN_MEM_BASE + (1ULL<<38))
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// qemu puts UART registers here in physical memory.
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#define UART0 (KERN_MEM_BASE + 0x09000000L)
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#define UART0_IRQ 33
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// virtio mmio interface
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#define VIRTIO0 (KERN_MEM_BASE + 0x0a000000L)
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#define VIRTIO0_IRQ 48
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#define V2P_WO(x) ((x) - KERN_OFFSET) // same as V2P, but without casts
|
||||
#define P2V_WO(x) ((x) + KERN_OFFSET) // same as P2V, but without casts
|
||||
|
||||
#define TIMER0_IRQ 27
|
||||
|
||||
// interrupt controller GICv3
|
||||
#define GICV3 (KERN_MEM_BASE + 0x08000000L)
|
||||
#define GICV3_REDIST (KERN_MEM_BASE + 0x080a0000L)
|
||||
|
||||
// map kernel stacks beneath the trampoline,
|
||||
// each surrounded by invalid guard pages.
|
||||
#define PGSIZE 4096 // bytes per page
|
||||
#define KSTACK(p) (MAXVA - ((p)+1) * 2*PGSIZE)
|
||||
|
||||
|
||||
// extract the three 9-bit page table indices from a virtual address.
|
||||
#define PXMASK 0x1FF // 9 bits
|
||||
#define PXSHIFT(level) (39-(level)*9)
|
||||
#define PX(level, va) ((((uint64)(va)) >> PXSHIFT(level)) & PXMASK)
|
||||
|
||||
// clang-format on
|
||||
@@ -29,21 +29,29 @@ Modification:
|
||||
#include "mmu.h"
|
||||
#include "mmu_common.h"
|
||||
|
||||
// void GetUsrPteAttr(uintptr_t* attr)
|
||||
// {
|
||||
// static char init = 0;
|
||||
// static PageTblEntry usr_pte_attr;
|
||||
// if (init == 0) {
|
||||
// init = 1;
|
||||
|
||||
// usr_pte_attr.entry = 0;
|
||||
// usr_pte_attr.desc_type = PAGE_4K;
|
||||
// usr_pte_attr.B = 1;
|
||||
// usr_pte_attr.C = 1;
|
||||
// usr_pte_attr.S = 1;
|
||||
// usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
|
||||
// }
|
||||
// *attr = usr_pte_attr.entry;
|
||||
// }
|
||||
|
||||
void GetUsrPteAttr(uintptr_t* attr)
|
||||
{
|
||||
// static char init = 0;
|
||||
// static PageTblEntry usr_pte_attr;
|
||||
// if (init == 0) {
|
||||
// init = 1;
|
||||
|
||||
// usr_pte_attr.entry = 0;
|
||||
// usr_pte_attr.desc_type = PAGE_4K;
|
||||
// usr_pte_attr.B = 1;
|
||||
// usr_pte_attr.C = 1;
|
||||
// usr_pte_attr.S = 1;
|
||||
// usr_pte_attr.AP1_0 = AccessPermission_KernelUser;
|
||||
// }
|
||||
// *attr = usr_pte_attr.entry;
|
||||
static char init = 0;
|
||||
if (init == 0) {
|
||||
init = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void GetUsrDevPteAttr(uintptr_t* attr)
|
||||
|
||||
Reference in New Issue
Block a user