developer
/
xiuos
forked from xuos/xiuos
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

1.feat support GPIO driver for ok1052-c and xidatong board;2.fix ok1052-c board H file description

This commit is contained in:
Liu_Weichao 2022-03-17 14:10:21 +08:00
parent 9ffd8fcbbb
commit 0e0564f377
44 changed files with 1307 additions and 2370 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Ubiquitous/XiZi/board/ok1052-c/board.c
View File

@ -31,7 +31,7 @@ Modification:
#include "pin_mux.h"
#ifdef BSP_USING_SDIO
extern int Imrt1052HwSdioInit(void);
extern int Imxrt1052HwSdioInit(void);
#endif
#ifdef BSP_USING_SEMC
@ -66,6 +66,9 @@ int MountSDCard(void)
#include "fsl_gpio.h"
#include "fsl_lpuart.h"
#ifdef BSP_USING_GPIO
#include <connect_gpio.h>
#endif
#ifdef BSP_USING_LWIP
#include <connect_ethernet.h>
#endif
@ -645,6 +648,10 @@ void InitBoardHardware()
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
#endif
#ifdef BSP_USING_GPIO
Imxrt1052HwGpioInit();
#endif
#ifdef BSP_USING_LPUART
imxrt_uart_pins_init();
#endif
@ -671,25 +678,25 @@ void InitBoardHardware()
#endif
#ifdef BSP_USING_LPUART
Imrt1052HwUartInit();
Imxrt1052HwUartInit();
#endif
#ifdef BSP_USING_ADC
Imrt1052HwAdcInit();
Imxrt1052HwAdcInit();
#endif
#ifdef BSP_USING_SPI
Imrt1052HwSpiInit();
Imxrt1052HwSpiInit();
#endif
#ifdef BSP_USING_RTC
Imrt1052HwRtcInit();
Imxrt1052HwRtcInit();
#endif
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
#ifdef BSP_USING_SDIO
Imrt1052HwSdioInit();
Imxrt1052HwSdioInit();
#endif
}

28
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/adc/connect_adc.c
View File

@ -78,7 +78,7 @@ void ADC2_IRQHandler(int vector, void *param)
DECLARE_HW_IRQ(ADC2_IRQn, ADC2_IRQHandler, NONE);
uint32 Imrt1052AdcOpen(void *dev)
uint32 Imxrt1052AdcOpen(void *dev)
{
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
adc_config_t adc_cfg;
@ -126,12 +126,12 @@ uint32 Imrt1052AdcOpen(void *dev)
return EOK;
}
uint32 Imrt1052AdcClose(void *dev)
uint32 Imxrt1052AdcClose(void *dev)
{
return EOK;
}
uint32 Imrt1052AdcRead(void *dev, struct BusBlockReadParam *read_param)
uint32 Imxrt1052AdcRead(void *dev, struct BusBlockReadParam *read_param)
{
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
adc_channel_config_t ch_cfg;
@ -169,7 +169,7 @@ uint32 Imrt1052AdcRead(void *dev, struct BusBlockReadParam *read_param)
return adc1_val;
}
static uint32 Imrt1052AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
static uint32 Imxrt1052AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
@ -179,14 +179,14 @@ static uint32 Imrt1052AdcDrvConfigure(void *drv, struct BusConfigureInfo *config
struct AdcDriver *adc_drv = (struct AdcDriver *)drv;
struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev;
struct Imrt1052HwAdc *adc_cfg = (struct Imrt1052HwAdc *)adc_dev->haldev.private_data;
struct Imxrt1052HwAdc *adc_cfg = (struct Imxrt1052HwAdc *)adc_dev->haldev.private_data;
switch (configure_info->configure_cmd)
{
case OPE_CFG:
adc_cfg->adc_channel = *(uint8 *)configure_info->private_data;
if (adc_cfg->adc_channel > 18) {
KPrintf("Imrt1052AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel);
KPrintf("Imxrt1052AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel);
adc_cfg->adc_channel = 0;
ret = ERROR;
}
@ -200,13 +200,13 @@ static uint32 Imrt1052AdcDrvConfigure(void *drv, struct BusConfigureInfo *config
static const struct AdcDevDone dev_done =
{
Imrt1052AdcOpen,
Imrt1052AdcClose,
Imxrt1052AdcOpen,
Imxrt1052AdcClose,
NONE,
Imrt1052AdcRead,
Imxrt1052AdcRead,
};
int Imrt1052HwAdcInit(void)
int Imxrt1052HwAdcInit(void)
{
x_err_t ret = EOK;
@ -214,9 +214,9 @@ int Imrt1052HwAdcInit(void)
static struct AdcBus adc1_bus;
static struct AdcDriver adc1_drv;
static struct AdcHardwareDevice adc1_dev;
static struct Imrt1052HwAdc adc1_cfg;
static struct Imxrt1052HwAdc adc1_cfg;
adc1_drv.configure = Imrt1052AdcDrvConfigure;
adc1_drv.configure = Imxrt1052AdcDrvConfigure;
ret = AdcBusInit(&adc1_bus, ADC_BUS_NAME_1);
if (ret != EOK) {
@ -254,9 +254,9 @@ int Imrt1052HwAdcInit(void)
static struct AdcBus adc2_bus;
static struct AdcDriver adc2_drv;
static struct AdcHardwareDevice adc2_dev;
static struct Imrt1052HwAdc adc2_cfg;
static struct Imxrt1052HwAdc adc2_cfg;
adc2_drv.configure = Imrt1052AdcDrvConfigure;
adc2_drv.configure = Imxrt1052AdcDrvConfigure;
ret = AdcBusInit(&adc2_bus, ADC_BUS_NAME_2);
if (ret != EOK) {

765
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c
View File

@ -1,39 +1,35 @@
/*
* Copyright (c) 2020 RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 balanceTWK first version
* 2019-04-23 WillianChan Fix GPIO serial number disorder
*/
* Date Author Notes
* 2018-4-30 misonyo the first version.
*/
/**
* @file connect_gpio.c
* @brief support gpio function using bus driver framework
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021-04-25
* @date 2022-03-16
*/
/*************************************************
File name: connect_gpio.c
Description: support gpio configure and register to bus framework
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c for references
Description: support gpio configure and register to bus framework
Others: take RT-Thread v4.0.2/bsp/imxrt/libraries/drivers/drv_gpio.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2021-04-25
1. Date: 2022-03-16
Author: AIIT XUOS Lab
Modification: add bus driver framework support for gpio
*************************************************/
#include <device.h>
#include <board.h>
#define STM32_PIN_NUMBERS 100 // [48, 64, 100, 144]
#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
#include <connect_gpio.h>
#include <fsl_gpio.h>
#include <fsl_iomuxc.h>
struct PinIndex
{
@ -50,81 +46,196 @@ struct PinIrq
uint32 exti_line;
};
static const struct PinIndex pins[] = {
{0, GPIO1, 0},
{1, GPIO1, 1},
{2, GPIO1, 2},
{3, GPIO1, 3},
{4, GPIO1, 4},
{5, GPIO1, 5},
{6, GPIO1, 6},
{7, GPIO1, 7},
{8, GPIO1, 8},
{9, GPIO1, 9},
{10, GPIO1, 10},
{11, GPIO1, 11},
{12, GPIO1, 12},
{13, GPIO1, 13},
{14, GPIO1, 14},
{15, GPIO1, 15},
{16, GPIO2, 0},
{17, GPIO2, 1},
{18, GPIO2, 2},
{19, GPIO2, 3},
{20, GPIO2, 4},
{21, GPIO2, 5},
{22, GPIO2, 6},
{23, GPIO2, 7},
{24, GPIO2, 8},
{25, GPIO2, 9},
{26, GPIO2, 10},
{27, GPIO2, 11},
{28, GPIO2, 12},
{29, GPIO2, 13},
{30, GPIO2, 14},
{31, GPIO2, 15},
{32, GPIO3, 0},
{33, GPIO3, 1},
{34, GPIO3, 2},
{35, GPIO3, 3},
{36, GPIO3, 4},
{37, GPIO3, 5},
{38, GPIO3, 6},
{39, GPIO3, 7},
{40, GPIO3, 8},
{41, GPIO3, 9},
{42, GPIO3, 10},
{43, GPIO3, 11},
{44, GPIO3, 12},
{45, GPIO3, 13},
{46, GPIO3, 14},
{47, GPIO3, 15},
{-1, 0u, -1}
struct PinMask
{
GPIO_Type *gpio;
uint32 valid_mask;
};
struct PinIrqHdr pin_irq_hdr_tab[] = {};
const struct PinIndex *GetPin(uint8_t pin)
static const IRQn_Type irq_tab[10] =
{
const struct PinIndex *index;
GPIO1_Combined_0_15_IRQn,
GPIO1_Combined_16_31_IRQn,
GPIO2_Combined_0_15_IRQn,
GPIO2_Combined_16_31_IRQn,
GPIO3_Combined_0_15_IRQn,
GPIO3_Combined_16_31_IRQn,
GPIO4_Combined_0_15_IRQn,
GPIO4_Combined_16_31_IRQn,
GPIO5_Combined_0_15_IRQn,
GPIO5_Combined_16_31_IRQn
};
if (pin < ITEM_NUM(pins)){
index = &pins[pin];
if (index->index == -1)
index = NONE;
}
else{
index = NONE;
const struct PinMask pin_mask[] =
{
{GPIO1, 0xFFFFFFFF}, /* GPIO1 */
{GPIO2, 0xFFFFFFFF}, /* GPIO2 */
{GPIO3, 0x0FFFFFFF}, /* GPIO3,28~31 not supported */
{GPIO4, 0xFFFFFFFF}, /* GPIO4 */
{GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
};
struct PinIrqHdr pin_irq_hdr_tab[] =
{
/* GPIO1 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO2 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO3 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO4 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO5 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
};
static int GetPin(struct PinIndex *pin_index, uint8_t pin)
{
pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5
pin_index->pin = pin & 31;//each GPIOx support 32 io
if ((pin_index->index > 4) || ((pin_mask[pin_index->index].valid_mask & (1 << pin_index->pin)) == 0)) {
KPrintf("GetPin unsupport pin index %u pin %u\n", pin_index->index, pin_index->pin);
return -1;
}
return index;
pin_index->gpio = pin_mask[pin_index->index].gpio;
return 0;
}
static int32 GpioConfigMode(int mode, const struct PinIndex* index)
static int32 GpioConfigMode(int mode, struct PinIndex *index)
{
gpio_pin_config_t gpio_config;
NULL_PARAM_CHECK(index);
gpio_config.outputLogic = 0;
switch (mode)
{
case GPIO_CFG_OUTPUT:
@ -137,14 +248,15 @@ static int32 GpioConfigMode(int mode, const struct PinIndex* index)
break;
case GPIO_CFG_INPUT_PULLUP:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntRisingEdge;
gpio_config.interruptMode = kGPIO_NoIntmode;
break;
case GPIO_CFG_INPUT_PULLDOWN:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntFallingEdge;
gpio_config.interruptMode = kGPIO_NoIntmode;
break;
case GPIO_CFG_OUTPUT_OD:
gpio_config.direction = kGPIO_DigitalOutput;
gpio_config.interruptMode = kGPIO_NoIntmode;
break;
default:
break;
@ -153,97 +265,33 @@ static int32 GpioConfigMode(int mode, const struct PinIndex* index)
return EOK;
}
static __inline int32 Bit2Bitnum(uint32 bit)
{
for (int i = 0; i < 32; i++){
if ((1UL << i) == bit){
return i;
}
}
return -1;
}
static __inline int32 Bitno2Bit(uint32 bitno)
{
if (bitno <= 32) {
return 1UL << bitno;
}
else {
return 0;
}
}
static const struct PinIrq *GetPinIrq(uint16_t pin)
{
static struct PinIrq irq;
const struct PinIndex* index = GetPin(pin);
if (index == NONE) {
return NONE;
}
irq.exti_line = index->pin;
irq.pin_source = Bit2Bitnum(index->pin);
irq.port_source = ((uint32_t)index->gpio - GPIO1_BASE) / (GPIO2_BASE - GPIO1_BASE);
switch (irq.pin_source)
{
case 0 :
irq.irq_exti_channel = GPIO1_INT0_IRQn;
break;
case 1 :
irq.irq_exti_channel = GPIO1_INT1_IRQn;
break;
case 2 :
irq.irq_exti_channel = GPIO1_INT2_IRQn;
break;
case 3 :
irq.irq_exti_channel = GPIO1_INT3_IRQn;
break;
case 4 :
irq.irq_exti_channel = GPIO1_INT4_IRQn;
break;
case 5 :
irq.irq_exti_channel = GPIO1_INT5_IRQn;
break;
case 6 :
irq.irq_exti_channel = GPIO1_INT6_IRQn;
break;
case 7 :
irq.irq_exti_channel = GPIO1_INT7_IRQn;
break;
default :
return NONE;
}
return &irq;
};
static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
struct PinIndex pin_index;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args
if (pin_irq_hdr_tab[pin].pin == pin &&
pin_irq_hdr_tab[pin].hdr == hdr &&
pin_irq_hdr_tab[pin].mode == mode &&
pin_irq_hdr_tab[pin].args == args
)
{
CriticalAreaUnLock(level);
return EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1) {
if (pin_irq_hdr_tab[pin].pin != -1) {
CriticalAreaUnLock(level);
return -EDEV_BUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
pin_irq_hdr_tab[pin].pin = pin;
pin_irq_hdr_tab[pin].hdr = hdr;
pin_irq_hdr_tab[pin].mode = mode;
pin_irq_hdr_tab[pin].args = args;
CriticalAreaUnLock(level);
return EOK;
@ -251,23 +299,21 @@ static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), voi
static uint32 GpioIrqFree(int32 pin)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
struct PinIndex pin_index;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1){
if (pin_irq_hdr_tab[pin].pin == -1){
CriticalAreaUnLock(level);
return EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = NONE;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = NONE;
pin_irq_hdr_tab[pin].pin = -1;
pin_irq_hdr_tab[pin].hdr = NONE;
pin_irq_hdr_tab[pin].mode = 0;
pin_irq_hdr_tab[pin].args = NONE;
CriticalAreaUnLock(level);
return EOK;
@ -275,74 +321,81 @@ static uint32 GpioIrqFree(int32 pin)
static int32 GpioIrqEnable(x_base pin)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
const struct PinIrq *irq;
gpio_pin_config_t gpio_config;
uint8_t irq_index;
gpio_interrupt_mode_t gpio_int_mode;
struct PinIndex pin_index;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
return -ENONESYS;
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1) {
if (pin_irq_hdr_tab[pin].pin == -1) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
irq = GetPinIrq(pin);
if (irq == NONE){
CriticalAreaUnLock(level);
return -ENONESYS;
}
switch (pin_irq_hdr_tab[irqindex].mode)
switch (pin_irq_hdr_tab[pin].mode)
{
case GPIO_IRQ_EDGE_RISING:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntRisingEdge;
break;
case GPIO_IRQ_EDGE_FALLING:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntFallingEdge;
break;
case GPIO_IRQ_EDGE_BOTH:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntRisingOrFallingEdge;
break;
case GPIO_IRQ_EDGE_RISING:
gpio_int_mode = kGPIO_IntRisingEdge;
break;
case GPIO_IRQ_EDGE_FALLING:
gpio_int_mode = kGPIO_IntFallingEdge;
break;
case GPIO_IRQ_EDGE_BOTH:
gpio_int_mode = kGPIO_IntRisingOrFallingEdge;
break;
case GPIO_IRQ_LEVEL_HIGH:
gpio_int_mode = kGPIO_IntHighLevel;
break;
case GPIO_IRQ_LEVEL_LOW:
gpio_int_mode = kGPIO_IntLowLevel;
break;
default:
gpio_int_mode = kGPIO_IntRisingEdge;
break;
}
GPIO_PinInit(index->gpio, index->pin, &gpio_config);
GPIO_PortEnableInterrupts(index->gpio, index->pin);
irq_index = (pin_index.index << 1) + (pin_index.pin >> 4);
GPIO_PinSetInterruptConfig(pin_index.gpio, pin_index.pin, gpio_int_mode);
GPIO_PortEnableInterrupts(pin_index.gpio, 1U << pin_index.pin);
NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
EnableIRQ(irq_tab[irq_index]);
CriticalAreaUnLock(level);
return EOK;
}
static int32 GpioIrqDisable(x_base pin)
{
const struct PinIndex* index = GetPin(pin);
const struct PinIrq *irq;
struct PinIndex pin_index;
irq = GetPinIrq(index->pin);
NULL_PARAM_CHECK(irq);
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
GPIO_PortDisableInterrupts(index->gpio, index->pin);
GPIO_PortDisableInterrupts(pin_index.gpio, 1U << pin_index.pin);
return EOK;
}
static uint32 Stm32PinConfigure(struct PinParam *param)
static uint32 Imxrt1052PinConfigure(struct PinParam *param)
{
NULL_PARAM_CHECK(param);
int ret = EOK;
const struct PinIndex *index = GetPin(param->pin);
struct PinIndex pin_index;
if (GetPin(&pin_index, param->pin) < 0) {
return ERROR;
}
switch(param->cmd)
{
case GPIO_CONFIG_MODE:
GpioConfigMode(param->mode, index);
GpioConfigMode(param->mode, &pin_index);
break;
case GPIO_IRQ_REGISTER:
ret = GpioIrqRegister(param->pin,param->irq_set.irq_mode,param->irq_set.hdr,param->irq_set.args);
ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
break;
case GPIO_IRQ_FREE:
ret = GpioIrqFree(param->pin);
@ -361,7 +414,7 @@ static uint32 Stm32PinConfigure(struct PinParam *param)
return ret;
}
static uint32 Stm32PinInit(void)
static uint32 Imxrt1052PinInit(void)
{
static x_bool pin_init_flag = RET_FALSE;
@ -372,7 +425,7 @@ static uint32 Stm32PinInit(void)
return EOK;
}
static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
static uint32 Imxrt1052GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
@ -383,11 +436,11 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32PinInit();
ret = Imxrt1052PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
ret = Imxrt1052PinConfigure(param);
break;
default:
break;
@ -396,47 +449,55 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
return ret;
}
uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
uint32 Imxrt1052PinWrite(void *dev, struct BusBlockWriteParam *write_param)
{
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(write_param);
struct PinStat *pinstat = (struct PinStat *)write_param->buffer;
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
struct PinStat *pin_stat = (struct PinStat *)write_param->buffer;
struct PinIndex pin_index;
if (GetPin(&pin_index, pin_stat->pin) < 0) {
return ERROR;
}
if (GPIO_LOW == pinstat->val) {
GPIO_PinWrite(index->gpio, index->pin, 0);
KPrintf("Imxrt1052PinWrite gpio 0x%x val %u\n", pin_index.gpio, pin_stat->val);
if (GPIO_LOW == pin_stat->val) {
GPIO_PinWrite(pin_index.gpio, pin_index.pin, 0);
} else {
GPIO_PinWrite(index->gpio, index->pin, 1);
GPIO_PinWrite(pin_index.gpio, pin_index.pin, 1);
}
return EOK;
}
uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
uint32 Imxrt1052PinRead(void *dev, struct BusBlockReadParam *read_param)
{
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(read_param);
struct PinStat *pinstat = (struct PinStat *)read_param->buffer;
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if(GPIO_PinRead(index->gpio, index->pin) == GPIO_LOW) {
pinstat->val = GPIO_LOW;
} else {
pinstat->val = GPIO_HIGH;
struct PinStat *pin_stat = (struct PinStat *)read_param->buffer;
struct PinIndex pin_index;
if (GetPin(&pin_index, pin_stat->pin) < 0) {
return ERROR;
}
return pinstat->val;
if(GPIO_LOW == GPIO_PinRead(pin_index.gpio, pin_index.pin)) {
pin_stat->val = GPIO_LOW;
} else {
pin_stat->val = GPIO_HIGH;
}
return pin_stat->val;
}
static const struct PinDevDone dev_done =
{
.open = NONE,
.close = NONE,
.write = Stm32PinWrite,
.read = Stm32PinRead,
.write = Imxrt1052PinWrite,
.read = Imxrt1052PinRead,
};
int Stm32HwGpioInit(void)
int Imxrt1052HwGpioInit(void)
{
x_err_t ret = EOK;
@ -449,7 +510,7 @@ int Stm32HwGpioInit(void)
}
static struct PinDriver drv;
drv.configure = &Stm32GpioDrvConfigure;
drv.configure = Imxrt1052GpioDrvConfigure;
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
if (ret != EOK) {
@ -479,66 +540,228 @@ int Stm32HwGpioInit(void)
return ret;
}
static __inline void PinIrqHdr(int irqno)
static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Type *gpio)
{
const struct PinIndex* index = GetPin(irqno);
const struct PinIrq *irq;
int i;
uint32_t isr_status, pin;
struct PinIndex pin_index;
irq = GetPinIrq(index->pin);
NULL_PARAM_CHECK(irq);
isr_status = GPIO_PortGetInterruptFlags(gpio) & gpio->IMR;
GPIO_ClearPinsInterruptFlags(index->gpio, index->pin);
for (i = pin_start; i <= pin_start + 15 ; i ++) {
if (pin_irq_hdr_tab[irqno].hdr){
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
if (GetPin(&pin_index, i + index_offset) < 0) {
continue;
}
if (isr_status & (1 << i)) {
GPIO_PortClearInterruptFlags(gpio, (1 << i));
pin = index_offset + i;
if (pin_irq_hdr_tab[pin].hdr) {
pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args);
}
}
}
}
void EXTI0_IRQHandler(int irq_num, void *arg)
void GPIO1_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(0);
}
DECLARE_HW_IRQ(GPIO1_INT0_IRQn, EXTI0_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI1_IRQHandler(int irq_num, void *arg)
PinIrqHdr(0, 0, GPIO1);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO1_Combined_0_15_IRQn, GPIO1_0_15_IRQHandler, NONE);
void GPIO1_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(1);
}
DECLARE_HW_IRQ(GPIO1_INT1_IRQn, EXTI1_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI2_IRQHandler(int irq_num, void *arg)
PinIrqHdr(0, 15, GPIO1);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO1_Combined_16_31_IRQn, GPIO1_16_31_IRQHandler, NONE);
void GPIO2_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(2);
}
DECLARE_HW_IRQ(GPIO1_INT2_IRQn, EXTI2_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI3_IRQHandler(int irq_num, void *arg)
PinIrqHdr(32, 0, GPIO2);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO2_Combined_0_15_IRQn, GPIO2_0_15_IRQHandler, NONE);
void GPIO2_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(3);
}
DECLARE_HW_IRQ(GPIO1_INT3_IRQn, EXTI3_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI4_IRQHandler(int irq_num, void *arg)
PinIrqHdr(32, 15, GPIO2);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO2_Combined_16_31_IRQn, GPIO2_16_31_IRQHandler, NONE);
void GPIO3_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(4);
}
DECLARE_HW_IRQ(GPIO1_INT4_IRQn, EXTI4_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI5_IRQHandler(int irq_num, void *arg)
PinIrqHdr(64, 0, GPIO3);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO3_Combined_0_15_IRQn, GPIO3_0_15_IRQHandler, NONE);
void GPIO3_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(5);
}
DECLARE_HW_IRQ(GPIO1_INT5_IRQn, EXTI5_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI6_IRQHandler(int irq_num, void *arg)
PinIrqHdr(64, 15, GPIO3);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO3_Combined_16_31_IRQn, GPIO3_16_31_IRQHandler, NONE);
void GPIO4_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(6);
}
DECLARE_HW_IRQ(GPIO1_INT6_IRQn, EXTI6_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI7_IRQHandler(int irq_num, void *arg)
PinIrqHdr(96, 0, GPIO4);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO4_Combined_0_15_IRQn, GPIO4_0_15_IRQHandler, NONE);
void GPIO4_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(7);
}
DECLARE_HW_IRQ(GPIO1_INT7_IRQn, EXTI7_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
PinIrqHdr(96, 15, GPIO4);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO4_Combined_16_31_IRQn, GPIO4_16_31_IRQHandler, NONE);
void GPIO5_0_15_IRQHandler(int irq_num, void *arg)
{
x_base lock = 0;
lock = DISABLE_INTERRUPT();
PinIrqHdr(128, 0, GPIO5);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO5_Combined_0_15_IRQn, GPIO5_0_15_IRQHandler, NONE);
void GPIO5_16_31_IRQHandler(int irq_num, void *arg)
{
x_base lock = 0;
lock = DISABLE_INTERRUPT();
PinIrqHdr(128, 15, GPIO5);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO5_Combined_16_31_IRQn, GPIO5_16_31_IRQHandler, NONE);
#ifdef GPIO_LED_TEST
static void GpioLedDelay(void)
{
volatile uint32_t i = 0;
for (i = 0; i < 8000000; ++i)
{
__asm("NOP"); /* delay */
}
}
void GpioLedTest(void)
{
BusType pin;
struct BusConfigureInfo configure_info;
struct BusBlockWriteParam write_param;
int ret = 0;
bool pinSet = 1;
pin = BusFind(PIN_BUS_NAME);
if (!pin) {
KPrintf("find %s failed!\n", PIN_BUS_NAME);
return;
}
pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME);
pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME);
configure_info.configure_cmd = OPE_INT;
ret = BusDrvConfigure(pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
return;
}
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
struct PinParam led_gpio_param;
struct PinStat led_gpio_stat;
/* config led pin as output*/
led_gpio_param.cmd = GPIO_CONFIG_MODE;
led_gpio_param.pin = IMXRT_GET_PIN(1, 9);
led_gpio_param.mode = GPIO_CFG_OUTPUT_OD;
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&led_gpio_param;
ret = BusDrvConfigure(pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config pin %d failed!\n", IMXRT_GET_PIN(1, 9));
return;
}
while (1) {
GpioLedDelay();
if (pinSet) {
/* set led pin as high*/
led_gpio_stat.pin = IMXRT_GET_PIN(1, 9);
led_gpio_stat.val = GPIO_HIGH;
write_param.buffer = (void *)&led_gpio_stat;
BusDevWriteData(pin->owner_haldev, &write_param);
pinSet = 0;
} else {
/* set led pin as low*/
led_gpio_stat.pin = IMXRT_GET_PIN(1, 9);
led_gpio_stat.val = GPIO_LOW;
write_param.buffer = (void *)&led_gpio_stat;
BusDevWriteData(pin->owner_haldev, &write_param);
pinSet = 1;
}
}
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
#endif

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_adc.h
View File

@ -23,12 +23,12 @@
#include <device.h>
struct Imrt1052HwAdc
struct Imxrt1052HwAdc
{
void *ADCx;
uint8 adc_channel;
};
int Imrt1052HwAdcInit(void);
int Imxrt1052HwAdcInit(void);
#endif

10
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_gpio.h
View File

@ -12,10 +12,10 @@
/**
* @file connect_gpio.h
* @brief define imxrt1052-baord gpio function and struct
* @version 1.0
* @brief define imxrt1052-board gpio function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-01
* @date 2022-03-15
*/
#ifndef __CONNECT_GPIO_H_
@ -27,7 +27,9 @@
extern "C" {
#endif
int Stm32HwGpioInit(void);
#define IMXRT_GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */
int Imxrt1052HwGpioInit(void);
#ifdef __cplusplus
}

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_rtc.h
View File

@ -31,7 +31,7 @@ void RtcI2cInit(void);
status_t RtcI2cWrite(LPI2C_Type *base, uint32_t sub_addr, uint8_t *buf, uint16_t size);
uint32_t RtcI2cRead(LPI2C_Type *base, uint32_t sub_addr, uint8_t *buf, uint16_t size);
int Imrt1052HwRtcInit(void);
int Imxrt1052HwRtcInit(void);
#endif

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_sdio.h
View File

@ -32,7 +32,7 @@
extern "C" {
#endif
int Imrt1052HwSdioInit(void);
int Imxrt1052HwSdioInit(void);
#ifdef __cplusplus
}

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_spi.h
View File

@ -45,7 +45,7 @@ struct Stm32Spi
struct SpiBus spi_bus;
};
int Imrt1052HwSpiInit(void);
int Imxrt1052HwSpiInit(void);
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name);
#ifdef __cplusplus

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_uart.h
View File

@ -33,7 +33,7 @@ extern "C" {
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
int Imrt1052HwUartInit(void);
int Imxrt1052HwUartInit(void);
#ifdef __cplusplus
}

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_usb.h
View File

@ -44,7 +44,7 @@ extern "C" {
#define USB_SINGLE_BLOCK_SIZE 512
int Imrt1052HwUsbHostInit(void);
int Imxrt1052HwUsbHostInit(void);
#ifdef __cplusplus
}

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/connect_rtc.c
View File

@ -404,7 +404,7 @@ static int BoardRtcDevBend(void)
return ret;
}
int Imrt1052HwRtcInit(void)
int Imxrt1052HwRtcInit(void)
{
x_err_t ret = EOK;
static struct RtcBus rtc_bus;

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/connect_sdio.c
View File

@ -269,7 +269,7 @@ static struct SdioDevDone dev_done =
SdioRead,
};
int Imrt1052HwSdioInit(void)
int Imxrt1052HwSdioInit(void)
{
x_err_t ret = EOK;
bool is_read_only;

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_spi.c
View File

@ -914,7 +914,7 @@ x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name)
return result;
}
int Imrt1052HwSpiInit(void)
int Imxrt1052HwSpiInit(void)
{
return Stm32HwSpiBusInit();
}

20
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/connect_uart.c
View File

@ -294,21 +294,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialBusInit error %d\n", ret);
KPrintf("Imxrt1052HwUartInit SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDriverInit error %d\n", ret);
KPrintf("Imxrt1052HwUartInit SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
KPrintf("Imxrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -322,20 +322,20 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
KPrintf("Imxrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
KPrintf("Imxrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
return ret;
}
int Imrt1052HwUartInit(void)
int Imxrt1052HwUartInit(void)
{
x_err_t ret = EOK;
@ -361,13 +361,13 @@ int Imrt1052HwUartInit(void)
ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
#endif
@ -394,13 +394,13 @@ int Imrt1052HwUartInit(void)
ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
#endif

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/connect_usb.c
View File

@ -256,7 +256,7 @@ static int BoardUsbDevBend(void)
}
/*RT1052 BOARD USB INIT*/
int Imrt1052HwUsbHostInit(void)
int Imxrt1052HwUsbHostInit(void)
{
x_err_t ret = EOK;
int32 usb_host_task = 0;

411
Ubiquitous/XiZi/board/xidatong/board.c
View File

@ -8,9 +8,9 @@
/**
* @file board.c
* @brief relative configure for xidatong
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022.03.15
*/
/*************************************************
@ -18,28 +18,17 @@ File name: board.c
Description: support imxrt1052-board init function
Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
History:
1. Date: 2022-01-25
1. Date: 2022-03-15
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board MPU、clock、memory init
2. support imxrt1052-board uart、semc、sdio driver init
2. support imxrt1052-board uart、sdio driver init
*************************************************/
#include "fsl_common.h"
#include "board.h"
#include "pin_mux.h"
#ifdef BSP_USING_SDIO
extern int Imrt1052HwSdioInit(void);
#endif
#ifdef BSP_USING_SEMC
extern status_t BOARD_InitSEMC(void);
#ifdef BSP_USING_EXTSRAM
extern int ExtSramInit(void);
#endif
#endif
#if defined(FS_VFS) && defined(MOUNT_SDCARD)
#include <iot-vfs.h>
@ -65,295 +54,21 @@ int MountSDCard(void)
#include "fsl_gpio.h"
#include "fsl_lpuart.h"
#ifdef BSP_USING_GPIO
#include <connect_gpio.h>
#endif
#ifdef BSP_USING_LPUART
#include <connect_uart.h>
#endif
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
#if 0
/* Get debug console frequency. */
uint32_t BOARD_DebugConsoleSrcFreq(void)
{
uint32_t freq;
/* To make it simple, we assume default PLL and divider settings, and the only variable
from application is use PLL3 source or OSC source */
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
{
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
else
{
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
return freq;
}
/* Initialize debug console. */
void BOARD_InitDebugConsole(void)
{
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
{
lpi2c_master_config_t lpi2cConfig = {0};
/*
* lpi2cConfig.debugEnable = false;
* lpi2cConfig.ignoreAck = false;
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
* lpi2cConfig.baudRate_Hz = 100000U;
* lpi2cConfig.busIdleTimeout_ns = 0;
* lpi2cConfig.pinLowTimeout_ns = 0;
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
*/
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
}
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
status_t reVal;
/* Send master blocking data to slave */
reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
if (kStatus_Success == reVal)
{
while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
{
}
reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterStop(base);
if (reVal != kStatus_Success)
{
return reVal;
}
}
return reVal;
}
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
status_t reVal;
reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
if (kStatus_Success == reVal)
{
while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
{
}
reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterStop(base);
if (reVal != kStatus_Success)
{
return reVal;
}
}
return reVal;
}
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
}
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
status_t reVal;
reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
if (kStatus_Success == reVal)
{
while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
{
}
reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
if (reVal != kStatus_Success)
{
return reVal;
}
/* SCCB does not support LPI2C repeat start, must stop then start. */
reVal = LPI2C_MasterStop(base);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
if (reVal != kStatus_Success)
{
return reVal;
}
reVal = LPI2C_MasterStop(base);
if (reVal != kStatus_Success)
{
return reVal;
}
}
return reVal;
}
void BOARD_Accel_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
}
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
{
uint8_t data = (uint8_t)txBuff;
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
}
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
}
void BOARD_Codec_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
}
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
void BOARD_Camera_I2C_Init(void)
{
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
}
status_t BOARD_Camera_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Camera_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
rxBuffSize);
}
status_t BOARD_Camera_I2C_SendSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Camera_I2C_ReceiveSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
rxBuffSize);
}
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#ifdef BSP_USING_CH438
#include <connect_ch438.h>
#endif
#ifdef BSP_USING_SDIO
#include <connect_sdio.h>
#endif
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
{
@ -558,7 +273,6 @@ void BOARD_ConfigMPU(void)
SCB_EnableICache();
}
/* This is the timer interrupt service routine. */
void SysTick_Handler(int irqn, void *arg)
{
@ -566,60 +280,8 @@ void SysTick_Handler(int irqn, void *arg)
}
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
#ifdef BSP_USING_LPUART
void imxrt_uart_pins_init(void)
{
#ifdef BSP_USING_LPUART1
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef BSP_USING_LPUART2
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0x10B0u);
#endif
}
#endif /* BSP_USING_LPUART */
/**
* This function will initial rt1050 board.
* This function will initial imxrt1050 board.
*/
void InitBoardHardware()
{
@ -627,56 +289,35 @@ void InitBoardHardware()
BOARD_InitPins();
BOARD_BootClockRUN();
#ifndef BSP_USING_LWIP
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
#ifdef BSP_USING_GPIO
Imxrt1052HwGpioInit();
#endif
#ifdef BSP_USING_LPUART
imxrt_uart_pins_init();
BOARD_InitUartPins();
#endif
#ifdef BSP_USING_CH438
BOARD_InitCh438Pins();
#endif
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
#ifdef BSP_USING_SEMC
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
/* Set semc clock to 163.86 MHz */
CLOCK_SetMux(kCLOCK_SemcMux, 1);
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
if (BOARD_InitSEMC() != kStatus_Success) {
KPrintf("\r\n SEMC Init Failed\r\n");
}
#ifdef MEM_EXTERN_SRAM
else {
ExtSramInit();
}
#endif
#endif
#ifdef BSP_USING_LWIP
ETH_BSP_Config();
#endif
#ifdef BSP_USING_LPUART
Imrt1052HwUartInit();
Imxrt1052HwUartInit();
#endif
#ifdef BSP_USING_ADC
Imrt1052HwAdcInit();
#endif
#ifdef BSP_USING_SPI
Imrt1052HwSpiInit();
#endif
#ifdef BSP_USING_RTC
Imrt1052HwRtcInit();
#ifdef BSP_USING_CH438
Imxrt1052HwCh438Init();
#endif
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
#ifdef BSP_USING_SDIO
Imrt1052HwSdioInit();
Imxrt1052HwSdioInit();
#endif
}

152
Ubiquitous/XiZi/board/xidatong/include/board.h
View File

@ -49,55 +49,17 @@ void InitBoardHardware(void);
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "IMXRT1050-EVKB"
#define BOARD_NAME "IMXRT1050"
/* The UART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
#define BOARD_DEBUG_UART_INSTANCE 1U
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
#define BOARD_UART_IRQ LPUART1_IRQn
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
#endif /* BOARD_DEBUG_UART_BAUDRATE */
/*! @brief The USER_LED used for board */
#define LOGIC_LED_ON (0U)
#define LOGIC_LED_OFF (1U)
#ifndef BOARD_USER_LED_GPIO
#define BOARD_USER_LED_GPIO GPIO1
#endif
#ifndef BOARD_USER_LED_GPIO_PIN
#define BOARD_USER_LED_GPIO_PIN (9U)
#endif
#define USER_LED_INIT(output) \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
#define USER_LED_ON() \
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
#define USER_LED_TOGGLE() \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
/*! @brief Define the port interrupt number for the board switches */
#ifndef BOARD_USER_BUTTON_GPIO
#define BOARD_USER_BUTTON_GPIO GPIO5
#endif
#ifndef BOARD_USER_BUTTON_GPIO_PIN
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
#endif
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
#define BOARD_USER_BUTTON_NAME "SW8"
/*! @brief The hyper flash size */
#define BOARD_FLASH_SIZE (0x4000000U)
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/
/*! @brief The ENET PHY address. */
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
@ -186,40 +148,6 @@ void InitBoardHardware(void);
#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
/*! @brief The WIFI-QCA shield pin. */
#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
/*! @brief The WIFI-QCA Silex 2401 shield pin. */
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
/* @Brief Board accelerator sensor configuration */
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
@ -234,71 +162,11 @@ void InitBoardHardware(void);
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
/* @Brief Board CAMERA configuration */
#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
#define BOARD_CAMERA_I2C_CLOCK_FREQ \
(CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
uint32_t BOARD_DebugConsoleSrcFreq(void);
void BOARD_InitDebugConsole(void);
void BOARD_ConfigMPU(void);
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
void BOARD_Accel_I2C_Init(void);
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Codec_I2C_Init(void);
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Camera_I2C_Init(void);
status_t BOARD_Camera_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Camera_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
status_t BOARD_Camera_I2C_SendSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Camera_I2C_ReceiveSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
#endif /* SDK_I2C_BASED_COMPONENT_USED */
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);

2
Ubiquitous/XiZi/board/xidatong/include/pin_mux.h
View File

@ -73,6 +73,8 @@ void BOARD_InitBootPins(void);
void BOARD_InitPins(void);
void BOARD_InitI2C1Pins(void);
void BOARD_InitSPIPins(void);
void BOARD_InitUartPins(void);
void BOARD_InitCh438Pins(void);
#if defined(__cplusplus)
}

8
Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig
View File

@ -6,11 +6,17 @@ menuconfig BSP_USING_LPUART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif
menuconfig BSP_USING_CH438
bool "Using CH438 device"
default n
if BSP_USING_CH438
source "$BSP_DIR/third_party_driver/ch438/Kconfig"
endif
menuconfig BSP_USING_GPIO
bool "Using GPIO device "
default y
select RESOURCES_PIN
if BSP_USING_GPIO
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
endif

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile
View File

@ -4,6 +4,10 @@ ifeq ($(CONFIG_BSP_USING_LPUART),y)
SRC_DIR += uart
endif
ifeq ($(CONFIG_BSP_USING_CH438),y)
SRC_DIR += ch438
endif
ifeq ($(CONFIG_BSP_USING_SDIO),y)
SRC_DIR += sdio
endif

135
Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c
View File

@ -1103,6 +1103,141 @@ void BOARD_InitI2C1Pins ( void )
Pull Up / Down Config. Field: 22K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
}
void BOARD_InitUartPins(void)
{
#ifdef BSP_USING_LPUART1
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef BSP_USING_LPUART2
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0x10B0u);
#endif
}
void BOARD_InitCh438Pins(void)
{
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, /* GPIO1_IO25 is configured as CH438_DATA0 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO1_IO24 is configured as CH438_DATA1 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, /* GPIO1_IO20 is configured as CH438_DATA2 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, /* GPIO1_IO21 is configured as CH438_DATA3 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, /* GPIO1_IO31 is configured as CH438_DATA4 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, /* GPIO1_IO28 is configured as CH438_DATA5 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, /* GPIO1_IO30 is configured as CH438_DATA6 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, /* GPIO1_IO29 is configured as CH438_DATA7 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, /* GPIO3_IO04 is configured as CH438_nWR */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, /* GPIO3_IO02 is configured as CH438_ALE */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, /* GPIO3_IO03 is configured as CH438_INT */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO3_IO02 is configured as CH438_485_A_DIR */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, /* GPIO1_IO00 is configured as CH438_485_B_DIR */
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, /* GPIO1_IO25 is configured as CH438_DATA0 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO1_IO24 is configured as CH438_DATA1 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, /* GPIO1_IO20 is configured as CH438_DATA2 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, /* GPIO1_IO21 is configured as CH438_DATA3 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, /* GPIO1_IO31 is configured as CH438_DATA4 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, /* GPIO1_IO28 is configured as CH438_DATA5 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, /* GPIO1_IO30 is configured as CH438_DATA6 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, /* GPIO1_IO29 is configured as CH438_DATA7 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, /* GPIO3_IO04 is configured as CH438_nWR */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, /* GPIO3_IO02 is configured as CH438_ALE */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, /* GPIO3_IO03 is configured as CH438_INT */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO3_IO02 is configured as CH438_485_A_DIR */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, /* GPIO1_IO00 is configured as CH438_485_B_DIR */
0x10B0u);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

765
Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c
View File

@ -1,39 +1,35 @@
/*
* Copyright (c) 2020 RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 balanceTWK first version
* 2019-04-23 WillianChan Fix GPIO serial number disorder
*/
* Date Author Notes
* 2018-4-30 misonyo the first version.
*/
/**
* @file connect_gpio.c
* @brief support gpio function using bus driver framework
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021-04-25
* @date 2022-03-16
*/
/*************************************************
File name: connect_gpio.c
Description: support gpio configure and register to bus framework
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c for references
Description: support gpio configure and register to bus framework
Others: take RT-Thread v4.0.2/bsp/imxrt/libraries/drivers/drv_gpio.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2021-04-25
1. Date: 2022-03-16
Author: AIIT XUOS Lab
Modification: add bus driver framework support for gpio
*************************************************/
#include <device.h>
#include <board.h>
#define STM32_PIN_NUMBERS 100 // [48, 64, 100, 144]
#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
#include <connect_gpio.h>
#include <fsl_gpio.h>
#include <fsl_iomuxc.h>
struct PinIndex
{
@ -50,81 +46,196 @@ struct PinIrq
uint32 exti_line;
};
static const struct PinIndex pins[] = {
{0, GPIO1, 0},
{1, GPIO1, 1},
{2, GPIO1, 2},
{3, GPIO1, 3},
{4, GPIO1, 4},
{5, GPIO1, 5},
{6, GPIO1, 6},
{7, GPIO1, 7},
{8, GPIO1, 8},
{9, GPIO1, 9},
{10, GPIO1, 10},
{11, GPIO1, 11},
{12, GPIO1, 12},
{13, GPIO1, 13},
{14, GPIO1, 14},
{15, GPIO1, 15},
{16, GPIO2, 0},
{17, GPIO2, 1},
{18, GPIO2, 2},
{19, GPIO2, 3},
{20, GPIO2, 4},
{21, GPIO2, 5},
{22, GPIO2, 6},
{23, GPIO2, 7},
{24, GPIO2, 8},
{25, GPIO2, 9},
{26, GPIO2, 10},
{27, GPIO2, 11},
{28, GPIO2, 12},
{29, GPIO2, 13},
{30, GPIO2, 14},
{31, GPIO2, 15},
{32, GPIO3, 0},
{33, GPIO3, 1},
{34, GPIO3, 2},
{35, GPIO3, 3},
{36, GPIO3, 4},
{37, GPIO3, 5},
{38, GPIO3, 6},
{39, GPIO3, 7},
{40, GPIO3, 8},
{41, GPIO3, 9},
{42, GPIO3, 10},
{43, GPIO3, 11},
{44, GPIO3, 12},
{45, GPIO3, 13},
{46, GPIO3, 14},
{47, GPIO3, 15},
{-1, 0u, -1}
struct PinMask
{
GPIO_Type *gpio;
uint32 valid_mask;
};
struct PinIrqHdr pin_irq_hdr_tab[] = {};
const struct PinIndex *GetPin(uint8_t pin)
static const IRQn_Type irq_tab[10] =
{
const struct PinIndex *index;
GPIO1_Combined_0_15_IRQn,
GPIO1_Combined_16_31_IRQn,
GPIO2_Combined_0_15_IRQn,
GPIO2_Combined_16_31_IRQn,
GPIO3_Combined_0_15_IRQn,
GPIO3_Combined_16_31_IRQn,
GPIO4_Combined_0_15_IRQn,
GPIO4_Combined_16_31_IRQn,
GPIO5_Combined_0_15_IRQn,
GPIO5_Combined_16_31_IRQn
};
if (pin < ITEM_NUM(pins)){
index = &pins[pin];
if (index->index == -1)
index = NONE;
}
else{
index = NONE;
const struct PinMask pin_mask[] =
{
{GPIO1, 0xFFFFFFFF}, /* GPIO1 */
{GPIO2, 0xFFFFFFFF}, /* GPIO2 */
{GPIO3, 0x0FFFFFFF}, /* GPIO3,28~31 not supported */
{GPIO4, 0xFFFFFFFF}, /* GPIO4 */
{GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
};
struct PinIrqHdr pin_irq_hdr_tab[] =
{
/* GPIO1 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO2 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO3 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO4 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
/* GPIO5 */
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
{-1, 0, NONE, NONE},
};
static int GetPin(struct PinIndex *pin_index, uint8_t pin)
{
pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5
pin_index->pin = pin & 31;//each GPIOx support 32 io
if ((pin_index->index > 4) || ((pin_mask[pin_index->index].valid_mask & (1 << pin_index->pin)) == 0)) {
KPrintf("GetPin unsupport pin index %u pin %u\n", pin_index->index, pin_index->pin);
return -1;
}
return index;
pin_index->gpio = pin_mask[pin_index->index].gpio;
return 0;
}
static int32 GpioConfigMode(int mode, const struct PinIndex* index)
static int32 GpioConfigMode(int mode, struct PinIndex *index)
{
gpio_pin_config_t gpio_config;
NULL_PARAM_CHECK(index);
gpio_config.outputLogic = 0;
switch (mode)
{
case GPIO_CFG_OUTPUT:
@ -137,14 +248,15 @@ static int32 GpioConfigMode(int mode, const struct PinIndex* index)
break;
case GPIO_CFG_INPUT_PULLUP:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntRisingEdge;
gpio_config.interruptMode = kGPIO_NoIntmode;
break;
case GPIO_CFG_INPUT_PULLDOWN:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntFallingEdge;
gpio_config.interruptMode = kGPIO_NoIntmode;
break;
case GPIO_CFG_OUTPUT_OD:
gpio_config.direction = kGPIO_DigitalOutput;
gpio_config.interruptMode = kGPIO_NoIntmode;
break;
default:
break;
@ -153,97 +265,33 @@ static int32 GpioConfigMode(int mode, const struct PinIndex* index)
return EOK;
}
static __inline int32 Bit2Bitnum(uint32 bit)
{
for (int i = 0; i < 32; i++){
if ((1UL << i) == bit){
return i;
}
}
return -1;
}
static __inline int32 Bitno2Bit(uint32 bitno)
{
if (bitno <= 32) {
return 1UL << bitno;
}
else {
return 0;
}
}
static const struct PinIrq *GetPinIrq(uint16_t pin)
{
static struct PinIrq irq;
const struct PinIndex* index = GetPin(pin);
if (index == NONE) {
return NONE;
}
irq.exti_line = index->pin;
irq.pin_source = Bit2Bitnum(index->pin);
irq.port_source = ((uint32_t)index->gpio - GPIO1_BASE) / (GPIO2_BASE - GPIO1_BASE);
switch (irq.pin_source)
{
case 0 :
irq.irq_exti_channel = GPIO1_INT0_IRQn;
break;
case 1 :
irq.irq_exti_channel = GPIO1_INT1_IRQn;
break;
case 2 :
irq.irq_exti_channel = GPIO1_INT2_IRQn;
break;
case 3 :
irq.irq_exti_channel = GPIO1_INT3_IRQn;
break;
case 4 :
irq.irq_exti_channel = GPIO1_INT4_IRQn;
break;
case 5 :
irq.irq_exti_channel = GPIO1_INT5_IRQn;
break;
case 6 :
irq.irq_exti_channel = GPIO1_INT6_IRQn;
break;
case 7 :
irq.irq_exti_channel = GPIO1_INT7_IRQn;
break;
default :
return NONE;
}
return &irq;
};
static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
struct PinIndex pin_index;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args
if (pin_irq_hdr_tab[pin].pin == pin &&
pin_irq_hdr_tab[pin].hdr == hdr &&
pin_irq_hdr_tab[pin].mode == mode &&
pin_irq_hdr_tab[pin].args == args
)
{
CriticalAreaUnLock(level);
return EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1) {
if (pin_irq_hdr_tab[pin].pin != -1) {
CriticalAreaUnLock(level);
return -EDEV_BUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
pin_irq_hdr_tab[pin].pin = pin;
pin_irq_hdr_tab[pin].hdr = hdr;
pin_irq_hdr_tab[pin].mode = mode;
pin_irq_hdr_tab[pin].args = args;
CriticalAreaUnLock(level);
return EOK;
@ -251,23 +299,21 @@ static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), voi
static uint32 GpioIrqFree(int32 pin)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
struct PinIndex pin_index;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1){
if (pin_irq_hdr_tab[pin].pin == -1){
CriticalAreaUnLock(level);
return EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = NONE;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = NONE;
pin_irq_hdr_tab[pin].pin = -1;
pin_irq_hdr_tab[pin].hdr = NONE;
pin_irq_hdr_tab[pin].mode = 0;
pin_irq_hdr_tab[pin].args = NONE;
CriticalAreaUnLock(level);
return EOK;
@ -275,74 +321,81 @@ static uint32 GpioIrqFree(int32 pin)
static int32 GpioIrqEnable(x_base pin)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
const struct PinIrq *irq;
gpio_pin_config_t gpio_config;
uint8_t irq_index;
gpio_interrupt_mode_t gpio_int_mode;
struct PinIndex pin_index;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
return -ENONESYS;
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1) {
if (pin_irq_hdr_tab[pin].pin == -1) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
irq = GetPinIrq(pin);
if (irq == NONE){
CriticalAreaUnLock(level);
return -ENONESYS;
}
switch (pin_irq_hdr_tab[irqindex].mode)
switch (pin_irq_hdr_tab[pin].mode)
{
case GPIO_IRQ_EDGE_RISING:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntRisingEdge;
break;
case GPIO_IRQ_EDGE_FALLING:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntFallingEdge;
break;
case GPIO_IRQ_EDGE_BOTH:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntRisingOrFallingEdge;
break;
case GPIO_IRQ_EDGE_RISING:
gpio_int_mode = kGPIO_IntRisingEdge;
break;
case GPIO_IRQ_EDGE_FALLING:
gpio_int_mode = kGPIO_IntFallingEdge;
break;
case GPIO_IRQ_EDGE_BOTH:
gpio_int_mode = kGPIO_IntRisingOrFallingEdge;
break;
case GPIO_IRQ_LEVEL_HIGH:
gpio_int_mode = kGPIO_IntHighLevel;
break;
case GPIO_IRQ_LEVEL_LOW:
gpio_int_mode = kGPIO_IntLowLevel;
break;
default:
gpio_int_mode = kGPIO_IntRisingEdge;
break;
}
GPIO_PinInit(index->gpio, index->pin, &gpio_config);
GPIO_PortEnableInterrupts(index->gpio, index->pin);
irq_index = (pin_index.index << 1) + (pin_index.pin >> 4);
GPIO_PinSetInterruptConfig(pin_index.gpio, pin_index.pin, gpio_int_mode);
GPIO_PortEnableInterrupts(pin_index.gpio, 1U << pin_index.pin);
NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
EnableIRQ(irq_tab[irq_index]);
CriticalAreaUnLock(level);
return EOK;
}
static int32 GpioIrqDisable(x_base pin)
{
const struct PinIndex* index = GetPin(pin);
const struct PinIrq *irq;
struct PinIndex pin_index;
irq = GetPinIrq(index->pin);
NULL_PARAM_CHECK(irq);
if (GetPin(&pin_index, pin) < 0) {
return ERROR;
}
GPIO_PortDisableInterrupts(index->gpio, index->pin);
GPIO_PortDisableInterrupts(pin_index.gpio, 1U << pin_index.pin);
return EOK;
}
static uint32 Stm32PinConfigure(struct PinParam *param)
static uint32 Imxrt1052PinConfigure(struct PinParam *param)
{
NULL_PARAM_CHECK(param);
int ret = EOK;
const struct PinIndex *index = GetPin(param->pin);
struct PinIndex pin_index;
if (GetPin(&pin_index, param->pin) < 0) {
return ERROR;
}
switch(param->cmd)
{
case GPIO_CONFIG_MODE:
GpioConfigMode(param->mode, index);
GpioConfigMode(param->mode, &pin_index);
break;
case GPIO_IRQ_REGISTER:
ret = GpioIrqRegister(param->pin,param->irq_set.irq_mode,param->irq_set.hdr,param->irq_set.args);
ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
break;
case GPIO_IRQ_FREE:
ret = GpioIrqFree(param->pin);
@ -361,7 +414,7 @@ static uint32 Stm32PinConfigure(struct PinParam *param)
return ret;
}
static uint32 Stm32PinInit(void)
static uint32 Imxrt1052PinInit(void)
{
static x_bool pin_init_flag = RET_FALSE;
@ -372,7 +425,7 @@ static uint32 Stm32PinInit(void)
return EOK;
}
static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
static uint32 Imxrt1052GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
@ -383,11 +436,11 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32PinInit();
ret = Imxrt1052PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
ret = Imxrt1052PinConfigure(param);
break;
default:
break;
@ -396,47 +449,55 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
return ret;
}
uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
uint32 Imxrt1052PinWrite(void *dev, struct BusBlockWriteParam *write_param)
{
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(write_param);
struct PinStat *pinstat = (struct PinStat *)write_param->buffer;
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
struct PinStat *pin_stat = (struct PinStat *)write_param->buffer;
struct PinIndex pin_index;
if (GetPin(&pin_index, pin_stat->pin) < 0) {
return ERROR;
}
if (GPIO_LOW == pinstat->val) {
GPIO_PinWrite(index->gpio, index->pin, 0);
KPrintf("Imxrt1052PinWrite gpio 0x%x val %u\n", pin_index.gpio, pin_stat->val);
if (GPIO_LOW == pin_stat->val) {
GPIO_PinWrite(pin_index.gpio, pin_index.pin, 0);
} else {
GPIO_PinWrite(index->gpio, index->pin, 1);
GPIO_PinWrite(pin_index.gpio, pin_index.pin, 1);
}
return EOK;
}
uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
uint32 Imxrt1052PinRead(void *dev, struct BusBlockReadParam *read_param)
{
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(read_param);
struct PinStat *pinstat = (struct PinStat *)read_param->buffer;
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if(GPIO_PinRead(index->gpio, index->pin) == GPIO_LOW) {
pinstat->val = GPIO_LOW;
} else {
pinstat->val = GPIO_HIGH;
struct PinStat *pin_stat = (struct PinStat *)read_param->buffer;
struct PinIndex pin_index;
if (GetPin(&pin_index, pin_stat->pin) < 0) {
return ERROR;
}
return pinstat->val;
if(GPIO_LOW == GPIO_PinRead(pin_index.gpio, pin_index.pin)) {
pin_stat->val = GPIO_LOW;
} else {
pin_stat->val = GPIO_HIGH;
}
return pin_stat->val;
}
static const struct PinDevDone dev_done =
{
.open = NONE,
.close = NONE,
.write = Stm32PinWrite,
.read = Stm32PinRead,
.write = Imxrt1052PinWrite,
.read = Imxrt1052PinRead,
};
int Stm32HwGpioInit(void)
int Imxrt1052HwGpioInit(void)
{
x_err_t ret = EOK;
@ -449,7 +510,7 @@ int Stm32HwGpioInit(void)
}
static struct PinDriver drv;
drv.configure = &Stm32GpioDrvConfigure;
drv.configure = Imxrt1052GpioDrvConfigure;
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
if (ret != EOK) {
@ -479,66 +540,228 @@ int Stm32HwGpioInit(void)
return ret;
}
static __inline void PinIrqHdr(int irqno)
static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Type *gpio)
{
const struct PinIndex* index = GetPin(irqno);
const struct PinIrq *irq;
int i;
uint32_t isr_status, pin;
struct PinIndex pin_index;
irq = GetPinIrq(index->pin);
NULL_PARAM_CHECK(irq);
isr_status = GPIO_PortGetInterruptFlags(gpio) & gpio->IMR;
GPIO_ClearPinsInterruptFlags(index->gpio, index->pin);
for (i = pin_start; i <= pin_start + 15 ; i ++) {
if (pin_irq_hdr_tab[irqno].hdr){
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
if (GetPin(&pin_index, i + index_offset) < 0) {
continue;
}
if (isr_status & (1 << i)) {
GPIO_PortClearInterruptFlags(gpio, (1 << i));
pin = index_offset + i;
if (pin_irq_hdr_tab[pin].hdr) {
pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args);
}
}
}
}
void EXTI0_IRQHandler(int irq_num, void *arg)
void GPIO1_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(0);
}
DECLARE_HW_IRQ(GPIO1_INT0_IRQn, EXTI0_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI1_IRQHandler(int irq_num, void *arg)
PinIrqHdr(0, 0, GPIO1);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO1_Combined_0_15_IRQn, GPIO1_0_15_IRQHandler, NONE);
void GPIO1_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(1);
}
DECLARE_HW_IRQ(GPIO1_INT1_IRQn, EXTI1_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI2_IRQHandler(int irq_num, void *arg)
PinIrqHdr(0, 15, GPIO1);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO1_Combined_16_31_IRQn, GPIO1_16_31_IRQHandler, NONE);
void GPIO2_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(2);
}
DECLARE_HW_IRQ(GPIO1_INT2_IRQn, EXTI2_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI3_IRQHandler(int irq_num, void *arg)
PinIrqHdr(32, 0, GPIO2);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO2_Combined_0_15_IRQn, GPIO2_0_15_IRQHandler, NONE);
void GPIO2_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(3);
}
DECLARE_HW_IRQ(GPIO1_INT3_IRQn, EXTI3_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI4_IRQHandler(int irq_num, void *arg)
PinIrqHdr(32, 15, GPIO2);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO2_Combined_16_31_IRQn, GPIO2_16_31_IRQHandler, NONE);
void GPIO3_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(4);
}
DECLARE_HW_IRQ(GPIO1_INT4_IRQn, EXTI4_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI5_IRQHandler(int irq_num, void *arg)
PinIrqHdr(64, 0, GPIO3);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO3_Combined_0_15_IRQn, GPIO3_0_15_IRQHandler, NONE);
void GPIO3_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(5);
}
DECLARE_HW_IRQ(GPIO1_INT5_IRQn, EXTI5_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI6_IRQHandler(int irq_num, void *arg)
PinIrqHdr(64, 15, GPIO3);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO3_Combined_16_31_IRQn, GPIO3_16_31_IRQHandler, NONE);
void GPIO4_0_15_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(6);
}
DECLARE_HW_IRQ(GPIO1_INT6_IRQn, EXTI6_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
void EXTI7_IRQHandler(int irq_num, void *arg)
PinIrqHdr(96, 0, GPIO4);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO4_Combined_0_15_IRQn, GPIO4_0_15_IRQHandler, NONE);
void GPIO4_16_31_IRQHandler(int irq_num, void *arg)
{
PinIrqHdr(7);
}
DECLARE_HW_IRQ(GPIO1_INT7_IRQn, EXTI7_IRQHandler, NONE);
x_base lock = 0;
lock = DISABLE_INTERRUPT();
PinIrqHdr(96, 15, GPIO4);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO4_Combined_16_31_IRQn, GPIO4_16_31_IRQHandler, NONE);
void GPIO5_0_15_IRQHandler(int irq_num, void *arg)
{
x_base lock = 0;
lock = DISABLE_INTERRUPT();
PinIrqHdr(128, 0, GPIO5);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO5_Combined_0_15_IRQn, GPIO5_0_15_IRQHandler, NONE);
void GPIO5_16_31_IRQHandler(int irq_num, void *arg)
{
x_base lock = 0;
lock = DISABLE_INTERRUPT();
PinIrqHdr(128, 15, GPIO5);
ENABLE_INTERRUPT(lock);
}
DECLARE_HW_IRQ(GPIO5_Combined_16_31_IRQn, GPIO5_16_31_IRQHandler, NONE);
#ifdef GPIO_LED_TEST
static void GpioLedDelay(void)
{
volatile uint32_t i = 0;
for (i = 0; i < 8000000; ++i)
{
__asm("NOP"); /* delay */
}
}
void GpioLedTest(void)
{
BusType pin;
struct BusConfigureInfo configure_info;
struct BusBlockWriteParam write_param;
int ret = 0;
bool pinSet = 1;
pin = BusFind(PIN_BUS_NAME);
if (!pin) {
KPrintf("find %s failed!\n", PIN_BUS_NAME);
return;
}
pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME);
pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME);
configure_info.configure_cmd = OPE_INT;
ret = BusDrvConfigure(pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
return;
}
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
struct PinParam led_gpio_param;
struct PinStat led_gpio_stat;
/* config led pin as output*/
led_gpio_param.cmd = GPIO_CONFIG_MODE;
led_gpio_param.pin = IMXRT_GET_PIN(1, 9);
led_gpio_param.mode = GPIO_CFG_OUTPUT_OD;
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&led_gpio_param;
ret = BusDrvConfigure(pin->owner_driver, &configure_info);
if (ret != EOK) {
KPrintf("config pin %d failed!\n", IMXRT_GET_PIN(1, 9));
return;
}
while (1) {
GpioLedDelay();
if (pinSet) {
/* set led pin as high*/
led_gpio_stat.pin = IMXRT_GET_PIN(1, 9);
led_gpio_stat.val = GPIO_HIGH;
write_param.buffer = (void *)&led_gpio_stat;
BusDevWriteData(pin->owner_haldev, &write_param);
pinSet = 0;
} else {
/* set led pin as low*/
led_gpio_stat.pin = IMXRT_GET_PIN(1, 9);
led_gpio_stat.val = GPIO_LOW;
write_param.buffer = (void *)&led_gpio_stat;
BusDevWriteData(pin->owner_haldev, &write_param);
pinSet = 1;
}
}
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
#endif

8
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_gpio.h
View File

@ -13,9 +13,9 @@
/**
* @file connect_gpio.h
* @brief define imxrt1052-board gpio function and struct
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-01
* @date 2022-03-15
*/
#ifndef __CONNECT_GPIO_H_
@ -27,7 +27,9 @@
extern "C" {
#endif
int Stm32HwGpioInit(void);
#define IMXRT_GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */
int Imxrt1052HwGpioInit(void);
#ifdef __cplusplus
}

6
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_sdio.h
View File

@ -13,9 +13,9 @@
/**
* @file connect_sdio.h
* @brief define imxrt1052-board sdio function and struct
* @version 2.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-01-24
* @date 2022-03-15
*/
#ifndef CONNECT_SDIO_H
@ -32,7 +32,7 @@
extern "C" {
#endif
int Imrt1052HwSdioInit(void);
int Imxrt1052HwSdioInit(void);
#ifdef __cplusplus
}

6
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_uart.h
View File

@ -13,9 +13,9 @@
/**
* @file connect_uart.h
* @brief define imxrt1052-board usart function and struct
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021-05-28
* @date 2022-03-15
*/
#ifndef CONNECT_UART_H
@ -33,7 +33,7 @@ extern "C" {
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
int Imrt1052HwUartInit(void);
int Imxrt1052HwUartInit(void);
#ifdef __cplusplus
}

6
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_usb.h
View File

@ -13,9 +13,9 @@
/**
* @file connect_usb.h
* @brief define imxrt1052-board usb function and struct
* @version 2.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-02-09
* @date 2022-03-15
*/
#ifndef CONNECT_USB_H
@ -44,7 +44,7 @@ extern "C" {
#define USB_SINGLE_BLOCK_SIZE 512
int Imrt1052HwUsbHostInit(void);
int Imxrt1052HwUsbHostInit(void);
#ifdef __cplusplus
}

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_cache.h
View File

@ -9,9 +9,9 @@
/**
* @file fsl_cache.h
* @brief cache drivers
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022-03-15
*/
#ifndef _FSL_CACHE_H_

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_clock.h
View File

@ -8,9 +8,9 @@
/**
* @file fsl_clock.h
* @brief clock drivers
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022-03-15
*/
#ifndef _FSL_CLOCK_H_

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_common.h
View File

@ -9,9 +9,9 @@
/**
* @file fsl_common.h
* @brief common drivers header
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022-03-15
*/
#ifndef _FSL_COMMON_H_

213
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_debug_console.h
View File

@ -1,213 +0,0 @@
/*
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Debug console shall provide input and output functions to scan and print formatted data.
* o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
* - [flags] :'-', '+', '#', ' ', '0'
* - [width]: number (0,1...)
* - [.precision]: number (0,1...)
* - [length]: do not support
* - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
* o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
* - [*]: is supported.
* - [width]: number (0,1...)
* - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
* - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
*/
#ifndef _FSL_DEBUGCONSOLE_H_
#define _FSL_DEBUGCONSOLE_H_
#include "fsl_common.h"
#include "serial_manager.h"
/*!
* @addtogroup debugconsole
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
extern serial_handle_t g_serialHandle; /*!< serial manager handle */
/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
* to be redefined in project setting.
*/
#ifndef SDK_DEBUGCONSOLE
#define SDK_DEBUGCONSOLE 1U
#endif
/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */
#ifndef SDK_DEBUGCONSOLE_UART
/* mcux will handle this macro, not define it here */
#if (!defined(__MCUXPRESSO))
#define SDK_DEBUGCONSOLE_UART
#endif
#endif
#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
#include <stdio.h>
#endif
/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
*
* if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
* if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
* if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
*/
#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
#define PRINTF
#define SCANF
#define PUTCHAR
#define GETCHAR
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
#define PRINTF DbgConsole_Printf
#define SCANF DbgConsole_Scanf
#define PUTCHAR DbgConsole_Putchar
#define GETCHAR DbgConsole_Getchar
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
*/
#define PRINTF printf
#define SCANF scanf
#define PUTCHAR putchar
#define GETCHAR getchar
#endif /* SDK_DEBUGCONSOLE */
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*! @name Initialization*/
/* @{ */
/*!
* @brief Initializes the peripheral used for debug messages.
*
* Call this function to enable debug log messages to be output via the specified peripheral
* initialized by the serial manager module.
* After this function has returned, stdout and stdin are connected to the selected peripheral.
*
* @param instance The instance of the module.
* @param baudRate The desired baud rate in bits per second.
* @param device Low level device type for the debug console, can be one of the following.
* @arg kSerialPort_Uart,
* @arg kSerialPort_UsbCdc
* @arg kSerialPort_UsbCdcVirtual.
* @param clkSrcFreq Frequency of peripheral source clock.
*
* @return Indicates whether initialization was successful or not.
* @retval kStatus_Success Execution successfully
*/
status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
/*!
* @brief De-initializes the peripheral used for debug messages.
*
* Call this function to disable debug log messages to be output via the specified peripheral
* initialized by the serial manager module.
*
* @return Indicates whether de-initialization was successful or not.
*/
status_t DbgConsole_Deinit(void);
#if SDK_DEBUGCONSOLE
/*!
* @brief Writes formatted output to the standard output stream.
*
* Call this function to write a formatted output to the standard output stream.
*
* @param formatString Format control string.
* @return Returns the number of characters printed or a negative value if an error occurs.
*/
int DbgConsole_Printf(const char *formatString, ...);
/*!
* @brief Writes a character to stdout.
*
* Call this function to write a character to stdout.
*
* @param ch Character to be written.
* @return Returns the character written.
*/
int DbgConsole_Putchar(int ch);
/*!
* @brief Reads formatted data from the standard input stream.
*
* Call this function to read formatted data from the standard input stream.
*
* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
* other tasks will not be scheduled), the function cannot be used when the
* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
* And an error is returned when the function called in this case. The suggestion
* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
*
* @param formatString Format control string.
* @return Returns the number of fields successfully converted and assigned.
*/
int DbgConsole_Scanf(char *formatString, ...);
/*!
* @brief Reads a character from standard input.
*
* Call this function to read a character from standard input.
*
* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
* other tasks will not be scheduled), the function cannot be used when the
* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
* And an error is returned when the function called in this case. The suggestion
* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
*
* @return Returns the character read.
*/
int DbgConsole_Getchar(void);
/*!
* @brief Debug console flush.
*
* Call this function to wait the tx buffer empty.
* If interrupt transfer is using, make sure the global IRQ is enable before call this function
* This function should be called when
* 1, before enter power down mode
* 2, log is required to print to terminal immediately
* @return Indicates whether wait idle was successful or not.
*/
status_t DbgConsole_Flush(void);
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
/*!
* @brief Debug console try to get char
* This function provides a API which will not block current task, if character is
* available return it, otherwise return fail.
* @param ch the address of char to receive
* @return Indicates get char was successful or not.
*/
status_t DbgConsole_TryGetchar(char *ch);
#endif
#endif /* SDK_DEBUGCONSOLE */
/*! @} */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/*! @} */
#endif /* _FSL_DEBUGCONSOLE_H_ */

158
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_debug_console_conf.h
View File

@ -1,158 +0,0 @@
/*
* Copyright 2017 - 2019 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
#define _FSL_DEBUG_CONSOLE_CONF_H_
/****************Debug console configuration********************/
/*! @brief If Non-blocking mode is needed, please define it at project setting,
* otherwise blocking mode is the default transfer mode.
* Warning: If you want to use non-blocking transfer,please make sure the corresponding
* IO interrupt is enable, otherwise there is no output.
* And non-blocking is combine with buffer, no matter bare-metal or rtos.
* Below shows how to configure in your project if you want to use non-blocking mode.
* For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
* For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
* For ARMGCC, open CmakeLists.txt and add the following lines,
* "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
* "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
* For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
* Complier->Preprocessor".
*
*/
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
* when
* non-blocking transfer is using,
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
* If it is configured too small, log maybe missed , because the log will not be
* buffered if the buffer is full, and the print will return immediately with -1.
* And this value should be multiple of 4 to meet memory alignment.
*
*/
#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
* non-blocking transfer is using,
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
* And this value should be multiple of 4 to meet memory alignment.
*
*/
#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
/*!@ brief Whether enable the reliable TX function
* If the macro is zero, the reliable TX function of the debug console is disabled.
* When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
*/
#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
#endif /* DEBUG_CONSOLE_RX_ENABLE */
#else
#define DEBUG_CONSOLE_TRANSFER_BLOCKING
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
/*!@ brief Whether enable the RX function
* If the macro is zero, the receive function of the debug console is disabled.
*/
#ifndef DEBUG_CONSOLE_RX_ENABLE
#define DEBUG_CONSOLE_RX_ENABLE (1U)
#endif /* DEBUG_CONSOLE_RX_ENABLE */
/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
* length can not bigger than this value.
* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
* the buffer is too big and current task stack size not big enough.
*/
#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
* length can not bigger than this value.
* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
*/
#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
/*! @brief Debug console synchronization
* User should not change these macro for synchronization mode, but add the
* corresponding synchronization mechanism per different software environment.
* Such as, if another RTOS is used,
* add:
* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
* in this configuration file and implement the synchronization in fsl.log.c.
*/
/*! @brief synchronization for baremetal software */
#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
/*! @brief synchronization for freertos software */
#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
/*! @brief RTOS synchronization mechanism disable
* If not defined, default is enable, to avoid multitask log print mess.
* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
* If synchronization is disabled, log maybe messed on terminal.
*/
#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
#ifdef FSL_RTOS_FREE_RTOS
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
#else
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
#endif /* FSL_RTOS_FREE_RTOS */
#else
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
/*! @brief echo function support
* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
* at your project setting.
*/
#ifndef DEBUG_CONSOLE_ENABLE_ECHO
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
#else
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
/*********************************************************************/
/***************Debug console other configuration*********************/
/*! @brief Definition to printf the float number. */
#ifndef PRINTF_FLOAT_ENABLE
#define PRINTF_FLOAT_ENABLE 0U
#endif /* PRINTF_FLOAT_ENABLE */
/*! @brief Definition to scanf the float number. */
#ifndef SCANF_FLOAT_ENABLE
#define SCANF_FLOAT_ENABLE 0U
#endif /* SCANF_FLOAT_ENABLE */
/*! @brief Definition to support advanced format specifier for printf. */
#ifndef PRINTF_ADVANCED_ENABLE
#define PRINTF_ADVANCED_ENABLE 0U
#endif /* PRINTF_ADVANCED_ENABLE */
/*! @brief Definition to support advanced format specifier for scanf. */
#ifndef SCANF_ADVANCED_ENABLE
#define SCANF_ADVANCED_ENABLE 0U
#endif /* SCANF_ADVANCED_ENABLE */
/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
#ifndef BOARD_USE_VIRTUALCOM
#define BOARD_USE_VIRTUALCOM 0U
#endif
/*******************************************************************/
#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */

8
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_device_registers.h
View File

@ -7,6 +7,14 @@
*
*/
/**
* @file fsl_device_registers.h
* @brief device register function
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-15
*/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_enet.h
View File

@ -9,9 +9,9 @@
/**
* @file fsl_enet.h
* @brief ethernet drivers
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022-03-15
*/
#ifndef _FSL_ENET_H_

8
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_gpio.h
View File

@ -6,6 +6,14 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file fsl_gpio.h
* @brief gpio drivers
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-15
*/
#ifndef _FSL_GPIO_H_
#define _FSL_GPIO_H_

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_iomuxc.h
View File

@ -9,9 +9,9 @@
/**
* @file fsl_iomuxc.h
* @brief io mux drivers
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022-03-15
*/
#ifndef _FSL_IOMUXC_H_

12
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpi2c.h
View File

@ -7,12 +7,12 @@
*/
/**
* @file fsl_lpi2c.h
* @brief support imxrt1052-board i2c driver
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
*/
* @file fsl_lpi2c.h
* @brief support imxrt1052-board i2c driver
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-15
*/
#ifndef _FSL_LPI2C_H_
#define _FSL_LPI2C_H_

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_lpuart.h
View File

@ -9,9 +9,9 @@
/**
* @file fsl_lpuart.h
* @brief fsl uart drivers
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021.11.11
* @date 2022-03-15
*/
#ifndef _FSL_LPUART_H_

830
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h
View File

@ -1,830 +0,0 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_SEMC_H_
#define _FSL_SEMC_H_
#include "fsl_common.h"
/*!
* @addtogroup semc
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief SEMC driver version 2.0.4. */
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*@}*/
/*! @brief SEMC status. */
enum _semc_status
{
kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0),
kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1),
kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2),
kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3),
kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4),
kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5),
kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6),
kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7),
kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8),
kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10),
kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11),
};
/*! @brief SEMC memory device type. */
typedef enum _semc_mem_type
{
kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
kSEMC_MemType_SRAM, /*!< SRAM */
kSEMC_MemType_NOR, /*!< NOR */
kSEMC_MemType_NAND, /*!< NAND */
kSEMC_MemType_8080 /*!< 8080. */
} semc_mem_type_t;
/*! @brief SEMC WAIT/RDY polarity. */
typedef enum _semc_waitready_polarity
{
kSEMC_LowActive = 0, /*!< Low active. */
kSEMC_HighActive, /*!< High active. */
} semc_waitready_polarity_t;
/*! @brief SEMC SDRAM Chip selection . */
typedef enum _semc_sdram_cs
{
kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
} semc_sdram_cs_t;
/*! @brief SEMC NAND device type. */
typedef enum _semc_nand_access_type
{
kSEMC_NAND_ACCESS_BY_AXI = 0,
kSEMC_NAND_ACCESS_BY_IPCMD,
} semc_nand_access_type_t;
/*! @brief SEMC interrupts . */
typedef enum _semc_interrupt_enable
{
kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
} semc_interrupt_enable_t;
/*! @brief SEMC IP command data size in bytes. */
typedef enum _semc_ipcmd_datasize
{
kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
} semc_ipcmd_datasize_t;
/*! @brief SEMC auto-refresh timing. */
typedef enum _semc_refresh_time
{
kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
} semc_refresh_time_t;
/*! @brief CAS latency */
typedef enum _semc_caslatency
{
kSEMC_LatencyOne = 1, /*!< Latency 1. */
kSEMC_LatencyTwo, /*!< Latency 2. */
kSEMC_LatencyThree, /*!< Latency 3. */
} semc_caslatency_t;
/*! @brief SEMC sdram column address bit number. */
typedef enum _semc_sdram_column_bit_num
{
kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
kSEMC_SdramColunm_11bit, /*!< 11 bit. */
kSEMC_SdramColunm_10bit, /*!< 10 bit. */
kSEMC_SdramColunm_9bit, /*!< 9 bit. */
} semc_sdram_column_bit_num_t;
/*! @brief SEMC sdram burst length. */
typedef enum _semc_sdram_burst_len
{
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
} sem_sdram_burst_len_t;
/*! @brief SEMC nand column address bit number. */
typedef enum _semc_nand_column_bit_num
{
kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
kSEMC_NandColum_15bit, /*!< 15 bit. */
kSEMC_NandColum_14bit, /*!< 14 bit. */
kSEMC_NandColum_13bit, /*!< 13 bit. */
kSEMC_NandColum_12bit, /*!< 12 bit. */
kSEMC_NandColum_11bit, /*!< 11 bit. */
kSEMC_NandColum_10bit, /*!< 10 bit. */
kSEMC_NandColum_9bit, /*!< 9 bit. */
} semc_nand_column_bit_num_t;
/*! @brief SEMC nand burst length. */
typedef enum _semc_nand_burst_len
{
kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
} sem_nand_burst_len_t;
/*! @brief SEMC nor/sram column address bit number. */
typedef enum _semc_norsram_column_bit_num
{
kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
kSEMC_NorColum_11bit, /*!< 11 bit. */
kSEMC_NorColum_10bit, /*!< 10 bit. */
kSEMC_NorColum_9bit, /*!< 9 bit. */
kSEMC_NorColum_8bit, /*!< 8 bit. */
kSEMC_NorColum_7bit, /*!< 7 bit. */
kSEMC_NorColum_6bit, /*!< 6 bit. */
kSEMC_NorColum_5bit, /*!< 5 bit. */
kSEMC_NorColum_4bit, /*!< 4 bit. */
kSEMC_NorColum_3bit, /*!< 3 bit. */
kSEMC_NorColum_2bit /*!< 2 bit. */
} semc_norsram_column_bit_num_t;
/*! @brief SEMC nor/sram burst length. */
typedef enum _semc_norsram_burst_len
{
kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
} sem_norsram_burst_len_t;
/*! @brief SEMC dbi column address bit number. */
typedef enum _semc_dbi_column_bit_num
{
kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
} semc_dbi_column_bit_num_t;
/*! @brief SEMC dbi burst length. */
typedef enum _semc_dbi_burst_len
{
kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
} sem_dbi_burst_len_t;
/*! @brief SEMC IOMUXC. */
typedef enum _semc_iomux_pin
{
kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
} semc_iomux_pin;
/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
typedef enum _semc_iomux_nora27_pin
{
kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
} semc_iomux_nora27_pin;
/*! @brief SEMC port size. */
typedef enum _semc_port_size
{
kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
kSEMC_PortSize16Bit /*!< 16-Bit port size. */
} smec_port_size_t;
/*! @brief SEMC address mode. */
typedef enum _semc_addr_mode
{
kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
} semc_addr_mode_t;
/*! @brief SEMC DQS read strobe mode. */
typedef enum _semc_dqs_mode
{
kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
} semc_dqs_mode_t;
/*! @brief SEMC ADV signal active polarity. */
typedef enum _semc_adv_polarity
{
kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
kSEMC_AdvActivehigh, /*!< Adv active low. */
} semc_adv_polarity_t;
/*! @brief SEMC RDY signal active polarity. */
typedef enum _semc_rdy_polarity
{
kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
kSEMC_RdyActivehigh, /*!< Adv active low. */
} semc_rdy_polarity_t;
/*! @brief SEMC IP command for NAND: address mode. */
typedef enum _semc_ipcmd_nand_addrmode
{
kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
} semc_ipcmd_nand_addrmode_t;
/*! @brief SEMC IP command for NAND： command mode. */
typedef enum _semc_ipcmd_nand_cmdmode
{
kSEMC_NANDCM_Command = 0x2U, /*!< command. */
kSEMC_NANDCM_CommandHold, /*!< Command hold. */
kSEMC_NANDCM_CommandAddress, /*!< Command address. */
kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
kSEMC_NANDCM_CommandRead, /*!< Command read. */
kSEMC_NANDCM_CommandWrite, /*!< Command write. */
kSEMC_NANDCM_Read, /*!< Read. */
kSEMC_NANDCM_Write /*!< Write. */
} semc_ipcmd_nand_cmdmode_t;
/*! @brief SEMC NAND address option. */
typedef enum _semc_nand_address_option
{
kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
} semc_nand_address_option_t;
/*! @brief SEMC IP command for NOR. */
typedef enum _semc_ipcmd_nor_dbi
{
kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
kSEMC_NORDBICM_Write /*!< NOR write. */
} semc_ipcmd_nor_dbi_t;
/*! @brief SEMC IP command for SRAM. */
typedef enum _semc_ipcmd_sram
{
kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
} semc_ipcmd_sram_t;
/*! @brief SEMC IP command for SDARM. */
typedef enum _semc_ipcmd_sdram
{
kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
} semc_ipcmd_sdram_t;
/*! @brief SEMC SDRAM configuration structure.
*
* 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
* should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
* Take refer to BR0~BR3 register in RM for details.
* 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
* it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
* The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
* idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
* similar to prescalePeriod_N16Cycle.
*
*/
typedef struct _semc_sdram_config
{
semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
smec_port_size_t portSize; /*!< Port size. */
sem_sdram_burst_len_t burstLen; /*!< Burst length. */
semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_caslatency_t casLatency; /*!< CAS latency. */
uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
uint8_t refreshBurstLen; /*!< Refresh burst length. */
} semc_sdram_config_t;
/*! @brief SEMC NAND device timing configuration structure. */
typedef struct _semc_nand_timing_config
{
uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
uint8_t tReLow_Ns; /*!< RE low time: tRP. */
uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
} semc_nand_timing_config_t;
/*! @brief SEMC NAND configuration structure. */
typedef struct _semc_nand_config
{
semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
uint32_t axiAddress; /*!< The base address for AXI nand. */
uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
uint32_t ipgAddress; /*!< The base address for IPG nand . */
uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
bool edoModeEnabled; /*!< EDO mode enabled. */
semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
sem_nand_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
} semc_nand_config_t;
/*! @brief SEMC NOR configuration structure. */
typedef struct _semc_nor_config
{
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
uint8_t addrPortWidth; /*!< The address port width. */
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_addr_mode_t addrMode; /*!< Address mode. */
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
uint8_t tCeHold_Ns; /*!< The CE hold time. */
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
uint8_t tAddrHold_Ns; /*!< The address hold time. */
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
#endif
uint8_t latencyCount; /*!< Latency count for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
} semc_nor_config_t;
/*! @brief SEMC SRAM configuration structure. */
typedef struct _semc_sram_config
{
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
uint8_t addrPortWidth; /*!< The address port width. */
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
semc_addr_mode_t addrMode; /*!< Address mode. */
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
uint8_t tCeHold_Ns; /*!< The CE hold time. */
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
uint8_t tAddrHold_Ns; /*!< The address hold time. */
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
uint8_t latencyCount; /*!< Latency count for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
} semc_sram_config_t;
/*! @brief SEMC DBI configuration structure. */
typedef struct _semc_dbi_config
{
semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
sem_dbi_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
uint8_t tWexLow_Ns; /*!< WEX low time. */
uint8_t tWexHigh_Ns; /*!< WEX high time. */
uint8_t tRdxLow_Ns; /*!< RDX low time. */
uint8_t tRdxHigh_Ns; /*!< RDX high time. */
uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
} semc_dbi_config_t;
/*! @brief SEMC AXI queue a weight setting structure. */
typedef struct _semc_queuea_weight_struct
{
uint32_t qos : 4; /*!< weight of qos for queue 0 . */
uint32_t aging : 4; /*!< weight of aging for queue 0.*/
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
} semc_queuea_weight_struct_t;
/*! @brief SEMC AXI queue a weight setting union. */
typedef union _semc_queuea_weight
{
semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
} semc_queuea_weight_t;
/*! @brief SEMC AXI queue b weight setting structure. */
typedef struct _semc_queueb_weight_struct
{
uint32_t qos : 4; /*!< weight of qos for queue 1. */
uint32_t aging : 4; /*!< weight of aging for queue 1.*/
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
} semc_queueb_weight_struct_t;
/*! @brief SEMC AXI queue b weight setting union. */
typedef union _semc_queueb_weight
{
semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
} semc_queueb_weight_t;
/*! @brief SEMC AXI queue weight setting. */
typedef struct _semc_axi_queueweight
{
semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
} semc_axi_queueweight_t;
/*!
* @brief SEMC configuration structure.
*
* busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
* 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
* cmdTimeoutCycles: is used for command execution timeout cycles. it's
* similar to the busTimeoutCycles.
*/
typedef struct _semc_config_t
{
semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
} semc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name SEMC Initialization and De-initialization
* @{
*/
/*!
* @brief Gets the SEMC default basic configuration structure.
*
* The purpose of this API is to get the default SEMC
* configure structure for SEMC_Init(). User may use the initialized
* structure unchanged in SEMC_Init(), or modify some fields of the
* structure before calling SEMC_Init().
* Example:
@code
semc_config_t config;
SEMC_GetDefaultConfig(&config);
@endcode
* @param config The SEMC configuration structure pointer.
*/
void SEMC_GetDefaultConfig(semc_config_t *config);
/*!
* @brief Initializes SEMC.
* This function ungates the SEMC clock and initializes SEMC.
* This function must be called before calling any other SEMC driver functions.
*
* @param base SEMC peripheral base address.
* @param configure The SEMC configuration structure pointer.
*/
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
/*!
* @brief Deinitializes the SEMC module and gates the clock.
*
* This function gates the SEMC clock. As a result, the SEMC module doesn't work after
* calling this function, for some IDE, calling this API may cause the next downloading
* operation failed. so, please call this API cautiously. Additional, users can
* using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
* operation in drivers.
*
* @param base SEMC peripheral base address.
*/
void SEMC_Deinit(SEMC_Type *base);
/* @} */
/*!
* @name SEMC Configuration Operation For Each Memory Type
* @{
*/
/*!
* @brief Configures SDRAM controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param cs The chip selection.
* @param config The sdram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures NAND controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The nand configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures NOR controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The nor configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures SRAM controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The sram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures DBI controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The dbi configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
/* @} */
/*!
* @name SEMC Interrupt Operation
* @{
*/
/*!
* @brief Enables the SEMC interrupt.
*
* This function enables the SEMC interrupts according to the provided mask. The mask
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
* For example, to enable the IP command done and error interrupt, do the following.
* @code
* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
* @endcode
*
* @param base SEMC peripheral base address.
* @param mask SEMC interrupts to enable. This is a logical OR of the
* enumeration :: semc_interrupt_enable_t.
*/
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
{
base->INTEN |= mask;
}
/*!
* @brief Disables the SEMC interrupt.
*
* This function disables the SEMC interrupts according to the provided mask. The mask
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
* For example, to disable the IP command done and error interrupt, do the following.
* @code
* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
* @endcode
*
* @param base SEMC peripheral base address.
* @param mask SEMC interrupts to disable. This is a logical OR of the
* enumeration :: semc_interrupt_enable_t.
*/
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
{
base->INTEN &= ~mask;
}
/*!
* @brief Gets the SEMC status.
*
* This function gets the SEMC interrupts event status.
* User can use the a logical OR of enumeration member as a mask.
* See @ref semc_interrupt_enable_t.
*
* @param base SEMC peripheral base address.
* @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
*/
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
{
return base->INTR;
}
/*!
* @brief Clears the SEMC status flag state.
*
* The following status register flags can be cleared SEMC interrupt status.
*
* @param base SEMC base pointer
* @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
*/
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
{
base->INTR |= mask;
}
/* @} */
/*!
* @name SEMC Memory Access Operation
* @{
*/
/*!
* @brief Check if SEMC is in idle.
*
* @param base SEMC peripheral base address.
* @return True SEMC is in idle, false is not in idle.
*/
static inline bool SEMC_IsInIdle(SEMC_Type *base)
{
return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false;
}
/*!
* @brief SEMC IP command access.
*
* @param base SEMC peripheral base address.
* @param type SEMC memory type. refer to "semc_mem_type_t"
* @param address SEMC device address.
* @param command SEMC IP command.
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
* For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
* For SRAM device, take refer to "semc_ipcmd_sram_t".
* For SDRAM device, take refer to "semc_ipcmd_sdram_t".
* @param write Data for write access.
* @param read Data pointer for read data out.
*/
status_t SEMC_SendIPCommand(
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read);
/*!
* @brief Build SEMC IP command for NAND.
*
* This function build SEMC NAND IP command. The command is build of user command code,
* SEMC address mode and SEMC command mode.
*
* @param userCommand NAND device normal command.
* @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
* @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
*/
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
semc_ipcmd_nand_addrmode_t addrMode,
semc_ipcmd_nand_cmdmode_t cmdMode)
{
return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu);
}
/*!
* @brief Check if the NAND device is ready.
*
* @param base SEMC peripheral base address.
* @return True NAND is ready, false NAND is not ready.
*/
static inline bool SEMC_IsNandReady(SEMC_Type *base)
{
return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false;
}
/*!
* @brief SEMC NAND device memory write through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NAND device address.
* @param data Data for write access.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NAND device memory read through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NAND device address.
* @param data Data pointer for data read out.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NOR device memory write through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NOR device address.
* @param data Data for write access.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NOR device memory read through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NOR device address.
* @param data Data pointer for data read out.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_SEMC_H_*/

9
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_usdhc.h
View File

@ -5,6 +5,15 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file fsl_usdhc.h
* @brief fsl usdhc drivers
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-15
*/
#ifndef _FSL_USDHC_H_
#define _FSL_USDHC_H_

2
Ubiquitous/XiZi/board/xidatong/third_party_driver/sdio/connect_sdio.c
View File

@ -269,7 +269,7 @@ static struct SdioDevDone dev_done =
SdioRead,
};
int Imrt1052HwSdioInit(void)
int Imxrt1052HwSdioInit(void)
{
x_err_t ret = EOK;
bool is_read_only;

20
Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/connect_uart.c
View File

@ -294,21 +294,21 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialBusInit error %d\n", ret);
KPrintf("Imxrt1052HwUartInit SerialBusInit error %d\n", ret);
return ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDriverInit error %d\n", ret);
KPrintf("Imxrt1052HwUartInit SerialDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
KPrintf("Imxrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -322,20 +322,20 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
KPrintf("Imxrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
KPrintf("Imxrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
return ret;
}
int Imrt1052HwUartInit(void)
int Imxrt1052HwUartInit(void)
{
x_err_t ret = EOK;
@ -361,13 +361,13 @@ int Imrt1052HwUartInit(void)
ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
#endif
@ -394,13 +394,13 @@ int Imrt1052HwUartInit(void)
ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
#endif

2
Ubiquitous/XiZi/board/xidatong/third_party_driver/usb/connect_usb.c
View File

@ -256,7 +256,7 @@ static int BoardUsbDevBend(void)
}
/*RT1052 BOARD USB INIT*/
int Imrt1052HwUsbHostInit(void)
int Imxrt1052HwUsbHostInit(void)
{
x_err_t ret = EOK;
int32 usb_host_task = 0;

2
Ubiquitous/XiZi/kernel/thread/init.c
View File

@ -109,7 +109,7 @@ struct InitSequenceDesc env_init[] =
{ "hw usb", Stm32HwUsbInit },
#endif
#ifdef BSP_USING_NXP_USBH
{ "nxp hw usb", Imrt1052HwUsbHostInit },
{ "nxp hw usb", Imxrt1052HwUsbHostInit },
#endif
#ifdef MOUNT_SDCARD
{ "MountSDCard", MountSDCard },

22
Ubiquitous/XiZi/resources/include/dev_pin.h
View File

@ -30,23 +30,23 @@ extern "C" {
#define GPIO_LOW 0x00
#define GPIO_HIGH 0x01
#define GPIO_CFG_OUTPUT 0x00
#define GPIO_CFG_INPUT 0x01
#define GPIO_CFG_OUTPUT 0x00
#define GPIO_CFG_INPUT 0x01
#define GPIO_CFG_INPUT_PULLUP 0x02
#define GPIO_CFG_INPUT_PULLDOWN 0x03
#define GPIO_CFG_OUTPUT_OD 0x04
#define GPIO_CFG_INPUT_PULLDOWN 0x03
#define GPIO_CFG_OUTPUT_OD 0x04
#define GPIO_IRQ_EDGE_RISING 0x00
#define GPIO_IRQ_EDGE_FALLING 0x01
#define GPIO_IRQ_EDGE_FALLING 0x01
#define GPIO_IRQ_EDGE_BOTH 0x02
#define GPIO_IRQ_LEVEL_HIGH 0x03
#define GPIO_IRQ_LEVEL_LOW 0x04
#define GPIO_IRQ_LEVEL_HIGH 0x03
#define GPIO_IRQ_LEVEL_LOW 0x04
#define GPIO_CONFIG_MODE 0xffffffff
#define GPIO_IRQ_REGISTER 0xfffffffe
#define GPIO_IRQ_FREE 0xfffffffd
#define GPIO_IRQ_DISABLE 0xfffffffc
#define GPIO_IRQ_ENABLE 0xfffffffb
#define GPIO_IRQ_REGISTER 0xfffffffe
#define GPIO_IRQ_FREE 0xfffffffd
#define GPIO_IRQ_DISABLE 0xfffffffc
#define GPIO_IRQ_ENABLE 0xfffffffb
struct PinDevIrq
{