forked from xuos/xiuos
Support the M33 of the RZ/V2L development board
This commit is contained in:
anguoyoula
parent
9d546c8c02
commit
05aa2078c8
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@ -6,7 +6,7 @@ MAKEFLAGS += --no-print-directory
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riscv_support := kd233 maix-go hifive1-rev-B gapuino gd32vf103-rvstar rv32m1-vega aiit-riscv64-board xidatong-riscv64 edu-riscv64 ch32v307vct6
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arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32 xiwangtong-arm32 edu-arm32 xishutong-arm32
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arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32 xiwangtong-arm32 edu-arm32 xishutong-arm32 rzv2l-m33
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emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator cortex-m7-emulator
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support := $(riscv_support) $(arm_support) $(emulator_support)
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@ -60,4 +60,8 @@ ifeq ($(CONFIG_BOARD_NUVOTON_M2354),y)
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SRC_DIR += cortex-m23
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endif
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ifeq ($(CONFIG_BOARD_RZV2L_M33),y)
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SRC_DIR += cortex-m33
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endif
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,3 @@
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SRC_FILES := arm32_switch.c interrupt.c pendsv.S prepare_ahwstack.c syscall_gcc.S trustzone.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,49 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef ARCH_INTERRUPT_H__
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#define ARCH_INTERRUPT_H__
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#include <xs_base.h>
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#include "bsp_api.h"
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#define ARCH_MAX_IRQ_NUM (480)
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#define ARCH_IRQ_NUM_OFFSET 16
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#ifndef LIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY
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#define LIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ((1))
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#endif
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#ifndef MAX_SYSCALL_INTERRUPT_PRIORITY
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#define MAX_SYSCALL_INTERRUPT_PRIORITY (LIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - __NVIC_PRIO_BITS))
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#endif
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#define NVIC_SHPR2_REG (*((volatile uint32_t *) 0xe000ed1c))
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#define NVIC_SHPR3_REG (*((volatile uint32_t *) 0xe000ed20))
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#define MAX_INTERRUPT_PRIORITY (0UL)
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#define MIN_INTERRUPT_PRIORITY (255UL)
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#define NVIC_SVC_PRI (MAX_INTERRUPT_PRIORITY << 24UL)
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#define NVIC_PENDSV_PRI (MIN_INTERRUPT_PRIORITY << 16UL)
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#define NVIC_SYSTICK_PRI (MIN_INTERRUPT_PRIORITY << 24UL)
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#define NVIC_SVC_MASK (unsigned long) (~(0xffUL << 24UL))
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#define NVIC_PENDSV_MASK (unsigned long) (~(0xffUL << 16UL))
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#define NVIC_SYSTICK_MASK (unsigned long) (~(0xffUL << 24UL))
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#define SVC_START_FIRST_TASK 1
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int32 ArchEnableHwIrq(uint32 irq_num);
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int32 ArchDisableHwIrq(uint32 irq_num);
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int32 ArchHwIrqState(void);
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#endif
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@ -0,0 +1,191 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#include <xs_base.h>
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#include <xs_ktask.h>
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#include <hal_data.h>
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#include "arch_interrupt.h"
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#define SCB_VTOR "0xE000ED08" /* Vector Table Offset Register */
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#define NVIC_INT_CTRL "0xE000ED04" /* interrupt control state register */
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#define NVIC_SYSPRI2 "0xE000ED20" /* system priority register (2) */
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#define NVIC_PENDSV_PRI "0xFFFF0000" /* PendSV and SysTick priority value (lowest) */
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#define NVIC_PENDSVSET "0x10000000" /* value to trigger PendSV exception */
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void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context)
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{
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__asm__ volatile("LDR r3, =InterruptFromKtask");
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__asm__ volatile("STR r0, [r3]");
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__asm__ volatile("LDR r3, =InterruptToKtask");
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__asm__ volatile("STR r1, [r3]");
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__asm__ volatile("LDR r3, =InterruptToKtaskDescriptor");
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__asm__ volatile("STR r2, [r3]");
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__asm__ volatile("LDR r2, =KtaskSwitchInterruptFlag");
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__asm__ volatile("LDR r3, [r2]");
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__asm__ volatile("CMP r3, #1");
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__asm__ volatile("BEQ Arm32SwitchReswitch");
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__asm__ volatile("MOVS r3, #1");
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__asm__ volatile("STR r3, [r2]");
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__asm__ volatile("B Arm32SwitchReswitch");
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}
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void __attribute__((naked)) Arm32SwitchReswitch()
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{
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__asm__ volatile("LDR r2, =InterruptToKtask");
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__asm__ volatile("STR r1, [r2]");
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__asm__ volatile("LDR r0, =" NVIC_INT_CTRL); /* trigger the PendSV exception (causes context switch) */
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__asm__ volatile("LDR r1, =" NVIC_PENDSVSET);
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__asm__ volatile("STR r1, [r0]");
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__asm__ volatile("BX lr");
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}
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void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task)
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{
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__asm__ volatile("B HwInterruptcontextSwitch");
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}
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void SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task)
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{
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__asm__ volatile("LDR r2, =InterruptToKtask");
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__asm__ volatile("STR r0, [r2]");
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__asm__ volatile("LDR r2, =InterruptToKtaskDescriptor");
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__asm__ volatile("STR r1, [r2]");
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__asm__ volatile("LDR r1, =InterruptFromKtask");
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__asm__ volatile("MOV r0, #0x0");
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__asm__ volatile("STR r0, [r1]");
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__asm__ volatile("LDR r1, =KtaskSwitchInterruptFlag");
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__asm__ volatile("MOV r0, #1");
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__asm__ volatile("STR r0, [r1]");
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__asm__ volatile("LDR r0, =" NVIC_SYSPRI2);
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__asm__ volatile("LDR r1, =" NVIC_PENDSV_PRI);
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__asm__ volatile("LDR r2, [r0,#0x00]");
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__asm__ volatile("ORR r1,r1,r2");
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__asm__ volatile("STR r1, [r0]");
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__asm__ volatile("LDR r0, =" NVIC_INT_CTRL);
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__asm__ volatile("LDR r1, =" NVIC_PENDSVSET);
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__asm__ volatile("STR r1, [r0]");
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__asm__ volatile("LDR r0, =" SCB_VTOR);
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__asm__ volatile("LDR r0, [r0]");
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__asm__ volatile("LDR r0, [r0]");
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__asm__ volatile("NOP");
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__asm__ volatile("MSR msp, r0");
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__asm__ volatile("CPSIE F");
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__asm__ volatile("CPSIE I");
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__asm__ volatile("DSB");
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__asm__ volatile("ISB");
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}
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void __attribute__((naked)) Arm32SwitchGetSpDone()
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{
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__asm__ volatile("MRS r3, primask");
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__asm__ volatile("SUB r0, r0, #0x24");
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__asm__ volatile("STMIA r0!, {r3 - r7}");
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__asm__ volatile("MOV r3, r8");
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__asm__ volatile("MOV r4, r9");
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__asm__ volatile("MOV r5, r10");
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__asm__ volatile("MOV r6, r11");
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__asm__ volatile("STMIA r0!, {r3 - r6}");
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__asm__ volatile("SUB r0, r0, #0x24");
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__asm__ volatile("SUB r0, r0, #0x4");
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__asm__ volatile("MOV r0, lr");
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__asm__ volatile("MOV r1, lr");
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__asm__ volatile("MOV r2, #0x04");
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__asm__ volatile("TST r1, r2");
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__asm__ volatile("BEQ Arm32SwitchUpdateMsp");
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__asm__ volatile("MSR psp, r0");
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__asm__ volatile("B Arm32SwitchUpdateDone");
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__asm__ volatile("B Arm32SwitchUpdateMsp");
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}
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void __attribute__((naked)) Arm32SwitchUpdateMsp()
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{
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__asm__ volatile("MSR msp, r0");
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__asm__ volatile("B Arm32SwitchUpdateDone");
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}
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void __attribute__((naked)) Arm32SwitchUpdateDone()
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{
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__asm__ volatile("PUSH {LR}");
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__asm__ volatile("BL HwHardFaultException");
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__asm__ volatile("POP {R1}");
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__asm__ volatile("MOV lr, r1");
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__asm__ volatile("MOV r1, lr");
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__asm__ volatile("MOV r2, #0x04");
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__asm__ volatile("ORR r1, r2");
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__asm__ volatile("MOV lr, r1");
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__asm__ volatile("BX lr");
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}
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void __attribute__((naked)) MemFaultHandler()
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{
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__asm__ volatile("MRS r0, msp");
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__asm__ volatile("TST lr, #0x04");
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__asm__ volatile("MOV r1, lr");
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__asm__ volatile("MOV r2, #0x04");
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__asm__ volatile("TST r1, r2");
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__asm__ volatile("BEQ Arm32Switch1");
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__asm__ volatile("MRS r0, psp");
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__asm__ volatile("B Arm32Switch1");
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}
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void __attribute__((naked)) Arm32Switch1()
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{
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__asm__ volatile("MRS r3, primask");
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__asm__ volatile("SUB r0, r0, #0x24");
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__asm__ volatile("STMIA r0!, {r3 - r7}");
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__asm__ volatile("MOV r3, r8");
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__asm__ volatile("MOV r4, r9");
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__asm__ volatile("MOV r5, r10");
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__asm__ volatile("MOV r6, r11");
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__asm__ volatile("STMIA r0!, {r3 - r6}");
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__asm__ volatile("SUB r0, r0, #0x24");
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__asm__ volatile("SUB r0, r0, #0x4");
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__asm__ volatile("MOV r0, lr");
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__asm__ volatile("PUSH {LR}");
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__asm__ volatile("BL MemFaultHandle");
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__asm__ volatile("POP {R5}");
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__asm__ volatile("MOV lr, r5");
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__asm__ volatile("MOV r5, lr");
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__asm__ volatile("MOV r6, #0x04");
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__asm__ volatile("ORR r5, r6");
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__asm__ volatile("MOV lr, r5");
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__asm__ volatile("BX lr");
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}
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@ -0,0 +1,91 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file interrupt.c
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* @brief support arm cortex-m23 interrupt function
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* @version 1.1
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* @author AIIT XUOS Lab
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* @date 2022-02-24
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*/
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#include <xizi.h>
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#include "arch_interrupt.h"
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x_base __attribute__((naked)) DisableLocalInterrupt()
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{
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__asm__ volatile ("MRS r0, PRIMASK");
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__asm__ volatile ("CPSID I");
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__asm__ volatile ("DSB");
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__asm__ volatile ("ISB");
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__asm__ volatile ("BX LR ");
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}
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void __attribute__((naked)) EnableLocalInterrupt(x_base level)
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{
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__asm__ volatile ("MSR PRIMASK, r0");
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__asm__ volatile ("DSB");
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__asm__ volatile ("ISB");
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__asm__ volatile ("BX LR");
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}
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int32 ArchEnableHwIrq(uint32 irq_num)
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{
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R_BSP_IrqEnable(irq_num);
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return EOK;
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}
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int32 ArchDisableHwIrq(uint32 irq_num)
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{
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R_BSP_IrqDisable(irq_num);
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return EOK;
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}
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extern void KTaskOsAssignAfterIrq(void *context);
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void IsrEntry()
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{
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uint32 ipsr;
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__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
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isrManager.done->incCounter();
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isrManager.done->handleIrq(ipsr);
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KTaskOsAssignAfterIrq(NONE);
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isrManager.done->decCounter();
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}
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void UsageFault_Handler()
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{
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/* Go to infinite loop when Usage Fault exception occurs */
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while (1)
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{
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}
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}
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void BusFault_Handler()
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{
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/* Go to infinite loop when Bus Fault exception occurs */
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while (1)
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{
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}
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}
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void NMI_Handler()
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{
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while (1)
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{
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}
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}
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@ -0,0 +1,160 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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* 2012-06-01 aozima set pendsv priority to 0xFF.
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* 2012-08-17 aozima fixed bug: store r8 - r11.
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* 2013-02-20 aozima port to gcc.
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-11-04 bright fixed hardfault bug for gcc.
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* 2019-03-31 xuzhuoyi port to Cortex-M23.
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*/
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/*************************************************
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File name: pendsv.S
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Description: PendSV interrupt handler
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Others: take RT-Thread v4.0.2/libcpu/arm/cortex-m23/context_gcc.S for references
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https://github.com/RT-Thread/rt-thread/tree/v4.0.2
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History:
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1. Date: 2022-02-28
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Author: AIIT XUOS Lab
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*************************************************/
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#include <xsconfig.h>
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.cpu cortex-m4
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.syntax unified
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.thumb
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.text
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.equ SCB_VTOR, 0xE000ED08
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.equ NVIC_INT_CTRL, 0xE000ED04
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.equ NVIC_SYSPRI2, 0xE000ED20
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.equ NVIC_PENDSV_PRI, 0xFFFF0000
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.equ NVIC_PENDSVSET, 0x10000000
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/* R0 --> switch from thread stack
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* R1 --> switch to thread stack
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* psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
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*/
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.global PendSV_Handler_NS
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.type PendSV_Handler_NS, %function
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PendSV_Handler_NS:
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/* disable interrupt to protect context switch */
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MRS r2, PRIMASK
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CPSID I
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/* get KtaskSwitchInterruptFlag */
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LDR r0, =KtaskSwitchInterruptFlag /* r0 = &KtaskSwitchInterruptFlag */
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LDR r1, [r0] /* r1 = *r1 */
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CMP r1, #0x00 /* compare r1 == 0x00 */
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BNE schedule
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MSR PRIMASK, r2 /* if r1 == 0x00, do msr PRIMASK, r2 */
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BX lr /* if r1 == 0x00, do bx lr */
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schedule:
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PUSH {r2} /* store interrupt state */
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/* clear KtaskSwitchInterruptFlag to 0 */
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MOV r1, #0x00 /* r1 = 0x00 */
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STR r1, [r0] /* *r0 = r1 */
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/* skip register save at the first time */
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LDR r0, =InterruptFromKtask /* r0 = &InterruptFromKtask */
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LDR r1, [r0] /* r1 = *r0 */
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CBZ r1, switch_to_thread /* if r1 == 0, goto switch_to_thread */
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/* Whether TrustZone thread stack exists */
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LDR r1, =xz_trustzone_current_context /* r1 = &xz_trustzone_current_context */
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LDR r1, [r1] /* r1 = *r1 */
|
||||
CBZ r1, contex_ns_store /* if r1 == 0, goto contex_ns_store */
|
||||
|
||||
/*call TrustZone fun, Save TrustZone stack */
|
||||
STMFD sp!, {r0-r1, lr} /* push register */
|
||||
MOV r0, r1 /* r0 = rt_secure_current_context */
|
||||
BL xz_trustzone_context_store /* call TrustZone store fun */
|
||||
LDMFD sp!, {r0-r1, lr} /* pop register */
|
||||
|
||||
/* check break from TrustZone */
|
||||
MOV r2, lr /* r2 = lr */
|
||||
TST r2, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */
|
||||
BEQ contex_ns_store /* if r2 & 0x40 == 0, goto contex_ns_store */
|
||||
|
||||
/* push PSPLIM CONTROL PSP LR current_context to stack */
|
||||
MRS r3, psplim /* r3 = psplim */
|
||||
MRS r4, control /* r4 = control */
|
||||
MRS r5, psp /* r5 = psp */
|
||||
STMFD r5!, {r1-r4} /* push to thread stack */
|
||||
|
||||
/* update from thread stack pointer */
|
||||
LDR r0, [r0] /* r0 = rt_thread_switch_interrupt_flag */
|
||||
STR r5, [r0] /* *r0 = r5 */
|
||||
b switch_to_thread /* goto switch_to_thread */
|
||||
|
||||
contex_ns_store:
|
||||
|
||||
MRS r1, psp /* get from thread stack pointer */
|
||||
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
TST lr, #0x10 /* if(!EXC_RETURN[4]) */
|
||||
IT EQ
|
||||
VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */
|
||||
#endif
|
||||
|
||||
STMFD r1!, {r4 - r11} /* push r4 - r11 register */
|
||||
|
||||
LDR r2, =xz_trustzone_current_context /* r2 = &xz_trustzone_current_context */
|
||||
LDR r2, [r2] /* r2 = *r2 */
|
||||
MOV r3, lr /* r3 = lr */
|
||||
MRS r4, psplim /* r4 = psplim */
|
||||
MRS r5, control /* r5 = control */
|
||||
STMFD r1!, {r2-r5} /* push to thread stack */
|
||||
|
||||
LDR r0, [r0]
|
||||
STR r1, [r0] /* update from thread stack pointer */
|
||||
|
||||
switch_to_thread:
|
||||
LDR r1, =InterruptToKtask
|
||||
LDR r1, [r1]
|
||||
LDR r1, [r1] /* load thread stack pointer */
|
||||
|
||||
/* update current TrustZone context */
|
||||
LDMFD r1!, {r2-r5} /* pop thread stack */
|
||||
MSR psplim, r4 /* psplim = r4 */
|
||||
MSR control, r5 /* control = r5 */
|
||||
MOV lr, r3 /* lr = r3 */
|
||||
LDR r6, =xz_trustzone_current_context /* r6 = &xz_trustzone_current_context */
|
||||
STR r2, [r6] /* *r6 = r2 */
|
||||
MOV r0, r2 /* r0 = r2 */
|
||||
|
||||
/* Whether TrustZone thread stack exists */
|
||||
CBZ r0, contex_ns_load /* if r0 == 0, goto contex_ns_load */
|
||||
PUSH {r1, r3} /* push lr, thread_stack */
|
||||
BL xz_trustzone_context_load /* call TrustZone load fun */
|
||||
POP {r1, r3} /* pop lr, thread_stack */
|
||||
MOV lr, r3 /* lr = r1 */
|
||||
TST r3, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */
|
||||
BEQ contex_ns_load /* if r1 & 0x40 == 0, goto contex_ns_load */
|
||||
B pendsv_exit
|
||||
|
||||
contex_ns_load:
|
||||
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
|
||||
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
TST lr, #0x10 /* if(!EXC_RETURN[4]) */
|
||||
IT EQ
|
||||
VLDMIAEQ r1!, {d8 - d15} /* pop FPU register s16~s31 */
|
||||
#endif
|
||||
|
||||
pendsv_exit:
|
||||
MSR psp, r1 /* update stack pointer */
|
||||
/* restore interrupt */
|
||||
POP {r2}
|
||||
MSR PRIMASK, r2
|
||||
|
||||
BX lr
|
||||
|
|
@ -0,0 +1,426 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
#include <xs_base.h>
|
||||
#include <xs_ktask.h>
|
||||
#include <xs_assign.h>
|
||||
#include "svc_handle.h"
|
||||
#include <board.h>
|
||||
#include <xizi.h>
|
||||
#include <shell.h>
|
||||
|
||||
#if (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__))
|
||||
#define USE_FPU 1
|
||||
#else
|
||||
#define USE_FPU 0
|
||||
#endif
|
||||
|
||||
uint32 InterruptFromKtask;
|
||||
uint32 InterruptToKtask;
|
||||
uint32 KtaskSwitchInterruptFlag;
|
||||
uint32 InterruptToKtaskDescriptor;
|
||||
|
||||
#define RunningKTask Assign.os_running_task
|
||||
|
||||
static x_err_t (*ExceptionHook)(void *context) = NONE;
|
||||
|
||||
struct ExceptionStackRegister
|
||||
{
|
||||
uint32 r0;
|
||||
uint32 r1;
|
||||
uint32 r2;
|
||||
uint32 r3;
|
||||
uint32 r12;
|
||||
uint32 lr;
|
||||
uint32 pc;
|
||||
uint32 psr;
|
||||
};
|
||||
|
||||
struct StackRegisterContent
|
||||
{
|
||||
uint32 tz;
|
||||
uint32 lr;
|
||||
uint32 psplim;
|
||||
uint32 control;
|
||||
|
||||
uint32 r4;
|
||||
uint32 r5;
|
||||
uint32 r6;
|
||||
uint32 r7;
|
||||
uint32 r8;
|
||||
uint32 r9;
|
||||
uint32 r10;
|
||||
uint32 r11;
|
||||
|
||||
struct ExceptionStackRegister ExErrorStackContex;
|
||||
};
|
||||
|
||||
struct ExceptionStackFrameFpu
|
||||
{
|
||||
uint32 r0;
|
||||
uint32 r1;
|
||||
uint32 r2;
|
||||
uint32 r3;
|
||||
uint32 r12;
|
||||
uint32 lr;
|
||||
uint32 pc;
|
||||
uint32 psr;
|
||||
|
||||
#if USE_FPU
|
||||
uint32 S0;
|
||||
uint32 S1;
|
||||
uint32 S2;
|
||||
uint32 S3;
|
||||
uint32 S4;
|
||||
uint32 S5;
|
||||
uint32 S6;
|
||||
uint32 S7;
|
||||
uint32 S8;
|
||||
uint32 S9;
|
||||
uint32 S10;
|
||||
uint32 S11;
|
||||
uint32 S12;
|
||||
uint32 S13;
|
||||
uint32 S14;
|
||||
uint32 S15;
|
||||
uint32 FPSCR;
|
||||
uint32 NO_NAME;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct StackFrameFpu
|
||||
{
|
||||
uint32 flag;
|
||||
|
||||
uint32 r4;
|
||||
uint32 r5;
|
||||
uint32 r6;
|
||||
uint32 r7;
|
||||
uint32 r8;
|
||||
uint32 r9;
|
||||
uint32 r10;
|
||||
uint32 r11;
|
||||
|
||||
#if USE_FPU
|
||||
uint32 s16;
|
||||
uint32 s17;
|
||||
uint32 s18;
|
||||
uint32 s19;
|
||||
uint32 s20;
|
||||
uint32 s21;
|
||||
uint32 s22;
|
||||
uint32 s23;
|
||||
uint32 s24;
|
||||
uint32 s25;
|
||||
uint32 s26;
|
||||
uint32 s27;
|
||||
uint32 s28;
|
||||
uint32 s29;
|
||||
uint32 s30;
|
||||
uint32 s31;
|
||||
#endif
|
||||
|
||||
struct ExceptionStackFrameFpu ExErrorStackContex;
|
||||
};
|
||||
|
||||
uint8 KTaskStackSetup(struct TaskDescriptor *task)
|
||||
{
|
||||
struct StackRegisterContent* StackContex;
|
||||
int i = 0;
|
||||
|
||||
task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), 8);
|
||||
|
||||
task->stack_point -= sizeof(struct StackRegisterContent);
|
||||
|
||||
StackContex = (struct StackRegisterContent*)task->stack_point;
|
||||
|
||||
for (i = 0; i < sizeof(struct StackRegisterContent) / sizeof(uint32); i++)
|
||||
((uint32 *)StackContex)[i] = 0xfadeface;
|
||||
|
||||
StackContex->ExErrorStackContex.r0 = (unsigned long)task->task_base_info.func_param;
|
||||
StackContex->ExErrorStackContex.r1 = 0;
|
||||
StackContex->ExErrorStackContex.r2 = 0;
|
||||
StackContex->ExErrorStackContex.r3 = 0;
|
||||
StackContex->ExErrorStackContex.r12 = 0;
|
||||
StackContex->ExErrorStackContex.pc = (unsigned long)task->task_base_info.func_entry ;
|
||||
StackContex->ExErrorStackContex.psr = 0x01000000L;
|
||||
#ifdef SEPARATE_COMPILE
|
||||
if(task->task_dync_sched_member.isolation_flag == 1 ) {
|
||||
StackContex->ExErrorStackContex.lr = (unsigned long)USERSPACE->us_taskquit;
|
||||
} else {
|
||||
StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit;
|
||||
}
|
||||
#else
|
||||
StackContex->ExErrorStackContex.lr = (unsigned long)KTaskQuit;
|
||||
#endif
|
||||
|
||||
StackContex->tz = 0x00;
|
||||
#ifdef ARCH_ARM_SECURE
|
||||
StackContex->lr = 0xfffffffdL;
|
||||
#else
|
||||
StackContex->lr = 0xffffffbcL;
|
||||
#endif
|
||||
|
||||
StackContex->psplim = 0x00;
|
||||
|
||||
StackContex->control = 0x00000000L;
|
||||
|
||||
// KPrintf("KTaskStackSetup: name = %s, stack_point = %p base_stack_point = %p stack_context = %p!\n",
|
||||
// task->task_base_info.name, task->stack_point,task->task_base_info.stack_start,StackContex);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
|
||||
void HwExceptionInstall(x_err_t (*exception_handle)(void *context))
|
||||
{
|
||||
ExceptionHook = exception_handle;
|
||||
}
|
||||
|
||||
#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28)
|
||||
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C)
|
||||
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34)
|
||||
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38)
|
||||
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C)
|
||||
#define SCB_RESET_VALUE 0x05FA0004
|
||||
|
||||
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28)
|
||||
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29)
|
||||
#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A)
|
||||
|
||||
#ifdef TOOL_SHELL
|
||||
static void UsageFaultTrack(void)
|
||||
{
|
||||
KPrintf("usage fault:\n");
|
||||
KPrintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
|
||||
|
||||
if(SCB_CFSR_UFSR & (1<<0))
|
||||
KPrintf("UNDEFINSTR ");
|
||||
|
||||
if(SCB_CFSR_UFSR & (1<<1))
|
||||
KPrintf("INVSTATE ");
|
||||
|
||||
if(SCB_CFSR_UFSR & (1<<2))
|
||||
KPrintf("INVPC ");
|
||||
|
||||
if(SCB_CFSR_UFSR & (1<<3))
|
||||
KPrintf("NOCP ");
|
||||
|
||||
if(SCB_CFSR_UFSR & (1<<8))
|
||||
KPrintf("UNALIGNED ");
|
||||
|
||||
if(SCB_CFSR_UFSR & (1<<9))
|
||||
KPrintf("DIVBYZERO ");
|
||||
|
||||
KPrintf("\n");
|
||||
}
|
||||
|
||||
static void BusFaultTrack(void)
|
||||
{
|
||||
KPrintf("bus fault:\n");
|
||||
KPrintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
|
||||
|
||||
if(SCB_CFSR_BFSR & (1<<0))
|
||||
KPrintf("IBUSERR ");
|
||||
|
||||
if(SCB_CFSR_BFSR & (1<<1))
|
||||
KPrintf("PRECISERR ");
|
||||
|
||||
if(SCB_CFSR_BFSR & (1<<2))
|
||||
KPrintf("IMPRECISERR ");
|
||||
|
||||
if(SCB_CFSR_BFSR & (1<<3))
|
||||
KPrintf("UNSTKERR ");
|
||||
|
||||
if(SCB_CFSR_BFSR & (1<<4))
|
||||
KPrintf("STKERR ");
|
||||
|
||||
if(SCB_CFSR_BFSR & (1<<7))
|
||||
KPrintf("SCB->BFAR:%08X\n", SCB_BFAR);
|
||||
else
|
||||
KPrintf("\n");
|
||||
}
|
||||
|
||||
static void MemManageFaultTrack(void)
|
||||
{
|
||||
KPrintf("mem manage fault:\n");
|
||||
KPrintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
|
||||
|
||||
if(SCB_CFSR_MFSR & (1<<0))
|
||||
KPrintf("IACCVIOL ");
|
||||
if(SCB_CFSR_MFSR & (1<<1))
|
||||
KPrintf("DACCVIOL ");
|
||||
|
||||
if(SCB_CFSR_MFSR & (1<<3))
|
||||
KPrintf("MUNSTKERR ");
|
||||
|
||||
if(SCB_CFSR_MFSR & (1<<4))
|
||||
KPrintf("MSTKERR ");
|
||||
|
||||
if(SCB_CFSR_MFSR & (1<<7))
|
||||
KPrintf("SCB->MMAR:%08X\n", SCB_MMAR);
|
||||
else
|
||||
KPrintf("\n");
|
||||
}
|
||||
|
||||
static void HardFaultTrack(void)
|
||||
{
|
||||
if(SCB_HFSR & (1UL<<1))
|
||||
KPrintf("failed vector fetch\n");
|
||||
|
||||
if(SCB_HFSR & (1UL<<30)) {
|
||||
if(SCB_CFSR_BFSR)
|
||||
BusFaultTrack();
|
||||
|
||||
if(SCB_CFSR_MFSR)
|
||||
MemManageFaultTrack();
|
||||
|
||||
if(SCB_CFSR_UFSR)
|
||||
UsageFaultTrack();
|
||||
}
|
||||
|
||||
if(SCB_HFSR & (1UL<<31))
|
||||
KPrintf("debug event\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
struct ExceptionInfo
|
||||
{
|
||||
uint32 ExcReturn;
|
||||
struct StackRegisterContent stackframe;
|
||||
};
|
||||
|
||||
void HwHardFaultException(struct ExceptionInfo *ExceptionInfo)
|
||||
{
|
||||
extern long ShowTask(void);
|
||||
struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex;
|
||||
struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe;
|
||||
|
||||
if (ExceptionHook != NONE) {
|
||||
x_err_t result = ExceptionHook(ExceptionStack);
|
||||
if (result == EOK) return;
|
||||
}
|
||||
|
||||
KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr);
|
||||
KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0);
|
||||
KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1);
|
||||
KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2);
|
||||
KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3);
|
||||
KPrintf("r04: 0x%08x\n", context->r4);
|
||||
KPrintf("r05: 0x%08x\n", context->r5);
|
||||
KPrintf("r06: 0x%08x\n", context->r6);
|
||||
KPrintf("r07: 0x%08x\n", context->r7);
|
||||
KPrintf("r08: 0x%08x\n", context->r8);
|
||||
KPrintf("r09: 0x%08x\n", context->r9);
|
||||
KPrintf("r10: 0x%08x\n", context->r10);
|
||||
KPrintf("r11: 0x%08x\n", context->r11);
|
||||
//KPrintf("exc_ret: 0x%08x\n", context->exc_ret);
|
||||
KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12);
|
||||
KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr);
|
||||
KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc);
|
||||
|
||||
if (ExceptionInfo->ExcReturn & (1 << 2)) {
|
||||
KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name);
|
||||
#ifdef TOOL_SHELL
|
||||
ShowTask();
|
||||
#endif
|
||||
} else {
|
||||
KPrintf("hard fault on handler\r\n\r\n");
|
||||
}
|
||||
|
||||
if ( (ExceptionInfo->ExcReturn & 0x10) == 0)
|
||||
KPrintf("FPU active!\r\n");
|
||||
|
||||
#ifdef TOOL_SHELL
|
||||
HardFaultTrack();
|
||||
#endif
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
void UpdateRunningTask(void)
|
||||
{
|
||||
RunningKTask = (struct TaskDescriptor *)InterruptToKtaskDescriptor;
|
||||
}
|
||||
|
||||
|
||||
void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo)
|
||||
{
|
||||
extern long ShowTask(void);
|
||||
struct ExErrorStackContex* ExceptionStack = (struct ExErrorStackContex*)&ExceptionInfo->stackframe.ExErrorStackContex;
|
||||
struct StackRegisterContent* context = (struct StackRegisterContent*)&ExceptionInfo->stackframe;
|
||||
|
||||
if (ExceptionHook != NONE) {
|
||||
x_err_t result = ExceptionHook(ExceptionStack);
|
||||
if (result == EOK) return;
|
||||
}
|
||||
|
||||
KPrintf("psr: 0x%08x\n", context->ExErrorStackContex.psr);
|
||||
KPrintf("r00: 0x%08x\n", context->ExErrorStackContex.r0);
|
||||
KPrintf("r01: 0x%08x\n", context->ExErrorStackContex.r1);
|
||||
KPrintf("r02: 0x%08x\n", context->ExErrorStackContex.r2);
|
||||
KPrintf("r03: 0x%08x\n", context->ExErrorStackContex.r3);
|
||||
KPrintf("r04: 0x%08x\n", context->r4);
|
||||
KPrintf("r05: 0x%08x\n", context->r5);
|
||||
KPrintf("r06: 0x%08x\n", context->r6);
|
||||
KPrintf("r07: 0x%08x\n", context->r7);
|
||||
KPrintf("r08: 0x%08x\n", context->r8);
|
||||
KPrintf("r09: 0x%08x\n", context->r9);
|
||||
KPrintf("r10: 0x%08x\n", context->r10);
|
||||
KPrintf("r11: 0x%08x\n", context->r11);
|
||||
KPrintf("exc_ret: 0x%08x\n", ExceptionInfo->ExcReturn);
|
||||
KPrintf("r12: 0x%08x\n", context->ExErrorStackContex.r12);
|
||||
KPrintf(" lr: 0x%08x\n", context->ExErrorStackContex.lr);
|
||||
KPrintf(" pc: 0x%08x\n", context->ExErrorStackContex.pc);
|
||||
|
||||
if (ExceptionInfo->ExcReturn & (1 << 2)) {
|
||||
KPrintf("hard fault on task: %s\r\n\r\n", GetKTaskDescriptor()->task_base_info.name);
|
||||
#ifdef TOOL_SHELL
|
||||
ShowTask();
|
||||
#endif
|
||||
} else {
|
||||
KPrintf("hard fault on handler\r\n\r\n");
|
||||
}
|
||||
|
||||
if ((ExceptionInfo->ExcReturn & 0x10) == 0)
|
||||
KPrintf("FPU active!\r\n");
|
||||
|
||||
|
||||
#ifdef TOOL_SHELL
|
||||
HardFaultTrack();
|
||||
#endif
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
void MemFaultHandle(uintptr_t *sp)
|
||||
{
|
||||
#ifdef TASK_ISOLATION
|
||||
struct TaskDescriptor *task;
|
||||
task = GetKTaskDescriptor();
|
||||
if( task->task_dync_sched_member.isolation_flag == 1){
|
||||
KPrintf("\nSegmentation fault, task: %s\n", task->task_base_info.name);
|
||||
KTaskQuit();
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
MemFaultExceptionPrint((struct ExceptionInfo *)sp);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
__attribute__((weak)) void HwCpuReset(void)
|
||||
{
|
||||
SCB_AIRCR = SCB_RESET_VALUE;
|
||||
}
|
||||
// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0), Reboot, HwCpuReset, reset machine );
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-25 tyx first version
|
||||
*/
|
||||
|
||||
.cpu cortex-m4
|
||||
.syntax unified
|
||||
.thumb
|
||||
.text
|
||||
|
||||
/*
|
||||
* int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
|
||||
*/
|
||||
.global tzcall
|
||||
.type tzcall, %function
|
||||
tzcall:
|
||||
SVC 1 /* call SVC 1 */
|
||||
BX LR
|
||||
|
||||
tzcall_entry:
|
||||
PUSH {R1, R4, LR}
|
||||
MOV R4, R1 /* copy thread SP to R4 */
|
||||
LDMFD R4!, {r0 - r3} /* pop user stack, get input arg0, arg1, arg2 */
|
||||
STMFD R4!, {r0 - r3} /* push stack, user stack recovery */
|
||||
BL xz_secure_svc_handle /* call fun */
|
||||
POP {R1, R4, LR}
|
||||
STR R0, [R1] /* update return value */
|
||||
BX LR /* return to thread */
|
||||
|
||||
syscall_entry:
|
||||
BX LR /* return to user app */
|
||||
|
||||
.global SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
|
||||
/* get SP, save to R1 */
|
||||
MRS R1, MSP /* get fault context from handler. */
|
||||
TST LR, #0x04 /* if(!EXC_RETURN[2]) */
|
||||
BEQ get_sp_done
|
||||
MRS R1, PSP /* get fault context from thread. */
|
||||
get_sp_done:
|
||||
|
||||
/* get svc index */
|
||||
LDR R0, [R1, #24]
|
||||
LDRB R0, [R0, #-2]
|
||||
|
||||
/* if svc == 0, do system call */
|
||||
CMP R0, #0x0
|
||||
BEQ syscall_entry
|
||||
|
||||
/* if svc == 1, do TrustZone call */
|
||||
CMP R0, #0x1
|
||||
BEQ tzcall_entry
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-28 tyx the first version.
|
||||
*/
|
||||
|
||||
#include <xizi.h>
|
||||
|
||||
#ifdef ARM_CM33_ENABLE_TRUSTZONE
|
||||
extern void TZ_InitContextSystem_S(void);
|
||||
extern uint32 TZ_AllocModuleContext_S (uint32 module);
|
||||
extern uint32 TZ_FreeModuleContext_S(uint32 id);
|
||||
extern uint32 TZ_LoadContext_S(uint32 id);
|
||||
extern uint32 TZ_StoreContext_S(uint32 id);
|
||||
#else
|
||||
void TZ_InitContextSystem_S(void){}
|
||||
uint32 TZ_AllocModuleContext_S (uint32 module){return 0;}
|
||||
uint32 TZ_FreeModuleContext_S(uint32 id) {return 0;}
|
||||
uint32 TZ_LoadContext_S(uint32 id){return 0;};
|
||||
uint32 TZ_StoreContext_S(uint32 id){return 0;};
|
||||
#endif
|
||||
extern int tzcall(int id, x_ubase arg0, x_ubase arg1, x_ubase arg2);
|
||||
|
||||
#define TZ_INIT_CONTEXT_ID (0x1001)
|
||||
#define TZ_ALLOC_CONTEXT_ID (0x1002)
|
||||
#define TZ_FREE_CONTEXT_ID (0x1003)
|
||||
|
||||
x_ubase xz_trustzone_current_context;
|
||||
|
||||
void xz_trustzone_init(void)
|
||||
{
|
||||
static uint8 _init;
|
||||
|
||||
if (_init)
|
||||
return;
|
||||
tzcall(TZ_INIT_CONTEXT_ID, 0, 0, 0);
|
||||
_init = 1;
|
||||
}
|
||||
|
||||
int64 xz_trustzone_enter(x_ubase module)
|
||||
{
|
||||
xz_trustzone_init();
|
||||
if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0))
|
||||
{
|
||||
return EOK;
|
||||
}
|
||||
return -ERROR;
|
||||
}
|
||||
|
||||
int64 xz_trustzone_exit(void)
|
||||
{
|
||||
tzcall(TZ_FREE_CONTEXT_ID, 0, 0, 0);
|
||||
return EOK;
|
||||
}
|
||||
|
||||
void xz_trustzone_context_store(x_ubase context)
|
||||
{
|
||||
TZ_StoreContext_S(context);
|
||||
}
|
||||
|
||||
void xz_trustzone_context_load(x_ubase context)
|
||||
{
|
||||
TZ_LoadContext_S(context);
|
||||
}
|
||||
|
||||
int xz_secure_svc_handle(int svc_id, x_ubase arg0, x_ubase arg1, x_ubase arg2)
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
switch (svc_id)
|
||||
{
|
||||
case TZ_INIT_CONTEXT_ID:
|
||||
TZ_InitContextSystem_S();
|
||||
break;
|
||||
case TZ_ALLOC_CONTEXT_ID:
|
||||
res = TZ_AllocModuleContext_S(arg0);
|
||||
if (res <= 0)
|
||||
{
|
||||
KPrintf("Alloc Context Failed\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
xz_trustzone_current_context = res;
|
||||
TZ_LoadContext_S(res);
|
||||
}
|
||||
break;
|
||||
case TZ_FREE_CONTEXT_ID:
|
||||
TZ_FreeModuleContext_S(xz_trustzone_current_context);
|
||||
xz_trustzone_current_context = 0;
|
||||
break;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
mainmenu "XiZi_IIoT Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_RZV2L_M33
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "rzv2l m33 feature"
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_rzv2l_m33_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
SRC_FILES := $(wildcard *.c)
|
||||
|
||||
SRC_DIR := rzv rzv_gen src
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
# 从零开始构建矽璓工业物联操作系统：使用 RZ/V2L 开发板的Cortex-M33核心
|
||||
|
||||
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。
|
||||
|
||||
## 一、开发环境搭建
|
||||
|
||||
### 操作系统：Ubuntu 20.04 （Ubuntu 18.04也可以）
|
||||
|
||||
### 1、Ubuntu 20.04 换源 （Ubuntu 18.04可自行百度）
|
||||
|
||||
### （1）、打开sources.list文件
|
||||
|
||||
```c
|
||||
sudo vim /etc/apt/sources.list
|
||||
```
|
||||
### （2）、将以下内容复制到sources.list文件
|
||||
|
||||
```c
|
||||
deb http://mirrors.aliyun.com/ubuntu/ focal main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ focal main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ focal-security main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ focal-security main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ focal-updates main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ focal-updates main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ focal-proposed main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ focal-proposed main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ focal-backports main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ focal-backports main restricted universe multiverse
|
||||
```
|
||||
### （3）、更新源和系统软件
|
||||
|
||||
```c
|
||||
sudo apt-get update
|
||||
sudo apt-get upgrade
|
||||
```
|
||||
### 2、项目依赖包安装
|
||||
```c
|
||||
$ sudo apt install build-essential pkg-config git
|
||||
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
|
||||
```
|
||||
### 3、开发工具安装
|
||||
**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)
|
||||
|
||||
### 4、VSCode 插件安装
|
||||
**推荐安装下图所示插件：**
|
||||
<div align= "center"><img src = img/vscode-plugins.png></div>
|
||||
|
||||
### 5、XiUOS操作系统源码下载
|
||||
XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
|
||||
|
||||
新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
|
||||
|
||||
```c
|
||||
mkdir test && cd test
|
||||
git clone https://gitlink.org.cn/xuos/xiuos.git
|
||||
```
|
||||
|
||||
1、打开XiUOS源码文件包可以看到以下目录：
|
||||
| 名称 | 说明 |
|
||||
| -- | -- |
|
||||
| APP_Framework | 应用代码 |
|
||||
| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
|
||||
|
||||
2、打开XiZi内核源码文件包可以看到以下目录：
|
||||
| 名称 | 说明 |
|
||||
| -- | -- |
|
||||
| arch | 架构代码 |
|
||||
| board | 板级支持包 |
|
||||
| fs | 文件系统 |
|
||||
| kernel | 内核源码 |
|
||||
| lib | 第三方库源码 |
|
||||
| resources | 驱动文件 |
|
||||
| tool | 系统工具 |
|
||||
|
||||
使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
|
||||
|
||||
<div align= "center">
|
||||
<img src = img/vscode.jpg width =1000>
|
||||
</div>
|
||||
|
||||
### 6、裁减配置工具的下载
|
||||
|
||||
**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：
|
||||
|
||||
```c
|
||||
mkdir kfrontends && cd kfrontends
|
||||
git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
|
||||
```
|
||||
|
||||
下载源码后按以下步骤执行软件安装：
|
||||
|
||||
```c
|
||||
cd kconfig-frontends
|
||||
./xs_build.sh
|
||||
```
|
||||
|
||||
### 7、编译工具链安装
|
||||
|
||||
**下载：GNU ARM Embedded Toolchain：** gcc-arm-none-eabi-9-2019-q4-major-x86_64-linux.tar.bz2 [https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads)
|
||||
|
||||
**下载：Libgen Update for GNU ARM Embedded Toolchains：** Libgen Update (Linux) for GCC ARM Embedded Toolchains v1.2020.02 [https://gcc-renesas.com/rz/rz-download-toolchains/](https://gcc-renesas.com/rz/rz-download-toolchains/)
|
||||
|
||||
**GNU ARM Embedded Toolchain 安装位置推荐：/usr/local/arm**
|
||||
|
||||
**找到下载的工具链更新包 Libgen ，并运行以下命令：**
|
||||
```c
|
||||
sudo chmod 755 LibgenUpdateInstall_v1.2020.02.run
|
||||
sudo ./LibgenUpdateInstall_v1.2020.02.run
|
||||
```
|
||||
**运行后输入ARM工具链根目录、回车，再输入 y 以确认**
|
||||
<div align= "center"><img src = img/libgen-update.png></div>
|
||||
|
||||
**至此，编译环境已经安装完毕**
|
||||
|
||||
## 二、系统源代码编译步骤
|
||||
|
||||
### 1、编译前准备：修改编译链位置
|
||||
### （1）修改文件 xiuos/Ubiquitous/XiZi_IIoT/board/rzv2l-m33/config.mk
|
||||
``` c
|
||||
// 参照原本的数据将其修改为自己的编译链位置
|
||||
export CROSS_COMPILE ?=/usr/local/arm/gcc-arm-none-eabi-9-2019-q4-major/bin/arm-none-eabi-
|
||||
```
|
||||
### （2）修改文件 xiuos/Ubiquitous/XiZi_IIoT/board/rzv2l-m33/script/postbuild.sh
|
||||
``` c
|
||||
// 参照原本的数据将其修改为自己的目标文件位置
|
||||
inputfilename={path to}/xiuos/Ubiquitous/XiZi_IIoT/build/XiZi-rzv2l-m33.elf
|
||||
// 将 objcopy 工具路径改为自己的路径
|
||||
{path to}/gcc-arm-none-eabi-9-2019-q4-major/bin/arm-none-eabi-objcopy
|
||||
```
|
||||
### 2、编译配置
|
||||
在VScode命令终端中执行以下命令，生成配置文件
|
||||
```c
|
||||
cd ./Ubiquitous/XiZi
|
||||
make BOARD=rzv2l-m33 distclean
|
||||
make BOARD=rzv2l-m33 menuconfig
|
||||
```
|
||||
### (1)、关闭文件系统支持
|
||||
<div align= "center"><img src = img/menuconfig-filesystem.png></div>
|
||||
|
||||
**退出并保存配置**
|
||||
|
||||
### 3、编译
|
||||
在VScode命令终端中执行以下命令以开始编译
|
||||
```c
|
||||
make BOARD=rzv2l-m33
|
||||
```
|
||||
等待编译完成：生成`XiZi-rzv2l-m33.elf`等文件
|
||||
<div align= "center"><img src = img/compile-result.png></div>
|
||||
|
||||
### 4、编译输出处理
|
||||
`RZ/V2L`的`M33`端没有`FLASH`，需要借助 `boot-loader` 加载到内存中直接运行。
|
||||
同时因为内存映射跨度大，不能作为一个`bin`文件进行烧录，需要将其拆分为多个`bin`文件由`loader`逐一加载。
|
||||
```c
|
||||
// 打开VSCode中断，进入目录： Ubiquitous/XiZi_IIoT/board/rzv2l-m33/script 执行脚本 postbuild.sh
|
||||
./postbuild.sh
|
||||
```
|
||||
生成的文件：安全/非安全的中断向量表和代码数据段共四个文件
|
||||
<div align= "center"><img src = img/postbuild-output.png></div>
|
||||
|
||||
## 三、运行执行
|
||||
|
||||
### 1、BootLoader烧录
|
||||
> 参考文档：SMARC EVK of RZ/V2L Linux Start-up Guide 进行 A55 端 Linux 编译和 BootLoader 烧录
|
||||
|
||||
### 2、将生成的文件拷贝到上一步生成的SD卡里
|
||||
<div align= "center"><img src = img/copy-bin-to-sd.png></div>
|
||||
|
||||
> 在上一步中，SD被划分为两个逻辑分区，一个作为根文件系统（RZ_ext），一个用于存放系统镜像（RZ_FAT包含Linux镜像、设备数已经刚放进去的M33端程序）
|
||||
|
||||
### 3、物理连接
|
||||
|
||||
除了在第一步中需要的`CN14`口作为下载和Linux/Loader串口外，还需要为`M33`端连接串口；
|
||||
|
||||
`Pmod1`的 2、3、5 脚分别是 `TXD、RXD、GND`将其利用`USB转串口模块`与电脑相连；
|
||||
|
||||
<div align= "center"><img src = img/connection-state.jpg></div>
|
||||
|
||||
### 4、修改 boot 参数以自动加载
|
||||
```c
|
||||
// 1. 加载安全区代码的环境变量
|
||||
setenv bootcmd_m3_sec_load "fatload mmc 1:1 0x0001FF80 rzv2l_cm33_demo_secure_vector.bin; fatload mmc 1:1 0x42EFF440 rzv2l_cm33_demo_secure_code.bin"
|
||||
// 2. 加载非安全区代码的环境变量
|
||||
setenv bootcmd_m3_nosec_load "fatload mmc 1:1 0x00010000 rzv2l_cm33_demo_non_secure_vector.bin; fatload mmc 1:1 0x40010000 rzv2l_cm33_demo_non_secure_code.bin"
|
||||
// 3. 防止环境变量过长，合并文件加载
|
||||
setenv bootcmd_m3_load "run bootcmd_m3_nosec_load; run bootcmd_m3_sec_load"
|
||||
// 4. M33 启动环境变量
|
||||
setenv bootcmd_m3_start "cm33 start_debug 0x1001FF80 0x00010000"
|
||||
// 5. 合并M33启动加载环境变量
|
||||
setenv bootcmd_m3_boot "dcache off; mmc dev 1; run bootcmd_m3_load; run bootcmd_m3_start; dcache on"
|
||||
// 6. Boot会在超时后自动执行 bootcmd ，将M33的启动命令加入该环境变量
|
||||
setenv bootcmd "run bootcmd_m3_boot" // 注意：若是需要启动Linux，需要把Linux内核的启动命令也放入该环境变量
|
||||
// 7. 保存环境变量
|
||||
saveenv
|
||||
```
|
||||
**环境变量如下：**
|
||||
<div align= "center"><img src = img/loader-env.jpeg></div>
|
||||
|
||||
### 5、运行M33
|
||||
**将SD插入卡槽，按下开发板 reset 按键**
|
||||
<div align= "center"><img src = img/run-result.jpeg></div>
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
export CROSS_COMPILE ?=/usr/local/arm/gcc-arm-none-eabi-9-2019-q4-major/bin/arm-none-eabi-
|
||||
|
||||
# DEBUG
|
||||
# CFLAGS := -mthumb -mcpu=cortex-m33+nodsp+nofp -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections
|
||||
# CFLAGS += -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Wlogical-op -Waggregate-return -Wfloat-equal
|
||||
# CFLAGS += -Wnull-dereference
|
||||
# CFLAGS += -g -std=c99 -mcmse
|
||||
|
||||
# RELEASE
|
||||
CFLAGS := -mthumb -mcpu=cortex-m33+nodsp+nofp -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections
|
||||
CFLAGS += -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Wlogical-op
|
||||
CFLAGS += -Waggregate-return -Wfloat-equal -Wnull-dereference -g -std=c99 -mcmse
|
||||
|
||||
export CFLAGS
|
||||
|
||||
export LFLAGS := -mthumb -mcpu=cortex-m33+nodsp+nofp -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-rzv2l-m33.map,-cref,-u,Warm_Reset_S -T $(BSP_ROOT)/link.lds
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H
|
||||
|
||||
export ARCH = arm
|
||||
export MCU = cortex-m33
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="8">
|
||||
<generalSettings>
|
||||
<option key="#Board#" value="board.rzv2l_smarc"/>
|
||||
<option key="CPU" value="RZV2L"/>
|
||||
<option key="#TargetName#" value="R9A07G054L23GBG_CM33"/>
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
|
||||
<option key="#DeviceCommand#" value="R9A07G054L23GBG_CM33"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R9A07G054L23GBG_CM33.pincfg"/>
|
||||
<option key="#FSPVersion#" value="1.1.0"/>
|
||||
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzv2l_smarc##"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="gcc-arm-embedded"/>
|
||||
<option key="#ToolchainVersion#" value="9.2.1.20191025"/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.rzv2l.R9A07G054L23GBG_CM33">
|
||||
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.rzv2l">
|
||||
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.rz">
|
||||
<property id="config.bsp.common.secure_stack" value="0x200"/>
|
||||
<property id="config.bsp.common.main" value="0x200"/>
|
||||
<property id="config.bsp.common.heap" value="0"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||
</config>
|
||||
</raBspConfiguration>
|
||||
<raClockConfiguration>
|
||||
<node id="board.clock.osc.freq" mul="24000000" option="_edit"/>
|
||||
<node id="board.clock.iclk.freq" mul="1200000000" option="_edit"/>
|
||||
<node id="board.clock.i2clk.freq" mul="200000000" option="_edit"/>
|
||||
<node id="board.clock.gclk.freq" mul="500000000" option="_edit"/>
|
||||
<node id="board.clock.s0clk.freq" mul="12000" option="_edit"/>
|
||||
<node id="board.clock.spi0clk.freq" mul="200000000" option="_edit"/>
|
||||
<node id="board.clock.spi1clk.freq" mul="100000000" option="_edit"/>
|
||||
<node id="board.clock.sd0clk.freq" mul="533000000" option="_edit"/>
|
||||
<node id="board.clock.sd1clk.freq" mul="533000000" option="_edit"/>
|
||||
<node id="board.clock.m0clk.freq" mul="200000000" option="_edit"/>
|
||||
<node id="board.clock.m1clk.freq" mul="3000000000" option="_edit"/>
|
||||
<node id="board.clock.m2clk.freq" mul="266500000" option="_edit"/>
|
||||
<node id="board.clock.m3clk.freq" mul="3000000000" option="_edit"/>
|
||||
<node id="board.clock.m4clk.freq" mul="16656000" option="_edit"/>
|
||||
<node id="board.clock.hpclk.freq" mul="250000000" option="_edit"/>
|
||||
<node id="board.clock.tsuclk.freq" mul="80000000" option="_edit"/>
|
||||
<node id="board.clock.ztclk.freq" mul="100000000" option="_edit"/>
|
||||
<node id="board.clock.p0clk.freq" mul="100000000" option="_edit"/>
|
||||
<node id="board.clock.p1clk.freq" mul="200000000" option="_edit"/>
|
||||
<node id="board.clock.p2clk.freq" mul="100000000" option="_edit"/>
|
||||
<node id="board.clock.atclk.freq" mul="400000000" option="_edit"/>
|
||||
</raClockConfiguration>
|
||||
<raComponentSelection>
|
||||
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.7.0">
|
||||
<description>Arm CMSIS Version 5 - Core (M)</description>
|
||||
<originalPack>Arm.CMSIS5.5.7.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="Board" subgroup="rzv2l_smarc" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>Evaluation Kit RZ/V2L Support Files (RZ/V2L)</description>
|
||||
<originalPack>Renesas.RZV_board_rzv2l_smarc.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="rzv2l" subgroup="device" variant="R9A07G054L23GBG_CM33" vendor="Renesas" version="1.1.0">
|
||||
<description>Board support package for R9A07G054L23GBG_CM33</description>
|
||||
<originalPack>Renesas.RZV_mcu_rzv2l.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="rzv2l" subgroup="device" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>Board support package for RZV2L</description>
|
||||
<originalPack>Renesas.RZV_mcu_rzv2l.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="rzv2l" subgroup="fsp" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>Board support package for RZ/V2L (RZ/V2L) - FSP Data</description>
|
||||
<originalPack>Renesas.RZV_mcu_rzv2l.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="pin_config" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>Pin Configuration Template File</description>
|
||||
<originalPack>Renesas.RZV_pin_config.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>Board Support Package Common Files</description>
|
||||
<originalPack>Renesas.RZV.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>I/O Port</description>
|
||||
<originalPack>Renesas.RZV.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_scif_uart" variant="" vendor="Renesas" version="1.1.0">
|
||||
<description>SCIF UART</description>
|
||||
<originalPack>Renesas.RZV.1.1.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
</context>
|
||||
<config id="config.driver.scif_uart">
|
||||
<property id="config.driver.scif_uart.param_checking_enable" value="config.driver.scif_uart.param_checking_enable.bsp"/>
|
||||
<property id="config.driver.scif_uart.flow_control" value="config.driver.scif_uart.flow_control.disabled"/>
|
||||
</config>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<pincfg active="true" name="RZV2L-SMARC.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="p007.output.high" configurationId="p007"/>
|
||||
<configSetting altId="p007.gpio_mode.gpio_mode_out.high" configurationId="p007.gpio_mode"/>
|
||||
<configSetting altId="p008.output.high" configurationId="p008"/>
|
||||
<configSetting altId="p008.gpio_mode.gpio_mode_out.high" configurationId="p008.gpio_mode"/>
|
||||
<configSetting altId="p009.output.high" configurationId="p009"/>
|
||||
<configSetting altId="p009.gpio_mode.gpio_mode_out.high" configurationId="p009.gpio_mode"/>
|
||||
</pincfg>
|
||||
<pincfg active="false" name="R9A07G054L23GBG_CM33.pincfg" selected="false" symbol=""/>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="com.renesas.cdt.launch.dsf.gdbremote.launchConfigurationType">
|
||||
<booleanAttribute key=".setStepMode" value="false"/>
|
||||
<intAttribute key="com.renesas.cdt.core.connectionTimeout" value="30"/>
|
||||
<stringAttribute key="com.renesas.cdt.core.initCommands" value=""/>
|
||||
<stringAttribute key="com.renesas.cdt.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="com.renesas.cdt.core.jtagDeviceId" value="com.renesas.hardwaredebug.rz.jlink"/>
|
||||
<listAttribute key="com.renesas.cdt.core.listGDBExe"/>
|
||||
<listAttribute key="com.renesas.cdt.core.listGDBLaunchName">
|
||||
<listEntry value="main"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.renesas.cdt.core.listGDBPort">
|
||||
<listEntry value="61234"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="com.renesas.cdt.core.optionInitCommands" value=""/>
|
||||
<intAttribute key="com.renesas.cdt.core.portNumber" value="61234"/>
|
||||
<stringAttribute key="com.renesas.cdt.core.runCommands" value=""/>
|
||||
<stringAttribute key="com.renesas.cdt.core.secondGDBExe" value="green_dsp-elf-gdb"/>
|
||||
<intAttribute key="com.renesas.cdt.core.secondGdbPortNumber" value="61237"/>
|
||||
<stringAttribute key="com.renesas.cdt.core.serverParam" value="-g SEGGERJLINKARM -t R9A07G054L_M33 -uConnectionTimeout= 30 -uSelect= "USB" -uJLinkSetting= "${workspace_loc:/${ProjName}}/${LaunchConfigName}.jlink" -uJLinkLog= "${workspace_loc:/${ProjName}}/JLinkLog.log" -uLowPower= 0 -uInteface= "JTAG" -uIfSpeed= "4000" -uResetBeginConnection= 1 -uNoReset= 1 -uIdCodeBytes= "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" -uReleaseCM3= 0 -uDisconnectionMode= "1" -uresetOnReload= 1 -n "0" -uFlashBp= 1 -uSimulation= 0 -ueraseRomOnDownload= 0 -ueraseDataRomOnDownload= 0 -uOSRestriction= 0 -uProgReWriteIRom= 0 -uResetBehavior= "Reset""/>
|
||||
<booleanAttribute key="com.renesas.cdt.core.setResume" value="true"/>
|
||||
<stringAttribute key="com.renesas.cdt.core.targetDevice" value="R9A07G054L23GBG_CM33"/>
|
||||
<booleanAttribute key="com.renesas.cdt.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="com.renesas.cdt.launch.dsf.IO_MAP" value="${support_area_loc}"/>
|
||||
<booleanAttribute key="com.renesas.cdt.launch.dsf.USE_DEFAULT_IO_MAP" value="true"/>
|
||||
<stringAttribute key="com.renesas.cdt.launch.dsf.launchSeqType" value="com.renesas.cdt.launch.dsf.launchSequence.e2GdbServer"/>
|
||||
<stringAttribute key="com.renesas.cdt.launch.dsf.serverPath" value="${renesas.support.targetLoc:com.renesas.ide.supportfiles.rz.debug.debugSupportFileTarget}\e2-server-gdb"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.break.allowSimulation" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.break.useFlashBreakpoints.resetorrepurposed" value="true"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.cfiFlash.flashBusType" value="SPIBSC"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.cfiFlash.flashMemoryType" value="SerialFlash"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.disconnectionMode" value="1"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.id_code2" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.jlinkScript" value=""/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.registerInit" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.reset" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.resetAfterDownload" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.resetBeginConnection" value="true"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.resetCon" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.resetPreRun" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.connection.setArMModeAfterDownload" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.enable.hot.plug" value="false"/>
|
||||
<intAttribute key="com.renesas.hardwaredebug.arm.jlink.interface.speed" value="4000"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.interface.type" value="JTAG"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.jlink.logFile" value="${workspace_loc:/${ProjName}}/JLinkLog.log"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.jlink.lowPowerHandling" value="No"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.jlink.scriptFile" value=""/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.jlink.settingsFile" value="${workspace_loc:/${ProjName}}/${LaunchConfigName}.jlink"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.memory.isLittleEndian" value="true"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.nonSecureVectorAddress" value=""/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.options.ArmJLinkDebugToolSettingsTree.prog_rewrite_irom" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.options.ArmJLinkDebugToolSettingsTree.resetAfterReload" value="true"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.options.ArmJLinkDebugToolSettingsTree.rtosIntegrationInDebugView" value="true"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.options.ArmJLinkDebugToolSettingsTree.rtosintegrationthreadsrunning" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.release.reset" value="true"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.reset.PcOnReset" value=""/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.reset.behaviorOfReset" value="Reset"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.reset.setCpsrOnReset" value=""/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.scanChain.multiDevices" value="false"/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.secureVectorAddress" value=""/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.semihosting.breakpointAddress" value=""/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.setTZAuthKey" value=""/>
|
||||
<stringAttribute key="com.renesas.hardwaredebug.arm.jlink.setTZAuthLevel" value="0"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.arm.jlink.setTZBoundaries" value="false"/>
|
||||
<booleanAttribute key="com.renesas.hardwaredebug.timemeasurement" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/demo.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="demo"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/demo"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
|
||||
</launchConfiguration>
|
||||
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|
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|
After Width: | Height: | Size: 198 KiB |
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|
After Width: | Height: | Size: 52 KiB |
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|
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|
After Width: | Height: | Size: 45 KiB |
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|
After Width: | Height: | Size: 23 KiB |
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|
After Width: | Height: | Size: 46 KiB |
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|
After Width: | Height: | Size: 102 KiB |
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|
After Width: | Height: | Size: 100 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 56 KiB |
|
|
@ -0,0 +1,350 @@
|
|||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
/* Memory allocation example using ddr. */
|
||||
VECTBL_N_START = 0x00010000;
|
||||
VECTBL_N_LENGTH = 0x00000800;
|
||||
VECTBL_S_START = 0x1001FF80;
|
||||
VECTBL_S_LENGTH = 0x00000080;
|
||||
|
||||
CODE_N_START = 0x60010000;
|
||||
CODE_N_LENGTH = 0x00100000;
|
||||
RAM_N_START = 0x60110000;
|
||||
RAM_N_LENGTH = 0x02DEF440;
|
||||
CODE_S_START = 0x72EFF440;
|
||||
CODE_S_LENGTH = 0x000003C0;
|
||||
RAM_S_START = 0x72EFF800;
|
||||
RAM_S_LENGTH = 0x00000800;
|
||||
|
||||
DDR_START = 0x60010000;
|
||||
DDR_LENGTH = 0x03EF0000;
|
||||
|
||||
OPENAMP_RSCTBL_START = 0x62F00000;
|
||||
OPENAMP_RSCTBL_LENGTH = 0x00001000;
|
||||
MHU_SHMEM_START = 0x62F01000;
|
||||
MHU_SHMEM_LENGTH = 0x00001000;
|
||||
OPENAMP_VRING_START = 0x63000000;
|
||||
OPENAMP_VRING_LENGTH = 0x00800000;
|
||||
|
||||
|
||||
/* When using OpenAMP, allocate the length of the OpenAMP relevant region. */
|
||||
OPENAMP_RSCTBL_START = DEFINED(OPENAMP_RSCTBL_START) ? OPENAMP_RSCTBL_START : 0;
|
||||
OPENAMP_RSCTBL_LENGTH = DEFINED(OPENAMP_RSCTBL_LENGTH)? OPENAMP_RSCTBL_LENGTH : 0;
|
||||
MHU_SHMEM_START = DEFINED(MHU_SHMEM_START) ? MHU_SHMEM_START : 0;
|
||||
MHU_SHMEM_LENGTH = DEFINED(MHU_SHMEM_LENGTH) ? MHU_SHMEM_LENGTH : 0;
|
||||
OPENAMP_VRING_START = DEFINED(OPENAMP_VRING_START) ? OPENAMP_VRING_START : 0;
|
||||
OPENAMP_VRING_LENGTH = DEFINED(OPENAMP_VRING_LENGTH) ? OPENAMP_VRING_LENGTH : 0;
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
RAM_S (rwx) : ORIGIN = RAM_S_START, LENGTH = RAM_S_LENGTH
|
||||
RAM_N (rwx) : ORIGIN = RAM_N_START, LENGTH = RAM_N_LENGTH
|
||||
CODE_S (rx) : ORIGIN = CODE_S_START, LENGTH = CODE_S_LENGTH
|
||||
CODE_N (rx) : ORIGIN = CODE_N_START, LENGTH = CODE_N_LENGTH
|
||||
VECTTBL_S (rx) : ORIGIN = VECTBL_S_START, LENGTH = VECTBL_S_LENGTH
|
||||
VECTTBL_N (rx) : ORIGIN = VECTBL_N_START, LENGTH = VECTBL_N_LENGTH
|
||||
OPENAMP_RSCTBL(rw): ORIGIN = OPENAMP_RSCTBL_START,LENGTH = OPENAMP_RSCTBL_LENGTH
|
||||
MHU_SHMEM(rw) : ORIGIN = MHU_SHMEM_START, LENGTH = MHU_SHMEM_LENGTH
|
||||
OPENAMP_VRING(rw) : ORIGIN = OPENAMP_VRING_START, LENGTH = OPENAMP_VRING_LENGTH
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions CODE, RAM and etc.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler_S : Entry of secure reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
*/
|
||||
ENTRY(Warm_Reset_S)
|
||||
SECTIONS
|
||||
{
|
||||
__tz_VECTBL_S = ABSOLUTE(VECTBL_S_START);
|
||||
. = __tz_VECTBL_S;
|
||||
|
||||
.text.secure_vector :
|
||||
{
|
||||
/* Even though the vector table is not 16 entries (64B) long, we still allocate that much space. */
|
||||
KEEP(*(.fixed_secure_vectors*))
|
||||
} >VECTTBL_S
|
||||
|
||||
__tz_CODE_S = ABSOLUTE(CODE_S_START);
|
||||
. = __tz_CODE_S;
|
||||
|
||||
.text.secure_code :
|
||||
{
|
||||
*\bsp_security.o (.text)
|
||||
*\bsp_security.o (.text.*)
|
||||
*\bsp_security.o (.rodata)
|
||||
*\bsp_security.o (.rodata.*)
|
||||
*\bsp_irqs.o (.text)
|
||||
*\bsp_irqs.o (.text.*)
|
||||
*\bsp_irqs.o (.rodata)
|
||||
*\bsp_irqs.o (.rodata.*)
|
||||
*\startups.o (.text)
|
||||
*\startups.o (.text.*)
|
||||
*\startups.o (.rodata)
|
||||
*\startups.o (.rodata.*)
|
||||
*\systems.o (.text)
|
||||
*\systems.o (.text.*)
|
||||
*\systems.o (.rodata)
|
||||
*\systems.o (.rodata.*)
|
||||
|
||||
__CODE_S_End = .;
|
||||
} >CODE_S
|
||||
|
||||
__tz_RAM_S = ABSOLUTE(RAM_S_START);
|
||||
. = __tz_RAM_S;
|
||||
|
||||
/* secure stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD) :
|
||||
{
|
||||
__S_StackLimit = .;
|
||||
/* secure main stack */
|
||||
KEEP(*(.s_stack))
|
||||
__S_StackTop = .;
|
||||
} >RAM_S
|
||||
|
||||
/* start at address VECTBL_N_START */
|
||||
__tz_VECTBL_N = ABSOLUTE(VECTBL_N_START);
|
||||
. = __tz_VECTBL_N;
|
||||
.text.non_secure_vector :
|
||||
{
|
||||
/* Even though the vector table is not 512 entries (2KB) long, we still allocate that much space. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
} >VECTTBL_N
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
/* start at address CODE_N_START */
|
||||
__tz_CODE_N = ABSOLUTE(CODE_N_START);
|
||||
. = __tz_CODE_N;
|
||||
|
||||
.text.non_secure_code :
|
||||
{
|
||||
*(.text*)
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(* crtend?.o * crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(* crtend?.o * crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
*(.rodata*)
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
_shell_command_start = .;
|
||||
KEEP (*(shellCommand))
|
||||
_shell_command_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__isrtbl_idx_start = .;
|
||||
KEEP(*(.isrtbl.idx))
|
||||
__isrtbl_start = .;
|
||||
KEEP(*(.isrtbl))
|
||||
__isrtbl_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||
KEEP(*(.g_service_table))
|
||||
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||
|
||||
} >CODE_N
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > CODE_N
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > CODE_N
|
||||
__exidx_end = .;
|
||||
/* To copy multiple CODE_N to RAM_N sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
* .copy.table :
|
||||
* {
|
||||
* . = ALIGN(4);
|
||||
* __copy_table_start__ = .;
|
||||
* LONG (__etext)
|
||||
* LONG (__data_start__)
|
||||
* LONG (__data_end__ - __data_start__)
|
||||
* LONG (__etext2)
|
||||
* LONG (__data2_start__)
|
||||
* LONG (__data2_end__ - __data2_start__)
|
||||
* __copy_table_end__ = .;
|
||||
* } > CODE_N
|
||||
*/
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
* .zero.table :
|
||||
* {
|
||||
* . = ALIGN(4);
|
||||
* __zero_table_start__ = .;
|
||||
* LONG (__bss_start__)
|
||||
* LONG (__bss_end__ - __bss_start__)
|
||||
* LONG (__bss2_start__)
|
||||
* LONG (__bss2_end__ - __bss2_start__)
|
||||
* __zero_table_end__ = .;
|
||||
* } > CODE_N
|
||||
*/
|
||||
__etext = .;
|
||||
__tz_RAM_N = ABSOLUTE(RAM_N_START);
|
||||
. = __tz_RAM_N;
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
__Code_In_RAM_Start = .;
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN(__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN(__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN(__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN(__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN(__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN(__fini_array_end = .);
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
} > RAM_N AT > CODE_N
|
||||
.bss.noinit (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM_N
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM_N
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM_N
|
||||
/* Stacks are stored in this section. */
|
||||
.stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM_N
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
PROVIDE(__tz_RAM_C = __RAM_segment_used_end__);
|
||||
|
||||
__tz_OPENAMP_RSCTBL = ABSOLUTE(OPENAMP_RSCTBL_START);
|
||||
. = __tz_OPENAMP_RSCTBL;
|
||||
|
||||
/* OpenAMP resource table */
|
||||
.bss.resource_table (NOLOAD) :
|
||||
{
|
||||
PROVIDE(__rsctbl_start = .);
|
||||
*(.resource_table)
|
||||
PROVIDE(__rsctbl_end = .);
|
||||
} > OPENAMP_RSCTBL
|
||||
|
||||
__tz_MHU_SHMEM = ABSOLUTE(MHU_SHMEM_START);
|
||||
. = __tz_MHU_SHMEM;
|
||||
|
||||
/* MHU driver shared memory */
|
||||
.bss.mhu_shmem (NOLOAD) :
|
||||
{
|
||||
PROVIDE(__mhu_shmem_start = .);
|
||||
. += MHU_SHMEM_LENGTH;
|
||||
PROVIDE(__mhu_shmem_end = .);
|
||||
} > MHU_SHMEM
|
||||
|
||||
__tz_OPENAMP_VRING = ABSOLUTE(OPENAMP_VRING_START);
|
||||
. = __tz_OPENAMP_VRING;
|
||||
|
||||
/* OpenAMP VRINGresource table */
|
||||
.bss.vring (NOLOAD) :
|
||||
{
|
||||
PROVIDE(__vring_start = .);
|
||||
. += OPENAMP_VRING_LENGTH;
|
||||
PROVIDE(__vring_end = .);
|
||||
} > OPENAMP_VRING
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
|
||||
SRC_DIR := board/rzv2l_smarc
|
||||
SRC_DIR += fsp/src/bsp/cmsis/Device/RENESAS/Source
|
||||
SRC_DIR += fsp/src/bsp/mcu/all
|
||||
SRC_DIR += fsp/src/r_ioport
|
||||
SRC_DIR += fsp/src/r_scif_uart
|
||||
SRC_DIR += fsp/src/r_gtm
|
||||
|
||||
SRC_FILES := $(wildcard *.c)
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,411 @@
|
|||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.0
|
||||
* @date 03. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
|
|
@ -0,0 +1,885 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.2.1
|
||||
* @date 26. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,283 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,968 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.2.0
|
||||
* @date 28. January 2020
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2019 IAR Systems
|
||||
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#if __ICCARM_V8
|
||||
#define __RESTRICT __restrict
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __iar_program_start
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP CSTACK$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT CSTACK$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __vector_table
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
|
||||
#endif
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,952 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.8
|
||||
* @date 21. August 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
|
||||
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,979 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.1
|
||||
* @date 12. November 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.1
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,352 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.0
|
||||
* @date 24. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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|
||||
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|
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@ -0,0 +1,5 @@
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|||
SRC_DIR :=
|
||||
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||||
SRC_FILES := $(wildcard *.c)
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : board.h
|
||||
* Version : 1.00
|
||||
* Description : board header
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/******************************************************************************************************************//**
|
||||
* @ingroup BOARDS
|
||||
* @defgroup BOARD_RZV2L_SMARC BSP for the RZV2L-SMARC board
|
||||
* @brief BSP for the RZV2L-SMARC Board
|
||||
*
|
||||
* The RZV2L_SMARC is a evaluation kit for the Renesas R9A07G054L23GBG microcontroller in a LFBGA456 package.
|
||||
*
|
||||
* @{
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* BSP Board Specific Includes. */
|
||||
#include "board_init.h"
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
*********************************************************************************************************************/
|
||||
#define BOARD_RZV2L_SMARC
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global functions (to be accessed by other files)
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/** @} (end defgroup BOARD_RZV2L_SMARC) */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : board_init.c
|
||||
* Version : 1.00
|
||||
* Description : board_init source code
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/******************************************************************************************************************//**
|
||||
* @addtogroup BOARD_RZV2L_SMARC
|
||||
*
|
||||
* @{
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
*********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
#include "board.h"
|
||||
#include <hal_data.h>
|
||||
|
||||
#if defined(BOARD_RZV2L_SMARC)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables (to be accessed by other files)
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Private global variables and functions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/******************************************************************************************************************//**
|
||||
* @brief Performs any initialization specific to this BSP.
|
||||
*
|
||||
* @param[in] p_args Pointer to arguments of the user's choice.
|
||||
*********************************************************************************************************************/
|
||||
void bsp_init (void * p_args)
|
||||
{
|
||||
FSP_PARAMETER_NOT_USED(p_args);
|
||||
}
|
||||
|
||||
#endif /* BOARD_RZV2L_SMARC */
|
||||
|
||||
/** @} (end addtogroup BOARD_RZV2L_SMARC) */
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : board_init.h
|
||||
* Version : 1.00
|
||||
* Description : board_init header
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/******************************************************************************************************************//**
|
||||
* @addtogroup BOARD_RZV2L_SMARC
|
||||
* @brief Board specific code for the RZV2L-SMARC Board
|
||||
*
|
||||
* This include file is specific to the RZV2L-SMARC board.
|
||||
*
|
||||
* @{
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef BOARD_INIT_H
|
||||
#define BOARD_INIT_H
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
// FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
*********************************************************************************************************************/
|
||||
#ifndef MAIN_KTASK_STACK_SIZE
|
||||
#define MAIN_KTASK_STACK_SIZE 2048
|
||||
#endif
|
||||
#ifndef MAIN_KTASK_PRIORITY
|
||||
#define MAIN_KTASK_PRIORITY (KTASK_PRIORITY_MAX / 3)
|
||||
#endif
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
*********************************************************************************************************************/
|
||||
|
||||
extern int __HeapBase;
|
||||
extern int __HeapLimit;
|
||||
|
||||
#define HEAP_START (&__HeapBase)
|
||||
#define HEAP_END (&__HeapLimit)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global functions (to be accessed by other files)
|
||||
*********************************************************************************************************************/
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
// FSP_FOOTER
|
||||
|
||||
#endif /* BOARD_INIT_H */
|
||||
|
||||
/** @} (end addtogroup BOARD_RZV2L_SMARC) */
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef BSP_API_H
|
||||
#define BSP_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* FSP Common Includes. */
|
||||
#include "../../inc/fsp_common_api.h"
|
||||
|
||||
/* Gets MCU configuration information. */
|
||||
#include "bsp_cfg.h"
|
||||
|
||||
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||
|
||||
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
|
||||
* We are not modifying these files so we will ignore these warnings temporarily. */
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#endif
|
||||
|
||||
/* Vector information for this project. This is generated by the tooling. */
|
||||
#include "vector_data.h"
|
||||
|
||||
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
|
||||
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
|
||||
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
|
||||
|
||||
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||
|
||||
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
/* BSP Common Includes. */
|
||||
#include "../../src/bsp/mcu/all/bsp_common.h"
|
||||
|
||||
/* BSP MCU Specific Includes. */
|
||||
#include "../../src/bsp/mcu/all/bsp_irq.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_io.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_clocks.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_security.h"
|
||||
|
||||
/* Factory MCU information. */
|
||||
#include "../../inc/fsp_features.h"
|
||||
|
||||
/* BSP Common Includes (Other than bsp_common.h) */
|
||||
#include "../../src/bsp/mcu/all/bsp_delay.h"
|
||||
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Exported global functions (to be accessed by other files)
|
||||
**********************************************************************************************************************/
|
||||
int fsp_main(void);
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup BSP_MCU
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
|
||||
|
||||
/** @} (end addtogroup BSP_MCU) */
|
||||
|
||||
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup IOPORT_API I/O Port Interface
|
||||
* @brief Interface for accessing I/O ports and configuring I/O functionality.
|
||||
*
|
||||
* @section IOPORT_API_SUMMARY Summary
|
||||
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
|
||||
* Port and pin direction can be changed.
|
||||
*
|
||||
* IOPORT Interface description: @ref IOPORT
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_IOPORT_API_H
|
||||
#define R_IOPORT_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common error codes and definitions. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#define IOPORT_API_VERSION_MAJOR (1U)
|
||||
#define IOPORT_API_VERSION_MINOR (0U)
|
||||
|
||||
/* Private definition to set enumeration values. */
|
||||
#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** IO port type used with ports */
|
||||
typedef uint16_t ioport_size_t; ///< IO port size on this device
|
||||
|
||||
/** Superset of all peripheral functions. */
|
||||
typedef enum e_ioport_peripheral
|
||||
{
|
||||
/** Pin will function as a Mode0 peripheral pin */
|
||||
IOPORT_PERIPHERAL_MODE0 = (0x0UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a Mode1 peripheral pin */
|
||||
IOPORT_PERIPHERAL_MODE1 = (0x1UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a Mode2 peripheral pin */
|
||||
IOPORT_PERIPHERAL_MODE2 = (0x2UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a Mode3 peripheral pin */
|
||||
IOPORT_PERIPHERAL_MODE3 = (0x3UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a Mode4 peripheral pin */
|
||||
IOPORT_PERIPHERAL_MODE4 = (0x4UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Pin will function as a Mode5 peripheral pin */
|
||||
IOPORT_PERIPHERAL_MODE5 = (0x5UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||
|
||||
/** Marks end of enum - used by parameter checking */
|
||||
IOPORT_PERIPHERAL_END
|
||||
} ioport_peripheral_t;
|
||||
|
||||
/** Superset of SD channels. */
|
||||
typedef enum e_ioport_sd_ch
|
||||
{
|
||||
IOPORT_SD_CHANNEL_0 = 0x10, ///< Used to select SD channel 0
|
||||
IOPORT_SD_CHANNEL_1 = 0x20, ///< Used to select SD channel 1
|
||||
IOPORT_SD_CHANNEL_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_sd_channel_t;
|
||||
|
||||
/** Superset of QSPI channels. */
|
||||
typedef enum e_ioport_qspi_ch
|
||||
{
|
||||
IOPORT_QSPI_CHANNEL_0 = 0x10, ///< Used to select QSPI channel 0
|
||||
IOPORT_QSPI_CHANNEL_1 = 0x20, ///< Used to select QSPI channel 1
|
||||
IOPORT_QSPI_CHANNEL_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_qspi_channel_t;
|
||||
|
||||
/** Superset of Ethernet channels. */
|
||||
typedef enum e_ioport_eth_ch
|
||||
{
|
||||
IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
|
||||
IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1
|
||||
IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_ethernet_channel_t;
|
||||
|
||||
/** Superset of SD voltages. */
|
||||
typedef enum e_ioport_sd_voltage
|
||||
{
|
||||
IOPORT_SD_VOLTAGE_33 = 0x00, ///< SD voltage set to 3.3V
|
||||
IOPORT_SD_VOLTAGE_18 = 0x01, ///< SD voltage set to 1.8V
|
||||
IOPORT_SD_VOLTAGE_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_sd_voltage_t;
|
||||
|
||||
/** Superset of QSPI voltages. */
|
||||
typedef enum e_ioport_qspi_voltage
|
||||
{
|
||||
IOPORT_QSPI_VOLTAGE_33 = 0x00, ///< QSPI voltage set to 3.3V
|
||||
IOPORT_QSPI_VOLTAGE_18 = 0x01, ///< QSPI voltage set to 1.8V
|
||||
IOPORT_QSPI_VOLTAGE_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_qspi_voltage_t;
|
||||
|
||||
/** Superset of Ethernet voltages. */
|
||||
typedef enum e_ioport_eth_voltage
|
||||
{
|
||||
IOPORT_ETHERNET_VOLTAGE_33 = 0x00, ///< Ethernet voltage set to 3.3V
|
||||
IOPORT_ETHERNET_VOLTAGE_18 = 0x01, ///< Ethernet voltage set to 1.8V
|
||||
IOPORT_ETHERNET_VOLTAGE_25 = 0x02, ///< Ethernet voltage set to 2.5V
|
||||
RESERVED,
|
||||
IOPORT_ETHERNET_VOLTAGE_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_ethernet_voltage_t;
|
||||
|
||||
/** Superset of Ethernet PHY modes. */
|
||||
typedef enum e_ioport_eth_mode
|
||||
{
|
||||
IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
|
||||
IOPORT_ETHERNET_MODE_MII = 0x01, ///< Ethernet PHY mode set to RMII
|
||||
IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking
|
||||
} ioport_ethernet_mode_t;
|
||||
|
||||
/** Options to configure pin functions */
|
||||
typedef enum e_ioport_cfg_options
|
||||
{
|
||||
/* For PM Register */
|
||||
IOPORT_CFG_PORT_DIRECTION_HIZ = 0x00000000, ///< Sets the pin direction to Hi-Z (default)
|
||||
IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000004, ///< Sets the pin direction to input
|
||||
IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000008, ///< Sets the pin direction to output (input disable)
|
||||
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x0000000C, ///< Sets the pin direction to output (input enable)
|
||||
|
||||
/* For P Register */
|
||||
IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low
|
||||
IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high
|
||||
|
||||
/* For PUPD Register */
|
||||
IOPORT_CFG_PULLUP_PULLDOWN_DISABLE = 0x00000000, ///< Disable the pin's internal pull-up and pull-down
|
||||
IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up
|
||||
IOPORT_CFG_PULLDOWN_ENABLE = 0x00000020, ///< Enables the pin's internal pull-down
|
||||
|
||||
/* For IOLH Register */
|
||||
IOPORT_CFG_DRIVE_B00 = 0x00000000, ///< Sets the IOLH register value to b'00
|
||||
IOPORT_CFG_DRIVE_B01 = 0x00000400, ///< Sets the IOLH register value to b'01
|
||||
IOPORT_CFG_DRIVE_B10 = 0x00000800, ///< Sets the IOLH register value to b'10
|
||||
IOPORT_CFG_DRIVE_B11 = 0x00000C00, ///< Sets the IOLH register value to b'11
|
||||
|
||||
/* For ISEL Register */
|
||||
IOPORT_CFG_TINT_DISABLE = 0x00000000, ///< Disable IRQ functionality for a pin
|
||||
IOPORT_CFG_TINT_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin
|
||||
|
||||
/* For SR Register */
|
||||
IOPORT_CFG_SLEW_RATE_SLOW = 0x00000000, ///< Sets the pin slew-rate to slow
|
||||
IOPORT_CFG_SLEW_RATE_FAST = 0x00020000, ///< Sets the pin slew-rate to fast
|
||||
IOPORT_CFG_SLEW_RATE_FLAT = 0x00020000, ///< DEPRECATED Sets the pin slew-rate to flat
|
||||
|
||||
/* For IEN Register */
|
||||
IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_DISABLE = 0x00000000, ///< Disable input the pin of special purpose port
|
||||
IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_ENABLE = 0x00040000, ///< Sets the pin of special purpose port to input
|
||||
|
||||
/* For FILONOFF Register */
|
||||
IOPORT_CFG_NOISE_FILTER_OFF = 0x00000000, ///< Noise filter disable
|
||||
IOPORT_CFG_NOISE_FILTER_ON = 0x00080000, ///< Noise filter enable
|
||||
|
||||
/* For FILNUM Register */
|
||||
IOPORT_CFG_NOISE_FILTER_NUM_4STAGE = 0x00000000, ///< Sets the pin noise filter to 4-stage filter
|
||||
IOPORT_CFG_NOISE_FILTER_NUM_8STAGE = 0x00100000, ///< Sets the pin noise filter to 8-stage filter
|
||||
IOPORT_CFG_NOISE_FILTER_NUM_12STAGE = 0x00200000, ///< Sets the pin noise filter to 12-stage filter
|
||||
IOPORT_CFG_NOISE_FILTER_NUM_16STAGE = 0x00300000, ///< Sets the pin noise filter to 16-stage filter
|
||||
|
||||
/* For FILCLKSEL Register */
|
||||
IOPORT_CFG_NOISE_FILTER_NOT_DIVIDED = 0x00000000, ///< Noise filter not divided
|
||||
IOPORT_CFG_NOISE_FILTER_DIVIDED_9000 = 0x00400000, ///< Noise filter divided by 9000
|
||||
IOPORT_CFG_NOISE_FILTER_DIVIDED_18000 = 0x00800000, ///< Noise filter divided by 18000
|
||||
IOPORT_CFG_NOISE_FILTER_DIVIDED_36000 = 0x00C00000, ///< Noise filter divided by 36000
|
||||
|
||||
/* For PMC Register */
|
||||
IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin
|
||||
} ioport_cfg_options_t;
|
||||
|
||||
/** PFS writing enable/disable. */
|
||||
typedef enum e_ioport_pwpr
|
||||
{
|
||||
IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access
|
||||
IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access
|
||||
} ioport_pwpr_t;
|
||||
|
||||
/** Pin identifier and Pin Function Setting (PFS) value */
|
||||
typedef struct st_ioport_pin_cfg
|
||||
{
|
||||
uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure
|
||||
bsp_io_port_pin_t pin; ///< Pin identifier
|
||||
} ioport_pin_cfg_t;
|
||||
|
||||
/** Multiple pin configuration data for loading into each GPIO register by R_IOPORT_Init() */
|
||||
typedef struct st_ioport_cfg
|
||||
{
|
||||
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
|
||||
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
|
||||
} ioport_cfg_t;
|
||||
|
||||
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
|
||||
* @par Implemented as
|
||||
* - ioport_instance_ctrl_t
|
||||
*/
|
||||
typedef void ioport_ctrl_t;
|
||||
|
||||
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
|
||||
typedef struct st_ioport_api
|
||||
{
|
||||
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
|
||||
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
|
||||
* multiple pins.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_Open()
|
||||
* @param[in] p_cfg Pointer to pin configuration data array.
|
||||
*/
|
||||
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
|
||||
/** Close the API.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
**/
|
||||
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Configure multiple pins.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinsCfg()
|
||||
* @param[in] p_cfg Pointer to pin configuration data array.
|
||||
*/
|
||||
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
|
||||
/** Configure settings for an individual pin.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinCfg()
|
||||
* @param[in] pin Pin to be read.
|
||||
* @param[in] cfg Configuration options for the pin.
|
||||
*/
|
||||
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
|
||||
|
||||
/** Read the event input data of the specified pin and return the level.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinEventInputRead()
|
||||
* @param[in] pin Pin to be read.
|
||||
* @param[in] p_pin_event Pointer to return the event data.
|
||||
*/
|
||||
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
|
||||
|
||||
/** Write pin event data.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinEventOutputWrite()
|
||||
* @param[in] pin Pin event data is to be written to.
|
||||
* @param[in] pin_value Level to be written to pin output event.
|
||||
*/
|
||||
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
|
||||
|
||||
/** Configure the SD voltage of the SD channels.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_SDVoltageModeCfg()
|
||||
* @param[in] channel Channel configuration will be set for.
|
||||
* @param[in] voltage Voltage to set the channel to.
|
||||
*/
|
||||
fsp_err_t (* pinSDVoltageModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_sd_channel_t channel,
|
||||
ioport_sd_voltage_t voltage);
|
||||
|
||||
/** Configure the QSPI voltage of the QSPI channels.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_QSPIVoltageModeCfg()
|
||||
* @param[in] channel Channel configuration will be set for.
|
||||
* @param[in] voltage Voltage to set the channel to.
|
||||
*/
|
||||
fsp_err_t (* pinQSPIVoltageModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_qspi_channel_t channel,
|
||||
ioport_qspi_voltage_t voltage);
|
||||
|
||||
/** Configure the Ethernet voltage of the Ethernet channels.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_EthernetVoltageModeCfg()
|
||||
* @param[in] channel Channel configuration will be set for.
|
||||
* @param[in] voltage Voltage to set the channel to.
|
||||
*/
|
||||
fsp_err_t (* pinEthernetVoltageModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
|
||||
ioport_ethernet_voltage_t voltage);
|
||||
|
||||
/** Configure the PHY mode of the Ethernet channels.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_EthernetModeCfg()
|
||||
* @param[in] channel Channel configuration will be set for.
|
||||
* @param[in] mode PHY mode to set the channel to.
|
||||
*/
|
||||
fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
|
||||
ioport_ethernet_mode_t mode);
|
||||
|
||||
/** Read level of a pin.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinRead()
|
||||
* @param[in] pin Pin to be read.
|
||||
* @param[in] p_pin_value Pointer to return the pin level.
|
||||
*/
|
||||
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
|
||||
|
||||
/** Write specified level to a pin.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PinWrite()
|
||||
* @param[in] pin Pin to be written to.
|
||||
* @param[in] level State to be written to the pin.
|
||||
*/
|
||||
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
|
||||
|
||||
/** Set the direction of one or more pins on a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortDirectionSet()
|
||||
* @param[in] port Port being configured.
|
||||
* @param[in] direction_values Value controlling direction of pins on port
|
||||
* (3 - output (input enable), 2 - output (input disable), 1 input, 0 - Hi-Z).
|
||||
* @param[in] mask Mask controlling which pins on the port are to be configured.
|
||||
*/
|
||||
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
|
||||
ioport_size_t mask);
|
||||
|
||||
/** Read captured event data for a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortEventInputRead()
|
||||
* @param[in] port Port to be read.
|
||||
* @param[in] p_event_data Pointer to return the event data.
|
||||
*/
|
||||
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
|
||||
|
||||
/** Write event output data for a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortEventOutputWrite()
|
||||
* @param[in] port Port event data will be written to.
|
||||
* @param[in] event_data Data to be written as event data to specified port.
|
||||
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
|
||||
* being written to port.
|
||||
*/
|
||||
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
|
||||
ioport_size_t mask_value);
|
||||
|
||||
/** Read states of pins on the specified port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortRead()
|
||||
* @param[in] port Port to be read.
|
||||
* @param[in] p_port_value Pointer to return the port value.
|
||||
*/
|
||||
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
|
||||
|
||||
/** Write to multiple pins on a port.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_PortWrite()
|
||||
* @param[in] port Port to be written to.
|
||||
* @param[in] value Value to be written to the port.
|
||||
* @param[in] mask Mask controlling which pins on the port are written to.
|
||||
*/
|
||||
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
|
||||
|
||||
/* DEPRECATED Return the version of the IOPort driver.
|
||||
* @par Implemented as
|
||||
* - @ref R_IOPORT_VersionGet()
|
||||
* @param[out] p_data Memory address to return version information to.
|
||||
*/
|
||||
fsp_err_t (* versionGet)(fsp_version_t * p_data);
|
||||
} ioport_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_ioport_instance
|
||||
{
|
||||
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} ioport_instance_t;
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup IOPORT_API)
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_TIMER_API_H
|
||||
#define R_TIMER_API_H
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @defgroup TIMER_API Timer Interface
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @brief Interface for timer functions.
|
||||
*
|
||||
* @section TIMER_API_SUMMARY Summary
|
||||
* The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output,
|
||||
* and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered.
|
||||
*
|
||||
* If an instance supports output compare mode, it is provided in the extension configuration
|
||||
* timer_on_<instance>_cfg_t defined in r_<instance>.h.
|
||||
*
|
||||
* Implemented by:
|
||||
* - @ref GPT
|
||||
* - @ref GTM
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Leading zeroes removed to avoid coding standard violation. */
|
||||
#define TIMER_API_VERSION_MAJOR (1U)
|
||||
#define TIMER_API_VERSION_MINOR (1U)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Events that can trigger a callback function */
|
||||
typedef enum e_timer_event
|
||||
{
|
||||
TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around
|
||||
TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only)
|
||||
TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A
|
||||
TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B
|
||||
TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only
|
||||
} timer_event_t;
|
||||
|
||||
/** Timer variant types. */
|
||||
typedef enum e_timer_variant
|
||||
{
|
||||
TIMER_VARIANT_32_BIT, ///< 32-bit timer
|
||||
TIMER_VARIANT_16_BIT ///< 16-bit timer
|
||||
} timer_variant_t;
|
||||
|
||||
/** Callback function parameter data */
|
||||
typedef struct st_timer_callback_args
|
||||
{
|
||||
/** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */
|
||||
void const * p_context;
|
||||
timer_event_t event; ///< The event can be used to identify what caused the callback.
|
||||
|
||||
/** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */
|
||||
uint32_t capture;
|
||||
} timer_callback_args_t;
|
||||
|
||||
/** Timer control block. Allocate an instance specific control block to pass into the timer API calls.
|
||||
* @par Implemented as
|
||||
* - gpt_instance_ctrl_t
|
||||
* - gtm_instance_ctrl_t
|
||||
*/
|
||||
typedef void timer_ctrl_t;
|
||||
|
||||
/** Possible status values returned by @ref timer_api_t::statusGet. */
|
||||
typedef enum e_timer_state
|
||||
{
|
||||
TIMER_STATE_STOPPED = 0, ///< Timer is stopped
|
||||
TIMER_STATE_COUNTING = 1, ///< Timer is running
|
||||
} timer_state_t;
|
||||
|
||||
/** Timer operational modes */
|
||||
typedef enum e_timer_mode
|
||||
{
|
||||
TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses.
|
||||
TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses.
|
||||
TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output.
|
||||
TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output.
|
||||
TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output.
|
||||
} timer_mode_t;
|
||||
|
||||
/** Direction of timer count */
|
||||
typedef enum e_timer_direction
|
||||
{
|
||||
TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up
|
||||
TIMER_DIRECTION_UP = 1 ///< Timer count goes down
|
||||
} timer_direction_t;
|
||||
|
||||
/** Clock source divisors */
|
||||
typedef enum e_timer_source_div
|
||||
{
|
||||
TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1
|
||||
TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2
|
||||
TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4
|
||||
TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8
|
||||
TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16
|
||||
TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32
|
||||
TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64
|
||||
TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128
|
||||
TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256
|
||||
TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024
|
||||
} timer_source_div_t;
|
||||
|
||||
/** Timer information structure to store various information for a timer resource */
|
||||
typedef struct st_timer_info
|
||||
{
|
||||
timer_direction_t count_direction; ///< Clock counting direction of the timer.
|
||||
uint32_t clock_frequency; ///< Clock frequency of the timer counter.
|
||||
|
||||
/** Period in raw timer counts.
|
||||
* @note For triangle wave PWM modes, the full period is double this value.
|
||||
*/
|
||||
uint32_t period_counts;
|
||||
} timer_info_t;
|
||||
|
||||
/** Current timer status. */
|
||||
typedef struct st_timer_status
|
||||
{
|
||||
uint32_t counter; ///< Current counter value
|
||||
timer_state_t state; ///< Current timer state (running or stopped)
|
||||
} timer_status_t;
|
||||
|
||||
/** User configuration structure, used in open function */
|
||||
typedef struct st_timer_cfg
|
||||
{
|
||||
timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t
|
||||
|
||||
/* Period in raw timer counts.
|
||||
* @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period.
|
||||
*/
|
||||
uint32_t period_counts; ///< Period in raw timer counts
|
||||
timer_source_div_t source_div; ///< Source clock divider
|
||||
uint32_t duty_cycle_counts; ///< Duty cycle in counts
|
||||
|
||||
/** Select a channel corresponding to the channel number of the hardware. */
|
||||
uint8_t channel;
|
||||
uint8_t cycle_end_ipl; ///< Cycle end interrupt priority
|
||||
IRQn_Type cycle_end_irq; ///< Cycle end interrupt
|
||||
|
||||
/** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */
|
||||
void (* p_callback)(timer_callback_args_t * p_args);
|
||||
|
||||
/** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */
|
||||
void const * p_context;
|
||||
void const * p_extend; ///< Extension parameter for hardware specific settings.
|
||||
} timer_cfg_t;
|
||||
|
||||
/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */
|
||||
typedef struct st_timer_api
|
||||
{
|
||||
/** Initial configuration.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Open()
|
||||
* - @ref R_GTM_Open()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user.
|
||||
*/
|
||||
fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
|
||||
|
||||
/** Start the counter.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Start()
|
||||
* - @ref R_GTM_Start()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* start)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Stop the counter.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Stop()
|
||||
* - @ref R_GTM_Stop()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Reset the counter to the initial value.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Reset()
|
||||
* - @ref R_GTM_Reset()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Enables input capture.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Enable()
|
||||
* - @ref R_GTM_Enable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Disables input capture.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Disable()
|
||||
* - @ref R_GTM_Disable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Set the time until the timer expires. See implementation for details of period update timing.
|
||||
*
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_PeriodSet()
|
||||
* - @ref R_GTM_PeriodSet()
|
||||
*
|
||||
* @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in
|
||||
* @ref timer_api_t::open.
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[in] p_period Time until timer should expire.
|
||||
*/
|
||||
fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period);
|
||||
|
||||
/** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is
|
||||
* reflected after the next timer expiration.
|
||||
*
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_DutyCycleSet()
|
||||
* - @ref R_GTM_DutyCycleSet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[in] duty_cycle_counts Time until duty cycle should expire.
|
||||
* @param[in] pin Which output pin to update. See implementation for details.
|
||||
*/
|
||||
fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
|
||||
|
||||
/** Stores timer information in p_info.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_InfoGet()
|
||||
* - @ref R_GTM_InfoGet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[out] p_info Collection of information for this timer.
|
||||
*/
|
||||
fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
|
||||
|
||||
/** Get the current counter value and timer state and store it in p_status.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_StatusGet()
|
||||
* - @ref R_GTM_StatusGet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[out] p_status Current status of this timer.
|
||||
*/
|
||||
fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
|
||||
|
||||
/** Specify callback function and optional context pointer and working memory pointer.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_CallbackSet()
|
||||
* - @ref R_GTM_CallbackSet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[in] p_callback Callback function to register
|
||||
* @param[in] p_context Pointer to send to callback function
|
||||
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||
* Callback arguments allocated here are only valid during the callback.
|
||||
*/
|
||||
fsp_err_t (* callbackSet)(timer_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *),
|
||||
void const * const p_context, timer_callback_args_t * const p_callback_memory);
|
||||
|
||||
/** Allows driver to be reconfigured and may reduce power consumption.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Close()
|
||||
* - @ref R_GTM_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* close)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/* DEPRECATED Get version and store it in provided pointer p_version.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_VersionGet()
|
||||
* - @ref R_GTM_VersionGet()
|
||||
*
|
||||
* @param[out] p_version Code and API version used.
|
||||
*/
|
||||
fsp_err_t (* versionGet)(fsp_version_t * const p_version);
|
||||
} timer_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_timer_instance
|
||||
{
|
||||
timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
timer_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} timer_instance_t;
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup TIMER_API)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,355 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup TRANSFER_API Transfer Interface
|
||||
*
|
||||
* @brief Interface for data transfer functions.
|
||||
*
|
||||
* @section TRANSFER_API_SUMMARY Summary
|
||||
* The transfer interface supports background data transfer (no CPU intervention).
|
||||
*
|
||||
* Implemented by:
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_TRANSFER_API_H
|
||||
#define R_TRANSFER_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common error codes and definitions. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#define TRANSFER_API_VERSION_MAJOR (1U)
|
||||
#define TRANSFER_API_VERSION_MINOR (0U)
|
||||
|
||||
#define TRANSFER_SETTINGS_MODE_BITS (30U)
|
||||
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
|
||||
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
|
||||
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
|
||||
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
|
||||
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
|
||||
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
|
||||
* @par Implemented as
|
||||
* - dtc_instance_ctrl_t
|
||||
* - dmac_instance_ctrl_t
|
||||
*/
|
||||
typedef void transfer_ctrl_t;
|
||||
|
||||
/** Transfer mode describes what will happen when a transfer request occurs. */
|
||||
typedef enum e_transfer_mode
|
||||
{
|
||||
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
|
||||
* the destination pointer. The transfer length is decremented and the source and address pointers are
|
||||
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
|
||||
* will not cause any further transfers. */
|
||||
TRANSFER_MODE_NORMAL = 0,
|
||||
|
||||
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
|
||||
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
|
||||
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
|
||||
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
|
||||
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
|
||||
TRANSFER_MODE_REPEAT = 1,
|
||||
|
||||
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
|
||||
* After each individual transfer, the source and destination pointers are updated according to
|
||||
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
|
||||
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
|
||||
* further transfers. */
|
||||
TRANSFER_MODE_BLOCK = 2
|
||||
} transfer_mode_t;
|
||||
|
||||
/** Transfer size specifies the size of each individual transfer.
|
||||
* Total transfer length = transfer_size_t * transfer_length_t
|
||||
*/
|
||||
typedef enum e_transfer_size
|
||||
{
|
||||
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
|
||||
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
|
||||
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
|
||||
} transfer_size_t;
|
||||
|
||||
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
|
||||
typedef enum e_transfer_addr_mode
|
||||
{
|
||||
/** Address pointer remains fixed after each transfer. */
|
||||
TRANSFER_ADDR_MODE_FIXED = 0,
|
||||
|
||||
/** Offset is added to the address pointer after each transfer. */
|
||||
TRANSFER_ADDR_MODE_OFFSET = 1,
|
||||
|
||||
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
|
||||
TRANSFER_ADDR_MODE_INCREMENTED = 2,
|
||||
|
||||
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
|
||||
TRANSFER_ADDR_MODE_DECREMENTED = 3
|
||||
} transfer_addr_mode_t;
|
||||
|
||||
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
|
||||
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK, the selected pointer
|
||||
* returns to its original value after each transfer. */
|
||||
typedef enum e_transfer_repeat_area
|
||||
{
|
||||
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK. */
|
||||
TRANSFER_REPEAT_AREA_DESTINATION = 0,
|
||||
|
||||
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK. */
|
||||
TRANSFER_REPEAT_AREA_SOURCE = 1
|
||||
} transfer_repeat_area_t;
|
||||
|
||||
/** Chain transfer mode options.
|
||||
* @note Only applies for DTC. */
|
||||
typedef enum e_transfer_chain_mode
|
||||
{
|
||||
/** Chain mode not used. */
|
||||
TRANSFER_CHAIN_MODE_DISABLED = 0,
|
||||
|
||||
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
|
||||
TRANSFER_CHAIN_MODE_EACH = 2,
|
||||
|
||||
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
|
||||
TRANSFER_CHAIN_MODE_END = 3
|
||||
} transfer_chain_mode_t;
|
||||
|
||||
/** Interrupt options. */
|
||||
typedef enum e_transfer_irq
|
||||
{
|
||||
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
|
||||
* the interrupt will occur only after subsequent chained transfer(s) are complete.
|
||||
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
|
||||
* prevent activation source interrupts until the transfer is complete. */
|
||||
TRANSFER_IRQ_END = 0,
|
||||
|
||||
/** Interrupt occurs after each transfer.
|
||||
* @note Not available in all HAL drivers. See HAL driver for details. */
|
||||
TRANSFER_IRQ_EACH = 1
|
||||
} transfer_irq_t;
|
||||
|
||||
/** Driver specific information. */
|
||||
typedef struct st_transfer_properties
|
||||
{
|
||||
uint32_t block_count_max; ///< Maximum number of blocks
|
||||
uint32_t block_count_remaining; ///< Number of blocks remaining
|
||||
uint32_t transfer_length_max; ///< Maximum number of transfers
|
||||
uint32_t transfer_length_remaining; ///< Number of transfers remaining
|
||||
} transfer_properties_t;
|
||||
|
||||
/** This structure specifies the properties of the transfer.
|
||||
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
|
||||
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
|
||||
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
|
||||
* have a unique transfer_info_t.
|
||||
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
|
||||
* structure must remain in scope until the transfer it is used for is closed.
|
||||
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
|
||||
typedef struct st_transfer_info
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t : 16;
|
||||
uint32_t : 2;
|
||||
|
||||
/** Select what happens to destination pointer after each transfer. */
|
||||
transfer_addr_mode_t dest_addr_mode : 2;
|
||||
|
||||
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
|
||||
transfer_repeat_area_t repeat_area : 1;
|
||||
|
||||
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
|
||||
* transfers. */
|
||||
transfer_irq_t irq : 1;
|
||||
|
||||
/** Select when the chain transfer ends. */
|
||||
transfer_chain_mode_t chain_mode : 2;
|
||||
|
||||
uint32_t : 2;
|
||||
|
||||
/** Select what happens to source pointer after each transfer. */
|
||||
transfer_addr_mode_t src_addr_mode : 2;
|
||||
|
||||
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
|
||||
transfer_size_t size : 2;
|
||||
|
||||
/** Select mode from @ref transfer_mode_t. */
|
||||
transfer_mode_t mode : 2;
|
||||
};
|
||||
uint32_t transfer_settings_word;
|
||||
};
|
||||
|
||||
void const * volatile p_src; ///< Source pointer
|
||||
void * volatile p_dest; ///< Destination pointer
|
||||
|
||||
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) and
|
||||
* @ref TRANSFER_MODE_REPEAT (DMAC only), unused in other modes. */
|
||||
volatile uint16_t num_blocks;
|
||||
|
||||
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT,
|
||||
* see HAL driver for details. */
|
||||
volatile uint16_t length;
|
||||
} transfer_info_t;
|
||||
|
||||
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
|
||||
* initialized. */
|
||||
typedef struct st_transfer_cfg
|
||||
{
|
||||
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
|
||||
* an array of chained transfers that will be completed in order. */
|
||||
transfer_info_t * p_info;
|
||||
|
||||
void const * p_extend; ///< Extension parameter for hardware specific settings.
|
||||
} transfer_cfg_t;
|
||||
|
||||
/** Select whether to start single or repeated transfer with software start. */
|
||||
typedef enum e_transfer_start_mode
|
||||
{
|
||||
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
|
||||
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
|
||||
} transfer_start_mode_t;
|
||||
|
||||
/** Transfer functions implemented at the HAL layer will follow this API. */
|
||||
typedef struct st_transfer_api
|
||||
{
|
||||
/** Initial configuration.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
|
||||
* must be set by user.
|
||||
*/
|
||||
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
|
||||
|
||||
/** Reconfigure the transfer.
|
||||
* Enable the transfer if p_info is valid.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||
* @param[in] p_info Pointer to a new transfer info structure.
|
||||
*/
|
||||
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
|
||||
|
||||
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
|
||||
* Enable the transfer if p_src, p_dest, and length are valid.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
|
||||
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
|
||||
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
|
||||
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
|
||||
* repeat mode. Not used in repeat mode for DTC.
|
||||
*/
|
||||
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
|
||||
uint16_t const num_transfers);
|
||||
|
||||
/** Enable transfer. Transfers occur after the activation source event (or when
|
||||
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source).
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Disable transfer. Transfers do not occur after the activation source event (or when
|
||||
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source).
|
||||
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
|
||||
* transfer.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Start transfer in software.
|
||||
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
|
||||
* @note Not supported for DTC.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
* @param[in] mode Select mode from @ref transfer_start_mode_t.
|
||||
*/
|
||||
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
|
||||
|
||||
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
|
||||
* @note Not supported for DTC.
|
||||
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
|
||||
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Provides information about this transfer.
|
||||
* @par Implemented as
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
* @param[out] p_properties Driver specific information.
|
||||
*/
|
||||
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
|
||||
|
||||
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
|
||||
* @par Implemented as
|
||||
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||
*/
|
||||
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
|
||||
|
||||
/* DEPRECATED Gets version and stores it in provided pointer p_version.
|
||||
* @par Implemented as
|
||||
* @param[out] p_version Code and API version used.
|
||||
*/
|
||||
fsp_err_t (* versionGet)(fsp_version_t * const p_version);
|
||||
} transfer_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_transfer_instance
|
||||
{
|
||||
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} transfer_instance_t;
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup TRANSFER_API)
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup UART_API UART Interface
|
||||
* @brief Interface for UART communications.
|
||||
*
|
||||
* @section UART_INTERFACE_SUMMARY Summary
|
||||
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
|
||||
* - Full-duplex UART communication
|
||||
* - Interrupt driven transmit/receive processing
|
||||
* - Callback function with returned event code
|
||||
* - Runtime baud-rate change
|
||||
* - Hardware resource locking during a transaction
|
||||
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
|
||||
*
|
||||
* Implemented by:
|
||||
* - @ref SCIF_UART
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_UART_API_H
|
||||
#define R_UART_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
#include "r_transfer_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#define UART_API_VERSION_MAJOR (1U)
|
||||
#define UART_API_VERSION_MINOR (1U)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** UART Event codes */
|
||||
typedef enum e_sf_event
|
||||
{
|
||||
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
|
||||
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
|
||||
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
|
||||
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
|
||||
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
|
||||
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
|
||||
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
|
||||
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
|
||||
} uart_event_t;
|
||||
|
||||
/** UART Data bit length definition */
|
||||
typedef enum e_uart_data_bits
|
||||
{
|
||||
UART_DATA_BITS_8, ///< Data bits 8-bit
|
||||
UART_DATA_BITS_7, ///< Data bits 7-bit
|
||||
UART_DATA_BITS_9 ///< Data bits 9-bit
|
||||
} uart_data_bits_t;
|
||||
|
||||
/** UART Parity definition */
|
||||
typedef enum e_uart_parity
|
||||
{
|
||||
UART_PARITY_OFF = 0U, ///< No parity
|
||||
UART_PARITY_EVEN = 2U, ///< Even parity
|
||||
UART_PARITY_ODD = 3U, ///< Odd parity
|
||||
} uart_parity_t;
|
||||
|
||||
/** UART Stop bits definition */
|
||||
typedef enum e_uart_stop_bits
|
||||
{
|
||||
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
|
||||
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
|
||||
} uart_stop_bits_t;
|
||||
|
||||
/** UART transaction definition */
|
||||
typedef enum e_uart_dir
|
||||
{
|
||||
UART_DIR_RX_TX = 3U, ///< Both RX and TX
|
||||
UART_DIR_RX = 1U, ///< Only RX
|
||||
UART_DIR_TX = 2U, ///< Only TX
|
||||
} uart_dir_t;
|
||||
|
||||
/** UART driver specific information */
|
||||
typedef struct st_uart_info
|
||||
{
|
||||
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
|
||||
uint32_t write_bytes_max;
|
||||
|
||||
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
|
||||
uint32_t read_bytes_max;
|
||||
} uart_info_t;
|
||||
|
||||
/** UART Callback parameter definition */
|
||||
typedef struct st_uart_callback_arg
|
||||
{
|
||||
uint32_t channel; ///< Device channel number
|
||||
uart_event_t event; ///< Event code
|
||||
|
||||
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
|
||||
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
|
||||
uint32_t data;
|
||||
void const * p_context; ///< Context provided to user during callback
|
||||
} uart_callback_args_t;
|
||||
|
||||
/** UART Configuration */
|
||||
typedef struct st_uart_cfg
|
||||
{
|
||||
/* UART generic configuration */
|
||||
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
|
||||
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
|
||||
uart_parity_t parity; ///< Parity type (none or odd or even)
|
||||
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
|
||||
uint8_t rxi_ipl; ///< Receive interrupt priority
|
||||
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
|
||||
uint8_t txi_ipl; ///< Transmit interrupt priority
|
||||
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
|
||||
uint8_t tei_ipl; ///< Transmit end interrupt priority
|
||||
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
|
||||
uint8_t eri_ipl; ///< Error interrupt priority
|
||||
IRQn_Type eri_irq; ///< Error interrupt IRQ number
|
||||
|
||||
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
|
||||
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
|
||||
transfer_instance_t const * p_transfer_rx;
|
||||
|
||||
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
|
||||
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
|
||||
transfer_instance_t const * p_transfer_tx;
|
||||
|
||||
/* Configuration for UART Event processing */
|
||||
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
|
||||
void const * p_context; ///< User defined context passed into callback function
|
||||
|
||||
/* Pointer to UART peripheral specific configuration */
|
||||
void const * p_extend; ///< UART hardware dependent configuration
|
||||
} uart_cfg_t;
|
||||
|
||||
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
|
||||
* @par Implemented as
|
||||
* - scif_uart_instance_ctrl_t
|
||||
*/
|
||||
typedef void uart_ctrl_t;
|
||||
|
||||
/** Shared Interface definition for UART */
|
||||
typedef struct st_uart_api
|
||||
{
|
||||
/** Open UART device.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_Open()
|
||||
*
|
||||
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
|
||||
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
|
||||
* user.
|
||||
*/
|
||||
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
|
||||
|
||||
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
|
||||
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
|
||||
* the callback function with event UART_EVENT_RX_CHAR.
|
||||
* The maximum transfer size is reported by infoGet().
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_Read()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block for the channel.
|
||||
* @param[in] p_dest Destination address to read data from.
|
||||
* @param[in] bytes Read data length.
|
||||
*/
|
||||
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
|
||||
|
||||
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
|
||||
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
|
||||
* the callback called with event UART_EVENT_TX_COMPLETE.
|
||||
* The maximum transfer size is reported by infoGet().
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_Write()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] p_src Source address to write data to.
|
||||
* @param[in] bytes Write data length.
|
||||
*/
|
||||
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
|
||||
|
||||
/** Change baud rate.
|
||||
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
|
||||
* settings have been applied.
|
||||
*
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_BaudSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
|
||||
*/
|
||||
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
|
||||
|
||||
/** Get the driver specific information.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_InfoGet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] baudrate Baud rate in bps.
|
||||
*/
|
||||
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
|
||||
|
||||
/**
|
||||
* Abort ongoing transfer.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_Abort()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
* @param[in] communication_to_abort Type of abort request.
|
||||
*/
|
||||
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
|
||||
|
||||
/**
|
||||
* Specify callback function and optional context pointer and working memory pointer.
|
||||
* @par Implemented as
|
||||
* - R_SCIF_Uart_CallbackSet()
|
||||
*
|
||||
* @param[in] p_api_ctrl Pointer to the UART control block.
|
||||
* @param[in] p_callback Callback function
|
||||
* @param[in] p_context Pointer to send to callback function
|
||||
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||
* Callback arguments allocated here are only valid during the callback.
|
||||
*/
|
||||
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *),
|
||||
void const * const p_context, uart_callback_args_t * const p_callback_memory);
|
||||
|
||||
/** Close UART device.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the UART control block.
|
||||
*/
|
||||
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
|
||||
|
||||
/* DEPRECATED Get version.
|
||||
* @par Implemented as
|
||||
* - @ref R_SCIF_UART_VersionGet()
|
||||
*
|
||||
* @param[in] p_version Pointer to the memory to store the version information.
|
||||
*/
|
||||
fsp_err_t (* versionGet)(fsp_version_t * p_version);
|
||||
} uart_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_uart_instance
|
||||
{
|
||||
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} uart_instance_t;
|
||||
|
||||
/** @} (end defgroup UART_API) */
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,359 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef FSP_COMMON_API_H
|
||||
#define FSP_COMMON_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* Includes FSP version macros. */
|
||||
#include "fsp_version.h"
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_COMMON
|
||||
* @defgroup RENESAS_ERROR_CODES Common Error Codes
|
||||
* All FSP modules share these common error codes.
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
|
||||
* about using this implementation is that it does not take any extra RAM or ROM. */
|
||||
|
||||
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
|
||||
|
||||
/** Determine if a C++ compiler is being used.
|
||||
* If so, ensure that standard C is used to process the API information. */
|
||||
#if defined(__cplusplus)
|
||||
#define FSP_CPP_HEADER extern "C" {
|
||||
#define FSP_CPP_FOOTER }
|
||||
#else
|
||||
#define FSP_CPP_HEADER
|
||||
#define FSP_CPP_FOOTER
|
||||
#endif
|
||||
|
||||
/** FSP Header and Footer definitions */
|
||||
#define FSP_HEADER FSP_CPP_HEADER
|
||||
#define FSP_FOOTER FSP_CPP_FOOTER
|
||||
|
||||
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
|
||||
* defined on the Secure side. */
|
||||
#define FSP_SECURE_ARGUMENT (NULL)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Common error codes */
|
||||
typedef enum e_fsp_err
|
||||
{
|
||||
FSP_SUCCESS = 0,
|
||||
|
||||
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
|
||||
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
|
||||
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
|
||||
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
|
||||
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
|
||||
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
|
||||
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
|
||||
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
|
||||
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
|
||||
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
|
||||
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
|
||||
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
|
||||
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
|
||||
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
|
||||
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
|
||||
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
|
||||
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
|
||||
FSP_ERR_ABORTED = 18, ///< An operation was aborted
|
||||
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
|
||||
FSP_ERR_TIMEOUT = 20, ///< Timeout error
|
||||
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
|
||||
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
|
||||
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
|
||||
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
|
||||
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
|
||||
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
|
||||
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
|
||||
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
|
||||
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
|
||||
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
|
||||
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
|
||||
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
|
||||
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
|
||||
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
|
||||
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
|
||||
|
||||
/* Start of RTOS only error codes */
|
||||
FSP_ERR_INTERNAL = 100, ///< Internal error
|
||||
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
|
||||
|
||||
/* Start of UART specific */
|
||||
FSP_ERR_FRAMING = 200, ///< Framing error occurs
|
||||
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
|
||||
FSP_ERR_PARITY = 202, ///< Parity error occurs
|
||||
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
|
||||
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
|
||||
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
|
||||
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
|
||||
|
||||
/* Start of SPI specific */
|
||||
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
|
||||
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
|
||||
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
|
||||
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
|
||||
FSP_ERR_OVERRUN = 304, ///< Overrun error.
|
||||
|
||||
/* Start of CGC Specific */
|
||||
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
|
||||
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
|
||||
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
|
||||
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
|
||||
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
|
||||
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
|
||||
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
|
||||
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
|
||||
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
|
||||
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
|
||||
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
|
||||
|
||||
/* Start of FLASH Specific */
|
||||
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
|
||||
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
|
||||
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
|
||||
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
|
||||
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
|
||||
|
||||
/* Start of CAC Specific */
|
||||
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
|
||||
|
||||
/* Start of GLCD Specific */
|
||||
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
|
||||
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
|
||||
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
|
||||
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
|
||||
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
|
||||
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
|
||||
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
|
||||
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
|
||||
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
|
||||
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
|
||||
|
||||
/* Start of JPEG Specific */
|
||||
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
|
||||
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
|
||||
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
|
||||
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
|
||||
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
|
||||
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
|
||||
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
|
||||
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
|
||||
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
|
||||
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
|
||||
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
|
||||
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
|
||||
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
|
||||
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
|
||||
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
|
||||
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
|
||||
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
|
||||
|
||||
/* Start of touch panel framework specific */
|
||||
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
|
||||
|
||||
/* Start of IP specific */
|
||||
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
|
||||
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
|
||||
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
|
||||
|
||||
/* Start of USB specific */
|
||||
FSP_ERR_USB_FAILED = 1500,
|
||||
FSP_ERR_USB_BUSY = 1501,
|
||||
FSP_ERR_USB_SIZE_SHORT = 1502,
|
||||
FSP_ERR_USB_SIZE_OVER = 1503,
|
||||
FSP_ERR_USB_NOT_OPEN = 1504,
|
||||
FSP_ERR_USB_NOT_SUSPEND = 1505,
|
||||
FSP_ERR_USB_PARAMETER = 1506,
|
||||
|
||||
/* Start of Message framework specific */
|
||||
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
|
||||
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
|
||||
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
|
||||
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
|
||||
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
|
||||
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
|
||||
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
|
||||
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
|
||||
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
|
||||
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
|
||||
|
||||
/* Start of 2DG Driver specific */
|
||||
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
|
||||
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
|
||||
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
|
||||
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
|
||||
|
||||
/* Start of ETHER Driver specific */
|
||||
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
|
||||
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
|
||||
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
|
||||
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
|
||||
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
|
||||
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
|
||||
|
||||
/* Start of ETHER_PHY Driver specific */
|
||||
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
|
||||
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
|
||||
|
||||
/* Start of BYTEQ library specific */
|
||||
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
|
||||
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
|
||||
|
||||
/* Start of CTSU Driver specific */
|
||||
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
|
||||
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
|
||||
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
|
||||
|
||||
/* Start of SDMMC specific */
|
||||
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
|
||||
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
|
||||
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
|
||||
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
|
||||
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
|
||||
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
|
||||
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
|
||||
|
||||
/* Start of FX_IO specific */
|
||||
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
|
||||
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
|
||||
|
||||
/* Start of CAN specific */
|
||||
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
|
||||
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
|
||||
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
|
||||
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
|
||||
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
|
||||
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
|
||||
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
|
||||
|
||||
/* Start of SF_WIFI Specific */
|
||||
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
|
||||
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
|
||||
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
|
||||
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
|
||||
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
|
||||
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
|
||||
|
||||
/* Start of SF_CELLULAR Specific */
|
||||
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
|
||||
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
|
||||
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
|
||||
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
|
||||
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
|
||||
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
|
||||
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
|
||||
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
|
||||
|
||||
/* Start of SF_BLE specific */
|
||||
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
|
||||
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
|
||||
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
|
||||
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
|
||||
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
|
||||
|
||||
/* Start of SF_BLE_ABS specific */
|
||||
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
|
||||
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
|
||||
|
||||
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
|
||||
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
|
||||
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
|
||||
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
|
||||
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
|
||||
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
|
||||
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
|
||||
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
|
||||
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
|
||||
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
|
||||
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
|
||||
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
|
||||
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
|
||||
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
|
||||
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
|
||||
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
|
||||
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
|
||||
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
|
||||
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
|
||||
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
|
||||
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013,
|
||||
|
||||
/* Start of SF_CRYPTO specific */
|
||||
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
|
||||
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
|
||||
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
|
||||
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
|
||||
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
|
||||
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
|
||||
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
|
||||
|
||||
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
|
||||
* Refer to sf_cryoto_err.h for Crypto error codes.
|
||||
*/
|
||||
|
||||
/* Start of Sensor specific */
|
||||
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid.
|
||||
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing.
|
||||
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
|
||||
|
||||
/* Start of COMMS specific */
|
||||
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open.
|
||||
} fsp_err_t;
|
||||
|
||||
/** Common version structure */
|
||||
typedef union st_fsp_version
|
||||
{
|
||||
/** Version id */
|
||||
uint32_t version_id;
|
||||
|
||||
/** Code version parameters */
|
||||
struct
|
||||
{
|
||||
uint8_t code_version_minor; ///< Code minor version
|
||||
uint8_t code_version_major; ///< Code major version
|
||||
uint8_t api_version_minor; ///< API minor version
|
||||
uint8_t api_version_major; ///< API major version
|
||||
};
|
||||
} fsp_version_t;
|
||||
|
||||
/** @} */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function prototypes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,556 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef FSP_FEATURES_H
|
||||
#define FSP_FEATURES_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes <System Includes> , "Project Includes"
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* C99 includes. */
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
|
||||
/* Different compiler support. */
|
||||
#include "fsp_common_api.h"
|
||||
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
|
||||
#include "../../fsp/src/bsp/mcu/all/bsp_module_stop.h"
|
||||
#include "../../fsp/src/bsp/mcu/all/bsp_clocks.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Start clock supply
|
||||
*
|
||||
* @param ip fsp_ip_t enum value for the ip to which the clock is supplied.
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON(ip, ch) (R_BSP_MODULE_CLKON_ ## ip(ch))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Stop clock supply
|
||||
*
|
||||
* @param ip fsp_ip_t enum value for the unit to stop clock.
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF(ip, ch) (R_BSP_MODULE_CLKOFF_ ## ip(ch))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Reset ip
|
||||
*
|
||||
* @param ip fsp_ip_t enum value for the ip to be reset.
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON(ip, ch) (R_BSP_MODULE_RSTON_ ## ip(ch))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Reset ip
|
||||
*
|
||||
* @param ip fsp_ip_t enum value for the ip to be reset.
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF(ip, ch) (R_BSP_MODULE_RSTOFF_ ## ip(ch))
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* Cancels the module stop state.
|
||||
*
|
||||
* @param ip fsp_ip_t enum value for the module to be started
|
||||
* @param ch The channel. Use ch 0 for modules without channels.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START(ip, ch) (R_BSP_MODULE_START_ ## ip(ch))
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* Enables the module stop state.
|
||||
*
|
||||
* @param ip fsp_ip_t enum value for the module to be stopped
|
||||
* @param ch The channel. Use ch 0 for modules without channels.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP(ip, ch) (R_BSP_MODULE_STOP_ ## ip(ch))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_GTM(ch) (R_BSP_CLKON(BSP_CLK_GTM, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_GTM(ch) (R_BSP_CLKOFF(BSP_CLK_GTM, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_GTM(ch) (R_BSP_RSTON(BSP_CLK_GTM, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_GTM(ch) (R_BSP_RSTOFF(BSP_CLK_GTM, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_GTM(ch) (R_BSP_MSTPSTART(BSP_MSTP_MPOSTM, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_GTM(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MPOSTM, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_GPT(ch) (R_BSP_CLKON(BSP_CLK_GPT, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_GPT(ch) (R_BSP_CLKOFF(BSP_CLK_GPT, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_GPT(ch) (R_BSP_RSTON(BSP_CLK_GPT, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_GPT(ch) (R_BSP_RSTOFF(BSP_CLK_GPT, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_GPT(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHGPT, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_GPT(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHGPT, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_POEG(ch) (R_BSP_CLKON(BSP_CLK_POEG, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_POEG(ch) (R_BSP_CLKOFF(BSP_CLK_POEG, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_POEG(ch) (R_BSP_RSTON(BSP_CLK_POEG, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_POEG(ch) (R_BSP_RSTOFF(BSP_CLK_POEG, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_POEG(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHPOEG, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_POEG(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHPOEG, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_PORT(ch) (R_BSP_CLKON(BSP_CLK_GPIO, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_PORT(ch) (R_BSP_CLKOFF(BSP_CLK_GPIO, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_PORT(ch) (R_BSP_RSTON(BSP_CLK_GPIO, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_PORT(ch) (R_BSP_RSTOFF(BSP_CLK_GPIO, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_PORT(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHGPIO, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_PORT(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHGPIO, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_IM33(ch) (R_BSP_CLKON(BSP_CLK_IM33, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_IM33(ch) (R_BSP_CLKOFF(BSP_CLK_IM33, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_IM33(ch) (R_BSP_RSTON(BSP_CLK_IM33, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_IM33(ch) (R_BSP_RSTOFF(BSP_CLK_IM33, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_IM33(ch) (R_BSP_MSTPSTART(BSP_MSTP_MPIM33, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_IM33(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MPIM33, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 4.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_SCIF(ch) (R_BSP_CLKON(BSP_CLK_SCIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 4.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_SCIF(ch) (R_BSP_CLKOFF(BSP_CLK_SCIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 4.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_SCIF(ch) (R_BSP_RSTON(BSP_CLK_SCIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 4.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_SCIF(ch) (R_BSP_RSTOFF(BSP_CLK_SCIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 4.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_SCIF(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHSCIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 4.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_SCIF(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHSCIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_RIIC(ch) (R_BSP_CLKON(BSP_CLK_I2C, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_RIIC(ch) (R_BSP_CLKOFF(BSP_CLK_I2C, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_RIIC(ch) (R_BSP_RSTON(BSP_CLK_I2C, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_RIIC(ch) (R_BSP_RSTOFF(BSP_CLK_I2C, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_RIIC(ch) (R_BSP_MSTPSTART(BSP_MSTP_MPI2C, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_RIIC(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MPI2C, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_RSPI(ch) (R_BSP_CLKON(BSP_CLK_RSPI, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_RSPI(ch) (R_BSP_CLKOFF(BSP_CLK_RSPI, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_RSPI(ch) (R_BSP_RSTON(BSP_CLK_RSPI, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_RSPI(ch) (R_BSP_RSTOFF(BSP_CLK_RSPI, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_RSPI(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHRSPI, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 2.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_RSPI(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHRSPI, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 5.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_MHU(ch) (R_BSP_CLKON(BSP_CLK_MHU, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 5.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_MHU(ch) (R_BSP_CLKOFF(BSP_CLK_MHU, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 5.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_MHU(ch) (R_BSP_RSTON(BSP_CLK_MHU, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 5.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_MHU(ch) (R_BSP_RSTOFF(BSP_CLK_MHU, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 5.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_MHU(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHU, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 5.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_MHU(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHU, 0))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_DMAC(ch) (R_BSP_CLKON(BSP_CLK_DMAC, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_DMAC(ch) (R_BSP_CLKOFF(BSP_CLK_DMAC, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_DMAC(ch) (R_BSP_RSTON(BSP_CLK_DMAC, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_DMAC(ch) (R_BSP_RSTOFF(BSP_CLK_DMAC, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_DMAC(ch) {R_BSP_MSTPSTART(BSP_MSTP_MXDMAC_NS, (ch)); \
|
||||
R_BSP_MSTPSTART(BSP_MSTP_MPDMAC_NS, (ch));}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_DMAC(ch) {R_BSP_MSTPSTOP(BSP_MSTP_MXDMAC_NS, (ch)); \
|
||||
R_BSP_MSTPSTOP(BSP_MSTP_MPDMAC_NS, (ch));}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_SSI(ch) (R_BSP_CLKON(BSP_CLK_SSIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_SSI(ch) (R_BSP_CLKOFF(BSP_CLK_SSIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_SSI(ch) (R_BSP_RSTON(BSP_CLK_SSIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_SSI(ch) (R_BSP_RSTOFF(BSP_CLK_SSIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_SSI(ch) (R_BSP_MSTPSTART(BSP_MSTP_MHSSIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 3.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_SSI(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MHSSIF, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKON_FSP_IP_CANFD(ch) (R_BSP_CLKON(BSP_CLK_CANFD, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_CLKOFF_FSP_IP_CANFD(ch) (R_BSP_CLKOFF(BSP_CLK_CANFD, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTON_FSP_IP_CANFD(ch) (R_BSP_RSTON(BSP_CLK_CANFD, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_RSTOFF_FSP_IP_CANFD(ch) (R_BSP_RSTOFF(BSP_CLK_CANFD, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_START_FSP_IP_CANFD(ch) (R_BSP_MSTPSTART(BSP_MSTP_MPCANFD, (ch)))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
*
|
||||
* @param ch The channel. Use ch 0 for units without channels. Only single bit can be set. ch 0 - 1.
|
||||
**********************************************************************************************************************/
|
||||
#define R_BSP_MODULE_STOP_FSP_IP_CANFD(ch) (R_BSP_MSTPSTOP(BSP_MSTP_MPCANFD, (ch)))
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup BSP_MCU
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Following IPs are available. Used for module standby release / transition, clock ON / OFF, and reset assert / negate. */
|
||||
typedef enum e_fsp_ip
|
||||
{
|
||||
FSP_IP_GTM = 0, ///< General Timer
|
||||
FSP_IP_GPT = 1, ///< General PWM Timer
|
||||
FSP_IP_POEG = 2, ///< Port Output Enable for GPT
|
||||
FSP_IP_PORT = 3, ///< I/O Ports
|
||||
FSP_IP_IM33 = 4, ///< IM33 (Interrupt controller)
|
||||
FSP_IP_SCIF = 5, ///< Serial Communications Interface with FIFO
|
||||
FSP_IP_RIIC = 6, ///< I2C Bus Interface
|
||||
FSP_IP_RSPI = 7, ///< Renesas Serial Peripheral Interface
|
||||
FSP_IP_MHU = 8, ///< Message Handling Unit
|
||||
FSP_IP_DMAC = 9, ///< Direct Memory Access Controller
|
||||
FSP_IP_SSI = 10, ///< Serial Sound Interface
|
||||
FSP_IP_CANFD = 11, ///< CANFD Interface (RS-CANFD)
|
||||
} fsp_ip_t;
|
||||
|
||||
typedef void (* fsp_vector_t)(void);
|
||||
|
||||
/** @} (end addtogroup BSP_MCU) */
|
||||
|
||||
#endif /* FSP_FEATURES_H */
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : fsp_version.h
|
||||
* Version : 1.00
|
||||
* Description : fsp_version header
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef FSP_VERSION_H
|
||||
#define FSP_VERSION_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup RENESAS_COMMON
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** FSP pack major version. */
|
||||
#define FSP_VERSION_MAJOR (1U)
|
||||
|
||||
/** FSP pack minor version. */
|
||||
#define FSP_VERSION_MINOR (1U)
|
||||
|
||||
/** FSP pack patch version. */
|
||||
#define FSP_VERSION_PATCH (0U)
|
||||
|
||||
/** FSP pack version build number (currently unused). */
|
||||
#define FSP_VERSION_BUILD (0U)
|
||||
|
||||
/** Public FSP version name. */
|
||||
#define FSP_VERSION_STRING ("1.1.0")
|
||||
|
||||
/** Unique FSP version ID. */
|
||||
#define FSP_VERSION_BUILD_STRING ("Build with RZ/V2L Flexible Software Package version 1.1.0")
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** FSP Pack version structure */
|
||||
typedef union st_fsp_pack_version
|
||||
{
|
||||
/** Version id */
|
||||
uint32_t version_id;
|
||||
|
||||
/** Code version parameters, little endian order. */
|
||||
struct
|
||||
{
|
||||
uint8_t build; ///< Build version of FSP Pack
|
||||
uint8_t patch; ///< Patch version of FSP Pack
|
||||
uint8_t minor; ///< Minor version of FSP Pack
|
||||
uint8_t major; ///< Major version of FSP Pack
|
||||
};
|
||||
} fsp_pack_version_t;
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* FSP_VERSION_H */
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_GTM_H
|
||||
#define R_GTM_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
#include "r_gtm_cfg.h"
|
||||
#include "r_timer_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Leading zeroes removed to avoid coding standards violation. */
|
||||
#define GTM_CODE_VERSION_MAJOR (0U)
|
||||
#define GTM_CODE_VERSION_MINOR (1U)
|
||||
|
||||
/** Maximum number of clock counts in 32 bit timer. */
|
||||
#define GTM_MAX_CLOCK_COUNTS (UINT32_MAX)
|
||||
|
||||
/** Maximum period value allowed for GTM. */
|
||||
#define GTM_MAX_PERIOD ((uint64_t)UINT32_MAX + 1ULL)
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup GTM
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Optional GTM interrupt setting */
|
||||
typedef enum e_gtm_giws_type
|
||||
{
|
||||
GTM_GIWS_TYPE_DISABLED = 0, ///< Do not generate interrupt when timer started
|
||||
GTM_GIWS_TYPE_ENABLED = 1, ///< Generates interrupt when timer started
|
||||
} gtm_giws_type_t;
|
||||
|
||||
/** Optional GTM timer mode setting */
|
||||
typedef enum e_gtm_timer_mode
|
||||
{
|
||||
GTM_TIMER_MODE_INTERVAL = 0, ///< Use interval timer mode
|
||||
GTM_TIMER_MODE_FREERUN = 1, ///< Use free-running comparison mode
|
||||
} gtm_timer_mode_t;
|
||||
|
||||
/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */
|
||||
typedef struct st_gtm_instance_ctrl
|
||||
{
|
||||
uint32_t open; // Whether or not channel is open
|
||||
const timer_cfg_t * p_cfg; // Pointer to initial configurations
|
||||
R_GTM0_Type * p_reg; // Base register for this channel
|
||||
uint32_t period; // Current timer period (counts)
|
||||
|
||||
void (* p_callback)(timer_callback_args_t * p_arg); // Pointer to callback
|
||||
timer_callback_args_t * p_callback_memory; // Pointer to pre-allocated callback argument
|
||||
void const * p_context; // Pointer to context to be passed into callback function
|
||||
} gtm_instance_ctrl_t;
|
||||
|
||||
/** Optional GTM extension data structure.*/
|
||||
typedef struct st_gtm_extended_cfg
|
||||
{
|
||||
gtm_giws_type_t generate_interrupt_when_starts; // Controls enabling/disabling of interrupt requests when start
|
||||
gtm_timer_mode_t gtm_mode; // Select GTM timer mode
|
||||
} gtm_extended_cfg_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const timer_api_t g_timer_on_gtm;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
fsp_err_t R_GTM_Close (timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GTM_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
|
||||
fsp_err_t R_GTM_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
|
||||
fsp_err_t R_GTM_Reset (timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GTM_Start (timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GTM_Enable (timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GTM_Disable (timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GTM_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
|
||||
fsp_err_t R_GTM_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
|
||||
fsp_err_t R_GTM_Stop (timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GTM_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
|
||||
fsp_err_t R_GTM_CallbackSet (
|
||||
timer_ctrl_t * const p_api_ctrl,
|
||||
void (* p_callback)(timer_callback_args_t * p_arg),
|
||||
void const * const p_context,
|
||||
timer_callback_args_t * const p_callback_memory);
|
||||
fsp_err_t R_GTM_VersionGet (fsp_version_t * const p_version);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup GTM)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
|
||||
FSP_FOOTER
|
||||
|
||||
#endif /* R_GTM_H */
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup IOPORT
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_IOPORT_H
|
||||
#define R_IOPORT_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#include "r_ioport_api.h"
|
||||
#include "r_ioport_cfg.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#define IOPORT_CODE_VERSION_MAJOR (1U)
|
||||
#define IOPORT_CODE_VERSION_MINOR (0U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
|
||||
typedef struct st_ioport_instance_ctrl
|
||||
{
|
||||
uint32_t open;
|
||||
void const * p_context;
|
||||
} ioport_instance_ctrl_t;
|
||||
|
||||
/* This typedef is here temporarily. See SWFLEX-144 for details. */
|
||||
/** Superset list of all possible IO port pins. */
|
||||
typedef enum e_ioport_port_pin
|
||||
{
|
||||
IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
|
||||
IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
|
||||
|
||||
IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
|
||||
IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
|
||||
|
||||
IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
|
||||
IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
|
||||
|
||||
IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
|
||||
IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
|
||||
|
||||
IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
|
||||
IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
|
||||
|
||||
IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
|
||||
IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
|
||||
IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
|
||||
|
||||
IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
|
||||
IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
|
||||
|
||||
IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
|
||||
IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
|
||||
IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
|
||||
|
||||
IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
|
||||
IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
|
||||
IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
|
||||
|
||||
IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
|
||||
IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
|
||||
|
||||
IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
|
||||
IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
|
||||
|
||||
IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
|
||||
IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
|
||||
|
||||
IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
|
||||
IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
|
||||
|
||||
IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
|
||||
IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
|
||||
IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
|
||||
|
||||
IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
|
||||
IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
|
||||
|
||||
IOPORT_PORT_15_PIN_00 = 0x0F00, ///< IO port 15 pin 0
|
||||
IOPORT_PORT_15_PIN_01 = 0x0F01, ///< IO port 15 pin 1
|
||||
|
||||
IOPORT_PORT_16_PIN_00 = 0x1000, ///< IO port 16 pin 0
|
||||
IOPORT_PORT_16_PIN_01 = 0x1001, ///< IO port 16 pin 1
|
||||
|
||||
IOPORT_PORT_17_PIN_00 = 0x1100, ///< IO port 17 pin 0
|
||||
IOPORT_PORT_17_PIN_01 = 0x1101, ///< IO port 17 pin 1
|
||||
IOPORT_PORT_17_PIN_02 = 0x1102, ///< IO port 17 pin 2
|
||||
|
||||
IOPORT_PORT_18_PIN_00 = 0x1200, ///< IO port 18 pin 0
|
||||
IOPORT_PORT_18_PIN_01 = 0x1201, ///< IO port 18 pin 1
|
||||
|
||||
IOPORT_PORT_19_PIN_00 = 0x1300, ///< IO port 19 pin 0
|
||||
IOPORT_PORT_19_PIN_01 = 0x1301, ///< IO port 19 pin 1
|
||||
|
||||
IOPORT_PORT_20_PIN_00 = 0x1400, ///< IO port 20 pin 0
|
||||
IOPORT_PORT_20_PIN_01 = 0x1401, ///< IO port 20 pin 1
|
||||
IOPORT_PORT_20_PIN_02 = 0x1402, ///< IO port 20 pin 2
|
||||
|
||||
IOPORT_PORT_21_PIN_00 = 0x1500, ///< IO port 21 pin 0
|
||||
IOPORT_PORT_21_PIN_01 = 0x1501, ///< IO port 21 pin 1
|
||||
|
||||
IOPORT_PORT_22_PIN_00 = 0x1600, ///< IO port 22 pin 0
|
||||
IOPORT_PORT_22_PIN_01 = 0x1601, ///< IO port 22 pin 1
|
||||
|
||||
IOPORT_PORT_23_PIN_00 = 0x1700, ///< IO port 23 pin 0
|
||||
IOPORT_PORT_23_PIN_01 = 0x1701, ///< IO port 23 pin 1
|
||||
|
||||
IOPORT_PORT_24_PIN_00 = 0x1800, ///< IO port 24 pin 0
|
||||
IOPORT_PORT_24_PIN_01 = 0x1801, ///< IO port 24 pin 1
|
||||
|
||||
IOPORT_PORT_25_PIN_00 = 0x1900, ///< IO port 25 pin 0
|
||||
IOPORT_PORT_25_PIN_01 = 0x1901, ///< IO port 25 pin 1
|
||||
|
||||
IOPORT_PORT_26_PIN_00 = 0x1A00, ///< IO port 26 pin 0
|
||||
IOPORT_PORT_26_PIN_01 = 0x1A01, ///< IO port 26 pin 1
|
||||
|
||||
IOPORT_PORT_27_PIN_00 = 0x1B00, ///< IO port 27 pin 0
|
||||
IOPORT_PORT_27_PIN_01 = 0x1B01, ///< IO port 27 pin 1
|
||||
|
||||
IOPORT_PORT_28_PIN_00 = 0x1C00, ///< IO port 28 pin 0
|
||||
IOPORT_PORT_28_PIN_01 = 0x1C01, ///< IO port 28 pin 1
|
||||
|
||||
IOPORT_PORT_29_PIN_00 = 0x1D00, ///< IO port 29 pin 0
|
||||
IOPORT_PORT_29_PIN_01 = 0x1D01, ///< IO port 29 pin 1
|
||||
|
||||
IOPORT_PORT_30_PIN_00 = 0x1E00, ///< IO port 30 pin 0
|
||||
IOPORT_PORT_30_PIN_01 = 0x1E01, ///< IO port 30 pin 1
|
||||
|
||||
IOPORT_PORT_31_PIN_00 = 0x1F00, ///< IO port 31 pin 0
|
||||
IOPORT_PORT_31_PIN_01 = 0x1F01, ///< IO port 31 pin 1
|
||||
|
||||
IOPORT_PORT_32_PIN_00 = 0x2000, ///< IO port 32 pin 0
|
||||
IOPORT_PORT_32_PIN_01 = 0x2001, ///< IO port 32 pin 1
|
||||
|
||||
IOPORT_PORT_33_PIN_00 = 0x2100, ///< IO port 33 pin 0
|
||||
IOPORT_PORT_33_PIN_01 = 0x2101, ///< IO port 33 pin 1
|
||||
|
||||
IOPORT_PORT_34_PIN_00 = 0x2200, ///< IO port 34 pin 0
|
||||
IOPORT_PORT_34_PIN_01 = 0x2201, ///< IO port 34 pin 1
|
||||
|
||||
IOPORT_PORT_35_PIN_00 = 0x2300, ///< IO port 35 pin 0
|
||||
IOPORT_PORT_35_PIN_01 = 0x2301, ///< IO port 35 pin 1
|
||||
|
||||
IOPORT_PORT_36_PIN_00 = 0x2400, ///< IO port 36 pin 0
|
||||
IOPORT_PORT_36_PIN_01 = 0x2401, ///< IO port 36 pin 1
|
||||
|
||||
IOPORT_PORT_37_PIN_00 = 0x2500, ///< IO port 37 pin 0
|
||||
IOPORT_PORT_37_PIN_01 = 0x2501, ///< IO port 37 pin 1
|
||||
IOPORT_PORT_37_PIN_02 = 0x2502, ///< IO port 37 pin 2
|
||||
|
||||
IOPORT_PORT_38_PIN_00 = 0x2600, ///< IO port 38 pin 0
|
||||
IOPORT_PORT_38_PIN_01 = 0x2601, ///< IO port 38 pin 1
|
||||
|
||||
IOPORT_PORT_39_PIN_00 = 0x2700, ///< IO port 39 pin 0
|
||||
IOPORT_PORT_39_PIN_01 = 0x2701, ///< IO port 39 pin 1
|
||||
IOPORT_PORT_39_PIN_02 = 0x2702, ///< IO port 39 pin 2
|
||||
|
||||
IOPORT_PORT_40_PIN_00 = 0x2800, ///< IO port 40 pin 0
|
||||
IOPORT_PORT_40_PIN_01 = 0x2801, ///< IO port 40 pin 1
|
||||
IOPORT_PORT_40_PIN_02 = 0x2802, ///< IO port 40 pin 2
|
||||
|
||||
IOPORT_PORT_41_PIN_00 = 0x2900, ///< IO port 41 pin 0
|
||||
IOPORT_PORT_41_PIN_01 = 0x2901, ///< IO port 41 pin 1
|
||||
|
||||
IOPORT_PORT_42_PIN_00 = 0x2A00, ///< IO port 42 pin 0
|
||||
IOPORT_PORT_42_PIN_01 = 0x2A01, ///< IO port 42 pin 1
|
||||
IOPORT_PORT_42_PIN_02 = 0x2A02, ///< IO port 42 pin 2
|
||||
IOPORT_PORT_42_PIN_03 = 0x2A03, ///< IO port 42 pin 3
|
||||
IOPORT_PORT_42_PIN_04 = 0x2A04, ///< IO port 42 pin 4
|
||||
|
||||
IOPORT_PORT_43_PIN_00 = 0x2B00, ///< IO port 43 pin 0
|
||||
IOPORT_PORT_43_PIN_01 = 0x2B01, ///< IO port 43 pin 1
|
||||
IOPORT_PORT_43_PIN_02 = 0x2B02, ///< IO port 43 pin 2
|
||||
IOPORT_PORT_43_PIN_03 = 0x2B03, ///< IO port 43 pin 3
|
||||
|
||||
IOPORT_PORT_44_PIN_00 = 0x2C00, ///< IO port 44 pin 0
|
||||
IOPORT_PORT_44_PIN_01 = 0x2C01, ///< IO port 44 pin 1
|
||||
IOPORT_PORT_44_PIN_02 = 0x2C02, ///< IO port 44 pin 2
|
||||
IOPORT_PORT_44_PIN_03 = 0x2C03, ///< IO port 44 pin 3
|
||||
|
||||
IOPORT_PORT_45_PIN_00 = 0x2D00, ///< IO port 45 pin 0
|
||||
IOPORT_PORT_45_PIN_01 = 0x2D01, ///< IO port 45 pin 1
|
||||
IOPORT_PORT_45_PIN_02 = 0x2D02, ///< IO port 45 pin 2
|
||||
IOPORT_PORT_45_PIN_03 = 0x2D03, ///< IO port 45 pin 3
|
||||
|
||||
IOPORT_PORT_46_PIN_00 = 0x2E00, ///< IO port 46 pin 0
|
||||
IOPORT_PORT_46_PIN_01 = 0x2E01, ///< IO port 46 pin 1
|
||||
IOPORT_PORT_46_PIN_02 = 0x2E02, ///< IO port 46 pin 2
|
||||
IOPORT_PORT_46_PIN_03 = 0x2E03, ///< IO port 46 pin 3
|
||||
|
||||
IOPORT_PORT_47_PIN_00 = 0x2F00, ///< IO port 47 pin 0
|
||||
IOPORT_PORT_47_PIN_01 = 0x2F01, ///< IO port 47 pin 1
|
||||
IOPORT_PORT_47_PIN_02 = 0x2F02, ///< IO port 47 pin 2
|
||||
IOPORT_PORT_47_PIN_03 = 0x2F03, ///< IO port 47 pin 3
|
||||
|
||||
IOPORT_PORT_48_PIN_00 = 0x3000, ///< IO port 48 pin 0
|
||||
IOPORT_PORT_48_PIN_01 = 0x3001, ///< IO port 48 pin 1
|
||||
IOPORT_PORT_48_PIN_02 = 0x3002, ///< IO port 48 pin 2
|
||||
IOPORT_PORT_48_PIN_03 = 0x3003, ///< IO port 48 pin 3
|
||||
IOPORT_PORT_48_PIN_04 = 0x3004, ///< IO port 48 pin 4
|
||||
|
||||
/* Special purpose port */
|
||||
IOPORT_NMI = 0xFFFF0100, ///< NMI
|
||||
|
||||
IOPORT_TMS_SWDIO = 0xFFFF0200, ///< TMS_SWDIO
|
||||
|
||||
IOPORT_TDO = 0xFFFF0300, ///< TDO
|
||||
|
||||
IOPORT_AUDIO_CLK1 = 0xFFFF0400, ///< AUDIO_CLK1
|
||||
IOPORT_AUDIO_CLK2 = 0xFFFF0401, ///< AUDIO_CLK2
|
||||
|
||||
IOPORT_SD0_CLK = 0xFFFF0600, ///< CD0_CLK
|
||||
IOPORT_SD0_CMD = 0xFFFF0601, ///< CD0_CMD
|
||||
IOPORT_SD0_RST_N = 0xFFFF0602, ///< CD0_RST_N
|
||||
|
||||
IOPORT_SD0_DATA0 = 0xFFFF0700, ///< SD0_DATA0
|
||||
IOPORT_SD0_DATA1 = 0xFFFF0701, ///< SD0_DATA1
|
||||
IOPORT_SD0_DATA2 = 0xFFFF0702, ///< SD0_DATA2
|
||||
IOPORT_SD0_DATA3 = 0xFFFF0703, ///< SD0_DATA3
|
||||
IOPORT_SD0_DATA4 = 0xFFFF0704, ///< SD0_DATA4
|
||||
IOPORT_SD0_DATA5 = 0xFFFF0705, ///< SD0_DATA5
|
||||
IOPORT_SD0_DATA6 = 0xFFFF0706, ///< SD0_DATA6
|
||||
IOPORT_SD0_DATA7 = 0xFFFF0707, ///< SD0_DATA7
|
||||
|
||||
IOPORT_SD1_CLK = 0xFFFF0800, ///< SD1_CLK
|
||||
IOPORT_SD1_CMD = 0xFFFF0801, ///< SD1_CMD
|
||||
|
||||
IOPORT_SD1_DATA0 = 0xFFFF0900, ///< SD1_DATA0
|
||||
IOPORT_SD1_DATA1 = 0xFFFF0901, ///< SD1_DATA1
|
||||
IOPORT_SD1_DATA2 = 0xFFFF0902, ///< SD1_DATA2
|
||||
IOPORT_SD1_DATA3 = 0xFFFF0903, ///< SD1_DATA3
|
||||
|
||||
IOPORT_QSPI0_SPCLK = 0xFFFF0A00, ///< QSPI0_SPCLK
|
||||
IOPORT_QSPI0_IO0 = 0xFFFF0A01, ///< QSPI0_IO0
|
||||
IOPORT_QSPI0_IO1 = 0xFFFF0A02, ///< QSPI0_IO1
|
||||
IOPORT_QSPI0_IO2 = 0xFFFF0A03, ///< QSPI0_IO2
|
||||
IOPORT_QSPI0_IO3 = 0xFFFF0A04, ///< QSPI0_IO3
|
||||
IOPORT_QSPI0_SSL = 0xFFFF0A05, ///< QSPI0_SSL
|
||||
|
||||
IOPORT_QSPI1_SPCLK = 0xFFFF0B00, ///< QSPI1_SPCLK
|
||||
IOPORT_QSPI1_IO0 = 0xFFFF0B01, ///< QSPI1_IO0
|
||||
IOPORT_QSPI1_IO1 = 0xFFFF0B02, ///< QSPI1_IO1
|
||||
IOPORT_QSPI1_IO2 = 0xFFFF0B03, ///< QSPI1_IO2
|
||||
IOPORT_QSPI1_IO3 = 0xFFFF0B04, ///< QSPI1_IO3
|
||||
IOPORT_QSPI1_SSL = 0xFFFF0B05, ///< QSPI1_SSL
|
||||
|
||||
IOPORT_QSPI_RESET_N = 0xFFFF0C00, ///< QSPI_RESET_N
|
||||
IOPORT_QSPI_WP_N = 0xFFFF0C01, ///< QSPI_WP_N
|
||||
IOPORT_QSPI_INT_N = 0xFFFF0C02, ///< QSPI_INT_N
|
||||
|
||||
IOPORT_WDTOVF_PERROUT_N = 0xFFFF0D00, ///< WDTOVF_PERROUT_N
|
||||
|
||||
IOPORT_RIIC0_SDA = 0xFFFF0E00, ///< RIIC0_SDA
|
||||
IOPORT_RIIC0_SCL = 0xFFFF0E01, ///< RIIC0_SCL
|
||||
IOPORT_RIIC1_SDA = 0xFFFF0E02, ///< RIIC1_SDA
|
||||
IOPORT_RIIC1_SCL = 0xFFFF0E03, ///< RIIC1_SCL
|
||||
} ioport_port_pin_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const ioport_api_t g_ioport_on_ioport;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Public APIs
|
||||
**********************************************************************************************************************/
|
||||
|
||||
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
|
||||
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
|
||||
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
|
||||
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
|
||||
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
|
||||
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
|
||||
bsp_io_port_t port,
|
||||
ioport_size_t direction_values,
|
||||
ioport_size_t mask);
|
||||
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
|
||||
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
|
||||
bsp_io_port_t port,
|
||||
ioport_size_t event_data,
|
||||
ioport_size_t mask_value);
|
||||
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
|
||||
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
|
||||
fsp_err_t R_IOPORT_SDVoltageModeCfg(ioport_ctrl_t * const p_ctrl,
|
||||
ioport_sd_channel_t channel,
|
||||
ioport_sd_voltage_t voltage);
|
||||
fsp_err_t R_IOPORT_QSPIVoltageModeCfg(ioport_ctrl_t * const p_ctrl,
|
||||
ioport_qspi_channel_t channel,
|
||||
ioport_qspi_voltage_t voltage);
|
||||
fsp_err_t R_IOPORT_EthernetVoltageModeCfg(ioport_ctrl_t * const p_ctrl,
|
||||
ioport_ethernet_channel_t channel,
|
||||
ioport_ethernet_voltage_t voltage);
|
||||
fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl,
|
||||
ioport_ethernet_channel_t channel,
|
||||
ioport_ethernet_mode_t mode);
|
||||
fsp_err_t R_IOPORT_VersionGet(fsp_version_t * p_data);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup IOPORT)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif // R_IOPORT_H
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_SCIF_UART_H
|
||||
#define R_SCIF_UART_H
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup SCIF_UART
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
#include "r_uart_api.h"
|
||||
#include "r_scif_uart_cfg.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#define SCIF_UART_CODE_VERSION_MAJOR (0U)
|
||||
#define SCIF_UART_CODE_VERSION_MINOR (1U)
|
||||
#define SCIF_UART_INVALID_16BIT_PARAM (0xFFFFU)
|
||||
#define SCIF_UART_INVALID_8BIT_PARAM (0xFFU)
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Enumeration for SCIF clock source */
|
||||
typedef enum e_scif_clk_src
|
||||
{
|
||||
SCIF_UART_CLOCK_INT, ///< Use internal clock for baud generation
|
||||
SCIF_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
|
||||
SCIF_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
|
||||
SCIF_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
|
||||
} scif_clk_src_t;
|
||||
|
||||
/** UART communication mode definition */
|
||||
typedef enum e_scif_uart_mode
|
||||
{
|
||||
SCIF_UART_MODE_RS232, ///< Enables RS232 communication mode
|
||||
SCIF_UART_MODE_RS485_HD, ///< Enables RS485 half duplex communication mode
|
||||
SCIF_UART_MODE_RS485_FD, ///< Enables RS485 full duplex communication mode
|
||||
} scif_uart_mode_t;
|
||||
|
||||
/** UART automatic flow control definition */
|
||||
typedef enum e_scif_uart_flow_control
|
||||
{
|
||||
SCIF_UART_FLOW_CONTROL_NONE, ///< Disables flow control
|
||||
SCIF_UART_FLOW_CONTROL_AUTO, ///< Enables automatic RTS/CTS flow control
|
||||
} scif_uart_flow_control_t;
|
||||
|
||||
/** Noise cancellation configuration. */
|
||||
typedef enum e_scif_uart_noise_cancellation
|
||||
{
|
||||
SCIF_UART_NOISE_CANCELLATION_DISABLE, ///< Disable noise cancellation
|
||||
SCIF_UART_NOISE_CANCELLATION_ENABLE, ///< Enable noise cancellation
|
||||
} scif_uart_noise_cancellation_t;
|
||||
|
||||
/** Receive FIFO trigger configuration. */
|
||||
typedef enum e_scif_uart_receive_trigger
|
||||
{
|
||||
SCIF_UART_RECEIVE_TRIGGER_ONE, ///< Interrupt at least one byte is in FIFO
|
||||
SCIF_UART_RECEIVE_TRIGGER_QUARTER, ///< Interrupt at least quarter of FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_HALF, ///< Interrupt at least half of FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_MAX, ///< Interrupt at almost full in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_1, ///< Interrupt at least 1 byte is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_2, ///< Interrupt at least 2 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_3, ///< Interrupt at least 3 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_4, ///< Interrupt at least 4 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_5, ///< Interrupt at least 5 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_6, ///< Interrupt at least 6 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_7, ///< Interrupt at least 7 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_8, ///< Interrupt at least 8 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_9, ///< Interrupt at least 9 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_10, ///< Interrupt at least 10 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_11, ///< Interrupt at least 11 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_12, ///< Interrupt at least 12 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_13, ///< Interrupt at least 13 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_14, ///< Interrupt at least 14 bytes is in FIFO or 15ETU past from last receive
|
||||
SCIF_UART_RECEIVE_TRIGGER_15, ///< Interrupt at least 15 bytes is in FIFO or 15ETU past from last receive
|
||||
} scif_uart_receive_trigger_t;
|
||||
|
||||
/** RTS trigger level. */
|
||||
typedef enum e_scif_uart_rts_trigger
|
||||
{
|
||||
SCIF_UART_RTS_TRIGGER_1, ///< RTS trigger level = 1
|
||||
SCIF_UART_RTS_TRIGGER_4, ///< RTS trigger level = 4
|
||||
SCIF_UART_RTS_TRIGGER_6, ///< RTS trigger level = 6
|
||||
SCIF_UART_RTS_TRIGGER_8, ///< RTS trigger level = 8
|
||||
SCIF_UART_RTS_TRIGGER_10, ///< RTS trigger level = 10
|
||||
SCIF_UART_RTS_TRIGGER_12, ///< RTS trigger level = 12
|
||||
SCIF_UART_RTS_TRIGGER_14, ///< RTS trigger level = 14
|
||||
SCIF_UART_RTS_TRIGGER_15, ///< RTS trigger level = 15
|
||||
} scif_uart_rts_trigger_t;
|
||||
|
||||
/** UART instance control block. */
|
||||
typedef struct st_scif_uart_instance_ctrl
|
||||
{
|
||||
/* Parameters to control UART peripheral device */
|
||||
uint32_t open; // Used to determine if the channel is configured
|
||||
|
||||
bsp_io_port_pin_t driver_enable_pin;
|
||||
|
||||
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
|
||||
uint8_t const * p_tx_src;
|
||||
|
||||
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
|
||||
uint32_t tx_src_bytes;
|
||||
|
||||
/* Destination buffer pointer used for receiving data. */
|
||||
uint8_t * p_rx_dest;
|
||||
|
||||
/* Size of destination buffer pointer used for receiving data. */
|
||||
uint32_t rx_dest_bytes;
|
||||
|
||||
/* Pointer to the configuration block. */
|
||||
uart_cfg_t const * p_cfg;
|
||||
|
||||
/* Base register for this channel */
|
||||
R_SCIFA0_Type * p_reg;
|
||||
|
||||
/* Backup SPTR value for writing */
|
||||
uint16_t sptr;
|
||||
|
||||
void (* p_callback)(uart_callback_args_t * p_arg); // Pointer to callback
|
||||
uart_callback_args_t * p_callback_memory; // Pointer to pre-allocated callback argument
|
||||
|
||||
/* Pointer to context to be passed into callback function */
|
||||
void const * p_context;
|
||||
} scif_uart_instance_ctrl_t;
|
||||
|
||||
/** Register settings to achieve a desired baud rate and modulation duty. */
|
||||
typedef struct st_scif_baud_setting
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select
|
||||
uint8_t brme : 1; ///< Bit Rate Modulation Enable
|
||||
uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
|
||||
uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
|
||||
};
|
||||
uint8_t brr; ///< Bit Rate Register setting
|
||||
uint8_t mddr; ///< Modulation Duty Register setting
|
||||
} scif_baud_setting_t;
|
||||
|
||||
/** UART on SCIF device Configuration */
|
||||
typedef struct st_scif_uart_extended_cfg
|
||||
{
|
||||
uint8_t bri_ipl; ///< Break interrupt priority
|
||||
IRQn_Type bri_irq; ///< Break interrupt IRQ number
|
||||
scif_clk_src_t clock; ///< The source clock for the baud-rate generator.
|
||||
scif_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
|
||||
|
||||
scif_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
|
||||
|
||||
scif_uart_receive_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level.
|
||||
scif_uart_rts_trigger_t rts_fifo_trigger; ///< RTS trigger level.
|
||||
|
||||
scif_uart_mode_t uart_mode; ///< UART communication mode selection
|
||||
bsp_io_port_pin_t driver_enable_pin; ///< UART Driver Enable pin
|
||||
scif_uart_flow_control_t flow_control; ///< CTS/RTS function
|
||||
} scif_uart_extended_cfg_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const uart_api_t g_uart_on_scif;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
fsp_err_t R_SCIF_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
|
||||
fsp_err_t R_SCIF_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
|
||||
fsp_err_t R_SCIF_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
|
||||
fsp_err_t R_SCIF_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
|
||||
fsp_err_t R_SCIF_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
|
||||
fsp_err_t R_SCIF_UART_Close(uart_ctrl_t * const p_api_ctrl);
|
||||
fsp_err_t R_SCIF_UART_VersionGet(fsp_version_t * p_version);
|
||||
fsp_err_t R_SCIF_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
|
||||
fsp_err_t R_SCIF_UART_BaudCalculate(uart_ctrl_t * const p_api_ctrl,
|
||||
uint32_t baudrate,
|
||||
bool bitrate_modulation,
|
||||
uint32_t baud_rate_error_x_1000,
|
||||
scif_baud_setting_t * const p_baud_setting);
|
||||
fsp_err_t R_SCIF_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
|
||||
void ( * p_callback)(uart_callback_args_t * p_arg),
|
||||
void const * const p_context,
|
||||
uart_callback_args_t * const p_callback_memory);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end addtogroup SCIF_UART)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif /* R_SCIF_UART_H */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : base_addresses.h
|
||||
* Version : 1.00
|
||||
* Description : base_addresses header
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef __BASE_ADDRESSES_H
|
||||
#define __BASE_ADDRESSES_H
|
||||
|
||||
#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers)
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ================ */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/** @addtogroup Device_Peripheral_peripheralAddr
|
||||
* @{
|
||||
*/
|
||||
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/** @addtogroup Device_Peripheral_declaration
|
||||
* @{
|
||||
*/
|
||||
/** @} */ /* End of group Device_Peripheral_declaration */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __BASE_ADDRESSES_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : iobitmask header
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef __IOBITMASK_HEADER__
|
||||
#define __IOBITMASK_HEADER__
|
||||
|
||||
#include "iobitmasks/accctl_iobitmask.h"
|
||||
#include "iobitmasks/cpg_iobitmask.h"
|
||||
#include "iobitmasks/canfd_iobitmask.h"
|
||||
#include "iobitmasks/gpio_iobitmask.h"
|
||||
#include "iobitmasks/gpt_iobitmask.h"
|
||||
#include "iobitmasks/gtm_iobitmask.h"
|
||||
#include "iobitmasks/intc_im33_iobitmask.h"
|
||||
#include "iobitmasks/mhu_iobitmask.h"
|
||||
#include "iobitmasks/mstp_iobitmask.h"
|
||||
#include "iobitmasks/poeg_iobitmask.h"
|
||||
#include "iobitmasks/riic_iobitmask.h"
|
||||
#include "iobitmasks/rspi_iobitmask.h"
|
||||
#include "iobitmasks/scifa_iobitmask.h"
|
||||
#include "iobitmasks/spibsc_iobitmask.h"
|
||||
#include "iobitmasks/ssi_iobitmask.h"
|
||||
#include "iobitmasks/sysc_iobitmask.h"
|
||||
#include "iobitmasks/wdt_iobitmask.h"
|
||||
|
||||
#endif /* __IOBITMASK_HEADER__ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : accctl_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for accctl.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef ACCCTL_IOBITMASK_H
|
||||
#define ACCCTL_IOBITMASK_H
|
||||
#endif /* ACCCTL_IOBITMASK_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,519 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : gpt_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for gpt.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef GPT_IOBITMASK_H
|
||||
#define GPT_IOBITMASK_H
|
||||
|
||||
#define R_GPT_GTWP_WP_Msk (0x00000001UL)
|
||||
#define R_GPT_GTWP_WP_Pos (0UL)
|
||||
#define R_GPT_GTWP_PRKEY_Msk (0x0000FF00UL)
|
||||
#define R_GPT_GTWP_PRKEY_Pos (8UL)
|
||||
#define R_GPT_GTSTR_CSTRT0_Msk (0x00000001UL)
|
||||
#define R_GPT_GTSTR_CSTRT0_Pos (0UL)
|
||||
#define R_GPT_GTSTR_CSTRT1_Msk (0x00000002UL)
|
||||
#define R_GPT_GTSTR_CSTRT1_Pos (1UL)
|
||||
#define R_GPT_GTSTR_CSTRT2_Msk (0x00000004UL)
|
||||
#define R_GPT_GTSTR_CSTRT2_Pos (2UL)
|
||||
#define R_GPT_GTSTR_CSTRT3_Msk (0x00000008UL)
|
||||
#define R_GPT_GTSTR_CSTRT3_Pos (3UL)
|
||||
#define R_GPT_GTSTR_CSTRT4_Msk (0x00000010UL)
|
||||
#define R_GPT_GTSTR_CSTRT4_Pos (4UL)
|
||||
#define R_GPT_GTSTR_CSTRT5_Msk (0x00000020UL)
|
||||
#define R_GPT_GTSTR_CSTRT5_Pos (5UL)
|
||||
#define R_GPT_GTSTR_CSTRT6_Msk (0x00000040UL)
|
||||
#define R_GPT_GTSTR_CSTRT6_Pos (6UL)
|
||||
#define R_GPT_GTSTR_CSTRT7_Msk (0x00000080UL)
|
||||
#define R_GPT_GTSTR_CSTRT7_Pos (7UL)
|
||||
#define R_GPT_GTSTP_CSTOP0_Msk (0x00000001UL)
|
||||
#define R_GPT_GTSTP_CSTOP0_Pos (0UL)
|
||||
#define R_GPT_GTSTP_CSTOP1_Msk (0x00000002UL)
|
||||
#define R_GPT_GTSTP_CSTOP1_Pos (1UL)
|
||||
#define R_GPT_GTSTP_CSTOP2_Msk (0x00000004UL)
|
||||
#define R_GPT_GTSTP_CSTOP2_Pos (2UL)
|
||||
#define R_GPT_GTSTP_CSTOP3_Msk (0x00000008UL)
|
||||
#define R_GPT_GTSTP_CSTOP3_Pos (3UL)
|
||||
#define R_GPT_GTSTP_CSTOP4_Msk (0x00000010UL)
|
||||
#define R_GPT_GTSTP_CSTOP4_Pos (4UL)
|
||||
#define R_GPT_GTSTP_CSTOP5_Msk (0x00000020UL)
|
||||
#define R_GPT_GTSTP_CSTOP5_Pos (5UL)
|
||||
#define R_GPT_GTSTP_CSTOP6_Msk (0x00000040UL)
|
||||
#define R_GPT_GTSTP_CSTOP6_Pos (6UL)
|
||||
#define R_GPT_GTSTP_CSTOP7_Msk (0x00000080UL)
|
||||
#define R_GPT_GTSTP_CSTOP7_Pos (7UL)
|
||||
#define R_GPT_GTCLR_CCLR0_Msk (0x00000001UL)
|
||||
#define R_GPT_GTCLR_CCLR0_Pos (0UL)
|
||||
#define R_GPT_GTCLR_CCLR1_Msk (0x00000002UL)
|
||||
#define R_GPT_GTCLR_CCLR1_Pos (1UL)
|
||||
#define R_GPT_GTCLR_CCLR2_Msk (0x00000004UL)
|
||||
#define R_GPT_GTCLR_CCLR2_Pos (2UL)
|
||||
#define R_GPT_GTCLR_CCLR3_Msk (0x00000008UL)
|
||||
#define R_GPT_GTCLR_CCLR3_Pos (3UL)
|
||||
#define R_GPT_GTCLR_CCLR4_Msk (0x00000010UL)
|
||||
#define R_GPT_GTCLR_CCLR4_Pos (4UL)
|
||||
#define R_GPT_GTCLR_CCLR5_Msk (0x00000020UL)
|
||||
#define R_GPT_GTCLR_CCLR5_Pos (5UL)
|
||||
#define R_GPT_GTCLR_CCLR6_Msk (0x00000040UL)
|
||||
#define R_GPT_GTCLR_CCLR6_Pos (6UL)
|
||||
#define R_GPT_GTCLR_CCLR7_Msk (0x00000080UL)
|
||||
#define R_GPT_GTCLR_CCLR7_Pos (7UL)
|
||||
#define R_GPT_GTSSR_SSGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTSSR_SSGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTSSR_SSGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTSSR_SSGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTSSR_SSGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTSSR_SSGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTSSR_SSGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTSSR_SSGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTSSR_SSGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTSSR_SSGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTSSR_SSGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTSSR_SSGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTSSR_SSGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTSSR_SSGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTSSR_SSGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTSSR_SSGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTSSR_SSCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTSSR_SSCARBL_Pos (8UL)
|
||||
#define R_GPT_GTSSR_SSCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTSSR_SSCARBH_Pos (9UL)
|
||||
#define R_GPT_GTSSR_SSCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTSSR_SSCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTSSR_SSCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTSSR_SSCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTSSR_SSCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTSSR_SSCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTSSR_SSCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTSSR_SSCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTSSR_SSCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTSSR_SSCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTSSR_SSCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTSSR_SSCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTSSR_CSTRT_Msk (0x80000000UL)
|
||||
#define R_GPT_GTSSR_CSTRT_Pos (31UL)
|
||||
#define R_GPT_GTPSR_PSGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTPSR_PSGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTPSR_PSGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTPSR_PSGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTPSR_PSGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTPSR_PSGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTPSR_PSGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTPSR_PSGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTPSR_PSGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTPSR_PSGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTPSR_PSGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTPSR_PSGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTPSR_PSGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTPSR_PSGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTPSR_PSGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTPSR_PSGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTPSR_PSCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTPSR_PSCARBL_Pos (8UL)
|
||||
#define R_GPT_GTPSR_PSCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTPSR_PSCARBH_Pos (9UL)
|
||||
#define R_GPT_GTPSR_PSCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTPSR_PSCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTPSR_PSCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTPSR_PSCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTPSR_PSCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTPSR_PSCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTPSR_PSCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTPSR_PSCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTPSR_PSCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTPSR_PSCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTPSR_PSCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTPSR_PSCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTPSR_CSTOP_Msk (0x80000000UL)
|
||||
#define R_GPT_GTPSR_CSTOP_Pos (31UL)
|
||||
#define R_GPT_GTCSR_CSGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTCSR_CSGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTCSR_CSGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTCSR_CSGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTCSR_CSGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTCSR_CSGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTCSR_CSGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTCSR_CSGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTCSR_CSGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTCSR_CSGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTCSR_CSGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTCSR_CSGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTCSR_CSGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTCSR_CSGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTCSR_CSGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTCSR_CSGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTCSR_CSCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTCSR_CSCARBL_Pos (8UL)
|
||||
#define R_GPT_GTCSR_CSCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTCSR_CSCARBH_Pos (9UL)
|
||||
#define R_GPT_GTCSR_CSCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTCSR_CSCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTCSR_CSCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTCSR_CSCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTCSR_CSCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTCSR_CSCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTCSR_CSCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTCSR_CSCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTCSR_CSCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTCSR_CSCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTCSR_CSCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTCSR_CSCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTCSR_CCLR_Msk (0x80000000UL)
|
||||
#define R_GPT_GTCSR_CCLR_Pos (31UL)
|
||||
#define R_GPT_GTUPSR_USGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTUPSR_USGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTUPSR_USGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTUPSR_USGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTUPSR_USGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTUPSR_USGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTUPSR_USGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTUPSR_USGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTUPSR_USGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTUPSR_USGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTUPSR_USGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTUPSR_USGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTUPSR_USGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTUPSR_USGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTUPSR_USGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTUPSR_USGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTUPSR_USCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTUPSR_USCARBL_Pos (8UL)
|
||||
#define R_GPT_GTUPSR_USCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTUPSR_USCARBH_Pos (9UL)
|
||||
#define R_GPT_GTUPSR_USCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTUPSR_USCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTUPSR_USCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTUPSR_USCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTUPSR_USCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTUPSR_USCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTUPSR_USCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTUPSR_USCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTUPSR_USCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTUPSR_USCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTUPSR_USCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTUPSR_USCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTDNSR_DSGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTDNSR_DSCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTDNSR_DSCARBL_Pos (8UL)
|
||||
#define R_GPT_GTDNSR_DSCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTDNSR_DSCARBH_Pos (9UL)
|
||||
#define R_GPT_GTDNSR_DSCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTDNSR_DSCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTDNSR_DSCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTDNSR_DSCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTDNSR_DSCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTDNSR_DSCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTDNSR_DSCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTDNSR_DSCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTDNSR_DSCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTDNSR_DSCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTDNSR_DSCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTDNSR_DSCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTICASR_ASGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTICASR_ASGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTICASR_ASGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTICASR_ASGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTICASR_ASGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTICASR_ASGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTICASR_ASGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTICASR_ASGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTICASR_ASGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTICASR_ASGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTICASR_ASGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTICASR_ASGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTICASR_ASGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTICASR_ASGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTICASR_ASGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTICASR_ASGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTICASR_ASCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTICASR_ASCARBL_Pos (8UL)
|
||||
#define R_GPT_GTICASR_ASCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTICASR_ASCARBH_Pos (9UL)
|
||||
#define R_GPT_GTICASR_ASCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTICASR_ASCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTICASR_ASCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTICASR_ASCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTICASR_ASCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTICASR_ASCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTICASR_ASCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTICASR_ASCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTICASR_ASCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTICASR_ASCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTICASR_ASCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTICASR_ASCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGAR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGAR_Pos (0UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGAF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGAF_Pos (1UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGBR_Msk (0x00000004UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGBR_Pos (2UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGBF_Msk (0x00000008UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGBF_Pos (3UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGCR_Msk (0x00000010UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGCR_Pos (4UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGCF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGCF_Pos (5UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGDR_Msk (0x00000040UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGDR_Pos (6UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGDF_Msk (0x00000080UL)
|
||||
#define R_GPT_GTICBSR_BSGTRGDF_Pos (7UL)
|
||||
#define R_GPT_GTICBSR_BSCARBL_Msk (0x00000100UL)
|
||||
#define R_GPT_GTICBSR_BSCARBL_Pos (8UL)
|
||||
#define R_GPT_GTICBSR_BSCARBH_Msk (0x00000200UL)
|
||||
#define R_GPT_GTICBSR_BSCARBH_Pos (9UL)
|
||||
#define R_GPT_GTICBSR_BSCAFBL_Msk (0x00000400UL)
|
||||
#define R_GPT_GTICBSR_BSCAFBL_Pos (10UL)
|
||||
#define R_GPT_GTICBSR_BSCAFBH_Msk (0x00000800UL)
|
||||
#define R_GPT_GTICBSR_BSCAFBH_Pos (11UL)
|
||||
#define R_GPT_GTICBSR_BSCBRAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTICBSR_BSCBRAL_Pos (12UL)
|
||||
#define R_GPT_GTICBSR_BSCBRAH_Msk (0x00002000UL)
|
||||
#define R_GPT_GTICBSR_BSCBRAH_Pos (13UL)
|
||||
#define R_GPT_GTICBSR_BSCBFAL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTICBSR_BSCBFAL_Pos (14UL)
|
||||
#define R_GPT_GTICBSR_BSCBFAH_Msk (0x00008000UL)
|
||||
#define R_GPT_GTICBSR_BSCBFAH_Pos (15UL)
|
||||
#define R_GPT_GTCR_CST_Msk (0x00000001UL)
|
||||
#define R_GPT_GTCR_CST_Pos (0UL)
|
||||
#define R_GPT_GTCR_MD_Msk (0x00070000UL)
|
||||
#define R_GPT_GTCR_MD_Pos (16UL)
|
||||
#define R_GPT_GTCR_TPCS_Msk (0x07000000UL)
|
||||
#define R_GPT_GTCR_TPCS_Pos (24UL)
|
||||
#define R_GPT_GTUDDTYC_UD_Msk (0x00000001UL)
|
||||
#define R_GPT_GTUDDTYC_UD_Pos (0UL)
|
||||
#define R_GPT_GTUDDTYC_UDF_Msk (0x00000002UL)
|
||||
#define R_GPT_GTUDDTYC_UDF_Pos (1UL)
|
||||
#define R_GPT_GTUDDTYC_OADTY_Msk (0x00030000UL)
|
||||
#define R_GPT_GTUDDTYC_OADTY_Pos (16UL)
|
||||
#define R_GPT_GTUDDTYC_OADTYF_Msk (0x00040000UL)
|
||||
#define R_GPT_GTUDDTYC_OADTYF_Pos (18UL)
|
||||
#define R_GPT_GTUDDTYC_OADTYR_Msk (0x00080000UL)
|
||||
#define R_GPT_GTUDDTYC_OADTYR_Pos (19UL)
|
||||
#define R_GPT_GTUDDTYC_OBDTY_Msk (0x03000000UL)
|
||||
#define R_GPT_GTUDDTYC_OBDTY_Pos (24UL)
|
||||
#define R_GPT_GTUDDTYC_OBDTYF_Msk (0x04000000UL)
|
||||
#define R_GPT_GTUDDTYC_OBDTYF_Pos (26UL)
|
||||
#define R_GPT_GTUDDTYC_OBDTYR_Msk (0x08000000UL)
|
||||
#define R_GPT_GTUDDTYC_OBDTYR_Pos (27UL)
|
||||
#define R_GPT_GTIOR_GTIOA_Msk (0x0000001FUL)
|
||||
#define R_GPT_GTIOR_GTIOA_Pos (0UL)
|
||||
#define R_GPT_GTIOR_OADFLT_Msk (0x00000040UL)
|
||||
#define R_GPT_GTIOR_OADFLT_Pos (6UL)
|
||||
#define R_GPT_GTIOR_OAHLD_Msk (0x00000080UL)
|
||||
#define R_GPT_GTIOR_OAHLD_Pos (7UL)
|
||||
#define R_GPT_GTIOR_OAE_Msk (0x00000100UL)
|
||||
#define R_GPT_GTIOR_OAE_Pos (8UL)
|
||||
#define R_GPT_GTIOR_OADF_Msk (0x00000600UL)
|
||||
#define R_GPT_GTIOR_OADF_Pos (9UL)
|
||||
#define R_GPT_GTIOR_NFAEN_Msk (0x00002000UL)
|
||||
#define R_GPT_GTIOR_NFAEN_Pos (13UL)
|
||||
#define R_GPT_GTIOR_NFCSA_Msk (0x0000C000UL)
|
||||
#define R_GPT_GTIOR_NFCSA_Pos (14UL)
|
||||
#define R_GPT_GTIOR_GTIOB_Msk (0x001F0000UL)
|
||||
#define R_GPT_GTIOR_GTIOB_Pos (16UL)
|
||||
#define R_GPT_GTIOR_OBDFLT_Msk (0x00400000UL)
|
||||
#define R_GPT_GTIOR_OBDFLT_Pos (22UL)
|
||||
#define R_GPT_GTIOR_OBHLD_Msk (0x00800000UL)
|
||||
#define R_GPT_GTIOR_OBHLD_Pos (23UL)
|
||||
#define R_GPT_GTIOR_OBE_Msk (0x01000000UL)
|
||||
#define R_GPT_GTIOR_OBE_Pos (24UL)
|
||||
#define R_GPT_GTIOR_OBDF_Msk (0x06000000UL)
|
||||
#define R_GPT_GTIOR_OBDF_Pos (25UL)
|
||||
#define R_GPT_GTIOR_NFBEN_Msk (0x20000000UL)
|
||||
#define R_GPT_GTIOR_NFBEN_Pos (29UL)
|
||||
#define R_GPT_GTIOR_NFCSB_Msk (0xC0000000UL)
|
||||
#define R_GPT_GTIOR_NFCSB_Pos (30UL)
|
||||
#define R_GPT_GTINTAD_GTINTA_Msk (0x00000001UL)
|
||||
#define R_GPT_GTINTAD_GTINTA_Pos (0UL)
|
||||
#define R_GPT_GTINTAD_GTINTB_Msk (0x00000002UL)
|
||||
#define R_GPT_GTINTAD_GTINTB_Pos (1UL)
|
||||
#define R_GPT_GTINTAD_GTINTC_Msk (0x00000004UL)
|
||||
#define R_GPT_GTINTAD_GTINTC_Pos (2UL)
|
||||
#define R_GPT_GTINTAD_GTINTD_Msk (0x00000008UL)
|
||||
#define R_GPT_GTINTAD_GTINTD_Pos (3UL)
|
||||
#define R_GPT_GTINTAD_GTINTE_Msk (0x00000010UL)
|
||||
#define R_GPT_GTINTAD_GTINTE_Pos (4UL)
|
||||
#define R_GPT_GTINTAD_GTINTF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTINTAD_GTINTF_Pos (5UL)
|
||||
#define R_GPT_GTINTAD_GTINTPR_Msk (0x000000C0UL)
|
||||
#define R_GPT_GTINTAD_GTINTPR_Pos (6UL)
|
||||
#define R_GPT_GTINTAD_ADTRAUEN_Msk (0x00010000UL)
|
||||
#define R_GPT_GTINTAD_ADTRAUEN_Pos (16UL)
|
||||
#define R_GPT_GTINTAD_ADTRADEN_Msk (0x00020000UL)
|
||||
#define R_GPT_GTINTAD_ADTRADEN_Pos (17UL)
|
||||
#define R_GPT_GTINTAD_ADTRBUEN_Msk (0x00040000UL)
|
||||
#define R_GPT_GTINTAD_ADTRBUEN_Pos (18UL)
|
||||
#define R_GPT_GTINTAD_ADTRBDEN_Msk (0x00080000UL)
|
||||
#define R_GPT_GTINTAD_ADTRBDEN_Pos (19UL)
|
||||
#define R_GPT_GTINTAD_GRP_Msk (0x03000000UL)
|
||||
#define R_GPT_GTINTAD_GRP_Pos (24UL)
|
||||
#define R_GPT_GTINTAD_GRPDTE_Msk (0x10000000UL)
|
||||
#define R_GPT_GTINTAD_GRPDTE_Pos (28UL)
|
||||
#define R_GPT_GTINTAD_GRPABH_Msk (0x20000000UL)
|
||||
#define R_GPT_GTINTAD_GRPABH_Pos (29UL)
|
||||
#define R_GPT_GTINTAD_GRPABL_Msk (0x40000000UL)
|
||||
#define R_GPT_GTINTAD_GRPABL_Pos (30UL)
|
||||
#define R_GPT_GTST_TCFA_Msk (0x00000001UL)
|
||||
#define R_GPT_GTST_TCFA_Pos (0UL)
|
||||
#define R_GPT_GTST_TCFB_Msk (0x00000002UL)
|
||||
#define R_GPT_GTST_TCFB_Pos (1UL)
|
||||
#define R_GPT_GTST_TCFC_Msk (0x00000004UL)
|
||||
#define R_GPT_GTST_TCFC_Pos (2UL)
|
||||
#define R_GPT_GTST_TCFD_Msk (0x00000008UL)
|
||||
#define R_GPT_GTST_TCFD_Pos (3UL)
|
||||
#define R_GPT_GTST_TCFE_Msk (0x00000010UL)
|
||||
#define R_GPT_GTST_TCFE_Pos (4UL)
|
||||
#define R_GPT_GTST_TCFF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTST_TCFF_Pos (5UL)
|
||||
#define R_GPT_GTST_TCFPO_Msk (0x00000040UL)
|
||||
#define R_GPT_GTST_TCFPO_Pos (6UL)
|
||||
#define R_GPT_GTST_TCFPU_Msk (0x00000080UL)
|
||||
#define R_GPT_GTST_TCFPU_Pos (7UL)
|
||||
#define R_GPT_GTST_ITCNT_Msk (0x00000700UL)
|
||||
#define R_GPT_GTST_ITCNT_Pos (8UL)
|
||||
#define R_GPT_GTST_TUCF_Msk (0x00008000UL)
|
||||
#define R_GPT_GTST_TUCF_Pos (15UL)
|
||||
#define R_GPT_GTST_ADTRAUF_Msk (0x00010000UL)
|
||||
#define R_GPT_GTST_ADTRAUF_Pos (16UL)
|
||||
#define R_GPT_GTST_ADTRADF_Msk (0x00020000UL)
|
||||
#define R_GPT_GTST_ADTRADF_Pos (17UL)
|
||||
#define R_GPT_GTST_ADTRBUF_Msk (0x00040000UL)
|
||||
#define R_GPT_GTST_ADTRBUF_Pos (18UL)
|
||||
#define R_GPT_GTST_ADTRBDF_Msk (0x00080000UL)
|
||||
#define R_GPT_GTST_ADTRBDF_Pos (19UL)
|
||||
#define R_GPT_GTST_ODF_Msk (0x01000000UL)
|
||||
#define R_GPT_GTST_ODF_Pos (24UL)
|
||||
#define R_GPT_GTST_DTEF_Msk (0x10000000UL)
|
||||
#define R_GPT_GTST_DTEF_Pos (28UL)
|
||||
#define R_GPT_GTST_OABHF_Msk (0x20000000UL)
|
||||
#define R_GPT_GTST_OABHF_Pos (29UL)
|
||||
#define R_GPT_GTST_OABLF_Msk (0x40000000UL)
|
||||
#define R_GPT_GTST_OABLF_Pos (30UL)
|
||||
#define R_GPT_GTBER_BD_Msk (0x0000000FUL)
|
||||
#define R_GPT_GTBER_BD_Pos (0UL)
|
||||
#define R_GPT_GTBER_CCRA_Msk (0x00030000UL)
|
||||
#define R_GPT_GTBER_CCRA_Pos (16UL)
|
||||
#define R_GPT_GTBER_CCRB_Msk (0x000C0000UL)
|
||||
#define R_GPT_GTBER_CCRB_Pos (18UL)
|
||||
#define R_GPT_GTBER_PR_Msk (0x00300000UL)
|
||||
#define R_GPT_GTBER_PR_Pos (20UL)
|
||||
#define R_GPT_GTBER_CCRSWT_Msk (0x00400000UL)
|
||||
#define R_GPT_GTBER_CCRSWT_Pos (22UL)
|
||||
#define R_GPT_GTBER_ADTTA_Msk (0x03000000UL)
|
||||
#define R_GPT_GTBER_ADTTA_Pos (24UL)
|
||||
#define R_GPT_GTBER_ADTDA_Msk (0x04000000UL)
|
||||
#define R_GPT_GTBER_ADTDA_Pos (26UL)
|
||||
#define R_GPT_GTBER_ADTTB_Msk (0x30000000UL)
|
||||
#define R_GPT_GTBER_ADTTB_Pos (28UL)
|
||||
#define R_GPT_GTBER_ADTDB_Msk (0x40000000UL)
|
||||
#define R_GPT_GTBER_ADTDB_Pos (30UL)
|
||||
#define R_GPT_GTITC_ITLA_Msk (0x00000001UL)
|
||||
#define R_GPT_GTITC_ITLA_Pos (0UL)
|
||||
#define R_GPT_GTITC_ITLB_Msk (0x00000002UL)
|
||||
#define R_GPT_GTITC_ITLB_Pos (1UL)
|
||||
#define R_GPT_GTITC_ITLC_Msk (0x00000004UL)
|
||||
#define R_GPT_GTITC_ITLC_Pos (2UL)
|
||||
#define R_GPT_GTITC_ITLD_Msk (0x00000008UL)
|
||||
#define R_GPT_GTITC_ITLD_Pos (3UL)
|
||||
#define R_GPT_GTITC_ITLE_Msk (0x00000010UL)
|
||||
#define R_GPT_GTITC_ITLE_Pos (4UL)
|
||||
#define R_GPT_GTITC_ITLF_Msk (0x00000020UL)
|
||||
#define R_GPT_GTITC_ITLF_Pos (5UL)
|
||||
#define R_GPT_GTITC_IVTC_Msk (0x000000C0UL)
|
||||
#define R_GPT_GTITC_IVTC_Pos (6UL)
|
||||
#define R_GPT_GTITC_IVTT_Msk (0x00000700UL)
|
||||
#define R_GPT_GTITC_IVTT_Pos (8UL)
|
||||
#define R_GPT_GTITC_ADTAL_Msk (0x00001000UL)
|
||||
#define R_GPT_GTITC_ADTAL_Pos (12UL)
|
||||
#define R_GPT_GTITC_ADTBL_Msk (0x00004000UL)
|
||||
#define R_GPT_GTITC_ADTBL_Pos (14UL)
|
||||
#define R_GPT_GTCNT_GTCNT_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCNT_GTCNT_Pos (0UL)
|
||||
#define R_GPT_GTCCRA_GTCCRA_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCCRA_GTCCRA_Pos (0UL)
|
||||
#define R_GPT_GTCCRB_GTCCRB_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCCRB_GTCCRB_Pos (0UL)
|
||||
#define R_GPT_GTCCRC_GTCCRC_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCCRC_GTCCRC_Pos (0UL)
|
||||
#define R_GPT_GTCCRE_GTCCRE_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCCRE_GTCCRE_Pos (0UL)
|
||||
#define R_GPT_GTCCRD_GTCCRD_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCCRD_GTCCRD_Pos (0UL)
|
||||
#define R_GPT_GTCCRF_GTCCRF_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTCCRF_GTCCRF_Pos (0UL)
|
||||
#define R_GPT_GTPR_GTPR_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTPR_GTPR_Pos (0UL)
|
||||
#define R_GPT_GTPBR_GTPBR_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTPBR_GTPBR_Pos (0UL)
|
||||
#define R_GPT_GTPDBR_GTPDBR_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTPDBR_GTPDBR_Pos (0UL)
|
||||
#define R_GPT_GTADTRA_GTADTRA_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTADTRA_GTADTRA_Pos (0UL)
|
||||
#define R_GPT_GTADTBRA_GTADTBRA_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTADTBRA_GTADTBRA_Pos (0UL)
|
||||
#define R_GPT_GTADTDBRA_GTADTDBRA_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTADTDBRA_GTADTDBRA_Pos (0UL)
|
||||
#define R_GPT_GTADTRB_GTADTRB_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTADTRB_GTADTRB_Pos (0UL)
|
||||
#define R_GPT_GTADTBRB_GTADTBRB_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTADTBRB_GTADTBRB_Pos (0UL)
|
||||
#define R_GPT_GTADTDBRB_GTADTDBRB_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTADTDBRB_GTADTDBRB_Pos (0UL)
|
||||
#define R_GPT_GTDTCR_TDE_Msk (0x00000001UL)
|
||||
#define R_GPT_GTDTCR_TDE_Pos (0UL)
|
||||
#define R_GPT_GTDTCR_TDBUE_Msk (0x00000010UL)
|
||||
#define R_GPT_GTDTCR_TDBUE_Pos (4UL)
|
||||
#define R_GPT_GTDTCR_TDBDE_Msk (0x00000020UL)
|
||||
#define R_GPT_GTDTCR_TDBDE_Pos (5UL)
|
||||
#define R_GPT_GTDTCR_TDFER_Msk (0x00000100UL)
|
||||
#define R_GPT_GTDTCR_TDFER_Pos (8UL)
|
||||
#define R_GPT_GTDVU_GTDVU_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTDVU_GTDVU_Pos (0UL)
|
||||
#define R_GPT_GTDVD_GTDVD_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTDVD_GTDVD_Pos (0UL)
|
||||
#define R_GPT_GTDBU_GTDBU_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTDBU_GTDBU_Pos (0UL)
|
||||
#define R_GPT_GTDBD_GTDBD_Msk (0xFFFFFFFFUL)
|
||||
#define R_GPT_GTDBD_GTDBD_Pos (0UL)
|
||||
#define R_GPT_GTSOS_SOS_Msk (0x00000003UL)
|
||||
#define R_GPT_GTSOS_SOS_Pos (0UL)
|
||||
#define R_GPT_GTSOTR_SOTR_Msk (0x00000001UL)
|
||||
#define R_GPT_GTSOTR_SOTR_Pos (0UL)
|
||||
|
||||
#endif /* GPT_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : gtm_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for gtm.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef GTM_IOBITMASK_H
|
||||
#define GTM_IOBITMASK_H
|
||||
|
||||
#define R_GTM0_OSTMnCMP_OSTMnCMP_Msk (0xFFFFFFFFUL)
|
||||
#define R_GTM0_OSTMnCMP_OSTMnCMP_Pos (0UL)
|
||||
#define R_GTM0_OSTMnCNT_OSTMnCNT_Msk (0xFFFFFFFFUL)
|
||||
#define R_GTM0_OSTMnCNT_OSTMnCNT_Pos (0UL)
|
||||
#define R_GTM0_OSTMnTE_OSTMnTE_Msk (0x01UL)
|
||||
#define R_GTM0_OSTMnTE_OSTMnTE_Pos (0UL)
|
||||
#define R_GTM0_OSTMnTS_OSTMnTS_Msk (0x01UL)
|
||||
#define R_GTM0_OSTMnTS_OSTMnTS_Pos (0UL)
|
||||
#define R_GTM0_OSTMnTT_OSTMnTT_Msk (0x01UL)
|
||||
#define R_GTM0_OSTMnTT_OSTMnTT_Pos (0UL)
|
||||
#define R_GTM0_OSTMnCTL_OSTMnMD0_Msk (0x01UL)
|
||||
#define R_GTM0_OSTMnCTL_OSTMnMD0_Pos (0UL)
|
||||
#define R_GTM0_OSTMnCTL_OSTMnMD1_Msk (0x02UL)
|
||||
#define R_GTM0_OSTMnCTL_OSTMnMD1_Pos (1UL)
|
||||
|
||||
#endif /* GTM_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,511 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : intc_im33_iobitmask.h.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for intc_im33.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef INTC_IM33_IOBITMASK_H
|
||||
#define INTC_IM33_IOBITMASK_H
|
||||
|
||||
#define R_INTC_IM33_NSCR_NSTAT_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_NSCR_NSTAT_Pos (0UL)
|
||||
#define R_INTC_IM33_NSCR_NSMON_Msk (0x00010000UL)
|
||||
#define R_INTC_IM33_NSCR_NSMON_Pos (16UL)
|
||||
#define R_INTC_IM33_NITSR_NTSEL_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_NITSR_NTSEL_Pos (0UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT0_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT0_Pos (0UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT1_Msk (0x00000002UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT1_Pos (1UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT2_Msk (0x00000004UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT2_Pos (2UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT3_Msk (0x00000008UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT3_Pos (3UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT4_Msk (0x00000010UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT4_Pos (4UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT5_Msk (0x00000020UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT5_Pos (5UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT6_Msk (0x00000040UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT6_Pos (6UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT7_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_ISCR_ISTAT7_Pos (7UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL0_Msk (0x00000003UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL0_Pos (0UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL1_Msk (0x0000000CUL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL1_Pos (2UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL2_Msk (0x00000030UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL2_Pos (4UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL3_Msk (0x000000C0UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL3_Pos (6UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL4_Msk (0x00000300UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL4_Pos (8UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL5_Msk (0x00000C00UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL5_Pos (10UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL6_Msk (0x00003000UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL6_Pos (12UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL7_Msk (0x0000C000UL)
|
||||
#define R_INTC_IM33_IITSR_IITSEL7_Pos (14UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT0_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT0_Pos (0UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT1_Msk (0x00000002UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT1_Pos (1UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT2_Msk (0x00000004UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT2_Pos (2UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT3_Msk (0x00000008UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT3_Pos (3UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT4_Msk (0x00000010UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT4_Pos (4UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT5_Msk (0x00000020UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT5_Pos (5UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT6_Msk (0x00000040UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT6_Pos (6UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT7_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT7_Pos (7UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT8_Msk (0x00000100UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT8_Pos (8UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT9_Msk (0x00000200UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT9_Pos (9UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT10_Msk (0x00000400UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT10_Pos (10UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT11_Msk (0x00000800UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT11_Pos (11UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT12_Msk (0x00001000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT12_Pos (12UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT13_Msk (0x00002000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT13_Pos (13UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT14_Msk (0x00004000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT14_Pos (14UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT15_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT15_Pos (15UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT16_Msk (0x00010000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT16_Pos (16UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT17_Msk (0x00020000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT17_Pos (17UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT18_Msk (0x00040000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT18_Pos (18UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT19_Msk (0x00080000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT19_Pos (19UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT20_Msk (0x00100000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT20_Pos (20UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT21_Msk (0x00200000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT21_Pos (21UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT22_Msk (0x00400000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT22_Pos (22UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT23_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT23_Pos (23UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT24_Msk (0x01000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT24_Pos (24UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT25_Msk (0x02000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT25_Pos (25UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT26_Msk (0x04000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT26_Pos (26UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT27_Msk (0x08000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT27_Pos (27UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT28_Msk (0x10000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT28_Pos (28UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT29_Msk (0x20000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT29_Pos (29UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT30_Msk (0x40000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT30_Pos (30UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT31_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSCR_TSTAT31_Pos (31UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL0_Msk (0x00000003UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL0_Pos (0UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL1_Msk (0x0000000CUL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL1_Pos (2UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL2_Msk (0x00000030UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL2_Pos (4UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL3_Msk (0x000000C0UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL3_Pos (6UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL4_Msk (0x00000300UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL4_Pos (8UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL5_Msk (0x00000C00UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL5_Pos (10UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL6_Msk (0x00003000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL6_Pos (12UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL7_Msk (0x0000C000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL7_Pos (14UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL8_Msk (0x00030000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL8_Pos (16UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL9_Msk (0x000C0000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL9_Pos (18UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL10_Msk (0x00300000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL10_Pos (20UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL11_Msk (0x00C00000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL11_Pos (22UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL12_Msk (0x03000000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL12_Pos (24UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL13_Msk (0x0C000000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL13_Pos (26UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL14_Msk (0x30000000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL14_Pos (28UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL15_Msk (0xC0000000UL)
|
||||
#define R_INTC_IM33_TITSR0_TITSEL15_Pos (30UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL16_Msk (0x00000003UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL16_Pos (0UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL17_Msk (0x0000000CUL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL17_Pos (2UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL18_Msk (0x00000030UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL18_Pos (4UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL19_Msk (0x000000C0UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL19_Pos (6UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL20_Msk (0x00000300UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL20_Pos (8UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL21_Msk (0x00000C00UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL21_Pos (10UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL22_Msk (0x00003000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL22_Pos (12UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL23_Msk (0x0000C000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL23_Pos (14UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL24_Msk (0x00030000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL24_Pos (16UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL25_Msk (0x000C0000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL25_Pos (18UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL26_Msk (0x00300000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL26_Pos (20UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL27_Msk (0x00C00000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL27_Pos (22UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL28_Msk (0x03000000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL28_Pos (24UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL29_Msk (0x0C000000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL29_Pos (26UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL30_Msk (0x30000000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL30_Pos (28UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL31_Msk (0xC0000000UL)
|
||||
#define R_INTC_IM33_TITSR1_TITSEL31_Pos (30UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL0_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL0_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN0_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN0_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL1_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL1_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN1_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN1_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL2_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL2_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN2_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN2_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL3_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR0_TSSEL3_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN3_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR0_TIEN3_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL4_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL4_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN4_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN4_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL5_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL5_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN5_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN5_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL6_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL6_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN6_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN6_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL7_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR1_TSSEL7_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN7_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR1_TIEN7_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL8_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL8_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN8_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN8_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL9_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL9_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN9_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN9_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL10_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL10_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN10_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN10_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL11_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR2_TSSEL11_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN11_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR2_TIEN11_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL12_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL12_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN12_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN12_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL13_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL13_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN13_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN13_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL14_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL14_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN14_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN14_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL15_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR3_TSSEL15_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN15_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR3_TIEN15_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL16_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL16_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN16_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN16_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL17_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL17_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN17_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN17_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL18_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL18_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN18_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN18_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL19_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR4_TSSEL19_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN19_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR4_TIEN19_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL20_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL20_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN20_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN20_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL21_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL21_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN21_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN21_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL22_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL22_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN22_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN22_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL23_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR5_TSSEL23_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN23_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR5_TIEN23_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL24_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL24_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN24_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN24_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL25_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL25_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN25_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN25_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL26_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL26_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN26_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN26_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL27_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR6_TSSEL27_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN27_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR6_TIEN27_Pos (31UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL28_Msk (0x0000007FUL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL28_Pos (0UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN28_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN28_Pos (7UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL29_Msk (0x00007F00UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL29_Pos (8UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN29_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN29_Pos (15UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL30_Msk (0x007F0000UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL30_Pos (16UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN30_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN30_Pos (23UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL31_Msk (0x7F000000UL)
|
||||
#define R_INTC_IM33_TSSR7_TSSEL31_Pos (24UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN31_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_TSSR7_TIEN31_Pos (31UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT0_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT0_Pos (0UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT1_Msk (0x00000002UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT1_Pos (1UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT2_Msk (0x00000004UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT2_Pos (2UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT3_Msk (0x00000008UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT3_Pos (3UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT4_Msk (0x00000010UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT4_Pos (4UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT5_Msk (0x00000020UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT5_Pos (5UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT6_Msk (0x00000040UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT6_Pos (6UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT7_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT7_Pos (7UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT8_Msk (0x00000100UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT8_Pos (8UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT9_Msk (0x00000200UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT9_Pos (9UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT10_Msk (0x00000400UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT10_Pos (10UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT11_Msk (0x00000800UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT11_Pos (11UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT12_Msk (0x00001000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT12_Pos (12UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT13_Msk (0x00002000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT13_Pos (13UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT14_Msk (0x00004000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT14_Pos (14UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT15_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT15_Pos (15UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT16_Msk (0x00010000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT16_Pos (16UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT17_Msk (0x00020000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT17_Pos (17UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT18_Msk (0x00040000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT18_Pos (18UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT19_Msk (0x00080000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT19_Pos (19UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT20_Msk (0x00100000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT20_Pos (20UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT21_Msk (0x00200000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT21_Pos (21UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT22_Msk (0x00400000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT22_Pos (22UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT23_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT23_Pos (23UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT24_Msk (0x01000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT24_Pos (24UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT25_Msk (0x02000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT25_Pos (25UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT26_Msk (0x04000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT26_Pos (26UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT27_Msk (0x08000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT27_Pos (27UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT28_Msk (0x10000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT28_Pos (28UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT29_Msk (0x20000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT29_Pos (29UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT30_Msk (0x40000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT30_Pos (30UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT31_Msk (0x80000000UL)
|
||||
#define R_INTC_IM33_BEISR0_BESTAT31_Pos (31UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT32_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT32_Pos (0UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT33_Msk (0x00000002UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT33_Pos (1UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT34_Msk (0x00000004UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT34_Pos (2UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT35_Msk (0x00000008UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT35_Pos (3UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT36_Msk (0x00000010UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT36_Pos (4UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT37_Msk (0x00000020UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT37_Pos (5UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT38_Msk (0x00000040UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT38_Pos (6UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT39_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT39_Pos (7UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT40_Msk (0x00000100UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT40_Pos (8UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT41_Msk (0x00000200UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT41_Pos (9UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT42_Msk (0x00000400UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT42_Pos (10UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT43_Msk (0x00000800UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT43_Pos (11UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT44_Msk (0x00001000UL)
|
||||
#define R_INTC_IM33_BEISR1_BESTAT44_Pos (12UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT0_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT0_Pos (0UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT1_Msk (0x00000002UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT1_Pos (1UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT2_Msk (0x00000004UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT2_Pos (2UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT3_Msk (0x00000008UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT3_Pos (3UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT4_Msk (0x00000010UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT4_Pos (4UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT5_Msk (0x00000020UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT5_Pos (5UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT6_Msk (0x00000040UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT6_Pos (6UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT7_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_EREISR0_E1STAT7_Pos (7UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT0_Msk (0x00000100UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT0_Pos (8UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT1_Msk (0x00000200UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT1_Pos (9UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT2_Msk (0x00000400UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT2_Pos (10UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT3_Msk (0x00000800UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT3_Pos (11UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT4_Msk (0x00001000UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT4_Pos (12UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT5_Msk (0x00002000UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT5_Pos (13UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT6_Msk (0x00004000UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT6_Pos (14UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT7_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_EREISR0_E2STAT7_Pos (15UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT0_Msk (0x00010000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT0_Pos (16UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT1_Msk (0x00020000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT1_Pos (17UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT2_Msk (0x00040000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT2_Pos (18UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT3_Msk (0x00080000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT3_Pos (19UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT4_Msk (0x00100000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT4_Pos (20UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT5_Msk (0x00200000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT5_Pos (21UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT6_Msk (0x00400000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT6_Pos (22UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT7_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_EREISR0_OFSTAT7_Pos (23UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT0_Msk (0x00000001UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT0_Pos (0UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT1_Msk (0x00000002UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT1_Pos (1UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT2_Msk (0x00000004UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT2_Pos (2UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT3_Msk (0x00000008UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT3_Pos (3UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT4_Msk (0x00000010UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT4_Pos (4UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT5_Msk (0x00000020UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT5_Pos (5UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT6_Msk (0x00000040UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT6_Pos (6UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT7_Msk (0x00000080UL)
|
||||
#define R_INTC_IM33_EREISR1_E1STAT7_Pos (7UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT0_Msk (0x00000100UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT0_Pos (8UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT1_Msk (0x00000200UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT1_Pos (9UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT2_Msk (0x00000400UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT2_Pos (10UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT3_Msk (0x00000800UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT3_Pos (11UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT4_Msk (0x00001000UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT4_Pos (12UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT5_Msk (0x00002000UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT5_Pos (13UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT6_Msk (0x00004000UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT6_Pos (14UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT7_Msk (0x00008000UL)
|
||||
#define R_INTC_IM33_EREISR1_E2STAT7_Pos (15UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT0_Msk (0x00010000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT0_Pos (16UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT1_Msk (0x00020000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT1_Pos (17UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT2_Msk (0x00040000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT2_Pos (18UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT3_Msk (0x00080000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT3_Pos (19UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT4_Msk (0x00100000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT4_Pos (20UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT5_Msk (0x00200000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT5_Pos (21UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT6_Msk (0x00400000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT6_Pos (22UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT7_Msk (0x00800000UL)
|
||||
#define R_INTC_IM33_EREISR1_OFSTAT7_Pos (23UL)
|
||||
|
||||
#endif /* INTC_IM33_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : mhu_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for mhu.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef MHU_IOBITMASK_H
|
||||
#define MHU_IOBITMASK_H
|
||||
|
||||
#define R_MHU0_MSG_INT_STSn_STAT_Msk (0x00000001UL)
|
||||
#define R_MHU0_MSG_INT_STSn_STAT_Pos (0UL)
|
||||
#define R_MHU0_MSG_INT_SETn_SET_Msk (0x00000001UL)
|
||||
#define R_MHU0_MSG_INT_SETn_SET_Pos (0UL)
|
||||
#define R_MHU0_MSG_INT_CLRn_CLEAR_Msk (0x00000001UL)
|
||||
#define R_MHU0_MSG_INT_CLRn_CLEAR_Pos (0UL)
|
||||
#define R_MHU0_RSP_INT_STSn_STAT_Msk (0x00000001UL)
|
||||
#define R_MHU0_RSP_INT_STSn_STAT_Pos (0UL)
|
||||
#define R_MHU0_RSP_INT_SETn_SET_Msk (0x00000001UL)
|
||||
#define R_MHU0_RSP_INT_SETn_SET_Pos (0UL)
|
||||
#define R_MHU0_RSP_INT_CLRn_CLEAR_Msk (0x00000001UL)
|
||||
#define R_MHU0_RSP_INT_CLRn_CLEAR_Pos (0UL)
|
||||
#define R_MHU0_SW_INT_STSn_STAT_Msk (0x00000001UL)
|
||||
#define R_MHU0_SW_INT_STSn_STAT_Pos (0UL)
|
||||
#define R_MHU0_SW_INT_SETn_SET_Msk (0x00000001UL)
|
||||
#define R_MHU0_SW_INT_SETn_SET_Pos (0UL)
|
||||
#define R_MHU0_SW_INT_CLRn_CLEAR_Msk (0x00000001UL)
|
||||
#define R_MHU0_SW_INT_CLRn_CLEAR_Pos (0UL)
|
||||
|
||||
#endif /* MHU_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : mstp_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for mstp.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef MSTP_IOBITMASK_H
|
||||
#define MSTP_IOBITMASK_H
|
||||
|
||||
#define R_MSTP_ACPU_MXSRAM_A_Msk (0x00000001UL)
|
||||
#define R_MSTP_ACPU_MXSRAM_A_Pos (0UL)
|
||||
#define R_MSTP_MCPU1_MXSRAM_M_Msk (0x00000001UL)
|
||||
#define R_MSTP_MCPU1_MXSRAM_M_Pos (0UL)
|
||||
#define R_MSTP_MCPU1_MHSPI_Msk (0x00000002UL)
|
||||
#define R_MSTP_MCPU1_MHSPI_Pos (1UL)
|
||||
#define R_MSTP_MCPU1_MHMTU3A_Msk (0x00000004UL)
|
||||
#define R_MSTP_MCPU1_MHMTU3A_Pos (2UL)
|
||||
#define R_MSTP_MCPU1_MHSRC_Msk (0x00000008UL)
|
||||
#define R_MSTP_MCPU1_MHSRC_Pos (3UL)
|
||||
#define R_MSTP_MCPU1_MHGPT_Msk (0x00000010UL)
|
||||
#define R_MSTP_MCPU1_MHGPT_Pos (4UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGA_Msk (0x00000020UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGA_Pos (5UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGB_Msk (0x00000040UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGB_Pos (6UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGC_Msk (0x00000080UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGC_Pos (7UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGD_Msk (0x00000100UL)
|
||||
#define R_MSTP_MCPU1_MHPOEGD_Pos (8UL)
|
||||
#define R_MSTP_MCPU1_MHPOE3_Msk (0x00000200UL)
|
||||
#define R_MSTP_MCPU1_MHPOE3_Pos (9UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF0_Msk (0x00000400UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF0_Pos (10UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF1_Msk (0x00000800UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF1_Pos (11UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF2_Msk (0x00001000UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF2_Pos (12UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF3_Msk (0x00002000UL)
|
||||
#define R_MSTP_MCPU1_MHSSIF3_Pos (13UL)
|
||||
#define R_MSTP_MCPU1_MHRSPI0_Msk (0x00004000UL)
|
||||
#define R_MSTP_MCPU1_MHRSPI0_Pos (14UL)
|
||||
#define R_MSTP_MCPU1_MHRSPI1_Msk (0x00008000UL)
|
||||
#define R_MSTP_MCPU1_MHRSPI1_Pos (15UL)
|
||||
#define R_MSTP_MCPU2_MHRSPI2_Msk (0x00000001UL)
|
||||
#define R_MSTP_MCPU2_MHRSPI2_Pos (0UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF0_Msk (0x00000002UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF0_Pos (1UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF1_Msk (0x00000004UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF1_Pos (2UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF2_Msk (0x00000008UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF2_Pos (3UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF3_Msk (0x00000010UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF3_Pos (4UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF4_Msk (0x00000020UL)
|
||||
#define R_MSTP_MCPU2_MHSCIF4_Pos (5UL)
|
||||
#define R_MSTP_MCPU2_MHIRDA_Msk (0x00000040UL)
|
||||
#define R_MSTP_MCPU2_MHIRDA_Pos (6UL)
|
||||
#define R_MSTP_MCPU2_MHSCI0_Msk (0x00000080UL)
|
||||
#define R_MSTP_MCPU2_MHSCI0_Pos (7UL)
|
||||
#define R_MSTP_MCPU2_MHSCI1_Msk (0x00000100UL)
|
||||
#define R_MSTP_MCPU2_MHSCI1_Pos (8UL)
|
||||
#define R_MSTP_MCPU2_MPCANFD_Msk (0x00000200UL)
|
||||
#define R_MSTP_MCPU2_MPCANFD_Pos (9UL)
|
||||
#define R_MSTP_MCPU2_MPI2C0_Msk (0x00000400UL)
|
||||
#define R_MSTP_MCPU2_MPI2C0_Pos (10UL)
|
||||
#define R_MSTP_MCPU2_MPI2C1_Msk (0x00000800UL)
|
||||
#define R_MSTP_MCPU2_MPI2C1_Pos (11UL)
|
||||
#define R_MSTP_MCPU2_MPI2C2_Msk (0x00001000UL)
|
||||
#define R_MSTP_MCPU2_MPI2C2_Pos (12UL)
|
||||
#define R_MSTP_MCPU2_MPI2C3_Msk (0x00002000UL)
|
||||
#define R_MSTP_MCPU2_MPI2C3_Pos (13UL)
|
||||
#define R_MSTP_MCPU2_MPADC_Msk (0x00004000UL)
|
||||
#define R_MSTP_MCPU2_MPADC_Pos (14UL)
|
||||
#define R_MSTP_MCPU2_MPTSU_Msk (0x00008000UL)
|
||||
#define R_MSTP_MCPU2_MPTSU_Pos (15UL)
|
||||
#define R_MSTP_PERI_COM_MXSDHI0_Msk (0x00000001UL)
|
||||
#define R_MSTP_PERI_COM_MXSDHI0_Pos (0UL)
|
||||
#define R_MSTP_PERI_COM_MXSDHI1_Msk (0x00000002UL)
|
||||
#define R_MSTP_PERI_COM_MXSDHI1_Pos (1UL)
|
||||
#define R_MSTP_PERI_COM_MPGIGE0_Msk (0x00000004UL)
|
||||
#define R_MSTP_PERI_COM_MPGIGE0_Pos (2UL)
|
||||
#define R_MSTP_PERI_COM_MPGIGE1_Msk (0x00000008UL)
|
||||
#define R_MSTP_PERI_COM_MPGIGE1_Pos (3UL)
|
||||
#define R_MSTP_PERI_COM_MPUSBT_Msk (0x00000010UL)
|
||||
#define R_MSTP_PERI_COM_MPUSBT_Pos (4UL)
|
||||
#define R_MSTP_PERI_COM_MHUSB2H_Msk (0x00000020UL)
|
||||
#define R_MSTP_PERI_COM_MHUSB2H_Pos (5UL)
|
||||
#define R_MSTP_PERI_COM_MHUSB2F_Msk (0x00000040UL)
|
||||
#define R_MSTP_PERI_COM_MHUSB2F_Pos (6UL)
|
||||
#define R_MSTP_PERI_COM_MHUSB21_Msk (0x00000080UL)
|
||||
#define R_MSTP_PERI_COM_MHUSB21_Pos (7UL)
|
||||
#define R_MSTP_PERI_COM_MXCOM_Msk (0x00000100UL)
|
||||
#define R_MSTP_PERI_COM_MXCOM_Pos (8UL)
|
||||
#define R_MSTP_PERI_CPU_MXMCPU_Msk (0x00000001UL)
|
||||
#define R_MSTP_PERI_CPU_MXMCPU_Pos (0UL)
|
||||
#define R_MSTP_PERI_CPU_MXACPU_Msk (0x00000002UL)
|
||||
#define R_MSTP_PERI_CPU_MXACPU_Pos (1UL)
|
||||
#define R_MSTP_PERI_CPU_MPCST_Msk (0x00000004UL)
|
||||
#define R_MSTP_PERI_CPU_MPCST_Pos (2UL)
|
||||
#define R_MSTP_PERI_CPU_MPSYC_Msk (0x00000008UL)
|
||||
#define R_MSTP_PERI_CPU_MPSYC_Pos (3UL)
|
||||
#define R_MSTP_PERI_CPU_MPCPG_Msk (0x00000010UL)
|
||||
#define R_MSTP_PERI_CPU_MPCPG_Pos (4UL)
|
||||
#define R_MSTP_PERI_CPU_MHGPIO_Msk (0x00000040UL)
|
||||
#define R_MSTP_PERI_CPU_MHGPIO_Pos (6UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC0_Msk (0x00000080UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC0_Pos (7UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC1_Msk (0x00000100UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC1_Pos (8UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC2_Msk (0x00000200UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC2_Pos (9UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC3_Msk (0x00000400UL)
|
||||
#define R_MSTP_PERI_CPU_MPTZC3_Pos (10UL)
|
||||
#define R_MSTP_PERI_CPU_MPSRAM_A_Msk (0x00000800UL)
|
||||
#define R_MSTP_PERI_CPU_MPSRAM_A_Pos (11UL)
|
||||
#define R_MSTP_PERI_CPU_MPSRAM_M_Msk (0x00001000UL)
|
||||
#define R_MSTP_PERI_CPU_MPSRAM_M_Pos (12UL)
|
||||
#define R_MSTP_PERI_CPU_MPIA55_Msk (0x00002000UL)
|
||||
#define R_MSTP_PERI_CPU_MPIA55_Pos (13UL)
|
||||
#define R_MSTP_PERI_CPU_MPIM33_Msk (0x00004000UL)
|
||||
#define R_MSTP_PERI_CPU_MPIM33_Pos (14UL)
|
||||
#define R_MSTP_PERI_CPU_MXREG0_Msk (0x00008000UL)
|
||||
#define R_MSTP_PERI_CPU_MXREG0_Pos (15UL)
|
||||
#define R_MSTP_PERI_DDR_MPPHY_Msk (0x00000001UL)
|
||||
#define R_MSTP_PERI_DDR_MPPHY_Pos (0UL)
|
||||
#define R_MSTP_PERI_DDR_MXMEMC_REG_Msk (0x00000002UL)
|
||||
#define R_MSTP_PERI_DDR_MXMEMC_REG_Pos (1UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPVCP4L_V_Msk (0x00000001UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPVCP4L_V_Pos (0UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPVCP4L_C_Msk (0x00000002UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPVCP4L_C_Pos (1UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPFCPCS_Msk (0x00000004UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPFCPCS_Pos (2UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPCRU_Msk (0x00000008UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPCRU_Pos (3UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPISU_Msk (0x00000010UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPISU_Pos (4UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPDSIPHY_Msk (0x00000020UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPDSIPHY_Pos (5UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPDSIL_Msk (0x00000040UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPDSIL_Pos (6UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPVSPD_Msk (0x00000080UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPVSPD_Pos (7UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPCPVD_Msk (0x00000100UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPCPVD_Pos (8UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPDU_Msk (0x00000200UL)
|
||||
#define R_MSTP_PERI_VIDEO_MPDU_Pos (9UL)
|
||||
#define R_MSTP_PERI_VIDEO_MXVIDEO_Msk (0x00000400UL)
|
||||
#define R_MSTP_PERI_VIDEO_MXVIDEO_Pos (10UL)
|
||||
#define R_MSTP_REG0_MPWDT3_Msk (0x00000001UL)
|
||||
#define R_MSTP_REG0_MPWDT3_Pos (0UL)
|
||||
#define R_MSTP_REG0_MPWDT2_Msk (0x00000002UL)
|
||||
#define R_MSTP_REG0_MPWDT2_Pos (1UL)
|
||||
#define R_MSTP_REG0_MPWDT0_Msk (0x00000004UL)
|
||||
#define R_MSTP_REG0_MPWDT0_Pos (2UL)
|
||||
#define R_MSTP_REG0_MPWDT1_Msk (0x00000008UL)
|
||||
#define R_MSTP_REG0_MPWDT1_Pos (3UL)
|
||||
#define R_MSTP_REG0_MPOSTM0_Msk (0x00000010UL)
|
||||
#define R_MSTP_REG0_MPOSTM0_Pos (4UL)
|
||||
#define R_MSTP_REG0_MPOSTM1_Msk (0x00000020UL)
|
||||
#define R_MSTP_REG0_MPOSTM1_Pos (5UL)
|
||||
#define R_MSTP_REG0_MPOSTM2_Msk (0x00000040UL)
|
||||
#define R_MSTP_REG0_MPOSTM2_Pos (6UL)
|
||||
#define R_MSTP_REG1_MXDMAC_S_Msk (0x00000001UL)
|
||||
#define R_MSTP_REG1_MXDMAC_S_Pos (0UL)
|
||||
#define R_MSTP_REG1_MPDMAC_S_Msk (0x00000002UL)
|
||||
#define R_MSTP_REG1_MPDMAC_S_Pos (1UL)
|
||||
#define R_MSTP_REG1_MXDMAC_NS_Msk (0x00000004UL)
|
||||
#define R_MSTP_REG1_MXDMAC_NS_Pos (2UL)
|
||||
#define R_MSTP_REG1_MPDMAC_NS_Msk (0x00000008UL)
|
||||
#define R_MSTP_REG1_MPDMAC_NS_Pos (3UL)
|
||||
#define R_MSTP_REG1_MXMALI_Msk (0x00000010UL)
|
||||
#define R_MSTP_REG1_MXMALI_Pos (4UL)
|
||||
#define R_MSTP_REG1_MHTSIPG_Msk (0x00000020UL)
|
||||
#define R_MSTP_REG1_MHTSIPG_Pos (5UL)
|
||||
#define R_MSTP_REG1_MHTSIPG_OTP_Msk (0x00000040UL)
|
||||
#define R_MSTP_REG1_MHTSIPG_OTP_Pos (6UL)
|
||||
#define R_MSTP_REG1_MXGIC_Msk (0x00000080UL)
|
||||
#define R_MSTP_REG1_MXGIC_Pos (7UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP0_Msk (0x00000001UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP0_Pos (0UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP1_Msk (0x00000002UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP1_Pos (1UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP2_Msk (0x00000004UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP2_Pos (2UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP3_Msk (0x00000008UL)
|
||||
#define R_MSTP_TZCDDR_MSTOP3_Pos (3UL)
|
||||
#define R_MSTP_MHU_MSTOP_Msk (0x00000001UL)
|
||||
#define R_MSTP_MHU_MSTOP_Pos (0UL)
|
||||
|
||||
#endif /* MSTP_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : poeg_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for poeg.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef POEG_IOBITMASK_H
|
||||
#define POEG_IOBITMASK_H
|
||||
|
||||
#define R_POEG_POEGGn_PIDF_Msk (0x00000001UL)
|
||||
#define R_POEG_POEGGn_PIDF_Pos (0UL)
|
||||
#define R_POEG_POEGGn_IOCF_Msk (0x00000002UL)
|
||||
#define R_POEG_POEGGn_IOCF_Pos (1UL)
|
||||
#define R_POEG_POEGGn_SSF_Msk (0x00000008UL)
|
||||
#define R_POEG_POEGGn_SSF_Pos (3UL)
|
||||
#define R_POEG_POEGGn_PIDE_Msk (0x00000010UL)
|
||||
#define R_POEG_POEGGn_PIDE_Pos (4UL)
|
||||
#define R_POEG_POEGGn_IOCE_Msk (0x00000020UL)
|
||||
#define R_POEG_POEGGn_IOCE_Pos (5UL)
|
||||
#define R_POEG_POEGGn_ST_Msk (0x00010000UL)
|
||||
#define R_POEG_POEGGn_ST_Pos (16UL)
|
||||
#define R_POEG_POEGGn_INV_Msk (0x10000000UL)
|
||||
#define R_POEG_POEGGn_INV_Pos (28UL)
|
||||
#define R_POEG_POEGGn_NFEN_Msk (0x20000000UL)
|
||||
#define R_POEG_POEGGn_NFEN_Pos (29UL)
|
||||
#define R_POEG_POEGGn_NFCS_Msk (0xC0000000UL)
|
||||
#define R_POEG_POEGGn_NFCS_Pos (30UL)
|
||||
|
||||
#endif /* POEG_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : riic_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for riic.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef RIIC_IOBITMASK_H
|
||||
#define RIIC_IOBITMASK_H
|
||||
|
||||
#define R_RIIC0_ICCR1_SDAI_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICCR1_SDAI_Pos (0UL)
|
||||
#define R_RIIC0_ICCR1_SCLI_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICCR1_SCLI_Pos (1UL)
|
||||
#define R_RIIC0_ICCR1_SDAO_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICCR1_SDAO_Pos (2UL)
|
||||
#define R_RIIC0_ICCR1_SCLO_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICCR1_SCLO_Pos (3UL)
|
||||
#define R_RIIC0_ICCR1_SOWP_Msk (0x00000010UL)
|
||||
#define R_RIIC0_ICCR1_SOWP_Pos (4UL)
|
||||
#define R_RIIC0_ICCR1_CLO_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICCR1_CLO_Pos (5UL)
|
||||
#define R_RIIC0_ICCR1_IICRST_Msk (0x00000040UL)
|
||||
#define R_RIIC0_ICCR1_IICRST_Pos (6UL)
|
||||
#define R_RIIC0_ICCR1_ICE_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICCR1_ICE_Pos (7UL)
|
||||
#define R_RIIC0_ICCR2_ST_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICCR2_ST_Pos (1UL)
|
||||
#define R_RIIC0_ICCR2_RS_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICCR2_RS_Pos (2UL)
|
||||
#define R_RIIC0_ICCR2_SP_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICCR2_SP_Pos (3UL)
|
||||
#define R_RIIC0_ICCR2_TRS_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICCR2_TRS_Pos (5UL)
|
||||
#define R_RIIC0_ICCR2_MST_Msk (0x00000040UL)
|
||||
#define R_RIIC0_ICCR2_MST_Pos (6UL)
|
||||
#define R_RIIC0_ICCR2_BBSY_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICCR2_BBSY_Pos (7UL)
|
||||
#define R_RIIC0_ICMR1_BC_Msk (0x00000007UL)
|
||||
#define R_RIIC0_ICMR1_BC_Pos (0UL)
|
||||
#define R_RIIC0_ICMR1_BCWP_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICMR1_BCWP_Pos (3UL)
|
||||
#define R_RIIC0_ICMR1_CKS_Msk (0x00000070UL)
|
||||
#define R_RIIC0_ICMR1_CKS_Pos (4UL)
|
||||
#define R_RIIC0_ICMR2_TMOS_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICMR2_TMOS_Pos (0UL)
|
||||
#define R_RIIC0_ICMR2_TMOL_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICMR2_TMOL_Pos (1UL)
|
||||
#define R_RIIC0_ICMR2_TMOH_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICMR2_TMOH_Pos (2UL)
|
||||
#define R_RIIC0_ICMR2_SDDL_Msk (0x00000070UL)
|
||||
#define R_RIIC0_ICMR2_SDDL_Pos (4UL)
|
||||
#define R_RIIC0_ICMR2_DLCS_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICMR2_DLCS_Pos (7UL)
|
||||
#define R_RIIC0_ICMR3_NF_Msk (0x00000003UL)
|
||||
#define R_RIIC0_ICMR3_NF_Pos (0UL)
|
||||
#define R_RIIC0_ICMR3_ACKBR_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICMR3_ACKBR_Pos (2UL)
|
||||
#define R_RIIC0_ICMR3_ACKBT_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICMR3_ACKBT_Pos (3UL)
|
||||
#define R_RIIC0_ICMR3_ACKWP_Msk (0x00000010UL)
|
||||
#define R_RIIC0_ICMR3_ACKWP_Pos (4UL)
|
||||
#define R_RIIC0_ICMR3_RDRFS_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICMR3_RDRFS_Pos (5UL)
|
||||
#define R_RIIC0_ICMR3_WAIT_Msk (0x00000040UL)
|
||||
#define R_RIIC0_ICMR3_WAIT_Pos (6UL)
|
||||
#define R_RIIC0_ICMR3_SMBE_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICMR3_SMBE_Pos (7UL)
|
||||
#define R_RIIC0_ICFER_TMOE_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICFER_TMOE_Pos (0UL)
|
||||
#define R_RIIC0_ICFER_MALE_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICFER_MALE_Pos (1UL)
|
||||
#define R_RIIC0_ICFER_NALE_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICFER_NALE_Pos (2UL)
|
||||
#define R_RIIC0_ICFER_SALE_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICFER_SALE_Pos (3UL)
|
||||
#define R_RIIC0_ICFER_NACKE_Msk (0x00000010UL)
|
||||
#define R_RIIC0_ICFER_NACKE_Pos (4UL)
|
||||
#define R_RIIC0_ICFER_NFE_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICFER_NFE_Pos (5UL)
|
||||
#define R_RIIC0_ICFER_SCLE_Msk (0x00000040UL)
|
||||
#define R_RIIC0_ICFER_SCLE_Pos (6UL)
|
||||
#define R_RIIC0_ICFER_FMPE_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICFER_FMPE_Pos (7UL)
|
||||
#define R_RIIC0_ICSER_SAR0_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICSER_SAR0_Pos (0UL)
|
||||
#define R_RIIC0_ICSER_SAR1_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICSER_SAR1_Pos (1UL)
|
||||
#define R_RIIC0_ICSER_SAR2_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICSER_SAR2_Pos (2UL)
|
||||
#define R_RIIC0_ICSER_GCE_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICSER_GCE_Pos (3UL)
|
||||
#define R_RIIC0_ICSER_DIDE_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICSER_DIDE_Pos (5UL)
|
||||
#define R_RIIC0_ICSER_HOAE_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICSER_HOAE_Pos (7UL)
|
||||
#define R_RIIC0_ICIER_TMOIE_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICIER_TMOIE_Pos (0UL)
|
||||
#define R_RIIC0_ICIER_ALIE_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICIER_ALIE_Pos (1UL)
|
||||
#define R_RIIC0_ICIER_STIE_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICIER_STIE_Pos (2UL)
|
||||
#define R_RIIC0_ICIER_SPIE_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICIER_SPIE_Pos (3UL)
|
||||
#define R_RIIC0_ICIER_NAKIE_Msk (0x00000010UL)
|
||||
#define R_RIIC0_ICIER_NAKIE_Pos (4UL)
|
||||
#define R_RIIC0_ICIER_RIE_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICIER_RIE_Pos (5UL)
|
||||
#define R_RIIC0_ICIER_TEIE_Msk (0x00000040UL)
|
||||
#define R_RIIC0_ICIER_TEIE_Pos (6UL)
|
||||
#define R_RIIC0_ICIER_TIE_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICIER_TIE_Pos (7UL)
|
||||
#define R_RIIC0_ICSR1_AAS0_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICSR1_AAS0_Pos (0UL)
|
||||
#define R_RIIC0_ICSR1_AAS1_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICSR1_AAS1_Pos (1UL)
|
||||
#define R_RIIC0_ICSR1_AAS2_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICSR1_AAS2_Pos (2UL)
|
||||
#define R_RIIC0_ICSR1_GCA_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICSR1_GCA_Pos (3UL)
|
||||
#define R_RIIC0_ICSR1_DID_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICSR1_DID_Pos (5UL)
|
||||
#define R_RIIC0_ICSR1_HOA_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICSR1_HOA_Pos (7UL)
|
||||
#define R_RIIC0_ICSR2_TMOF_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICSR2_TMOF_Pos (0UL)
|
||||
#define R_RIIC0_ICSR2_AL_Msk (0x00000002UL)
|
||||
#define R_RIIC0_ICSR2_AL_Pos (1UL)
|
||||
#define R_RIIC0_ICSR2_START_Msk (0x00000004UL)
|
||||
#define R_RIIC0_ICSR2_START_Pos (2UL)
|
||||
#define R_RIIC0_ICSR2_STOP_Msk (0x00000008UL)
|
||||
#define R_RIIC0_ICSR2_STOP_Pos (3UL)
|
||||
#define R_RIIC0_ICSR2_NACKF_Msk (0x00000010UL)
|
||||
#define R_RIIC0_ICSR2_NACKF_Pos (4UL)
|
||||
#define R_RIIC0_ICSR2_RDRF_Msk (0x00000020UL)
|
||||
#define R_RIIC0_ICSR2_RDRF_Pos (5UL)
|
||||
#define R_RIIC0_ICSR2_TEND_Msk (0x00000040UL)
|
||||
#define R_RIIC0_ICSR2_TEND_Pos (6UL)
|
||||
#define R_RIIC0_ICSR2_TDRE_Msk (0x00000080UL)
|
||||
#define R_RIIC0_ICSR2_TDRE_Pos (7UL)
|
||||
#define R_RIIC0_ICSAR0_SVA0_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICSAR0_SVA0_Pos (0UL)
|
||||
#define R_RIIC0_ICSAR0_SVA_Msk (0x000003FEUL)
|
||||
#define R_RIIC0_ICSAR0_SVA_Pos (1UL)
|
||||
#define R_RIIC0_ICSAR0_FS0_Msk (0x00008000UL)
|
||||
#define R_RIIC0_ICSAR0_FS0_Pos (15UL)
|
||||
#define R_RIIC0_ICSAR1_SVA0_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICSAR1_SVA0_Pos (0UL)
|
||||
#define R_RIIC0_ICSAR1_SVA_Msk (0x000003FEUL)
|
||||
#define R_RIIC0_ICSAR1_SVA_Pos (1UL)
|
||||
#define R_RIIC0_ICSAR1_FS1_Msk (0x00008000UL)
|
||||
#define R_RIIC0_ICSAR1_FS1_Pos (15UL)
|
||||
#define R_RIIC0_ICSAR2_SVA0_Msk (0x00000001UL)
|
||||
#define R_RIIC0_ICSAR2_SVA0_Pos (0UL)
|
||||
#define R_RIIC0_ICSAR2_SVA_Msk (0x000003FEUL)
|
||||
#define R_RIIC0_ICSAR2_SVA_Pos (1UL)
|
||||
#define R_RIIC0_ICSAR2_FS2_Msk (0x00008000UL)
|
||||
#define R_RIIC0_ICSAR2_FS2_Pos (15UL)
|
||||
#define R_RIIC0_ICBRL_BRL_Msk (0x0000001FUL)
|
||||
#define R_RIIC0_ICBRL_BRL_Pos (0UL)
|
||||
#define R_RIIC0_ICBRH_BRH_Msk (0x0000001FUL)
|
||||
#define R_RIIC0_ICBRH_BRH_Pos (0UL)
|
||||
#define R_RIIC0_ICDRT_DRT_Msk (0x000000FFUL)
|
||||
#define R_RIIC0_ICDRT_DRT_Pos (0UL)
|
||||
#define R_RIIC0_ICDRR_DRR_Msk (0x000000FFUL)
|
||||
#define R_RIIC0_ICDRR_DRR_Pos (0UL)
|
||||
|
||||
#endif /* RIIC_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : rspi_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for rspi.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef RSPI_IOBITMASK_H
|
||||
#define RSPI_IOBITMASK_H
|
||||
|
||||
#define R_RSPI0_SPCR_MODFEN_Msk (0x04UL)
|
||||
#define R_RSPI0_SPCR_MODFEN_Pos (2UL)
|
||||
#define R_RSPI0_SPCR_MSTR_Msk (0x08UL)
|
||||
#define R_RSPI0_SPCR_MSTR_Pos (3UL)
|
||||
#define R_RSPI0_SPCR_SPEIE_Msk (0x10UL)
|
||||
#define R_RSPI0_SPCR_SPEIE_Pos (4UL)
|
||||
#define R_RSPI0_SPCR_SPTIE_Msk (0x20UL)
|
||||
#define R_RSPI0_SPCR_SPTIE_Pos (5UL)
|
||||
#define R_RSPI0_SPCR_SPE_Msk (0x40UL)
|
||||
#define R_RSPI0_SPCR_SPE_Pos (6UL)
|
||||
#define R_RSPI0_SPCR_SPRIE_Msk (0x80UL)
|
||||
#define R_RSPI0_SPCR_SPRIE_Pos (7UL)
|
||||
#define R_RSPI0_SSLP_SSL0P_Msk (0x01UL)
|
||||
#define R_RSPI0_SSLP_SSL0P_Pos (0UL)
|
||||
#define R_RSPI0_SPPCR_SPLP_Msk (0x01UL)
|
||||
#define R_RSPI0_SPPCR_SPLP_Pos (0UL)
|
||||
#define R_RSPI0_SPPCR_MOIFV_Msk (0x10UL)
|
||||
#define R_RSPI0_SPPCR_MOIFV_Pos (4UL)
|
||||
#define R_RSPI0_SPPCR_MOIFE_Msk (0x20UL)
|
||||
#define R_RSPI0_SPPCR_MOIFE_Pos (5UL)
|
||||
#define R_RSPI0_SPSR_OVRF_Msk (0x01UL)
|
||||
#define R_RSPI0_SPSR_OVRF_Pos (0UL)
|
||||
#define R_RSPI0_SPSR_MODF_Msk (0x04UL)
|
||||
#define R_RSPI0_SPSR_MODF_Pos (2UL)
|
||||
#define R_RSPI0_SPSR_SPTEF_Msk (0x20UL)
|
||||
#define R_RSPI0_SPSR_SPTEF_Pos (5UL)
|
||||
#define R_RSPI0_SPSR_TEND_Msk (0x40UL)
|
||||
#define R_RSPI0_SPSR_TEND_Pos (6UL)
|
||||
#define R_RSPI0_SPSR_SPRF_Msk (0x80UL)
|
||||
#define R_RSPI0_SPSR_SPRF_Pos (7UL)
|
||||
#define R_RSPI0_SPDR_SPD_Msk (0xFFFFFFFFUL)
|
||||
#define R_RSPI0_SPDR_SPD_Pos (0UL)
|
||||
#define R_RSPI0_SPSCR_SPSLN_Msk (0x03UL)
|
||||
#define R_RSPI0_SPSCR_SPSLN_Pos (0UL)
|
||||
#define R_RSPI0_SPSSR_SPCP_Msk (0x03UL)
|
||||
#define R_RSPI0_SPSSR_SPCP_Pos (0UL)
|
||||
#define R_RSPI0_SPBR_SPR_Msk (0xFFUL)
|
||||
#define R_RSPI0_SPBR_SPR_Pos (0UL)
|
||||
#define R_RSPI0_SPDCR_SPLW_Msk (0x60UL)
|
||||
#define R_RSPI0_SPDCR_SPLW_Pos (5UL)
|
||||
#define R_RSPI0_SPDCR_TXDMY_Msk (0x80UL)
|
||||
#define R_RSPI0_SPDCR_TXDMY_Pos (7UL)
|
||||
#define R_RSPI0_SPCKD_SCKDL_Msk (0x07UL)
|
||||
#define R_RSPI0_SPCKD_SCKDL_Pos (0UL)
|
||||
#define R_RSPI0_SSLND_SLNDL_Msk (0x07UL)
|
||||
#define R_RSPI0_SSLND_SLNDL_Pos (0UL)
|
||||
#define R_RSPI0_SPND_SPNDL_Msk (0x07UL)
|
||||
#define R_RSPI0_SPND_SPNDL_Pos (0UL)
|
||||
#define R_RSPI0_SPCMD0_CPHA_Msk (0x0001UL)
|
||||
#define R_RSPI0_SPCMD0_CPHA_Pos (0UL)
|
||||
#define R_RSPI0_SPCMD0_CPOL_Msk (0x0002UL)
|
||||
#define R_RSPI0_SPCMD0_CPOL_Pos (1UL)
|
||||
#define R_RSPI0_SPCMD0_BRDV_Msk (0x000CUL)
|
||||
#define R_RSPI0_SPCMD0_BRDV_Pos (2UL)
|
||||
#define R_RSPI0_SPCMD0_SSLKP_Msk (0x0080UL)
|
||||
#define R_RSPI0_SPCMD0_SSLKP_Pos (7UL)
|
||||
#define R_RSPI0_SPCMD0_SPB_Msk (0x0F00UL)
|
||||
#define R_RSPI0_SPCMD0_SPB_Pos (8UL)
|
||||
#define R_RSPI0_SPCMD0_LSBF_Msk (0x1000UL)
|
||||
#define R_RSPI0_SPCMD0_LSBF_Pos (12UL)
|
||||
#define R_RSPI0_SPCMD0_SPNDEN_Msk (0x2000UL)
|
||||
#define R_RSPI0_SPCMD0_SPNDEN_Pos (13UL)
|
||||
#define R_RSPI0_SPCMD0_SLNDEN_Msk (0x4000UL)
|
||||
#define R_RSPI0_SPCMD0_SLNDEN_Pos (14UL)
|
||||
#define R_RSPI0_SPCMD0_SCKDEN_Msk (0x8000UL)
|
||||
#define R_RSPI0_SPCMD0_SCKDEN_Pos (15UL)
|
||||
#define R_RSPI0_SPCMD1_CPHA_Msk (0x0001UL)
|
||||
#define R_RSPI0_SPCMD1_CPHA_Pos (0UL)
|
||||
#define R_RSPI0_SPCMD1_CPOL_Msk (0x0002UL)
|
||||
#define R_RSPI0_SPCMD1_CPOL_Pos (1UL)
|
||||
#define R_RSPI0_SPCMD1_BRDV_Msk (0x000CUL)
|
||||
#define R_RSPI0_SPCMD1_BRDV_Pos (2UL)
|
||||
#define R_RSPI0_SPCMD1_SSLKP_Msk (0x0080UL)
|
||||
#define R_RSPI0_SPCMD1_SSLKP_Pos (7UL)
|
||||
#define R_RSPI0_SPCMD1_SPB_Msk (0x0F00UL)
|
||||
#define R_RSPI0_SPCMD1_SPB_Pos (8UL)
|
||||
#define R_RSPI0_SPCMD1_LSBF_Msk (0x1000UL)
|
||||
#define R_RSPI0_SPCMD1_LSBF_Pos (12UL)
|
||||
#define R_RSPI0_SPCMD1_SPNDEN_Msk (0x2000UL)
|
||||
#define R_RSPI0_SPCMD1_SPNDEN_Pos (13UL)
|
||||
#define R_RSPI0_SPCMD1_SLNDEN_Msk (0x4000UL)
|
||||
#define R_RSPI0_SPCMD1_SLNDEN_Pos (14UL)
|
||||
#define R_RSPI0_SPCMD1_SCKDEN_Msk (0x8000UL)
|
||||
#define R_RSPI0_SPCMD1_SCKDEN_Pos (15UL)
|
||||
#define R_RSPI0_SPCMD2_CPHA_Msk (0x0001UL)
|
||||
#define R_RSPI0_SPCMD2_CPHA_Pos (0UL)
|
||||
#define R_RSPI0_SPCMD2_CPOL_Msk (0x0002UL)
|
||||
#define R_RSPI0_SPCMD2_CPOL_Pos (1UL)
|
||||
#define R_RSPI0_SPCMD2_BRDV_Msk (0x000CUL)
|
||||
#define R_RSPI0_SPCMD2_BRDV_Pos (2UL)
|
||||
#define R_RSPI0_SPCMD2_SSLKP_Msk (0x0080UL)
|
||||
#define R_RSPI0_SPCMD2_SSLKP_Pos (7UL)
|
||||
#define R_RSPI0_SPCMD2_SPB_Msk (0x0F00UL)
|
||||
#define R_RSPI0_SPCMD2_SPB_Pos (8UL)
|
||||
#define R_RSPI0_SPCMD2_LSBF_Msk (0x1000UL)
|
||||
#define R_RSPI0_SPCMD2_LSBF_Pos (12UL)
|
||||
#define R_RSPI0_SPCMD2_SPNDEN_Msk (0x2000UL)
|
||||
#define R_RSPI0_SPCMD2_SPNDEN_Pos (13UL)
|
||||
#define R_RSPI0_SPCMD2_SLNDEN_Msk (0x4000UL)
|
||||
#define R_RSPI0_SPCMD2_SLNDEN_Pos (14UL)
|
||||
#define R_RSPI0_SPCMD2_SCKDEN_Msk (0x8000UL)
|
||||
#define R_RSPI0_SPCMD2_SCKDEN_Pos (15UL)
|
||||
#define R_RSPI0_SPCMD3_CPHA_Msk (0x0001UL)
|
||||
#define R_RSPI0_SPCMD3_CPHA_Pos (0UL)
|
||||
#define R_RSPI0_SPCMD3_CPOL_Msk (0x0002UL)
|
||||
#define R_RSPI0_SPCMD3_CPOL_Pos (1UL)
|
||||
#define R_RSPI0_SPCMD3_BRDV_Msk (0x000CUL)
|
||||
#define R_RSPI0_SPCMD3_BRDV_Pos (2UL)
|
||||
#define R_RSPI0_SPCMD3_SSLKP_Msk (0x0080UL)
|
||||
#define R_RSPI0_SPCMD3_SSLKP_Pos (7UL)
|
||||
#define R_RSPI0_SPCMD3_SPB_Msk (0x0F00UL)
|
||||
#define R_RSPI0_SPCMD3_SPB_Pos (8UL)
|
||||
#define R_RSPI0_SPCMD3_LSBF_Msk (0x1000UL)
|
||||
#define R_RSPI0_SPCMD3_LSBF_Pos (12UL)
|
||||
#define R_RSPI0_SPCMD3_SPNDEN_Msk (0x2000UL)
|
||||
#define R_RSPI0_SPCMD3_SPNDEN_Pos (13UL)
|
||||
#define R_RSPI0_SPCMD3_SLNDEN_Msk (0x4000UL)
|
||||
#define R_RSPI0_SPCMD3_SLNDEN_Pos (14UL)
|
||||
#define R_RSPI0_SPCMD3_SCKDEN_Msk (0x8000UL)
|
||||
#define R_RSPI0_SPCMD3_SCKDEN_Pos (15UL)
|
||||
#define R_RSPI0_SPBFCR_RXTRG_Msk (0x07UL)
|
||||
#define R_RSPI0_SPBFCR_RXTRG_Pos (0UL)
|
||||
#define R_RSPI0_SPBFCR_TXTRG_Msk (0x30UL)
|
||||
#define R_RSPI0_SPBFCR_TXTRG_Pos (4UL)
|
||||
#define R_RSPI0_SPBFCR_RXRST_Msk (0x40UL)
|
||||
#define R_RSPI0_SPBFCR_RXRST_Pos (6UL)
|
||||
#define R_RSPI0_SPBFCR_TXRST_Msk (0x80UL)
|
||||
#define R_RSPI0_SPBFCR_TXRST_Pos (7UL)
|
||||
#define R_RSPI0_SPBFDR_R_Msk (0x003FUL)
|
||||
#define R_RSPI0_SPBFDR_R_Pos (0UL)
|
||||
#define R_RSPI0_SPBFDR_T_Msk (0x0F00UL)
|
||||
#define R_RSPI0_SPBFDR_T_Pos (8UL)
|
||||
|
||||
#endif /* RSPI_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : scifa_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for scifa.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef SCIFA_IOBITMASK_H
|
||||
#define SCIFA_IOBITMASK_H
|
||||
|
||||
#define R_SCIFA0_SMR_CKS_Msk (0x0003UL)
|
||||
#define R_SCIFA0_SMR_CKS_Pos (0UL)
|
||||
#define R_SCIFA0_SMR_STOP_Msk (0x0008UL)
|
||||
#define R_SCIFA0_SMR_STOP_Pos (3UL)
|
||||
#define R_SCIFA0_SMR_PM_Msk (0x0010UL)
|
||||
#define R_SCIFA0_SMR_PM_Pos (4UL)
|
||||
#define R_SCIFA0_SMR_PE_Msk (0x0020UL)
|
||||
#define R_SCIFA0_SMR_PE_Pos (5UL)
|
||||
#define R_SCIFA0_SMR_CHR_Msk (0x0040UL)
|
||||
#define R_SCIFA0_SMR_CHR_Pos (6UL)
|
||||
#define R_SCIFA0_SMR_CM_Msk (0x0080UL)
|
||||
#define R_SCIFA0_SMR_CM_Pos (7UL)
|
||||
#define R_SCIFA0_MDDR_MDDR_Msk (0xFFUL)
|
||||
#define R_SCIFA0_MDDR_MDDR_Pos (0UL)
|
||||
#define R_SCIFA0_BRR_BRR_Msk (0xFFUL)
|
||||
#define R_SCIFA0_BRR_BRR_Pos (0UL)
|
||||
#define R_SCIFA0_SCR_CKE_Msk (0x0003UL)
|
||||
#define R_SCIFA0_SCR_CKE_Pos (0UL)
|
||||
#define R_SCIFA0_SCR_TEIE_Msk (0x0004UL)
|
||||
#define R_SCIFA0_SCR_TEIE_Pos (2UL)
|
||||
#define R_SCIFA0_SCR_REIE_Msk (0x0008UL)
|
||||
#define R_SCIFA0_SCR_REIE_Pos (3UL)
|
||||
#define R_SCIFA0_SCR_RE_Msk (0x0010UL)
|
||||
#define R_SCIFA0_SCR_RE_Pos (4UL)
|
||||
#define R_SCIFA0_SCR_TE_Msk (0x0020UL)
|
||||
#define R_SCIFA0_SCR_TE_Pos (5UL)
|
||||
#define R_SCIFA0_SCR_RIE_Msk (0x0040UL)
|
||||
#define R_SCIFA0_SCR_RIE_Pos (6UL)
|
||||
#define R_SCIFA0_SCR_TIE_Msk (0x0080UL)
|
||||
#define R_SCIFA0_SCR_TIE_Pos (7UL)
|
||||
#define R_SCIFA0_FTDR_FTDR_Msk (0xFFUL)
|
||||
#define R_SCIFA0_FTDR_FTDR_Pos (0UL)
|
||||
#define R_SCIFA0_FSR_DR_Msk (0x0001UL)
|
||||
#define R_SCIFA0_FSR_DR_Pos (0UL)
|
||||
#define R_SCIFA0_FSR_RDF_Msk (0x0002UL)
|
||||
#define R_SCIFA0_FSR_RDF_Pos (1UL)
|
||||
#define R_SCIFA0_FSR_PER_Msk (0x0004UL)
|
||||
#define R_SCIFA0_FSR_PER_Pos (2UL)
|
||||
#define R_SCIFA0_FSR_FER_Msk (0x0008UL)
|
||||
#define R_SCIFA0_FSR_FER_Pos (3UL)
|
||||
#define R_SCIFA0_FSR_BRK_Msk (0x0010UL)
|
||||
#define R_SCIFA0_FSR_BRK_Pos (4UL)
|
||||
#define R_SCIFA0_FSR_TDFE_Msk (0x0020UL)
|
||||
#define R_SCIFA0_FSR_TDFE_Pos (5UL)
|
||||
#define R_SCIFA0_FSR_TEND_Msk (0x0040UL)
|
||||
#define R_SCIFA0_FSR_TEND_Pos (6UL)
|
||||
#define R_SCIFA0_FSR_ER_Msk (0x0080UL)
|
||||
#define R_SCIFA0_FSR_ER_Pos (7UL)
|
||||
#define R_SCIFA0_FRDR_FRDR_Msk (0xFFUL)
|
||||
#define R_SCIFA0_FRDR_FRDR_Pos (0UL)
|
||||
#define R_SCIFA0_FCR_LOOP_Msk (0x0001UL)
|
||||
#define R_SCIFA0_FCR_LOOP_Pos (0UL)
|
||||
#define R_SCIFA0_FCR_RFRST_Msk (0x0002UL)
|
||||
#define R_SCIFA0_FCR_RFRST_Pos (1UL)
|
||||
#define R_SCIFA0_FCR_TFRST_Msk (0x0004UL)
|
||||
#define R_SCIFA0_FCR_TFRST_Pos (2UL)
|
||||
#define R_SCIFA0_FCR_MCE_Msk (0x0008UL)
|
||||
#define R_SCIFA0_FCR_MCE_Pos (3UL)
|
||||
#define R_SCIFA0_FCR_TTRG_Msk (0x0030UL)
|
||||
#define R_SCIFA0_FCR_TTRG_Pos (4UL)
|
||||
#define R_SCIFA0_FCR_RTRG_Msk (0x00C0UL)
|
||||
#define R_SCIFA0_FCR_RTRG_Pos (6UL)
|
||||
#define R_SCIFA0_FCR_RSTRG_Msk (0x0700UL)
|
||||
#define R_SCIFA0_FCR_RSTRG_Pos (8UL)
|
||||
#define R_SCIFA0_FDR_R_Msk (0x001FUL)
|
||||
#define R_SCIFA0_FDR_R_Pos (0UL)
|
||||
#define R_SCIFA0_FDR_T_Msk (0x1F00UL)
|
||||
#define R_SCIFA0_FDR_T_Pos (8UL)
|
||||
#define R_SCIFA0_SPTR_SPB2DT_Msk (0x0001UL)
|
||||
#define R_SCIFA0_SPTR_SPB2DT_Pos (0UL)
|
||||
#define R_SCIFA0_SPTR_SPB2IO_Msk (0x0002UL)
|
||||
#define R_SCIFA0_SPTR_SPB2IO_Pos (1UL)
|
||||
#define R_SCIFA0_SPTR_SCKDT_Msk (0x0004UL)
|
||||
#define R_SCIFA0_SPTR_SCKDT_Pos (2UL)
|
||||
#define R_SCIFA0_SPTR_SCKIO_Msk (0x0008UL)
|
||||
#define R_SCIFA0_SPTR_SCKIO_Pos (3UL)
|
||||
#define R_SCIFA0_SPTR_CTS2DT_Msk (0x0010UL)
|
||||
#define R_SCIFA0_SPTR_CTS2DT_Pos (4UL)
|
||||
#define R_SCIFA0_SPTR_CTS2IO_Msk (0x0020UL)
|
||||
#define R_SCIFA0_SPTR_CTS2IO_Pos (5UL)
|
||||
#define R_SCIFA0_SPTR_RTS2DT_Msk (0x0040UL)
|
||||
#define R_SCIFA0_SPTR_RTS2DT_Pos (6UL)
|
||||
#define R_SCIFA0_SPTR_RTS2IO_Msk (0x0080UL)
|
||||
#define R_SCIFA0_SPTR_RTS2IO_Pos (7UL)
|
||||
#define R_SCIFA0_LSR_ORER_Msk (0x0001UL)
|
||||
#define R_SCIFA0_LSR_ORER_Pos (0UL)
|
||||
#define R_SCIFA0_LSR_FER_Msk (0x003CUL)
|
||||
#define R_SCIFA0_LSR_FER_Pos (2UL)
|
||||
#define R_SCIFA0_LSR_PER_Msk (0x0F00UL)
|
||||
#define R_SCIFA0_LSR_PER_Pos (8UL)
|
||||
#define R_SCIFA0_SEMR_ABCS0_Msk (0x01UL)
|
||||
#define R_SCIFA0_SEMR_ABCS0_Pos (0UL)
|
||||
#define R_SCIFA0_SEMR_NFEN_Msk (0x04UL)
|
||||
#define R_SCIFA0_SEMR_NFEN_Pos (2UL)
|
||||
#define R_SCIFA0_SEMR_DIR_Msk (0x08UL)
|
||||
#define R_SCIFA0_SEMR_DIR_Pos (3UL)
|
||||
#define R_SCIFA0_SEMR_MDDRS_Msk (0x10UL)
|
||||
#define R_SCIFA0_SEMR_MDDRS_Pos (4UL)
|
||||
#define R_SCIFA0_SEMR_BRME_Msk (0x20UL)
|
||||
#define R_SCIFA0_SEMR_BRME_Pos (5UL)
|
||||
#define R_SCIFA0_SEMR_BGDM_Msk (0x80UL)
|
||||
#define R_SCIFA0_SEMR_BGDM_Pos (7UL)
|
||||
#define R_SCIFA0_FTCR_TFTC_Msk (0x001FUL)
|
||||
#define R_SCIFA0_FTCR_TFTC_Pos (0UL)
|
||||
#define R_SCIFA0_FTCR_TTRGS_Msk (0x0080UL)
|
||||
#define R_SCIFA0_FTCR_TTRGS_Pos (7UL)
|
||||
#define R_SCIFA0_FTCR_RFTC_Msk (0x1F00UL)
|
||||
#define R_SCIFA0_FTCR_RFTC_Pos (8UL)
|
||||
#define R_SCIFA0_FTCR_RTRGS_Msk (0x8000UL)
|
||||
#define R_SCIFA0_FTCR_RTRGS_Pos (15UL)
|
||||
|
||||
#endif /* SCIFA_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : spibsc_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for spibsc.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef SPIBSC_IOBITMASK_H
|
||||
#define SPIBSC_IOBITMASK_H
|
||||
|
||||
#define R_SPIBSC_CMNCR_BSZ_Msk (0x00000003UL)
|
||||
#define R_SPIBSC_CMNCR_BSZ_Pos (0UL)
|
||||
#define R_SPIBSC_CMNCR_IO0FV_Msk (0x00000300UL)
|
||||
#define R_SPIBSC_CMNCR_IO0FV_Pos (8UL)
|
||||
#define R_SPIBSC_CMNCR_IO2FV_Msk (0x00003000UL)
|
||||
#define R_SPIBSC_CMNCR_IO2FV_Pos (12UL)
|
||||
#define R_SPIBSC_CMNCR_IO3FV_Msk (0x0000C000UL)
|
||||
#define R_SPIBSC_CMNCR_IO3FV_Pos (14UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO0_Msk (0x00030000UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO0_Pos (16UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO1_Msk (0x000C0000UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO1_Pos (18UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO2_Msk (0x00300000UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO2_Pos (20UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO3_Msk (0x00C00000UL)
|
||||
#define R_SPIBSC_CMNCR_MOIIO3_Pos (22UL)
|
||||
#define R_SPIBSC_CMNCR_MD_Msk (0x80000000UL)
|
||||
#define R_SPIBSC_CMNCR_MD_Pos (31UL)
|
||||
#define R_SPIBSC_SSLDR_SCKDL_Msk (0x00000007UL)
|
||||
#define R_SPIBSC_SSLDR_SCKDL_Pos (0UL)
|
||||
#define R_SPIBSC_SSLDR_SLNDL_Msk (0x00000700UL)
|
||||
#define R_SPIBSC_SSLDR_SLNDL_Pos (8UL)
|
||||
#define R_SPIBSC_SSLDR_SPNDL_Msk (0x00070000UL)
|
||||
#define R_SPIBSC_SSLDR_SPNDL_Pos (16UL)
|
||||
#define R_SPIBSC_DRCR_SSLE_Msk (0x00000001UL)
|
||||
#define R_SPIBSC_DRCR_SSLE_Pos (0UL)
|
||||
#define R_SPIBSC_DRCR_RBE_Msk (0x00000100UL)
|
||||
#define R_SPIBSC_DRCR_RBE_Pos (8UL)
|
||||
#define R_SPIBSC_DRCR_RCF_Msk (0x00000200UL)
|
||||
#define R_SPIBSC_DRCR_RCF_Pos (9UL)
|
||||
#define R_SPIBSC_DRCR_RBURST_Msk (0x001F0000UL)
|
||||
#define R_SPIBSC_DRCR_RBURST_Pos (16UL)
|
||||
#define R_SPIBSC_DRCR_SSLN_Msk (0x01000000UL)
|
||||
#define R_SPIBSC_DRCR_SSLN_Pos (24UL)
|
||||
#define R_SPIBSC_DRCMR_OCMD_Msk (0x000000FFUL)
|
||||
#define R_SPIBSC_DRCMR_OCMD_Pos (0UL)
|
||||
#define R_SPIBSC_DRCMR_CMD_Msk (0x00FF0000UL)
|
||||
#define R_SPIBSC_DRCMR_CMD_Pos (16UL)
|
||||
#define R_SPIBSC_DREAR_EAC_Msk (0x00000007UL)
|
||||
#define R_SPIBSC_DREAR_EAC_Pos (0UL)
|
||||
#define R_SPIBSC_DREAR_EAV_Msk (0x00FF0000UL)
|
||||
#define R_SPIBSC_DREAR_EAV_Pos (16UL)
|
||||
#define R_SPIBSC_DROPR_OPD0_Msk (0x000000FFUL)
|
||||
#define R_SPIBSC_DROPR_OPD0_Pos (0UL)
|
||||
#define R_SPIBSC_DROPR_OPD1_Msk (0x0000FF00UL)
|
||||
#define R_SPIBSC_DROPR_OPD1_Pos (8UL)
|
||||
#define R_SPIBSC_DROPR_OPD2_Msk (0x00FF0000UL)
|
||||
#define R_SPIBSC_DROPR_OPD2_Pos (16UL)
|
||||
#define R_SPIBSC_DROPR_OPD3_Msk (0xFF000000UL)
|
||||
#define R_SPIBSC_DROPR_OPD3_Pos (24UL)
|
||||
#define R_SPIBSC_DRENR_OPDE_Msk (0x000000F0UL)
|
||||
#define R_SPIBSC_DRENR_OPDE_Pos (4UL)
|
||||
#define R_SPIBSC_DRENR_ADE_Msk (0x00000F00UL)
|
||||
#define R_SPIBSC_DRENR_ADE_Pos (8UL)
|
||||
#define R_SPIBSC_DRENR_OCDE_Msk (0x00001000UL)
|
||||
#define R_SPIBSC_DRENR_OCDE_Pos (12UL)
|
||||
#define R_SPIBSC_DRENR_CDE_Msk (0x00004000UL)
|
||||
#define R_SPIBSC_DRENR_CDE_Pos (14UL)
|
||||
#define R_SPIBSC_DRENR_DME_Msk (0x00008000UL)
|
||||
#define R_SPIBSC_DRENR_DME_Pos (15UL)
|
||||
#define R_SPIBSC_DRENR_DRDB_Msk (0x00030000UL)
|
||||
#define R_SPIBSC_DRENR_DRDB_Pos (16UL)
|
||||
#define R_SPIBSC_DRENR_OPDB_Msk (0x00300000UL)
|
||||
#define R_SPIBSC_DRENR_OPDB_Pos (20UL)
|
||||
#define R_SPIBSC_DRENR_ADB_Msk (0x03000000UL)
|
||||
#define R_SPIBSC_DRENR_ADB_Pos (24UL)
|
||||
#define R_SPIBSC_DRENR_OCDB_Msk (0x30000000UL)
|
||||
#define R_SPIBSC_DRENR_OCDB_Pos (28UL)
|
||||
#define R_SPIBSC_DRENR_CDB_Msk (0xC0000000UL)
|
||||
#define R_SPIBSC_DRENR_CDB_Pos (30UL)
|
||||
#define R_SPIBSC_SMCR_SPIE_Msk (0x00000001UL)
|
||||
#define R_SPIBSC_SMCR_SPIE_Pos (0UL)
|
||||
#define R_SPIBSC_SMCR_SPIWE_Msk (0x00000002UL)
|
||||
#define R_SPIBSC_SMCR_SPIWE_Pos (1UL)
|
||||
#define R_SPIBSC_SMCR_SPIRE_Msk (0x00000004UL)
|
||||
#define R_SPIBSC_SMCR_SPIRE_Pos (2UL)
|
||||
#define R_SPIBSC_SMCR_SSLKP_Msk (0x00000100UL)
|
||||
#define R_SPIBSC_SMCR_SSLKP_Pos (8UL)
|
||||
#define R_SPIBSC_SMCMR_OCMD_Msk (0x000000FFUL)
|
||||
#define R_SPIBSC_SMCMR_OCMD_Pos (0UL)
|
||||
#define R_SPIBSC_SMCMR_CMD_Msk (0x00FF0000UL)
|
||||
#define R_SPIBSC_SMCMR_CMD_Pos (16UL)
|
||||
#define R_SPIBSC_SMADR_ADR_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_SMADR_ADR_Pos (0UL)
|
||||
#define R_SPIBSC_SMOPR_OPD0_Msk (0x000000FFUL)
|
||||
#define R_SPIBSC_SMOPR_OPD0_Pos (0UL)
|
||||
#define R_SPIBSC_SMOPR_OPD1_Msk (0x0000FF00UL)
|
||||
#define R_SPIBSC_SMOPR_OPD1_Pos (8UL)
|
||||
#define R_SPIBSC_SMOPR_OPD2_Msk (0x00FF0000UL)
|
||||
#define R_SPIBSC_SMOPR_OPD2_Pos (16UL)
|
||||
#define R_SPIBSC_SMOPR_OPD3_Msk (0xFF000000UL)
|
||||
#define R_SPIBSC_SMOPR_OPD3_Pos (24UL)
|
||||
#define R_SPIBSC_SMENR_SPIDE_Msk (0x0000000FUL)
|
||||
#define R_SPIBSC_SMENR_SPIDE_Pos (0UL)
|
||||
#define R_SPIBSC_SMENR_OPDE_Msk (0x000000F0UL)
|
||||
#define R_SPIBSC_SMENR_OPDE_Pos (4UL)
|
||||
#define R_SPIBSC_SMENR_ADE_Msk (0x00000F00UL)
|
||||
#define R_SPIBSC_SMENR_ADE_Pos (8UL)
|
||||
#define R_SPIBSC_SMENR_OCDE_Msk (0x00001000UL)
|
||||
#define R_SPIBSC_SMENR_OCDE_Pos (12UL)
|
||||
#define R_SPIBSC_SMENR_CDE_Msk (0x00004000UL)
|
||||
#define R_SPIBSC_SMENR_CDE_Pos (14UL)
|
||||
#define R_SPIBSC_SMENR_DME_Msk (0x00008000UL)
|
||||
#define R_SPIBSC_SMENR_DME_Pos (15UL)
|
||||
#define R_SPIBSC_SMENR_SPIDB_Msk (0x00030000UL)
|
||||
#define R_SPIBSC_SMENR_SPIDB_Pos (16UL)
|
||||
#define R_SPIBSC_SMENR_OPDB_Msk (0x00300000UL)
|
||||
#define R_SPIBSC_SMENR_OPDB_Pos (20UL)
|
||||
#define R_SPIBSC_SMENR_ADB_Msk (0x03000000UL)
|
||||
#define R_SPIBSC_SMENR_ADB_Pos (24UL)
|
||||
#define R_SPIBSC_SMENR_OCDB_Msk (0x30000000UL)
|
||||
#define R_SPIBSC_SMENR_OCDB_Pos (28UL)
|
||||
#define R_SPIBSC_SMENR_CDB_Msk (0xC0000000UL)
|
||||
#define R_SPIBSC_SMENR_CDB_Pos (30UL)
|
||||
#define R_SPIBSC_SMRDR0_RDATA0_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_SMRDR0_RDATA0_Pos (0UL)
|
||||
#define R_SPIBSC_SMRDR1_RDATA1_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_SMRDR1_RDATA1_Pos (0UL)
|
||||
#define R_SPIBSC_SMWDR0_WDATA0_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_SMWDR0_WDATA0_Pos (0UL)
|
||||
#define R_SPIBSC_SMWDR1_WDATA1_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_SMWDR1_WDATA1_Pos (0UL)
|
||||
#define R_SPIBSC_CMNSR_TEND_Msk (0x00000001UL)
|
||||
#define R_SPIBSC_CMNSR_TEND_Pos (0UL)
|
||||
#define R_SPIBSC_CMNSR_SSLF_Msk (0x00000002UL)
|
||||
#define R_SPIBSC_CMNSR_SSLF_Pos (1UL)
|
||||
#define R_SPIBSC_DRDMCR_DMCYC_Msk (0x0000001FUL)
|
||||
#define R_SPIBSC_DRDMCR_DMCYC_Pos (0UL)
|
||||
#define R_SPIBSC_DRDRENR_DRDRE_Msk (0x00000001UL)
|
||||
#define R_SPIBSC_DRDRENR_DRDRE_Pos (0UL)
|
||||
#define R_SPIBSC_DRDRENR_OPDRE_Msk (0x00000010UL)
|
||||
#define R_SPIBSC_DRDRENR_OPDRE_Pos (4UL)
|
||||
#define R_SPIBSC_DRDRENR_ADDRE_Msk (0x00000100UL)
|
||||
#define R_SPIBSC_DRDRENR_ADDRE_Pos (8UL)
|
||||
#define R_SPIBSC_DRDRENR_HYPE_Msk (0x00007000UL)
|
||||
#define R_SPIBSC_DRDRENR_HYPE_Pos (12UL)
|
||||
#define R_SPIBSC_SMDMCR_DMCYC_Msk (0x0000001FUL)
|
||||
#define R_SPIBSC_SMDMCR_DMCYC_Pos (0UL)
|
||||
#define R_SPIBSC_SMDRENR_SPIDRE_Msk (0x00000001UL)
|
||||
#define R_SPIBSC_SMDRENR_SPIDRE_Pos (0UL)
|
||||
#define R_SPIBSC_SMDRENR_OPDRE_Msk (0x00000010UL)
|
||||
#define R_SPIBSC_SMDRENR_OPDRE_Pos (4UL)
|
||||
#define R_SPIBSC_SMDRENR_ADDRE_Msk (0x00000100UL)
|
||||
#define R_SPIBSC_SMDRENR_ADDRE_Pos (8UL)
|
||||
#define R_SPIBSC_SMDRENR_HYPE_Msk (0x00007000UL)
|
||||
#define R_SPIBSC_SMDRENR_HYPE_Pos (12UL)
|
||||
#define R_SPIBSC_PHYADJ1_ADJ1_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_PHYADJ1_ADJ1_Pos (0UL)
|
||||
#define R_SPIBSC_PHYADJ2_ADJ2_Msk (0xFFFFFFFFUL)
|
||||
#define R_SPIBSC_PHYADJ2_ADJ2_Pos (0UL)
|
||||
#define R_SPIBSC_PHYCNT_PHYMEM_Msk (0x00000003UL)
|
||||
#define R_SPIBSC_PHYCNT_PHYMEM_Pos (0UL)
|
||||
#define R_SPIBSC_PHYCNT_WBUF_Msk (0x00000004UL)
|
||||
#define R_SPIBSC_PHYCNT_WBUF_Pos (2UL)
|
||||
#define R_SPIBSC_PHYCNT_WBUF2_Msk (0x00000010UL)
|
||||
#define R_SPIBSC_PHYCNT_WBUF2_Pos (4UL)
|
||||
#define R_SPIBSC_PHYCNT_CKSEL_Msk (0x00030000UL)
|
||||
#define R_SPIBSC_PHYCNT_CKSEL_Pos (16UL)
|
||||
#define R_SPIBSC_PHYCNT_HS_Msk (0x00040000UL)
|
||||
#define R_SPIBSC_PHYCNT_HS_Pos (18UL)
|
||||
#define R_SPIBSC_PHYCNT_OCT_Msk (0x00100000UL)
|
||||
#define R_SPIBSC_PHYCNT_OCT_Pos (20UL)
|
||||
#define R_SPIBSC_PHYCNT_EXDS_Msk (0x00200000UL)
|
||||
#define R_SPIBSC_PHYCNT_EXDS_Pos (21UL)
|
||||
#define R_SPIBSC_PHYCNT_OCTA_Msk (0x00C00000UL)
|
||||
#define R_SPIBSC_PHYCNT_OCTA_Pos (22UL)
|
||||
#define R_SPIBSC_PHYCNT_ALT_ALIGN_Msk (0x40000000UL)
|
||||
#define R_SPIBSC_PHYCNT_ALT_ALIGN_Pos (30UL)
|
||||
#define R_SPIBSC_PHYCNT_CAL_Msk (0x80000000UL)
|
||||
#define R_SPIBSC_PHYCNT_CAL_Pos (31UL)
|
||||
#define R_SPIBSC_PHYOFFSET1_DDRTMG_Msk (0x30000000UL)
|
||||
#define R_SPIBSC_PHYOFFSET1_DDRTMG_Pos (28UL)
|
||||
#define R_SPIBSC_PHYOFFSET2_OCTTMG_Msk (0x00000700UL)
|
||||
#define R_SPIBSC_PHYOFFSET2_OCTTMG_Pos (8UL)
|
||||
#define R_SPIBSC_PHYINT_INT_Msk (0x00000001UL)
|
||||
#define R_SPIBSC_PHYINT_INT_Pos (0UL)
|
||||
#define R_SPIBSC_PHYINT_WPVAL_Msk (0x00000002UL)
|
||||
#define R_SPIBSC_PHYINT_WPVAL_Pos (1UL)
|
||||
#define R_SPIBSC_PHYINT_RSTVAL_Msk (0x00000004UL)
|
||||
#define R_SPIBSC_PHYINT_RSTVAL_Pos (2UL)
|
||||
#define R_SPIBSC_PHYINT_INTEN_Msk (0x01000000UL)
|
||||
#define R_SPIBSC_PHYINT_INTEN_Pos (24UL)
|
||||
#define R_SPIBSC_PHYINT_WPEN_Msk (0x02000000UL)
|
||||
#define R_SPIBSC_PHYINT_WPEN_Pos (25UL)
|
||||
#define R_SPIBSC_PHYINT_RSTEN_Msk (0x04000000UL)
|
||||
#define R_SPIBSC_PHYINT_RSTEN_Pos (26UL)
|
||||
|
||||
#endif /* SPIBSC_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : ssi_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for ssi.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef SSI_IOBITMASK_H
|
||||
#define SSI_IOBITMASK_H
|
||||
|
||||
#define R_SSI_SSICR_REN_Msk (0x00000001UL)
|
||||
#define R_SSI_SSICR_REN_Pos (0UL)
|
||||
#define R_SSI_SSICR_TEN_Msk (0x00000002UL)
|
||||
#define R_SSI_SSICR_TEN_Pos (1UL)
|
||||
#define R_SSI_SSICR_MUEN_Msk (0x00000008UL)
|
||||
#define R_SSI_SSICR_MUEN_Pos (3UL)
|
||||
#define R_SSI_SSICR_CKDV_Msk (0x000000F0UL)
|
||||
#define R_SSI_SSICR_CKDV_Pos (4UL)
|
||||
#define R_SSI_SSICR_DEL_Msk (0x00000100UL)
|
||||
#define R_SSI_SSICR_DEL_Pos (8UL)
|
||||
#define R_SSI_SSICR_PDTA_Msk (0x00000200UL)
|
||||
#define R_SSI_SSICR_PDTA_Pos (9UL)
|
||||
#define R_SSI_SSICR_SDTA_Msk (0x00000400UL)
|
||||
#define R_SSI_SSICR_SDTA_Pos (10UL)
|
||||
#define R_SSI_SSICR_SPDP_Msk (0x00000800UL)
|
||||
#define R_SSI_SSICR_SPDP_Pos (11UL)
|
||||
#define R_SSI_SSICR_LRCKP_Msk (0x00001000UL)
|
||||
#define R_SSI_SSICR_LRCKP_Pos (12UL)
|
||||
#define R_SSI_SSICR_BCKP_Msk (0x00002000UL)
|
||||
#define R_SSI_SSICR_BCKP_Pos (13UL)
|
||||
#define R_SSI_SSICR_MST_Msk (0x00004000UL)
|
||||
#define R_SSI_SSICR_MST_Pos (14UL)
|
||||
#define R_SSI_SSICR_SWL_Msk (0x00070000UL)
|
||||
#define R_SSI_SSICR_SWL_Pos (16UL)
|
||||
#define R_SSI_SSICR_DWL_Msk (0x00380000UL)
|
||||
#define R_SSI_SSICR_DWL_Pos (19UL)
|
||||
#define R_SSI_SSICR_FRM_Msk (0x00C00000UL)
|
||||
#define R_SSI_SSICR_FRM_Pos (22UL)
|
||||
#define R_SSI_SSICR_IIEN_Msk (0x02000000UL)
|
||||
#define R_SSI_SSICR_IIEN_Pos (25UL)
|
||||
#define R_SSI_SSICR_ROIEN_Msk (0x04000000UL)
|
||||
#define R_SSI_SSICR_ROIEN_Pos (26UL)
|
||||
#define R_SSI_SSICR_RUIEN_Msk (0x08000000UL)
|
||||
#define R_SSI_SSICR_RUIEN_Pos (27UL)
|
||||
#define R_SSI_SSICR_TOIEN_Msk (0x10000000UL)
|
||||
#define R_SSI_SSICR_TOIEN_Pos (28UL)
|
||||
#define R_SSI_SSICR_TUIEN_Msk (0x20000000UL)
|
||||
#define R_SSI_SSICR_TUIEN_Pos (29UL)
|
||||
#define R_SSI_SSICR_CKS_Msk (0x40000000UL)
|
||||
#define R_SSI_SSICR_CKS_Pos (30UL)
|
||||
#define R_SSI_SSISR_IIRQ_Msk (0x02000000UL)
|
||||
#define R_SSI_SSISR_IIRQ_Pos (25UL)
|
||||
#define R_SSI_SSISR_ROIRQ_Msk (0x04000000UL)
|
||||
#define R_SSI_SSISR_ROIRQ_Pos (26UL)
|
||||
#define R_SSI_SSISR_RUIRQ_Msk (0x08000000UL)
|
||||
#define R_SSI_SSISR_RUIRQ_Pos (27UL)
|
||||
#define R_SSI_SSISR_TOIRQ_Msk (0x10000000UL)
|
||||
#define R_SSI_SSISR_TOIRQ_Pos (28UL)
|
||||
#define R_SSI_SSISR_TUIRQ_Msk (0x20000000UL)
|
||||
#define R_SSI_SSISR_TUIRQ_Pos (29UL)
|
||||
#define R_SSI_SSIFCR_RFRST_Msk (0x00000001UL)
|
||||
#define R_SSI_SSIFCR_RFRST_Pos (0UL)
|
||||
#define R_SSI_SSIFCR_TFRST_Msk (0x00000002UL)
|
||||
#define R_SSI_SSIFCR_TFRST_Pos (1UL)
|
||||
#define R_SSI_SSIFCR_RIE_Msk (0x00000004UL)
|
||||
#define R_SSI_SSIFCR_RIE_Pos (2UL)
|
||||
#define R_SSI_SSIFCR_TIE_Msk (0x00000008UL)
|
||||
#define R_SSI_SSIFCR_TIE_Pos (3UL)
|
||||
#define R_SSI_SSIFCR_RXDNCE_Msk (0x00000100UL)
|
||||
#define R_SSI_SSIFCR_RXDNCE_Pos (8UL)
|
||||
#define R_SSI_SSIFCR_LRCKNCE_Msk (0x00000200UL)
|
||||
#define R_SSI_SSIFCR_LRCKNCE_Pos (9UL)
|
||||
#define R_SSI_SSIFCR_BCKNCE_Msk (0x00000400UL)
|
||||
#define R_SSI_SSIFCR_BCKNCE_Pos (10UL)
|
||||
#define R_SSI_SSIFCR_BSW_Msk (0x00000800UL)
|
||||
#define R_SSI_SSIFCR_BSW_Pos (11UL)
|
||||
#define R_SSI_SSIFCR_SSIRST_Msk (0x00010000UL)
|
||||
#define R_SSI_SSIFCR_SSIRST_Pos (16UL)
|
||||
#define R_SSI_SSIFCR_AUCKE_Msk (0x80000000UL)
|
||||
#define R_SSI_SSIFCR_AUCKE_Pos (31UL)
|
||||
#define R_SSI_SSIFSR_RDF_Msk (0x00000001UL)
|
||||
#define R_SSI_SSIFSR_RDF_Pos (0UL)
|
||||
#define R_SSI_SSIFSR_RDC_Msk (0x00003F00UL)
|
||||
#define R_SSI_SSIFSR_RDC_Pos (8UL)
|
||||
#define R_SSI_SSIFSR_TDE_Msk (0x00010000UL)
|
||||
#define R_SSI_SSIFSR_TDE_Pos (16UL)
|
||||
#define R_SSI_SSIFSR_TDC_Msk (0x3F000000UL)
|
||||
#define R_SSI_SSIFSR_TDC_Pos (24UL)
|
||||
#define R_SSI_SSIFTDR_SSIFTDR_Msk (0xFFFFFFFFUL)
|
||||
#define R_SSI_SSIFTDR_SSIFTDR_Pos (0UL)
|
||||
#define R_SSI_SSIFRDR_SSIFRDR_Msk (0xFFFFFFFFUL)
|
||||
#define R_SSI_SSIFRDR_SSIFRDR_Pos (0UL)
|
||||
#define R_SSI_SSIOFR_OMOD_Msk (0x00000003UL)
|
||||
#define R_SSI_SSIOFR_OMOD_Pos (0UL)
|
||||
#define R_SSI_SSIOFR_LRCONT_Msk (0x00000100UL)
|
||||
#define R_SSI_SSIOFR_LRCONT_Pos (8UL)
|
||||
#define R_SSI_SSIOFR_BCKSTP_Msk (0x00000200UL)
|
||||
#define R_SSI_SSIOFR_BCKSTP_Pos (9UL)
|
||||
#define R_SSI_SSISCR_RDFS_Msk (0x0000001FUL)
|
||||
#define R_SSI_SSISCR_RDFS_Pos (0UL)
|
||||
#define R_SSI_SSISCR_TDES_Msk (0x00001F00UL)
|
||||
#define R_SSI_SSISCR_TDES_Pos (8UL)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,405 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : sysc_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for sysc.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef SYSC_IOBITMASK_H
|
||||
#define SYSC_IOBITMASK_H
|
||||
|
||||
#define R_SYSC_SYS_RAM0_ECC_VECCEN_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_RAM0_ECC_VECCEN_Pos (0UL)
|
||||
#define R_SYSC_SYS_RAM0_EN_VCEN_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_RAM0_EN_VCEN_Pos (0UL)
|
||||
#define R_SYSC_SYS_RAM0_EN_VLWEN_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_RAM0_EN_VLWEN_Pos (1UL)
|
||||
#define R_SYSC_SYS_RAM1_ECC_VECCEN_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_RAM1_ECC_VECCEN_Pos (0UL)
|
||||
#define R_SYSC_SYS_RAM1_EN_VCEN_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_RAM1_EN_VCEN_Pos (0UL)
|
||||
#define R_SYSC_SYS_RAM1_EN_VLWEN_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_RAM1_EN_VLWEN_Pos (1UL)
|
||||
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Pos (0UL)
|
||||
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Pos (16UL)
|
||||
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Pos (0UL)
|
||||
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Pos (16UL)
|
||||
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Pos (0UL)
|
||||
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Pos (16UL)
|
||||
#define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Pos (24UL)
|
||||
#define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Pos (24UL)
|
||||
#define R_SYSC_SYS_I2C0_CFG_af_bypass_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_I2C0_CFG_af_bypass_Pos (0UL)
|
||||
#define R_SYSC_SYS_I2C1_CFG_af_bypass_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_I2C1_CFG_af_bypass_Pos (0UL)
|
||||
#define R_SYSC_SYS_I2C2_CFG_af_bypass_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_I2C2_CFG_af_bypass_Pos (0UL)
|
||||
#define R_SYSC_SYS_I2C3_CFG_af_bypass_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_I2C3_CFG_af_bypass_Pos (0UL)
|
||||
#define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Msk (0x03FFFFFFUL)
|
||||
#define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Pos (0UL)
|
||||
#define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Msk (0x03FFFFFFUL)
|
||||
#define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Pos (0UL)
|
||||
#define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Msk (0xFFFFFF80UL)
|
||||
#define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Pos (7UL)
|
||||
#define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Msk (0xFFFFFF80UL)
|
||||
#define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Pos (7UL)
|
||||
#define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Pos (0UL)
|
||||
#define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Pos (1UL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Msk (0xFFFFFFFCUL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Pos (2UL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Msk (0x000000FFUL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Pos (0UL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAL1_RVBARADDRL1_Msk (0xFFFFFFFCUL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAL1_RVBARADDRL1_Pos (2UL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAH1_RVBARADDRH1_Msk (0x000000FFUL)
|
||||
#define R_SYSC_SYS_CA55_CFG_RVAH1_RVBARADDRH1_Pos (0UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Msk (0x00000007UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Pos (0UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Pos (9UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Msk (0x00001000UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Pos (12UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_MD_OSCDRV_Msk (0x0000C000UL)
|
||||
#define R_SYSC_SYS_LSI_MODE_STAT_MD_OSCDRV_Pos (14UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Msk (0x000F0000UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Pos (16UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Msk (0x00F00000UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Pos (20UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Msk (0x0F000000UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Pos (24UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Msk (0xF0000000UL)
|
||||
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Pos (28UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Msk (0x000F0000UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Pos (16UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Msk (0x00F00000UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Pos (20UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Msk (0x0F000000UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Pos (24UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Msk (0xF0000000UL)
|
||||
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Pos (28UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Msk (0x000F0000UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Pos (16UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Msk (0x00F00000UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Pos (20UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Msk (0x0F000000UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Pos (24UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Msk (0xF0000000UL)
|
||||
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Pos (28UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS00_SXLCDC_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF4_OFS00_SXLCDC_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS01_SXLCDC_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS01_SXLCDC_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS10_SXLCDC_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS10_SXLCDC_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS11_SXLCDC_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS11_SXLCDC_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS00_SXDSIL_Msk (0x000F0000UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS00_SXDSIL_Pos (16UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS01_SXDSIL_Msk (0x00F00000UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS01_SXDSIL_Pos (20UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS10_SXDSIL_Msk (0x0F000000UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS10_SXDSIL_Pos (24UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS11_SXDSIL_Msk (0xF0000000UL)
|
||||
#define R_SYSC_SYS_AOF4_OFS11_SXDSIL_Pos (28UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS00_SXH264_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF5_OFS00_SXH264_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS01_SXH264_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS01_SXH264_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS10_SXH264_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS10_SXH264_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS11_SXH264_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF5_OFS11_SXH264_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Msk (0x0000000FUL)
|
||||
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Pos (0UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Msk (0x000000F0UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Pos (4UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Msk (0x00000F00UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Pos (8UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Msk (0x0000F000UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Pos (12UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Msk (0x000F0000UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Pos (16UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Msk (0x00F00000UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Pos (20UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Msk (0x0F000000UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Pos (24UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Msk (0xF0000000UL)
|
||||
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Pos (28UL)
|
||||
#define R_SYSC_SYS_LP_CTL0_MAIN_CPU_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL0_MAIN_CPU_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_STBY_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_STBY_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Msk (0x00000300UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Msk (0x00001000UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Pos (12UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_STBY_CA55ST_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_STBY_CA55ST_Pos (16UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_STBY_CM33ST_Msk (0x00020000UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_STBY_CM33ST_Pos (17UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Msk (0x03000000UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Pos (24UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Msk (0x10000000UL)
|
||||
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Pos (28UL)
|
||||
#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0DP_F_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0DP_F_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0DM_F_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0DM_F_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0VBUSIN_F_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0VBUSIN_F_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0OVRCLR_F_Msk (0x00000008UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U0OVRCLR_F_Pos (3UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U1DP_F_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U1DP_F_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U1DM_F_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U1DM_F_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U1OVRCLR_F_Msk (0x00000800UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_U1OVRCLR_F_Pos (11UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_IRQ_F70_Msk (0x00FF0000UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_IRQ_F70_Pos (16UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_NMI_F_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_LP_CTL3_NMI_F_Pos (24UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0DP_E_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0DP_E_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0DM_E_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0DM_E_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0VBUSIN_E_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0VBUSIN_E_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0OVRCLR_E_Msk (0x00000008UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U0OVRCLR_E_Pos (3UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U1DP_E_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U1DP_E_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U1DM_E_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U1DM_E_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U1OVRCLR_E_Msk (0x00000800UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_U1OVRCLR_E_Pos (11UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E0_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E0_Pos (16UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E1_Msk (0x00020000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E1_Pos (17UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E2_Msk (0x00040000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E2_Pos (18UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E3_Msk (0x00080000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E3_Pos (19UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E4_Msk (0x00100000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E4_Pos (20UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E5_Msk (0x00200000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E5_Pos (21UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E6_Msk (0x00400000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E6_Pos (22UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E7_Msk (0x00800000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_IRQ_E7_Pos (23UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_NMI_E_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_LP_CTL4_NMI_E_Pos (24UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_STBY_F_Msk (0x00000010UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_STBY_F_Pos (4UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CA55SLEEP1_F_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CA55SLEEP1_F_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Msk (0x00000400UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Pos (10UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CA55STBYDONE_F_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CA55STBYDONE_F_Pos (16UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CM33STBYR_F_Msk (0x00100000UL)
|
||||
#define R_SYSC_SYS_LP_CTL5_CM33STBYR_F_Pos (20UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_STBY_E_Msk (0x00000010UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_STBY_E_Pos (4UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CA55STBYDONE_E_Msk (0x00000020UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CA55STBYDONE_E_Pos (5UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CM33STBYR_E_Msk (0x00000040UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CM33STBYR_E_Pos (6UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CA55SLEEP1_E_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CA55SLEEP1_E_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Msk (0x00000400UL)
|
||||
#define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Pos (10UL)
|
||||
#define R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL7_IM33_MASK_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CTL8_SUBCPU_RTRIG_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CTL8_SUBCPU_RTRIG_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Msk (0x00000010UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Pos (4UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_WICENABLEREQ_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_WICENABLEREQ_Pos (24UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_WICENABLEACK_Msk (0x02000000UL)
|
||||
#define R_SYSC_SYS_LP_CM33CTL0_WICENABLEACK_Pos (25UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Msk (0x00000400UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Pos (10UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Msk (0x00000800UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Pos (11UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQREQn_Msk (0x00000400UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQREQn_Pos (10UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Msk (0x00000800UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Pos (11UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Msk (0x00000400UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Pos (10UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Msk (0x00000800UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Pos (11UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN1_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN1_Pos (16UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Msk (0x00020000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Pos (17UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Msk (0x00040000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Pos (18UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Pos (24UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Msk (0x02000000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Pos (25UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Msk (0x04000000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Pos (26UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Msk (0x08000000UL)
|
||||
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Pos (27UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_GPU_Msk (0x00000001UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_GPU_Pos (0UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_AXI_SLV_Msk (0x00000002UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_AXI_SLV_Pos (1UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_AXI_MST_Msk (0x00000004UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_AXI_MST_Pos (2UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_ACE_SLV_Msk (0x00000008UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_ACE_SLV_Pos (3UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_ACE_MST_Msk (0x00000010UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACTIVE_ACE_MST_Pos (4UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_GPU_Msk (0x00000100UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_GPU_Pos (8UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_AXI_SLV_Msk (0x00000200UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_AXI_SLV_Pos (9UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_AXI_MST_Msk (0x00000400UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_AXI_MST_Pos (10UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_ACE_SLV_Msk (0x00000800UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_ACE_SLV_Pos (11UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_ACE_MST_Msk (0x00001000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QREQn_ACE_MST_Pos (12UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_GPU_Msk (0x00010000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_GPU_Pos (16UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_AXI_SLV_Msk (0x00020000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_AXI_SLV_Pos (17UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_AXI_MST_Msk (0x00040000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_AXI_MST_Pos (18UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_ACE_SLV_Msk (0x00080000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_ACE_SLV_Pos (19UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_ACE_MST_Msk (0x00100000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QACCEPTn_ACE_MST_Pos (20UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_GPU_Msk (0x01000000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_GPU_Pos (24UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_AXI_SLV_Msk (0x02000000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_AXI_SLV_Pos (25UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_AXI_MST_Msk (0x04000000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_AXI_MST_Pos (26UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_ACE_SLV_Msk (0x08000000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_ACE_SLV_Pos (27UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_ACE_MST_Msk (0x10000000UL)
|
||||
#define R_SYSC_SYS_LP_GPU_CTL_QDENY_ACE_MST_Pos (28UL)
|
||||
#define R_SYSC_SYS_GPREG_0_GPREG0_Msk (0xFFFFFFFFUL)
|
||||
#define R_SYSC_SYS_GPREG_0_GPREG0_Pos (0UL)
|
||||
#define R_SYSC_SYS_GPREG_1_GPREG1_Msk (0xFFFFFFFFUL)
|
||||
#define R_SYSC_SYS_GPREG_1_GPREG1_Pos (0UL)
|
||||
#define R_SYSC_SYS_GPREG_2_GPREG2_Msk (0xFFFFFFFFUL)
|
||||
#define R_SYSC_SYS_GPREG_2_GPREG2_Pos (0UL)
|
||||
#define R_SYSC_SYS_GPREG_3_GPREG3_Msk (0xFFFFFFFFUL)
|
||||
#define R_SYSC_SYS_GPREG_3_GPREG3_Pos (0UL)
|
||||
|
||||
#endif /* SYSC_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : wdt_iobitmask.h
|
||||
* Version : 1.00
|
||||
* Description : IO bit mask file for wdt.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef WDT_IOBITMASK_H
|
||||
#define WDT_IOBITMASK_H
|
||||
|
||||
#define R_WDT0_WDTCNT_WDTEN_Msk (0x00000001UL)
|
||||
#define R_WDT0_WDTCNT_WDTEN_Pos (0UL)
|
||||
#define R_WDT0_WDTSET_WDTTIME_Msk (0xFFF00000UL)
|
||||
#define R_WDT0_WDTSET_WDTTIME_Pos (20UL)
|
||||
#define R_WDT0_WDTTIM_CRTTIME_Msk (0xFFFFFFFFUL)
|
||||
#define R_WDT0_WDTTIM_CRTTIME_Pos (0UL)
|
||||
#define R_WDT0_WDTINT_INTDISP_Msk (0x00000001UL)
|
||||
#define R_WDT0_WDTINT_INTDISP_Pos (0UL)
|
||||
#define R_WDT0_PECR_PECR_Msk (0xFFFFFFFFUL)
|
||||
#define R_WDT0_PECR_PECR_Pos (0UL)
|
||||
#define R_WDT0_PEEN_PEEN_Msk (0x00000001UL)
|
||||
#define R_WDT0_PEEN_PEEN_Pos (0UL)
|
||||
#define R_WDT0_PESR_PESR_Msk (0xFFFFFFFFUL)
|
||||
#define R_WDT0_PESR_PESR_Pos (0UL)
|
||||
#define R_WDT0_PEER_PEER_Msk (0xFFFFFFFFUL)
|
||||
#define R_WDT0_PEER_PEER_Pos (0UL)
|
||||
#define R_WDT0_PEPO_PEPO_Msk (0xFFFFFFFFUL)
|
||||
#define R_WDT0_PEPO_PEPO_Pos (0UL)
|
||||
|
||||
#endif /* WDT_IOBITMASK_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : iodefine header
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef __IODEFINE_HEADER__
|
||||
#define __IODEFINE_HEADER__
|
||||
|
||||
#include "iodefines/accctl_iodefine.h"
|
||||
#include "iodefines/canfd_iodefine.h"
|
||||
#include "iodefines/cpg_iodefine.h"
|
||||
#include "iodefines/gpio_iodefine.h"
|
||||
#include "iodefines/gpt_iodefine.h"
|
||||
#include "iodefines/gtm_iodefine.h"
|
||||
#include "iodefines/intc_im33_iodefine.h"
|
||||
#include "iodefines/mhu_iodefine.h"
|
||||
#include "iodefines/mstp_iodefine.h"
|
||||
#include "iodefines/poeg_iodefine.h"
|
||||
#include "iodefines/riic_iodefine.h"
|
||||
#include "iodefines/rspi_iodefine.h"
|
||||
#include "iodefines/scifa_iodefine.h"
|
||||
#include "iodefines/spibsc_iodefine.h"
|
||||
#include "iodefines/ssi_iodefine.h"
|
||||
#include "iodefines/sysc_iodefine.h"
|
||||
#include "iodefines/wdt_iodefine.h"
|
||||
|
||||
#endif /* __IODEFINE_HEADER__ */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : accctl_iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : IO define file for accctl.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Cluster Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#ifndef ACCCTL_IODEFINE_H
|
||||
#define ACCCTL_IODEFINE_H
|
||||
|
||||
typedef struct /*!< R_ACCCTL_Type Structure */
|
||||
{
|
||||
__IOM uint32_t SYS_SLVACCCTL0;
|
||||
__IOM uint32_t SYS_SLVACCCTL1;
|
||||
__IOM uint32_t SYS_SLVACCCTL2;
|
||||
__IOM uint32_t SYS_SLVACCCTL3;
|
||||
__IOM uint32_t SYS_SLVACCCTL4;
|
||||
__IOM uint32_t SYS_SLVACCCTL5;
|
||||
__IOM uint32_t SYS_SLVACCCTL6;
|
||||
__IOM uint32_t SYS_SLVACCCTL7;
|
||||
__IOM uint32_t SYS_SLVACCCTL8;
|
||||
__IOM uint32_t SYS_SLVACCCTL9;
|
||||
__IOM uint32_t SYS_SLVACCCTL10;
|
||||
__IOM uint32_t SYS_SLVACCCTL11;
|
||||
__IOM uint32_t SYS_SLVACCCTL12;
|
||||
__IOM uint32_t SYS_SLVACCCTL13;
|
||||
__IOM uint32_t SYS_SLVACCCTL14;
|
||||
__IOM uint32_t SYS_SLVACCCTL15;
|
||||
} R_ACCCTL_Type; /*!< */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_ACCCTL_BASE_S 0x51020100 /* Access Control(Secure)*/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_ACCCTL_S ((R_ACCCTL_Type *) R_ACCCTL_BASE_S)
|
||||
|
||||
#endif /* ACCCTL_IODEFINE_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,681 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : gpt_iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : IO define file for gpt.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Cluster Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#ifndef GPT_IODEFINE_H
|
||||
#define GPT_IODEFINE_H
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTWP;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t WP : 1;
|
||||
uint32_t : 7;
|
||||
__IOM uint32_t PRKEY : 8;
|
||||
uint32_t : 16;
|
||||
} GTWP_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTSTR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CSTRT0 : 1;
|
||||
__IOM uint32_t CSTRT1 : 1;
|
||||
__IOM uint32_t CSTRT2 : 1;
|
||||
__IOM uint32_t CSTRT3 : 1;
|
||||
__IOM uint32_t CSTRT4 : 1;
|
||||
__IOM uint32_t CSTRT5 : 1;
|
||||
__IOM uint32_t CSTRT6 : 1;
|
||||
__IOM uint32_t CSTRT7 : 1;
|
||||
uint32_t : 24;
|
||||
} GTSTR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTSTP;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CSTOP0 : 1;
|
||||
__IOM uint32_t CSTOP1 : 1;
|
||||
__IOM uint32_t CSTOP2 : 1;
|
||||
__IOM uint32_t CSTOP3 : 1;
|
||||
__IOM uint32_t CSTOP4 : 1;
|
||||
__IOM uint32_t CSTOP5 : 1;
|
||||
__IOM uint32_t CSTOP6 : 1;
|
||||
__IOM uint32_t CSTOP7 : 1;
|
||||
uint32_t : 24;
|
||||
} GTSTP_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCLR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CCLR0 : 1;
|
||||
__IOM uint32_t CCLR1 : 1;
|
||||
__IOM uint32_t CCLR2 : 1;
|
||||
__IOM uint32_t CCLR3 : 1;
|
||||
__IOM uint32_t CCLR4 : 1;
|
||||
__IOM uint32_t CCLR5 : 1;
|
||||
__IOM uint32_t CCLR6 : 1;
|
||||
__IOM uint32_t CCLR7 : 1;
|
||||
uint32_t : 24;
|
||||
} GTCLR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTSSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t SSGTRGAR : 1;
|
||||
__IOM uint32_t SSGTRGAF : 1;
|
||||
__IOM uint32_t SSGTRGBR : 1;
|
||||
__IOM uint32_t SSGTRGBF : 1;
|
||||
__IOM uint32_t SSGTRGCR : 1;
|
||||
__IOM uint32_t SSGTRGCF : 1;
|
||||
__IOM uint32_t SSGTRGDR : 1;
|
||||
__IOM uint32_t SSGTRGDF : 1;
|
||||
__IOM uint32_t SSCARBL : 1;
|
||||
__IOM uint32_t SSCARBH : 1;
|
||||
__IOM uint32_t SSCAFBL : 1;
|
||||
__IOM uint32_t SSCAFBH : 1;
|
||||
__IOM uint32_t SSCBRAL : 1;
|
||||
__IOM uint32_t SSCBRAH : 1;
|
||||
__IOM uint32_t SSCBFAL : 1;
|
||||
__IOM uint32_t SSCBFAH : 1;
|
||||
uint32_t : 15;
|
||||
__IOM uint32_t CSTRT : 1;
|
||||
} GTSSR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTPSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t PSGTRGAR : 1;
|
||||
__IOM uint32_t PSGTRGAF : 1;
|
||||
__IOM uint32_t PSGTRGBR : 1;
|
||||
__IOM uint32_t PSGTRGBF : 1;
|
||||
__IOM uint32_t PSGTRGCR : 1;
|
||||
__IOM uint32_t PSGTRGCF : 1;
|
||||
__IOM uint32_t PSGTRGDR : 1;
|
||||
__IOM uint32_t PSGTRGDF : 1;
|
||||
__IOM uint32_t PSCARBL : 1;
|
||||
__IOM uint32_t PSCARBH : 1;
|
||||
__IOM uint32_t PSCAFBL : 1;
|
||||
__IOM uint32_t PSCAFBH : 1;
|
||||
__IOM uint32_t PSCBRAL : 1;
|
||||
__IOM uint32_t PSCBRAH : 1;
|
||||
__IOM uint32_t PSCBFAL : 1;
|
||||
__IOM uint32_t PSCBFAH : 1;
|
||||
uint32_t : 15;
|
||||
__IOM uint32_t CSTOP : 1;
|
||||
} GTPSR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CSGTRGAR : 1;
|
||||
__IOM uint32_t CSGTRGAF : 1;
|
||||
__IOM uint32_t CSGTRGBR : 1;
|
||||
__IOM uint32_t CSGTRGBF : 1;
|
||||
__IOM uint32_t CSGTRGCR : 1;
|
||||
__IOM uint32_t CSGTRGCF : 1;
|
||||
__IOM uint32_t CSGTRGDR : 1;
|
||||
__IOM uint32_t CSGTRGDF : 1;
|
||||
__IOM uint32_t CSCARBL : 1;
|
||||
__IOM uint32_t CSCARBH : 1;
|
||||
__IOM uint32_t CSCAFBL : 1;
|
||||
__IOM uint32_t CSCAFBH : 1;
|
||||
__IOM uint32_t CSCBRAL : 1;
|
||||
__IOM uint32_t CSCBRAH : 1;
|
||||
__IOM uint32_t CSCBFAL : 1;
|
||||
__IOM uint32_t CSCBFAH : 1;
|
||||
uint32_t : 15;
|
||||
__IOM uint32_t CCLR : 1;
|
||||
} GTCSR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTUPSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t USGTRGAR : 1;
|
||||
__IOM uint32_t USGTRGAF : 1;
|
||||
__IOM uint32_t USGTRGBR : 1;
|
||||
__IOM uint32_t USGTRGBF : 1;
|
||||
__IOM uint32_t USGTRGCR : 1;
|
||||
__IOM uint32_t USGTRGCF : 1;
|
||||
__IOM uint32_t USGTRGDR : 1;
|
||||
__IOM uint32_t USGTRGDF : 1;
|
||||
__IOM uint32_t USCARBL : 1;
|
||||
__IOM uint32_t USCARBH : 1;
|
||||
__IOM uint32_t USCAFBL : 1;
|
||||
__IOM uint32_t USCAFBH : 1;
|
||||
__IOM uint32_t USCBRAL : 1;
|
||||
__IOM uint32_t USCBRAH : 1;
|
||||
__IOM uint32_t USCBFAL : 1;
|
||||
__IOM uint32_t USCBFAH : 1;
|
||||
uint32_t : 16;
|
||||
} GTUPSR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTDNSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t DSGTRGAR : 1;
|
||||
__IOM uint32_t DSGTRGAF : 1;
|
||||
__IOM uint32_t DSGTRGBR : 1;
|
||||
__IOM uint32_t DSGTRGBF : 1;
|
||||
__IOM uint32_t DSGTRGCR : 1;
|
||||
__IOM uint32_t DSGTRGCF : 1;
|
||||
__IOM uint32_t DSGTRGDR : 1;
|
||||
__IOM uint32_t DSGTRGDF : 1;
|
||||
__IOM uint32_t DSCARBL : 1;
|
||||
__IOM uint32_t DSCARBH : 1;
|
||||
__IOM uint32_t DSCAFBL : 1;
|
||||
__IOM uint32_t DSCAFBH : 1;
|
||||
__IOM uint32_t DSCBRAL : 1;
|
||||
__IOM uint32_t DSCBRAH : 1;
|
||||
__IOM uint32_t DSCBFAL : 1;
|
||||
__IOM uint32_t DSCBFAH : 1;
|
||||
uint32_t : 16;
|
||||
} GTDNSR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTICASR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t ASGTRGAR : 1;
|
||||
__IOM uint32_t ASGTRGAF : 1;
|
||||
__IOM uint32_t ASGTRGBR : 1;
|
||||
__IOM uint32_t ASGTRGBF : 1;
|
||||
__IOM uint32_t ASGTRGCR : 1;
|
||||
__IOM uint32_t ASGTRGCF : 1;
|
||||
__IOM uint32_t ASGTRGDR : 1;
|
||||
__IOM uint32_t ASGTRGDF : 1;
|
||||
__IOM uint32_t ASCARBL : 1;
|
||||
__IOM uint32_t ASCARBH : 1;
|
||||
__IOM uint32_t ASCAFBL : 1;
|
||||
__IOM uint32_t ASCAFBH : 1;
|
||||
__IOM uint32_t ASCBRAL : 1;
|
||||
__IOM uint32_t ASCBRAH : 1;
|
||||
__IOM uint32_t ASCBFAL : 1;
|
||||
__IOM uint32_t ASCBFAH : 1;
|
||||
uint32_t : 16;
|
||||
} GTICASR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTICBSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t BSGTRGAR : 1;
|
||||
__IOM uint32_t BSGTRGAF : 1;
|
||||
__IOM uint32_t BSGTRGBR : 1;
|
||||
__IOM uint32_t BSGTRGBF : 1;
|
||||
__IOM uint32_t BSGTRGCR : 1;
|
||||
__IOM uint32_t BSGTRGCF : 1;
|
||||
__IOM uint32_t BSGTRGDR : 1;
|
||||
__IOM uint32_t BSGTRGDF : 1;
|
||||
__IOM uint32_t BSCARBL : 1;
|
||||
__IOM uint32_t BSCARBH : 1;
|
||||
__IOM uint32_t BSCAFBL : 1;
|
||||
__IOM uint32_t BSCAFBH : 1;
|
||||
__IOM uint32_t BSCBRAL : 1;
|
||||
__IOM uint32_t BSCBRAH : 1;
|
||||
__IOM uint32_t BSCBFAL : 1;
|
||||
__IOM uint32_t BSCBFAH : 1;
|
||||
uint32_t : 16;
|
||||
} GTICBSR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CST : 1;
|
||||
uint32_t : 15;
|
||||
__IOM uint32_t MD : 3;
|
||||
uint32_t : 5;
|
||||
__IOM uint32_t TPCS : 3;
|
||||
uint32_t : 5;
|
||||
} GTCR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTUDDTYC;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t UD : 1;
|
||||
__IOM uint32_t UDF : 1;
|
||||
uint32_t : 14;
|
||||
__IOM uint32_t OADTY : 2;
|
||||
__IOM uint32_t OADTYF : 1;
|
||||
__IOM uint32_t OADTYR : 1;
|
||||
uint32_t : 4;
|
||||
__IOM uint32_t OBDTY : 2;
|
||||
__IOM uint32_t OBDTYF : 1;
|
||||
__IOM uint32_t OBDTYR : 1;
|
||||
uint32_t : 4;
|
||||
} GTUDDTYC_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTIOR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTIOA : 5;
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t OADFLT : 1;
|
||||
__IOM uint32_t OAHLD : 1;
|
||||
__IOM uint32_t OAE : 1;
|
||||
__IOM uint32_t OADF : 2;
|
||||
uint32_t : 2;
|
||||
__IOM uint32_t NFAEN : 1;
|
||||
__IOM uint32_t NFCSA : 2;
|
||||
__IOM uint32_t GTIOB : 5;
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t OBDFLT : 1;
|
||||
__IOM uint32_t OBHLD : 1;
|
||||
__IOM uint32_t OBE : 1;
|
||||
__IOM uint32_t OBDF : 2;
|
||||
uint32_t : 2;
|
||||
__IOM uint32_t NFBEN : 1;
|
||||
__IOM uint32_t NFCSB : 2;
|
||||
} GTIOR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTINTAD;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTINTA : 1;
|
||||
__IOM uint32_t GTINTB : 1;
|
||||
__IOM uint32_t GTINTC : 1;
|
||||
__IOM uint32_t GTINTD : 1;
|
||||
__IOM uint32_t GTINTE : 1;
|
||||
__IOM uint32_t GTINTF : 1;
|
||||
__IOM uint32_t GTINTPR : 2;
|
||||
uint32_t : 8;
|
||||
__IOM uint32_t ADTRAUEN : 1;
|
||||
__IOM uint32_t ADTRADEN : 1;
|
||||
__IOM uint32_t ADTRBUEN : 1;
|
||||
__IOM uint32_t ADTRBDEN : 1;
|
||||
uint32_t : 4;
|
||||
__IOM uint32_t GRP : 2;
|
||||
uint32_t : 2;
|
||||
__IOM uint32_t GRPDTE : 1;
|
||||
__IOM uint32_t GRPABH : 1;
|
||||
__IOM uint32_t GRPABL : 1;
|
||||
uint32_t : 1;
|
||||
} GTINTAD_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTST;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TCFA : 1;
|
||||
__IOM uint32_t TCFB : 1;
|
||||
__IOM uint32_t TCFC : 1;
|
||||
__IOM uint32_t TCFD : 1;
|
||||
__IOM uint32_t TCFE : 1;
|
||||
__IOM uint32_t TCFF : 1;
|
||||
__IOM uint32_t TCFPO : 1;
|
||||
__IOM uint32_t TCFPU : 1;
|
||||
__IM uint32_t ITCNT : 3;
|
||||
uint32_t : 4;
|
||||
__IM uint32_t TUCF : 1;
|
||||
__IOM uint32_t ADTRAUF : 1;
|
||||
__IOM uint32_t ADTRADF : 1;
|
||||
__IOM uint32_t ADTRBUF : 1;
|
||||
__IOM uint32_t ADTRBDF : 1;
|
||||
uint32_t : 4;
|
||||
__IM uint32_t ODF : 1;
|
||||
uint32_t : 3;
|
||||
__IM uint32_t DTEF : 1;
|
||||
__IM uint32_t OABHF : 1;
|
||||
__IM uint32_t OABLF : 1;
|
||||
uint32_t : 1;
|
||||
} GTST_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTBER;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t BD : 4;
|
||||
uint32_t : 12;
|
||||
__IOM uint32_t CCRA : 2;
|
||||
__IOM uint32_t CCRB : 2;
|
||||
__IOM uint32_t PR : 2;
|
||||
__IOM uint32_t CCRSWT : 1;
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t ADTTA : 2;
|
||||
__IOM uint32_t ADTDA : 1;
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t ADTTB : 2;
|
||||
__IOM uint32_t ADTDB : 1;
|
||||
uint32_t : 1;
|
||||
} GTBER_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTITC;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t ITLA : 1;
|
||||
__IOM uint32_t ITLB : 1;
|
||||
__IOM uint32_t ITLC : 1;
|
||||
__IOM uint32_t ITLD : 1;
|
||||
__IOM uint32_t ITLE : 1;
|
||||
__IOM uint32_t ITLF : 1;
|
||||
__IOM uint32_t IVTC : 2;
|
||||
__IOM uint32_t IVTT : 3;
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t ADTAL : 1;
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t ADTBL : 1;
|
||||
uint32_t : 17;
|
||||
} GTITC_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCNT;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCNT : 32;
|
||||
} GTCNT_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCCRA;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCCRA : 32;
|
||||
} GTCCRA_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCCRB;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCCRB : 32;
|
||||
} GTCCRB_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCCRC;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCCRC : 32;
|
||||
} GTCCRC_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCCRE;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCCRE : 32;
|
||||
} GTCCRE_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCCRD;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCCRD : 32;
|
||||
} GTCCRD_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTCCRF;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTCCRF : 32;
|
||||
} GTCCRF_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTPR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTPR : 32;
|
||||
} GTPR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTPBR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTPBR : 32;
|
||||
} GTPBR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTPDBR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTPDBR : 32;
|
||||
} GTPDBR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTADTRA;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTADTRA : 32;
|
||||
} GTADTRA_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTADTBRA;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTADTBRA : 32;
|
||||
} GTADTBRA_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTADTDBRA;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTADTDBRA : 32;
|
||||
} GTADTDBRA_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTADTRB;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTADTRB : 32;
|
||||
} GTADTRB_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTADTBRB;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTADTBRB : 32;
|
||||
} GTADTBRB_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTADTDBRB;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTADTDBRB : 32;
|
||||
} GTADTDBRB_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTDTCR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TDE : 1;
|
||||
uint32_t : 3;
|
||||
__IOM uint32_t TDBUE : 1;
|
||||
__IOM uint32_t TDBDE : 1;
|
||||
uint32_t : 2;
|
||||
__IOM uint32_t TDFER : 1;
|
||||
uint32_t : 23;
|
||||
} GTDTCR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTDVU;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTDVU : 32;
|
||||
} GTDVU_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTDVD;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTDVD : 32;
|
||||
} GTDVD_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTDBU;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTDBU : 32;
|
||||
} GTDBU_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTDBD;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t GTDBD : 32;
|
||||
} GTDBD_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IM uint32_t GTSOS;
|
||||
struct
|
||||
{
|
||||
__IM uint32_t SOS : 2;
|
||||
uint32_t : 30;
|
||||
} GTSOS_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t GTSOTR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t SOTR : 1;
|
||||
uint32_t : 31;
|
||||
} GTSOTR_b;
|
||||
};
|
||||
} R_GPT32E0_Type;
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_GPT32E0_BASE 0x40048000
|
||||
#define R_GPT32E1_BASE 0x40048100
|
||||
#define R_GPT32E2_BASE 0x40048200
|
||||
#define R_GPT32E3_BASE 0x40048300
|
||||
#define R_GPT32E4_BASE 0x40048400
|
||||
#define R_GPT32E5_BASE 0x40048500
|
||||
#define R_GPT32E6_BASE 0x40048600
|
||||
#define R_GPT32E7_BASE 0x40048700
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_GPT32E0 ((R_GPT32E0_Type *) R_GPT32E0_BASE)
|
||||
#define R_GPT32E1 ((R_GPT32E0_Type *) R_GPT32E1_BASE)
|
||||
#define R_GPT32E2 ((R_GPT32E0_Type *) R_GPT32E2_BASE)
|
||||
#define R_GPT32E3 ((R_GPT32E0_Type *) R_GPT32E3_BASE)
|
||||
#define R_GPT32E4 ((R_GPT32E0_Type *) R_GPT32E4_BASE)
|
||||
#define R_GPT32E5 ((R_GPT32E0_Type *) R_GPT32E5_BASE)
|
||||
#define R_GPT32E6 ((R_GPT32E0_Type *) R_GPT32E6_BASE)
|
||||
#define R_GPT32E7 ((R_GPT32E0_Type *) R_GPT32E7_BASE)
|
||||
|
||||
#endif /* GPT_IODEFINE_H */
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : gtm_iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : IO define file for gtm.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Cluster Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#ifndef GTM_IODEFINE_H
|
||||
#define GTM_IODEFINE_H
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
__IOM uint32_t OSTMnCMP;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t OSTMnCMP : 32;
|
||||
} OSTMnCMP_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IM uint32_t OSTMnCNT;
|
||||
struct
|
||||
{
|
||||
__IM uint32_t OSTMnCNT : 32;
|
||||
} OSTMnCNT_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED[8];
|
||||
union
|
||||
{
|
||||
__IM uint8_t OSTMnTE;
|
||||
struct
|
||||
{
|
||||
__IM uint8_t OSTMnTE : 1;
|
||||
uint8_t : 7;
|
||||
} OSTMnTE_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED1[3];
|
||||
union
|
||||
{
|
||||
__IOM uint8_t OSTMnTS;
|
||||
struct
|
||||
{
|
||||
__OM uint8_t OSTMnTS : 1;
|
||||
uint8_t : 7;
|
||||
} OSTMnTS_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED2[3];
|
||||
union
|
||||
{
|
||||
__IOM uint8_t OSTMnTT;
|
||||
struct
|
||||
{
|
||||
__OM uint8_t OSTMnTT : 1;
|
||||
uint8_t : 7;
|
||||
} OSTMnTT_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED3[7];
|
||||
union
|
||||
{
|
||||
__IOM uint8_t OSTMnCTL;
|
||||
struct
|
||||
{
|
||||
__IOM uint8_t OSTMnMD0 : 1;
|
||||
__IOM uint8_t OSTMnMD1 : 1;
|
||||
uint8_t : 6;
|
||||
} OSTMnCTL_b;
|
||||
};
|
||||
} R_GTM0_Type;
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_GTM0_BASE 0x42801000
|
||||
#define R_GTM1_BASE 0x42801400
|
||||
#define R_GTM2_BASE 0x42801800
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_GTM0 ((R_GTM0_Type *) R_GTM0_BASE)
|
||||
#define R_GTM1 ((R_GTM0_Type *) R_GTM1_BASE)
|
||||
#define R_GTM2 ((R_GTM0_Type *) R_GTM2_BASE)
|
||||
|
||||
#endif /* GTM_IODEFINE_H */
|
||||
|
|
@ -0,0 +1,457 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : intc_im33_iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : IO define file for intc_im33.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Cluster Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#ifndef INTC_IM33_IODEFINE_H
|
||||
#define INTC_IM33_IODEFINE_H
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
__IOM uint32_t NSCR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t NSTAT : 1;
|
||||
uint32_t : 15;
|
||||
__IM uint32_t NSMON : 1;
|
||||
uint32_t : 15;
|
||||
} NSCR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t NITSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t NTSEL : 1;
|
||||
uint32_t : 31;
|
||||
} NITSR_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED[8];
|
||||
union
|
||||
{
|
||||
__IOM uint32_t ISCR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t ISTAT0 : 1;
|
||||
__IOM uint32_t ISTAT1 : 1;
|
||||
__IOM uint32_t ISTAT2 : 1;
|
||||
__IOM uint32_t ISTAT3 : 1;
|
||||
__IOM uint32_t ISTAT4 : 1;
|
||||
__IOM uint32_t ISTAT5 : 1;
|
||||
__IOM uint32_t ISTAT6 : 1;
|
||||
__IOM uint32_t ISTAT7 : 1;
|
||||
uint32_t : 24;
|
||||
} ISCR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t IITSR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t IITSEL0 : 2;
|
||||
__IOM uint32_t IITSEL1 : 2;
|
||||
__IOM uint32_t IITSEL2 : 2;
|
||||
__IOM uint32_t IITSEL3 : 2;
|
||||
__IOM uint32_t IITSEL4 : 2;
|
||||
__IOM uint32_t IITSEL5 : 2;
|
||||
__IOM uint32_t IITSEL6 : 2;
|
||||
__IOM uint32_t IITSEL7 : 2;
|
||||
uint32_t : 16;
|
||||
} IITSR_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED1[8];
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSCR;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSTAT0 : 1;
|
||||
__IOM uint32_t TSTAT1 : 1;
|
||||
__IOM uint32_t TSTAT2 : 1;
|
||||
__IOM uint32_t TSTAT3 : 1;
|
||||
__IOM uint32_t TSTAT4 : 1;
|
||||
__IOM uint32_t TSTAT5 : 1;
|
||||
__IOM uint32_t TSTAT6 : 1;
|
||||
__IOM uint32_t TSTAT7 : 1;
|
||||
__IOM uint32_t TSTAT8 : 1;
|
||||
__IOM uint32_t TSTAT9 : 1;
|
||||
__IOM uint32_t TSTAT10 : 1;
|
||||
__IOM uint32_t TSTAT11 : 1;
|
||||
__IOM uint32_t TSTAT12 : 1;
|
||||
__IOM uint32_t TSTAT13 : 1;
|
||||
__IOM uint32_t TSTAT14 : 1;
|
||||
__IOM uint32_t TSTAT15 : 1;
|
||||
__IOM uint32_t TSTAT16 : 1;
|
||||
__IOM uint32_t TSTAT17 : 1;
|
||||
__IOM uint32_t TSTAT18 : 1;
|
||||
__IOM uint32_t TSTAT19 : 1;
|
||||
__IOM uint32_t TSTAT20 : 1;
|
||||
__IOM uint32_t TSTAT21 : 1;
|
||||
__IOM uint32_t TSTAT22 : 1;
|
||||
__IOM uint32_t TSTAT23 : 1;
|
||||
__IOM uint32_t TSTAT24 : 1;
|
||||
__IOM uint32_t TSTAT25 : 1;
|
||||
__IOM uint32_t TSTAT26 : 1;
|
||||
__IOM uint32_t TSTAT27 : 1;
|
||||
__IOM uint32_t TSTAT28 : 1;
|
||||
__IOM uint32_t TSTAT29 : 1;
|
||||
__IOM uint32_t TSTAT30 : 1;
|
||||
__IOM uint32_t TSTAT31 : 1;
|
||||
} TSCR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TITSR0;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TITSEL0 : 2;
|
||||
__IOM uint32_t TITSEL1 : 2;
|
||||
__IOM uint32_t TITSEL2 : 2;
|
||||
__IOM uint32_t TITSEL3 : 2;
|
||||
__IOM uint32_t TITSEL4 : 2;
|
||||
__IOM uint32_t TITSEL5 : 2;
|
||||
__IOM uint32_t TITSEL6 : 2;
|
||||
__IOM uint32_t TITSEL7 : 2;
|
||||
__IOM uint32_t TITSEL8 : 2;
|
||||
__IOM uint32_t TITSEL9 : 2;
|
||||
__IOM uint32_t TITSEL10 : 2;
|
||||
__IOM uint32_t TITSEL11 : 2;
|
||||
__IOM uint32_t TITSEL12 : 2;
|
||||
__IOM uint32_t TITSEL13 : 2;
|
||||
__IOM uint32_t TITSEL14 : 2;
|
||||
__IOM uint32_t TITSEL15 : 2;
|
||||
} TITSR0_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TITSR1;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TITSEL16 : 2;
|
||||
__IOM uint32_t TITSEL17 : 2;
|
||||
__IOM uint32_t TITSEL18 : 2;
|
||||
__IOM uint32_t TITSEL19 : 2;
|
||||
__IOM uint32_t TITSEL20 : 2;
|
||||
__IOM uint32_t TITSEL21 : 2;
|
||||
__IOM uint32_t TITSEL22 : 2;
|
||||
__IOM uint32_t TITSEL23 : 2;
|
||||
__IOM uint32_t TITSEL24 : 2;
|
||||
__IOM uint32_t TITSEL25 : 2;
|
||||
__IOM uint32_t TITSEL26 : 2;
|
||||
__IOM uint32_t TITSEL27 : 2;
|
||||
__IOM uint32_t TITSEL28 : 2;
|
||||
__IOM uint32_t TITSEL29 : 2;
|
||||
__IOM uint32_t TITSEL30 : 2;
|
||||
__IOM uint32_t TITSEL31 : 2;
|
||||
} TITSR1_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED2[4];
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR0;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL0 : 7;
|
||||
__IOM uint32_t TIEN0 : 1;
|
||||
__IOM uint32_t TSSEL1 : 7;
|
||||
__IOM uint32_t TIEN1 : 1;
|
||||
__IOM uint32_t TSSEL2 : 7;
|
||||
__IOM uint32_t TIEN2 : 1;
|
||||
__IOM uint32_t TSSEL3 : 7;
|
||||
__IOM uint32_t TIEN3 : 1;
|
||||
} TSSR0_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR1;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL4 : 7;
|
||||
__IOM uint32_t TIEN4 : 1;
|
||||
__IOM uint32_t TSSEL5 : 7;
|
||||
__IOM uint32_t TIEN5 : 1;
|
||||
__IOM uint32_t TSSEL6 : 7;
|
||||
__IOM uint32_t TIEN6 : 1;
|
||||
__IOM uint32_t TSSEL7 : 7;
|
||||
__IOM uint32_t TIEN7 : 1;
|
||||
} TSSR1_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR2;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL8 : 7;
|
||||
__IOM uint32_t TIEN8 : 1;
|
||||
__IOM uint32_t TSSEL9 : 7;
|
||||
__IOM uint32_t TIEN9 : 1;
|
||||
__IOM uint32_t TSSEL10 : 7;
|
||||
__IOM uint32_t TIEN10 : 1;
|
||||
__IOM uint32_t TSSEL11 : 7;
|
||||
__IOM uint32_t TIEN11 : 1;
|
||||
} TSSR2_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR3;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL12 : 7;
|
||||
__IOM uint32_t TIEN12 : 1;
|
||||
__IOM uint32_t TSSEL13 : 7;
|
||||
__IOM uint32_t TIEN13 : 1;
|
||||
__IOM uint32_t TSSEL14 : 7;
|
||||
__IOM uint32_t TIEN14 : 1;
|
||||
__IOM uint32_t TSSEL15 : 7;
|
||||
__IOM uint32_t TIEN15 : 1;
|
||||
} TSSR3_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR4;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL16 : 7;
|
||||
__IOM uint32_t TIEN16 : 1;
|
||||
__IOM uint32_t TSSEL17 : 7;
|
||||
__IOM uint32_t TIEN17 : 1;
|
||||
__IOM uint32_t TSSEL18 : 7;
|
||||
__IOM uint32_t TIEN18 : 1;
|
||||
__IOM uint32_t TSSEL19 : 7;
|
||||
__IOM uint32_t TIEN19 : 1;
|
||||
} TSSR4_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR5;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL20 : 7;
|
||||
__IOM uint32_t TIEN20 : 1;
|
||||
__IOM uint32_t TSSEL21 : 7;
|
||||
__IOM uint32_t TIEN21 : 1;
|
||||
__IOM uint32_t TSSEL22 : 7;
|
||||
__IOM uint32_t TIEN22 : 1;
|
||||
__IOM uint32_t TSSEL23 : 7;
|
||||
__IOM uint32_t TIEN23 : 1;
|
||||
} TSSR5_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR6;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL24 : 7;
|
||||
__IOM uint32_t TIEN24 : 1;
|
||||
__IOM uint32_t TSSEL25 : 7;
|
||||
__IOM uint32_t TIEN25 : 1;
|
||||
__IOM uint32_t TSSEL26 : 7;
|
||||
__IOM uint32_t TIEN26 : 1;
|
||||
__IOM uint32_t TSSEL27 : 7;
|
||||
__IOM uint32_t TIEN27 : 1;
|
||||
} TSSR6_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TSSR7;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t TSSEL28 : 7;
|
||||
__IOM uint32_t TIEN28 : 1;
|
||||
__IOM uint32_t TSSEL29 : 7;
|
||||
__IOM uint32_t TIEN29 : 1;
|
||||
__IOM uint32_t TSSEL30 : 7;
|
||||
__IOM uint32_t TIEN30 : 1;
|
||||
__IOM uint32_t TSSEL31 : 7;
|
||||
__IOM uint32_t TIEN31 : 1;
|
||||
} TSSR7_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t BEISR0;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t BESTAT0 : 1;
|
||||
__IOM uint32_t BESTAT1 : 1;
|
||||
__IOM uint32_t BESTAT2 : 1;
|
||||
__IOM uint32_t BESTAT3 : 1;
|
||||
__IOM uint32_t BESTAT4 : 1;
|
||||
__IOM uint32_t BESTAT5 : 1;
|
||||
__IOM uint32_t BESTAT6 : 1;
|
||||
__IOM uint32_t BESTAT7 : 1;
|
||||
__IOM uint32_t BESTAT8 : 1;
|
||||
__IOM uint32_t BESTAT9 : 1;
|
||||
__IOM uint32_t BESTAT10 : 1;
|
||||
__IOM uint32_t BESTAT11 : 1;
|
||||
__IOM uint32_t BESTAT12 : 1;
|
||||
__IOM uint32_t BESTAT13 : 1;
|
||||
__IOM uint32_t BESTAT14 : 1;
|
||||
__IOM uint32_t BESTAT15 : 1;
|
||||
__IOM uint32_t BESTAT16 : 1;
|
||||
__IOM uint32_t BESTAT17 : 1;
|
||||
__IOM uint32_t BESTAT18 : 1;
|
||||
__IOM uint32_t BESTAT19 : 1;
|
||||
__IOM uint32_t BESTAT20 : 1;
|
||||
__IOM uint32_t BESTAT21 : 1;
|
||||
__IOM uint32_t BESTAT22 : 1;
|
||||
__IOM uint32_t BESTAT23 : 1;
|
||||
__IOM uint32_t BESTAT24 : 1;
|
||||
__IOM uint32_t BESTAT25 : 1;
|
||||
__IOM uint32_t BESTAT26 : 1;
|
||||
__IOM uint32_t BESTAT27 : 1;
|
||||
__IOM uint32_t BESTAT28 : 1;
|
||||
__IOM uint32_t BESTAT29 : 1;
|
||||
__IOM uint32_t BESTAT30 : 1;
|
||||
__IOM uint32_t BESTAT31 : 1;
|
||||
} BEISR0_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t BEISR1;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t BESTAT32 : 1;
|
||||
__IOM uint32_t BESTAT33 : 1;
|
||||
__IOM uint32_t BESTAT34 : 1;
|
||||
__IOM uint32_t BESTAT35 : 1;
|
||||
__IOM uint32_t BESTAT36 : 1;
|
||||
__IOM uint32_t BESTAT37 : 1;
|
||||
__IOM uint32_t BESTAT38 : 1;
|
||||
__IOM uint32_t BESTAT39 : 1;
|
||||
__IOM uint32_t BESTAT40 : 1;
|
||||
__IOM uint32_t BESTAT41 : 1;
|
||||
__IOM uint32_t BESTAT42 : 1;
|
||||
__IOM uint32_t BESTAT43 : 1;
|
||||
__IOM uint32_t BESTAT44 : 1;
|
||||
uint32_t : 19;
|
||||
} BEISR1_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED3[8];
|
||||
union
|
||||
{
|
||||
__IOM uint32_t EREISR0;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t E1STAT0 : 1;
|
||||
__IOM uint32_t E1STAT1 : 1;
|
||||
__IOM uint32_t E1STAT2 : 1;
|
||||
__IOM uint32_t E1STAT3 : 1;
|
||||
__IOM uint32_t E1STAT4 : 1;
|
||||
__IOM uint32_t E1STAT5 : 1;
|
||||
__IOM uint32_t E1STAT6 : 1;
|
||||
__IOM uint32_t E1STAT7 : 1;
|
||||
__IOM uint32_t E2STAT0 : 1;
|
||||
__IOM uint32_t E2STAT1 : 1;
|
||||
__IOM uint32_t E2STAT2 : 1;
|
||||
__IOM uint32_t E2STAT3 : 1;
|
||||
__IOM uint32_t E2STAT4 : 1;
|
||||
__IOM uint32_t E2STAT5 : 1;
|
||||
__IOM uint32_t E2STAT6 : 1;
|
||||
__IOM uint32_t E2STAT7 : 1;
|
||||
__IOM uint32_t OFSTAT0 : 1;
|
||||
__IOM uint32_t OFSTAT1 : 1;
|
||||
__IOM uint32_t OFSTAT2 : 1;
|
||||
__IOM uint32_t OFSTAT3 : 1;
|
||||
__IOM uint32_t OFSTAT4 : 1;
|
||||
__IOM uint32_t OFSTAT5 : 1;
|
||||
__IOM uint32_t OFSTAT6 : 1;
|
||||
__IOM uint32_t OFSTAT7 : 1;
|
||||
uint32_t : 8;
|
||||
} EREISR0_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t EREISR1;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t E1STAT0 : 1;
|
||||
__IOM uint32_t E1STAT1 : 1;
|
||||
__IOM uint32_t E1STAT2 : 1;
|
||||
__IOM uint32_t E1STAT3 : 1;
|
||||
__IOM uint32_t E1STAT4 : 1;
|
||||
__IOM uint32_t E1STAT5 : 1;
|
||||
__IOM uint32_t E1STAT6 : 1;
|
||||
__IOM uint32_t E1STAT7 : 1;
|
||||
__IOM uint32_t E2STAT0 : 1;
|
||||
__IOM uint32_t E2STAT1 : 1;
|
||||
__IOM uint32_t E2STAT2 : 1;
|
||||
__IOM uint32_t E2STAT3 : 1;
|
||||
__IOM uint32_t E2STAT4 : 1;
|
||||
__IOM uint32_t E2STAT5 : 1;
|
||||
__IOM uint32_t E2STAT6 : 1;
|
||||
__IOM uint32_t E2STAT7 : 1;
|
||||
__IOM uint32_t OFSTAT0 : 1;
|
||||
__IOM uint32_t OFSTAT1 : 1;
|
||||
__IOM uint32_t OFSTAT2 : 1;
|
||||
__IOM uint32_t OFSTAT3 : 1;
|
||||
__IOM uint32_t OFSTAT4 : 1;
|
||||
__IOM uint32_t OFSTAT5 : 1;
|
||||
__IOM uint32_t OFSTAT6 : 1;
|
||||
__IOM uint32_t OFSTAT7 : 1;
|
||||
uint32_t : 8;
|
||||
} EREISR1_b;
|
||||
};
|
||||
} R_INTC_IM33_Type;
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_INTC_IM33_BASE 0x410B0000
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_INTC_IM33 ((R_INTC_IM33_Type *) R_INTC_IM33_BASE)
|
||||
|
||||
#endif /* INTC_IM33_IODEFINE_H */
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : mhu_iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : IO define file for mhu.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Cluster Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#ifndef MHU_IODEFINE_H
|
||||
#define MHU_IODEFINE_H
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
__IM uint32_t MSG_INT_STSn;
|
||||
struct
|
||||
{
|
||||
__IM uint32_t STAT : 1;
|
||||
uint32_t : 31;
|
||||
} MSG_INT_STSn_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t MSG_INT_SETn;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t SET : 1;
|
||||
uint32_t : 31;
|
||||
} MSG_INT_SETn_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t MSG_INT_CLRn;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CLEAR : 1;
|
||||
uint32_t : 31;
|
||||
} MSG_INT_CLRn_b;
|
||||
};
|
||||
|
||||
__IM uint8_t RESERVED[4];
|
||||
union
|
||||
{
|
||||
__IM uint32_t RSP_INT_STSn;
|
||||
struct
|
||||
{
|
||||
__IM uint32_t STAT : 1;
|
||||
uint32_t : 31;
|
||||
} RSP_INT_STSn_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t RSP_INT_SETn;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t SET : 1;
|
||||
uint32_t : 31;
|
||||
} RSP_INT_SETn_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t RSP_INT_CLRn;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CLEAR : 1;
|
||||
uint32_t : 31;
|
||||
} RSP_INT_CLRn_b;
|
||||
};
|
||||
} R_MHU0_Type;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
__IM uint32_t SW_INT_STSn;
|
||||
struct
|
||||
{
|
||||
__IM uint32_t STAT : 1;
|
||||
uint32_t : 31;
|
||||
} SW_INT_STSn_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t SW_INT_SETn;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t SET : 1;
|
||||
uint32_t : 31;
|
||||
} SW_INT_SETn_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t SW_INT_CLRn;
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t CLEAR : 1;
|
||||
uint32_t : 31;
|
||||
} SW_INT_CLRn_b;
|
||||
};
|
||||
} R_MHU_SWINT0_Type;
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_MHU0_BASE 0x40400000
|
||||
#define R_MHU1_BASE 0x40400020
|
||||
#define R_MHU2_BASE 0x40400040
|
||||
#define R_MHU3_BASE 0x40400060
|
||||
#define R_MHU4_BASE 0x40400080
|
||||
#define R_MHU5_BASE 0x404000A0
|
||||
#define R_MHU_SWINT0_BASE 0x40400800
|
||||
#define R_MHU_SWINT1_BASE 0x40400810
|
||||
#define R_MHU_SWINT2_BASE 0x40400820
|
||||
#define R_MHU_SWINT3_BASE 0x40400830
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_MHU0 ((R_MHU0_Type *) R_MHU0_BASE)
|
||||
#define R_MHU1 ((R_MHU0_Type *) R_MHU1_BASE)
|
||||
#define R_MHU2 ((R_MHU0_Type *) R_MHU2_BASE)
|
||||
#define R_MHU3 ((R_MHU0_Type *) R_MHU3_BASE)
|
||||
#define R_MHU4 ((R_MHU0_Type *) R_MHU4_BASE)
|
||||
#define R_MHU5 ((R_MHU0_Type *) R_MHU5_BASE)
|
||||
#define R_MHU_SWINT0 ((R_MHU_SWINT0_Type *) R_MHU_SWINT0_BASE)
|
||||
#define R_MHU_SWINT1 ((R_MHU_SWINT0_Type *) R_MHU_SWINT1_BASE)
|
||||
#define R_MHU_SWINT2 ((R_MHU_SWINT0_Type *) R_MHU_SWINT2_BASE)
|
||||
#define R_MHU_SWINT3 ((R_MHU_SWINT0_Type *) R_MHU_SWINT3_BASE)
|
||||
|
||||
#endif /* MHU_IODEFINE_H */
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
|
||||
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
|
||||
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
|
||||
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
|
||||
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
|
||||
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
|
||||
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
|
||||
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
|
||||
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
|
||||
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
|
||||
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
|
||||
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
|
||||
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* File Name : mstp_iodefine.h
|
||||
* Version : 1.00
|
||||
* Description : IO define file for mstp.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Cluster Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Section ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#ifndef MSTP_IODEFINE_H
|
||||
#define MSTP_IODEFINE_H
|
||||
|
||||
typedef struct /*!< (@ 0x41010B60) R_MSTP Structure */
|
||||
{
|
||||
union
|
||||
{
|
||||
__IOM uint32_t ACPU; /*!< (@ 0x41010B60) ACPU Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MXSRAM_A : 1; /*!< [ 0.. 0] Module Stop of MXSRAM_A */
|
||||
uint32_t : 15;
|
||||
__IOM uint32_t MXSRAM_A_WE : 1; /*!< [16..16] Write Enable of MXSRAM_A */
|
||||
uint32_t : 15;
|
||||
} ACPU_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t MCPU1; /*!< (@ 0x41010B64) MCPU1 Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MXSRAM_M : 1; /*!< [ 0.. 0] Module Stop of MXSRAM_M */
|
||||
__IOM uint32_t MHSPI : 1; /*!< [ 1.. 1] Module Stop of MHSPI */
|
||||
__IOM uint32_t MHMTU3A : 1; /*!< [ 2.. 2] Module Stop of MHMTU3A */
|
||||
__IOM uint32_t MHSRC : 1; /*!< [ 3.. 3] Module Stop of MHSRC */
|
||||
__IOM uint32_t MHGPT : 1; /*!< [ 4.. 4] Module Stop of MHGPT */
|
||||
__IOM uint32_t MHPOEGA : 1; /*!< [ 5.. 5] Module Stop of MHPOEGA */
|
||||
__IOM uint32_t MHPOEGB : 1; /*!< [ 6.. 6] Module Stop of MHPOEGB */
|
||||
__IOM uint32_t MHPOEGC : 1; /*!< [ 7.. 7] Module Stop of MHPOEGC */
|
||||
__IOM uint32_t MHPOEGD : 1; /*!< [ 8.. 8] Module Stop of MHPOEGD */
|
||||
__IOM uint32_t MHPOE3 : 1; /*!< [ 9.. 9] Module Stop of MHPOE3 */
|
||||
__IOM uint32_t MHSSIF0 : 1; /*!< [10..10] Module Stop of MHSSIF0 */
|
||||
__IOM uint32_t MHSSIF1 : 1; /*!< [11..11] Module Stop of MHSSIF1 */
|
||||
__IOM uint32_t MHSSIF2 : 1; /*!< [12..12] Module Stop of MHSSIF2 */
|
||||
__IOM uint32_t MHSSIF3 : 1; /*!< [13..13] Module Stop of MHSSIF3 */
|
||||
__IOM uint32_t MHRSPI0 : 1; /*!< [14..14] Module Stop of MHRSPI0 */
|
||||
__IOM uint32_t MHRSPI1 : 1; /*!< [15..15] Module Stop of MHRSPI1 */
|
||||
__IOM uint32_t MXSRAM_M_WE : 1; /*!< [16..16] Write Enable of MXSRAM_M */
|
||||
__IOM uint32_t MHSPI_WE : 1; /*!< [17..17] Write Enable of MHSPI */
|
||||
__IOM uint32_t MHMTU3A_WE : 1; /*!< [18..18] Write Enable of MHMTU3A */
|
||||
__IOM uint32_t MHSRC_WE : 1; /*!< [19..19] Write Enable of MHSRC */
|
||||
__IOM uint32_t MHGPT_WE : 1; /*!< [20..20] Write Enable of MHGPT */
|
||||
__IOM uint32_t MHPOEGA_WE : 1; /*!< [21..21] Write Enable of MHPOEGA */
|
||||
__IOM uint32_t MHPOEGB_WE : 1; /*!< [22..22] Write Enable of MHPOEGB */
|
||||
__IOM uint32_t MHPOEGC_WE : 1; /*!< [23..23] Write Enable of MHPOEGC */
|
||||
__IOM uint32_t MHPOEGD_WE : 1; /*!< [24..24] Write Enable of MHPOEGD */
|
||||
__IOM uint32_t MHPOE3_WE : 1; /*!< [25..25] Write Enable of MHPOE3 */
|
||||
__IOM uint32_t MHSSIF0_WE : 1; /*!< [26..26] Write Enable of MHSSIF0 */
|
||||
__IOM uint32_t MHSSIF1_WE : 1; /*!< [27..27] Write Enable of MHSSIF1 */
|
||||
__IOM uint32_t MHSSIF2_WE : 1; /*!< [28..28] Write Enable of MHSSIF2 */
|
||||
__IOM uint32_t MHSSIF3_WE : 1; /*!< [29..29] Write Enable of MHSSIF3 */
|
||||
__IOM uint32_t MHRSPI0_WE : 1; /*!< [30..30] Write Enable of MHRSPI0 */
|
||||
__IOM uint32_t MHRSPI1_WE : 1; /*!< [31..31] Write Enable of MHRSPI1 */
|
||||
} MCPU1_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t MCPU2; /*!< (@ 0x41010B68) MCPU2 Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MHRSPI2 : 1; /*!< [ 0.. 0] Module Stop of MHRSPI2 */
|
||||
__IOM uint32_t MHSCIF0 : 1; /*!< [ 1.. 1] Module Stop of MHSCIF0 */
|
||||
__IOM uint32_t MHSCIF1 : 1; /*!< [ 2.. 2] Module Stop of MHSCIF1 */
|
||||
__IOM uint32_t MHSCIF2 : 1; /*!< [ 3.. 3] Module Stop of MHSCIF2 */
|
||||
__IOM uint32_t MHSCIF3 : 1; /*!< [ 4.. 4] Module Stop of MHSCIF3 */
|
||||
__IOM uint32_t MHSCIF4 : 1; /*!< [ 5.. 5] Module Stop of MHSCIF4 */
|
||||
__IOM uint32_t MHIRDA : 1; /*!< [ 6.. 6] Module Stop of MHIRDA */
|
||||
__IOM uint32_t MHSCI0 : 1; /*!< [ 7.. 7] Module Stop of MHSCI0 */
|
||||
__IOM uint32_t MHSCI1 : 1; /*!< [ 8.. 8] Module Stop of MHSCI1 */
|
||||
__IOM uint32_t MPCANFD : 1; /*!< [ 9.. 9] Module Stop of MPCANFD */
|
||||
__IOM uint32_t MPI2C0 : 1; /*!< [10..10] Module Stop of MPI2C0 */
|
||||
__IOM uint32_t MPI2C1 : 1; /*!< [11..11] Module Stop of MPI2C1 */
|
||||
__IOM uint32_t MPI2C2 : 1; /*!< [12..12] Module Stop of MPI2C2 */
|
||||
__IOM uint32_t MPI2C3 : 1; /*!< [13..13] Module Stop of MPI2C3 */
|
||||
__IOM uint32_t MPADC : 1; /*!< [14..14] Module Stop of MPADC */
|
||||
__IOM uint32_t MPTSU : 1; /*!< [15..15] Module Stop of MPTSU */
|
||||
__IOM uint32_t MHRSPI2_WE : 1; /*!< [16..16] Write Enable of MHRSPI2 */
|
||||
__IOM uint32_t MHSCIF0_WE : 1; /*!< [17..17] Write Enable of MHSCIF0 */
|
||||
__IOM uint32_t MHSCIF1_WE : 1; /*!< [18..18] Write Enable of MHSCIF1 */
|
||||
__IOM uint32_t MHSCIF2_WE : 1; /*!< [19..19] Write Enable of MHSCIF2 */
|
||||
__IOM uint32_t MHSCIF3_WE : 1; /*!< [20..20] Write Enable of MHSCIF3 */
|
||||
__IOM uint32_t MHSCIF4_WE : 1; /*!< [21..21] Write Enable of MHSCIF4 */
|
||||
__IOM uint32_t MHIRDA_WE : 1; /*!< [22..22] Write Enable of MHIRDA */
|
||||
__IOM uint32_t MHSCI0_WE : 1; /*!< [23..23] Write Enable of MHSCI0 */
|
||||
__IOM uint32_t MHSCI1_WE : 1; /*!< [24..24] Write Enable of MHSCI1 */
|
||||
__IOM uint32_t MPCANFD_WE : 1; /*!< [25..25] Write Enable of MPCANFD */
|
||||
__IOM uint32_t MPI2C0_WE : 1; /*!< [26..26] Write Enable of MPI2C0 */
|
||||
__IOM uint32_t MPI2C1_WE : 1; /*!< [27..27] Write Enable of MPI2C1 */
|
||||
__IOM uint32_t MPI2C2_WE : 1; /*!< [28..28] Write Enable of MPI2C2 */
|
||||
__IOM uint32_t MPI2C3_WE : 1; /*!< [29..29] Write Enable of MPI2C3 */
|
||||
__IOM uint32_t MPADC_WE : 1; /*!< [30..30] Write Enable of MPADC */
|
||||
__IOM uint32_t MPTSU_WE : 1; /*!< [31..31] Write Enable of MPTSU */
|
||||
} MCPU2_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t PERI_COM; /*!< (@ 0x41010B6C) PERI_COM Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MXSDHI0 : 1; /*!< [ 0.. 0] Module Stop of MXSDHI0 */
|
||||
__IOM uint32_t MXSDHI1 : 1; /*!< [ 1.. 1] Module Stop of MXSDHI1 */
|
||||
__IOM uint32_t MPGIGE0 : 1; /*!< [ 2.. 2] Module Stop of MPGIGE0 */
|
||||
__IOM uint32_t MPGIGE1 : 1; /*!< [ 3.. 3] Module Stop of MPGIGE1 */
|
||||
__IOM uint32_t MPUSBT : 1; /*!< [ 4.. 4] Module Stop of MPUSBT */
|
||||
__IOM uint32_t MHUSB2H : 1; /*!< [ 5.. 5] Module Stop of MHUSB2H */
|
||||
__IOM uint32_t MHUSB2F : 1; /*!< [ 6.. 6] Module Stop of MHUSB2F */
|
||||
__IOM uint32_t MHUSB21 : 1; /*!< [ 7.. 7] Module Stop of MHUSB21 */
|
||||
__IOM uint32_t MXCOM : 1; /*!< [ 8.. 8] Module Stop of MXCOM */
|
||||
uint32_t : 7;
|
||||
__IOM uint32_t MXSDHI0_WE : 1; /*!< [16..16] Write Enable of MXSDHI0 */
|
||||
__IOM uint32_t MXSDHI1_WE : 1; /*!< [17..17] Write Enable of MXSDHI1 */
|
||||
__IOM uint32_t MPGIGE0_WE : 1; /*!< [18..18] Write Enable of MPGIGE0 */
|
||||
__IOM uint32_t MPGIGE1_WE : 1; /*!< [19..19] Write Enable of MPGIGE1 */
|
||||
__IOM uint32_t MPUSBT_WE : 1; /*!< [20..20] Write Enable of MPUSBT */
|
||||
__IOM uint32_t MHUSB2H_WE : 1; /*!< [21..21] Write Enable of MHUSB2H */
|
||||
__IOM uint32_t MHUSB2F_WE : 1; /*!< [22..22] Write Enable of MHUSB2F */
|
||||
__IOM uint32_t MHUSB21_WE : 1; /*!< [23..23] Write Enable of MHUSB21 */
|
||||
__IOM uint32_t MXCOM_WE : 1; /*!< [24..24] Write Enable of MXCOM */
|
||||
uint32_t : 7;
|
||||
} PERI_COM_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t PERI_CPU; /*!< (@ 0x41010B70) PERI_CPU Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MXMCPU : 1; /*!< [ 0.. 0] Module Stop of MXMCPU */
|
||||
__IOM uint32_t MXACPU : 1; /*!< [ 1.. 1] Module Stop of MXACPU */
|
||||
__IOM uint32_t MPCST : 1; /*!< [ 2.. 2] Module Stop of MPCST */
|
||||
__IOM uint32_t MPSYC : 1; /*!< [ 3.. 3] Module Stop of MPSYC */
|
||||
__IOM uint32_t MPCPG : 1; /*!< [ 4.. 4] Module Stop of MPCPG */
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t MHGPIO : 1; /*!< [ 6.. 6] Module Stop of MHGPIO */
|
||||
__IOM uint32_t MPTZC0 : 1; /*!< [ 7.. 7] Module Stop of MPTZC0 */
|
||||
__IOM uint32_t MPTZC1 : 1; /*!< [ 8.. 8] Module Stop of MPTZC1 */
|
||||
__IOM uint32_t MPTZC2 : 1; /*!< [ 9.. 9] Module Stop of MPTZC2 */
|
||||
__IOM uint32_t MPTZC3 : 1; /*!< [10..10] Module Stop of MPTZC3 */
|
||||
__IOM uint32_t MPSRAM_A : 1; /*!< [11..11] Module Stop of MPSRAM_A */
|
||||
__IOM uint32_t MPSRAM_M : 1; /*!< [12..12] Module Stop of MPSRAM_M */
|
||||
__IOM uint32_t MPIA55 : 1; /*!< [13..13] Module Stop of MPIA55 */
|
||||
__IOM uint32_t MPIM33 : 1; /*!< [14..14] Module Stop of MPIM33 */
|
||||
__IOM uint32_t MXREG0 : 1; /*!< [15..15] Module Stop of MXREG0 */
|
||||
__IOM uint32_t MXMCPU_WE : 1; /*!< [16..16] Write Enable of MXMCPU */
|
||||
__IOM uint32_t MXACPU_WE : 1; /*!< [17..17] Write Enable of MXACPU */
|
||||
__IOM uint32_t MPCST_WE : 1; /*!< [18..18] Write Enable of MPCST */
|
||||
__IOM uint32_t MPSYC_WE : 1; /*!< [19..19] Write Enable of MPSYC */
|
||||
__IOM uint32_t MPCPG_WE : 1; /*!< [20..20] Write Enable of MPCPG */
|
||||
uint32_t : 1;
|
||||
__IOM uint32_t MHGPIO_WE : 1; /*!< [22..22] Write Enable of MHGPIO */
|
||||
__IOM uint32_t MPTZC0_WE : 1; /*!< [23..23] Write Enable of MPTZC0 */
|
||||
__IOM uint32_t MPTZC1_WE : 1; /*!< [24..24] Write Enable of MPTZC1 */
|
||||
__IOM uint32_t MPTZC2_WE : 1; /*!< [25..25] Write Enable of MPTZC2 */
|
||||
__IOM uint32_t MPTZC3_WE : 1; /*!< [26..26] Write Enable of MPTZC3 */
|
||||
__IOM uint32_t MPSRAM_A_WE : 1; /*!< [27..27] Write Enable of MPSRAM_A */
|
||||
__IOM uint32_t MPSRAM_M_WE : 1; /*!< [28..28] Write Enable of MPSRAM_M */
|
||||
__IOM uint32_t MPIA55_WE : 1; /*!< [29..29] Write Enable of MPIA55 */
|
||||
__IOM uint32_t MPIM33_WE : 1; /*!< [30..30] Write Enable of MPIM33 */
|
||||
__IOM uint32_t MXREG0_WE : 1; /*!< [31..31] Write Enable of MXREG0 */
|
||||
} PERI_CPU_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t PERI_DDR; /*!< (@ 0x41010B74) PERI_DDR Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MPPHY : 1; /*!< [ 0.. 0] Module Stop of MPPHY */
|
||||
__IOM uint32_t MXMEMC_REG : 1; /*!< [ 1.. 1] Module Stop of MXMEMC_REG */
|
||||
uint32_t : 14;
|
||||
__IOM uint32_t MPPHY_WE : 1; /*!< [16..16] Write Enable of MPPHY */
|
||||
__IOM uint32_t MXMEMC_REG_WE : 1; /*!< [17..17] Write Enable of MXMEMC_REG */
|
||||
uint32_t : 14;
|
||||
} PERI_DDR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t PERI_VIDEO; /*!< (@ 0x41010B78) PERI_VIDEO Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MPVCP4L_V : 1; /*!< [ 0.. 0] Module Stop of MPVCP4L_V */
|
||||
__IOM uint32_t MPVCP4L_C : 1; /*!< [ 1.. 1] Module Stop of MPVCP4L_C */
|
||||
__IOM uint32_t MPFCPCS : 1; /*!< [ 2.. 2] Module Stop of MPFCPCS */
|
||||
__IOM uint32_t MPCRU : 1; /*!< [ 3.. 3] Module Stop of MPCRU */
|
||||
__IOM uint32_t MPISU : 1; /*!< [ 4.. 4] Module Stop of MPISU */
|
||||
__IOM uint32_t MPDSIPHY : 1; /*!< [ 5.. 5] Module Stop of MPDSIPHY */
|
||||
__IOM uint32_t MPDSIL : 1; /*!< [ 6.. 6] Module Stop of MPDSIL */
|
||||
__IOM uint32_t MPVSPD : 1; /*!< [ 7.. 7] Module Stop of MPVSPD */
|
||||
__IOM uint32_t MPCPVD : 1; /*!< [ 8.. 8] Module Stop of MPCPVD */
|
||||
__IOM uint32_t MPDU : 1; /*!< [ 9.. 9] Module Stop of MPDU */
|
||||
__IOM uint32_t MXVIDEO : 1; /*!< [10..10] Module Stop of MXVIDEO */
|
||||
uint32_t : 5;
|
||||
__IOM uint32_t MPVCP4L_V_WE : 1; /*!< [16..16] Write Enable of MPVCP4L_V */
|
||||
__IOM uint32_t MPVCP4L_C_WE : 1; /*!< [17..17] Write Enable of MPVCP4L_C */
|
||||
__IOM uint32_t MPFCPCS_WE : 1; /*!< [18..18] Write Enable of MPFCPCS */
|
||||
__IOM uint32_t MPCRU_WE : 1; /*!< [19..19] Write Enable of MPCRU */
|
||||
__IOM uint32_t MPISU_WE : 1; /*!< [20..20] Write Enable of MPISU */
|
||||
__IOM uint32_t MPDSIPHY_WE : 1; /*!< [21..21] Write Enable of MPDSIPHY */
|
||||
__IOM uint32_t MPDSIL_WE : 1; /*!< [22..22] Write Enable of MPDSIL */
|
||||
__IOM uint32_t MPVSPD_WE : 1; /*!< [23..23] Write Enable of MPVSPD */
|
||||
__IOM uint32_t MPCPVD_WE : 1; /*!< [24..24] Write Enable of MPCPVD */
|
||||
__IOM uint32_t MPDU_WE : 1; /*!< [25..25] Write Enable of MPDU */
|
||||
__IOM uint32_t MXVIDEO_WE : 1; /*!< [26..26] Write Enable of MXVIDEO */
|
||||
uint32_t : 5;
|
||||
} PERI_VIDEO_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t REG0; /*!< (@ 0x41010B7C) REG0 Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MPWDT3 : 1; /*!< [ 0.. 0] Module Stop of MPWDT3 */
|
||||
__IOM uint32_t MPWDT2 : 1; /*!< [ 1.. 1] Module Stop of MPWDT2 */
|
||||
__IOM uint32_t MPWDT0 : 1; /*!< [ 2.. 2] Module Stop of MPWDT0 */
|
||||
__IOM uint32_t MPWDT1 : 1; /*!< [ 3.. 3] Module Stop of MPWDT1 */
|
||||
__IOM uint32_t MPOSTM0 : 1; /*!< [ 4.. 4] Module Stop of MPOSTM0 */
|
||||
__IOM uint32_t MPOSTM1 : 1; /*!< [ 5.. 5] Module Stop of MPOSTM1 */
|
||||
__IOM uint32_t MPOSTM2 : 1; /*!< [ 6.. 6] Module Stop of MPOSTM2 */
|
||||
uint32_t : 9;
|
||||
__IOM uint32_t MPWDT3_WE : 1; /*!< [16..16] Write Enable of MPWDT3 */
|
||||
__IOM uint32_t MPWDT2_WE : 1; /*!< [17..17] Write Enable of MPWDT2 */
|
||||
__IOM uint32_t MPWDT0_WE : 1; /*!< [18..18] Write Enable of MPWDT0 */
|
||||
__IOM uint32_t MPWDT1_WE : 1; /*!< [19..19] Write Enable of MPWDT1 */
|
||||
__IOM uint32_t MPOSTM0_WE : 1; /*!< [20..20] Write Enable of MPOSTM0 */
|
||||
__IOM uint32_t MPOSTM1_WE : 1; /*!< [21..21] Write Enable of MPOSTM1 */
|
||||
__IOM uint32_t MPOSTM2_WE : 1; /*!< [22..22] Write Enable of MPOSTM2 */
|
||||
uint32_t : 9;
|
||||
} REG0_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t REG1; /*!< (@ 0x41010B80) REG1 Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MXDMAC_S : 1; /*!< [ 0.. 0] Module Stop of MXDMAC_S */
|
||||
__IOM uint32_t MPDMAC_S : 1; /*!< [ 1.. 1] Module Stop of MPDMAC_S */
|
||||
__IOM uint32_t MXDMAC_NS : 1; /*!< [ 2.. 2] Module Stop of MXDMAC_NS */
|
||||
__IOM uint32_t MPDMAC_NS : 1; /*!< [ 3.. 3] Module Stop of MPDMAC_NS */
|
||||
__IOM uint32_t MXMALI : 1; /*!< [ 4.. 4] Module Stop of MXMALI */
|
||||
__IOM uint32_t MHTSIPG : 1; /*!< [ 5.. 5] Module Stop of MHTSIPG */
|
||||
__IOM uint32_t MHTSIPG_OTP : 1; /*!< [ 6.. 6] Module Stop of MHTSIPG_OTP */
|
||||
__IOM uint32_t MXGIC : 1; /*!< [ 7.. 7] Module Stop of MXGIC */
|
||||
uint32_t : 8;
|
||||
__IOM uint32_t MXDMAC_S_WE : 1; /*!< [16..16] Write Enable of MXDMAC_S */
|
||||
__IOM uint32_t MPDMAC_S_WE : 1; /*!< [17..17] Write Enable of MPDMAC_S */
|
||||
__IOM uint32_t MXDMAC_NS_WE : 1; /*!< [18..18] Write Enable of MXDMAC_NS */
|
||||
__IOM uint32_t MPDMAC_NS_WE : 1; /*!< [19..19] Write Enable of MPDMAC_NS */
|
||||
__IOM uint32_t MXMALI_WE : 1; /*!< [20..20] Write Enable of MXMALI */
|
||||
__IOM uint32_t MHTSIPG_WE : 1; /*!< [21..21] Write Enable of MHTSIPG */
|
||||
__IOM uint32_t MHTSIPG_OTP_WE : 1; /*!< [22..22] Write Enable of MHTSIPG_OTP */
|
||||
__IOM uint32_t MXGIC_WE : 1; /*!< [23..23] Write Enable of MXGIC */
|
||||
uint32_t : 8;
|
||||
} REG1_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t TZCDDR; /*!< (@ 0x41010B84) TZCDDR Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MSTOP0 : 1; /*!< [ 0.. 0] Module Stop of MSTOP0 */
|
||||
__IOM uint32_t MSTOP1 : 1; /*!< [ 1.. 1] Module Stop of MSTOP1 */
|
||||
__IOM uint32_t MSTOP2 : 1; /*!< [ 2.. 2] Module Stop of MSTOP2 */
|
||||
__IOM uint32_t MSTOP3 : 1; /*!< [ 3.. 3] Module Stop of MSTOP3 */
|
||||
uint32_t : 12;
|
||||
__IOM uint32_t MSTOP0_WE : 1; /*!< [16..16] Write Enable of MSTOP0 */
|
||||
__IOM uint32_t MSTOP1_WE : 1; /*!< [17..17] Write Enable of MSTOP1 */
|
||||
__IOM uint32_t MSTOP2_WE : 1; /*!< [18..18] Write Enable of MSTOP2 */
|
||||
__IOM uint32_t MSTOP3_WE : 1; /*!< [19..19] Write Enable of MSTOP3 */
|
||||
uint32_t : 12;
|
||||
} TZCDDR_b;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
__IOM uint32_t MHU; /*!< (@ 0x41010B88) MHU Register */
|
||||
|
||||
struct
|
||||
{
|
||||
__IOM uint32_t MSTOP : 1; /*!< [ 0.. 0] Module Stop of MSTOP */
|
||||
uint32_t : 15;
|
||||
__IOM uint32_t MSTOP_WE : 1; /*!< [16..16] Write Enable of MSTOP_A */
|
||||
uint32_t : 15;
|
||||
} MHU_b;
|
||||
};
|
||||
} R_MSTOP_Type; /*!< Size = 44 (0x2C) */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Device Specific Peripheral Address Map ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_MSTP_BASE 0x41010B60 /* Module Stop Control */
|
||||
|
||||
/* ================================================================================================================= */
|
||||
/* ================ Peripheral declaration ====== */
|
||||
/* ================================================================================================================= */
|
||||
|
||||
#define R_MSTP ((R_MSTOP_Type *) R_MSTP_BASE)
|
||||
|
||||
#endif /* MSTP_IODEFINE_H */
|
||||
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Reference in New Issue