diff --git a/.gitmodules b/.gitmodules index 3b619568a..24e876903 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,12 +4,12 @@ [submodule "Ubiquitous/RT_Thread/aiit_board/k210/kendryte-sdk/kendryte-sdk-source"] path = Ubiquitous/RT_Thread/aiit_board/k210/kendryte-sdk/kendryte-sdk-source url = https://code.gitlink.org.cn/chunyexixiaoyu/kendryte-sdk-source.git -[submodule "Ubiquitous/Nuttx/apps"] - path = Ubiquitous/Nuttx/apps - url = https://gitlink.org.cn/wgzAIIT/incubator-nuttx-apps.git -[submodule "Ubiquitous/Nuttx/nuttx"] - path = Ubiquitous/Nuttx/nuttx - url = https://gitlink.org.cn/wgzAIIT/incubator-nuttx.git [submodule "Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source"] path = Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source url = https://code.gitlink.org.cn/chunyexixiaoyu/kendryte-sdk-source.git +[submodule "Ubiquitous/Nuttx_Fusion_XiUOS/apps"] + path = Ubiquitous/Nuttx_Fusion_XiUOS/apps + url = https://code.gitlink.org.cn/wgzAIIT/incubator-nuttx-apps.git +[submodule "Ubiquitous/Nuttx_Fusion_XiUOS/nuttx"] + path = Ubiquitous/Nuttx_Fusion_XiUOS/nuttx + url = https://code.gitlink.org.cn/wgzAIIT/incubator-nuttx.git diff --git a/APP_Framework/Applications/app_test/test_spi_flash.c b/APP_Framework/Applications/app_test/test_spi_flash.c index a4248402c..3a4a0651e 100644 --- a/APP_Framework/Applications/app_test/test_spi_flash.c +++ b/APP_Framework/Applications/app_test/test_spi_flash.c @@ -1,21 +1,7 @@ /* - * File : spi_flash_sfud.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/APP_Framework/Applications/sensor_app/Makefile b/APP_Framework/Applications/sensor_app/Makefile index 54daa1592..76fd4e16c 100644 --- a/APP_Framework/Applications/sensor_app/Makefile +++ b/APP_Framework/Applications/sensor_app/Makefile @@ -47,6 +47,14 @@ ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) CSRCS += temperature_hs300x.c endif + ifeq ($(CONFIG_APPLICATION_SENSOR_WINDDIRECTION_QS_FX), y) + CSRCS += winddirection_qs_fx.c + endif + + ifeq ($(CONFIG_APPLICATION_SENSOR_WINDSPEED_QS_FS), y) + CSRCS += windspeed_qs_fs.c + endif + include $(APPDIR)/Application.mk endif diff --git a/APP_Framework/Applications/sensor_app/SConscript b/APP_Framework/Applications/sensor_app/SConscript index 58ec915b4..d526a7b38 100644 --- a/APP_Framework/Applications/sensor_app/SConscript +++ b/APP_Framework/Applications/sensor_app/SConscript @@ -15,6 +15,10 @@ if GetDepend(['APPLICATION_SENSOR_HUMIDITY_HS300X']): SOURCES = ['humidity_hs300x.c'] + SOURCES if GetDepend(['APPLICATION_SENSOR_TEMPERATURE_HS300X']): SOURCES = ['temperature_hs300x.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_CH4_AS830']): + SOURCES = ['ch4_as830.c'] + SOURCES +if GetDepend(['APPLICATION_SENSOR_HCHO']): + SOURCES = ['hcho_tb600b_wq_hcho1os.c'] + SOURCES path = [cwd] objs = DefineGroup('sensor_app', src = SOURCES, depend = DEPENDS,CPPPATH = path) Return("objs") \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c b/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c index 455b64ec1..d5032718b 100644 --- a/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c +++ b/APP_Framework/Applications/sensor_app/winddirection_qs_fx.c @@ -34,5 +34,7 @@ void WindDirectionQsFx(void) printf("wind direction : %d degree\n", result); SensorQuantityClose(wind_direction); } +#ifdef ADD_XIZI_FETURES SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, WindDirectionQsFx, WindDirectionQsFx, WindDirectionQsFx function); +#endif diff --git a/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c b/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c index 006296aac..72b91db6e 100644 --- a/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c +++ b/APP_Framework/Applications/sensor_app/windspeed_qs_fs.c @@ -34,5 +34,7 @@ void WindSpeedQsFs(void) printf("wind speed : %d.%d m/s\n", result/10, result%10); SensorQuantityClose(wind_speed); } +#ifdef ADD_XIZI_FETURES SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, WindSpeedQsFs, WindSpeedQsFs, WindSpeedQsFs function); +#endif diff --git a/APP_Framework/Framework/sensor/ch4/Kconfig b/APP_Framework/Framework/sensor/ch4/Kconfig index 85b5099cd..63011de1d 100644 --- a/APP_Framework/Framework/sensor/ch4/Kconfig +++ b/APP_Framework/Framework/sensor/ch4/Kconfig @@ -43,6 +43,23 @@ config SENSOR_AS830 endif if ADD_RTTHREAD_FETURES + config SENSOR_AS830_DRIVER_EXTUART + bool "Using extra uart to support as830" + default y + config SENSOR_DEVICE_AS830_DEV + string "as830 device uart path" + default "/dev/uart2" + depends on !SENSOR_AS830_DRIVER_EXTUART + + if SENSOR_AS830_DRIVER_EXTUART + config SENSOR_DEVICE_AS830_DEV + string "as830 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_AS830_DEV_EXT_PORT + int "if AS830 device using extuart, choose port" + default "4" + endif endif endif diff --git a/APP_Framework/Framework/sensor/ch4/SConscript b/APP_Framework/Framework/sensor/ch4/SConscript new file mode 100644 index 000000000..f307e3f70 --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/ch4/as830/SConscript b/APP_Framework/Framework/sensor/ch4/as830/SConscript new file mode 100644 index 000000000..1e361eddf --- /dev/null +++ b/APP_Framework/Framework/sensor/ch4/as830/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_AS830']): + src += ['as830.c'] +group = DefineGroup('sensor ch4 as830', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/co2/Kconfig b/APP_Framework/Framework/sensor/co2/Kconfig index da5581985..e4c4c430f 100644 --- a/APP_Framework/Framework/sensor/co2/Kconfig +++ b/APP_Framework/Framework/sensor/co2/Kconfig @@ -43,7 +43,24 @@ config SENSOR_ZG09 endif if ADD_RTTHREAD_FETURES + config SENSOR_ZG09_DRIVER_EXTUART + bool "Using extra uart to support zg09" + default y + config SENSOR_DEVICE_ZG09_DEV + string "zg09 device uart path" + default "/dev/uart2_dev2" + depends on !SENSOR_ZG09_DRIVER_EXTUART + + if SENSOR_ZG09_DRIVER_EXTUART + config SENSOR_DEVICE_ZG09_DEV + string "zg09 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_ZG09_DEV_EXT_PORT + int "if ZG09 device using extuart, choose port" + default "4" + endif endif endif diff --git a/APP_Framework/Framework/sensor/co2/zg09/SConscript b/APP_Framework/Framework/sensor/co2/zg09/SConscript new file mode 100644 index 000000000..084f10122 --- /dev/null +++ b/APP_Framework/Framework/sensor/co2/zg09/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_ZG09']): + src += ['zg09.c'] +group = DefineGroup('sensor co2 zg09', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/hcho/Kconfig b/APP_Framework/Framework/sensor/hcho/Kconfig index 07bd8168e..cd87003b6 100644 --- a/APP_Framework/Framework/sensor/hcho/Kconfig +++ b/APP_Framework/Framework/sensor/hcho/Kconfig @@ -43,6 +43,23 @@ config SENSOR_TB600B_WQ_HCHO1OS endif if ADD_RTTHREAD_FETURES + config SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + bool "Using extra uart to support tb600b wq_hcho1os" + default y + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device uart path" + default "/dev/uart2" + depends on !SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + + if SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV + string "tb600b wq_hcho1os device extra uart path" + default "/dev/extuart_dev1" + + config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT + int "if TB600B_WQ_HCHO1OS device using extuart, choose port" + default "1" + endif endif endif diff --git a/APP_Framework/Framework/sensor/hcho/SConscript b/APP_Framework/Framework/sensor/hcho/SConscript new file mode 100644 index 000000000..f307e3f70 --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/SConscript @@ -0,0 +1,14 @@ +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript new file mode 100644 index 000000000..e8f068b84 --- /dev/null +++ b/APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = [] +if GetDepend(['SENSOR_TB600B_WQ_HCHO1OS']): + src += ['tb600b_wq_hcho1os.c'] +group = DefineGroup('sensor hcho', src, depend = [], CPPPATH = [cwd]) + +Return('group') \ No newline at end of file diff --git a/APP_Framework/Framework/sensor/voice/Kconfig b/APP_Framework/Framework/sensor/voice/Kconfig index bad0d4602..87a8c213f 100644 --- a/APP_Framework/Framework/sensor/voice/Kconfig +++ b/APP_Framework/Framework/sensor/voice/Kconfig @@ -43,6 +43,23 @@ config SENSOR_D124 endif if ADD_RTTHREAD_FETURES + config SENSOR_D124_DRIVER_EXTUART + bool "Using extra uart to support D124" + default y + config SENSOR_DEVICE_D124_DEV + string "D124 device name" + default "/dev/uart2_dev2" + depends on !SENSOR_D124_DRIVER_EXTUART + + if SENSOR_D124_DRIVER_EXTUART + config SENSOR_DEVICE_D124_DEV + string "D124 device extra uart path" + default "/dev/extuart_dev4" + + config SENSOR_DEVICE_D124_DEV_EXT_PORT + int "if D124 device using extuart, choose port" + default "4" + endif endif endif diff --git a/APP_Framework/Framework/sensor/winddirection/Kconfig b/APP_Framework/Framework/sensor/winddirection/Kconfig index 94b2385f0..726bfea8a 100644 --- a/APP_Framework/Framework/sensor/winddirection/Kconfig +++ b/APP_Framework/Framework/sensor/winddirection/Kconfig @@ -34,6 +34,11 @@ config SENSOR_QS_FX endif if ADD_NUTTX_FETURES + config SENSOR_DEVICE_QS_FX_DEV + string "qs-fx device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. endif diff --git a/APP_Framework/Framework/sensor/winddirection/Make.defs b/APP_Framework/Framework/sensor/winddirection/Make.defs new file mode 100644 index 000000000..75fed1c91 --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/winddirection/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/winddirection/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs b/APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs new file mode 100644 index 000000000..8d9518b2d --- /dev/null +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/winddirection/qs-fx/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_QS_FX),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/winddirection/qs-fx +endif diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile b/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile index 4752b388f..e45522588 100644 --- a/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/Makefile @@ -1,3 +1,11 @@ -SRC_FILES := qs-fx.c +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += qs-fx.c + include $(APPDIR)/Application.mk +endif -include $(KERNEL_ROOT)/compiler.mk +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := qs-fx.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c b/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c index 6f3c7ad13..24a6cb726 100644 --- a/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c +++ b/APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c @@ -35,6 +35,18 @@ static struct SensorProductInfo info = * @param sdev - sensor device pointer * @return success: 1 , failure: other */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_QS_FX_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_QS_FX_DEV); + return -1; + } + + return sdev->fd ; +} +#else static int SensorDeviceOpen(struct SensorDevice *sdev) { int result = 0; @@ -64,7 +76,8 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); return result; -} +} +#endif /** * @description: Read sensor device diff --git a/APP_Framework/Framework/sensor/windspeed/Kconfig b/APP_Framework/Framework/sensor/windspeed/Kconfig index 8db034a35..91bc1fb92 100644 --- a/APP_Framework/Framework/sensor/windspeed/Kconfig +++ b/APP_Framework/Framework/sensor/windspeed/Kconfig @@ -34,6 +34,11 @@ config SENSOR_QS_FS endif if ADD_NUTTX_FETURES + config SENSOR_DEVICE_QS_FS_DEV + string "qs-fx device name" + default "/dev/ttyS1" + ---help--- + If USART1 is selected, then fill in /dev/ttyS1 here. endif diff --git a/APP_Framework/Framework/sensor/windspeed/Make.defs b/APP_Framework/Framework/sensor/windspeed/Make.defs new file mode 100644 index 000000000..ae9715416 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/Make.defs @@ -0,0 +1,4 @@ +############################################################################ +# APP_Framework/Framework/sensor/windspeed/Make.defs +############################################################################ +include $(wildcard $(APPDIR)/../../../APP_Framework/Framework/sensor/windspeed/*/Make.defs) diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs b/APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs new file mode 100644 index 000000000..8edbfb6f7 --- /dev/null +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs @@ -0,0 +1,6 @@ +############################################################################ +# APP_Framework/Framework/sensor/windspeed/qs-fs/Make.defs +############################################################################ +ifneq ($(CONFIG_SENSOR_QS_FS),) +CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/sensor/windspeed/qs-fs +endif diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile b/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile index 32a4000d0..a6872570e 100644 --- a/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/Makefile @@ -1,3 +1,11 @@ -SRC_FILES := qs-fs.c +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += qs-fs.c + include $(APPDIR)/Application.mk +endif -include $(KERNEL_ROOT)/compiler.mk +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) + SRC_FILES := qs-fs.c + include $(KERNEL_ROOT)/compiler.mk +endif diff --git a/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c b/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c index 6478fd2c9..427fa8273 100644 --- a/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c +++ b/APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c @@ -35,6 +35,17 @@ static struct SensorProductInfo info = * @param sdev - sensor device pointer * @return success: 1 , failure: other */ +#ifdef ADD_NUTTX_FETURES +static int SensorDeviceOpen(struct SensorDevice *sdev) +{ + sdev->fd = PrivOpen(SENSOR_DEVICE_QS_FS_DEV, O_RDWR); + if (sdev->fd < 0) { + printf("open %s error\n", SENSOR_DEVICE_QS_FS_DEV); + return -1; + } + return sdev->fd; +} +#else static int SensorDeviceOpen(struct SensorDevice *sdev) { int result = 0; @@ -65,6 +76,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) return result; } +#endif /** * @description: Read sensor device diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/Kconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/Kconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/README.txt b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/README.txt similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/README.txt rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/README.txt diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/adb/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/adb/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/adb/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/adb/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/audio/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/audio/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/audio/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/audio/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/canard/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/canard/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/canard/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/canard/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/cxxtest/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/cxxtest/Make.defs similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/cxxtest/Make.defs rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/cxxtest/Make.defs diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/cxxtest/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/cxxtest/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/cxxtest/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/cxxtest/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/elf/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/elf/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/elf/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/elf/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/ipv6/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/ipv6/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/ipv6/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/ipv6/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/kostest/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/kostest/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/kostest/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/kostest/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/lcd1602/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/lcd1602/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/lcd1602/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/lcd1602/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/lwl/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/lwl/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/lwl/defconfig rename to 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a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/netnsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/netnsh/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/netnsh/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/netnsh/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/nsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/nsh/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/nsh/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/nsh/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/nxlines/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/nxlines/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/nxlines/defconfig rename to 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a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/sporadic/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/sporadic/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/sporadic/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/sporadic/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/st7789/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/st7789/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/st7789/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/st7789/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/configs/testlibcxx/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/configs/testlibcxx/Make.defs similarity index 100% rename from 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rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/include/board.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/include/board.h diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/kernel/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/kernel/Makefile similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/kernel/Makefile rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/kernel/Makefile diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/kernel/stm32_userspace.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/kernel/stm32_userspace.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/kernel/stm32_userspace.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/kernel/stm32_userspace.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/Make.defs 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a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/ld.script b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/scripts/ld.script similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/ld.script rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/scripts/ld.script diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/memory.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/scripts/memory.ld similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/memory.ld rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/scripts/memory.ld diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/user-space.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/scripts/user-space.ld similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/scripts/user-space.ld rename to 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similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_bringup.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_bringup.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_buttons.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_buttons.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_buttons.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_buttons.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_can.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_can.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_can.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_can.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_critmon.c 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a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_enc28j60.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_enc28j60.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_enc28j60.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_enc28j60.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_ethernet.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_ethernet.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_ethernet.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_ethernet.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_extmem.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_extmem.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_extmem.c rename to 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a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_ug2864ambag01.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_ug2864ambag01.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_ug2864ambag01.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_ug2864ambag01.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_ug2864hsweg01.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_ug2864hsweg01.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_ug2864hsweg01.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_ug2864hsweg01.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_uid.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-arm32-board/src/stm32_uid.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-arm32-board/src/stm32_uid.c rename to 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b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/configs/smp/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/configs/smp/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/configs/smp/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/configs/smp2/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/configs/smp2/defconfig similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/configs/smp2/defconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/configs/smp2/defconfig diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/include/board.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/include/board.h similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/include/board.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/include/board.h diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/kernel/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kernel/Makefile similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/kernel/Makefile rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kernel/Makefile diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/kernel/k210_userspace.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kernel/k210_userspace.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/kernel/k210_userspace.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kernel/k210_userspace.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/Make.defs similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/Make.defs rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/Make.defs diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/gnu-elf.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/gnu-elf.ld similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/gnu-elf.ld rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/gnu-elf.ld diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/ld.script b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/ld.script similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/ld.script rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/ld.script diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/memory.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/memory.ld similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/memory.ld rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/memory.ld diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/user-space.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/user-space.ld similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/scripts/user-space.ld rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/scripts/user-space.ld diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/Makefile similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/Makefile rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/Makefile diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/aiit-riscv64-board.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/aiit-riscv64-board.h similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/aiit-riscv64-board.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/aiit-riscv64-board.h diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_appinit.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_appinit.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_appinit.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_appinit.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_boot.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_boot.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_boot.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_boot.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_bringup.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_bringup.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_bringup.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_bringup.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_gpio.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_gpio.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_gpio.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_gpio.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_leds.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_leds.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_leds.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_leds.c diff --git a/Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_ostest.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_ostest.c similarity index 100% rename from Ubiquitous/Nuttx/aiit_board/aiit-riscv64-board/src/k210_ostest.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/aiit-riscv64-board/src/k210_ostest.c diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/Kconfig new file mode 100644 index 000000000..27b484b4c --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/Kconfig @@ -0,0 +1,27 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_XIDATONG + +choice + prompt "Boot Flash" + default XIDATONG_QSPI_FLASH + +config XIDATONG_HYPER_FLASH + bool "HYPER Flash" + +config XIDATONG_QSPI_FLASH + bool "QSPI Flash" + +endchoice # Boot Flash + +config XIDATONG_SDRAM + bool "Enable SDRAM" + default y + select IMXRT_SEMC_INIT_DONE + ---help--- + Activate DCD configuration of SDRAM + +endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/Make.defs new file mode 100644 index 000000000..3b7371cf7 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/Make.defs @@ -0,0 +1,74 @@ +############################################################################ +# boards/arm/imxrt/xidatong/configs/knsh/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT1 = memory.ld +LDSCRIPT2 = kernel-space.ld + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1)}" + ARCHSCRIPT += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) + ARCHSCRIPT += -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/defconfig new file mode 100644 index 000000000..e0cd4e51b --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/knsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_RAMFUNCS is not set +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xidatong" +CONFIG_ARCH_BOARD_XIDATONG=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y +CONFIG_ARCH_INTERRUPTSTACK=10240 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_LAZYFPU=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_ARM_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILD_PROTECTED=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x60200000 +CONFIG_PASS1_BUILDIR="boards/arm/imxrt/xidatong/kernel" +CONFIG_RAM_SIZE=524288 +CONFIG_RAM_START=0x20200000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=8 +CONFIG_START_MONTH=6 +CONFIG_SYSTEM_NSH=y +CONFIG_SYS_RESERVED=9 +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/Make.defs new file mode 100644 index 000000000..8d5a217a8 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/Make.defs @@ -0,0 +1,85 @@ +############################################################################ +# boards/arm/imxrt/xidatong/configs/libcxxtest/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARMV7M_DTCM),y) + LDSCRIPT = flash-dtcm.ld +else + LDSCRIPT = flash-ocram.ld +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing \ + -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ifeq ($(CONFIG_CXX_EXCEPTION),y) + ARCHCPUFLAGSXX = -fno-builtin +else + ARCHCPUFLAGSXX = -fno-builtin -fno-exceptions -fcheck-new +endif +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef #-fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) +CXXFLAGS += $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -std=c++11 +CXXFLAGS += -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +CXXFLAGS += -pedantic -D_DEBUG -D_LIBCPP_BUILD_STATIC -D_LIBCPP_NO_EXCEPTIONS +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/defconfig new file mode 100644 index 000000000..a38942cd3 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/libcxxtest/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xidatong" +CONFIG_ARCH_BOARD_XIDATONG=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y +CONFIG_ARCH_INTERRUPTSTACK=10240 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=20000 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_C99_BOOL8=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LIBM=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=536870912 +CONFIG_RAM_START=0x20200000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CPULOAD=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/netnsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/netnsh/defconfig new file mode 100644 index 000000000..974ab7dd8 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/netnsh/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xidatong" +CONFIG_ARCH_BOARD_XIDATONG=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y +CONFIG_ARCH_INTERRUPTSTACK=10240 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_ETH0_PHY_KSZ8081=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_ENET=y +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="i.MXRT1050 EVK" +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NET=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=524288 +CONFIG_RAM_START=0x20200000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_SYSTEM_PING=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/nsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/nsh/defconfig new file mode 100644 index 000000000..78b8bbd2d --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/nsh/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xidatong" +CONFIG_ARCH_BOARD_XIDATONG=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y +CONFIG_ARCH_INTERRUPTSTACK=10240 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=524288 +CONFIG_RAM_START=0x20200000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usdhc/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usdhc/defconfig new file mode 100644 index 000000000..c22671e64 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usdhc/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xidatong" +CONFIG_ARCH_BOARD_XIDATONG=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y +CONFIG_ARCH_INTERRUPTSTACK=10240 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_ZERO=y +CONFIG_FAT_LCNAMES=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_EXAMPLES_HELLO=y +CONFIG_IMXRT1020_EVK_QSPI_FLASH=y +CONFIG_IMXRT_GPIO1_0_15_IRQ=y +CONFIG_IMXRT_GPIO_IRQ=y +CONFIG_IMXRT_LPUART1=y +CONFIG_IMXRT_USDHC1=y +CONFIG_IMXRT_USDHC1_WIDTH_D1_D4=y +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_NCHAINS=8 +CONFIG_LIBC_STRERROR=y +CONFIG_LPUART1_RXBUFSIZE=1024 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXBUFSIZE=1024 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_IOB=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CMDOPT_DD_STATS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=524288 +CONFIG_RAM_START=0x20200000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_CLE_CMD_HISTORY=y +CONFIG_SYSTEM_COLOR_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/NXPBootUtility_1.png b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/NXPBootUtility_1.png new file mode 100644 index 000000000..939f60f23 Binary files /dev/null and b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/NXPBootUtility_1.png differ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/NXPBootUtility_2.png b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/NXPBootUtility_2.png new file mode 100644 index 000000000..df8610a7a Binary files /dev/null and b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/NXPBootUtility_2.png differ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/flashconfig.png b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/img/flashconfig.png new file mode 100644 index 000000000..9db4bd312 Binary files /dev/null and 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+/**************************************************************************** + * boards/arm/imxrt/xidatong/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file board.h +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +#ifndef __BOARDS_ARM_IMXRT_XIDATONG_INCLUDE_BOARD_H +#define __BOARDS_ARM_IMXRT_XIDATONG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Do not include i.MXRT header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Set VDD_SOC to 1.25V */ + +#define IMXRT_VDD_SOC (0x12) + +/* Set Arm PLL (PLL1) to fOut = (24Mhz * ARM_PLL_DIV_SELECT/2) / + * ARM_PODF_DIVISOR + * 600Mhz = (24Mhz * ARM_PLL_DIV_SELECT/2) / + * ARM_PODF_DIVISOR + * ARM_PLL_DIV_SELECT = 100 + * ARM_PODF_DIVISOR = 2 + * 600Mhz = (24Mhz * 100/2) / 2 + * + * AHB_CLOCK_ROOT = PLL1fOut / IMXRT_AHB_PODF_DIVIDER + * 1Hz to 600 MHz = 600Mhz / IMXRT_ARM_CLOCK_DIVIDER + * IMXRT_ARM_CLOCK_DIVIDER = 1 + * 600Mhz = 600Mhz / 1 + * + * PRE_PERIPH_CLK_SEL = PRE_PERIPH_CLK_SEL_PLL1 + * PERIPH_CLK_SEL = 1 (0 select PERIPH_CLK2_PODF, + * 1 select PRE_PERIPH_CLK_SEL_PLL1) + * PERIPH_CLK = 600Mhz + * + * IPG_CLOCK_ROOT = AHB_CLOCK_ROOT / IMXRT_IPG_PODF_DIVIDER + * IMXRT_IPG_PODF_DIVIDER = 4 + * 150Mhz = 600Mhz / 4 + * + * PERCLK_CLOCK_ROOT = IPG_CLOCK_ROOT / + * IMXRT_PERCLK_PODF_DIVIDER + * IMXRT_PERCLK_PODF_DIVIDER = 9 + * 16.6Mhz = 150Mhz / 9 + * + * SEMC_CLK_ROOT = 600Mhz / IMXRT_SEMC_PODF_DIVIDER + * (labeled AIX_PODF in 18.2) + * IMXRT_SEMC_PODF_DIVIDER = 8 + * 75Mhz = 600Mhz / 8 + * + * Set Sys PLL (PLL2) to fOut = (24Mhz * (20+(2*(DIV_SELECT))) + * 528Mhz = (24Mhz * (20+(2*(1))) + * + * Set USB1 PLL (PLL3) to fOut = (24Mhz * 20) + * 480Mhz = (24Mhz * 20) + * + * Set LPSPI PLL3 PFD0 to fOut = (480Mhz / 12 * 18) + * 720Mhz = (480Mhz / 12 * 18) + * 90Mhz = (720Mhz / LSPI_PODF_DIVIDER) + * + * Set LPI2C PLL3 / 8 to fOut = (480Mhz / 8) + * 60Mhz = (480Mhz / 8) + * 12Mhz = (60Mhz / LSPI_PODF_DIVIDER) + * + * These clock frequencies can be verified via the CCM_CLKO1 pin and sending + * the appropriate clock to it with something like; + * + * putreg32( | CCM_CCOSR_CLKO1_EN , IMXRT_CCM_CCOSR); + * imxrt_config_gpio(GPIO_CCM_CLKO1); + */ + +#define BOARD_XTAL_FREQUENCY 24000000 +#define BOARD_CPU_FREQUENCY 528000000 + +#define IMXRT_PRE_PERIPH_CLK_SEL CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 +#define IMXRT_PERIPH_CLK_SEL CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH +#define IMXRT_ARM_PLL_DIV_SELECT 100 +#define IMXRT_ARM_PODF_DIVIDER 2 +#define IMXRT_AHB_PODF_DIVIDER 1 +#define IMXRT_IPG_PODF_DIVIDER 4 +#define IMXRT_PERCLK_CLK_SEL CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT +#define IMXRT_PERCLK_PODF_DIVIDER 9 +#define IMXRT_SEMC_PODF_DIVIDER 8 +#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 +#define IMXRT_LSPI_PODF_DIVIDER 8 + +#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 +#define IMXRT_LSPI_PODF_DIVIDER 8 + +#define IMXRT_LPI2C_CLK_SELECT CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M +#define IMXRT_LSI2C_PODF_DIVIDER 5 + +#define IMXRT_USDHC1_CLK_SELECT CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 +#define IMXRT_USDHC1_PODF_DIVIDER 2 + +#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22 + +#define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20 + +// #define BOARD_CPU_FREQUENCY \ +// (BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER + +/* Define this to enable tracing */ + +#if 0 +# define IMXRT_TRACE_PODF_DIVIDER 1 +# define IMXRT_TRACE_CLK_SELECT CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 +#endif + +/* LED definitions **********************************************************/ + +/* There are four LED status indicators located on the EVK Board. + * The functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_USERLED 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_USERLED_BIT (1 << BOARD_USERLED) + +/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/imxrt_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* Not used */ + +/* Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Button definitions *******************************************************/ + +/* The IMXRT board has one external user button + * + * 1. SW8 (IRQ88) GPIO5-00 + */ + +#define BUTTON_SW8 0 + +#define BUTTON_SW8_BIT (1 << BUTTON_SW8) + +/* SDIO *********************************************************************/ + +/* Pin drive characteristics - drive strength in particular may need tuning + * for specific boards, but has been checked by scope on the EVKB to make + * sure shapes are square with minimal ringing. + */ + + +#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_02 */ +#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_03 */ +#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_04 */ +#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_05 */ +#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT) /* GPIO_SD_B0_01 */ +#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT) /* GPIO_SD_B0_00 */ +//#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT) + +#define PIN_USDHC1_CD_GPIO (IOMUX_VSD_DEFAULT | GPIO_PORT2 | GPIO_PIN28) /* GPIO_B1_12 */ + +/* 386 KHz for initial inquiry stuff */ + +#define BOARD_USDHC_IDMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV256 +#define BOARD_USDHC_IDMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(2) + +/* 24.8MHz for other modes */ + +#define BOARD_USDHC_MMCMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_MMCMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +#define BOARD_USDHC_SD1MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_SD1MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +#define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +/* LCD **********************************************************************/ + +#ifdef CONFIG_IMXRT_LCD +/* LCD controller */ + +# define GPIO_LCD_DATA23 (GPIO_LCD_DATA23_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA22 (GPIO_LCD_DATA22_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA21 (GPIO_LCD_DATA21_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA20 (GPIO_LCD_DATA20_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA19 (GPIO_LCD_DATA19_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA18 (GPIO_LCD_DATA18_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA17 (GPIO_LCD_DATA17_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA16 (GPIO_LCD_DATA16_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA15 (GPIO_LCD_DATA15_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA14 (GPIO_LCD_DATA14_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA13 (GPIO_LCD_DATA13_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA12 (GPIO_LCD_DATA12_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA11 (GPIO_LCD_DATA11_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA10 (GPIO_LCD_DATA10_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA09 (GPIO_LCD_DATA09_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA08 (GPIO_LCD_DATA08_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA07 (GPIO_LCD_DATA07_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA06 (GPIO_LCD_DATA06_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA05 (GPIO_LCD_DATA05_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA04 (GPIO_LCD_DATA04_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA03 (GPIO_LCD_DATA03_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA02 (GPIO_LCD_DATA02_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA01 (GPIO_LCD_DATA01_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_DATA00 (GPIO_LCD_DATA00_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_ENABLE (GPIO_LCD_ENABLE_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_HSYNC (GPIO_LCD_HSYNC_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_VSYNC (GPIO_LCD_VSYNC_1 | IOMUX_LCD_DEFAULT) +# define GPIO_LCD_CLK (GPIO_LCD_CLK_1 | IOMUX_LCD_DEFAULT) +#endif + +/* ETH Disambiguation *******************************************************/ + +#define GPIO_ENET_TX_DATA00 (GPIO_ENET_TX_DATA00_1| \ + IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_07 */ +#define GPIO_ENET_TX_DATA01 (GPIO_ENET_TX_DATA01_1| \ + IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_08 */ +#define GPIO_ENET_RX_DATA00 (GPIO_ENET_RX_DATA00_1| \ + IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_04 */ +#define GPIO_ENET_RX_DATA01 (GPIO_ENET_RX_DATA01_1| \ + IOMUX_ENET_DATA_DEFAULT) /* GPIO_B1_05 */ +#define GPIO_ENET_MDIO (GPIO_ENET_MDIO_3|IOMUX_ENET_MDIO_DEFAULT) /* GPIO_EMC_41 */ +#define GPIO_ENET_MDC (GPIO_ENET_MDC_3|IOMUX_ENET_MDC_DEFAULT) /* GPIO_EMC_40 */ +#define GPIO_ENET_RX_EN (GPIO_ENET_RX_EN_1|IOMUX_ENET_EN_DEFAULT) /* GPIO_B1_06 */ +#define GPIO_ENET_RX_ER (GPIO_ENET_RX_ER_1|IOMUX_ENET_RXERR_DEFAULT) /* GPIO_B1_11 */ +#define GPIO_ENET_TX_CLK (GPIO_ENET_REF_CLK_2|\ + IOMUX_ENET_TX_CLK_DEFAULT) /* GPIO_B1_10 */ +#define GPIO_ENET_TX_EN (GPIO_ENET_TX_EN_1|IOMUX_ENET_EN_DEFAULT) /* GPIO_B1_09 */ + +/* PIO Disambiguation *******************************************************/ + +/* LPUARTs + * + * Virtual console port provided by OpenSDA on UART1. + * + */ + +/* LPUART1 */ +#define GPIO_LPUART1_RX (GPIO_LPUART1_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B0_13 */ +#define GPIO_LPUART1_TX (GPIO_LPUART1_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B0_12 */ + +/* LPUART2 */ +#define GPIO_LPUART2_RX (GPIO_LPUART2_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_03 */ +#define GPIO_LPUART2_TX (GPIO_LPUART2_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_02 */ + +/* LPUART3 */ +#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_07 */ +#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_06 */ + +/* LPUART4 */ +#define GPIO_LPUART4_RX (GPIO_LPUART4_RX_1|IOMUX_UART_DEFAULT) /* GPIO_SD_B1_01 */ +#define GPIO_LPUART4_TX (GPIO_LPUART4_TX_1|IOMUX_UART_DEFAULT) /* GPIO_SD_B1_00 */ + +/* LPUART8 */ +#define GPIO_LPUART8_RX (GPIO_LPUART8_RX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_11 */ +#define GPIO_LPUART8_TX (GPIO_LPUART8_TX_1|IOMUX_UART_DEFAULT) /* GPIO_AD_B1_10 */ + + +/* LPI2C1 */ +#define GPIO_LPI2C1_SDA (GPIO_LPI2C1_SDA_2|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B1_01 */ +#define GPIO_LPI2C1_SCL (GPIO_LPI2C1_SCL_2|IOMUX_LPI2C_DEFAULT) /* GPIO_AD_B1_00 */ + +/* LPI2C3 */ +#define GPIO_LPI2C3_SDA (GPIO_LPI2C3_SDA_2|IOMUX_LPI2C_DEFAULT) /* GPIO_EMC_21 */ +#define GPIO_LPI2C3_SCL (GPIO_LPI2C3_SCL_2|IOMUX_LPI2C_DEFAULT) /* GPIO_EMC_22 */ + + +/* LPSPI */ +#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_2|IOMUX_LPSPI_DEFAULT) /* GPIO_AD_B0_00 */ +#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDI_2|IOMUX_LPSPI_DEFAULT) /* GPIO_AD_B0_02 */ +#define GPIO_LPSPI3_MOSI (GPIO_LPSPI3_SDO_2|IOMUX_LPSPI_DEFAULT) /* GPIO_AD_B0_01 */ + + +/* FLEXCAN2 */ +#define GPIO_FLEXCAN2_TX (GPIO_FLEXCAN2_TX_3|IOMUX_CAN_DEFAULT) /* GPIO_AD_B0_14 */ +#define GPIO_FLEXCAN2_RX (GPIO_FLEXCAN2_RX_3|IOMUX_CAN_DEFAULT) /* GPIO_AD_B0_15 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_IMXRT_XIDATONG_INCLUDE_BOARD_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/kernel/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/kernel/Makefile new file mode 100644 index 000000000..147b40f82 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/kernel/Makefile @@ -0,0 +1,103 @@ +############################################################################ +# boards/arm/imxrt/xidatong/kernel/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_USER_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_USER_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + # Windows-native toolchains + USER_LIBPATHS = ${shell for path in $(USERLIBS); do dir=`dirname $(TOPDIR)$(DELIM)$$path`;echo "-L\"`cygpath -w $$dir`\"";done} + USER_LDSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld}" + USER_LDSCRIPT += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld}" + USER_HEXFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.hex}" + USER_SRECFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.srec}" + USER_BINFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.bin}" +else + # Linux/Cygwin-native toolchain + USER_LIBPATHS = $(addprefix -L$(TOPDIR)$(DELIM),$(dir $(USERLIBS))) + USER_LDSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld + USER_LDSCRIPT += -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld + USER_HEXFILE += "$(TOPDIR)$(DELIM)nuttx_user.hex" + USER_SRECFILE += "$(TOPDIR)$(DELIM)nuttx_user.srec" + USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin" +endif + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = imxrt_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/kernel/imxrt_userspace.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/kernel/imxrt_userspace.c new file mode 100644 index 000000000..6735ddec2 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/kernel/imxrt_userspace.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/kernel/imxrt_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/** +* @file imxrt_userspace.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x60200000 +# error "CONFIG_NUTTX_USERSPACE must be 0x60200000 to match user-space.ld" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. + * They are not actual uint32_t storage locations! + * They are only used meaningfully in the following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declareion extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data (it + * is not!). + * - We can recoved the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +extern uint32_t _stext; /* Start of .text */ +extern uint32_t _etext; /* End_1 of .text + .rodata */ +extern const uint32_t _eronly; /* End+1 of read only section (.text + .rodata) */ +extern uint32_t _sdata; /* Start of .data */ +extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _sbss; /* Start of .bss */ +extern uint32_t _ebss; /* End+1 of .bss */ + +/* This is the user space entry point */ + +int CONFIG_USER_ENTRYPOINT(int argc, char *argv[]); + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = (main_t)CONFIG_USER_ENTRYPOINT, + .us_textstart = (uintptr_t)&_stext, + .us_textend = (uintptr_t)&_etext, + .us_datasource = (uintptr_t)&_eronly, + .us_datastart = (uintptr_t)&_sdata, + .us_dataend = (uintptr_t)&_edata, + .us_bssstart = (uintptr_t)&_sbss, + .us_bssend = (uintptr_t)&_ebss, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/readme.md b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/readme.md new file mode 100644 index 000000000..4dd1f3e84 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/readme.md @@ -0,0 +1,182 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的矽达通 + +# xidatong + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 1. 简介 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| MIMXRT1052CVL5B | +|架构| cortex-m7 | +|主频| 600MHz | +|片内SRAM| 512KB shared with TCM | +|外设支持| UART | + +XiUOS板级当前支持使用UART。 + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +## 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```shell +cd ./Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx +source build.sh + +执行完毕会自动进入./Ubiquitous/Nuttx_Fusion_XiUOS/nuttx下，继续执行 + +sudo ./tools/configure.sh xidatong:nsh +sudo make menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig](./img/menuconfig.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig1](./img/menuconfigexit.png) + +3.继续执行以下命令，进行编译 + +```shell +sudo make +或 +sudo make -j8 +``` + +make时加上V=1参数可以看到较为详细的编译信息，但是编译过程会比较慢。 + +4.如果编译正确无误，会在当前目录下产生nuttx、nuttx.hex等文件。 + +## 3. 烧写及运行 + +### 3.1 烧写 +1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility) + +2、xidatong开发板支持UART串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用串口转USB线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，重新上电，选择对应的COM口和波特率（需关闭串口终端连接，确保该COM口空闲，否则会导致Utility工具连接失败），连接成功后，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示： +![NXPBootUtility_1](./img/NXPBootUtility_1.png) + +3、同时需要匹配xidatong开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示： +![flashconfig](./img/flashconfig.png) + +4、选择编译生成的nuttx.bin文件路径,按照图示步骤，将文件烧写至Flash中（若烧写无误，则下列绿色进度条会执行到底）。如下图所示： +![NXPBootUtility_2](./img/NXPBootUtility_2.png) + +### 3.2 运行结果 + +按照3.1烧写步骤执行后，将拨码开关设置为1 off 2 off 3 off 4 off，重新上电后，重新打开该COM口串口终端，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示： +![terminal](./img/terminal.png) + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/Make.defs new file mode 100644 index 000000000..c3fecc52d --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# boards/arm/imxrt/xidatong/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARMV7M_DTCM),y) + LDSCRIPT = flash-dtcm.ld +else + LDSCRIPT = flash-ocram.ld +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(APPPATHS) $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/flash-ocram.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/flash-ocram.ld new file mode 100644 index 000000000..fb625d802 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/flash-ocram.ld @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/scripts/flash-ocram.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Specify the memory areas */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x60000000, LENGTH = 0x04000000 + sram (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00080000 + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flash_config) +EXTERN(g_image_vector_table) +EXTERN(g_boot_data) +EXTERN(g_dcd_data) + +ENTRY(_stext) + +SECTIONS +{ + /* Image Vector Table and Boot Data for booting from external flash */ + + .boot_hdr : ALIGN(4) + { + FILL(0xff) + __boot_hdr_start__ = ABSOLUTE(.) ; + KEEP(*(.boot_hdr.conf)) + . = 0x1000 ; + KEEP(*(.boot_hdr.ivt)) + . = 0x1020 ; + KEEP(*(.boot_hdr.boot_data)) + . = 0x1030 ; + KEEP(*(.boot_hdr.dcd_data)) + __boot_hdr_end__ = ABSOLUTE(.) ; + . = 0x2000 ; + } >flash + + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/kernel-space.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/kernel-space.ld new file mode 100644 index 000000000..7ad3587d0 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/kernel-space.ld @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/scripts/kernel-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : + { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > kocram AT > kflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > kocram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/memory.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/memory.ld new file mode 100644 index 000000000..fea61bc8d --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/memory.ld @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/scripts/memory.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The i.MXRT1050-EVK has 64Mb of Hyper FLASH beginning at address, + * 0x0060:0000, 512Kb of DTCM RAM beginning at 0x2000:0000, and 512Kb OCRAM + * beginning at 0x2020:0000. Neither DTCM or SDRAM are used in this + * configuration. + * + * The user and kernel space partitions will be spanned with a single + * region of size 2**n bytes. As a consequence, as the partitions increase + * in size, the alignment requirement also increases. The sizes below give + * the largest possible user address spaces (but leave far too much for the + * OS). + * + * The solution to this wasted memory is to (1) use more than one region to + * span the user spaces, or (2) poke holes in a larger region (via sub- + * regions) to trim it to fit better. + * + * A detailed memory map for the 512KB SRAM region is as follows: + * + * 0x2020 0000: Kernel .data region. Typical size: 0.1KB + * ------ ---- Kernel .bss region. Typical size: 1.8KB + * 0x2020 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------ ---- Padded to 4KB + * 0x2040 0000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x2042 0000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------ ---- Beginning of user heap. Can vary with other settings. + * 0x2080 0000: End+1 of mappable OCRAM + */ + +/* Specify the memory areas */ + +MEMORY +{ + /* 64Mb of HyperFLASH */ + + kflash (rx) : ORIGIN = 0x60000000, LENGTH = 1M + uflash (rx) : ORIGIN = 0x60200000, LENGTH = 1M + flash (rx) : ORIGIN = 0x60400000, LENGTH = 62M + + /* 512Kb of OCRAM */ + + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 512K + kocram (rwx) : ORIGIN = 0x20200000, LENGTH = 256K + uocram (rwx) : ORIGIN = 0x20240000, LENGTH = 256K +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/user-space.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/user-space.ld new file mode 100644 index 000000000..ed09f8110 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/scripts/user-space.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/scripts/user-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : + { + *(.userspace) + } > uflash + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : + { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > uocram AT > uflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > uocram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/Makefile new file mode 100644 index 000000000..06e625952 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/Makefile @@ -0,0 +1,69 @@ +############################################################################ +# boards/arm/imxrt/xidatong/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = imxrt_boot.c imxrt_flexspi_nor_boot.c imxrt_flexspi_nor_flash.c + +ifeq ($(CONFIG_IMXRT_SDRAMC),y) +CSRCS += imxrt_sdram.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += imxrt_appinit.c imxrt_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += imxrt_bringup.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += imxrt_autoleds.c +else +CSRCS += imxrt_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += imxrt_buttons.c +endif + +ifeq ($(CONFIG_IMXRT_ENET),y) +CSRCS += imxrt_ethernet.c +endif + +ifeq ($(CONFIG_IMXRT_LPSPI),y) +CSRCS += imxrt_spi.c +endif + +ifeq ($(CONFIG_IMXRT_LCD),y) +CSRCS += imxrt_lcd.c +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += imxrt_mmcsd_spi.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += imxrt_gpio.c +endif + +ifeq ($(CONFIG_XIDATONG_SDRAM),y) +CSRCS += imxrt_sdram_ini_dcd.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_appinit.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_appinit.c new file mode 100644 index 000000000..6070be4c9 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_appinit.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_appinit.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "xidatong.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return imxrt_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_autoleds.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_autoleds.c new file mode 100644 index 000000000..56ce9daeb --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_autoleds.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_autoleds.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/* There are four LED status indicators located on the EVK Board. The + * functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + * + * This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/imxrt_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------- ------ + * + * LED_STARTED 0 NuttX has been started OFF + * LED_HEAPALLOCATE 0 Heap has been allocated OFF + * LED_IRQSENABLED 0 Interrupts enabled OFF + * LED_STACKCREATED 1 Idle stack created ON + * LED_INIRQ 2 In an interrupt N/C + * LED_SIGNAL 2 In a signal handler N/C + * LED_ASSERTION 2 An assertion failed N/C + * LED_PANIC 3 The system has crashed FLASH + * LED_IDLE Not used + * + * Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imxrt_gpio.h" +#include "imxrt_iomuxc.h" +#include "xidatong.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imxrt_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + imxrt_config_gpio(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turn on the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool ledoff = false; + + switch (led) + { + case 0: /* LED Off */ + ledoff = true; + break; + + case 2: /* LED No change */ + return; + + case 1: /* LED On */ + case 3: /* LED On */ + break; + } + + imxrt_gpio_write(GPIO_LED, ledoff); /* Low illuminates */ +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turn off the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 0: /* LED Off */ + case 1: /* LED Off */ + case 3: /* LED Off */ + break; + + case 2: /* LED No change */ + return; + } + + imxrt_gpio_write(GPIO_LED, true); /* Low illuminates */ +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_boot.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_boot.c new file mode 100644 index 000000000..81d823f5d --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_boot.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_boot.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imxrt_start.h" +#include "xidatong.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_boardinitialize + * + * Description: + * All i.MX RT architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void imxrt_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + imxrt_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + imxrt_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_bringup.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_bringup.c new file mode 100644 index 000000000..eda38f3b0 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_bringup.c @@ -0,0 +1,199 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_bringup.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_IMXRT_USDHC +# include "imxrt_usdhc.h" +#endif + +#include "xidatong.h" + +#include /* Must always be included last */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by MMC/SDCard */ + +#ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +#else +# define MMCSD_MINOR 0 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if defined(CONFIG_I2C_DRIVER) && defined(CONFIG_IMXRT_LPI2C) +static void imxrt_i2c_register(int bus) +{ + FAR struct i2c_master_s *i2c; + int ret; + + i2c = imxrt_i2cbus_initialize(bus); + if (i2c == NULL) + { + serr("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + imxrt_i2cbus_uninitialize(i2c); + } + } +} +#endif + +#ifdef CONFIG_IMXRT_USDHC +static int nsh_sdmmc_initialize(void) +{ + struct sdio_dev_s *sdmmc; + int ret = 0; + + /* Get an instance of the SDIO interface */ + + sdmmc = imxrt_usdhc_initialize(0); + if (!sdmmc) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n"); + } + else + { + /* Bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(0, sdmmc); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } + } + + return OK; +} +#else +# define nsh_sdmmc_initialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int imxrt_bringup(void) +{ + int ret; + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C_DRIVER) && defined(CONFIG_IMXRT_LPI2C1) + imxrt_i2c_register(1); +#endif + +#ifdef CONFIG_IMXRT_USDHC + /* Initialize SDHC-base MMC/SD card support */ + + nsh_sdmmc_initialize(); +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Initialize SPI-based MMC/SD card support */ + + imxrt_spidev_initialize(); + + ret = imxrt_mmcsd_spi_initialize(MMCSD_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SD slot %d: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = imxrt_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_buttons.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_buttons.c new file mode 100644 index 000000000..b5283cb71 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_buttons.c @@ -0,0 +1,138 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_buttons.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "arm_arch.h" + +#include "imxrt_config.h" +#include "imxrt_irq.h" +#include "imxrt_gpio.h" +#include "xidatong.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The IMXRT has 1 user button (SW8)): + * + * 1. SW8 (IRQ88) GPIO5-00 + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the button as input */ + + imxrt_config_gpio(GPIO_SW8); + return 1; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + + if (!imxrt_gpio_read(GPIO_SW8)) + { + ret |= BUTTON_SW8_BIT; + } + + return ret; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler) +{ + int ret = -EINVAL; + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = irq_attach(id, irqhandler, NULL); + + /* Then make sure that interrupts are enabled on the pin */ + + up_enable_irq(id); + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_ethernet.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_ethernet.c new file mode 100644 index 000000000..dafbc9e4b --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_ethernet.c @@ -0,0 +1,293 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_ethernet.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_ethernet.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Force verbose debug on in this file only to support unit-level testing. */ + +#ifdef CONFIG_NETDEV_PHY_DEBUG +# undef CONFIG_DEBUG_INFO +# define CONFIG_DEBUG_INFO 1 +# undef CONFIG_DEBUG_NET +# define CONFIG_DEBUG_NET 1 +#endif + +#include +#include +#include +#include + +#include +#include +#include + +#include "imxrt_gpio.h" +#include "imxrt_enet.h" + +#include "xidatong.h" + +#include + +#ifdef CONFIG_IMXRT_ENET + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMXRT_ENET_DEVNAME "eth0" + +/* Debug ********************************************************************/ + +/* Extra, in-depth debug output that is only available if + * CONFIG_NETDEV_PHY_DEBUG us defined. + */ + +#ifdef CONFIG_NETDEV_PHY_DEBUG +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +#else +# define phyerr(x...) +# define phywarn(x...) +# define phyinfo(x...) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_enet_phy_enable + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ +static void imxrt_enet_phy_enable(bool enable) +{ + phyinfo("IRQ%d: enable=%d\n", GPIO_ENET_INT, enable); + + if (enable) + { + up_enable_irq(GPIO_ENET_IRQ); + } + else + { + up_disable_irq(GPIO_ENET_IRQ); + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imxrt_phy_boardinitialize + * + * Description: + * Some boards require specialized initialization of the PHY before it can + * be used. + * This may include such things as configuring GPIOs, resetting the PHY, + * etc. + * If CONFIG_IMXRT_ENET_PHYINIT is defined in the configuration then the + * board specific logic must provide imxrt_phyinitialize(); + * The i.MX RT Ethernet driver will call this function one time before it + * first uses the PHY. + * + * Input Parameters: + * intf - Always zero for now. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int imxrt_phy_boardinitialize(int intf) +{ +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ + /* Configure the PHY interrupt pin */ + + phyinfo("Configuring interrupt: %08x\n", GPIO_ENET_INT); + imxrt_config_gpio(GPIO_ENET_INT); +#endif + + /* Configure the PHY reset pin. + * + * The #RST uses inverted logic. The initial value of zero will put the + * PHY into the reset state. + */ +#ifdef GPIO_ENET_RST + /* On the EVK the RST pin is combined with LED, so sometimes can't be + * accessed. Only stress about it if we've got a definition. + */ + + phyinfo("Configuring reset: %08x\n", GPIO_ENET_RST); + imxrt_config_gpio(GPIO_ENET_RST); + + /* Take the PHY out of reset. */ + + imxrt_gpio_write(GPIO_ENET_RST, true); +#endif + return OK; +} + +/**************************************************************************** + * Name: arch_phy_irq + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a PHY interrupt occurs. This function both attaches + * the interrupt handler and enables the interrupt if 'handler' is non- + * NULL. If handler is NULL, then the interrupt is detached and disabled + * instead. + * + * The PHY interrupt is always disabled upon return. The caller must + * call back through the enable function point to control the state of + * the interrupt. + * + * This interrupt may or may not be available on a given platform depending + * on how the network hardware architecture is implemented. In a typical + * case, the PHY interrupt is provided to board-level logic as a GPIO + * interrupt (in which case this is a board-specific interface and really + * should be called board_phy_irq()); In other cases, the PHY interrupt + * may be cause by the chip's MAC logic (in which case arch_phy_irq()) is + * an appropriate name. Other other boards, there may be no PHY interrupts + * available at all. If client attachable PHY interrupts are available + * from the board or from the chip, then CONFIG_ARCH_PHY_INTERRUPT should + * be defined to indicate that fact. + * + * Typical usage: + * a. OS service logic (not application logic*) attaches to the PHY + * PHY interrupt and enables the PHY interrupt. + * b. When the PHY interrupt occurs: (1) the interrupt should be + * disabled and () work should be scheduled on the worker thread (or + * perhaps a dedicated application thread). + * c. That worker thread should use the SIOCGMIIPHY, SIOCGMIIREG, + * and SIOCSMIIREG ioctl calls** to communicate with the PHY, + * determine what network event took place (Link Up/Down?), and + * take the appropriate actions. + * d. It should then interact the PHY to clear any pending + * interrupts, then re-enable the PHY interrupt. + * + * * This is an OS internal interface and should not be used from + * application space. Rather applications should use the SIOCMIISIG + * ioctl to receive a signal when a PHY event occurs. + * ** This interrupt is really of no use if the Ethernet MAC driver + * does not support these ioctl calls. + * + * Input Parameters: + * intf - Identifies the network interface. For example "eth0". Only + * useful on platforms that support multiple Ethernet interfaces + * and, hence, multiple PHYs and PHY interrupts. + * handler - The client interrupt handler to be invoked when the PHY + * asserts an interrupt. Must reside in OS space, but can + * signal tasks in user space. A value of NULL can be passed + * in order to detach and disable the PHY interrupt. + * arg - The argument that will accompany the interrupt + * enable - A function pointer that be unused to enable or disable the + * PHY interrupt. + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ +int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg, + phy_enable_t *enable) +{ + irqstate_t flags; + phy_enable_t enabler; + int irq; + + DEBUGASSERT(intf); + + ninfo("%s: handler=%p\n", intf, handler); + phyinfo("EMAC: devname=%s\n", IMXRT_ENET_DEVNAME); + + if (strcmp(intf, IMXRT_ENET_DEVNAME) == 0) + { + irq = GPIO_ENET_IRQ; + enabler = imxrt_enet_phy_enable; + } + else + { + nerr("ERROR: Unsupported interface: %s\n", intf); + return -EINVAL; + } + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = spin_lock_irqsave(NULL); + + /* Configure the interrupt */ + + if (handler) + { + /* The interrupt pin has already been configured as an interrupting + * input (by imxrt_phy_boardinitialize() above). + * + * Attach the new button handler. + */ + + phyinfo("Attach IRQ%d\n", irq); + irq_attach(irq, handler, arg); + } + else + { + phyinfo("Detach IRQ%d\n", irq); + irq_detach(irq); + enabler = NULL; + } + + /* Return with the interrupt disabled in either case */ + + up_disable_irq(GPIO_ENET_IRQ); + + /* Return the enabling function pointer */ + + if (enable) + { + *enable = enabler; + } + + /* Return the old handler (so that it can be restored) */ + + spin_unlock_irqrestore(NULL, flags); + return OK; +} +#endif /* CONFIG_IMXRT_GPIO1_0_15_IRQ */ + +#endif /* CONFIG_IMXRT_ENET */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_boot.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_boot.c new file mode 100644 index 000000000..c2ce4e2b1 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_boot.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_flexspi_nor_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_flexspi_nor_boot.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imxrt_flexspi_nor_boot.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +locate_data(".boot_hdr.ivt") +const struct ivt_s g_image_vector_table = +{ + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&g_image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +locate_data(".boot_hdr.boot_data") +const struct boot_data_s g_boot_data = +{ + FLASH_BASE, /* boot start location */ + (FLASH_END - FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag */ + 0xffffffff /* empty - extra data word */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_boot.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_boot.h new file mode 100644 index 000000000..33b86eb40 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_boot.h @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_flexspi_nor_boot.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_flexspi_nor_boot.h +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +#ifndef __BOARDS_ARM_IMXRT_XIDATONG_SRC_IMXRT_FLEXSPI_NOR_BOOT_H +#define __BOARDS_ARM_IMXRT_XIDATONG_SRC_IMXRT_FLEXSPI_NOR_BOOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IVT Data */ + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xf +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xf + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xd1) /* Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + +/* DCD Data */ + +#define DCD_TAG_HEADER (0xd2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7f7fffff +#define SCLK 1 + +#ifdef CONFIG_XIDATONG_SDRAM +# define DCD_ADDRESS &g_dcd_data +#else +# define DCD_ADDRESS 0 +#endif + +#define BOOT_DATA_ADDRESS &g_boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* IVT Data */ + +struct ivt_s +{ + /* Header with tag #HAB_TAG_IVT, length and HAB version fields + * (see data) + */ + + uint32_t hdr; + + /* Absolute address of the first instruction to execute from the + * image + */ + + uint32_t entry; + + /* Reserved in this version of HAB: should be NULL. */ + + uint32_t reserved1; + + /* Absolute address of the image DCD: may be NULL. */ + + uint32_t dcd; + + /* Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + + uint32_t boot_data; + + /* Absolute address of the IVT. */ + + uint32_t self; + + /* Absolute address of the image CSF. */ + + uint32_t csf; + + /* Reserved in this version of HAB: should be zero. */ + + uint32_t reserved2; +}; + +/* Boot Data */ + +struct boot_data_s +{ + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placeholder to make even 0x10 size */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern const struct boot_data_s g_boot_data; + +#ifdef CONFIG_XIDATONG_SDRAM +extern const uint8_t g_dcd_data[]; +#endif + +#endif /* __BOARDS_ARM_IMXRT_XIDATONG_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.c new file mode 100644 index 000000000..b3ba34f0c --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.c @@ -0,0 +1,135 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_flexspi_nor_flash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_flexspi_nor_flash.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imxrt_flexspi_nor_flash.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined (CONFIG_XIDATONG_HYPER_FLASH) +locate_data(".boot_hdr.conf") +const struct flexspi_nor_config_s g_flash_config = +{ + .mem_config = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD, + .cs_hold_time = 3u, + .cs_setup_time = 3u, + .column_address_width = 3u, + + /* Enable DDR mode, Word addassable, + * Safe configuration, Differential clock + */ + + .controller_misc_option = + (1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN) | + (1u << FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN) | + (1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN) | + (1u << FLEXSPIMISC_OFFSET_DIFFCLKEN), + .sflash_pad_type = SERIAL_FLASH_8PADS, + .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz, + .sflash_a1size = 64u * 1024u * 1024u, + .data_valid_time = + { + 16u, 16u + }, + .lookup_table = + { + /* Read LUTs */ + + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0xa0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, + FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, + FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .page_size = 512u, + .sector_size = 256u * 1024u, + .blocksize = 256u * 1024u, + .is_uniform_blocksize = 1, +}; + +#elif defined (CONFIG_XIDATONG_QSPI_FLASH) +locate_data(".boot_hdr.conf") +const struct flexspi_nor_config_s g_flash_config = +{ + .mem_config = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY, + .cs_hold_time = 3u, + .cs_setup_time = 3u, + .device_mode_cfg_enable = true, + .device_mode_type = 1, + .device_mode_seq.seq_num = 1, + .device_mode_seq.seq_id = 4, + .device_mode_arg = 0x000200, + .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, + .sflash_pad_type = SERIAL_FLASH_4PADS, + .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_60MHz, + .sflash_a1size = 16u * 1024u * 1024u, + .data_valid_time = {16u, 16u}, + + /* Enable DDR mode, Word addassable, + * Safe configuration, Differential clock + */ + .lookup_table = + { + /* Read LUTs */ + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), + + [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + //Write Enable + [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), + //Write status + [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2), + }, + }, + .page_size = 256u, + .sector_size = 4u * 1024u, +}; +#else +# error Boot Flash type not chosen! +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.h new file mode 100644 index 000000000..3ea7a74d2 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_flexspi_nor_flash.h @@ -0,0 +1,359 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_flexspi_nor_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_flexspi_nor_flash.h +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +#ifndef __BOARDS_ARM_IMXRT_XIDATONG_SRC_IMXRT_FLEXSPI_NOR_FLASH_H +#define __BOARDS_ARM_IMXRT_XIDATONG_SRC_IMXRT_FLEXSPI_NOR_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* FLEXSPI memory config block related definitions */ + +#define FLEXSPI_CFG_BLK_TAG (0x42464346ul) +#define FLEXSPI_CFG_BLK_VERSION (0x56010400ul) +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ + +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related definitions */ + +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0a +#define LEARN_DDR 0x2a +#define DATSZ_SDR 0x0b +#define DATSZ_DDR 0x2b +#define DUMMY_SDR 0x0c +#define DUMMY_DDR 0x2c +#define DUMMY_RWDS_SDR 0x0d +#define DUMMY_RWDS_DDR 0x2d +#define JMP_ON_CS 0x1f +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_OPERAND0_MASK (0xffu) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & \ + FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300u) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8u) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & \ + FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xfc00u) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10u) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & \ + FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xff0000u) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & \ + FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000u) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24u) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & \ + FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xfc000000u) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26u) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & \ + FLEXSPI_LUT_OPCODE1_MASK) + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ + FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +#define NOR_CMD_INDEX_READ CMD_INDEX_READ +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE +#define NOR_CMD_INDEX_ERASESECTOR 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE +#define NOR_CMD_INDEX_CHIPERASE 5 +#define NOR_CMD_INDEX_DUMMY 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 + +/* READ LUT sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ + +/* Read Status LUT sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS + +/* 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config + * block + */ + +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 + +/* 3 Write Enable sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE + +/* 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config + * block + */ + +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 + +/* 5 Erase Sector sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 + +/* 8 Erase Block sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 + +/* 9 Program sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE + +/* 11 Chip Erase sequence in lookupTable id stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 + +/* 13 Read SFDP sequence in lookupTable id stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 + +/* 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config + * block + */ + +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 + +/* 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config + * blobk + */ + +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Definitions for FlexSPI Serial Clock Frequency */ + +enum flexspi_serial_clkfreq_e +{ + FLEXSPI_SERIAL_CLKFREQ_30MHz = 1, + FLEXSPI_SERIAL_CLKFREQ_50MHz = 2, + FLEXSPI_SERIAL_CLKFREQ_60MHz = 3, + FLEXSPI_SERIAL_CLKFREQ_75MHz = 4, + FLEXSPI_SERIAL_CLKFREQ_80MHz = 5, + FLEXSPI_SERIAL_CLKFREQ_100MHz = 6, + FLEXSPI_SERIAL_CLKFREQ_133MHz = 7, + FLEXSPI_SERIAL_CLKFREQ_166MHz = 8, + FLEXSPI_SERIAL_CLKFREQ_200MHz = 9, +}; + +/* FlexSPI clock configuration type */ + +enum flexspi_serial_clockmode_e +{ + FLEXSPI_CLKMODE_SDR, + FLEXSPI_CLKMODE_DDR, +}; + +/* FlexSPI Read Sample Clock Source definition */ + +enum flash_read_sample_clk_e +{ + FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0, + FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1, + FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2, + FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD = 3, +}; + +/* Misc feature bit definitions */ + +enum flash_misc_feature_e +{ + FLEXSPIMISC_OFFSET_DIFFCLKEN = 0, /* Bit for Differential clock enable */ + FLEXSPIMISC_OFFSET_CK2EN = 1, /* Bit for CK2 enable */ + FLEXSPIMISC_OFFSET_PARALLELEN = 2, /* Bit for Parallel mode enable */ + FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ + FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ + FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ +}; + +/* Flash Type Definition */ + +enum flash_flash_type_e +{ + FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1, /* Flash devices are Serial NOR */ + FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2, /* Flash devices are Serial NAND */ + FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3, /* Flash devices are Serial RAM/HyperFLASH */ + FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ + FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ +}; + +/* Flash Pad Definitions */ + +enum flash_flash_pad_e +{ + SERIAL_FLASH_1PAD = 1, + SERIAL_FLASH_2PADS = 2, + SERIAL_FLASH_4PADS = 4, + SERIAL_FLASH_8PADS = 8, +}; + +/* Flash Configuration Command Type */ + +enum flash_config_cmd_e +{ + DEVICE_CONFIG_CMD_TYPE_GENERIC, /* Generic command, for example: configure dummy cycles, drive strength, etc */ + DEVICE_CONFIG_CMD_TYPE_QUADENABLE, /* Quad Enable command */ + DEVICE_CONFIG_CMD_TYPE_SPI2XPI, /* Switch from SPI to DPI/QPI/OPI mode */ + DEVICE_CONFIG_CMD_TYPE_XPI2SPI, /* Switch from DPI/QPI/OPI to SPI mode */ + DEVICE_CONFIG_CMD_TYPE_SPI2NO_CMD, /* Switch to 0-4-4/0-8-8 mode */ + DEVICE_CONFIG_CMD_TYPE_RESET, /* Reset device command */ +}; + +/* FlexSPI LUT Sequence structure */ + +struct flexspi_lut_seq_s +{ + uint8_t seq_num; /* Sequence Number, valid number: 1-16 */ + uint8_t seq_id; /* Sequence Index, valid number: 0-15 */ + uint16_t reserved; +}; + +/* FlexSPI Memory Configuration Block */ + +struct flexspi_mem_config_s +{ + uint32_t tag; + uint32_t version; + uint32_t reserved0; + uint8_t read_sample_clksrc; + uint8_t cs_hold_time; + uint8_t cs_setup_time; + uint8_t column_address_width; /* [0x00f-0x00f] Column Address with, for + * HyperBus protocol, it is fixed to 3, For + * Serial NAND, need to refer to datasheet + */ + uint8_t device_mode_cfg_enable; + uint8_t device_mode_type; + uint16_t wait_time_cfg_commands; + struct flexspi_lut_seq_s device_mode_seq; + uint32_t device_mode_arg; + uint8_t config_cmd_enable; + uint8_t config_mode_type[3]; + struct flexspi_lut_seq_s config_cmd_seqs[3]; + uint32_t reserved1; + uint32_t config_cmd_args[3]; + uint32_t reserved2; + uint32_t controller_misc_option; + uint8_t device_type; + uint8_t sflash_pad_type; + uint8_t serial_clk_freq; + uint8_t lut_custom_seq_enable; + uint32_t reserved3[2]; + uint32_t sflash_a1size; + uint32_t sflash_a2size; + uint32_t sflash_b1size; + uint32_t sflash_b2size; + uint32_t cspad_setting_override; + uint32_t sclkpad_setting_override; + uint32_t datapad_setting_override; + uint32_t dqspad_setting_override; + uint32_t timeout_in_ms; + uint32_t command_interval; + uint16_t data_valid_time[2]; + uint16_t busy_offset; + uint16_t busybit_polarity; + uint32_t lookup_table[64]; + struct flexspi_lut_seq_s lut_customseq[12]; + uint32_t reserved4[4]; +}; + +/* Serial NOR configuration block */ + +struct flexspi_nor_config_s +{ + struct flexspi_mem_config_s mem_config; /* Common memory configuration info via FlexSPI */ + uint32_t page_size; /* Page size of Serial NOR */ + uint32_t sector_size; /* Sector size of Serial NOR */ + uint8_t ipcmd_serial_clkfreq; /* Clock frequency for IP command */ + uint8_t is_uniform_blocksize; /* Sector/Block size is the same */ + uint8_t reserved0[2]; /* Reserved for future use */ + uint8_t serial_nor_type; /* Serial NOR Flash type: 0/1/2/3 */ + uint8_t need_exit_nocmdmode; /* Need to exit NoCmd mode before other IP command */ + uint8_t halfclk_for_nonreadcmd; /* Half the Serial Clock for non-read command: true/false */ + uint8_t need_restore_nocmdmode; /* Need to Restore NoCmd mode after IP command execution */ + uint32_t blocksize; /* Block size */ + uint32_t reserve2[11]; /* Reserved for future use */ +}; + +#endif /* __BOARDS_ARM_IMXRT_XIDATONG_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_gpio.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_gpio.c new file mode 100644 index 000000000..c5909edd2 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_gpio.c @@ -0,0 +1,224 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_gpio.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" + +#include +#include "xidatong.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrtgpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value); +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_write(FAR struct gpio_dev_s *dev, bool value); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + + #if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct imxrtgpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_GOUT1, + GPIO_GOUT2, + GPIO_GOUT3, + GPIO_GOUT4, +}; + +static struct imxrtgpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct imxrtgpio_dev_s *imxrtgpio = (FAR struct imxrtgpio_dev_s *)dev; + + DEBUGASSERT(imxrtgpio != NULL && value != NULL); + DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = imxrt_gpio_read(g_gpioinputs[imxrtgpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct imxrtgpio_dev_s *imxrtgpio = (FAR struct imxrtgpio_dev_s *)dev; + + DEBUGASSERT(imxrtgpio != NULL && value != NULL); + DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = imxrt_gpio_read(g_gpiooutputs[imxrtgpio->id]); + return OK; +} + +static int gpout_write(FAR struct gpio_dev_s *dev, bool value) +{ + FAR struct imxrtgpio_dev_s *imxrtgpio = (FAR struct imxrtgpio_dev_s *)dev; + + DEBUGASSERT(imxrtgpio != NULL); + DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + imxrt_gpio_write(g_gpiooutputs[imxrtgpio->id], value); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int imxrt_gpio_initialize(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + imxrt_config_gpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + imxrt_gpio_write(g_gpiooutputs[i], 0); + imxrt_config_gpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_lcd.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_lcd.c new file mode 100644 index 000000000..8b8a6c7b4 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_lcd.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_lcd.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_lcd.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imxrt_lcd.h" +#include "imxrt_gpio.h" + +#include "xidatong.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ****************************************************************************/ + +void imxrt_lcd_initialize(void) +{ + /* Configure the LCD backlight (and turn the backlight off) */ + + imxrt_config_gpio(GPIO_LCD_BL); +} + +/**************************************************************************** + * Name: imxrt_backlight + * + * Description: + * If CONFIG_IMXRT_LCD_BACKLIGHT is defined, then the board-specific + * logic must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LCD_BACKLIGHT +void imxrt_backlight(bool blon) +{ + imxrt_gpio_write(GPIO_LCD_BL, blon); /* High illuminates */ +} +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_mmcsd_spi.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_mmcsd_spi.c new file mode 100644 index 000000000..1f495ec14 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_mmcsd_spi.c @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_mmcsd_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_mmcsd_spi.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_arch.h" +#include "chip.h" +#include "imxrt_lpspi.h" + +#ifdef CONFIG_MMCSD_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_IMXRT_LPSPI1 +# error "SD driver requires CONFIG_IMXRT_LPSPI1 to be enabled" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +static const int SD_SPI_PORT = CONFIG_NSH_MMCSDSPIPORTNO; /* SD is connected to SPI1 port */ + +static const int SD_SLOT_NO = 0; /* There is only one SD slot */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* NOTE: We are using a SDCard adapter/module without Card Detect pin! + * Then we don't need to Card Detect callback here. + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LPSPI1 +int imxrt_lpspi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi1 device\n"); + return OK; +} +#endif + +/**************************************************************************** + * Name: imxrt_mmcsd_spi_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + * + ****************************************************************************/ + +int imxrt_mmcsd_spi_initialize(int minor) +{ + struct spi_dev_s *spi; + int rv; + + mcinfo("INFO: Initializing mmcsd card\n"); + + spi = imxrt_lpspibus_initialize(SD_SPI_PORT); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + SD_SPI_PORT, SD_SLOT_NO); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} + +#endif /* CONFIG_MMCSD_SPI */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_sdram_ini_dcd.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_sdram_ini_dcd.c new file mode 100644 index 000000000..91692c2b4 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_sdram_ini_dcd.c @@ -0,0 +1,1266 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_sdram_ini_dcd.c + * + * Copyright (C) 2017, NXP Semiconductors, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +/** +* @file imxrt_sdram_ini_dcd.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imxrt_flexspi_nor_boot.h" + +locate_data(".boot_hdr.dcd_data") + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const uint8_t g_dcd_data[] = +{ + /* 0000 */ DCD_TAG_HEADER, + + 0x04, + 0x30, + 0x41, + 0xcc, + 0x03, + 0xac, + 0x04, + 0x40, + 0x0f, + 0xc0, + 0x68, + 0xff, + 0xff, + 0xff, + 0xff, + + /* 0010 */ 0x40, + + 0x0f, + 0xc0, + 0x6c, + 0xff, + 0xff, + 0xff, + 0xff, + 0x40, + 0x0f, + 0xc0, + 0x70, + 0xff, + 0xff, + 0xff, + 0xff, + + /* 0020 */ 0x40, + + 0x0f, + 0xc0, + 0x74, + 0xff, + 0xff, + 0xff, + 0xff, + 0x40, + 0x0f, + 0xc0, + 0x78, + 0xff, + 0xff, + 0xff, + 0xff, + + /* 0030 */ 0x40, + + 0x0f, + 0xc0, + 0x7c, + 0xff, + 0xff, + 0xff, + 0xff, + 0x40, + 0x0f, + 0xc0, + 0x80, + 0xff, + 0xff, + 0xff, + 0xff, + + /* 0040 */ 0x40, + + 0x0d, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0d, + 0x81, + 0x00, + 0x00, + 0x1d, + 0x00, + 0x00, + + /* 0050 */ 0x40, + + 0x0f, + 0xc0, + 0x14, + 0x00, + 0x01, + 0x0d, + 0x40, + 0x40, + 0x1f, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0060 */ 0x40, + + 0x1f, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x1c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0070 */ 0x40, + + 0x1f, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0080 */ 0x40, + + 0x1f, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x2c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0090 */ 0x40, + + 0x1f, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 00a0 */ 0x40, + + 0x1f, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 00b0 */ 0x40, + + 0x1f, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 00c0 */ 0x40, + + 0x1f, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x4c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 00d0 */ 0x40, + + 0x1f, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 00e0 */ 0x40, + + 0x1f, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x5c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 00f0 */ 0x40, + + 0x1f, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0100 */ 0x40, + + 0x1f, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x6c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0110 */ 0x40, + + 0x1f, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0120 */ 0x40, + + 0x1f, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x7c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0130 */ 0x40, + + 0x1f, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0140 */ 0x40, + + 0x1f, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x8c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0150 */ 0x40, + + 0x1f, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0160 */ 0x40, + + 0x1f, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x9c, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0170 */ 0x40, + + 0x1f, + 0x80, + 0xa0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0xa4, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0180 */ 0x40, + + 0x1f, + 0x80, + 0xa8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0xac, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 0190 */ 0x40, + + 0x1f, + 0x80, + 0xb0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1f, + 0x80, + 0xb4, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 01a0 */ 0x40, + + 0x1f, + 0x80, + 0xb8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 01b0 */ 0x40, + + 0x1f, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x0c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 01c0 */ 0x40, + + 0x1f, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 01d0 */ 0x40, + + 0x1f, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x1c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 01e0 */ 0x40, + + 0x1f, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 01f0 */ 0x40, + + 0x1f, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x2c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0200 */ 0x40, + + 0x1f, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0210 */ 0x40, + + 0x1f, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x3c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0220 */ 0x40, + + 0x1f, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0230 */ 0x40, + + 0x1f, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x4c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0240 */ 0x40, + + 0x1f, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0250 */ 0x40, + + 0x1f, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x5c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0260 */ 0x40, + + 0x1f, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0270 */ 0x40, + + 0x1f, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x6c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0280 */ 0x40, + + 0x1f, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 0290 */ 0x40, + + 0x1f, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x7c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 02a0 */ 0x40, + + 0x1f, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 02b0 */ 0x40, + + 0x1f, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x8c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 02c0 */ 0x40, + + 0x1f, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 02d0 */ 0x40, + + 0x1f, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x9c, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 02e0 */ 0x40, + + 0x1f, + 0x82, + 0xa0, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0xa4, + 0x00, + 0x01, + 0x10, + 0xf9, + + /* 02f0 */ 0x40, + + 0x1f, + 0x82, + 0xa8, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x2f, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + + /* 0300 */ 0x40, + + 0x2f, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2f, + 0x00, + 0x0c, + 0x06, + 0x03, + 0x05, + 0x24, + + /* 0310 */ 0x40, + + 0x2f, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1b, + 0x40, + 0x2f, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1b, + + /* 0320 */ 0x40, + + 0x2f, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1b, + 0x40, + 0x2f, + 0x00, + 0x1c, + 0x86, + 0x00, + 0x00, + 0x1b, + + /* 0330 */ 0x40, + + 0x2f, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2f, + 0x00, + 0x24, + 0xa0, + 0x00, + 0x00, + 0x19, + + /* 0340 */ 0x40, + + 0x2f, + 0x00, + 0x28, + 0xa8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2f, + 0x00, + 0x2c, + 0xa9, + 0x00, + 0x00, + 0x1b, + + /* 0350 */ 0x40, + + 0x2f, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2f, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xa8, + + /* 0360 */ 0x40, + + 0x2f, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0f, + 0x31, + 0x40, + 0x2f, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + + /* 0370 */ 0x40, + + 0x2f, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2f, + 0x00, + 0x4c, + 0x50, + 0x21, + 0x0a, + 0x08, + + /* 0380 */ 0x40, + + 0x2f, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2f, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + + /* 0390 */ 0x40, + + 0x2f, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2f, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + + /* 03a0 */ 0x40, + + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0f, + + /* 03b0 */ 0xcf, + + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x14, + 0x04, + + /* 03c0 */ 0x40, + + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0c, + + /* 03d0 */ 0xcf, + + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x14, + 0x04, + + /* 03e0 */ 0x40, + + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0c, + + /* 03f0 */ 0xcf, + + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x1c, + 0x04, + + /* 0400 */ 0x40, + + 0x2f, + 0x00, + 0xa0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + + /* 0410 */ 0x40, + + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0a, + 0xcf, + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + + /* 0420 */ 0x00, + + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x0c, + 0x04, + 0x40, + 0x2f, + 0x00, + 0x4c, + 0x50, + 0x07, + 0x0a, + 0x09, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_spi.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_spi.c new file mode 100644 index 000000000..673eaec0b --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_spi.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_spi.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_arch.h" + +#include "imxrt_config.h" +#include "imxrt_lpspi.h" +#include "imxrt_gpio.h" +#include "xidatong.h" + +#if defined(CONFIG_IMXRT_LPSPI1) || defined(CONFIG_IMXRT_LPSPI2) || \ + defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the xidatong + * board. + * + ****************************************************************************/ + +void weak_function imxrt_spidev_initialize(void) +{ +#ifdef CONFIG_IMXRT_LPSPI1 + imxrt_config_gpio(GPIO_LPSPI1_CS); /* LPSPI1 chip select */ + imxrt_config_gpio(GPIO_MMCSD_EN); +#endif +#ifdef CONFIG_IMXRT_LPSPI3 + imxrt_config_gpio(GPIO_LPSPI3_CS); /* LPSPI3 chip select */ +#endif +} + +/**************************************************************************** + * Name: imxrt_lpspi1/2/3select and imxrt_lpspi1/2/3status + * + * Description: + * The external functions, imxrt_lpspi1/2/3select and + * imxrt_lpspi1/2/3status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including imxrt_lpspibus_initialize()) are provided + * by common STM32 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in imxrt_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide imxrt_lpspi1/2/3select() and imxrt_lpspi1/2/3status() + * functions in your board-specific logic. + * These functions will perform chip selection and status operations + * using GPIOs in the way your board is configured. + * 3. Add a calls to imxrt_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by imxrt_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LPSPI1 +void imxrt_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + imxrt_gpio_write(GPIO_LPSPI1_CS, !selected); +} + +uint8_t imxrt_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_IMXRT_LPSPI2 +void imxrt_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + imxrt_gpio_write(GPIO_LPSPI2_CS, !selected); +} + +uint8_t imxrt_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_IMXRT_LPSPI3 +void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + imxrt_gpio_write(GPIO_LPSPI3_CS, !selected); +} + +uint8_t imxrt_lpspi3status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_IMXRT_LPSPI4 +void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + imxrt_gpio_write(GPIO_LPSPI4_CS, !selected); +} + +uint8_t imxrt_lpspi4status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: imxrt_lpspi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_IMXRT_LPSPI1 +int imxrt_lpspi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_IMXRT_LPSPI2 +int imxrt_lpspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_IMXRT_LPSPI3 +int imxrt_lpspi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_IMXRT_LPSPI4 +int imxrt_lpspi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ +#endif /* CONFIG_IMXRT_LPSPI1 || CONFIG_IMXRT_LPSPI2 */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_userleds.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_userleds.c new file mode 100644 index 000000000..1b5c187c9 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_userleds.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/imxrt_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_userleds.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/* There are four LED status indicators located on the EVK Board. The + * functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imxrt_gpio.h" +#include "imxrt_iomuxc.h" +#include "xidatong.h" + +#include + +#if !defined(CONFIG_ARCH_LEDS) && defined(GPIO_LED) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIO for output */ + + imxrt_config_gpio(GPIO_LED); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + imxrt_gpio_write(GPIO_LED, !ledon); /* Low illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* Low illuminates */ + + imxrt_gpio_write(GPIO_LED, (ledset & BOARD_USERLED_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/xidatong.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/xidatong.h new file mode 100644 index 000000000..d8828d756 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/xidatong.h @@ -0,0 +1,202 @@ +/**************************************************************************** + * boards/arm/imxrt/xidatong/src/xidatong.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file xidatong.h +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +#ifndef __BOARDS_ARM_IMXRT_XIDATONG_SRC_XIDATONG_H +#define __BOARDS_ARM_IMXRT_XIDATONG_SRC_XIDATONG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "imxrt_gpio.h" +#include "imxrt_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs */ + +#define GPIO_LED (GPIO_OUTPUT | IOMUX_LED_DEFAULT | \ + GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN9) /* AD_BO_09 */ + +/* Buttons ******************************************************************/ + +#define GPIO_SW8 (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | \ + IOMUX_SW_DEFAULT | \ + GPIO_PORT5 | GPIO_PIN0 | ) /* WAKEUP */ + +/* Test Pins ****************************************************************/ + +#define BOARD_NGPIOIN 0 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 4 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 0 /* Amount of GPIO Input w/ Interruption pins */ + +#define GPIO_GOUT1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PORT1 | GPIO_PIN19) + +#define GPIO_GOUT2 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PIN18 | GPIO_PORT1) + +#define GPIO_GOUT3 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PIN10 | GPIO_PORT1) + +#define GPIO_GOUT4 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PIN9 | GPIO_PORT1) + +/* Backlight */ + +#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT2 | \ + GPIO_PIN31 | IOMUX_LCD_BL_DEFAULT) + +/* Ethernet */ + +#define GPIO_ENET_INT (IOMUX_ENET_INT_DEFAULT | \ + GPIO_PORT1 | GPIO_PIN10) /* AD_B0_10 */ +#define GPIO_ENET_IRQ IMXRT_IRQ_GPIO1_10 +#define GPIO_ENET_RST (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT1 | GPIO_PIN9 | IOMUX_ENET_RST_DEFAULT) + +#ifdef CONFIG_ETH0_PHY_KSZ8081 +#ifdef GPIO_LED +#warning LED interferes with ETH reset unless R323 is removed. +#endif +#endif + +/* LPSPI CS: */ + +#define IOMUX_LPSPI3_CS (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \ + IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \ + _IOMUX_PULL_ENABLE) +#define GPIO_LPSPI3_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \ + GPIO_PORT1 | GPIO_PIN3 | IOMUX_LPSPI3_CS) /* GPIO_AD_B0_03 */ + +/* LPSPI1 CS: GPIO_SD_B0_01 */ + +#define IOMUX_LPSPI1_CS (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \ + IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \ + _IOMUX_PULL_ENABLE) +#define GPIO_LPSPI1_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \ + GPIO_PORT3 | GPIO_PIN13 | IOMUX_LPSPI1_CS) + +#define IOMUX_MMCSD_EN (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \ + IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \ + _IOMUX_PULL_ENABLE) +#define GPIO_MMCSD_EN (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT3 | GPIO_PIN2 | IOMUX_MMCSD_EN) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int imxrt_bringup(void); +#endif + +/**************************************************************************** + * Name: imxrt_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the i.MXRT1050 EVK. + * + ****************************************************************************/ + +void imxrt_spidev_initialize(void); + +/**************************************************************************** + * Name: imxrt_mmcsd_spi_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD_SPI +int imxrt_mmcsd_spi_initialize(int minor); +#endif + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void imxrt_autoled_initialize(void); +#endif + +#ifdef CONFIG_DEV_GPIO + +/**************************************************************************** + * Name: imxrt_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int imxrt_gpio_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_IMXRT_XIDATONG_SRC_XIDATONG_H */ diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/Makefile similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/Makefile rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/Makefile diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/examples/sx127x_demo/sx127x_demo.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/examples/sx127x_demo/sx127x_demo.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/examples/sx127x_demo/sx127x_demo.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/examples/sx127x_demo/sx127x_demo.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Kconfig similarity index 99% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Kconfig index 0ce94d01a..f84148ed5 100644 --- a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/Kconfig +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Kconfig @@ -630,6 +630,14 @@ config NSH_DISABLE_TEMPHS300X config NSH_DISABLE_HUMIHS300X bool "Disable the humidity function of the sensor Hs300x." default n + +config NSH_DISABLE_QS_FX + bool "Disable the winddirection function of the sensor QS-FX." + default n + +config NSH_DISABLE_QS_FS + bool "Disable the windspeed function of the sensor QS-FS." + default n config NSH_DISABLE_OPENZIGBEE bool "Disable the open function of the zigebee." diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Makefile similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/Makefile rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Makefile diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h similarity index 99% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h index a10aa150d..f23773552 100644 --- a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h @@ -1461,6 +1461,14 @@ int nsh_foreach_var(FAR struct nsh_vtbl_s *vtbl, nsh_foreach_var_t cb, int cmd_HumiHs300x(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); #endif +#if defined(CONFIG_APPLICATION_SENSOR_WINDDIRECTION_QS_FX) && !defined(CONFIG_NSH_DISABLE_QS_FX) + int cmd_WindDirectionQsFx(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + +#if defined(CONFIG_APPLICATION_SENSOR_WINDSPEED_QS_FS) && !defined(CONFIG_NSH_DISABLE_QS_FS) + int cmd_WindSpeedQsFs(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + #if defined(CONFIG_CONNECTION_ADAPTER_ZIGBEE) && !defined(CONFIG_NSH_DISABLE_OPENZIGBEE) int cmd_openzigbee(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c similarity index 88% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c index f42fec198..68a5da9d4 100644 --- a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c @@ -204,6 +204,35 @@ int cmd_HumiHs300x(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) } #endif +/**************************************************************************** + * Name: cmd_WindDirectionQsFx + ****************************************************************************/ + +#if defined(CONFIG_APPLICATION_SENSOR_WINDDIRECTION_QS_FX) && !defined(CONFIG_NSH_DISABLE_QS_FX) +extern void WindDirectionQsFx(void); +int cmd_WindDirectionQsFx(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, world!\n"); + FrameworkInit(); + WindDirectionQsFx(); + return OK; +} +#endif + +/**************************************************************************** + * Name: cmd_WindSpeedQsFs + ****************************************************************************/ + +#if defined(CONFIG_APPLICATION_SENSOR_WINDSPEED_QS_FS) && !defined(CONFIG_NSH_DISABLE_QS_FS) +extern void WindSpeedQsFs(void); +int cmd_WindSpeedQsFs(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, world!\n"); + FrameworkInit(); + WindSpeedQsFs(); + return OK; +} +#endif /**************************************************************************** * Name: cmd_openzigbee diff --git a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh_command.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c similarity index 98% rename from Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh_command.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c index a60bc254f..8cd21e468 100644 --- a/Ubiquitous/Nuttx/app_match_nuttx/apps/nshlib/nsh_command.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c @@ -634,6 +634,14 @@ static const struct cmdmap_s g_cmdmap[] = { "humi", cmd_HumiHs300x, 1, 1, "[get humidity with sensor HS300x.]" }, #endif +#if defined(CONFIG_APPLICATION_SENSOR_WINDDIRECTION_QS_FX) && !defined(CONFIG_NSH_DISABLE_QS_FX) + { "WindDirectionQsFx", cmd_WindDirectionQsFx, 1, 1, "[get WindDirection with sensor QsFx.]" }, +#endif + +#if defined(CONFIG_APPLICATION_SENSOR_WINDSPEED_QS_FS) && !defined(CONFIG_NSH_DISABLE_QS_FS) + { "WindSpeedQsFs", cmd_WindSpeedQsFs, 1, 1, "[get WindSpeed with sensor QsFs.]" }, +#endif + #if defined(CONFIG_CONNECTION_ADAPTER_ZIGBEE) && !defined(CONFIG_NSH_DISABLE_OPENZIGBEE) { "openzigbee", cmd_openzigbee, 1, 1, "[open the zigebee device.]" }, #endif diff --git a/Ubiquitous/Nuttx/app_match_nuttx/build.sh b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh similarity index 71% rename from Ubiquitous/Nuttx/app_match_nuttx/build.sh rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh index 7b5b39fcc..c8bb5ca86 100644 --- a/Ubiquitous/Nuttx/app_match_nuttx/build.sh +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh @@ -7,8 +7,8 @@ export top=$current/../../.. cd $top git submodule git submodule init -git submodule update Ubiquitous/Nuttx/apps -git submodule update Ubiquitous/Nuttx/nuttx +git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/apps +git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/nuttx cd $current chmod -R +x $top @@ -18,5 +18,6 @@ cp -rf $current/nuttx $nuttx cp -rf $current/apps $nuttx cp -rf $nuttx/aiit_board/aiit-arm32-board $nuttx/nuttx/boards/arm/stm32 cp -rf $nuttx/aiit_board/aiit-riscv64-board $nuttx/nuttx/boards/risc-v/k210 +cp -rf $nuttx/aiit_board/xidatong $nuttx/nuttx/boards/arm/imxrt cd ../nuttx diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/Kconfig similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/Kconfig diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/Makefile similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/Makefile rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/Makefile diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/imxrt/chip.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/imxrt/chip.h new file mode 100644 index 000000000..26a96acae --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/imxrt/chip.h @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/arm/include/imxrt/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file chip.h +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H +#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A) + +/* MIMXRT1021CAG4A - 144 pin, 400MHz Industrial + * MIMXRT1021CAF4A - 100 pin, 400MHz Industrial + * MIMXRT1021DAF5A - 100 pin, 500MHz Consumer + * MIMXRT1021DAG5A - 144 pin, 500MHz Consumer + */ + +# define IMXRT_OCRAM_SIZE (256 * 1024) /* 256Kb OCRAM */ +# define IMXRT_GPIO_NPORTS 5 /* Five total ports */ + /* but 4 doesn't exist */ + +#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5B) +/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz + * MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz + * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz + * MIMXRT1052CVL5B - Industrial, Full Feature, 528MHz + * MIMXRT1052DVL6A - Consumer, Full Feature, 600MHz + */ + +# define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */ +# define IMXRT_GPIO_NPORTS 5 /* Five total ports */ + +#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1064DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1064CVL5A) +/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz + * MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz + * MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz + * MIMXRT1062DVL6A - Consumer, Full Feature, 600MHz + * MIMXRT1064CVL5A - Industrial, Full Feature, 528MHz + * MIMXRT1064DVL6A - Consumer, Full Feature, 600MHz + */ + +# define IMXRT_OCRAM_SIZE (1024 * 1024) /* 1024Kb OCRAM */ +# define IMXRT_GPIO_NPORTS 9 /* Nine total ports */ +#else +# error "Unknown i.MX RT chip type" +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds an 8-bit priority value, 0-15. The lower the + * value, the greater the priority of the corresponding interrupt. The i.MX + * RT processor implements only bits[7:4] of each field, bits[3:0] read as + * zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/Kconfig new file mode 100644 index 000000000..e46a53aa1 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/Kconfig @@ -0,0 +1,2013 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_IMXRT + +comment "i.MX RT Configuration Options" + +choice + prompt "i.MX RT Chip Selection" + default ARCH_CHIP_MIMXRT1052CVL5B + depends on ARCH_CHIP_IMXRT + +config ARCH_CHIP_MIMXRT1021CAG4A + bool "MIMXRT1021CAG4A" + select ARCH_FAMILY_MIMXRT1021C + +config ARCH_CHIP_MIMXRT1021CAF4A + bool "MIMXRT1021CAF4A" + select ARCH_FAMILY_MIMXRT1021C + +config ARCH_CHIP_MIMXRT1021DAF5A + bool "MIMXRT1021DAF5A" + select ARCH_FAMILY_MIMXRT1021D + +config ARCH_CHIP_MIMXRT1021DAG5A + bool "MIMXRT1021DAG5A" + select ARCH_FAMILY_MIMXRT1021D + +config ARCH_CHIP_MIMXRT1051DVL6A + bool "MIMXRT1051DVL6A" + select ARCH_FAMILY_MIMXRT105xDVL6A + +config ARCH_CHIP_MIMXRT1051CVL5A + bool "MIMXRT1051CVL5A" + select ARCH_FAMILY_MIMXRT105xCVL5A + +config ARCH_CHIP_MIMXRT1052DVL6A + bool "MIMXRT1052DVL6A" + select ARCH_FAMILY_MIMXRT105xDVL6A + select IMXRT_HAVE_LCD + +config ARCH_CHIP_MIMXRT1052CVL5A + bool "MIMXRT1052CVL5A" + select ARCH_FAMILY_MIMXRT105xCVL5A + select IMXRT_HAVE_LCD + +config ARCH_CHIP_MIMXRT1052CVL5B + bool "MIMXRT1052CVL5B" + select ARCH_FAMILY_MIMXRT105xCVL5B + select IMXRT_HAVE_LCD + +config ARCH_CHIP_MIMXRT1061DVL6A + bool "MIMXRT1061DVL6A" + select ARCH_FAMILY_MXRT106xDVL6A + +config ARCH_CHIP_MIMXRT1061CVL5A + bool "MIMXRT1061CVL5A" + select ARCH_FAMILY_MIMXRT106xCVL5A + +config ARCH_CHIP_MIMXRT1062DVL6A + bool "MIMXRT1062DVL6A" + select ARCH_FAMILY_MXRT106xDVL6A + select IMXRT_HAVE_LCD + +config ARCH_CHIP_MIMXRT1062CVL5A + bool "MIMXRT1062DVL6A" + select ARCH_FAMILY_MIMXRT106xCVL5A + select IMXRT_HAVE_LCD + +config ARCH_CHIP_MIMXRT1064DVL6A + bool "MIMXRT1064DVL6A" + select ARCH_FAMILY_MXRT106xDVL6A + select IMXRT_HAVE_LCD + +config ARCH_CHIP_MIMXRT1064CVL5A + bool "MIMXRT1064DVL6A" + select ARCH_FAMILY_MIMXRT106xCVL5A + select IMXRT_HAVE_LCD + +endchoice # i.MX RT Chip Selection + +# i.MX RT Families + +config ARCH_FAMILY_MIMXRT1021D + bool + default n + select ARCH_FAMILY_IMXRT102x + ---help--- + i.MX RT1020 Crossover Processors for Consumer Products + +config ARCH_FAMILY_MIMXRT1021C + bool + default n + select ARCH_FAMILY_IMXRT102x + ---help--- + i.MX RT1020 Crossover Processors for Industrial Products + +config ARCH_FAMILY_IMXRT102x + bool + default n + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + +config ARCH_FAMILY_MIMXRT105xDVL6A + bool + default n + select ARCH_FAMILY_IMXRT105x + ---help--- + i.MX RT1050 Crossover Processors for Consumer Products + +config ARCH_FAMILY_MIMXRT105xCVL5A + bool + default n + select ARCH_FAMILY_IMXRT105x + ---help--- + i.MX RT1050 Crossover Processors for Industrial Products + +config ARCH_FAMILY_MIMXRT105xCVL5B + bool + default n + select ARCH_FAMILY_IMXRT105x + ---help--- + i.MX RT1050 Crossover Processors for Industrial Products + +config ARCH_FAMILY_IMXRT105x + bool + default n + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + +config ARCH_FAMILY_MXRT106xDVL6A + bool + default n + select ARCH_FAMILY_IMXRT106x + ---help--- + i.MX RT1060 Crossover Processors for Consumer Products + +config ARCH_FAMILY_MIMXRT106xCVL5A + bool + default n + select ARCH_FAMILY_IMXRT106x + ---help--- + i.MX RT1056 Crossover Processors for Industrial Products + +config ARCH_FAMILY_IMXRT106x + bool + default n + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select IMXRT_HIGHSPEED_GPIO + +# Peripheral support + +config IMXRT_USDHC + bool + default n + +config IMXRT_FLEXIO + bool + default n + +config IMXRT_HAVE_LPUART + bool + default n + +config IMXRT_FLEXCAN + bool + default n + select ARCH_HAVE_NETDEV_STATISTICS + +config IMXRT_FLEXPWM + bool + default n + select ARCH_HAVE_PWM_MULTICHAN + +config IMXRT_LPI2C + bool + default n + +config IMXRT_LPSPI + bool + default n + +config IMXRT_FLEXSPI + bool + default n + +config IMXRT_ADC + bool + default n + +config IMXRT_ENC + bool + default n + +config IMXRT_HIGHSPEED_GPIO + bool + default n + +config IMXRT_HAVE_LCD + bool + default n + +config IMXRT_SEMC_INIT_DONE + bool + default n + +menu "i.MX RT Peripheral Selection" + +config IMXRT_EDMA + bool "eDMA" + default n + select ARCH_DMA + +config IMXRT_USBOTG + bool "USB EHCI" + default n + select USBHOST_HAVE_ASYNCH if USBHOST + select USBHOST_ASYNCH + +config IMXRT_USBDEV + bool "USB Device" + default n + +config IMXRT_ENET + bool "Ethernet" + default n + select ARCH_HAVE_PHY + select ARCH_PHY_INTERRUPT + select ARCH_HAVE_NETDEV_STATISTICS + +config IMXRT_LCD + bool "LCD controller" + default n + depends on IMXRT_HAVE_LCD + +config IMXRT_WDOG + bool "Watchdog 1" + default n + depends on WATCHDOG + +menu "FlexIO Peripherals" + +config IMXRT_FLEXIO1 + bool "FLEXIO1" + default n + select IMXRT_FLEXIO + +if IMXRT_FLEXIO1 + +choice + prompt "FLEXIO1 Clock Source" + default FLEXIO1_CLK_PLL3_SW + ---help--- + The clock source that drives the FLEXIO. + Used to set FLEXIO1_CLK_SEL. + +config FLEXIO1_CLK_PLL4 + bool "PLL4" + +config FLEXIO1_CLK_PLL3_PFD2 + bool "PLL3_PFD2" + +if ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +config FLEXIO1_CLK_PLL5 + bool "PLL5" + +endif # ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +config FLEXIO1_CLK_PLL3_SW + bool "PLL3_SW_CLK" + +endchoice # FLEXIO1 Clock Source + +config FLEXIO1_CLK + int + default 0 if FLEXIO1_CLK_PLL4 + default 1 if FLEXIO1_CLK_PLL3_PFD2 + default 2 if FLEXIO1_CLK_PLL5 + default 3 if FLEXIO1_CLK_PLL3_SW + +config FLEXIO1_PRED_DIVIDER + int "FLEXIO1 Predivider" + range 1 8 + default 2 + ---help--- + The clock source predivider value (FLEXIO1_PRED). [1-8] + +config FLEXIO1_PODF_DIVIDER + int "FLEXIO1 Divider" + range 1 8 + default 8 + ---help--- + The clock source divider value (FLEXIO1_PODF). [1-8] + +endif # IMXRT_FLEXIO1 + +if ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +config IMXRT_FLEXIO2 + bool "FLEXIO2" + default n + select IMXRT_FLEXIO + +if IMXRT_FLEXIO2 || IMXRT_FLEXIO3 + +choice + prompt "FLEXIO2 Clock Source" + default FLEXIO2_CLK_PLL3_SW + ---help--- + The clock source that drives the FLEXIO. + Used to set FLEXIO2_CLK_SEL. + +config FLEXIO2_CLK_PLL4 + bool "PLL4" + +config FLEXIO2_CLK_PLL3_PFD2 + bool "PLL3_PFD2" + +config FLEXIO2_CLK_PLL5 + bool "PLL5" + +config FLEXIO2_CLK_PLL3_SW + bool "PLL3_SW_CLK" + +endchoice # FLEXIO2 Clock Source + +config FLEXIO2_CLK + int + default 0 if FLEXIO2_CLK_PLL4 + default 1 if FLEXIO2_CLK_PLL3_PFD2 + default 2 if FLEXIO2_CLK_PLL5 + default 3 if FLEXIO2_CLK_PLL3_SW + +config FLEXIO2_PRED_DIVIDER + int + prompt "FLEXIO2 Predivider" + range 1 8 + default 2 + ---help--- + The clock source predivider value (FLEXIO2_PRED). [1-8] + +config FLEXIO2_PODF_DIVIDER + int + prompt "FLEXIO2 Divider" + range 1 8 + default 8 + ---help--- + The clock source divider value (FLEXIO2_PODF). [1-8] + +endif # IMXRT_FLEXIO2 || IMXRT_FLEXIO3 + +if ARCH_FAMILY_IMXRT106x + +config IMXRT_FLEXIO3 + bool "FLEXIO3" + default n + select IMXRT_FLEXIO + ---help--- + FLEXIO3 uses the FLEXIO2 clock settings. + +endif # ARCH_FAMILY_IMXRT106x +endif # ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +endmenu # FlexIO Peripherals + +menu "LPUART Peripherals" + +config IMXRT_LPUART1 + bool "LPUART1" + default n + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART2 + bool "LPUART2" + default n + select LPUART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART3 + bool "LPUART3" + default n + select LPUART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART4 + bool "LPUART4" + default n + select LPUART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART5 + bool "LPUART5" + default n + select LPUART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART6 + bool "LPUART6" + default n + select LPUART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART7 + bool "LPUART7" + default n + select LPUART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +config IMXRT_LPUART8 + bool "LPUART8" + default n + select LPUART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select IMXRT_HAVE_LPUART + +endmenu # LPUART Peripherals + +menu "LPUART Configuration" + depends on IMXRT_HAVE_LPUART + +config IMXRT_LPUART_INVERT + bool "Signal Invert Support" + default n + depends on IMXRT_HAVE_LPUART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the IMXRT serial driver. + +config IMXRT_LPUART_SINGLEWIRE + bool "Single Wire Support" + default n + depends on IMXRT_HAVE_LPUART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the IMXRT serial driver. + +endmenu # LPUART Configuration + +menu "FLEXCAN Peripherals" + +config IMXRT_FLEXCAN1 + bool "FLEXCAN1" + default n + select IMXRT_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + +config IMXRT_FLEXCAN2 + bool "FLEXCAN2" + default n + select IMXRT_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + +config IMXRT_FLEXCAN3 + bool "FLEXCAN3" + default n + select IMXRT_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + select NET_CAN_HAVE_CANFD + +if IMXRT_FLEXCAN1 || IMXRT_FLEXCAN2 || IMXRT_FLEXCAN3 + +config IMXRT_FLEXCAN_TXMB + int "Number of TX message buffers" + default 3 + ---help--- + This defines number of TX messages buffers. Please note that + maximum number of all message buffers is 13 (one MB has to + be reserved for chip errata ERR005829). + +config IMXRT_FLEXCAN_RXMB + int "Number of RX message buffers" + default 10 + ---help--- + This defines number of RX messages buffers. Please note that + maximum number of all message buffers is 13 (one MB has to + be reserved for chip errata ERR005829). + +endif + +endmenu # FLEXCAN Peripherals + +menu "FLEXCAN1 Configuration" + depends on IMXRT_FLEXCAN1 + +config FLEXCAN1_BITRATE + int "CAN bitrate" + default 1000000 + +config FLEXCAN1_SAMPLEP + int "CAN sample point" + default 80 + +endmenu # IMXRT_FLEXCAN1 + +menu "FLEXCAN2 Configuration" + depends on IMXRT_FLEXCAN2 + +config FLEXCAN2_BITRATE + int "CAN bitrate" + default 1000000 + +config FLEXCAN2_SAMPLEP + int "CAN sample point" + default 80 + +endmenu # IMXRT_FLEXCAN2 + +menu "FLEXCAN3 Configuration" + depends on IMXRT_FLEXCAN3 + +config FLEXCAN3_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FLEXCAN3_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config FLEXCAN3_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FLEXCAN3_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN3_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN3_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMXRT_FLEXCAN3 + +menu "FLEXPWM Peripherals" + +config IMXRT_FLEXPWM1 + bool "FLEXPWM1" + default n + select IMXRT_FLEXPWM + +config IMXRT_FLEXPWM2 + bool "FLEXPWM2" + default n + select IMXRT_FLEXPWM + +if ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +config IMXRT_FLEXPWM3 + bool "FLEXPWM3" + default n + select IMXRT_FLEXPWM + +config IMXRT_FLEXPWM4 + bool "FLEXPWM4" + default n + select IMXRT_FLEXPWM + +endif # ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +endmenu # FLEXPWM Peripherals + +menu "FLEXPWM1 Configuration" + depends on IMXRT_FLEXPWM1 + +config IMXRT_FLEXPWM1_MOD1 + bool "FLEXPWM1 Module 1" + default n + +if IMXRT_FLEXPWM1_MOD1 + +config IMXRT_FLEXPWM1_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM1_MOD2 + bool "FLEXPWM1 Module 2" + default n + +if IMXRT_FLEXPWM1_MOD2 + +config IMXRT_FLEXPWM1_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM1_MOD3 + bool "FLEXPWM1 Module 3" + default n + +if IMXRT_FLEXPWM1_MOD3 + +config IMXRT_FLEXPWM1_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM1_MOD4 + bool "FLEXPWM1 Module 4" + default n + +if IMXRT_FLEXPWM1_MOD4 + +config IMXRT_FLEXPWM1_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM1 + +menu "FLEXPWM2 Configuration" + depends on IMXRT_FLEXPWM2 + +config IMXRT_FLEXPWM2_MOD1 + bool "FLEXPWM2 Module 1" + default n + +if IMXRT_FLEXPWM2_MOD1 + +config IMXRT_FLEXPWM2_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM2_MOD2 + bool "FLEXPWM2 Module 2" + default n + +if IMXRT_FLEXPWM2_MOD2 + +config IMXRT_FLEXPWM2_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM2_MOD3 + bool "FLEXPWM2 Module 3" + default n + +if IMXRT_FLEXPWM2_MOD3 + +config IMXRT_FLEXPWM2_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM2_MOD4 + bool "FLEXPWM2 Module 4" + default n + +if IMXRT_FLEXPWM2_MOD4 + +config IMXRT_FLEXPWM2_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM2 + +menu "FLEXPWM3 Configuration" + depends on IMXRT_FLEXPWM3 + +config IMXRT_FLEXPWM3_MOD1 + bool "FLEXPWM3 Module 1" + default n + +if IMXRT_FLEXPWM3_MOD1 + +config IMXRT_FLEXPWM3_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM3_MOD2 + bool "FLEXPWM3 Module 2" + default n + +if IMXRT_FLEXPWM3_MOD2 + +config IMXRT_FLEXPWM3_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM3_MOD3 + bool "FLEXPWM3 Module 3" + default n + +if IMXRT_FLEXPWM3_MOD3 + +config IMXRT_FLEXPWM3_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM3_MOD4 + bool "FLEXPWM3 Module 4" + default n + +if IMXRT_FLEXPWM3_MOD4 + +config IMXRT_FLEXPWM3_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM3 + +menu "FLEXPWM4 Configuration" + depends on IMXRT_FLEXPWM4 + +config IMXRT_FLEXPWM4_MOD1 + bool "FLEXPWM4 Module 1" + default n + +if IMXRT_FLEXPWM4_MOD1 + +config IMXRT_FLEXPWM4_MOD1_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM4_MOD2 + bool "FLEXPWM4 Module 2" + default n + +if IMXRT_FLEXPWM4_MOD2 + +config IMXRT_FLEXPWM4_MOD2_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM4_MOD3 + bool "FLEXPWM4 Module 3" + default n + +if IMXRT_FLEXPWM4_MOD3 + +config IMXRT_FLEXPWM4_MOD3_COMP + bool "Use complementary output" + default n + +endif + +config IMXRT_FLEXPWM4_MOD4 + bool "FLEXPWM4 Module 4" + default n + +if IMXRT_FLEXPWM4_MOD4 + +config IMXRT_FLEXPWM4_MOD4_COMP + bool "Use complementary output" + default n + +endif + +endmenu # IMXRT_FLEXPWM4 + +menu "LPI2C Peripherals" + +menuconfig IMXRT_LPI2C1 + bool "LPI2C1" + default n + select IMXRT_LPI2C + +if IMXRT_LPI2C1 + +config LPI2C1_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config LPI2C1_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config LPI2C1_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMXRT_LPI2C1 + +menuconfig IMXRT_LPI2C2 + bool "LPI2C2" + default n + select IMXRT_LPI2C + +if IMXRT_LPI2C2 + +config LPI2C2_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config LPI2C2_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config LPI2C2_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMXRT_LPI2C2 + +menuconfig IMXRT_LPI2C3 + bool "LPI2C3" + default n + select IMXRT_LPI2C + +if IMXRT_LPI2C3 + +config LPI2C3_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config LPI2C3_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config LPI2C3_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMXRT_LPI2C3 + +menuconfig IMXRT_LPI2C4 + bool "LPI2C4" + default n + select IMXRT_LPI2C + +if IMXRT_LPI2C4 + +config LPI2C4_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config LPI2C4_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config LPI2C4_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMXRT_LPI2C4 +endmenu # LPI2C Peripherals + +menu "LPSPI Peripherals" + +menuconfig IMXRT_LPSPI1 + bool "LPSPI1" + default n + select IMXRT_LPSPI + +menuconfig IMXRT_LPSPI2 + bool "LPSPI2" + default n + select IMXRT_LPSPI + +menuconfig IMXRT_LPSPI3 + bool "LPSPI3" + default n + select IMXRT_LPSPI + +menuconfig IMXRT_LPSPI4 + bool "LPSPI4" + default n + select IMXRT_LPSPI + +endmenu # LPSPI Peripherals + +menu "FLEXSPI Peripherals" + +menuconfig IMXRT_FLEXSPI1 + bool "FLEXSPI1" + default n + select IMXRT_FLEXSPI + +endmenu # FLEXSPI Peripherals + +menu "ADC Peripherals" + +menuconfig IMXRT_ADC1 + bool "ADC1" + default n + select IMXRT_ADC + +menuconfig IMXRT_ADC2 + bool "ADC2" + default n + select IMXRT_ADC + +endmenu + +config IMXRT_SEMC + bool "Smart External Memory Controller (SEMC)" + default n + +config IMXRT_SNVS_LPSRTC + bool "LP SRTC" + default n + select IMXRT_SNVS_HPRTC + +config IMXRT_SNVS_HPRTC + bool "HP RTC" + default n + +config IMXRT_USDHC1 + bool "USDHC1" + default n + select ARCH_HAVE_SDIO + select IMXRT_USDHC + ---help--- + Support USDHC host controller 1 + +config IMXRT_USDHC2 + bool "USDHC2" + default n + select ARCH_HAVE_SDIO + select IMXRT_USDHC + ---help--- + Support USDHC host controller 2 + +menu "ENC Peripherals" + +menuconfig IMXRT_ENC1 + bool "ENC1" + default n + select IMXRT_ENC + +if IMXRT_ENC1 + +config ENC1_INITVAL + int "Initial position counter value" + default 0 + +config ENC1_DIR + bool "Reverse positive rotation direction" + default n + ---help--- + Select if PHASEB leading PHASEA pulses is positive rotation + +config ENC1_FILTPER + int "Input filter sample period in clock cycles" + default 0 + +config ENC1_FILTCNT + int "Number of input samples that filter will compare" + default 0 + +config ENC1_MOD + bool "Enable modulo counting" + default n + +if ENC1_MOD + +config ENC1_MODULUS + hex "Modulus to wrap around" + default 0xffffffff + +endif # ENC1_MOD + +config ENC1_HIP + bool "HOME signal initializes position counter" + default n + +if ENC1_HIP + +config ENC1_HNE + bool "Initialize on negedge of HOME" + default n + +endif # ENC1_HIP + +config ENC1_XIP + bool "INDEX signal initializes position counter" + default n + +if ENC1_XIP + +config ENC1_XNE + bool "Initialize on negedge of INDEX" + default n + +endif # ENC1_XIP + +if DEBUG_SENSORS + +config ENC1_TST_DIR + bool "Generate negative test counter advances" + default n + +config ENC1_TST_PER + int "Period of test pulses in clock cycles" + default 31 + +endif # DEBUG_SENSORS + +endif # IMXRT_ENC1 + +menuconfig IMXRT_ENC2 + bool "ENC2" + default n + select IMXRT_ENC + +if IMXRT_ENC2 + +config ENC2_INITVAL + int "Initial position counter value" + default 0 + +config ENC2_DIR + bool "Reverse positive rotation direction" + default n + ---help--- + Select if PHASEB leading PHASEA pulses is positive rotation + +config ENC2_FILTPER + int "Input filter sample period in clock cycles" + default 0 + +config ENC2_FILTCNT + int "Number of input samples that filter will compare" + default 0 + +config ENC2_MOD + bool "Enable modulo counting" + default n + +if ENC2_MOD + +config ENC2_MODULUS + hex "Modulus to wrap around" + default 0xffffffff + +endif # ENC2_MOD + +config ENC2_HIP + bool "HOME signal initializes position counter" + default n + +if ENC2_HIP + +config ENC2_HNE + bool "Initialize on negedge of HOME" + default n + +endif # ENC2_HIP + +config ENC2_XIP + bool "INDEX signal initializes position counter" + default n + +if ENC2_XIP + +config ENC2_XNE + bool "Initialize on negedge of INDEX" + default n + +endif # ENC2_XIP + +if DEBUG_SENSORS + +config ENC2_TST_DIR + bool "Generate negative test counter advances" + default n + +config ENC2_TST_PER + int "Period of test pulses in clock cycles" + default 31 + +endif # DEBUG_SENSORS + +endif # IMXRT_ENC2 + +if ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +menuconfig IMXRT_ENC3 + bool "ENC3" + default n + select IMXRT_ENC + +if IMXRT_ENC3 + +config ENC3_INITVAL + int "Initial position counter value" + default 0 + +config ENC3_DIR + bool "Reverse positive rotation direction" + default n + ---help--- + Select if PHASEB leading PHASEA pulses is positive rotation + +config ENC3_FILTPER + int "Input filter sample period in clock cycles" + default 0 + +config ENC3_FILTCNT + int "Number of input samples that filter will compare" + default 0 + +config ENC3_MOD + bool "Enable modulo counting" + default n + +if ENC3_MOD + +config ENC3_MODULUS + hex "Modulus to wrap around" + default 0xffffffff + +endif # ENC3_MOD + +config ENC3_HIP + bool "HOME signal initializes position counter" + default n + +if ENC3_HIP + +config ENC3_HNE + bool "Initialize on negedge of HOME" + default n + +endif # ENC3_HIP + +config ENC3_XIP + bool "INDEX signal initializes position counter" + default n + +if ENC3_XIP + +config ENC3_XNE + bool "Initialize on negedge of INDEX" + default n + +endif # ENC3_XIP + +if DEBUG_SENSORS + +config ENC3_TST_DIR + bool "Generate negative test counter advances" + default n + +config ENC3_TST_PER + int "Period of test pulses in clock cycles" + default 31 + +endif # DEBUG_SENSORS + +endif # IMXRT_ENC3 + +menuconfig IMXRT_ENC4 + bool "ENC4" + default n + select IMXRT_ENC + +if IMXRT_ENC4 + +config ENC4_INITVAL + int "Initial position counter value" + default 0 + +config ENC4_DIR + bool "Reverse positive rotation direction" + default n + ---help--- + Select if PHASEB leading PHASEA pulses is positive rotation + +config ENC4_FILTPER + int "Input filter sample period in clock cycles" + default 0 + +config ENC4_FILTCNT + int "Number of input samples that filter will compare" + default 0 + +config ENC4_MOD + bool "Enable modulo counting" + default n + +if ENC4_MOD + +config ENC4_MODULUS + hex "Modulus to wrap around" + default 0xffffffff + +endif # ENC4_MOD + +config ENC4_HIP + bool "HOME signal initializes position counter" + default n + +if ENC4_HIP + +config ENC4_HNE + bool "Initialize on negedge of HOME" + default n + +endif # ENC4_HIP + +config ENC4_XIP + bool "INDEX signal initializes position counter" + default n + +if ENC4_XIP + +config ENC4_XNE + bool "Initialize on negedge of INDEX" + default n + +endif # ENC4_XIP + +if DEBUG_SENSORS + +config ENC4_TST_DIR + bool "Generate negative test counter advances" + default n + +config ENC4_TST_PER + int "Period of test pulses in clock cycles" + default 31 + +endif # DEBUG_SENSORS + +endif # IMXRT_ENC4 + +endif # ARCH_FAMILY_IMXRT105x || ARCH_FAMILY_IMXRT106x + +endmenu # ENC Peripherals + +endmenu # i.MX RT Peripheral Selection + +menuconfig IMXRT_GPIO_IRQ + bool "GPIO Interrupt Support" + default n + +if IMXRT_GPIO_IRQ + +config IMXRT_GPIO1_0_15_IRQ + bool "GPIO1 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO1_16_31_IRQ + bool "GPIO1 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO2_0_15_IRQ + bool "GPIO2 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO2_16_31_IRQ + bool "GPIO2 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO3_0_15_IRQ + bool "GPIO3 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO3_16_31_IRQ + bool "GPIO3 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO4_0_15_IRQ + bool "GPIO4 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO4_16_31_IRQ + bool "GPIO4 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO5_0_15_IRQ + bool "GPIO5 Pins 0-15 interrupts" + default n + +config IMXRT_GPIO5_16_31_IRQ + bool "GPIO5 Pins 16-31 interrupts" + default n + +config IMXRT_GPIO6_0_15_IRQ + bool "GPIO6 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO6_16_31_IRQ + bool "GPIO6 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO7_0_15_IRQ + bool "GPIO7 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO7_16_31_IRQ + bool "GPIO7 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO8_0_15_IRQ + bool "GPIO8 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO8_16_31_IRQ + bool "GPIO8 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO9_0_15_IRQ + bool "GPIO9 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO9_16_31_IRQ + bool "GPIO9 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +endif # IMXRT_GPIO_IRQ + +menu "Ethernet Configuration" + depends on IMXRT_ENET + +config IMXRT_ENET_NRXBUFFERS + int "Number Rx buffers" + default 6 + +config IMXRT_ENET_NTXBUFFERS + int "Number Tx buffers" + default 2 + +config IMXRT_ENET_ENHANCEDBD + bool # not optional + default n + +config IMXRT_ENET_NETHIFS + int # Not optional + default 1 + +config IMXRT_ENET_PHYINIT + bool "Board-specific PHY Initialization" + default n + ---help--- + Some boards require specialized initialization of the PHY before it + can be used. This may include such things as configuring GPIOs, + resetting the PHY, etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in + the configuration then the board specific logic must provide + imxrt_phy_boardinitialize(); The i.MXRT ENET driver will call this + function one time before it first uses the PHY. + +endmenu # IMXRT_ENET + +menu "Memory Configuration" + +config IMXRT_DTCM + int "FLEXRAM DTCM Size in K" + default 128 + depends on ARMV7M_HAVE_DTCM + +config IMXRT_ITCM + int "FLEXRAM ITCM Size in K" + default 128 + depends on ARMV7M_HAVE_ITCM + +config IMXRT_SEMC_SDRAM + bool "External SDRAM installed" + default n + depends on IMXRT_SEMC + +if IMXRT_SEMC_SDRAM + +config IMXRT_SDRAM_START + hex "SDRAM start address" + default 0x10000000 + +config IMXRT_SDRAM_SIZE + int "SDRAM size (bytes)" + default 268435456 + +endif # IMXRT_SEMC_SDRAM + +config IMXRT_SEMC_SRAM + bool "External SRAM installed" + default n + depends on IMXRT_SEMC + +if IMXRT_SEMC_SRAM + +config IMXRT_SRAM_START + hex "SRAM start address" + default 0x10000000 + +config IMXRT_SRAM_SIZE + int "SRAM size (bytes)" + default 268435456 + +endif # IMXRT_SRAM_SIZE + +config IMXRT_SEMC_NOR + bool "External NOR FLASH installed" + default n + depends on IMXRT_SEMC + +choice + prompt "i.MX RT Boot Configuration" + default IMXRT_BOOT_NOR if IMXRT_SEMC_NOR + default IMXRT_BOOT_SDRAM if IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR + default IMXRT_BOOT_SRAM if IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR + default IMXRT_BOOT_OCRAM if !IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR + ---help--- + The startup code needs to know if the code is running from internal + OCRAM, external SDRAM, external NOR, or external SDRAM in order to + initialize properly. Note that the boot device is not known for + cases where the code is copied into RAM by a bootloader. + +config IMXRT_BOOT_OCRAM + bool "Running from internal OCRAM" + select BOOT_RUNFROMISRAM + +config IMXRT_BOOT_SDRAM + bool "Running from external SDRAM" + select BOOT_RUNFROMSDRAM + depends on IMXRT_SEMC_SDRAM + +config IMXRT_BOOT_NOR + bool "Running from external NOR FLASH" + select BOOT_RUNFROMFLASH + depends on IMXRT_SEMC_NOR + +config IMXRT_BOOT_SRAM + bool "Running from external SRAM" + select BOOT_RUNFROMEXTSRAM + depends on IMXRT_SEMC_SRAM + +endchoice # i.MX RT Boot Configuration + +choice + prompt "i.MX RT Primary RAM" + default IMXRT_OCRAM_PRIMARY + ---help--- + The primary RAM is the RAM that contains the system BLOB's .data and + .bss. The unused portion of the primary RAM will automatically be + added to the system heap. + +config IMXRT_OCRAM_PRIMARY + bool "Internal OCRAM primary" + +config IMXRT_SDRAM_PRIMARY + bool "External SDRAM primary" + depends on IMXRT_SEMC_SDRAM + +config IMXRT_SRAM_PRIMARY + bool "External SRAM primary" + depends on IMXRT_SEMC_SRAM + +endchoice # i.MX RT Primary RAM + +menu "i.MX RT Heap Configuration" + +config IMXRT_OCRAM_HEAP + bool "Add OCRAM to heap" + depends on !IMXRT_OCRAM_PRIMARY + ---help--- + Select to add the entire OCRAM to the heap + +config IMXRT_DTCM_HEAP + bool "Add DTCM to heap" + depends on IMXRT_DTCM > 0 + ---help--- + Select to add the entire DTCM to the heap + +config IMXRT_BOOTLOADER_HEAP + bool "Add ROM bootloader 40Kib RAM to heap" + default false + depends on BOOT_RUNFROMISRAM + ---help--- + Select to add the memory used by the ROM bootloader to heap + +config IMXRT_SDRAM_HEAP + bool "Add SDRAM to heap" + depends on IMXRT_SEMC_SDRAM && !IMXRT_SDRAM_PRIMARY + ---help--- + Add a region of SDRAM to the heap. A region of SDRAM will be added + to the heap that starts at (CONFIG_IMXRT_SDRAM_START + + CONFIG_IMXRT_SDRAM_HEAPOFFSET) and extends up to + (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_SIZE). Note that the + START is the actual start of SDRAM but SIZE is not necessarily the + actual SIZE. + +config IMXRT_SDRAM_HEAPOFFSET + hex "SDRAM heap offset" + default 0x0 + depends on IMXRT_SDRAM_HEAP + ---help--- + Used to reserve memory at the beginning of SDRAM for, as an example, + a framebuffer. + +config IMXRT_SRAM_HEAP + bool "Add SRAM to heap" + depends on IMXRT_SEMC_SRAM && !IMXRT_SRAM_PRIMARY + ---help--- + Add a region of SRAM to the heap. A region of SDRAM will be added + to the heap that starts at (CONFIG_IMXRT_SRAM_START + + CONFIG_IMXRT_SRAM_HEAPOFFSET) and extends up to + (CONFIG_IMXRT_SRAM_START + CONFIG_IMXRT_SRAM_SIZE). Note that the + START is the actual start of SRAM but SIZE is not necessarily the + actual SIZE. + +config IMXRT_SRAM_HEAPOFFSET + hex "SRAM heap offset" + default 0x0 + depends on IMXRT_SRAM_HEAP + ---help--- + Used to reserve memory at the beginning of SRAM for, as an example, + a framebuffer. + +endmenu # i.MX RT Heap Configuration +endmenu # Memory Configuration + +menu "LPI2C Configuration" + depends on IMXRT_LPI2C + +config IMXRT_LPI2C_DYNTIMEO + bool "Use dynamic timeouts" + default n + depends on IMXRT_LPI2C + +config IMXRT_LPI2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + default 500 + depends on IMXRT_LPI2C_DYNTIMEO + +config IMXRT_LPI2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + default 1000 + depends on IMXRT_LPI2C_DYNTIMEO + +config IMXRT_LPI2C_TIMEOSEC + int "Timeout seconds" + default 0 + depends on IMXRT_LPI2C + +config IMXRT_LPI2C_TIMEOMS + int "Timeout Milliseconds" + default 500 + depends on IMXRT_LPI2C && !IMXRT_LPI2C_DYNTIMEO + +config IMXRT_LPI2C_TIMEOTICKS + int "Timeout for Done and Stop (ticks)" + default 500 + depends on IMXRT_LPI2C && !IMXRT_LPI2C_DYNTIMEO + +endmenu # LPI2C Configuration + +menu "USDHC Configuration" + depends on IMXRT_USDHC + +config IMXRT_USDHC_DMA + bool "Support DMA data transfers" + default y + select SDIO_DMA + ---help--- + Support DMA data transfers. + Enable SD card DMA data transfers. This is marginally optional. + For most usages, SD accesses will cause data overruns if used without + DMA. + +choice + prompt "Bus width for USDHC1" + default IMXRT_USDHC1_WIDTH_D1_ONLY + depends on IMXRT_USDHC1 + +config IMXRT_USDHC1_WIDTH_D1_ONLY + bool "One bit" + +config IMXRT_USDHC1_WIDTH_D1_D4 + bool "Four bit" +endchoice + +config IMXRT_USDHC1_INVERT_CD + bool "Invert the USDHC1 CD" + default n + depends on IMXRT_USDHC1 + ---help--- + If the board defines PIN_USDHC1_CD the CD_B input to the USDHC it is + assumed to be active low. Selecting IMXRT_USDHC1_INVERT_CD will make it + active high. + + If the board defines PIN_USDHC1_CD_GPIO it is assumed to be active low. + Selecting IMXRT_USDHC1_INVERT_CD will make it active high. + +choice + depends on IMXRT_USDHC2 + prompt "Bus width for USDHC2" + default IMXRT_USDHC2_WIDTH_D1_D4 + +config IMXRT_USDHC2_WIDTH_D1_ONLY + bool "One bit" + +config IMXRT_USDHC2_WIDTH_D1_D4 + bool "Four bit" + +config IMXRT_USDHC2_WIDTH_D1_D8 + bool "Eight bit" +endchoice + +config IMXRT_USDHC2_INVERT_CD + bool "Invert the USDHC2 CD" + default n + depends on IMXRT_USDHC2 + ---help--- + If the board defines PIN_USDHC2_CD the CD_B input to the USDHC it is + assumed to be active low. Selecting IMXRT_USDHC_INVERT_CD will make it + active high. + + If the board defines PIN_USDHC2_CD_GPIO it is assumed to be active low. + Selecting IMXRT_USDHC2_INVERT_CD will make it active high. + +endmenu # USDHC Configuration + +menu "eDMA Configuration" + depends on IMXRT_EDMA + +config IMXRT_EDMA_NTCD + int "Number of transfer descriptors" + default 0 + ---help--- + Number of pre-allocated transfer descriptors. Needed for scatter- + gather DMA. Make to be set to zero to disable in-memory TCDs in + which case only the TCD channel registers will be used and scatter- + will not be supported. + +config IMXRT_EDMA_ELINK + bool "Channeling Linking" + default n + ---help--- + This option enables optional minor or major loop channel linking: + + Minor loop channel linking: As the channel completes the minor + loop, this flag enables linking to another channel. The link target + channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the specified + channel. + + If minor loop channel linking is disabled, this link mechanism is + suppressed in favor of the major loop channel linking. + + Major loop channel linking: As the channel completes the minor + loop, this option enables the linking to another channel. The link + target channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the linked channel. + +config IMXRT_EDMA_ERCA + bool "Round Robin Channel Arbitration" + default n + ---help--- + Normally, a fixed priority arbitration is used for channel + selection. If this option is selected, round robin arbitration is + used for channel selection. + +config IMXRT_EDMA_HOE + bool "Halt On Error" + default y + ---help--- + Any error causes the HALT bit to set. Subsequently, all service + requests are ignored until the HALT bit is cleared. + +config IMXRT_EDMA_CLM + bool "Continuous Link Mode" + default n + ---help--- + By default, A minor loop channel link made to itself goes through + channel arbitration before being activated again. If this option is + selected, a minor loop channel link made to itself does not go + through channel arbitration before being activated again. Upon minor + loop completion, the channel activates again if that channel has a + minor loop channel link enabled and the link channel is itself. This + effectively applies the minor loop offsets and restarts the next + minor loop. + +config IMXRT_EDMA_EMLIM + bool "Minor Loop Mapping" + default n + ---help--- + Normally TCD word 2 is a 32-bit NBYTES field. When this option is + enabled, TCD word 2 is redefined to include individual enable fields, + an offset field, and the NBYTES field. The individual enable fields + allow the minor loop offset to be applied to the source address, the + destination address, or both. The NBYTES field is reduced when either + offset is enabled. + +config IMXRT_EDMA_EDBG + bool "Enable Debug" + default n + ---help--- + When in debug mode, the DMA stalls the start of a new channel. Executing + channels are allowed to complete. Channel execution resumes when the + system exits debug mode or the EDBG bit is cleared + +endmenu # eDMA Global Configuration + +if PM + +config IMXRT_PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +endif + +menu "RTC Configuration" + depends on IMXRT_SNVS_HPRTC + +config IMXRT_RTC_MAGIC_REG + int "RTC SNVS GPR" + default 0 + range 0 3 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config IMXRT_RTC_MAGIC + hex "RTC Magic 1" + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +endmenu + +menu "LCD Configuration" + depends on IMXRT_LCD + +config IMXRT_LCD_VIDEO_PLL_FREQ + int "Video PLL Frequency" + default 92000000 + range 41500000 1300000000 + ---help--- + Frequency of Video PLL. + +config IMXRT_LCD_VRAMBASE + hex "Video RAM base address" + default 0x80000000 + ---help--- + Base address of the video RAM frame buffer. + Default: SDRAM + +config IMXRT_LCD_REFRESH_FREQ + int "LCD refresh rate (Hz)" + default 60 + ---help--- + LCD refresh rate (Hz) + +config IMXRT_LCD_BACKLIGHT + bool "Enable backlight" + default y + ---help--- + Enable backlight support. If IMXRT_LCD_BACKLIGHT is selected, then + the board-specific logic must provide this IMXRT_backlight() + interface so that the LCD driver can turn the backlight on and off + as necessary. You should select this option and implement + IMXRT_backlight() if your board provides GPIO control over the + backlight. This interface provides only ON/OFF control of the + backlight. If you want finer control over the backlight level (for + example, using PWM), then this interface would need to be extended. + +choice + prompt "Input Bits per pixel" + default IMXRT_LCD_INPUT_BPP16 + +config IMXRT_LCD_INPUT_BPP8_LUT + bool "8 BPP Color Map" + select FB_CMAP + +config IMXRT_LCD_INPUT_BPP8 + bool "8 BPP RGB_332" + +config IMXRT_LCD_INPUT_BPP15 + bool "16 BPP RGB_555" + +config IMXRT_LCD_INPUT_BPP16 + bool "16 BPP RGB_565" + +config IMXRT_LCD_INPUT_BPP24 + bool "24 BPP RGB_888" + +config IMXRT_LCD_INPUT_BPP32 + bool "32 BPP RGB_0888" + +endchoice + +config IMXRT_LCD_BGR + bool "Blue-Green-Red color order" + default n + ---help--- + This option selects BGR color order vs. default RGB + +choice + prompt "Output Bus width" + default IMXRT_LCD_OUTPUT_16 + +config IMXRT_LCD_OUTPUT_8 + bool "8 Bit LCD Bus" + +config IMXRT_LCD_OUTPUT_16 + bool "16 Bit LCD Bus" + +config IMXRT_LCD_OUTPUT_18 + bool "18 Bit LCD Bus" + +config IMXRT_LCD_OUTPUT_24 + bool "24 Bit LCD Bus" + +endchoice + +config IMXRT_LCD_BACKCOLOR + hex "Initial background color" + default 0x0 + ---help--- + Initial background color + +config IMXRT_LCD_HWIDTH + int "Display width (pixels)" + default 480 + ---help--- + Horizontal width the display in pixels + +config IMXRT_LCD_HPULSE + int "Horizontal pulse" + default 41 + +config IMXRT_LCD_HFRONTPORCH + int "Horizontal front porch" + default 4 + +config IMXRT_LCD_HBACKPORCH + int "Horizontal back porch" + default 8 + +config IMXRT_LCD_VHEIGHT + int "Display height (rows)" + default 272 + ---help--- + Vertical height of the display in rows + +config IMXRT_LCD_VPULSE + int "Vertical pulse" + default 10 + +config IMXRT_LCD_VFRONTPORCH + int "Vertical front porch" + default 4 + +config IMXRT_LCD_VBACKPORCH + int "Vertical back porch" + default 2 + +config IMXRT_VSYNC_ACTIVE_HIGH + bool "V-sync active high" + default n + +config IMXRT_HSYNC_ACTIVE_HIGH + bool "H-sync active high" + default n + +config IMXRT_DATAEN_ACTIVE_HIGH + bool "Data enable active high" + default y + +config IMXRT_DATA_RISING_EDGE + bool "Data clock rising edge" + default y + +endmenu # LCD Configuration + +menu "Timer Configuration" + +if SCHED_TICKLESS + +config IMXRT_TICKLESS_TIMER + int "Tickless hardware timer" + default 1 + range 1 2 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the GPT timer needed by the OS. + +config IMXRT_TICKLESS_CHANNEL + int "Tickless timer channel" + default 1 + range 1 3 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +endif # SCHED_TICKLESS + +endmenu # Timer Configuration + +if IMXRT_USBOTG && USBHOST + +menu "USB host controller driver (HCD) options" + +config IMXRT_EHCI_NQHS + int "Number of Queue Head (QH) structures" + default 4 + ---help--- + Configurable number of Queue Head (QH) structures. The default is + one per Root hub port plus one for EP0 (4). + +config IMXRT_EHCI_NQTDS + int "Number of Queue Element Transfer Descriptor (qTDs)" + default 6 + ---help--- + Configurable number of Queue Element Transfer Descriptor (qTDs). + The default is one per root hub plus three from EP0 (6). + +config IMXRT_EHCI_BUFSIZE + int "Size of one request/descriptor buffer" + default 128 + ---help--- + The size of one request/descriptor buffer in bytes. The TD buffe + size must be an even number of 32-bit words and must be large enough + to hangle the largest transfer via a SETUP request. + +config IMXRT_EHCI_PREALLOCATE + bool "Preallocate descriptor pool" + default y + ---help--- + Select this option to pre-allocate EHCI queue and descriptor + structure pools in .bss. Otherwise, these pools will be + dynamically allocated using kmm_memalign(). + +endmenu # USB host controller driver (HCD) options +endif # IMXRT_USBOTG && USBHOST + +if IMXRT_USBDEV + +menu "USB device controller driver (DCD) options" + +config IMXRT_USBDEV_NOVBUS + bool "No USB VBUS sensing" + default n + +config IMXRT_USBDEV_FRAME_INTERRUPT + bool "USB frame interrupt" + default n + ---help--- + Handle USB Start-Of-Frame events. Enable reading SOF from interrupt + handler vs. simply reading on demand. Probably a bad idea... Unless + there is some issue with sampling the SOF from hardware asynchronously. + +config IMXRT_USBDEV_REGDEBUG + bool "Register level debug" + depends on DEBUG_USB_INFO + default n + ---help--- + Output detailed register-level USB device debug information. Requires + also CONFIG_DEBUG_USB_INFO. + +endmenu # USB device controller driver (DCD) options +endif # IMXRT_USBDEV + +endif # ARCH_CHIP_IMXRT diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_serial.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_serial.c new file mode 100644 index 000000000..895084b09 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_serial.c @@ -0,0 +1,1844 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file imxrt_serial.c +* @brief nuttx source code +* https://github.com/apache/incubator-nuttx.git +* @version 10.2.0 +* @author AIIT XUOS Lab +* @date 2022-03-23 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_arch.h" +#include "arm_internal.h" + +#include "hardware/imxrt_lpuart.h" +#include "imxrt_gpio.h" +#include "hardware/imxrt_pinmux.h" +#include "imxrt_config.h" +#include "imxrt_lowputc.h" + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Which LPUART with be tty0/console and which tty1-7? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of LPUART1-8 */ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* LPUART1 is console */ +# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* LPUART2 is console */ +# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* LPUART3 is console */ +# define TTYS0_DEV g_uart3port /* LPUART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* LPUART4 is console */ +# define TTYS0_DEV g_uart4port /* LPUART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5port /* LPUART5 is console */ +# define TTYS0_DEV g_uart5port /* LPUART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart6port /* LPUART6 is console */ +# define TTYS0_DEV g_uart6port /* LPUART6 is ttyS0 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart7port /* LPUART7 is console */ +# define TTYS0_DEV g_uart7port /* LPUART7 is ttyS0 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart8port /* LPUART8 is console */ +# define TTYS0_DEV g_uart8port /* LPUART8 is ttyS0 */ +# define UART8_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_IMXRT_LPUART1) +# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART2) +# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART3) +# define TTYS0_DEV g_uart3port /* LPUART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART4) +# define TTYS0_DEV g_uart4port /* LPUART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART5) +# define TTYS0_DEV g_uart5port /* LPUART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART6) +# define TTYS0_DEV g_uart6port /* LPUART6 is ttyS0 */ +# define UART6_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART7) +# define TTYS0_DEV g_uart7port /* LPUART7 is ttyS0 */ +# define UART7_ASSIGNED 1 +# elif defined(CONFIG_IMXRT_LPUART8) +# define TTYS0_DEV g_uart8port /* LPUART8 is ttyS0 */ +# define UART8_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of UART1-8 excluding the console UART. + * One of UART1-8 could be the console; one of UART1-8 has already been + * assigned to ttys0. + */ + +#if defined(CONFIG_IMXRT_LPUART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* LPUART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART2) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* LPUART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART3) && !defined(UART3_ASSIGNED) +# define TTYS1_DEV g_uart3port /* LPUART3 is ttyS1 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS1_DEV g_uart4port /* LPUART4 is ttyS1 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS1_DEV g_uart5port /* LPUART5 is ttyS1 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS1_DEV g_uart6port /* LPUART6 is ttyS1 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS1_DEV g_uart7port /* LPUART7 is ttyS1 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS1_DEV g_uart8port /* LPUART8 is ttyS1 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART2-8. It can't be UART1 because that + * was either assigned as ttyS0 or ttys1. One of UART 1-8 could be the + * console. One of UART2-8 has already been assigned to ttys0 or ttyS1. + */ + +#if defined(CONFIG_IMXRT_LPUART2) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* LPUART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART3) && !defined(UART3_ASSIGNED) +# define TTYS2_DEV g_uart3port /* LPUART3 is ttyS2 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS2_DEV g_uart4port /* LPUART4 is ttyS2 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS2_DEV g_uart5port /* LPUART5 is ttyS2 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS2_DEV g_uart6port /* LPUART6 is ttyS2 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS2_DEV g_uart7port /* LPUART7 is ttyS2 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS2_DEV g_uart8port /* LPUART8 is ttyS2 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of UART3-8. It can't be UART1-2 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * UART3-8 could also be the console. One of UART3-8 has already + * been assigned to ttys0, 1, or 3. + */ + +#if defined(CONFIG_IMXRT_LPUART3) && !defined(UART3_ASSIGNED) +# define TTYS3_DEV g_uart3port /* LPUART3 is ttyS3 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS3_DEV g_uart4port /* LPUART4 is ttyS3 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS3_DEV g_uart5port /* LPUART5 is ttyS3 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS3_DEV g_uart6port /* LPUART6 is ttyS3 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS3_DEV g_uart7port /* LPUART7 is ttyS3 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS3_DEV g_uart8port /* LPUART8 is ttyS3 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of UART4-8. It can't be UART1-3 because + * those have already been assigned to ttsyS0, 1, 2 or 3. One of + * UART 4-8 could be the console. One of UART4-8 has already been + * assigned to ttys0, 1, 3, or 4. + */ + +#if defined(CONFIG_IMXRT_LPUART4) && !defined(UART4_ASSIGNED) +# define TTYS4_DEV g_uart4port /* LPUART4 is ttyS4 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS4_DEV g_uart5port /* LPUART5 is ttyS4 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS4_DEV g_uart6port /* LPUART6 is ttyS4 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS4_DEV g_uart7port /* LPUART7 is ttyS4 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS4_DEV g_uart8port /* LPUART8 is ttyS4 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of UART5-8. It can't be UART1-4 because + * those have already been assigned to ttsyS0, 1, 2, 3 or 4. One of + * UART 5-8 could be the console. One of UART5-8 has already been + * assigned to ttys0, 1, 2, 3, or 4. + */ + +#if defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) +# define TTYS5_DEV g_uart5port /* LPUART5 is ttyS5 */ +# define UART5_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS5_DEV g_uart6port /* LPUART6 is ttyS5 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS5_DEV g_uart7port /* LPUART7 is ttyS5 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS5_DEV g_uart8port /* LPUART8 is ttyS5 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys6. This could be one of UART6-8. It can't be UART1-5 because + * those have already been assigned to ttsyS0, 1, 2, 3, 4 or 5. One of + * UART 6-8 could be the console. One of UART6-8 has already been + * assigned to ttys0, 1, 2, 3, 4 or 5. + */ + +#if defined(CONFIG_IMXRT_LPUART6) && !defined(UART6_ASSIGNED) +# define TTYS6_DEV g_uart6port /* LPUART6 is ttyS5 */ +# define UART6_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS6_DEV g_uart7port /* LPUART7 is ttyS5 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS6_DEV g_uart8port /* LPUART8 is ttyS5 */ +# define UART8_ASSIGNED 1 +#endif + +/* Pick ttys7. This could be one of UART7-8. It can't be UART1-6 because + * those have already been assigned to ttsyS0, 1, 2, 3, 4, 5 or 6. One of + * UART 7-8 could be the console. One of UART7-8 has already been + * assigned to ttys0, 1, 2, 3, 4, 5 or 6. + */ + +#if defined(CONFIG_IMXRT_LPUART7) && !defined(UART7_ASSIGNED) +# define TTYS7_DEV g_uart7port /* LPUART7 is ttyS5 */ +# define UART7_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_LPUART8) && !defined(UART8_ASSIGNED) +# define TTYS7_DEV g_uart8port /* LPUART8 is ttyS5 */ +# define UART8_ASSIGNED 1 +#endif + +/* UART, if available, should have been assigned to ttyS0-7. */ + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_IMXRT_PM_SERIAL_ACTIVITY) +# define CONFIG_IMXRT_PM_SERIAL_ACTIVITY 10 +#endif + +#if defined(CONFIG_PM) +# define PM_IDLE_DOMAIN 0 /* Revisit */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrt_uart_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t ie; /* Saved enabled interrupts */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ +#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) + uint8_t inviflow:1; /* Invert RTS sense */ + const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + const uint32_t tx_gpio; /* TX GPIO pin configuration */ +#endif + + uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t iflow:1; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t oflow:1; /* output flow control (CTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_RS485CONTROL + uint8_t rs485mode:1; /* We are in RS485 (RTS on TX) mode */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t imxrt_serialin(struct imxrt_uart_s *priv, + uint32_t offset); +static inline void imxrt_serialout(struct imxrt_uart_s *priv, + uint32_t offset, uint32_t value); +static inline void imxrt_disableuartint(struct imxrt_uart_s *priv, + uint32_t *ie); +static inline void imxrt_restoreuartint(struct imxrt_uart_s *priv, + uint32_t ie); + +static int imxrt_setup(struct uart_dev_s *dev); +static void imxrt_shutdown(struct uart_dev_s *dev); +static int imxrt_attach(struct uart_dev_s *dev); +static void imxrt_detach(struct uart_dev_s *dev); +static int imxrt_interrupt(int irq, void *context, FAR void *arg); +static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg); +static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status); +static void imxrt_rxint(struct uart_dev_s *dev, bool enable); +static bool imxrt_rxavailable(struct uart_dev_s *dev); +static void imxrt_send(struct uart_dev_s *dev, int ch); +static void imxrt_txint(struct uart_dev_s *dev, bool enable); +static bool imxrt_txready(struct uart_dev_s *dev); +static bool imxrt_txempty(struct uart_dev_s *dev); + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int dowmin, + enum pm_state_e pmstate); +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Serial driver UART operations */ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = imxrt_setup, + .shutdown = imxrt_shutdown, + .attach = imxrt_attach, + .detach = imxrt_detach, + .ioctl = imxrt_ioctl, + .receive = imxrt_receive, + .rxint = imxrt_rxint, + .rxavailable = imxrt_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = imxrt_send, + .txint = imxrt_txint, + .txready = imxrt_txready, + .txempty = imxrt_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_IMXRT_LPUART1 +static char g_uart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART2 +static char g_uart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_LPUART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART3 +static char g_uart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_LPUART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART4 +static char g_uart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_LPUART4_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART5 +static char g_uart5rxbuffer[CONFIG_LPUART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_LPUART5_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART6 +static char g_uart6rxbuffer[CONFIG_LPUART6_RXBUFSIZE]; +static char g_uart6txbuffer[CONFIG_LPUART6_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART7 +static char g_uart7rxbuffer[CONFIG_LPUART7_RXBUFSIZE]; +static char g_uart7txbuffer[CONFIG_LPUART7_TXBUFSIZE]; +#endif + +#ifdef CONFIG_IMXRT_LPUART8 +static char g_uart8rxbuffer[CONFIG_LPUART8_RXBUFSIZE]; +static char g_uart8txbuffer[CONFIG_LPUART8_TXBUFSIZE]; +#endif + +/* This describes the state of the IMXRT lpuart1 port. */ + +#ifdef CONFIG_IMXRT_LPUART1 +static struct imxrt_uart_s g_uart1priv = +{ + .uartbase = IMXRT_LPUART1_BASE, + .baud = CONFIG_LPUART1_BAUD, + .irq = IMXRT_IRQ_LPUART1, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .stopbits2 = CONFIG_LPUART1_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART1_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART1_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART1_TX, +#endif + +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART1_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart1port = +{ + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the IMXRT lpuart2 port. */ + +#ifdef CONFIG_IMXRT_LPUART2 +static struct imxrt_uart_s g_uart2priv = +{ + .uartbase = IMXRT_LPUART2_BASE, + .baud = CONFIG_LPUART2_BAUD, + .irq = IMXRT_IRQ_LPUART2, + .parity = CONFIG_LPUART2_PARITY, + .bits = CONFIG_LPUART2_BITS, + .stopbits2 = CONFIG_LPUART2_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART2_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART2_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART2_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART2_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart2port = +{ + .recv = + { + .size = CONFIG_LPUART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART3 +static struct imxrt_uart_s g_uart3priv = +{ + .uartbase = IMXRT_LPUART3_BASE, + .baud = CONFIG_LPUART3_BAUD, + .irq = IMXRT_IRQ_LPUART3, + .parity = CONFIG_LPUART3_PARITY, + .bits = CONFIG_LPUART3_BITS, + .stopbits2 = CONFIG_LPUART3_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART3_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART3_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART3_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART3_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart3port = +{ + .recv = + { + .size = CONFIG_LPUART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART4 +static struct imxrt_uart_s g_uart4priv = +{ + .uartbase = IMXRT_LPUART4_BASE, + .baud = CONFIG_LPUART4_BAUD, + .irq = IMXRT_IRQ_LPUART4, + .parity = CONFIG_LPUART4_PARITY, + .bits = CONFIG_LPUART4_BITS, + .stopbits2 = CONFIG_LPUART4_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART4_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART4_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART4_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART4_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart4port = +{ + .recv = + { + .size = CONFIG_LPUART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART5 +static struct imxrt_uart_s g_uart5priv = +{ + .uartbase = IMXRT_LPUART5_BASE, + .baud = CONFIG_LPUART5_BAUD, + .irq = IMXRT_IRQ_LPUART5, + .parity = CONFIG_LPUART5_PARITY, + .bits = CONFIG_LPUART5_BITS, + .stopbits2 = CONFIG_LPUART5_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART5_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART5_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART5_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART5_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart5port = +{ + .recv = + { + .size = CONFIG_LPUART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart5priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART6 +static struct imxrt_uart_s g_uart6priv = +{ + .uartbase = IMXRT_LPUART6_BASE, + .baud = CONFIG_LPUART6_BAUD, + .irq = IMXRT_IRQ_LPUART6, + .parity = CONFIG_LPUART6_PARITY, + .bits = CONFIG_LPUART6_BITS, + .stopbits2 = CONFIG_LPUART6_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART6_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART6_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART6_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART6_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart6port = +{ + .recv = + { + .size = CONFIG_LPUART6_RXBUFSIZE, + .buffer = g_uart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART6_TXBUFSIZE, + .buffer = g_uart6txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart6priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART7 +static struct imxrt_uart_s g_uart7priv = +{ + .uartbase = IMXRT_LPUART7_BASE, + .baud = CONFIG_LPUART7_BAUD, + .irq = IMXRT_IRQ_LPUART7, + .parity = CONFIG_LPUART7_PARITY, + .bits = CONFIG_LPUART7_BITS, + .stopbits2 = CONFIG_LPUART7_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART7_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART7_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART7_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART7_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart7port = +{ + .recv = + { + .size = CONFIG_LPUART7_RXBUFSIZE, + .buffer = g_uart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART7_TXBUFSIZE, + .buffer = g_uart7txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart7priv, +}; +#endif + +#ifdef CONFIG_IMXRT_LPUART8 +static struct imxrt_uart_s g_uart8priv = +{ + .uartbase = IMXRT_LPUART8_BASE, + .baud = CONFIG_LPUART8_BAUD, + .irq = IMXRT_IRQ_LPUART8, + .parity = CONFIG_LPUART8_PARITY, + .bits = CONFIG_LPUART8_BITS, + .stopbits2 = CONFIG_LPUART8_2STOP, +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART8_CTS, +#endif +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) + .iflow = 1, +#endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \ + || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART8_RTS, +#endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + .tx_gpio = GPIO_LPUART8_TX, +#endif +#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ + && defined(CONFIG_LPUART8_INVERTIFLOWCONTROL)) + .inviflow = 1, +#endif + +#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) + .rs485mode = 1, +#endif +}; + +static struct uart_dev_s g_uart8port = +{ + .recv = + { + .size = CONFIG_LPUART8_RXBUFSIZE, + .buffer = g_uart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART8_TXBUFSIZE, + .buffer = g_uart8txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart8priv, +}; +#endif + +#ifdef CONFIG_PM +static struct pm_callback_s g_serial_pmcb = +{ + .notify = up_pm_notify, + .prepare = up_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_serialin + ****************************************************************************/ + +static inline uint32_t imxrt_serialin(struct imxrt_uart_s *priv, + uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imxrt_serialout + ****************************************************************************/ + +static inline void imxrt_serialout(struct imxrt_uart_s *priv, + uint32_t offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imxrt_disableuartint + ****************************************************************************/ + +static inline void imxrt_disableuartint(struct imxrt_uart_s *priv, + uint32_t *ie) +{ + irqstate_t flags; + uint32_t regval; + + flags = spin_lock_irqsave(NULL); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + + /* Return the current Rx and Tx interrupt state */ + + if (ie != NULL) + { + *ie = regval & LPUART_ALL_INTS; + } + + regval &= ~LPUART_ALL_INTS; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imxrt_restoreuartint + ****************************************************************************/ + +static inline void imxrt_restoreuartint(struct imxrt_uart_s *priv, + uint32_t ie) +{ + irqstate_t flags; + uint32_t regval; + + /* Enable/disable any interrupts that are currently disabled but should be + * enabled/disabled. + */ + + flags = spin_lock_irqsave(NULL); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= ie; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imxrt_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int imxrt_setup(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + int ret; + struct uart_config_s config = + { + 0 + }; + + /* Configure the UART */ + + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + config.usects = priv->iflow; /* Flow control on inbound side */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + config.userts = priv->oflow; /* Flow control on outbound side */ +#endif +#ifdef CONFIG_SERIAL_RS485CONTROL + config.users485 = priv->rs485mode; /* Switch into RS485 mode */ +#endif +#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) + config.invrts = priv->inviflow; /* Inversion of outbound flow control */ +#endif + + ret = imxrt_lpuart_configure(priv->uartbase, &config); + + priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) & \ + LPUART_ALL_INTS; + return ret; + +#else + priv->ie = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET) & \ + LPUART_ALL_INTS; + return OK; +#endif +} + +/**************************************************************************** + * Name: imxrt_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void imxrt_shutdown(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + /* Disable the UART */ + + imxrt_serialout(priv, IMXRT_LPUART_GLOBAL_OFFSET, LPUART_GLOBAL_RST); +} + +/**************************************************************************** + * Name: imxrt_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate + * in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int imxrt_attach(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, imxrt_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: imxrt_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void imxrt_detach(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: imxrt_interrupt (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It should call + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ****************************************************************************/ + +static int imxrt_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct imxrt_uart_s *priv; + uint32_t usr; + int passes = 0; + bool handled; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct imxrt_uart_s *)dev->priv; + +#if defined(CONFIG_PM) && CONFIG_IMXRT_PM_SERIAL_ACTIVITY > 0 + /* Report serial activity to the power management logic */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_IMXRT_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the current UART status and check for loop + * termination conditions + */ + + usr = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + usr &= (LPUART_STAT_RDRF | LPUART_STAT_TDRE | LPUART_STAT_OR | + LPUART_STAT_FE); + + /* Clear serial overrun and framing errors */ + + if ((usr & LPUART_STAT_OR) != 0) + { + imxrt_serialout(priv, IMXRT_LPUART_STAT_OFFSET, LPUART_STAT_OR); + } + + if ((usr & LPUART_STAT_FE) != 0) + { + imxrt_serialout(priv, IMXRT_LPUART_STAT_OFFSET, LPUART_STAT_FE); + } + + /* Handle incoming, receive bytes */ + + if ((usr & LPUART_STAT_RDRF) != 0 && + (priv->ie & LPUART_CTRL_RIE) != 0) + { + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + if ((usr & LPUART_STAT_TDRE) != 0 && + (priv->ie & LPUART_CTRL_TIE) != 0) + { + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: imxrt_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct imxrt_uart_s *user = (struct imxrt_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct imxrt_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); +#endif + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + +#if defined(CS9) + case 9: + termiosp->c_cflag |= CS9; + break; +#endif + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + +#if defined(CS9) + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flags = spin_lock_irqsave(NULL); + imxrt_disableuartint(priv, &ie); + ret = imxrt_setup(dev); + + /* Restore the interrupt state */ + + imxrt_restoreuartint(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(NULL, flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + uint32_t regval; + irqstate_t flags; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + flags = spin_lock_irqsave(NULL); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val = IOMUX_OPENDRAIN; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLUP ? + IOMUX_PULL_UP_47K : IOMUX_PULL_NONE; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLDOWN ? + IOMUX_PULL_DOWN_100K : IOMUX_PULL_NONE; + imxrt_config_gpio((priv->tx_gpio & + ~(IOMUX_PULL_MASK | IOMUX_OPENDRAIN)) | gpio_val); + regval |= LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC; + } + else + { + imxrt_config_gpio((priv->tx_gpio & ~(IOMUX_PULL_MASK | + IOMUX_OPENDRAIN)) | + IOMUX_PULL_NONE); + regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC); + } + + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + + spin_unlock_irqrestore(NULL, flags); + } + break; +#endif + +#ifdef CONFIG_IMXRT_LPUART_INVERT + case TIOCSINVERT: + { + uint32_t ctrl; + uint32_t stat; + uint32_t regval; + irqstate_t flags; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + + flags = spin_lock_irqsave(NULL); + ctrl = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + stat = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + regval = ctrl; + + /* {R|T}XINV bit field can only be written when the receiver + * is disabled (RE=0). + */ + + regval &= ~LPUART_CTRL_RE; + + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + + /* Enable/disable signal inversion. */ + + if (arg & SER_INVERT_ENABLED_RX) + { + stat |= LPUART_STAT_RXINV; + } + else + { + stat &= ~LPUART_STAT_RXINV; + } + + if (arg & SER_INVERT_ENABLED_TX) + { + ctrl |= LPUART_CTRL_TXINV; + } + else + { + ctrl &= ~LPUART_CTRL_TXINV; + } + + imxrt_serialout(priv, IMXRT_LPUART_STAT_OFFSET, stat); + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, ctrl); + + spin_unlock_irqrestore(NULL, flags); + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: imxrt_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t rxd; + + rxd = imxrt_serialin(priv, IMXRT_LPUART_DATA_OFFSET); + *status = rxd >> LPUART_DATA_STATUS_SHIFT; + return (rxd & LPUART_DATA_MASK) >> LPUART_DATA_SHIFT; +} + +/**************************************************************************** + * Name: imxrt_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void imxrt_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupts for data available at Rx */ + + flags = spin_lock_irqsave(NULL); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE; +#endif + } + else + { + priv->ie &= ~(LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE); + } + + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imxrt_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool imxrt_rxavailable(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t regval; + + /* Return true is data is ready in the Rx FIFO */ + + regval = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + return ((regval & LPUART_STAT_RDRF) != 0); +} + +/**************************************************************************** + * Name: imxrt_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void imxrt_send(struct uart_dev_s *dev, int ch) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + imxrt_serialout(priv, IMXRT_LPUART_DATA_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: imxrt_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void imxrt_txint(struct uart_dev_s *dev, bool enable) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupt for TX complete */ + + flags = spin_lock_irqsave(NULL); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_TIE; +#endif + } + else + { + priv->ie &= ~LPUART_CTRL_TIE; + } + + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imxrt_txready + * + * Description: + * Return true if the transmit register is available to be written to + * + ****************************************************************************/ + +static bool imxrt_txready(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t regval; + + regval = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + return ((regval & LPUART_STAT_TDRE) != 0); +} + +/**************************************************************************** + * Name: imxrt_txempty + * + * Description: + * Return true if the transmission has completed and been sent to line. + * + ****************************************************************************/ + +static bool imxrt_txempty(struct uart_dev_s *dev) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; + uint32_t regval; + + regval = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + return ((regval & LPUART_STAT_TC) != 0); +} + +/**************************************************************************** + * Name: up_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case(PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case(PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case(PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: up_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +void imxrt_earlyserialinit(void) +{ + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was performed by the + * function imxrt_lowsetup() earlier in the boot sequence. + */ + + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + imxrt_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that imxrt_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef CONFIG_PM + int ret; + + /* Register to receive power management callbacks */ + + ret = pm_register(&g_serial_pmcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + +#ifdef CONFIG_IMXRT_LPUART1 + uart_register("/dev/ttyS1", &g_uart1port); +#endif +#ifdef CONFIG_IMXRT_LPUART2 + uart_register("/dev/ttyS2", &g_uart2port); +#endif +#ifdef CONFIG_IMXRT_LPUART3 + uart_register("/dev/ttyS3", &g_uart3port); +#endif +#ifdef CONFIG_IMXRT_LPUART4 + uart_register("/dev/ttyS4", &g_uart4port); +#endif +#ifdef CONFIG_IMXRT_LPUART5 + uart_register("/dev/ttyS5", &g_uart5port); +#endif +#ifdef CONFIG_IMXRT_LPUART6 + uart_register("/dev/ttyS6", &g_uart6port); +#endif +#ifdef CONFIG_IMXRT_LPUART7 + uart_register("/dev/ttyS7", &g_uart7port); +#endif +#ifdef CONFIG_IMXRT_LPUART8 + uart_register("/dev/ttyS8", &g_uart8port); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef CONSOLE_DEV + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)CONSOLE_DEV.priv; + uint32_t ie; + + imxrt_disableuartint(priv, &ie); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + imxrt_lowputc('\r'); + } + + imxrt_lowputc(ch); + imxrt_restoreuartint(priv, ie); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#if CONSOLE_LPUART > 0 + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm_lowputc('\r'); + } + + arm_lowputc(ch); +#endif + + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/arm/src/stm32/stm32_serial.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/stm32/stm32_serial.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/arm/src/stm32/stm32_serial.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/stm32/stm32_serial.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/common/riscv_internal.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/common/riscv_internal.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/common/riscv_internal.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/common/riscv_internal.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/apu.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/atomic.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/atomic.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/atomic.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/atomic.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/bsp.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/bsp.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/bsp.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/bsp.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/clint.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/dmac.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fft.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/fpioa.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio_common.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio_common.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio_common.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpio_common.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/gpiohs.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/i2s.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/interrupt.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/io.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/io.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/io.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/io.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_arch.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_arch.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_arch.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_arch.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_head.S b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_head.S similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_head.S rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_head.S diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_start.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_start.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_start.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_start.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/platform.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/platform.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/platform.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/platform.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/plic.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/syscalls.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/sysctl.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/uarths.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/utils.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/rv64gc/riscv_syscall.S b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/rv64gc/riscv_syscall.S similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/arch/risc-v/src/rv64gc/riscv_syscall.S rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/rv64gc/riscv_syscall.S diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/Kconfig similarity index 99% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/Kconfig index a2cd90a8c..5311f8b96 100644 --- a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/Kconfig +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/Kconfig @@ -445,6 +445,16 @@ config ARCH_BOARD_IMXRT1050_EVK This is the board configuration for the port of NuttX to the NXP i.MXRT evaluation kit, MIMXRT1050-EVKB. This board features the MIMXRT1052DVL6A MCU. +config ARCH_BOARD_XIDATONG + bool "NXP i.MX RT 1052 XIDATONG" + depends on ARCH_CHIP_MIMXRT1052CVL5B + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This is the board configuration for the port of NuttX to the NXP i.MXRT + evaluation kit, MIMXRT1052-XIDATONG. This board features the MIMXRT1052CVL5B MCU. + config ARCH_BOARD_IMXRT1060_EVK bool "NXP i.MX RT 1060 EVK" depends on ARCH_CHIP_MIMXRT1062DVL6A @@ -2382,6 +2392,7 @@ config ARCH_BOARD default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V default "imxrt1020-evk" if ARCH_BOARD_IMXRT1020_EVK default "imxrt1050-evk" if ARCH_BOARD_IMXRT1050_EVK + default "xidatong" if ARCH_BOARD_XIDATONG default "imxrt1060-evk" if ARCH_BOARD_IMXRT1060_EVK default "imxrt1064-evk" if ARCH_BOARD_IMXRT1064_EVK default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40 @@ -2660,6 +2671,9 @@ endif if ARCH_BOARD_IMXRT1050_EVK source "boards/arm/imxrt/imxrt1050-evk/Kconfig" endif +if ARCH_BOARD_XIDATONG +source "boards/arm/imxrt/xidatong/Kconfig" +endif if ARCH_BOARD_IMXRT1060_EVK source "boards/arm/imxrt/imxrt1060-evk/Kconfig" endif diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/README.txt b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/README.txt similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/README.txt rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/README.txt diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/common/include/stm32_hs300x.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/common/include/stm32_hs300x.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/common/include/stm32_hs300x.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/common/include/stm32_hs300x.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/common/src/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/common/src/Make.defs similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/common/src/Make.defs rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/common/src/Make.defs diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/common/src/stm32_hs300x.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/common/src/stm32_hs300x.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/common/src/stm32_hs300x.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/common/src/stm32_hs300x.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/scripts/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/scripts/Make.defs similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/scripts/Make.defs rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/scripts/Make.defs diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/sensors/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/sensors/Kconfig similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/sensors/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/sensors/Kconfig diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/sensors/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/sensors/Make.defs similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/sensors/Make.defs rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/sensors/Make.defs diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/sensors/hs300x.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/sensors/hs300x.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/sensors/hs300x.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/sensors/hs300x.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/wireless/lpwan/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/wireless/lpwan/Kconfig similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/wireless/lpwan/Kconfig rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/wireless/lpwan/Kconfig diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/wireless/lpwan/sx127x/sx127x.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/wireless/lpwan/sx127x/sx127x.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/drivers/wireless/lpwan/sx127x/sx127x.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/wireless/lpwan/sx127x/sx127x.c diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/include/nuttx/sensors/hs300x.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/include/nuttx/sensors/hs300x.h similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/include/nuttx/sensors/hs300x.h rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/include/nuttx/sensors/hs300x.h diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/tools/Makefile.unix b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/tools/Makefile.unix similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/tools/Makefile.unix rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/tools/Makefile.unix diff --git a/Ubiquitous/Nuttx/app_match_nuttx/nuttx/tools/cfgdefine.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/tools/cfgdefine.c similarity index 100% rename from Ubiquitous/Nuttx/app_match_nuttx/nuttx/tools/cfgdefine.c rename to Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/tools/cfgdefine.c diff --git a/Ubiquitous/Nuttx/apps b/Ubiquitous/Nuttx_Fusion_XiUOS/apps similarity index 100% rename from Ubiquitous/Nuttx/apps rename to Ubiquitous/Nuttx_Fusion_XiUOS/apps diff --git a/Ubiquitous/Nuttx/nuttx b/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx similarity index 100% rename from Ubiquitous/Nuttx/nuttx rename to Ubiquitous/Nuttx_Fusion_XiUOS/nuttx diff --git a/Ubiquitous/Nuttx/readme.md b/Ubiquitous/Nuttx_Fusion_XiUOS/readme.md similarity index 98% rename from Ubiquitous/Nuttx/readme.md rename to Ubiquitous/Nuttx_Fusion_XiUOS/readme.md index ebd61a130..9f1567c1b 100644 --- a/Ubiquitous/Nuttx/readme.md +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/readme.md @@ -12,8 +12,8 @@ nuttx代码及apps代码以子仓的形式托管在xiuos\Ubiquitous\Nuttx下，a cd xiuos git submodule git submodule init -git submodule update Ubiquitous/Nuttx/apps -git submodule update Ubiquitous/Nuttx/nuttx +git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/apps +git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/nuttx ``` 执行完成后在Ubiquitous/Nuttx目录下，apps和nuttx的代码都被下载下来，当前的版本是nuttx-10.2.0版本。 @@ -199,7 +199,7 @@ CFLAGS := $(APPPATHS) $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCP └── stm32_serial.c ``` -(1)Nuttx/app_match_nuttx/apps/nshlib下修改，将应用编译成cmd形式，与上面HS300x处描述一致，参考上面即可 +(1)Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib下修改，将应用编译成cmd形式，与上面HS300x处描述一致，参考上面即可 (2)/nuttx/arch/arm/src/stm32/stm32_serial.c，此处代码原本是会将所有打开的串口从0开始依次注册为ttyS1-ttySN，比较不方便，例如打开了USART1、USART3、USART5，USART3将会被注册为ttyS2，容易引起歧义，这边做的修改会将USARTN，注册为ttySN。 diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config index 7888f84f1..a35ce48a2 100644 --- a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config @@ -11,7 +11,7 @@ CONFIG_BOARD_K210_EVB=y # # RT-Thread Kernel # -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=24 # CONFIG_RT_USING_BIG_ENDIAN is not set # CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMP=y @@ -292,11 +292,6 @@ CONFIG_BSP_UART1_CTS_PIN=-1 # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_LCD is not set -# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW is not set -# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set -# CONFIG_BSP_BOARD_KD233 is not set -# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set -# CONFIG_BSP_BOARD_USER is not set # CONFIG_BSP_USING_SDCARD is not set # CONFIG_BSP_USING_DVP is not set CONFIG_BSP_USING_CH438=y @@ -332,10 +327,34 @@ CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055 # Framework # CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y -CONFIG_ADD_XIZI_FETURES=y +# CONFIG_ADD_XIZI_FETURES is not set # CONFIG_ADD_NUTTX_FETURES is not set -# CONFIG_ADD_RTTHREAD_FETURES is not set -# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set +CONFIG_ADD_RTTHREAD_FETURES=y +CONFIG_SUPPORT_SENSOR_FRAMEWORK=y +CONFIG_SENSOR_HCHO=y +CONFIG_SENSOR_TB600B_WQ_HCHO1OS=y +CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS="tb600b_wq_hcho1os_1" +CONFIG_SENSOR_QUANTITY_TB600B_HCHO="hcho_1" +CONFIG_SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART=y +CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV="/dev/extuart_dev1" +CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT=1 +# CONFIG_SENSOR_TVOC is not set +# CONFIG_SENSOR_IAQ is not set +CONFIG_SENSOR_CH4=y +CONFIG_SENSOR_AS830=y +CONFIG_SENSOR_DEVICE_AS830="as830_1" +CONFIG_SENSOR_QUANTITY_AS830_CH4="ch4_1" +CONFIG_SENSOR_AS830_DRIVER_EXTUART=y +CONFIG_SENSOR_DEVICE_AS830_DEV="/dev/extuart_dev4" +CONFIG_SENSOR_DEVICE_AS830_DEV_EXT_PORT=4 +# CONFIG_SENSOR_CO2 is not set +# CONFIG_SENSOR_PM is not set +# CONFIG_SENSOR_VOICE is not set +# CONFIG_SENSOR_TEMPERATURE is not set +# CONFIG_SENSOR_HUMIDITY is not set +# CONFIG_SENSOR_WINDSPEED is not set +# CONFIG_SENSOR_WINDDIRECTION is not set +# CONFIG_SENSOR_ALTITUDE is not set # CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set # CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set # CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set @@ -382,10 +401,12 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024 # sensor app # CONFIG_APPLICATION_SENSOR=y -# CONFIG_APPLICATION_SENSOR_HCHO is not set +CONFIG_APPLICATION_SENSOR_HCHO=y +CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS=y # CONFIG_APPLICATION_SENSOR_TVOC is not set # CONFIG_APPLICATION_SENSOR_IAQ is not set -# CONFIG_APPLICATION_SENSOR_CH4 is not set +CONFIG_APPLICATION_SENSOR_CH4=y +CONFIG_APPLICATION_SENSOR_CH4_AS830=y # CONFIG_APPLICATION_SENSOR_CO2 is not set # CONFIG_APPLICATION_SENSOR_PM1_0 is not set # CONFIG_APPLICATION_SENSOR_PM2_5 is not set @@ -403,7 +424,7 @@ CONFIG_APPLICATION_SENSOR=y # CONFIG_APP_SELECT_NEWLIB=y # CONFIG_APP_SELECT_OTHER_LIB is not set -CONFIG_LIB_USING_CJSON=y +# CONFIG_LIB_USING_CJSON is not set # CONFIG_LIB_USING_QUEUE is not set # CONFIG_LIB_LV is not set # CONFIG_USING_EMBEDDED_DATABASE is not set diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c index 0ae9f62ea..43f682c6a 100644 --- a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c @@ -20,9 +20,10 @@ #include #include - +extern int FrameworkInit(); int main(void) { printf("Hello World\n"); + FrameworkInit(); return 0; } diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c index 2d75e64a0..f561deb5f 100644 --- a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c @@ -5,11 +5,10 @@ #include "board.h" #include "ch438.h" #include "sleep.h" - -static struct rt_semaphore ch438_sem; +#include static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */ -rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8]; +struct rt_serial_device *extuart_serial_parm[8]; void CH438_INIT(void) { @@ -25,7 +24,7 @@ void CH438_INIT(void) gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); } -void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate ) +void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate ) { rt_uint32_t div; rt_uint8_t DLL,DLM,dlab; @@ -117,7 +116,7 @@ void set_485_output(rt_uint8_t ch_no) rt_uint8_t ReadCH438Data( rt_uint8_t addr ) { - rt_uint8_t dat; + rt_uint8_t dat = 0; gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); @@ -164,7 +163,6 @@ rt_uint8_t ReadCH438Data( rt_uint8_t addr ) usleep(1); return dat; - } @@ -216,141 +214,98 @@ static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat) return; } - static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf ) { - while ( mLen -- ) WriteCH438Data( mAddr, *mBuf++ ); - } +static int Ch438Irq(void *parameter) +{ + rt_uint8_t gInterruptStatus; + rt_uint8_t port = 0; + struct rt_serial_device *serial = (struct rt_serial_device *)parameter; + /* multi irq may happen*/ + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + port = log(gInterruptStatus & 0xFF)/log(2); -// void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num ) -// { -// rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR; - -// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; -// REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; - -// while( 1 ) -// { - -// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 ); - -// if( Num <= 128 ) -// { - -// WriteCH438Block( REG_THR_ADDR, Num, Data ); - -// break; - -// } - -// else -// { - -// WriteCH438Block( REG_THR_ADDR, 128, Data ); - -// Num -= 128; - -// Data += 128; - -// } - -// } -// } - - - -// rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf ) -// { -// rt_uint8_t RcvNum = 0; -// rt_uint8_t dat = 0; -// rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR; -// rt_uint8_t *p_rev; - -// p_rev = buf; - -// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; -// REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; - -// { - -// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 ); - -// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) -// { -// dat = ReadCH438Data( REG_RBR_ADDR ); - -// Ch438Buff[ext_uart_no][Ch438BuffPtr[ext_uart_no]] = dat; - -// Ch438BuffPtr[ext_uart_no] = Ch438BuffPtr[ext_uart_no] + 1; -// if (Ch438BuffPtr[ext_uart_no] == BUFFSIZE) -// Ch438BuffPtr[ext_uart_no] = 0; - -// RcvNum = RcvNum + 1; - -// } -// } -// return( RcvNum ); -// } + rt_hw_serial_isr(extuart_serial_parm[port], RT_SERIAL_EVENT_RX_IND); +} static rt_err_t rt_extuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { + rt_uint32_t baud_rate = cfg->baud_rate; + rt_uint16_t port = cfg->reserved; - rt_uint32_t baud_rate = cfg->baud_rate; - uint16_t port = cfg->reserved; CH438_PORT_INIT(port, baud_rate); + return RT_EOK; } static rt_err_t extuart_control(struct rt_serial_device *serial, int cmd, void *arg) { + rt_uint16_t ext_uart_no = serial->config.reserved; + static rt_uint16_t register_flag = 0; + switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: + if(1 == register_flag) + { + gpiohs_irq_unregister(FPIOA_CH438_INT); + register_flag = 0; + } break; - case RT_DEVICE_CTRL_SET_INT: - break; + if(0 == register_flag) + { + gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING); + gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, (void*)serial); + register_flag = 1; + } + + break; } - return (RT_EOK); } static int drv_extuart_putc(struct rt_serial_device *serial, char c) { uint16_t ext_uart_no = serial->config.reserved; - rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR; REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; - while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 ); - WriteCH438Block( REG_THR_ADDR, 1, &c ); + if((ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT) != 0) + { + WriteCH438Block( REG_THR_ADDR, 1, &c ); + return 1; + } else { + return 0; + } + } static int drv_extuart_getc(struct rt_serial_device *serial) { rt_uint8_t dat = 0; rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR; - uint16_t ext_uart_no = serial->config.reserved;///< get extern uart port REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; - - while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 ); - // while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) - // { - dat = ReadCH438Data( REG_RBR_ADDR ); - // } - - return( dat ); + if((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) + { + dat = ReadCH438Data( REG_RBR_ADDR ); + if(dat >= 0) + return dat; + } else { + return -1; + } } const struct rt_uart_ops extuart_ops = @@ -362,111 +317,168 @@ const struct rt_uart_ops extuart_ops = RT_NULL }; -static int Ch438Irq(void *parameter) -{ - rt_sem_release(&ch438_sem); -} - -int Ch438InitDefault(void) -{ - rt_err_t flag; - - flag = rt_sem_init(&ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO); - if (flag != RT_EOK) - { - rt_kprintf("ch438.drv create sem failed .\n"); - return -1; - } - - gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); - gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING); - gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, 0); - - CH438_INIT(); - return 0; -} -INIT_APP_EXPORT(Ch438InitDefault); - int rt_hw_ch438_init(void) { struct rt_serial_device *extserial; struct device_uart *extuart; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t ret; - -// #ifdef BSP_USING_UART1 { static struct rt_serial_device extserial0; - // static struct device_uart extuart0; extserial = &extserial0; - // extuart = &extuart0; - extserial->ops = &extuart_ops; extserial->config = config; extserial->config.baud_rate = 115200; - extserial->config.reserved = 0; ///< extern uart port + extserial->config.reserved = 0; ///< extern uart port - // extuart->hw_base = UART1_BASE_ADDR; - // extuart->irqno = IRQN_UART1_INTERRUPT; + extuart_serial_parm[0] = &extserial0; - // _uart_init(UART_DEVICE_1); - - rt_hw_serial_register(extserial, + ret = rt_hw_serial_register(extserial, "extuart_dev0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, extuart); + if(ret < 0){ + rt_kprintf("extuart_dev0 register failed.\n"); + } } -// #endif + { + static struct rt_serial_device extserial1; -// #ifdef BSP_USING_UART2 - // { - // static struct rt_serial_device serial2; - // static struct device_uart uart2; + extserial = &extserial1; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 1; ///< extern uart port - // serial = &serial2; - // uart = &uart2; + extuart_serial_parm[1] = &extserial1; - // serial->ops = &_uart_ops; - // serial->config = config; - // serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + ret = rt_hw_serial_register(extserial, + "extuart_dev1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev1 register failed.\n"); + } + } + { + static struct rt_serial_device extserial2; - // uart->hw_base = UART2_BASE_ADDR; - // uart->irqno = IRQN_UART2_INTERRUPT; + extserial = &extserial2; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 2; ///< extern uart port - // _uart_init(UART_DEVICE_2); + extuart_serial_parm[2] = &extserial2; - // rt_hw_serial_register(serial, - // "uart2", - // RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - // uart); - // } -// #endif + ret = rt_hw_serial_register(extserial, + "extuart_dev2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev2 register failed.\n"); + } -// #ifdef BSP_USING_UART3 - // { - // static struct rt_serial_device serial3; - // static struct device_uart uart3; + } + { + static struct rt_serial_device extserial3; - // serial = &serial3; - // uart = &uart3; + extserial = &extserial3; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 3; ///< extern uart port - // serial->ops = &_uart_ops; - // serial->config = config; - // serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + ret = rt_hw_serial_register(extserial, + "extuart_dev3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev3 register failed.\n"); + } - // uart->hw_base = UART3_BASE_ADDR; - // uart->irqno = IRQN_UART3_INTERRUPT; + extuart_serial_parm[3] = &extserial3; + } + { + static struct rt_serial_device extserial4; - // _uart_init(UART_DEVICE_3); + extserial = &extserial4; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 4; ///< extern uart port - // rt_hw_serial_register(serial, - // "uart3", - // RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - // uart); - // } -// #endif - // Ch438InitDefault(); + ret = rt_hw_serial_register(extserial, + "extuart_dev4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev4 register failed.\n"); + } + + extuart_serial_parm[4] = &extserial4; + } + { + static struct rt_serial_device extserial5; + + extserial = &extserial5; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 115200; + extserial->config.reserved = 5; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev5 register failed.\n"); + } + + extuart_serial_parm[5] = &extserial5; + } + { + static struct rt_serial_device extserial6; + + extserial = &extserial6; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 57600; + extserial->config.reserved = 6; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev6 register failed.\n"); + } + + extuart_serial_parm[6] = &extserial6; + } + { + static struct rt_serial_device extserial7; + + extserial = &extserial7; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 7; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev7", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev7 register failed.\n"); + } + extuart_serial_parm[7] = &extserial7; + + } + + CH438_INIT(); return 0; } INIT_DEVICE_EXPORT(rt_hw_ch438_init); diff --git a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h index e8a596e33..714ab891e 100644 --- a/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h +++ b/Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h @@ -12,7 +12,7 @@ /* RT-Thread Kernel */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 24 #define RT_USING_SMP #define RT_CPUS_NR 2 #define RT_ALIGN_SIZE 8 @@ -206,7 +206,22 @@ /* Framework */ #define TRANSFORM_LAYER_ATTRIUBUTE -#define ADD_XIZI_FETURES +#define ADD_RTTHREAD_FETURES +#define SUPPORT_SENSOR_FRAMEWORK +#define SENSOR_HCHO +#define SENSOR_TB600B_WQ_HCHO1OS +#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS "tb600b_wq_hcho1os_1" +#define SENSOR_QUANTITY_TB600B_HCHO "hcho_1" +#define SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART +#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV "/dev/extuart_dev1" +#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT 1 +#define SENSOR_CH4 +#define SENSOR_AS830 +#define SENSOR_DEVICE_AS830 "as830_1" +#define SENSOR_QUANTITY_AS830_CH4 "ch4_1" +#define SENSOR_AS830_DRIVER_EXTUART +#define SENSOR_DEVICE_AS830_DEV "/dev/extuart_dev4" +#define SENSOR_DEVICE_AS830_DEV_EXT_PORT 4 /* Security */ @@ -234,11 +249,14 @@ /* sensor app */ #define APPLICATION_SENSOR +#define APPLICATION_SENSOR_HCHO +#define APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS +#define APPLICATION_SENSOR_CH4 +#define APPLICATION_SENSOR_CH4_AS830 /* lib */ #define APP_SELECT_NEWLIB -#define LIB_USING_CJSON #define __STACKSIZE__ 4096 #endif diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/.config b/Ubiquitous/RT_Thread/aiit_board/xidatong/.config new file mode 100644 index 000000000..409076860 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/.config @@ -0,0 +1,339 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_ROOT_DIR="../../../.." +CONFIG_BSP_DIR="." +CONFIG_RT_Thread_DIR="../.." +CONFIG_RTT_DIR="../../rt-thread" + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_BIG_ENDIAN is not set +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CPUTIME=y +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_IMXRT1052CVL5B=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_BOOT_IMAGE=y +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART2 is not set +# CONFIG_BSP_USING_LPUART3 is not set +# CONFIG_BSP_USING_LPUART4 is not set +# CONFIG_BSP_USING_LPUART8 is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_RTC is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_SDRAM=y + +# +# MicroPython +# +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# More Drivers +# +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_DRV_USING_OV2640 is not set + +# +# APP_Framework +# + +# +# Framework +# +CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y +# CONFIG_ADD_XIZI_FETURES is not set +# CONFIG_ADD_NUTTX_FETURES is not set +CONFIG_ADD_RTTHREAD_FETURES=y +# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set +# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set +# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set +# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set + +# +# Security +# +# CONFIG_CRYPTO is not set + +# +# Applications +# + +# +# config stack size and priority of main task +# +CONFIG_MAIN_KTASK_STACK_SIZE=1024 + +# +# ota app +# +# CONFIG_APPLICATION_OTA is not set + +# +# test app +# +# CONFIG_USER_TEST is not set + +# +# connection app +# +# CONFIG_APPLICATION_CONNECTION is not set + +# +# control app +# + +# +# knowing app +# +# CONFIG_APPLICATION_KNOWING is not set + +# +# sensor app +# +# CONFIG_APPLICATION_SENSOR is not set +# CONFIG_USING_EMBEDDED_DATABASE_APP is not set + +# +# lib +# +CONFIG_APP_SELECT_NEWLIB=y +# CONFIG_APP_SELECT_OTHER_LIB is not set +# CONFIG_LIB_USING_CJSON is not set +# CONFIG_LIB_USING_QUEUE is not set +# CONFIG_LIB_LV is not set +# CONFIG_USING_EMBEDDED_DATABASE is not set diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/Kconfig b/Ubiquitous/RT_Thread/aiit_board/xidatong/Kconfig new file mode 100644 index 000000000..478f8394b --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Configuration" + +config ROOT_DIR + string + default "../../../.." + +config BSP_DIR + string + default "." + +config RT_Thread_DIR + string + default "../.." + +config RTT_DIR + string + default "../../rt-thread" + +config APP_DIR + string + default "../../../../APP_Framework" + +source "$RTT_DIR/Kconfig" +source "$RTT_DIR/bsp/imxrt/libraries/Kconfig" +source "board/Kconfig" +source "$RT_Thread_DIR/micropython/Kconfig" +source "$RT_Thread_DIR/app_match_rt-thread/Kconfig" +source "$ROOT_DIR/APP_Framework/Kconfig" + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/README.md b/Ubiquitous/RT_Thread/aiit_board/xidatong/README.md new file mode 100644 index 000000000..a29a927cb --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/README.md @@ -0,0 +1,121 @@ +# XiDaTong_ARM_Reference_Resource + +## 1. 矽达通介绍 + +矽达通外观图: + +![](https://s2.loli.net/2022/03/17/56PYhSplI1Ud89a.png) + +拆开后盖: + +![](https://s2.loli.net/2022/03/17/5SkJish7VqRfwrX.png) + +矽达通烧录这里介绍两种方式，分别是 NXP-MCUBootUtility 和 Keil MDK5 + +## 2. NXP-MCUBootUtility 方式烧录 + +**[NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility/tree/v3.4.0)** 是一款开源免费的专为 NXP MCU 安全启动而设计的 GUI 工具。目前主要支持 i.MXRT、LPC、Kinetis 系列 MCU 芯片 + +> ### 测试环境 + +- Windows + +- NXP-MCUBootUtility v3.4.0 + +> ### 烧录流程 + +将矽达通串口1通过 usb 转串口连接至电脑，并在电脑端查看到相应端口，如下图，com15 + +![](https://s2.loli.net/2022/03/17/b2alJPrmvcEXh5Z.png)![](https://s2.loli.net/2022/03/17/lu2jfeGnyzHKZpD.png) + +打开 NXP-MCUBootUtility.exe + +确保一下配置选项正确，COM Port记得选择上述对应的串口 + +![](https://s2.loli.net/2022/03/16/3z2NLbqlS4f6VGY.png) + +将拨码开关拨到 1 on 2 on 3 off 4 off 进入 Serial Download Programming(SDP) 模式, 重新连接电源 + +先点击 Connect to ROM，若连接成功按钮会变蓝 + +![](https://s2.loli.net/2022/03/16/9pefoEvilVYSOrh.png) + +在 Application Image File 一栏中选择要烧录的 elf 文件，文件格式选择 .out(elf) from GCC ARM，然后点击 All-In-One Action 烧录即可 + +![](https://s2.loli.net/2022/03/16/SrEywuekORU2sNz.png) + +烧录完后后，将拨码开关拨回 1 off 2 off 3 off 4 off 进入 nor-flash 启动模式，重新上电，即可从 QSPI Flash 启动程序，此时可以从串口看到调试信息 + +`注：由于采用串口烧录，在连接和烧录的时候记得先关闭串口调试工具` + +## 2. Keil MDK 方式烧录 + +Keil MDK 是一系列基于 Arm Cortex-M 的微控制器设备的完整软件开发环境，可以自行去官网 **[购买下载](https://www.keil.com/download/product/)** ，需要注意的是请选择使用 Keil MDK5.24a 及以上版本 + +开发板连接 CMSIS-DAP 调试器，如下图所示，连接 DIO/CLK/GND 对应的三个引脚即可 + +![](https://s2.loli.net/2022/03/17/V6sQ8R5SXHMbZdU.png) + +> ### 芯片支持包导入 + +去keil官网 [http://www.keil.com/dd2/pack/#/eula-container](http://www.keil.com/dd2/pack/#/eula-container) 下载对应的板级安装包 + +![](https://s2.loli.net/2022/03/17/Fofnw1ajkuyOLmi.png) + +注意： 安装包可能随时间推移，版本有所改动，可选择最新版本下载。 + +下载完成，安装即可。 + +> ### 烧写固件安装 + +将开发板烧写固件复制到 Keil5 安装目录 Keil_v5\ARM\Flash\MIMXRT_QSPIFLASH.FLM，该固件可以兼容32M以下nor Flash烧写。 + +例如： c:\Keil_v5\ARM\Flash\MIMXRT_QSPIFLASH.FLM + +> ### Keil 环境配置 + +查看仿真器是否连接成功： + +![](https://s2.loli.net/2022/03/17/xmQqBslFL1j2SDN.png) + +![](https://s2.loli.net/2022/03/17/H5it68ZWzuRwA4J.png) + +> ### 添加烧写固件 + +选择 Flash Download，删除原来的烧写配置 + +![](https://s2.loli.net/2022/03/17/xOZCnXdaErIF5oS.png) + +添加该烧写固件，size 大小为 32MB + +![](https://s2.loli.net/2022/03/17/xfCIsgOF2N5t3pM.png) + +下载的一些设置记得勾上： + +![](https://s2.loli.net/2022/03/17/acizCh5tH7MJATO.png)![](https://s2.loli.net/2022/03/17/cUqhyRgoPFQHW6L.png) + +然后编译烧录即可，keil下载不需要进入 SDP 模式，无需拨拨码开关。 + + + +## 3.矽达通硬件资源 + +| 端口 | 功能 | +| :------------: | :----------------: | +| uart1 | shell | +| uart3 | 485CH1（外围接口） | +| uart4 | 485CH2（外围接口） | +| uart8 | ec200t 4G 通讯 | +| uart2 | wifi esp07 | +| ch438 EXTU2 | Bluetooth HC08 | +| ch438 EXTU3 | Lora E220-400T22S | +| ch438 EXTU1 | zigbee E18-MS1PA1 | +| SD | sd卡 | +| usb1 | ec200t 4G通讯 | +| usb2 | 外围usb接口 | +| can | can外围接口 | +| IIC | 屏幕 | +| 其他CH438 EXTU | 外围接口 | + + + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/SConscript b/Ubiquitous/RT_Thread/aiit_board/xidatong/SConscript new file mode 100644 index 000000000..c7ef7659e --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/SConstruct b/Ubiquitous/RT_Thread/aiit_board/xidatong/SConstruct new file mode 100644 index 000000000..525661e52 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/SConstruct @@ -0,0 +1,85 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +#if os.path.exists(SDK_ROOT + '/libraries'): +# libraries_path_prefix = SDK_ROOT + '/libraries' +#else: +# libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' +libraries_path_prefix = RTT_ROOT + '/bsp/imxrt/libraries' +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1050' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# include more drivers +objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript')) + +# include APP_Framework/Framework +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript')) + +# include APP_Framework/Applications +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript')) + +# include APP_Framework/lib +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript')) + +# include Ubiquitous/RT-Thread/micropython +objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript')) +# make a building +DoBuilding(TARGET, objs) diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/applications/SConscript b/Ubiquitous/RT_Thread/aiit_board/xidatong/applications/SConscript new file mode 100644 index 000000000..20bf17933 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/applications/SConscript @@ -0,0 +1,17 @@ +import os +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/applications/main.c b/Ubiquitous/RT_Thread/aiit_board/xidatong/applications/main.c new file mode 100644 index 000000000..314b7f590 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/applications/main.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-29 tyustli first version + * + */ + +#include +#include +#include "drv_gpio.h" +#include + +/* defined the LED pin: GPIO1_IO9 */ +#define LED0_PIN GET_PIN(1,9) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + rt_kprintf("XIUOS xidatong build %s %s\n",__DATE__,__TIME__); + while (1) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + +#ifdef BSP_USING_SDRAM +static void sram_test2(void) +{ + char *p =NULL; + p = rt_malloc(1024*1024*8); + if(p == NULL) + { + rt_kprintf("apply for 8MB memory fail ~!!!"); + } + else + { + rt_kprintf("appyle for 8MB memory success!!!"); + } + rt_free(p); +} +MSH_CMD_EXPORT(sram_test2, sram test2); +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/Kconfig b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/Kconfig new file mode 100644 index 000000000..3c2355e2b --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/Kconfig @@ -0,0 +1,216 @@ +menu "Hardware Drivers Config" + +config SOC_IMXRT1052CVL5B + bool + select SOC_MIMXRT1050_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_BOOT_IMAGE + bool "Enable boot image" + default y + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART2 + bool "Enable LPUART2" + default y + + config BSP_LPUART2_RX_USING_DMA + bool "Enable LPUART2 RX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART2_RX_DMA_CHANNEL + depends on BSP_LPUART2_RX_USING_DMA + int "Set LPUART2 RX DMA channel (0-32)" + default 2 + + config BSP_LPUART2_TX_USING_DMA + bool "Enable LPUART2 TX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART2_TX_DMA_CHANNEL + depends on BSP_LPUART2_TX_USING_DMA + int "Set LPUART2 TX DMA channel (0-32)" + default 3 + + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default y + + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 4 + + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 5 + + config BSP_USING_LPUART4 + bool "Enable LPUART4" + default n + + config BSP_LPUART4_RX_USING_DMA + bool "Enable LPUART4 RX DMA" + depends on BSP_USING_LPUART4 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART4_RX_DMA_CHANNEL + depends on BSP_LPUART4_RX_USING_DMA + int "Set LPUART4 RX DMA channel (0-32)" + default 6 + + config BSP_LPUART4_TX_USING_DMA + bool "Enable LPUART4 TX DMA" + depends on BSP_USING_LPUART4 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART4_TX_DMA_CHANNEL + depends on BSP_LPUART4_TX_USING_DMA + int "Set LPUART4 TX DMA channel (0-32)" + default 7 + + + config BSP_USING_LPUART8 + bool "Enable LPUART8" + default y + + config BSP_LPUART8_RX_USING_DMA + bool "Enable LPUART8 RX DMA" + depends on BSP_USING_LPUART8 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART8_RX_DMA_CHANNEL + depends on BSP_LPUART8_RX_USING_DMA + int "Set LPUART8 RX DMA channel (0-32)" + default 8 + + config BSP_LPUART8_TX_USING_DMA + bool "Enable LPUART8 TX DMA" + depends on BSP_USING_LPUART8 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART8_TX_DMA_CHANNEL + depends on BSP_LPUART8_TX_USING_DMA + int "Set LPUART8 TX DMA channel (0-32)" + default 9 + + endif + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + choice + prompt "Select I2C1 badurate" + default HW_I2C1_BADURATE_100kHZ + + config HW_I2C1_BADURATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C1_BADURATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "Enable CAN1" + default y + endif + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n +endmenu + + +endmenu diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/MCUX_Config.mex b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/MCUX_Config.mex new file mode 100644 index 000000000..5b8653181 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/MCUX_Config.mex @@ -0,0 +1,468 @@ + + + + MIMXRT1052xxxxB + MIMXRT1052DVL6B + IMXRT1050-EVKB + A + ksdk2_0 + + + + + + + false + false + + + + + 5.0.2 + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 5.0.2 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + + true + + + + + 2.2.4 + + + + + true + + + + + 2.1.5 + + + + + 5.0.2 + + + + + + + + + 0 + + + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/clock_config.c b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/clock_config.c new file mode 100644 index 000000000..2df780010 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/clock_config.c @@ -0,0 +1,465 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v5.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 5.0.2 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 20 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.CAN_CLK_PODF.scale, value: '4', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 3); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 7); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); + /* Disable pfd offset. */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK; +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Tx clock source. */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/clock_config.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/clock_config.h new file mode 100644 index 000000000..43fbb9d80 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/clock_config.h @@ -0,0 +1,66 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/pin_mux.c b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/pin_mux.c new file mode 100644 index 000000000..bc1567915 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/pin_mux.c @@ -0,0 +1,691 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v5.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 5.0.2 +board: IMXRT1050-EVKB +pin_labels: +- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BSP_BEEP} +- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: BSP_RS485_RE, identifier: CSI_D7} +- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: BSP_DS18B20, identifier: CSI_D6} +- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: BSP_AP3216C_INT, identifier: CSI_MCLK} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13} + - {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02} + - {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03} + - {pin_num: D13, peripheral: LPUART5, signal: TX, pin_signal: GPIO_B1_12} + - {pin_num: D14, peripheral: LPUART5, signal: RX, pin_signal: GPIO_B1_13} + - {pin_num: H13, peripheral: PWM4, signal: 'A, 0', pin_signal: GPIO_AD_B1_08} + - {pin_num: M13, peripheral: PWM4, signal: 'A, 1', pin_signal: GPIO_AD_B1_09} + - {pin_num: G13, peripheral: PWM1, signal: 'A, 3', pin_signal: GPIO_AD_B0_10} + - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, software_input_on: Enable} + - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, software_input_on: Enable} + - {pin_num: L13, peripheral: GPIO1, signal: 'gpio_io, 26', pin_signal: GPIO_AD_B1_10} + - {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03} + - {pin_num: J13, peripheral: GPIO1, signal: 'gpio_io, 27', pin_signal: GPIO_AD_B1_11} + - {pin_num: K12, peripheral: GPIO1, signal: 'gpio_io, 21', pin_signal: GPIO_AD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + + /*CH438 IO initialize + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD + 0U);*/ + + /* uart 1 2 3 4 8 io initialize */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate*/ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0x10B0u); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0x10B0u); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0x10B0u); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0x10B0u); + + /* Semc io initialize sdram can used*/ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 is configured as SEMC_CS0 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 is configured as SEMC_DQS */ + 1U); /* Software Input On Field: Force input path of pad GPIO_EMC_39 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 is configured as SEMC_RDY */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 PAD functional properties : */ + 0x0110F9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/7 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Enabled */ + + +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/pin_mux.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/pin_mux.h new file mode 100644 index 000000000..b6aa2b3da --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MCUX_Config/pin_mux.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */ + +/* GPIO_AD_B1_02 (coord L11), SPDIF_OUT/J22[7] */ +#define BOARD_INITPINS_SPDIF_OUT_PERIPHERAL LPUART2 /*!< Device name: LPUART2 */ +#define BOARD_INITPINS_SPDIF_OUT_SIGNAL TX /*!< LPUART2 signal: TX */ + +/* GPIO_AD_B1_03 (coord M12), SPDIF_IN/J22[8] */ +#define BOARD_INITPINS_SPDIF_IN_PERIPHERAL LPUART2 /*!< Device name: LPUART2 */ +#define BOARD_INITPINS_SPDIF_IN_SIGNAL RX /*!< LPUART2 signal: RX */ + + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MIMXRT_QSPIFLASH.FLM b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MIMXRT_QSPIFLASH.FLM new file mode 100644 index 000000000..097d6c449 Binary files /dev/null and b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/MIMXRT_QSPIFLASH.FLM differ diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/SConscript b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/SConscript new file mode 100644 index 000000000..82349a3db --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/SConscript @@ -0,0 +1,17 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/clock_config.c +MCUX_Config/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +CPPDEFINES = ['CPU_MIMXRT1052CVL5B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/board.c b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/board.c new file mode 100644 index 000000000..fb0458803 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/board.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + */ + +#include +#include +#include "board.h" +#include "pin_mux.h" + +#ifdef BSP_USING_DMA +#include "fsl_dmamux.h" +#include "fsl_edma.h" +#endif + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +/* MPU configuration. */ +static void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + SCB_DisableICache(); + SCB_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Region 0 setting */ + MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 2 setting */ + // spi flash: normal type, cacheable, no bufferable, no shareable + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +#if defined(BSP_USING_SDRAM) + /* Region 7 setting */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + /* Region 8 setting */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#ifdef BSP_USING_DMA +void imxrt_dma_init(void) +{ + edma_config_t config; + + DMAMUX_Init(DMAMUX); + EDMA_GetDefaultConfig(&config); + EDMA_Init(DMA0, &config); +} +#endif + +void rt_hw_board_init() +{ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef BSP_USING_DMA + imxrt_dma_init(); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t usec) +{ + ; +} diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/board.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/board.h new file mode 100644 index 000000000..100b932eb --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/board.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "fsl_common.h" +#include "clock_config.h" + +#ifdef __CC_ARM +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) + +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +void rt_hw_board_init(void); + +#endif + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.icf b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.icf new file mode 100644 index 000000000..8acfc82bf --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.icf @@ -0,0 +1,95 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x61FFFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x2023FFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; +define exported symbol __RTT_HEAP_END = m_data2_end; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.lds b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.lds new file mode 100644 index 000000000..b8c229ae3 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.lds @@ -0,0 +1,276 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 + + m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + PROVIDE(__ctors_start__ = .); + /* __CTOR_LIST__ = .; */ + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* __CTOR_END__ = .; */ + PROVIDE(__ctors_end__ = .); + } > m_text + + .dtors : + { + PROVIDE(__dtors_start__ = .); + /* __DTOR_LIST__ = .; */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* __DTOR_END__ = .; */ + PROVIDE(__dtors_end__ = .); + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_dtcm + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_dtcm + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_dtcm + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_dtcm + + PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.sct b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.sct new file mode 100644 index 000000000..8d8ab008d --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/linker_scripts/link.sct @@ -0,0 +1,134 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x1F7FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + + + +#if 1 +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } + ITCM 0x400 0xFBFF { + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } +} diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/board/ports/sdram_port.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/ports/sdram_port.h new file mode 100644 index 000000000..6673e369c --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/board/ports/sdram_port.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-05 zylx The first version for STM32F4xx + * 2019-4-25 misonyo port to IMXRT + */ + +#ifndef SDRAM_PORT_H__ +#define SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) +/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ +#define SDRAM_REGION kSEMC_SDRAM_CS0 +/* CS pin: kSEMC_MUXCSX0/1/2/3 */ +#define SDRAM_CS_PIN kSEMC_MUXCSX0 +/* size(kbyte):32MB = 32*1024*1KBytes */ +#define SDRAM_SIZE ((uint32_t)0x8000) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit +/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ +#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit +/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ +#define SDRAM_CAS_LATENCY kSEMC_LatencyThree + +/* Timing configuration for W9825G6KH */ +/* TRP:precharge to active command time (ns) */ +#define SDRAM_TRP 18 +/* TRCD:active to read/write command delay time (ns) */ +#define SDRAM_TRCD 18 +/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ +#define SDRAM_REFRESH_RECOVERY 67 +/* TWR:write recovery time (ns). */ +#define SDRAM_TWR 12 +/* TRAS:active to precharge command time (ns). */ +#define SDRAM_TRAS 42 +/* TRC time (ns). */ +#define SDRAM_TRC 60 +/* active to active time (ns). */ +#define SDRAM_ACT2ACT 60 +/* refresh time (ns). 64ms */ +#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 + +#endif /* SDRAM_PORT_H__ */ diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/project.uvoptx b/Ubiquitous/RT_Thread/aiit_board/xidatong/project.uvoptx new file mode 100644 index 000000000..0f04e4573 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/project.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + .\flexspi_nor.ini + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP-v1-MuseLab" -U0700000105dcff343730534243072257 -O974 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT_QSPIFLASH -FS060000000 -FL02000000 + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/project.uvprojx b/Ubiquitous/RT_Thread/aiit_board/xidatong/project.uvprojx new file mode 100644 index 000000000..a5d874f6a --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/project.uvprojx @@ -0,0 +1,987 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rtthread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + MIMXRT1052DVL6B + NXP + NXP.MIMXRT1052_DFP.10.0.1 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) XRAM(0x20200000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + + 0 + $$Device:MIMXRT1052DVL6B$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1052DVL6B$MIMXRT1052.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM7 + SARMCM3.DLL + + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x20200000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20200000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + SKIP_SYSCLK_INIT, CPU_MIMXRT1052CVL5B, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, XIP_EXTERNAL_FLASH=1, EVK_MCIMXRM, RT_USING_ARM_LIBC + + applications;..\..\rt-thread\libcpu\arm\common;..\..\rt-thread\libcpu\arm\cortex-m7;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;board;board\MCUX_Config;board\ports;..\..\rt-thread\bsp\imxrt\libraries\drivers;..\..\rt-thread\bsp\imxrt\libraries\drivers\config;..\..\rt-thread\components\dfs\include;..\..\rt-thread\components\dfs\filesystems\devfs;..\..\rt-thread\components\finsh;.;..\..\rt-thread\include;..\..\rt-thread\components\libc\compilers\armlibc;..\..\rt-thread\components\libc\compilers\common;..\..\rt-thread\components\libc\compilers\common\nogcc;..\..\rt-thread\components\libc\posix\pthreads;..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\CMSIS\Include;..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052;..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers;..\..\..\..\APP_Framework\Applications\general_functions\list;..\..\..\..\APP_Framework\Framework\knowing\ota;..\..\..\..\APP_Framework\Framework\sensor;..\..\..\..\APP_Framework\Applications;..\..\..\..\APP_Framework\Framework\sensor\altitude\bmp180;..\..\..\..\APP_Framework\Framework\sensor\co2\g8s;..\..\..\..\APP_Framework\Framework\sensor\voice\d124;..\..\..\..\APP_Framework\Framework\sensor\winddirection\qs-fx;..\..\..\..\APP_Framework\Framework\sensor\windspeed\qs-fs;..\..\..\..\APP_Framework\Framework\transform_layer\rtthread;..\..\rt-thread\examples\utest\testcases\kernel;xip + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link.sct + + + --keep=*(.boot_hdr.ivt)--keep=*(.boot_hdr.boot_data)--keep=*(.boot_hdr.dcd_data)--keep=*(.boot_hdr.conf) + + 6314 + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + div0.c + 1 + ..\..\rt-thread\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\rt-thread\libcpu\arm\common\showmem.c + + + + + backtrace.c + 1 + ..\..\rt-thread\libcpu\arm\common\backtrace.c + + + + + cpu_cache.c + 1 + ..\..\rt-thread\libcpu\arm\cortex-m7\cpu_cache.c + + + + + context_rvds.S + 2 + ..\..\rt-thread\libcpu\arm\cortex-m7\context_rvds.S + + + + + cpuport.c + 1 + ..\..\rt-thread\libcpu\arm\cortex-m7\cpuport.c + + + + + DeviceDrivers + + + cputime.c + 1 + ..\..\rt-thread\components\drivers\cputime\cputime.c + + + + + pin.c + 1 + ..\..\rt-thread\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\rt-thread\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\rt-thread\components\drivers\src\completion.c + + + + + waitqueue.c + 1 + ..\..\rt-thread\components\drivers\src\waitqueue.c + + + + + ringbuffer.c + 1 + ..\..\rt-thread\components\drivers\src\ringbuffer.c + + + + + ringblk_buf.c + 1 + ..\..\rt-thread\components\drivers\src\ringblk_buf.c + + + + + workqueue.c + 1 + ..\..\rt-thread\components\drivers\src\workqueue.c + + + + + pipe.c + 1 + ..\..\rt-thread\components\drivers\src\pipe.c + + + + + dataqueue.c + 1 + ..\..\rt-thread\components\drivers\src\dataqueue.c + + + + + Drivers + + + pin_mux.c + 1 + board\MCUX_Config\pin_mux.c + + + + + board.c + 1 + board\board.c + + + + + clock_config.c + 1 + board\MCUX_Config\clock_config.c + + + + + drv_sdram.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\drivers\drv_sdram.c + + + + + drv_gpio.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\drivers\drv_gpio.c + + + + + drv_uart.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\drivers\drv_uart.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\rt-thread\components\dfs\src\dfs_posix.c + + + + + dfs_poll.c + 1 + ..\..\rt-thread\components\dfs\src\dfs_poll.c + + + + + dfs_file.c + 1 + ..\..\rt-thread\components\dfs\src\dfs_file.c + + + + + dfs.c + 1 + ..\..\rt-thread\components\dfs\src\dfs.c + + + + + dfs_fs.c + 1 + ..\..\rt-thread\components\dfs\src\dfs_fs.c + + + + + dfs_select.c + 1 + ..\..\rt-thread\components\dfs\src\dfs_select.c + + + + + devfs.c + 1 + ..\..\rt-thread\components\dfs\filesystems\devfs\devfs.c + + + + + Finsh + + + shell.c + 1 + ..\..\rt-thread\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\rt-thread\components\finsh\msh.c + + + + + msh_file.c + 1 + ..\..\rt-thread\components\finsh\msh_file.c + + + + + cmd.c + 1 + ..\..\rt-thread\components\finsh\cmd.c + + + + + Kernel + + + memheap.c + 1 + ..\..\rt-thread\src\memheap.c + + + + + idle.c + 1 + ..\..\rt-thread\src\idle.c + + + + + timer.c + 1 + ..\..\rt-thread\src\timer.c + + + + + mempool.c + 1 + ..\..\rt-thread\src\mempool.c + + + + + components.c + 1 + ..\..\rt-thread\src\components.c + + + + + ipc.c + 1 + ..\..\rt-thread\src\ipc.c + + + + + device.c + 1 + ..\..\rt-thread\src\device.c + + + + + clock.c + 1 + ..\..\rt-thread\src\clock.c + + + + + thread.c + 1 + ..\..\rt-thread\src\thread.c + + + + + irq.c + 1 + ..\..\rt-thread\src\irq.c + + + + + scheduler.c + 1 + ..\..\rt-thread\src\scheduler.c + + + + + object.c + 1 + ..\..\rt-thread\src\object.c + + + + + kservice.c + 1 + ..\..\rt-thread\src\kservice.c + + + + + libc + + + stdio.c + 1 + ..\..\rt-thread\components\libc\compilers\armlibc\stdio.c + + + + + syscalls.c + 1 + ..\..\rt-thread\components\libc\compilers\armlibc\syscalls.c + + + + + mem_std.c + 1 + ..\..\rt-thread\components\libc\compilers\armlibc\mem_std.c + + + + + libc.c + 1 + ..\..\rt-thread\components\libc\compilers\armlibc\libc.c + + + + + unistd.c + 1 + ..\..\rt-thread\components\libc\compilers\common\unistd.c + + + + + delay.c + 1 + ..\..\rt-thread\components\libc\compilers\common\delay.c + + + + + time.c + 1 + ..\..\rt-thread\components\libc\compilers\common\time.c + + + + + stdlib.c + 1 + ..\..\rt-thread\components\libc\compilers\common\stdlib.c + + + + + mqueue.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\mqueue.c + + + + + pthread_cond.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_cond.c + + + + + semaphore.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\semaphore.c + + + + + pthread_barrier.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_barrier.c + + + + + sched.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\sched.c + + + + + pthread_rwlock.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_rwlock.c + + + + + pthread_attr.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_attr.c + + + + + pthread_spin.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_spin.c + + + + + pthread_mutex.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_mutex.c + + + + + pthread_tls.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread_tls.c + + + + + pthread.c + 1 + ..\..\rt-thread\components\libc\posix\pthreads\pthread.c + + + + + Libraries + + + system_MIMXRT1052.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\system_MIMXRT1052.c + + + + + fsl_gpio.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_gpio.c + + + + + fsl_lpuart.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_lpuart.c + + + + + fsl_semc.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_semc.c + + + + + fsl_clock.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_clock.c + + + + + fsl_cache.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_cache.c + + + + + fsl_common.c + 1 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_common.c + + + + + startup_MIMXRT1052.s + 2 + ..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\arm\startup_MIMXRT1052.s + + + + + list + + + double_list.c + 1 + ..\..\..\..\APP_Framework\Applications\general_functions\list\double_list.c + + + + + single_list.c + 1 + ..\..\..\..\APP_Framework\Applications\general_functions\list\single_list.c + + + + + sensor + + + framework_init.c + 1 + ..\..\..\..\APP_Framework\Applications\framework_init.c + + + + + transform + + + transform.c + 1 + ..\..\..\..\APP_Framework\Framework\transform_layer\rtthread\transform.c + + + + + xip + + + fsl_flexspi_nor_boot.c + 1 + xip\fsl_flexspi_nor_boot.c + + + + + fsl_flexspi_nor_flash.c + 1 + xip\fsl_flexspi_nor_flash.c + + + + + + + + + + + + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/rtconfig.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/rtconfig.h new file mode 100644 index 000000000..f85a45db3 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/rtconfig.h @@ -0,0 +1,194 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define ROOT_DIR "../../../.." +#define BSP_DIR "." +#define RT_Thread_DIR "../.." +#define RTT_DIR "../../rt-thread" + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CPUTIME +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_PTHREADS +#define PTHREAD_NUM_MAX 8 +#define RT_USING_POSIX +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* Hardware Drivers Config */ + +#define SOC_IMXRT1052CVL5B + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_BOOT_IMAGE +#define BSP_USING_GPIO +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_SDRAM + +/* MicroPython */ + + +/* More Drivers */ + + +/* APP_Framework */ + +/* Framework */ + +#define TRANSFORM_LAYER_ATTRIUBUTE +#define ADD_RTTHREAD_FETURES + +/* Security */ + + +/* Applications */ + +/* config stack size and priority of main task */ + +#define MAIN_KTASK_STACK_SIZE 1024 + +/* ota app */ + + +/* test app */ + + +/* connection app */ + + +/* control app */ + +/* knowing app */ + + +/* sensor app */ + + +/* lib */ + +#define APP_SELECT_NEWLIB + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/rtconfig.py b/Ubiquitous/RT_Thread/aiit_board/xidatong/rtconfig.py new file mode 100644 index 000000000..02b8e1933 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/rtconfig.py @@ -0,0 +1,162 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + + \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/template.uvoptx b/Ubiquitous/RT_Thread/aiit_board/xidatong/template.uvoptx new file mode 100644 index 000000000..0f04e4573 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + .\flexspi_nor.ini + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP-v1-MuseLab" -U0700000105dcff343730534243072257 -O974 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT_QSPIFLASH -FS060000000 -FL02000000 + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/template.uvprojx b/Ubiquitous/RT_Thread/aiit_board/xidatong/template.uvprojx new file mode 100644 index 000000000..fc37564b1 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + MIMXRT1052DVL6B + NXP + NXP.MIMXRT1052_DFP.10.0.1 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) XRAM(0x20200000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + + 0 + $$Device:MIMXRT1052DVL6B$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1052DVL6B$MIMXRT1052.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM7 + SARMCM3.DLL + + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x8000 + + + 1 + 0x20200000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20200000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link.sct + + + + + 6314 + + + + + + + + + + + + + diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/SConscript b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/SConscript new file mode 100644 index 000000000..787a0aa93 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/SConscript @@ -0,0 +1,20 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +cwd = GetCurrentDir() +SOURCES = [] +CPPPATH = [cwd] +if GetDepend('BSP_USING_BOOT_IMAGE'): + SOURCES = Glob('*.c') + if rtconfig.CROSS_TOOL == 'keil': + LINKFLAGS = '--keep=*(.boot_hdr.ivt)' + LINKFLAGS += '--keep=*(.boot_hdr.boot_data)' + LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)' + LINKFLAGS += '--keep=*(.boot_hdr.conf)' + else: + SOURCES = Glob('*.c') + LINKFLAGS = '' +else: + LINKFLAGS = '' +group = DefineGroup('xip', src= SOURCES, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) +Return('group') \ No newline at end of file diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_boot.c b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 000000000..e4b38b4d1 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,1219 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.c +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif +//const uint8_t dcd_sdram[1044] = { +///*0000*/ 0xD2, 0x04, 0x14, 0x41, 0xCC, 0x02, 0xF4, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, +///*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, +///*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, +///*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, +///*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, +///*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x09, 0x83, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, +///*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, +///*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, +///*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, +///*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, +///*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, +///*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, +///*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, +///*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, +///*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, +///*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, +///*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, +///*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, +///*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, +///*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, +///*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, +///*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, +///*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, +///*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, +///*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, +///*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, +///*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xF1, +///*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xF1, +///*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xF1, +///*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xF1, +///*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xF1, +///*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x00, 0x00, 0xF1, +///*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x00, 0x00, 0xF1, +///*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x00, 0x00, 0xF1, +///*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x00, 0x00, 0xF1, +///*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x00, 0x00, 0xF1, +///*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x00, 0x00, 0xF1, +///*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x00, 0x00, 0xF1, +///*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x00, 0x00, 0xF1, +///*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x00, 0x00, 0xF1, +///*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x00, 0x00, 0xF1, +///*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x00, 0x00, 0xF1, +///*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x00, 0x00, 0xF1, +///*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x00, 0x00, 0xF1, +///*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x00, 0x00, 0xF1, +///*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x00, 0x00, 0xF1, +///*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x00, 0x00, 0xF1, +///*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x00, 0x00, 0xF1, 0xCC, 0x00, 0x0C, 0x14, 0x40, 0x2F, 0x00, 0x00, +///*0300*/ 0x00, 0x00, 0x00, 0x02, 0xCC, 0x00, 0x9C, 0x04, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, +///*0310*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, +///*0320*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x14, 0x90, 0x00, 0x00, 0x21, +///*0330*/ 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0B, 0x27, +///*0340*/ 0x40, 0x2F, 0x00, 0x44, 0x00, 0x10, 0x01, 0x00, 0x40, 0x2F, 0x00, 0x48, 0x00, 0x02, 0x02, 0x01, +///*0350*/ 0x40, 0x2F, 0x00, 0x4C, 0x08, 0x19, 0x3D, 0x0E, 0x40, 0x2F, 0x00, 0x74, 0x00, 0x65, 0x29, 0x22, +///*0360*/ 0x40, 0x2F, 0x00, 0x78, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x7C, 0x50, 0x21, 0x0A, 0x08, +///*0370*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, +///*0380*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, +///*0390*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, +///*03a0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +///*03b0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +///*03c0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +///*03d0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +///*03e0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, +///*03f0*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x22, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, +///*0400*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, +///*0410*/ 0x00, 0x00, 0x00, 0x01, +//}; + + + +const uint8_t dcd_sdram[1072] = { + /*0000*/ 0xD2, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x07, + 0x0A, + 0x09, +}; diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_boot.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 000000000..56b568b8e --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,123 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.h +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +//extern const uint8_t dcd_sdram[1044]; +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_flash.c b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 000000000..9fd83eef8 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,88 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.c +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t Qspiflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3u, + .csSetupTime = 3u, + .deviceModeCfgEnable = true, + .deviceModeType = 1,//Quad Enable command + .deviceModeSeq.seqNum = 1, + .deviceModeSeq.seqId = 4, + .deviceModeArg = 0x000200,//Set QE + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI + .sflashA1Size = 16u * 1024u * 1024u,//4MBytes + .dataValidTime = {16u, 16u}, + .lookupTable = + { +// //Fast Read Sequence +// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18), +// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08), +// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0), + //Quad Input/output read sequence + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), + //Read Status + [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + //Write Enable + [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), + //Write status + [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, +}; diff --git a/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_flash.h b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 000000000..940baf8b5 --- /dev/null +++ b/Ubiquitous/RT_Thread/aiit_board/xidatong/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.h +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__ diff --git a/Ubiquitous/XiZi/arch/arm/Makefile b/Ubiquitous/XiZi/arch/arm/Makefile index c1a6ed745..4deddfcac 100644 --- a/Ubiquitous/XiZi/arch/arm/Makefile +++ b/Ubiquitous/XiZi/arch/arm/Makefile @@ -7,7 +7,7 @@ endif ifeq ($(CONFIG_BOARD_STM32F103_NANO),y) SRC_DIR := shared -SRC_DIR +=cortex-m3 +SRC_DIR += cortex-m3 endif ifeq ($(CONFIG_BOARD_STM32F407_EVB),y) @@ -15,6 +15,11 @@ SRC_DIR := shared SRC_DIR += cortex-m4 endif +ifeq ($(CONFIG_BOARD_CORTEX_M4_EVB),y) +SRC_DIR := shared +SRC_DIR += cortex-m4 +endif + ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y) SRC_DIR := shared SRC_DIR += cortex-m7 diff --git a/Ubiquitous/XiZi/board/ok1052-c/Makefile b/Ubiquitous/XiZi/board/ok1052-c/Makefile index 837118429..c50f207a4 100644 --- a/Ubiquitous/XiZi/board/ok1052-c/Makefile +++ b/Ubiquitous/XiZi/board/ok1052-c/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := third_party_driver +SRC_DIR := third_party_driver xip SRC_FILES := board.c diff --git a/Ubiquitous/XiZi/board/ok1052-c/README.md b/Ubiquitous/XiZi/board/ok1052-c/README.md index 81477339f..4e489f05c 100644 --- a/Ubiquitous/XiZi/board/ok1052-c/README.md +++ b/Ubiquitous/XiZi/board/ok1052-c/README.md @@ -161,7 +161,10 @@ make BOARD=ok1052-c 2、ok1052-c开发板支持micro usb口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用usb线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，按下复位键K1后，若连接成功，可见Vendor ID和Product ID均有数字显示，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示： ![NXPBootUtility_1](./img/NXPBootUtility_1.png) -3、选择编译生成的XiZi_ok1052-c.elf文件路径，并选择.out(elf) from GCC ARM烧写选项，最后点击ALL-In-One Action即可烧写程序，若烧写无误，则下列绿色进度条会执行到底。如下图所示： +3、同时需要匹配ok1052-c开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示： +![flashconfig](./img/flashconfig.png) + +4、选择编译生成的XiZi_ok1052-c.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示： ![NXPBootUtility_2](./img/NXPBootUtility_2.png) ### 3.2 运行结果 diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png b/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png index 671bcb0c2..a607ce8e5 100644 Binary files a/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png and b/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png differ diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/flashconfig.png b/Ubiquitous/XiZi/board/ok1052-c/img/flashconfig.png new file mode 100644 index 000000000..9db4bd312 Binary files /dev/null and b/Ubiquitous/XiZi/board/ok1052-c/img/flashconfig.png differ diff --git a/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds b/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds index d98553676..0af5e162f 100755 --- a/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds +++ b/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds @@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; /* Specify the memory areas */ MEMORY { + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 @@ -63,6 +66,17 @@ MEMORY /* Define output sections */ SECTIONS { + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table /* The startup code goes first into internal RAM */ .interrupts : diff --git a/Ubiquitous/XiZi/board/ok1052-c/link.lds b/Ubiquitous/XiZi/board/ok1052-c/link.lds index 582743f76..d9fce959f 100644 --- a/Ubiquitous/XiZi/board/ok1052-c/link.lds +++ b/Ubiquitous/XiZi/board/ok1052-c/link.lds @@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; /* Specify the memory areas */ MEMORY { + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 @@ -63,6 +66,17 @@ MEMORY /* Define output sections */ SECTIONS { + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table /* The startup code goes first into internal RAM */ .interrupts : diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c index a61d7d035..dd6697921 100755 --- a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c +++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c @@ -13,7 +13,7 @@ * @brief support gpio function using bus driver framework * @version 2.0 * @author AIIT XUOS Lab -* @date 2022-03-16 +* @date 2022-03-22 */ /************************************************* @@ -22,7 +22,7 @@ Description: support gpio configure and register to bus framework Others: take RT-Thread v4.0.2/bsp/imxrt/libraries/drivers/drv_gpio.c for references https://github.com/RT-Thread/rt-thread/tree/v4.0.2 History: -1. Date: 2022-03-16 +1. Date: 2022-03-22 Author: AIIT XUOS Lab Modification: add bus driver framework support for gpio *************************************************/ @@ -215,6 +215,20 @@ struct PinIrqHdr pin_irq_hdr_tab[] = {-1, 0, NONE, NONE}, }; +#define MUX_BASE 0x401f8014 +#define CONFIG_BASE 0x401f8204 + +#define GPIO5_MUX_BASE 0x400A8000 +#define GPIO5_CONFIG_BASE 0x400A8018 + +const uint8_t reg_offset[] = +{ + 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105, + 112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + static int GetPin(struct PinIndex *pin_index, uint8_t pin) { pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5 @@ -229,39 +243,52 @@ static int GetPin(struct PinIndex *pin_index, uint8_t pin) return 0; } -static int32 GpioConfigMode(int mode, struct PinIndex *index) +static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin) { gpio_pin_config_t gpio_config; - NULL_PARAM_CHECK(index); + uint32_t config_value = 0; + NULL_PARAM_CHECK(pin_index); gpio_config.outputLogic = 0; + gpio_config.interruptMode = kGPIO_NoIntmode; switch (mode) { case GPIO_CFG_OUTPUT: gpio_config.direction = kGPIO_DigitalOutput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x0030U; /* Drive Strength R0/6 */ break; case GPIO_CFG_INPUT: gpio_config.direction = kGPIO_DigitalInput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x0830U; /* Open Drain Enable */ break; case GPIO_CFG_INPUT_PULLUP: gpio_config.direction = kGPIO_DigitalInput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0xB030U; /* 100K Ohm Pull Up */ break; case GPIO_CFG_INPUT_PULLDOWN: gpio_config.direction = kGPIO_DigitalInput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x3030U; /* 100K Ohm Pull Down */ break; case GPIO_CFG_OUTPUT_OD: gpio_config.direction = kGPIO_DigitalOutput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x0830U; /* Open Drain Enable */ break; default: break; } - GPIO_PinInit(index->gpio, index->pin, &gpio_config); + + if (pin_mask[pin_index->index].gpio != GPIO5) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1); + IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value); + } else { + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1); + IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value); + } + + GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config); return EOK; } @@ -392,7 +419,7 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param) switch(param->cmd) { case GPIO_CONFIG_MODE: - GpioConfigMode(param->mode, &pin_index); + GpioConfigMode(param->mode, &pin_index, param->pin); break; case GPIO_IRQ_REGISTER: ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args); @@ -554,6 +581,9 @@ static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Ty if (isr_status & (1 << i)) { GPIO_PortClearInterruptFlags(gpio, (1 << i)); + + __DSB(); + pin = index_offset + i; if (pin_irq_hdr_tab[pin].hdr) { pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args); @@ -705,21 +735,6 @@ void GpioLedTest(void) KPrintf("initialize %s failed!\n", PIN_BUS_NAME); return; } - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ struct PinParam led_gpio_param; struct PinStat led_gpio_stat; @@ -762,4 +777,3 @@ void GpioLedTest(void) SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED); #endif - diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/Makefile b/Ubiquitous/XiZi/board/ok1052-c/xip/Makefile new file mode 100755 index 000000000..e27f9550a --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/xip/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 000000000..503d56845 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,1149 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.c +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif + +const uint8_t dcd_sdram[1072] = { + /*0000*/ 0xD2, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x07, + 0x0A, + 0x09, +}; diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 000000000..b6677b274 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,123 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.h +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +//extern const uint8_t dcd_sdram[1044]; +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 000000000..c5cc52dbc --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,88 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.c +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t Qspiflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3u, + .csSetupTime = 3u, + .deviceModeCfgEnable = true, + .deviceModeType = 1,//Quad Enable command + .deviceModeSeq.seqNum = 1, + .deviceModeSeq.seqId = 4, + .deviceModeArg = 0x000200,//Set QE + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI + .sflashA1Size = 16u * 1024u * 1024u,//4MBytes + .dataValidTime = {16u, 16u}, + .lookupTable = + { +// //Fast Read Sequence +// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18), +// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08), +// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0), + //Quad Input/output read sequence + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), + //Read Status + [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + //Write Enable + [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), + //Write status + [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, +}; diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 000000000..73d4547b7 --- /dev/null +++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.h +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__ diff --git a/Ubiquitous/XiZi/board/xidatong/Makefile b/Ubiquitous/XiZi/board/xidatong/Makefile index 837118429..c50f207a4 100644 --- a/Ubiquitous/XiZi/board/xidatong/Makefile +++ b/Ubiquitous/XiZi/board/xidatong/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := third_party_driver +SRC_DIR := third_party_driver xip SRC_FILES := board.c diff --git a/Ubiquitous/XiZi/board/xidatong/README.md b/Ubiquitous/XiZi/board/xidatong/README.md index 3b8e2817b..5eddfd9a1 100644 --- a/Ubiquitous/XiZi/board/xidatong/README.md +++ b/Ubiquitous/XiZi/board/xidatong/README.md @@ -156,8 +156,17 @@ make BOARD=xidatong ## 3. 烧写及运行 ### 3.1 烧写 +1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility) +2、xidatong开发板支持UART串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用串口转USB线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，重新上电，选择对应的COM口和波特率（需关闭串口终端连接，确保该COM口空闲，否则会导致Utility工具连接失败），连接成功后，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示： +![NXPBootUtility_1](./img/NXPBootUtility_1.png) +3、同时需要匹配xidatong开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示： +![flashconfig](./img/flashconfig.png) + +4、选择编译生成的XiZi_xidatong.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示： +![NXPBootUtility_2](./img/NXPBootUtility_2.png) ### 3.2 运行结果 - +按照3.1烧写步骤执行后，将拨码开关设置为1 off 2 off 3 off 4 off，重新上电后，重新打开该COM口串口终端，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示： +![terminal](./img/terminal.png) diff --git a/Ubiquitous/XiZi/board/xidatong/board.c b/Ubiquitous/XiZi/board/xidatong/board.c index 6844ef96f..54a2f1966 100644 --- a/Ubiquitous/XiZi/board/xidatong/board.c +++ b/Ubiquitous/XiZi/board/xidatong/board.c @@ -70,6 +70,17 @@ int MountSDCard(void) #include #endif +#ifdef BSP_USING_SEMC +extern status_t BOARD_InitSEMC(void); +#ifdef BSP_USING_EXTSRAM +extern int ExtSramInit(void); +#endif +#endif + +#ifdef BSP_USING_LWIP +extern int ETH_BSP_Config(); +#endif + void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength) { IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, @@ -289,8 +300,10 @@ void InitBoardHardware() BOARD_InitPins(); BOARD_BootClockRUN(); +#ifndef BSP_USING_LWIP NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / TICK_PER_SECOND); +#endif #ifdef BSP_USING_GPIO Imxrt1052HwGpioInit(); @@ -300,22 +313,38 @@ void InitBoardHardware() BOARD_InitUartPins(); #endif -#ifdef BSP_USING_CH438 - BOARD_InitCh438Pins(); + InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END); + +#ifdef BSP_USING_SEMC + CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); + /* Set semc clock to 163.86 MHz */ + CLOCK_SetMux(kCLOCK_SemcMux, 1); + CLOCK_SetDiv(kCLOCK_SemcDiv, 1); + + if (BOARD_InitSEMC() != kStatus_Success) { + KPrintf("\r\n SEMC Init Failed\r\n"); + } +#ifdef MEM_EXTERN_SRAM + else { + ExtSramInit(); + } +#endif #endif - InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END); +#ifdef BSP_USING_LWIP + ETH_BSP_Config(); +#endif #ifdef BSP_USING_LPUART Imxrt1052HwUartInit(); #endif + InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); + #ifdef BSP_USING_CH438 Imxrt1052HwCh438Init(); #endif - InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); - #ifdef BSP_USING_SDIO Imxrt1052HwSdioInit(); #endif diff --git a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png index 734f03825..939f60f23 100644 Binary files a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png and b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png index 671bcb0c2..df8610a7a 100644 Binary files a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png and b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/flashconfig.png b/Ubiquitous/XiZi/board/xidatong/img/flashconfig.png new file mode 100644 index 000000000..9db4bd312 Binary files /dev/null and b/Ubiquitous/XiZi/board/xidatong/img/flashconfig.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png b/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png index ede182cfc..8da38688a 100644 Binary files a/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png and b/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png b/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png index 8cb7e6f40..cb8291f00 100644 Binary files a/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png and b/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/img/terminal.png b/Ubiquitous/XiZi/board/xidatong/img/terminal.png index 8dad4f4d1..75d214c2f 100644 Binary files a/Ubiquitous/XiZi/board/xidatong/img/terminal.png and b/Ubiquitous/XiZi/board/xidatong/img/terminal.png differ diff --git a/Ubiquitous/XiZi/board/xidatong/include/board.h b/Ubiquitous/XiZi/board/xidatong/include/board.h index b0a207fb5..9e9e12d44 100755 --- a/Ubiquitous/XiZi/board/xidatong/include/board.h +++ b/Ubiquitous/XiZi/board/xidatong/include/board.h @@ -62,7 +62,7 @@ void InitBoardHardware(void); #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/ /*! @brief The ENET PHY address. */ -#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */ +#define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */ /* USB PHY condfiguration */ #define BOARD_USB_PHY_D_CAL (0x0CU) diff --git a/Ubiquitous/XiZi/board/xidatong/link-usb.lds b/Ubiquitous/XiZi/board/xidatong/link-usb.lds index 570c10d29..fc005fd55 100755 --- a/Ubiquitous/XiZi/board/xidatong/link-usb.lds +++ b/Ubiquitous/XiZi/board/xidatong/link-usb.lds @@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; /* Specify the memory areas */ MEMORY { + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 @@ -63,6 +66,17 @@ MEMORY /* Define output sections */ SECTIONS { + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table /* The startup code goes first into internal RAM */ .interrupts : diff --git a/Ubiquitous/XiZi/board/xidatong/link.lds b/Ubiquitous/XiZi/board/xidatong/link.lds index b4176b174..38d111b23 100644 --- a/Ubiquitous/XiZi/board/xidatong/link.lds +++ b/Ubiquitous/XiZi/board/xidatong/link.lds @@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; /* Specify the memory areas */ MEMORY { + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 @@ -63,7 +66,18 @@ MEMORY /* Define output sections */ SECTIONS { + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + /* The startup code goes first into internal RAM */ .interrupts : { diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig index 3277d6e95..1c4cbea81 100644 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig @@ -21,6 +21,18 @@ menuconfig BSP_USING_GPIO source "$BSP_DIR/third_party_driver/gpio/Kconfig" endif +menuconfig BSP_USING_LWIP + bool "Using LwIP device" + default n + select RESOURCES_LWIP + +menuconfig BSP_USING_SEMC + bool "Using SEMC device" + default n + if BSP_USING_SEMC + source "$BSP_DIR/third_party_driver/semc/Kconfig" + endif + menuconfig BSP_USING_SDIO bool "Using SD card device" default n diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile index 7d1446aa2..b439cc98f 100644 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile @@ -1,5 +1,13 @@ SRC_DIR := common gpio +ifeq ($(CONFIG_BSP_USING_LWIP),y) + SRC_DIR += ethernet +endif + +ifeq ($(CONFIG_BSP_USING_SEMC),y) + SRC_DIR += semc +endif + ifeq ($(CONFIG_BSP_USING_LPUART),y) SRC_DIR += uart endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig new file mode 100644 index 000000000..389b67525 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig @@ -0,0 +1,39 @@ +config CH438_BUS_NAME + string + default "extuart" + +config CH438_DRIVER_NAME + string + default "extuart_drv" + +config CH438_DEVICE_NAME_0 + string + default "extuart_dev0" + +config CH438_DEVICE_NAME_1 + string + default "extuart_dev1" + +config CH438_DEVICE_NAME_2 + string + default "extuart_dev2" + +config CH438_DEVICE_NAME_3 + string + default "extuart_dev3" + +config CH438_DEVICE_NAME_4 + string + default "extuart_dev4" + +config CH438_DEVICE_NAME_5 + string + default "extuart_dev5" + +config CH438_DEVICE_NAME_6 + string + default "extuart_dev6" + +config CH438_DEVICE_NAME_7 + string + default "extuart_dev7" diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile new file mode 100644 index 000000000..47968574c --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := connect_ch438.c + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c new file mode 100644 index 000000000..500a54fa7 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c @@ -0,0 +1,1350 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.c +* @brief support to register ch438 pointer and function +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-17 +*/ + +#include + +static const uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/ +static const uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/ +static BusType ch438_pin; +static int ch438_sem = NONE; + +static void Ch438Irq(void *parameter) +{ + KSemaphoreAbandon(ch438_sem); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void ImxrtUdelay(uint32 us) +{ + uint32 ticks; + uint32 told, tnow, tcnt = 0; + uint32 reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + + told = tnow; + if (tcnt >= ticks) { + break; + } + } + } +} + +void CH438SetOutput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d failed!\n", CH438_D0_PIN); + return ; + } + + pin_cfg.pin = CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d failed!\n", CH438_D1_PIN); + return ; + } + + pin_cfg.pin = CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d failed!\n", CH438_D2_PIN); + return ; + } + + pin_cfg.pin = CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d failed!\n", CH438_D3_PIN); + return ; + } + + pin_cfg.pin = CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d failed!\n", CH438_D4_PIN); + return ; + } + + pin_cfg.pin = CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d failed!\n", CH438_D5_PIN); + return ; + } + + pin_cfg.pin = CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d failed!\n", CH438_D6_PIN); + return ; + } + + pin_cfg.pin = CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d failed!\n", CH438_D7_PIN); + return ; + } +} + +void CH438SetInput(void) +{ + struct PinParam pin_cfg; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_D0_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D0_PIN pin %d INPUT_PULLUP failed!\n", CH438_D0_PIN); + return ; + } + + pin_cfg.pin = CH438_D1_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D1_PIN pin %d INPUT_PULLUP failed!\n", CH438_D1_PIN); + return ; + } + + pin_cfg.pin = CH438_D2_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D2_PIN pin %d INPUT_PULLUP failed!\n", CH438_D2_PIN); + return ; + } + + pin_cfg.pin = CH438_D3_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D3_PIN pin %d INPUT_PULLUP failed!\n", CH438_D3_PIN); + return ; + } + + pin_cfg.pin = CH438_D4_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D4_PIN pin %d INPUT_PULLUP failed!\n", CH438_D4_PIN); + return ; + } + + pin_cfg.pin = CH438_D5_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D5_PIN pin %d INPUT_PULLUP failed!\n", CH438_D5_PIN); + return ; + } + + pin_cfg.pin = CH438_D6_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D6_PIN pin %d INPUT_PULLUP failed!\n", CH438_D6_PIN); + return ; + } + + pin_cfg.pin = CH438_D7_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config CH438_D7_PIN pin %d INPUT_PULLUP failed!\n", CH438_D7_PIN); + return ; + } +} + +/********************************************************************************************************* +** Function name: ReadCH438Data +** Function: read data from CH438 +** input: address +** +** output: data +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +uint8 ReadCH438Data( uint8 addr ) +{ +//read data api + +//ALE WR RD is high level when not busy, when reading data, put address on the serial port and put ALE low level for a few clock + +//switch input pin, put RD low level, delay a few clock, read the data from the serial port + +//put RD and ALE high level + uint8 dat; + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + struct BusBlockReadParam read_param; + write_param.buffer = (void *)&pin_stat; + read_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + ImxrtUdelay(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + CH438SetInput(); + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + dat = 0; + + pin_stat.pin = CH438_D7_PIN; + if(BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x80; + + pin_stat.pin = CH438_D6_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x40; + + pin_stat.pin = CH438_D5_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x20; + + pin_stat.pin = CH438_D4_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x10; + + pin_stat.pin = CH438_D3_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x08; + + pin_stat.pin = CH438_D2_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x04; + + pin_stat.pin = CH438_D1_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x02; + + pin_stat.pin = CH438_D0_PIN; + if (BusDevReadData(ch438_pin->owner_haldev, &read_param)) + dat |= 0x01; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + return dat; +} + +void WriteCH438Data(uint8 addr, uint8 dat) +{ + struct PinStat pin_stat; + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NRD_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + CH438SetOutput(); + ImxrtUdelay(1); + + if (addr &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (addr &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + if (dat &0x80) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D7_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x40) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D6_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x20) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D5_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x10) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D4_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x08) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D3_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x04) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D2_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x02) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D1_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + if (dat &0x01) { + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } else { + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_D0_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + } + + ImxrtUdelay(1); + + pin_stat.val = GPIO_LOW; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_NWR_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + pin_stat.val = GPIO_HIGH; + pin_stat.pin = CH438_ALE_PIN; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + ImxrtUdelay(1); + + CH438SetInput(); + + return; +} + +/********************************************************************************************************* +** Function name: WriteCH438Block +** Function: write data to CH438 +** input: CH438 register address, data block length, data cache address +** +** output: +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf) +{ + while (mlen--) { + WriteCH438Data(maddr, *mbuf++); + } +} + +/********************************************************************************************************* +** Function name: Ch438UartSend +** Function: active FIFO mode, CH438 send multibyte data by uart 0, max length is 128 bytes a single time +** input: send data cache address, send data length +** +** output: +** +** date: 2011.8.26. +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +void Ch438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num ) +{ + uint8 REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + + while (1) { + while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); /* wait for sending data done, THR and TSR is NULL */ + + if (Num <= 128) { + WriteCH438Block(REG_THR_ADDR, Num, data); + break; + } else { + WriteCH438Block(REG_THR_ADDR, 128, data); + Num -= 128; + data += 128; + } + } +} + +/********************************************************************************************************* +** Function name: Ch438UartRcv +** Function: forbidden FIFO mode, CH438 receive multibyte data from uart 0 +** input: recv data address +** +** output: recv data length +** +** date: 2011.8.26 +**------------------------------------------------------------------------------------------------------- +** modify: +** date: +**------------------------------------------------------------------------------------------------------- +********************************************************************************************************/ +uint8 Ch438UartRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size) +{ + uint8 rcv_num = 0; + uint8 dat = 0; + uint8 REG_LSR_ADDR,REG_RBR_ADDR; + uint8 *read_buffer; + x_size_t buffer_index = 0; + + read_buffer = buf; + + REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + + while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); /* wait for data is ready */ + + while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) { + dat = ReadCH438Data(REG_RBR_ADDR); + + *read_buffer = dat; + read_buffer++; + buffer_index++; + + if (CH438_BUFFSIZE == buffer_index) { + buffer_index = 0; + read_buffer = buf; + } + + rcv_num = rcv_num + 1; + --size; + } + + return rcv_num; +} + +static void Timeout438Proc(void *parameter) +{ + uint8_t rbr,lsr; + + while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR0_ADDR ); + KPrintf("0.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR1_ADDR ); + KPrintf("1.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR2_ADDR ); + KPrintf("2.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR3_ADDR ); + KPrintf("3.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR4_ADDR ); + KPrintf("4.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR5_ADDR ); + KPrintf("5.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR6_ADDR ); + KPrintf("6.RBR=%02x\r\n",rbr); + } + + while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) { + rbr = ReadCH438Data( REG_RBR7_ADDR ); + KPrintf("7.RBR=%02x\r\n",rbr); + } +} + +void Ch438PortInit(uint8 ext_uart_no, uint32 BaudRate ) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */ + //MdelayKTask(50); + ImxrtUdelay(50000); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; //set LCR register DLAB bit 1 + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL); /* set bps */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN); /* set FIFO mode, 112 bytes */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0); /* 8 bit word size, 1 bit stop bit, no crc */ + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); /* enable interrupt */ + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS | BIT_MCR_DTR ); /* allow interrupt output, DTR and RTS is 1 */ + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST); /* release the data in FIFO */ +} + +void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate) +{ + uint32 div; + uint8 DLL,DLM,dlab; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + + REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */ + //MdelayKTask(50); + ImxrtUdelay(50000); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; //set LCR register DLAB bit 1 + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = (Fpclk >> 4) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data(REG_DLL_ADDR, DLL); /* set bps */ + WriteCH438Data(REG_DLM_ADDR, DLM); + WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_FIFOEN); /* set FIFO mode, 64 bytes */ + + WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0); /* 8 bit work size, 1 bit stop bit, even parity check */ + + WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV); /* enable interrupt */ + + WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS | BIT_MCR_DTR ); /* allow interrupt output, DTR and RTS is 1 */ + + WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST); /* release the data in FIFO */ +} + +static uint32 ImxrtCh438Configure(struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(ext_serial_cfg); + + switch (ext_serial_cfg->data_cfg.port_configure) + { + case PORT_CFG_INIT: + Ch438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + case PORT_CFG_PARITY_CHECK: + CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate); + break; + default: + KPrintf("ImxrtCh438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure); + return ERROR; + break; + } + + return EOK; +} + +static uint32 ImxrtCh438Init(struct SerialDriver *serial_drv, struct SerialCfgParam *ext_serial_cfg) +{ + NULL_PARAM_CHECK(serial_drv); + + struct PinParam pin_cfg; + struct PinStat pin_stat; + int ret = 0; + + struct BusConfigureInfo configure_info; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + struct BusBlockWriteParam write_param; + write_param.buffer = (void *)&pin_stat; + + ch438_pin = PinBusInitGet(); + + CH438SetOutput(); + + /* config NWR pin as output*/ + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_NWR_PIN; + pin_cfg.mode = GPIO_CFG_OUTPUT; + + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NWR pin %d failed!\n", CH438_NWR_PIN); + return ERROR; + } + + /* config NRD pin as output*/ + pin_cfg.pin = CH438_NRD_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config NRD pin %d failed!\n", CH438_NRD_PIN); + return ERROR; + } + + /* config ALE pin as output*/ + pin_cfg.pin = CH438_ALE_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config ALE pin %d failed!\n", CH438_ALE_PIN); + return ERROR; + } + + /* set NWR pin as high*/ + pin_stat.pin = CH438_NWR_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set NRD pin as high*/ + pin_stat.pin = CH438_NRD_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + /* set ALE pin as high*/ + pin_stat.pin = CH438_ALE_PIN; + pin_stat.val = GPIO_HIGH; + BusDevWriteData(ch438_pin->owner_haldev, &write_param); + + return ImxrtCh438Configure(ext_serial_cfg); +} + +static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = ImxrtCh438Init(serial_drv, ext_serial_cfg); + break; + default: + break; + } + + return ret; +} + +static uint32 ImxrtCh438WriteData(void *dev, struct BusBlockWriteParam *write_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(write_param); + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + Ch438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size); + + return EOK; +} + +static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param) +{ + NULL_PARAM_CHECK(dev); + NULL_PARAM_CHECK(read_param); + + x_err_t result; + uint8 rcv_num = 0; + uint8 gInterruptStatus; + uint8 InterruptStatus; + static uint8 dat; + uint8 REG_LCR_ADDR; + uint8 REG_DLL_ADDR; + uint8 REG_DLM_ADDR; + uint8 REG_IER_ADDR; + uint8 REG_MCR_ADDR; + uint8 REG_FCR_ADDR; + uint8 REG_RBR_ADDR; + uint8 REG_THR_ADDR; + uint8 REG_IIR_ADDR; + uint8 REG_LSR_ADDR; + uint8 REG_MSR_ADDR; + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER); + if (EOK == result) { + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + if (!gInterruptStatus) { + dat = ReadCH438Data(REG_LCR0_ADDR); + dat = ReadCH438Data(REG_IER0_ADDR); + dat = ReadCH438Data(REG_MCR0_ADDR); + dat = ReadCH438Data(REG_LSR0_ADDR); + dat = ReadCH438Data(REG_MSR0_ADDR); + dat = ReadCH438Data(REG_RBR0_ADDR); + dat = ReadCH438Data(REG_THR0_ADDR); + dat = ReadCH438Data(REG_IIR0_ADDR); + dat = dat ; + } else { + if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/ + REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR; + REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR; + REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR; + + InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/ + + switch( InterruptStatus ) + { + case INT_NOINT: /* NO INTERRUPT */ + break; + case INT_THR_EMPTY: /* THR EMPTY INTERRUPT*/ + break; + case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT*/ + case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/ + rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size); + read_param->read_length = rcv_num; + break; + case INT_RCV_LINES: /* RECV LINES INTERRUPT */ + ReadCH438Data( REG_LSR_ADDR ); + break; + case INT_MODEM_CHANGE: /* MODEM CHANGE INTERRUPT */ + ReadCH438Data( REG_MSR_ADDR ); + break; + default: + break; + } + } + } + } + return rcv_num; +} + +static const struct SerialDevDone dev_done = +{ + NONE, + NONE, + ImxrtCh438WriteData, + ImxrtCh438ReadData, +}; + +static void Ch438InitDefault(struct SerialDriver *serial_drv) +{ + struct PinParam pin_cfg; + BusType ch438_pin; + + struct BusConfigureInfo configure_info; + + int ret = 0; + configure_info.configure_cmd = OPE_CFG; + configure_info.private_data = (void *)&pin_cfg; + + ch438_sem = KSemaphoreCreate(0); + if (ch438_sem < 0) { + KPrintf("Ch438InitDefault create sem failed .\n"); + return; + } + + ch438_pin = PinBusInitGet(); + + pin_cfg.cmd = GPIO_CONFIG_MODE; + pin_cfg.pin = CH438_INT_PIN; + pin_cfg.mode = GPIO_CFG_INPUT_PULLUP; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", CH438_INT_PIN); + return; + } + + pin_cfg.cmd = GPIO_IRQ_REGISTER; + pin_cfg.pin = CH438_INT_PIN; + pin_cfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING; + pin_cfg.irq_set.hdr = Ch438Irq; + pin_cfg.irq_set.args = NONE; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_REGISTER %d failed!\n", CH438_INT_PIN); + return; + } + + //disable ch438 int gpio irq + pin_cfg.cmd = GPIO_IRQ_DISABLE; + pin_cfg.pin = CH438_INT_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_DISABLE %d failed!\n", CH438_INT_PIN); + return; + } + + //enable ch438 int gpio irq + pin_cfg.cmd = GPIO_IRQ_ENABLE; + pin_cfg.pin = CH438_INT_PIN; + ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info); + if (ret != EOK) { + KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_ENABLE %d failed!\n", CH438_INT_PIN); + return; + } +} + +static uint32 ImxrtCh438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name) +{ + x_err_t ret = EOK; + serial_dev->dev_done = &dev_done; + serial_dev->ext_serial_mode = RET_TRUE; + ret = SerialDeviceRegister(serial_dev, NONE, dev_name); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial device %s register error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int Imxrt1052HwCh438Init(void) +{ + static struct SerialBus serial_bus; + static struct SerialDriver serial_drv; + + x_err_t ret = EOK; + + ret = SerialBusInit(&serial_bus, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial bus init error %d\n", ret); + return ERROR; + } + + serial_drv.configure = Ch438DrvConfigure; + ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial driver init error %d\n", ret); + return ERROR; + } + + ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init Serial driver attach error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_0; + static struct SerialDevParam dev_param_0; + dev_param_0.ext_uart_no = 0; + serial_dev_0.haldev.private_data = (void *)&dev_param_0; + ret = ImxrtCh438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_1; + static struct SerialDevParam dev_param_1; + dev_param_1.ext_uart_no = 1; + serial_dev_1.haldev.private_data = (void *)&dev_param_1; + ret = ImxrtCh438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_2; + static struct SerialDevParam dev_param_2; + dev_param_2.ext_uart_no = 2; + serial_dev_2.haldev.private_data = (void *)&dev_param_2; + ret = ImxrtCh438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_3; + static struct SerialDevParam dev_param_3; + dev_param_3.ext_uart_no = 3; + serial_dev_3.haldev.private_data = (void *)&dev_param_3; + ret = ImxrtCh438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_4; + static struct SerialDevParam dev_param_4; + dev_param_4.ext_uart_no = 4; + serial_dev_4.haldev.private_data = (void *)&dev_param_4; + ret = ImxrtCh438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_5; + static struct SerialDevParam dev_param_5; + dev_param_5.ext_uart_no = 5; + serial_dev_5.haldev.private_data = (void *)&dev_param_5; + ret = ImxrtCh438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_6; + static struct SerialDevParam dev_param_6; + dev_param_6.ext_uart_no = 6; + serial_dev_6.haldev.private_data = (void *)&dev_param_6; + ret = ImxrtCh438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + static struct SerialHardwareDevice serial_dev_7; + static struct SerialDevParam dev_param_7; + dev_param_7.ext_uart_no = 7; + serial_dev_7.haldev.private_data = (void *)&dev_param_7; + ret = ImxrtCh438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7); + if (ret != EOK) { + KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret); + return ERROR; + } + + Ch438InitDefault(&serial_drv); + + return ret; +} + +#ifdef CH438_EXTUART_TEST +static void CH438RegTest(unsigned char num)//for test +{ + uint8 dat; + + KPrintf("current test serial num: %02x \r\n",offset_addr[num]); + KPrintf("IER: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//IER + KPrintf("IIR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//IIR + KPrintf("LCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//LCR + KPrintf("MCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//MCR + KPrintf("LSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//LSR + KPrintf("MSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//MSR + KPrintf("FCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//FCR + KPrintf("SSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_SSR_ADDR ));//SSR + + KPrintf("SCR0: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR + dat = 0x55; + WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat); + KPrintf("SCR55: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR + dat = 0xAA; + WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat); + KPrintf("SCRAA: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR +} + +static struct Bus *bus; +static struct HardwareDev *dev; +static struct Driver *drv; + +static void Ch438Read(void *parameter) +{ + uint8 RevLen; + uint8 ext_uart_no = 0; + uint8 i, cnt = 0; + + struct BusBlockReadParam read_param; + static uint8 Ch438Buff[8][256]; + + struct BusBlockWriteParam write_param; + + while (1) + { + KPrintf("ready to read test_ch438 data\n"); + + read_param.buffer = Ch438Buff[ext_uart_no]; + RevLen = BusDevReadData(dev, &read_param); + + KPrintf("test_ch438 get data %u\n", RevLen); + + if (RevLen) { + for(i = 0 ; i < RevLen; i ++) { + KPrintf("i %u data 0x%x\n", i, Ch438Buff[ext_uart_no][i]); + Ch438Buff[ext_uart_no][i] = 0; + } + + cnt ++; + write_param.buffer = &cnt; + write_param.size = 1; + BusDevWriteData(dev, &write_param); + } + + } +} + +static void TestCh438Init(void) +{ + x_err_t flag; + + struct BusConfigureInfo configure_info; + + bus = BusFind(CH438_BUS_NAME); + drv = BusFindDriver(bus, CH438_DRIVER_NAME); + + dev = BusFindDevice(bus, CH438_DEVICE_NAME_0); + + struct SerialCfgParam serial_cfg; + memset(&serial_cfg, 0, sizeof(struct SerialCfgParam)); + configure_info.configure_cmd = OPE_INT; + configure_info.private_data = (void *)&serial_cfg; + + serial_cfg.data_cfg.port_configure = PORT_CFG_INIT; + + serial_cfg.data_cfg.ext_uart_no = 0; + serial_cfg.data_cfg.serial_baud_rate = 115200; + BusDrvConfigure(drv, &configure_info); + + KPrintf("ready to create test_ch438 task\n"); + + int32 task_CH438_read = KTaskCreate("task_CH438_read", Ch438Read, NONE, 2048, 10); + flag = StartupKTask(task_CH438_read); + if (flag != EOK) { + KPrintf("StartupKTask task_CH438_read failed .\n"); + return; + } +} + +void TestCh438(void) +{ + TestCh438Init(); + + CH438RegTest(0); +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), + TestCh438, TestCh438, TestCh438 ); + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c index 27013148d..63eed88b2 100755 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c @@ -8,9 +8,9 @@ /** * @file pin_mux.c * @brief support imxrt1052-board pin configure -* @version 1.0 +* @version 2.0 * @author AIIT XUOS Lab -* @date 2021-05-29 +* @date 2022-03-22 */ /*********************************************************************************************************************** @@ -749,121 +749,9 @@ BOARD_InitPins: * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ - -void BOARD_InitSPIPins ( void ) -{ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, /* GPIO_AD_B0_00 is configured as LPSPI3_SCK */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 is configured as LPSPI3_SDO */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 is configured as LPSPI3_SDI */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 is configured as LPSPI3_PCS0 */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 is configured as LPSPI1_SCK */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 is configured as LPSPI1_PCS0 */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 is configured as LPSPI1_SDO */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 is configured as LPSPI1_SDI */ - 0U ); /* Software Input On Field: Input Path is determined by functionality */ - - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_AD_B0_00 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 PAD functional properties : */ - 0x10B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ -} void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - -// IOMUXC_SetPinMux( -// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ -// 0U); /* Software Input On Field: Input Path is determined by functionality */ + /* Software Input On Field: Input Path is determined by functionality */ SemcPinmuxConfig(); IOMUXC_SetPinMux( @@ -914,16 +802,6 @@ void BOARD_InitPins(void) { IOMUXC_SetPinMux( IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ 0U); /* Software Input On Field: Input Path is determined by functionality */ -// IOMUXC_SetPinConfig( -// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ -// 0xB0A9u); /* Slew Rate Field: Fast Slew Rate -// Drive Strength Field: R0/5 -// Speed Field: medium(100MHz) -// Open Drain Enable Field: Open Drain Disabled -// Pull / Keep Enable Field: Pull/Keeper Enabled -// Pull / Keep Select Field: Pull -// Pull Up / Down Config. Field: 100K Ohm Pull Up -// Hyst. Enable Field: Hysteresis Disabled */ IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, /* GPIO_AD_B0_09 PAD functional properties : */ @@ -1073,37 +951,6 @@ void BOARD_InitPins(void) { Hyst. Enable Field: Hysteresis Disabled */ } -void BOARD_InitI2C1Pins ( void ) -{ - CLOCK_EnableClock ( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */ - 1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */ - IOMUXC_SetPinMux ( - IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */ - 1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */ - 0xD8B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 22K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig ( - IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */ - 0xD8B0u ); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 22K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ -} - void BOARD_InitUartPins(void) { #ifdef BSP_USING_LPUART1 @@ -1150,94 +997,6 @@ void BOARD_InitUartPins(void) #endif } -void BOARD_InitCh438Pins(void) -{ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, /* GPIO1_IO25 is configured as CH438_DATA0 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO1_IO24 is configured as CH438_DATA1 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, /* GPIO1_IO20 is configured as CH438_DATA2 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, /* GPIO1_IO21 is configured as CH438_DATA3 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, /* GPIO1_IO31 is configured as CH438_DATA4 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, /* GPIO1_IO28 is configured as CH438_DATA5 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, /* GPIO1_IO30 is configured as CH438_DATA6 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, /* GPIO1_IO29 is configured as CH438_DATA7 */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, /* GPIO3_IO04 is configured as CH438_nWR */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, /* GPIO3_IO02 is configured as CH438_ALE */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, /* GPIO3_IO03 is configured as CH438_INT */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO3_IO02 is configured as CH438_485_A_DIR */ - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, /* GPIO1_IO00 is configured as CH438_485_B_DIR */ - 0U); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, /* GPIO1_IO25 is configured as CH438_DATA0 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO1_IO24 is configured as CH438_DATA1 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, /* GPIO1_IO20 is configured as CH438_DATA2 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, /* GPIO1_IO21 is configured as CH438_DATA3 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, /* GPIO1_IO31 is configured as CH438_DATA4 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, /* GPIO1_IO28 is configured as CH438_DATA5 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, /* GPIO1_IO30 is configured as CH438_DATA6 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, /* GPIO1_IO29 is configured as CH438_DATA7 */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, /* GPIO3_IO04 is configured as CH438_nWR */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, /* GPIO3_IO02 is configured as CH438_ALE */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, /* GPIO3_IO03 is configured as CH438_INT */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO3_IO02 is configured as CH438_485_A_DIR */ - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, /* GPIO1_IO00 is configured as CH438_485_B_DIR */ - 0x10B0u); -} /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Kconfig new file mode 100755 index 000000000..8b1378917 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Kconfig @@ -0,0 +1 @@ + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile new file mode 100755 index 000000000..65f5adc78 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := enet_ethernetif.c enet_ethernetif_kinetis.c fsl_enet.c +SRC_DIR := lan8720 +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif.c new file mode 100755 index 000000000..d04c8adb3 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif.c @@ -0,0 +1,313 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif.c + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/ethip6.h" +#include "netif/etharp.h" +#include "netif/ppp/pppoe.h" +#include "lwip/igmp.h" +#include "lwip/mld6.h" + +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) +//#include "FreeRTOS.h" +//#include "event_groups.h" +#endif + +#include "netif/ethernet.h" +#include "enet_ethernetif.h" +#include "enet_ethernetif_priv.h" + +#include "fsl_enet.h" +#include "fsl_phy.h" +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" + +#include "sys_arch.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void enet_delay(void) +{ + volatile uint32_t i = 0; + for (i = 0; i < 1000000; ++i) + { + __asm("NOP"); /* delay */ + } +} + +void Time_Update_LwIP(void) +{ +} + +void ethernetif_clk_init(void) +{ + const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1}; + CLOCK_InitEnetPll(&config); + SysTick_Config(USEC_TO_COUNT(1000U, CLOCK_GetFreq(kCLOCK_CoreSysClk))); +} + +void ethernetif_gpio_init(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); + + GPIO_PinInit(GPIO1, 3, &gpio_config); + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + GPIO_WritePinOutput(GPIO1, 3, 0); + enet_delay(); + GPIO_WritePinOutput(GPIO1, 3, 1); +} + +void ETH_BSP_Config(void) +{ + static int flag = 0; + if(flag == 0) + { + ethernetif_clk_init(); + ethernetif_gpio_init(); + flag = 1; + } +} + +void ethernetif_phy_init(struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig, + enet_config_t *config) +{ + uint32_t sysClock; + status_t status; + bool link = false; + uint32_t count = 0; + phy_speed_t speed; + phy_duplex_t duplex; + + sysClock = CLOCK_GetFreq(ethernetifConfig->clockName); + + LWIP_PLATFORM_DIAG(("Initializing PHY...\r\n")); + + while ((count < ENET_ATONEGOTIATION_TIMEOUT) && (!link)) + { + status = PHY_Init(*ethernetif_enet_ptr(ethernetif), ethernetifConfig->phyAddress, sysClock); + + if (kStatus_Success == status) + { + PHY_GetLinkStatus(*ethernetif_enet_ptr(ethernetif), ethernetifConfig->phyAddress, &link); + } + else if (kStatus_PHY_AutoNegotiateFail == status) + { + LWIP_PLATFORM_DIAG(("PHY Auto-negotiation failed. Please check the ENET cable connection and link partner setting.")); + } + else + { + LWIP_ASSERT("\r\nCannot initialize PHY.\r\n", 0); + } + + count++; + } + + if (link) + { + /* Get the actual PHY link speed. */ + PHY_GetLinkSpeedDuplex(*ethernetif_enet_ptr(ethernetif), ethernetifConfig->phyAddress, &speed, &duplex); + /* Change the MII speed and duplex for actual link status. */ + config->miiSpeed = (enet_mii_speed_t)speed; + config->miiDuplex = (enet_mii_duplex_t)duplex; + } +#if 0 /* Disable assert. If initial auto-negation is timeout, \ \ + the ENET is set to default (100Mbs and full-duplex). */ + else + { + LWIP_ASSERT("\r\nGiving up PHY initialization. Please check the ENET cable connection and link partner setting and reset the board.\r\n", 0); + } +#endif +} + +/** + * This function should be called when a packet is ready to be read + * from the interface. It uses the function ethernetif_linkinput() that + * should handle the actual reception of bytes from the network + * interface. Then the type of the received packet is determined and + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ + +void ethernetif_input(struct netif *netif) +{ + struct pbuf *p; + err_t ret = 0; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + /* move received packet into a new pbuf */ + while ((p = ethernetif_linkinput(netif)) != NULL) + { + /* pass all packets to ethernet_input, which decides what packets it supports */ + if ((ret = netif->input(p, netif)) != ERR_OK) + { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + lw_print("lw: [%s] ret %d p %p\n", __func__, ret, p); + pbuf_free(p); + p = NULL; + } + } +} + +static ENET_Type *ethernetif_get_enet_base(const uint8_t enetIdx) +{ + ENET_Type* enets[] = ENET_BASE_PTRS; + int arrayIdx; + int enetCount; + + for (arrayIdx = 0, enetCount = 0; arrayIdx < ARRAY_SIZE(enets); arrayIdx++) + { + if (enets[arrayIdx] != 0U) /* process only defined positions */ + { /* (some SOC headers count ENETs from 1 instead of 0) */ + if (enetCount == enetIdx) + { + return enets[arrayIdx]; + } + enetCount++; + } + } + return NULL; +} + +err_t ethernetif_init(struct netif *netif, struct ethernetif *ethernetif, + const uint8_t enetIdx, + const ethernetif_config_t *ethernetifConfig) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("ethernetifConfig != NULL", (ethernetifConfig != NULL)); + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); + + netif->state = ethernetif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; +/* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ +#if LWIP_IPV4 + netif->output = etharp_output; +#endif +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif /* LWIP_IPV6 */ + netif->linkoutput = ethernetif_linkoutput; + +#if LWIP_IPV4 && LWIP_IGMP + netif_set_igmp_mac_filter(netif, ethernetif_igmp_mac_filter); + netif->flags |= NETIF_FLAG_IGMP; +#endif +#if LWIP_IPV6 && LWIP_IPV6_MLD + netif_set_mld_mac_filter(netif, ethernetif_mld_mac_filter); + netif->flags |= NETIF_FLAG_MLD6; +#endif + + /* Init ethernetif parameters.*/ + *ethernetif_enet_ptr(ethernetif) = ethernetif_get_enet_base(enetIdx); + LWIP_ASSERT("*ethernetif_enet_ptr(ethernetif) != NULL", (*ethernetif_enet_ptr(ethernetif) != NULL)); + + /* set MAC hardware address length */ + netif->hwaddr_len = ETH_HWADDR_LEN; + + /* set MAC hardware address */ + memcpy(netif->hwaddr, ethernetifConfig->macAddress, NETIF_MAX_HWADDR_LEN); + + /* maximum transfer unit */ + netif->mtu = 1500; /* TODO: define a config */ + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* ENET driver initialization.*/ + ethernetif_enet_init(netif, ethernetif, ethernetifConfig); + +#if LWIP_IPV6 && LWIP_IPV6_MLD + /* + * For hardware/netifs that implement MAC filtering. + * All-nodes link-local is handled by default, so we must let the hardware know + * to allow multicast packets in. + * Should set mld_mac_filter previously. */ + if (netif->mld_mac_filter != NULL) + { + ip6_addr_t ip6_allnodes_ll; + ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll); + netif->mld_mac_filter(netif, &ip6_allnodes_ll, NETIF_ADD_MAC_FILTER); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + + return ERR_OK; +} + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_kinetis.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_kinetis.c new file mode 100755 index 000000000..fe8f7c3d1 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_kinetis.c @@ -0,0 +1,674 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif_kinetis.c + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include "sys_arch.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/ethip6.h" +#include "netif/etharp.h" +#include "netif/ppp/pppoe.h" +#include "lwip/igmp.h" +#include "lwip/mld6.h" + +#ifdef FSL_RTOS_XIUOS +#define USE_RTOS 1 +#define FSL_RTOS_FREE_RTOS +#endif + +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) + +#ifdef FSL_RTOS_XIUOS +#include "xs_sem.h" + +#else +#include "FreeRTOS.h" +#include "event_groups.h" +#include "list.h" +#endif + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +typedef TickType_t EventBits_t; + +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#define portBASE_TYPE long + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) + +#ifndef FSL_RTOS_XIUOS +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; +#endif + +#endif + +#include "enet_ethernetif.h" +#include "enet_ethernetif_priv.h" + +#include "fsl_enet.h" +#include "fsl_phy.h" + +#include "sys_arch.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** + * Helper struct to hold private data used to operate your ethernet interface. + */ +struct ethernetif +{ + ENET_Type *base; +#if (defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)) || \ + (USE_RTOS && defined(FSL_RTOS_FREE_RTOS)) + enet_handle_t handle; +#endif +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) + +#ifdef FSL_RTOS_XIUOS + int enetSemaphore; +#else + EventGroupHandle_t enetTransmitAccessEvent; +#endif + EventBits_t txFlag; +#endif + enet_rx_bd_struct_t *RxBuffDescrip; + enet_tx_bd_struct_t *TxBuffDescrip; + rx_buffer_t *RxDataBuff; + tx_buffer_t *TxDataBuff; +}; + + +/******************************************************************************* + * Code + ******************************************************************************/ +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) + +int32 lwip_obtain_semaphore(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + return (KSemaphoreObtain(ethernetif->enetSemaphore, WAITING_FOREVER) == EOK); +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, uint32_t ringId, enet_event_t event, void *param) +#else +static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param) +#endif /* FSL_FEATURE_ENET_QUEUE */ +{ + struct netif *netif = (struct netif *)param; + struct ethernetif *ethernetif = netif->state; + BaseType_t xResult; + + switch (event) + { + case kENET_RxEvent: + ethernetif_input(netif); + break; + case kENET_TxEvent: +#ifndef FSL_RTOS_XIUOS + { + portBASE_TYPE taskToWake = pdFALSE; + +#ifdef __CA7_REV + if (SystemGetIRQNestingLevel()) +#else + if (__get_IPSR()) +#endif + { + xResult = xEventGroupSetBitsFromISR(ethernetif->enetTransmitAccessEvent, ethernetif->txFlag, &taskToWake); + if ((pdPASS == xResult) && (pdTRUE == taskToWake)) + { + portYIELD_FROM_ISR(taskToWake); + } + } + else + { + xEventGroupSetBits(ethernetif->enetTransmitAccessEvent, ethernetif->txFlag); + } + } +#endif + break; + default: + break; + } + + KSemaphoreAbandon(ethernetif->enetSemaphore); +} +#endif + +#if LWIP_IPV4 && LWIP_IGMP +err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group, + enum netif_mac_filter_action action) +{ + struct ethernetif *ethernetif = netif->state; + uint8_t multicastMacAddr[6]; + err_t result; + + multicastMacAddr[0] = 0x01U; + multicastMacAddr[1] = 0x00U; + multicastMacAddr[2] = 0x5EU; + multicastMacAddr[3] = (group->addr >> 8) & 0x7FU; + multicastMacAddr[4] = (group->addr >> 16) & 0xFFU; + multicastMacAddr[5] = (group->addr >> 24) & 0xFFU; + + switch (action) + { + case IGMP_ADD_MAC_FILTER: + /* Adds the ENET device to a multicast group.*/ + ENET_AddMulticastGroup(ethernetif->base, multicastMacAddr); + result = ERR_OK; + break; + case IGMP_DEL_MAC_FILTER: + /* + * Moves the ENET device from a multicast group. + * Since the ENET_LeaveMulticastGroup() could filter out also other + * group addresses having the same hash, the call is commented out. + */ + /* ENET_LeaveMulticastGroup(ethernetif->base, multicastMacAddr); */ + result = ERR_OK; + break; + default: + result = ERR_IF; + break; + } + + return result; +} +#endif + +#if LWIP_IPV6 && LWIP_IPV6_MLD +err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group, + enum netif_mac_filter_action action) +{ + struct ethernetif *ethernetif = netif->state; + uint8_t multicastMacAddr[6]; + err_t result; + + multicastMacAddr[0] = 0x33U; + multicastMacAddr[1] = 0x33U; + multicastMacAddr[2] = (group->addr[3]) & 0xFFU; + multicastMacAddr[3] = (group->addr[3] >> 8) & 0xFFU; + multicastMacAddr[4] = (group->addr[3] >> 16) & 0xFFU; + multicastMacAddr[5] = (group->addr[3] >> 24) & 0xFFU; + + switch (action) + { + case NETIF_ADD_MAC_FILTER: + /* Adds the ENET device to a multicast group.*/ + ENET_AddMulticastGroup(ethernetif->base, multicastMacAddr); + result = ERR_OK; + break; + case NETIF_DEL_MAC_FILTER: + /* + * Moves the ENET device from a multicast group. + * Since the ENET_LeaveMulticastGroup() could filter out also other + * group addresses having the same hash, the call is commented out. + */ + /* ENET_LeaveMulticastGroup(ethernetif->base, multicastMacAddr); */ + result = ERR_OK; + break; + default: + result = ERR_IF; + break; + } + + return result; +} +#endif + +/** + * Initializes ENET driver. + */ +void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig) +{ + enet_config_t config; + uint32_t sysClock; + enet_buffer_config_t buffCfg[ENET_RING_NUM]; + + /* prepare the buffer configuration. */ + buffCfg[0].rxBdNumber = ENET_RXBD_NUM; /* Receive buffer descriptor number. */ + buffCfg[0].txBdNumber = ENET_TXBD_NUM; /* Transmit buffer descriptor number. */ + buffCfg[0].rxBuffSizeAlign = sizeof(rx_buffer_t); /* Aligned receive data buffer size. */ + buffCfg[0].txBuffSizeAlign = sizeof(tx_buffer_t); /* Aligned transmit data buffer size. */ + buffCfg[0].rxBdStartAddrAlign = &(ethernetif->RxBuffDescrip[0]); /* Aligned receive buffer descriptor start address. */ + buffCfg[0].txBdStartAddrAlign = &(ethernetif->TxBuffDescrip[0]); /* Aligned transmit buffer descriptor start address. */ + buffCfg[0].rxBufferAlign = &(ethernetif->RxDataBuff[0][0]); /* Receive data buffer start address. */ + buffCfg[0].txBufferAlign = &(ethernetif->TxDataBuff[0][0]); /* Transmit data buffer start address. */ + + sysClock = CLOCK_GetFreq(ethernetifConfig->clockName); + + ENET_GetDefaultConfig(&config); + config.ringNum = ENET_RING_NUM; + + ethernetif_phy_init(ethernetif, ethernetifConfig, &config); + +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) + uint32_t instance; + static ENET_Type *const enetBases[] = ENET_BASE_PTRS; + static const IRQn_Type enetTxIrqId[] = ENET_Transmit_IRQS; + /*! @brief Pointers to enet receive IRQ number for each instance. */ + static const IRQn_Type enetRxIrqId[] = ENET_Receive_IRQS; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /*! @brief Pointers to enet timestamp IRQ number for each instance. */ + static const IRQn_Type enetTsIrqId[] = ENET_1588_Timer_IRQS; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Create the Event for transmit busy release trigger. */ +#ifdef FSL_RTOS_XIUOS + if(ethernetif->enetSemaphore < 0) + { + ethernetif->enetSemaphore = KSemaphoreCreate(0); + } +#else + ethernetif->enetTransmitAccessEvent = xEventGroupCreate(); +#endif + ethernetif->txFlag = 0x1; + + config.interrupt |= kENET_RxFrameInterrupt | kENET_TxFrameInterrupt | kENET_TxBufferInterrupt; + + for (instance = 0; instance < ARRAY_SIZE(enetBases); instance++) + { + if (enetBases[instance] == ethernetif->base) + { +#ifdef __CA7_REV + GIC_SetPriority(enetRxIrqId[instance], ENET_PRIORITY); + GIC_SetPriority(enetTxIrqId[instance], ENET_PRIORITY); +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + GIC_SetPriority(enetTsIrqId[instance], ENET_1588_PRIORITY); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +#else + NVIC_SetPriority(enetRxIrqId[instance], ENET_PRIORITY); + NVIC_SetPriority(enetTxIrqId[instance], ENET_PRIORITY); +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + NVIC_SetPriority(enetTsIrqId[instance], ENET_1588_PRIORITY); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +#endif /* __CA7_REV */ + break; + } + } + + LWIP_ASSERT("Input Ethernet base error!", (instance != ARRAY_SIZE(enetBases))); +#endif /* USE_RTOS */ + + /* Initialize the ENET module.*/ + ENET_Init(ethernetif->base, ðernetif->handle, &config, &buffCfg[0], netif->hwaddr, sysClock); + +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) + ENET_SetCallback(ðernetif->handle, ethernet_callback, netif); +#endif + + ENET_ActiveRead(ethernetif->base); +// low_level_init(); +} + +ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif) +{ + return &(ethernetif->base); +} + +/** + * Returns next buffer for TX. + * Can wait if no buffer available. + */ +static unsigned char *enet_get_tx_buffer(struct ethernetif *ethernetif) +{ + static unsigned char ucBuffer[ENET_FRAME_MAX_FRAMELEN]; + return ucBuffer; +} + +/** + * Sends frame via ENET. + */ +static err_t enet_send_frame(struct ethernetif *ethernetif, unsigned char *data, const uint32_t length) +{ +#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS) + { + status_t result; + + lw_print("lw: [%s] len %d\n", __func__, length); + + do + { + result = ENET_SendFrame(ethernetif->base, ðernetif->handle, data, length); + + if (result == kStatus_ENET_TxFrameBusy) + { +#ifdef FSL_RTOS_XIUOS + KSemaphoreObtain(ethernetif->enetSemaphore, portMAX_DELAY); +#else + xEventGroupWaitBits(ethernetif->enetTransmitAccessEvent, ethernetif->txFlag, pdTRUE, (BaseType_t) false, + portMAX_DELAY); +#endif + } + + } while (result == kStatus_ENET_TxFrameBusy); + + return ERR_OK; + } +#else + { + uint32_t counter; + + for (counter = ENET_TIMEOUT; counter != 0U; counter--) + { + if (ENET_SendFrame(ethernetif->base, ðernetif->handle, data, length) != kStatus_ENET_TxFrameBusy) + { + return ERR_OK; + } + } + + return ERR_TIMEOUT; + } +#endif +} + +struct pbuf *ethernetif_linkinput(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *p = NULL; + struct pbuf *q; + uint32_t len; + status_t status; + + /* Obtain the size of the packet and put it into the "len" + variable. */ + status = ENET_GetRxFrameSize(ðernetif->handle, &len); + + if (kStatus_ENET_RxFrameEmpty != status) + { + /* Call ENET_ReadFrame when there is a received frame. */ + if (len != 0) + { +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) + { +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + if (p->next == 0) /* One-chain buffer.*/ + { + ENET_ReadFrame(ethernetif->base, ðernetif->handle, p->payload, p->len); + } + else /* Multi-chain buffer.*/ + { + uint8_t data_tmp[ENET_FRAME_MAX_FRAMELEN]; + uint32_t data_tmp_len = 0; + + ENET_ReadFrame(ethernetif->base, ðernetif->handle, data_tmp, p->tot_len); + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for (q = p; (q != NULL) && ((data_tmp_len + q->len) <= sizeof(data_tmp)); q = q->next) + { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. */ + memcpy(q->payload, &data_tmp[data_tmp_len], q->len); + data_tmp_len += q->len; + } + } + + MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); + if (((u8_t *)p->payload)[0] & 1) + { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifinnucastpkts); + } + else + { + /* unicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + } +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } + else + { + /* drop packet*/ + ENET_ReadFrame(ethernetif->base, ðernetif->handle, NULL, 0U); + + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_linkinput: Fail to allocate new memory space\n")); + + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifindiscards); + } + } + else + { + /* Update the received buffer when error happened. */ + if (status == kStatus_ENET_RxFrameError) + { +#if 0 && defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0) /* Error statisctics */ + enet_data_error_stats_t eErrStatic; + /* Get the error information of the received g_frame. */ + ENET_GetRxErrBeforeReadFrame(ðernetif->handle, &eErrStatic); +#endif + /* Update the receive buffer. */ + ENET_ReadFrame(ethernetif->base, ðernetif->handle, NULL, 0U); + + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_linkinput: RxFrameError\n")); + + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifindiscards); + } + } + } + + return p; +} + +err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) +{ + err_t result; + struct ethernetif *ethernetif = netif->state; + struct pbuf *q; + unsigned char *pucBuffer; + unsigned char *pucChar; + + LWIP_ASSERT("Output packet buffer empty", p); + + pucBuffer = enet_get_tx_buffer(ethernetif); + if (pucBuffer == NULL) + { + return ERR_BUF; + } + +/* Initiate transfer. */ + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + if (p->len == p->tot_len) + { + /* No pbuf chain, don't have to copy -> faster. */ + pucBuffer = (unsigned char *)p->payload; + } + else + { + /* pbuf chain, copy into contiguous ucBuffer. */ + if (p->tot_len > ENET_FRAME_MAX_FRAMELEN) + { + return ERR_BUF; + } + else + { + pucChar = pucBuffer; + + for (q = p; q != NULL; q = q->next) + { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + /* send data from(q->payload, q->len); */ + memcpy(pucChar, q->payload, q->len); + pucChar += q->len; + } + } + } + + /* Send frame. */ + result = enet_send_frame(ethernetif, pucBuffer, p->tot_len); + + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); + if (((u8_t *)p->payload)[0] & 1) + { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + } + else + { + /* unicast packet */ + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + } +/* increase ifoutdiscards or ifouterrors on error */ + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return result; +} + +/** + * Should be called at the beginning of the program to set up the + * first network interface. It calls the function ethernetif_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif0_init(struct netif *netif) +{ + static struct ethernetif ethernetif_0; + AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + SDK_ALIGN(static rx_buffer_t rxDataBuff_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + SDK_ALIGN(static tx_buffer_t txDataBuff_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + + ethernetif_0.RxBuffDescrip = &(rxBuffDescrip_0[0]); + ethernetif_0.TxBuffDescrip = &(txBuffDescrip_0[0]); + ethernetif_0.RxDataBuff = &(rxDataBuff_0[0]); + ethernetif_0.TxDataBuff = &(txDataBuff_0[0]); + + return ethernetif_init(netif, ðernetif_0, 0U, (ethernetif_config_t *)netif->state); +} + +#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 1) +/** + * Should be called at the beginning of the program to set up the + * second network interface. It calls the function ethernetif_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif1_init(struct netif *netif) +{ + static struct ethernetif ethernetif_1; + AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_1[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + SDK_ALIGN(static rx_buffer_t rxDataBuff_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + SDK_ALIGN(static tx_buffer_t txDataBuff_1[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + + ethernetif_1.RxBuffDescrip = &(rxBuffDescrip_1[0]); + ethernetif_1.TxBuffDescrip = &(txBuffDescrip_1[0]); + ethernetif_1.RxDataBuff = &(rxDataBuff_1[0]); + ethernetif_1.TxDataBuff = &(txDataBuff_1[0]); + + return ethernetif_init(netif, ðernetif_1, 1U, (ethernetif_config_t *)netif->state); +} +#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_lpc.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_lpc.c new file mode 100755 index 000000000..622fb8b2d --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_lpc.c @@ -0,0 +1,960 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif_lpc.c + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/sys.h" +#include "lwip/ethip6.h" +#include "netif/etharp.h" +#include "netif/ppp/pppoe.h" +#include "lwip/igmp.h" +#include "lwip/mld6.h" + +//#if !NO_SYS +//#include "FreeRTOS.h" +//#include "event_groups.h" +//#include "lwip/tcpip.h" +//#endif /* !NO_SYS */ + +#include "enet_ethernetif.h" +#include "enet_ethernetif_priv.h" + +#include "fsl_enet.h" +#include "fsl_phy.h" + +//#if MEM_ALIGNMENT != FSL_ENET_BUFF_ALIGNMENT +///* These two has to match for zero-copy functionality */ +//#error "MEM_ALIGNMENT != FSL_ENET_BUFF_ALIGNMENT" +//#endif /* MEM_ALIGNMENT != FSL_ENET_BUFF_ALIGNMENT */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Used to wrap received data in a pbuf to be passed into lwIP + * without copying. + * Once last reference is released, RX descriptor will be returned to DMA. + */ +typedef struct rx_pbuf_wrapper +{ + struct pbuf_custom p; /*!< Pbuf wrapper. Has to be first. */ + enet_rx_bd_struct_t* rxDesc; /*!< Descriptor holding the data. */ + struct ethernetif *ethernetif; /*!< Ethernet interface context data. */ + volatile bool ownedByLwip; /*!< If true, descriptor cannot be reused by DMA yet. */ +} rx_pbuf_wrapper_t; + +/*! + * @brief Helper struct to hold private data used to operate + * your ethernet interface. + */ +struct ethernetif +{ + ENET_Type *base; + enet_handle_t handle; +#if !NO_SYS + EventGroupHandle_t enetTransmitAccessEvent; + EventBits_t txFlag; +#endif /* !NO_SYS */ + enet_rx_bd_struct_t *RxBuffDescrip; + enet_tx_bd_struct_t *TxBuffDescrip; + rx_buffer_t *RxDataBuff; + volatile struct pbuf *txPbufs[ENET_TXBD_NUM]; + volatile uint8_t txIdx; + volatile uint8_t txReleaseIdx; + rx_pbuf_wrapper_t rxPbufs[ENET_RXBD_NUM]; + uint8_t rxIdx; + const mem_range_t *non_dma_memory; +}; + +static void ethernetif_tx_release(struct ethernetif *ethernetif); +static void ethernetif_rx_release(struct pbuf *p); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/** + * Called from ENET ISR. + */ +static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, + enet_event_t event, uint8_t channel, void *param) +#if NO_SYS +{ + struct netif *netif = (struct netif *)param; + struct ethernetif *ethernetif = netif->state; + + if (event == kENET_TxIntEvent) + { + ethernetif_tx_release(ethernetif); + } +} +#else +{ + struct netif *netif = (struct netif *)param; + struct ethernetif *ethernetif = netif->state; + BaseType_t xResult; + + switch (event) + { + case kENET_RxIntEvent: + ethernetif_input(netif); + break; + case kENET_TxIntEvent: + { + portBASE_TYPE taskToWake = pdFALSE; + + ethernetif_tx_release(ethernetif); + +#ifdef __CA7_REV + if (SystemGetIRQNestingLevel()) +#else + if (__get_IPSR()) +#endif + { + xResult = xEventGroupSetBitsFromISR( + ethernetif->enetTransmitAccessEvent, + ethernetif->txFlag, &taskToWake); + if ((pdPASS == xResult) && (pdTRUE == taskToWake)) + { + portYIELD_FROM_ISR(taskToWake); + } + } + else + { + xEventGroupSetBits(ethernetif->enetTransmitAccessEvent, + ethernetif->txFlag); + } + + break; + } + default: + break; + } +} +#endif /* NO_SYS */ + +#if LWIP_IPV4 && LWIP_IGMP +err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group, + enum netif_mac_filter_action action) +{ + struct ethernetif *ethernetif = netif->state; + err_t result; + + switch (action) + { + case IGMP_ADD_MAC_FILTER: + /* LPC ENET does not accept multicast selectively, + * so all multicast has to be passed through. */ + ENET_AcceptAllMulticast(ethernetif->base); + result = ERR_OK; + break; + case IGMP_DEL_MAC_FILTER: + /* + * Moves the ENET device from a multicast group. + * Since we don't keep track of which multicast groups + * are still to enabled, the call is commented out. + */ + /* ENET_RejectAllMulticast(ethernetif->base); */ + result = ERR_OK; + break; + default: + result = ERR_IF; + break; + } + + return result; +} +#endif + +#if LWIP_IPV6 && LWIP_IPV6_MLD +err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group, + enum netif_mac_filter_action action) +{ + struct ethernetif *ethernetif = netif->state; + err_t result; + + switch (action) + { + case NETIF_ADD_MAC_FILTER: + /* LPC ENET does not accept multicast selectively, + * so all multicast has to be passed through. */ + ENET_AcceptAllMulticast(ethernetif->base); + result = ERR_OK; + break; + case NETIF_DEL_MAC_FILTER: + /* + * Moves the ENET device from a multicast group. + * Since we don't keep track of which multicast groups + * are still to enabled, the call is commented out. + */ + /* ENET_RejectAllMulticast(ethernetif->base); */ + result = ERR_OK; + break; + default: + result = ERR_IF; + break; + } + + return result; +} +#endif + +/** + * Gets the RX descriptor by its index. + */ +static inline enet_rx_bd_struct_t *ethernetif_get_rx_desc( + struct ethernetif *ethernetif, + uint32_t index) +{ + return &(ethernetif->RxBuffDescrip[index]); +} + +/** + * Gets the TX descriptor by its index. + */ +static inline enet_tx_bd_struct_t *ethernetif_get_tx_desc( + struct ethernetif *ethernetif, + uint32_t index) +{ + return &(ethernetif->TxBuffDescrip[index]); +} + +/** + * Initializes ENET driver. + */ +void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig) +{ + enet_config_t config; + uint32_t sysClock; + enet_buffer_config_t buffCfg[ENET_RING_NUM]; + uint32_t rxBufferStartAddr[ENET_RXBD_NUM]; + uint32_t i; + + /* calculate start addresses of all rx buffers */ + for (i = 0; i < ENET_RXBD_NUM; i++) + { + rxBufferStartAddr[i] = (uint32_t)&(ethernetif->RxDataBuff[i][ETH_PAD_SIZE]); + } + + /* prepare the buffer configuration. */ + buffCfg[0].rxRingLen = ENET_RXBD_NUM; /* The length of receive buffer descriptor ring. */ + buffCfg[0].txRingLen = ENET_TXBD_NUM; /* The length of transmit buffer descriptor ring. */ + buffCfg[0].txDescStartAddrAlign = ethernetif_get_tx_desc(ethernetif, 0U); /* Aligned transmit descriptor start address. */ + buffCfg[0].txDescTailAddrAlign = ethernetif_get_tx_desc(ethernetif, 0U); /* Aligned transmit descriptor tail address. */ + buffCfg[0].rxDescStartAddrAlign = ethernetif_get_rx_desc(ethernetif, 0U); /* Aligned receive descriptor start address. */ + buffCfg[0].rxDescTailAddrAlign = ethernetif_get_rx_desc(ethernetif, ENET_RXBD_NUM); /* Aligned receive descriptor tail address. */ + buffCfg[0].rxBufferStartAddr = rxBufferStartAddr; /* Start addresses of the rx buffers. */ + buffCfg[0].rxBuffSizeAlign = sizeof(rx_buffer_t); /* Aligned receive data buffer size. */ + + sysClock = CLOCK_GetFreq(ethernetifConfig->clockName); + + LWIP_ASSERT("ethernetifConfig->non_dma_memory == NULL", (ethernetifConfig->non_dma_memory != NULL)); + ethernetif->non_dma_memory = ethernetifConfig->non_dma_memory; + + ENET_GetDefaultConfig(&config); + config.multiqueueCfg = NULL; + + ethernetif_phy_init(ethernetif, ethernetifConfig, &config); + +#if !NO_SYS + /* Create the Event for transmit busy release trigger. */ + ethernetif->enetTransmitAccessEvent = xEventGroupCreate(); + ethernetif->txFlag = 0x1; +#endif /* !NO_SYS */ + NVIC_SetPriority(ETHERNET_IRQn, ENET_PRIORITY); + + ethernetif->txIdx = 0U; + ethernetif->rxIdx = 0U; + ethernetif->txReleaseIdx = 0U; + + for (i = 0; i < ENET_RXBD_NUM; i++) + { + ethernetif->rxPbufs[i].p.custom_free_function = ethernetif_rx_release; + ethernetif->rxPbufs[i].rxDesc = ðernetif->RxBuffDescrip[i]; + ethernetif->rxPbufs[i].ethernetif = ethernetif; + ethernetif->rxPbufs[i].ownedByLwip = false; + } + + ENET_Init(ethernetif->base, &config, netif->hwaddr, sysClock); + +#if defined(LPC54018_SERIES) + /* Workaround for receive issue on lpc54018 */ + ethernetif->base->MAC_FRAME_FILTER |= ENET_MAC_FRAME_FILTER_RA_MASK; +#endif + + /* Create the handler. */ +#if NO_SYS + ENET_EnableInterrupts(ethernetif->base, kENET_DmaTx); +#else + ENET_EnableInterrupts(ethernetif->base, kENET_DmaTx | kENET_DmaRx); +#endif /* NO_SYS */ + ENET_CreateHandler(ethernetif->base, ðernetif->handle, &config, + &buffCfg[0], ethernet_callback, netif); + + ENET_DescriptorInit(ethernetif->base, &config, &buffCfg[0]); + + /* Active TX/RX. */ + ENET_StartRxTx(ethernetif->base, 1, 1); +} + +ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif) +{ + return &(ethernetif->base); +} + +/** + * Find the ENET instance index from its base address. + */ +static uint32_t ethernetif_get_enet_idx(ENET_Type *base) +{ + static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + uint32_t instance; + + for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + + LWIP_ASSERT("Cannot find ENET instance index from its base address.", + instance < FSL_FEATURE_SOC_LPC_ENET_COUNT); + + return instance; +} + +/** + * Sends (part of) a frame via ENET. + * TODO: Since ENET_SendFrame() could not be used, some functionality it does + * is missing here for now (channel selection depending on AVB content, + * timestamping. + */ +static void ethernetif_send_buffer(struct ethernetif *ethernetif, + unsigned char *data, + const uint32_t length, + struct pbuf *p_to_release, + enet_desc_flag flag) +{ + static const IRQn_Type s_enetIrqId[] = ENET_IRQS; + enet_tx_bd_struct_t *txDesc = ethernetif_get_tx_desc(ethernetif, + ethernetif->txIdx); + ethernetif->txPbufs[ethernetif->txIdx] = p_to_release; + ethernetif->txIdx = (ethernetif->txIdx + 1) % ENET_TXBD_NUM; + + /* Prepare the descriptor for transmit. */ + txDesc->buff1Addr = (uint32_t)data; + txDesc->buff2Addr = (uint32_t)NULL; + txDesc->buffLen = + ENET_TXDESCRIP_RD_BL1(length) | ENET_TXDESCRIP_RD_IOC_MASK; + + txDesc->controlStat = + ENET_TXDESCRIP_RD_FL(length) | ENET_TXDESCRIP_RD_LDFD(flag); + if ((flag & kENET_FirstFlagOnly) == 0) + { + /* + * Submit to DMA if not the first descriptor in chain. + * All the descriptors have to be prepared before the first one + * is flagged for DMA and transfer starts. ENET could output invalid + * frames otherwise (the exception is Store and Forward mode, where + * delays between preparing of descriptors does not matter). + */ + txDesc->controlStat |= ENET_TXDESCRIP_RD_OWN_MASK; + } + + enet_tx_bd_ring_t *txBdRing = (enet_tx_bd_ring_t *) + ðernetif->handle.txBdRing[0]; + + /* + * Increment txDescUsed. + * Without this, callback would not fire from ENET ISR on finished TX. + * This is kind of a hack. Alternative could be to define + * void ETHERNET_DriverIRQHandler(void) and handle IRQs completely + * in this file. + */ + DisableIRQ(s_enetIrqId[ethernetif_get_enet_idx(ethernetif->base)]); + txBdRing->txDescUsed++; + EnableIRQ(s_enetIrqId[ethernetif_get_enet_idx(ethernetif->base)]); +} + +/** + * Reclaims exactly one TX descriptor after its data has been sent out. + * Then the descriptor can be used by application to prepare next data to send. + */ +static void ethernetif_tx_release(struct ethernetif *ethernetif) +{ + LWIP_ASSERT("Attempt to release more TX buffers than acquired.", + ethernetif->txIdx != ethernetif->txReleaseIdx); + enet_tx_bd_struct_t *txDesc + = ðernetif->TxBuffDescrip[ethernetif->txReleaseIdx]; + LWIP_ASSERT("TX buffer still owned by DMA.", + !ENET_IsTxDescriptorDmaOwn(txDesc)); + + struct pbuf *p = (struct pbuf *) + ethernetif->txPbufs[ethernetif->txReleaseIdx]; + if (p != NULL) + { +#if ETH_PAD_SIZE + /* Reclaim the padding, force because it may be REF pbuf. */ + pbuf_header_force(p, ETH_PAD_SIZE); +#endif + +#if NO_SYS +#if defined(LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT) && LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + pbuf_free(p); +#else + #error "Bare metal requires LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT=1 because pbuf_free() is being called from an ISR" +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ +#else + if (pbuf_free_callback(p) != ERR_OK) + { +#if defined(LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT) && LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + pbuf_free(p); +#else + LWIP_ASSERT("Failed to enqueue pbuf deallocation on tcpip_thread", + 0); +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + } +#endif /* NO_SYS */ + + ethernetif->txPbufs[ethernetif->txReleaseIdx] = NULL; + } + + ethernetif->txReleaseIdx = (ethernetif->txReleaseIdx + 1) % ENET_TXBD_NUM; +} + +/** + * Reclaims RX descriptor which holds the p's buffer after p is no longer used + * by the application / lwIP. The DMA can receive new data into + * the descriptor's buffer then. + * Note that RX buffers may be freed by lwIP out of the order in which they were + * passed to lwIP. Therefore there may be spaces between the RX descriptors + * flagged as owned by DMA and DMA could still wait until it's actual position + * is released. + */ +static void ethernetif_rx_release(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + rx_pbuf_wrapper_t *wrapper = (rx_pbuf_wrapper_t *)p; +#if NO_SYS + bool intEnable = false; +#else + bool intEnable = true; +#endif /* NO_SYS */ + + SYS_ARCH_PROTECT(old_level); + + wrapper->ownedByLwip = false; + + /* Update the receive buffer descriptor. */ + ENET_UpdateRxDescriptor(wrapper->rxDesc, NULL, NULL, intEnable, false); + ENET_UpdateRxDescriptorTail(wrapper->ethernetif->base, 0U, + (uint32_t)ethernetif_get_rx_desc(wrapper->ethernetif, ENET_RXBD_NUM)); + + SYS_ARCH_UNPROTECT(old_level); +} + +/** + * Gets the length of a received frame (if there is some). + */ +static status_t ethernetif_get_rx_frame_size(struct ethernetif *ethernetif, + uint32_t *length) +{ + uint8_t index = ethernetif->rxIdx; + enet_rx_bd_struct_t *rxDesc; + uint32_t rxControl; + + /* Reset the length to zero. */ + *length = 0; + + do + { + rxDesc = ethernetif_get_rx_desc(ethernetif, index); + rxControl = ENET_GetRxDescriptor(rxDesc); + + if ((rxControl & ENET_RXDESCRIP_WR_OWN_MASK) + || (ethernetif->rxPbufs[index].ownedByLwip)) + { + /* + * Buffer descriptor is owned by DMA or lwIP. + * We haven't received any complete frame yet. + */ + return kStatus_ENET_RxFrameEmpty; + } + + /* Application owns the buffer descriptor. */ + if (rxControl & ENET_RXDESCRIP_WR_LD_MASK) + { + /* It's last descriptor of a frame, get its status or length. */ + if (rxControl & ENET_RXDESCRIP_WR_ERRSUM_MASK) + { + return kStatus_ENET_RxFrameError; + } + else + { + *length = rxControl & ENET_RXDESCRIP_WR_PACKETLEN_MASK; + return kStatus_Success; + } + } + + index = (index + 1U) % ENET_RXBD_NUM; + } while (index != ethernetif->rxIdx); + + /* + * All descriptors have data but the end of the frame not detected. + */ + return kStatus_ENET_RxFrameError; +} + +/** + * Drops (releases) receive descriptors until the last one of a frame is reached + * or drops entire descriptor ring when all descriptors have data but end + * of the frame not detected among them. + * Function can be called only after ethernetif_get_rx_frame_size() indicates + * that there actually is a frame error or a received frame. + */ +static void ethernetif_drop_frame(struct ethernetif *ethernetif) +{ +#if NO_SYS + bool intEnable = false; +#else + bool intEnable = true; +#endif /* NO_SYS */ + + enet_rx_bd_struct_t *rxDesc; + uint8_t index = ethernetif->rxIdx; + uint32_t rxControl; + + do + { + rxDesc = ethernetif_get_rx_desc(ethernetif, ethernetif->rxIdx); + ethernetif->rxIdx = (ethernetif->rxIdx + 1U) % ENET_RXBD_NUM; + rxControl = ENET_GetRxDescriptor(rxDesc); + + /* Update the receive buffer descriptor. */ + ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, intEnable, false); + + /* Find the last buffer descriptor for the frame. */ + if (rxControl & ENET_RXDESCRIP_WR_LD_MASK) + { + break; + } + } while (ethernetif->rxIdx != index); + + ENET_UpdateRxDescriptorTail(ethernetif->base, 0U, + (uint32_t)ethernetif_get_rx_desc(ethernetif, ENET_RXBD_NUM)); +} + +/** + * Reads a received frame - wraps its descriptor buffer(s) into a pbuf + * or a pbuf chain, flag descriptors as owned by lwIP and returns the pbuf. + * The descriptors are returned to DMA only after the returned pbuf is released. + * Function can be called only after ethernetif_get_rx_frame_size() indicates + * that there actually is a received frame. + */ +static struct pbuf *ethernetif_read_frame(struct ethernetif *ethernetif, + uint32_t length) +{ + rx_pbuf_wrapper_t *wrapper; + enet_rx_bd_struct_t *rxDesc; + uint32_t rxControl; + uint32_t len = 0; + struct pbuf *p = NULL; + struct pbuf *q = NULL; + + do + { + wrapper = ðernetif->rxPbufs[ethernetif->rxIdx]; + wrapper->ownedByLwip = true; + ethernetif->rxIdx = (ethernetif->rxIdx + 1U) % ENET_RXBD_NUM; + + rxDesc = wrapper->rxDesc; + rxControl = ENET_GetRxDescriptor(rxDesc); + + len = (rxControl & ENET_RXDESCRIP_WR_PACKETLEN_MASK); + + /* Wrap the receive buffer in pbuf. */ + if (p == NULL) + { + p = pbuf_alloced_custom(PBUF_RAW, len, PBUF_REF, &wrapper->p, + (void *)rxDesc->buff1Addr, len); + LWIP_ASSERT("pbuf_alloced_custom() failed", p); + +#if ETH_PAD_SIZE + /* Add the padding header, force because it is a REF type buffer. */ + pbuf_header_force(p, ETH_PAD_SIZE); +#endif + } + else + { + q = pbuf_alloced_custom(PBUF_RAW, len, PBUF_REF, &wrapper->p, + (void *)rxDesc->buff1Addr, len); + LWIP_ASSERT("pbuf_alloced_custom() failed", q); + + pbuf_cat(p, q); + } + } while (((rxControl & ENET_RXDESCRIP_WR_LD_MASK) == 0U) + && (p->tot_len < length)); + + MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); + if (((u8_t *)p->payload)[0] & 1) + { + /* broadcast or multicast packet */ + MIB2_STATS_NETIF_INC(netif, ifinnucastpkts); + } + else + { + /* unicast packet */ + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + } + + LINK_STATS_INC(link.recv); + + return p; +} + +/** + * Attempts to read a frame from ENET and returns it wrapped in a pbuf + * or returns NULL when no frame is received. Discards invalid frames. + */ +struct pbuf *ethernetif_linkinput(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *p = NULL; + uint32_t len; + status_t status; + + /* Obtain the size of the packet and put it into the "len" variable. */ + status = ethernetif_get_rx_frame_size(ethernetif, &len); + + if (status == kStatus_Success) + { + p = ethernetif_read_frame(ethernetif, len); + + if (p == NULL) + { + /* Could not initialise wrapper pbuf(s) - drop the frame. */ + ethernetif_drop_frame(ethernetif); + + LWIP_DEBUGF(NETIF_DEBUG, + ("ethernetif_linkinput: Fail to allocate new memory space\n")); + + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifindiscards); + } + } + else if (status == kStatus_ENET_RxFrameError) + { + /* Update the received buffer when error happened. */ + ethernetif_drop_frame(ethernetif); + + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_linkinput: RxFrameError\n")); + + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifindiscards); + } + + return p; +} + +/** + * Returns the number of TX descriptors which could be used by lwIP/application + * to put new TX data into. + * + * The max number of free descriptors is (ENET_TXBD_NUM - 1), that is when + * ethernetif->txReleaseIdx == ethernetif->txIdx. Having the capacity decreased + * by one allows to avoid locking: txReleaseIdx is advanced only from ISR + * and txIdx from tcpip_thread/main loop. Should we use full capacity and have + * some variable to indicate between the "all buffers are free" vs. "all buffers + * are used" situation, it would be manipulated from two contexts hence locking + * would be needed. + */ +static inline int ethernetif_avail_tx_descs(struct ethernetif *ethernetif) +{ + return (ethernetif->txReleaseIdx + ENET_TXBD_NUM - 1 - ethernetif->txIdx) + % ENET_TXBD_NUM; +} + +/** + * Attempts to output a frame from ENET. The function avoids copying of + * p's payload when possible. In such situation it increases p's reference count + * and decreases it (and possibly releases p) after the payload is sent. + */ +err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *q; + struct pbuf *pbuf_to_free = NULL; + struct pbuf *p_copy; + uint16_t clen; + bool copy = false; + const mem_range_t *non_dma_memory; + uint8_t *dst; + uint32_t cnt = 0; + uint8_t first_idx; + uint32_t tail_address; + + LWIP_ASSERT("Output packet buffer empty", p); + + if ((p->tot_len - ETH_PAD_SIZE) > ENET_FRAME_MAX_FRAMELEN) + { + return ERR_BUF; + } + + clen = pbuf_clen(p); + + /* Check if relocation is needed */ + + if (clen > (ENET_TXBD_NUM - 1)) + { + /* Pbuf chain is too long to be prepared for DMA at once. */ + copy = true; + } + + for (q = p; (q != NULL) && !copy; q = q->next) + { + /* + * Check if payload is aligned is not desired: lwIP creates RAM pbufs + * in a way that the data coming after the headers are aligned, but not + * the beginning of the ethernet header. LPC ENET DMA will read from + * the aligned address, which is ok, because there is additional space + * before the headers to make up for alignment - so DMA will not read + * from invalid address or unrelated data. + */ + + /* Check payload address is usable by ENET DMA */ + for (non_dma_memory = ethernetif->non_dma_memory; + (non_dma_memory->start != 0U) + || (non_dma_memory->end != 0U); non_dma_memory++) + { + if ((q->payload >= (void *) non_dma_memory->start) + && (q->payload < (void *) non_dma_memory->end)) + { + copy = true; + break; + } + } + } + + if (copy) + { + /* Pbuf needs to be copied. */ + + p_copy = pbuf_alloc(PBUF_RAW, (uint16_t) p->tot_len, PBUF_POOL); + if (p_copy == NULL) + { + return ERR_MEM; + } + + dst = (uint8_t *) p_copy->payload; + for (q = p; q != NULL; q = q->next) + { + LWIP_ASSERT("Copied bytes would exceed p->tot_len", + (q->len + dst - (uint8_t *) p_copy->payload) <= p->tot_len); + memcpy(dst, (uint8_t *)q->payload, q->len); + dst += q->len; + } + LWIP_ASSERT("Copied bytes != p->tot_len", + (dst - (uint8_t *) p_copy->payload) == p->tot_len); + p_copy->len = p_copy->tot_len = p->tot_len; + + p = p_copy; + } + else + { + /* + * Increase reference count so p is released only after it is sent. + * For copied pbuf, ref is already 1 after pbuf_alloc(). + */ + pbuf_ref(p); + } + + /* + * Wait until the sufficient number of descriptors are available, + * as we have to start the transfer of the first buffer only + * after all buffers in chain are prepared. + */ + while (ethernetif_avail_tx_descs(ethernetif) < clen) + { +#if !NO_SYS + xEventGroupWaitBits(ethernetif->enetTransmitAccessEvent, + ethernetif->txFlag, pdTRUE, (BaseType_t) false, + portMAX_DELAY); +#endif /* !NO_SYS */ + cnt++; + if (cnt >= ENET_TIMEOUT) + { + return ERR_TIMEOUT; + } + } + +#if ETH_PAD_SIZE + /* Drop the padding. */ + pbuf_header(p, -ETH_PAD_SIZE); +#endif + + /* Initiate transfer. */ + + first_idx = ethernetif->txIdx; + + for (q = p; q != NULL; q = q->next) + { + enet_desc_flag flag = kENET_MiddleFlag; + pbuf_to_free = NULL; + + if (q == p) + { + flag |= kENET_FirstFlagOnly; + } + + if (q->next == NULL) + { + flag |= kENET_LastFlagOnly; + + /* On last TX interrupt, free pbuf chain. */ + pbuf_to_free = p; + } + + ethernetif_send_buffer(ethernetif, q->payload, q->len, pbuf_to_free, + flag); + } + + /* All pbufs from chain are prepared, allow DMA to access the first one. */ + ethernetif_get_tx_desc(ethernetif, first_idx)->controlStat |= + ENET_TXDESCRIP_RD_OWN_MASK; + + /* Update the transmit tail address. */ + if (ethernetif->txIdx == 0U) + { + tail_address = (uint32_t)ethernetif_get_tx_desc(ethernetif, + ENET_TXBD_NUM); + } + else + { + tail_address = (uint32_t)ethernetif_get_tx_desc(ethernetif, + ethernetif->txIdx); + } + ENET_UpdateTxDescriptorTail(ethernetif->base, 0, tail_address); + + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); + if (((uint8_t *)p->payload)[0] & 1) + { + /* broadcast or multicast packet */ + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + } + else + { + /* unicast packet */ + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + } + LINK_STATS_INC(link.xmit); + + return ERR_OK; +} + +/** + * Should be called at the beginning of the program to set up the + * first network interface. It calls the function ethernetif_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif0_init(struct netif *netif) +{ + static struct ethernetif ethernetif_0; + AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + SDK_ALIGN(static rx_buffer_t rxDataBuff_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + + ethernetif_0.RxBuffDescrip = &(rxBuffDescrip_0[0]); + ethernetif_0.TxBuffDescrip = &(txBuffDescrip_0[0]); + ethernetif_0.RxDataBuff = &(rxDataBuff_0[0]); + + return ethernetif_init(netif, ðernetif_0, 0U, (ethernetif_config_t *)netif->state); +} + +#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 1) +/** + * Should be called at the beginning of the program to set up the + * second network interface. It calls the function ethernetif_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif1_init(struct netif *netif) +{ + static struct ethernetif ethernetif_1; + AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_1[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + SDK_ALIGN(static rx_buffer_t rxDataBuff_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT); + + ethernetif_1.RxBuffDescrip = &(rxBuffDescrip_1[0]); + ethernetif_1.TxBuffDescrip = &(txBuffDescrip_1[0]); + ethernetif_1.RxDataBuff = &(rxDataBuff_1[0]); + + return ethernetif_init(netif, ðernetif_1, 1U, (ethernetif_config_t *)netif->state); +} +#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/fsl_enet.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/fsl_enet.c new file mode 100755 index 000000000..cd73be820 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/fsl_enet.c @@ -0,0 +1,3484 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_enet.c + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include "fsl_enet.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +#include "lwipopts.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enet" +#endif + +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U +/*! @brief Ethernet mac address length. */ +#define ENET_FRAME_MACLEN 6U +/*! @brief Ethernet VLAN header length. */ +#define ENET_FRAME_VLAN_TAGLEN 4U +/*! @brief MDC frequency. */ +#define ENET_MDC_FREQUENCY 2500000U +/*! @brief NanoSecond in one second. */ +#define ENET_NANOSECOND_ONE_SECOND 1000000000U +/*! @brief Define a common clock cycle delays used for time stamp capture. */ +#ifndef ENET_1588TIME_DELAY_COUNT +#define ENET_1588TIME_DELAY_COUNT 10U +#endif + +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/*! @brief Define the ENET ring/class bumber . */ +enum _enet_ring_number +{ + kENET_Ring0 = 0U, /*!< ENET ring/class 0. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + kENET_Ring1 = 1U, /*!< ENET ring/class 1. */ + kENET_Ring2 = 2U /*!< ENET ring/class 2. */ +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +}; + +/*! @brief Define interrupt IRQ handler. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET Mac configuration. + * @param bufferConfig ENET buffer configuration. + * @param macAddr ENET six-byte mac address. + * @param srcClock_Hz ENET module clock source, normally it's system clock. + */ +static void ENET_SetMacController(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Set ENET handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET configuration stucture pointer. + * @param bufferConfig ENET buffer configuration. + */ +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); +/*! + * @brief Set ENET MAC transmit buffer descriptors. + * + * @param handle The ENET handle pointer. + * @param config The ENET configuration structure. + * @param bufferConfig The ENET buffer configuration. + */ +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); + +/*! + * @brief Set ENET MAC receive buffer descriptors. + * + * @param handle The ENET handle pointer. + * @param config The ENET configuration structure. + * @param bufferConfig The ENET buffer configuration. + */ +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); + +/*! + * @brief Updates the ENET read buffer descriptors. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + */ +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief Activates ENET send for multiple tx rings. + * + * @param base ENET peripheral base address. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * this should be called when the ENET receive required. + */ +static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. + * + * @param data The ENET read data for frame parse. + * @param ptpTsData The ENET PTP message and time-stamp data pointer. + * @param isFastEnabled The fast parse flag. + * - true , Fast processing, only check if this is a PTP message. + * - false, Store the PTP message data after check the PTP message. + */ +static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); + +/*! + * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The new PTP 1588 time-stamp data pointer. + */ +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. + */ +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); + +/*! + * @brief Store the transmit time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + */ +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ptpTimeData The PTP 1588 time-stamp data pointer. + */ +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_AVB +/*! + * @brief Gets the ring index for transmission. + * + * @param base ENET peripheral base address. + * @param data The ENET transmit data. + * @param handle The ENET handle pointer. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * this should be called when the ENET receive required. + */ +static uint8_t ENET_GetTxRingId(ENET_Type *base, uint8_t *data, enet_handle_t *handle); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL}; + +/*! @brief Pointers to enet clocks for each instance. */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to enet transmit IRQ number for each instance. */ +static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS; +/*! @brief Pointers to enet receive IRQ number for each instance. */ +static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Pointers to enet timestamp IRQ number for each instance. */ +static const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! @brief Pointers to enet error IRQ number for each instance. */ +static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS; + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/* ENET ISR for transactional APIs. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +static enet_isr_ring_t s_enetTxIsr; +static enet_isr_ring_t s_enetRxIsr; +#else +static enet_isr_t s_enetTxIsr; +static enet_isr_t s_enetRxIsr; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +static enet_isr_t s_enetErrIsr; +static enet_isr_t s_enetTsIsr; +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_enetBases)); + + return instance; +} + +/*! + * brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + code + enet_config_t config; + ENET_GetDefaultConfig(&config); + endcode + * param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + assert(config); + + /* Initializes the MAC configure structure to zero. */ + memset(config, 0, sizeof(enet_config_t)); + +/* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + config->miiMode = kENET_RgmiiMode; +#else + config->miiMode = kENET_RmiiMode; +#endif + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + config->ringNum = 1; + + /* Sets the maximum receive frame length. */ + config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +} + +/*! + * brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * param srcClock_Hz The internal module clock source for MII clock. + * + * note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + /* Checks input parameters. */ + assert(handle); + assert(config); + assert(bufferConfig); + assert(macAddr); + assert(config->ringNum <= FSL_FEATURE_ENET_QUEUE); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ENET_GetInstance(base); + + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset ENET module. */ + ENET_Reset(base); + + /* Initializes the ENET transmit buffer descriptors. */ + ENET_SetTxBufferDescriptors(handle, config, bufferConfig); + + /* Initializes the ENET receive buffer descriptors. */ + ENET_SetRxBufferDescriptors(handle, config, bufferConfig); + + /* Initializes the ENET MAC controller with basic function. */ + ENET_SetMacController(base, handle, config, bufferConfig, macAddr, srcClock_Hz); + + /* Set all buffers or data in handler for data transmit/receive process. */ + ENET_SetHandler(base, handle, config, bufferConfig); +} + +/*! + * brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base) +{ + /* Disable interrupt. */ + base->EIMR = 0; + + /* Disable ENET. */ + base->ECR &= ~ENET_ECR_ETHEREN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disables the clock source. */ + CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * param handle ENET handler pointer. Should be provided by application. + * param callback The ENET callback function. + * param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) +{ + assert(handle); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; +} + +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + uint8_t count; + uint32_t instance = ENET_GetInstance(base); + const enet_buffer_config_t *buffCfg = bufferConfig; + + /* Store transfer parameters in handle pointer. */ + memset(handle, 0, sizeof(enet_handle_t)); + + handle->ringNum = (config->ringNum > FSL_FEATURE_ENET_QUEUE) ? FSL_FEATURE_ENET_QUEUE : config->ringNum; + for (count = 0; count < handle->ringNum; count++) + { + assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); + + handle->rxBdBase[count] = buffCfg->rxBdStartAddrAlign; + handle->rxBdCurrent[count] = buffCfg->rxBdStartAddrAlign; + handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; + handle->txBdBase[count] = buffCfg->txBdStartAddrAlign; + handle->txBdCurrent[count] = buffCfg->txBdStartAddrAlign; + handle->txBuffSizeAlign[count] = buffCfg->txBuffSizeAlign; + + buffCfg++; + } + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[instance] = handle; + + /* Set the IRQ handler when the interrupt is enabled. */ + if (config->interrupt & ENET_TX_INTERRUPT) + { + s_enetTxIsr = ENET_TransmitIRQHandler; + EnableIRQ(s_enetTxIrqId[instance]); + } + if (config->interrupt & ENET_RX_INTERRUPT) + { + s_enetRxIsr = ENET_ReceiveIRQHandler; + EnableIRQ(s_enetRxIrqId[instance]); + } + if (config->interrupt & ENET_ERR_INTERRUPT) + { + s_enetErrIsr = ENET_ErrorIRQHandler; + EnableIRQ(s_enetErrIrqId[instance]); + } +} + +static void ENET_SetMacController(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + /* Check the MII mode/speed/duplex setting. */ + if (config->miiSpeed == kENET_MiiSpeed1000M) + { + /* Only RGMII mode has the 1000M bit/s. The 1000M only support full duplex. */ + assert(config->miiMode == kENET_RgmiiMode); + assert(config->miiDuplex == kENET_MiiFullDuplex); + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + uint32_t rcr = 0; + uint32_t tcr = 0; + uint32_t ecr = base->ECR; + uint32_t macSpecialConfig = config->macSpecialConfig; + uint32_t maxFrameLen = config->rxMaxFrameLen; + + /* Maximum frame length check. */ + if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN)) + { + maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN); +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (macSpecialConfig & kENET_ControlSVLANEnable) + { + /* Double vlan tag (SVLAN) supported. */ + maxFrameLen += ENET_FRAME_VLAN_TAGLEN; + } + ecr |= ((macSpecialConfig & kENET_ControlSVLANEnable) ? (ENET_ECR_SVLANEN_MASK | ENET_ECR_SVLANDBL_MASK) : 0) | + ((macSpecialConfig & kENET_ControlVLANUseSecondTag) ? ENET_ECR_VLANUSE2ND_MASK : 0); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + } + + /* Configures MAC receive controller with user configure structure. */ + rcr = ((macSpecialConfig & kENET_ControlRxPayloadCheckEnable) ? ENET_RCR_NLC_MASK : 0) | + ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_CFEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_FCE_MASK : 0) | + ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | + ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; + +/* Set the RGMII or RMII, MII mode and control register. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (config->miiMode == kENET_RgmiiMode) + { + rcr |= ENET_RCR_RGMII_EN_MASK; + rcr &= ~ENET_RCR_MII_MODE_MASK; + } + else + { + rcr &= ~ENET_RCR_RGMII_EN_MASK; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + rcr |= ENET_RCR_MII_MODE_MASK; + if (config->miiMode == kENET_RmiiMode) + { + rcr |= ENET_RCR_RMII_MODE_MASK; + } +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + /* Speed. */ + if (config->miiSpeed == kENET_MiiSpeed10M) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (config->miiSpeed == kENET_MiiSpeed1000M) + { + ecr |= ENET_ECR_SPEED_MASK; + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Receive setting for half duplex. */ + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + } + /* Sets internal loop only for MII mode. */ + if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode != kENET_RmiiMode)) + { + rcr |= ENET_RCR_LOOP_MASK; + rcr &= ~ENET_RCR_DRT_MASK; + } + base->RCR = rcr; + + /* Configures MAC transmit controller: duplex mode, mac address insertion. */ + tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); + tcr |= (config->miiDuplex ? ENET_TCR_FDEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlMacAddrInsert) ? ENET_TCR_ADDINS_MASK : 0); + base->TCR = tcr; + + /* Configures receive and transmit accelerator. */ + base->TACC = config->txAccelerConfig; + base->RACC = config->rxAccelerConfig; + + /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ + if (macSpecialConfig & kENET_ControlFlowControlEnable) + { + uint32_t reemReg; + base->OPD = config->pauseDuration; + reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); +#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + base->RSEM = reemReg; + } + + /* FIFO threshold setting for store and forward enable/disable case. */ + if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) + { + /* Transmit fifo watermark settings. */ + base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; + /* Receive fifo full threshold settings. */ + base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; + } + else + { + /* Transmit fifo watermark settings. */ + base->TFWR = ENET_TFWR_STRFWD_MASK; + base->RSFL = 0; + } + + /* Enable store and forward when accelerator is enabled */ + if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) + { + base->TFWR = ENET_TFWR_STRFWD_MASK; + } + if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) + { + base->RSFL = 0; + } + +/* Initializes the ring 0. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; + base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; +#endif + base->MRBR = bufferConfig->rxBuffSizeAlign; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + const enet_buffer_config_t *buffCfg = bufferConfig; + + if (config->ringNum > 1) + { + /* Initializes the ring 1. */ + buffCfg++; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; + base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; +#endif + base->MRBR1 = buffCfg->rxBuffSizeAlign; + /* Enable the DMAC for ring 1 and with no rx classification set. */ + base->DMACFG[0] = ENET_DMACFG_DMA_CLASS_EN_MASK; + } + if (config->ringNum > 2) + { + /* Initializes the ring 2. */ + buffCfg++; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR2 = (uint32_t)buffCfg->txBdStartAddrAlign; + base->RDSR2 = (uint32_t)buffCfg->rxBdStartAddrAlign; +#endif + base->MRBR2 = buffCfg->rxBuffSizeAlign; + /* Enable the DMAC for ring 2 and with no rx classification set. */ + base->DMACFG[1] = ENET_DMACFG_DMA_CLASS_EN_MASK; + } + + /* Default the class/ring 1 and 2 are not enabled and the receive classification is disabled + * so we set the default transmit scheme with the round-robin mode. beacuse the legacy bd mode + * only support the round-robin mode. if the avb feature is required, just call the setup avb + * feature API. */ + base->QOS |= ENET_QOS_TX_SCHEME(1); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Configures the Mac address. */ + ENET_SetMacAddr(base, macAddr); + + /* Initialize the SMI if uninitialized. */ + if (!ENET_GetSMI(base)) + { + ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); + } + +/* Enables Ethernet interrupt, enables the interrupt coalsecing if it is required. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + if (config->intCoalesceCfg) + { + uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK); + +#if FSL_FEATURE_ENET_QUEUE > 1 + uint8_t queue = 0; + intMask |= ENET_EIMR_TXB2_MASK | ENET_EIMR_RXB2_MASK | ENET_EIMR_TXB1_MASK | ENET_EIMR_RXB1_MASK; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + /* Clear all buffer interrupts. */ + base->EIMR &= ~intMask; + +/* Set the interrupt coalescence. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + for (queue = 0; queue < FSL_FEATURE_ENET_QUEUE; queue++) + { + base->TXIC[queue] = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[queue]) | + config->intCoalesceCfg->txCoalesceTimeCount[queue] | ENET_TXIC_ICCS_MASK | + ENET_TXIC_ICEN_MASK; + base->RXIC[queue] = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[queue]) | + config->intCoalesceCfg->rxCoalesceTimeCount[queue] | ENET_RXIC_ICCS_MASK | + ENET_RXIC_ICEN_MASK; + } +#else + base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) | + config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK; + base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) | + config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + ENET_EnableInterrupts(base, config->interrupt); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Sets the 1588 enhanced feature. */ + ecr |= ENET_ECR_EN1588_MASK; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Enables Ethernet module after all configuration except the buffer descriptor active. */ + ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; + base->ECR = ecr; +} + +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + /* Default single ring is supported. */ + uint8_t ringNum; + uint32_t count; + uint32_t txBuffSizeAlign; + uint8_t *txBuffer; + const enet_buffer_config_t *buffCfg = bufferConfig; + + /* Check the input parameters. */ + for (ringNum = 0; ringNum < config->ringNum; ringNum++) + { + if ((buffCfg->txBdStartAddrAlign > 0) && (buffCfg->txBufferAlign > 0)) + { + volatile enet_tx_bd_struct_t *curBuffDescrip = buffCfg->txBdStartAddrAlign; + txBuffSizeAlign = buffCfg->txBuffSizeAlign; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + txBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBufferAlign, kMEMORY_Local2DMA); +#else + txBuffer = buffCfg->txBufferAlign; +#endif + for (count = 0; count < buffCfg->txBdNumber; count++) + { + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffer[count * txBuffSizeAlign]); + /* Initializes data length. */ + curBuffDescrip->length = 0; + /* Sets the crc. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == buffCfg->txBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Enable transmit interrupt for store the transmit timestamp. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK; +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + /* Set the type of the frame when the credit-based scheme is used. */ + curBuffDescrip->controlExtend1 |= ENET_BD_FTYPE(ringNum); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } + } + buffCfg++; + } +} + +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + /* Default single ring is supported. */ + uint8_t ringNum; + uint32_t count; + uint32_t rxBuffSizeAlign; + uint8_t *rxBuffer; + const enet_buffer_config_t *buffCfg = bufferConfig; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t mask = (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Check the input parameters. */ + for (ringNum = 0; ringNum < config->ringNum; ringNum++) + { + assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#if FSL_FEATURE_ENET_QUEUE > 1 + if (ringNum == 1) + { + mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); + } + else if (ringNum == 2) + { + mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); + } +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + if ((buffCfg->rxBdStartAddrAlign > 0) && (buffCfg->rxBufferAlign > 0)) + { + volatile enet_rx_bd_struct_t *curBuffDescrip = buffCfg->rxBdStartAddrAlign; + rxBuffSizeAlign = buffCfg->rxBuffSizeAlign; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + rxBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBufferAlign, kMEMORY_Local2DMA); +#else + rxBuffer = buffCfg->rxBufferAlign; +#endif + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Invalidate rx buffers before DMA transfer data into them. */ + DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + + for (count = 0; count < buffCfg->rxBdNumber; count++) + { + /* Set data buffer and the length. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffer[count * rxBuffSizeAlign]); + curBuffDescrip->length = 0; + + /* Initializes the buffer descriptors with empty bit. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == buffCfg->rxBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (config->interrupt & mask) + { + /* Enable receive interrupt. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK; + } + else + { + curBuffDescrip->controlExtend1 = 0; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } + } + buffCfg++; + } +} + +static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId) +{ + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Ensure previous data update is completed with Data Synchronization Barrier before activing Tx BD. */ + __DSB(); + + switch (ringId) + { + case kENET_Ring0: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->TDAR1 = ENET_TDAR1_TDAR_MASK; + break; + case kENET_Ring2: + base->TDAR2 = ENET_TDAR2_TDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; + } +} + +/*! + * brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * param base ENET peripheral base address. + * param speed The speed of the RMII mode. + * param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t rcr = base->RCR; + uint32_t tcr = base->TCR; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + uint32_t ecr = base->ECR; + + if (kENET_MiiSpeed1000M == speed) + { + assert(duplex == kENET_MiiFullDuplex); + ecr |= ENET_ECR_SPEED_MASK; + } + else + { + ecr &= ~ENET_ECR_SPEED_MASK; + } + + base->ECR = ecr; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Sets speed mode. */ + if (kENET_MiiSpeed10M == speed) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } + else + { + rcr &= ~ENET_RCR_RMII_10T_MASK; + } + /* Set duplex mode. */ + if (duplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + tcr &= ~ENET_TCR_FDEN_MASK; + } + else + { + rcr &= ~ENET_RCR_DRT_MASK; + tcr |= ENET_TCR_FDEN_MASK; + } + + base->RCR = rcr; + base->TCR = tcr; +} + +/*! + * brief Sets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + uint32_t address; + + /* Set physical address lower register. */ + address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | + (uint32_t)macAddr[3]); + base->PALR = address; + /* Set physical address high register. */ + address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); + base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; +} + +/*! + * brief Gets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + assert(macAddr); + + uint32_t address; + + /* Get from physical address lower register. */ + address = base->PALR; + macAddr[0] = 0xFFU & (address >> 24U); + macAddr[1] = 0xFFU & (address >> 16U); + macAddr[2] = 0xFFU & (address >> 8U); + macAddr[3] = 0xFFU & address; + + /* Get from physical address high register. */ + address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; +} + +/*! + * brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * param base ENET peripheral base address. + * param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) +{ + assert(srcClock_Hz); + + uint32_t clkCycle = 0; + uint32_t speed = 0; + uint32_t mscr = 0; + + /* Calculate the MII speed which controls the frequency of the MDC. */ + speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); + /* Calculate the hold time on the MDIO output. */ + clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; + /* Build the configuration for MDC/MDIO control. */ + mscr = + ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); + base->MSCR = mscr; +} + +/*! + * brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The write operation. + * param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | + (data & 0xFFFF); + base->MMFR = mmfr; +} + +/*! + * brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) +{ + uint32_t mmfr = 0; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); + base->MMFR = mmfr; +} + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); + base->MMFR = mmfr; +} + +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2); + base->MMFR = mmfr; +} +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! + * brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * endcode + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + assert(eErrorStatic); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[0]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[0]); +} + +/*! + * brief Gets the size of the read frame for single ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". + * + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param length The length of the valid frame received. + * retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. + * retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data + * and NULL length to update the receive buffers. + * retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + assert(length); + + /* Reset the length to zero. */ + *length = 0; + + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Add check for abnormal case. */ + if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) + { + return kStatus_ENET_RxFrameError; + } + + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[0]; + } + else + { + curBuffDescrip++; + } + } while (curBuffDescrip != handle->rxBdCurrent[0]); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +/*! + * brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * endcode + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + + uint32_t len = 0; + uint32_t offset = 0; + uint16_t control; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + status_t result = kStatus_Success; + uint32_t address; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Update the control flag. */ + control = handle->rxBdCurrent[0]->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + break; + } + + } while (handle->rxBdCurrent[0] != curBuffDescrip); + + return result; + } + else + { + +/* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, (void *)address, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + return result; + } + else + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + } + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + break; + } + + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]); + offset += handle->rxBuffSizeAlign[0]; + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + } + + /* Get the current buffer descriptor. */ + curBuffDescrip = handle->rxBdCurrent[0]; + +/* Add the cache invalidate maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + } + } + + return kStatus_ENET_RxFrameFail; +} + +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +{ + assert(handle); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + +// lw_print("lw: [%s] base %p handle %p ring %d\n", __func__, base, handle, ringId); + + /* Clears status. */ + handle->rxBdCurrent[ringId]->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + /* Sets the receive buffer descriptor with the empty flag. */ + handle->rxBdCurrent[ringId]->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + + /* Increase current buffer descriptor to the next one. */ + if (handle->rxBdCurrent[ringId]->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent[ringId] = handle->rxBdBase[ringId]; + } + else + { + handle->rxBdCurrent[ringId]++; + } + + /* Ensure previous data update is completed with Data Synchronization Barrier before activing Rx BD. */ + __DSB(); + + /* Actives the receive buffer descriptor. */ + switch (ringId) + { + case kENET_Ring0: + base->RDAR = ENET_RDAR_RDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->RDAR1 = ENET_RDAR1_RDAR_MASK; + break; + case kENET_Ring2: + base->RDAR2 = ENET_RDAR2_RDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->RDAR = ENET_RDAR_RDAR_MASK; + break; + } +} + +/*! + * brief Transmits an ENET frame for single ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) +{ + assert(handle); + assert(data); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[0]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +// lw_print("lw: [%s] size %d len %d\n", __func__, handle->txBuffSizeAlign[0], length); + + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[0] >= length) + { +/* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (sizeleft > handle->txBuffSizeAlign[0]) + { + /* Data copy. */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[0]; + len += handle->txBuffSizeAlign[0]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + /* Active the transmit buffer descriptor*/ + ENET_ActiveSend(base, 0); + } + else + { + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[0]; + + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ +void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) +{ + assert(handle); + assert(eErrorStatic); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[ringId]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[ringId]); +} + +/*! + * brief Gets the size of the read frame for extended mutli-ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is + * the same to the single ring, refer to ENET_GetRxFrameSize. + * + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param length The length of the valid frame received. + * param ringId The ring index or ring number; + * retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. + * retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data + * and NULL length to update the receive buffers. + * retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId) +{ + assert(handle); + assert(length); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Reset the length to zero. */ + *length = 0; + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip; + + curBuffDescrip = handle->rxBdCurrent[ringId]; + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Add check for abnormal case. */ + if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) + { + return kStatus_ENET_RxFrameError; + } + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[ringId]; + } + else + { + curBuffDescrip++; + } + } while (curBuffDescrip != handle->rxBdCurrent[ringId]); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +/*! + * brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * param ringId The ring index or ring number; + * return The execute status, successful or failure. + */ +status_t ENET_ReadFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) +{ + assert(handle); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint32_t len = 0; + uint32_t offset = 0; + uint16_t control; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; + status_t result = kStatus_Success; + uint32_t address; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Update the control flag. */ + control = handle->rxBdCurrent[ringId]->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + break; + } + + } while (handle->rxBdCurrent[ringId] != curBuffDescrip); + + return result; + } + else + { +/* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, (void *)address, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + return result; + } + else + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + } + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + break; + } + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); + offset += handle->rxBuffSizeAlign[ringId]; + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + } + + /* Get the current buffer descriptor. */ + + curBuffDescrip = handle->rxBdCurrent[ringId]; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + } + } + + return kStatus_ENET_RxFrameFail; +} + +/*! + * brief Transmits an ENET frame for extended multi-ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * param ringId The ring index for transmission. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) +{ + assert(handle); + assert(data); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[ringId]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[ringId] >= length) + { +/* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data, length); + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdCurrent[ringId]++; + } + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, ringId); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdCurrent[ringId]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (sizeleft > handle->txBuffSizeAlign[ringId]) + { + /* Data copy. */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[ringId]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[ringId]; + len += handle->txBuffSizeAlign[ringId]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + + /* Active the transmit buffer descriptor*/ + ENET_ActiveSend(base, ringId); + } + else + { + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, ringId); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[ringId]; + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * brief Adds the ENET device to a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Enable a multicast group address. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } + else + { + base->GAUR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } +} + +/*! + * brief Moves the ENET device from a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Set the hash table. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } + else + { + base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(eErrorStatic); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic[0]->control; + controlExt = handle->txBdDirtyStatic[0]->controlExtend0; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic[0]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic[0] = handle->txBdBase[0]; + } + else + { + handle->txBdDirtyStatic[0]++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic[0] != handle->txBdCurrent[0]); + + return kStatus_ENET_TxFrameFail; +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index. + * return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) +{ + assert(handle); + assert(eErrorStatic); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic[ringId]->control; + controlExt = handle->txBdDirtyStatic[ringId]->controlExtend0; + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyStatic[ringId]++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic[ringId] != handle->txBdCurrent[ringId]); + + return kStatus_ENET_TxFrameFail; +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) +{ + assert(data); + if (!isFastEnabled) + { + assert(ptpTsData); + } + + bool isPtpMsg = false; + const uint8_t *buffer = data; + uint16_t ptpType; + + /* Check for VLAN frame. + * Add Double vlan tag check for receiving extended QIN vlan frame. */ + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == (ENET_HTONS(ENET_8021QVLAN) +#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB + || ENET_HTONS(ENET_8021QSVLAN) +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + )) + { + buffer += ENET_FRAME_VLAN_TAGLEN; +#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) + { + buffer += ENET_FRAME_VLAN_TAGLEN; + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + } + + ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); + switch (ENET_HTONS(ptpType)) + { /* Ethernet layer 2. */ + case ENET_ETHERNETL2: + if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType) + { + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a ptpv2 message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), + kENET_PtpSrcPortIdLen); + } + } + break; + /* IPV4. */ + case ENET_IPV4: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV4 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + /* IPV6. */ + case ENET_IPV6: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV6 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + default: + break; + } + return isPtpMsg; +} + +/*! + * brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) +{ + assert(handle); + assert(ptpConfig); + uint8_t count; + + uint32_t instance = ENET_GetInstance(base); + uint32_t mask = kENET_TxBufferInterrupt; +#if FSL_FEATURE_ENET_QUEUE > 1 + mask |= kENET_TxBuffer1Interrupt | kENET_TxBuffer2Interrupt; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + /* Start the 1588 timer. */ + ENET_Ptp1588StartTimer(base, ptpConfig->ptp1588ClockSrc_Hz); + + for (count = 0; count < handle->ringNum; count++) + { + handle->txBdDirtyTime[count] = handle->txBdBase[count]; + handle->txBdDirtyStatic[count] = handle->txBdBase[count]; + } + + /* Setting the receive and transmit state for transaction. */ + handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData; + handle->rxPtpTsDataRing.size = ptpConfig->ptpTsRxBuffNum; + handle->rxPtpTsDataRing.front = 0; + handle->rxPtpTsDataRing.end = 0; + handle->txPtpTsDataRing.ptpTsData = ptpConfig->txPtpTsData; + handle->txPtpTsDataRing.size = ptpConfig->ptpTsTxBuffNum; + handle->txPtpTsDataRing.front = 0; + handle->txPtpTsDataRing.end = 0; + handle->msTimerSecond = 0; + + /* Set the IRQ handler when the interrupt is enabled. */ + s_enetTxIsr = ENET_TransmitIRQHandler; + s_enetTsIsr = ENET_Ptp1588TimerIRQHandler; + + /* Enables the time stamp interrupt and transmit frame interrupt to + * handle the time-stamp . */ + ENET_EnableInterrupts(base, (ENET_TS_INTERRUPT | ENET_TX_INTERRUPT)); + ENET_DisableInterrupts(base, mask); + + EnableIRQ(s_enetTsIrqId[instance]); + EnableIRQ(s_enetTxIrqId[instance]); +} + +/*! + * brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * param base ENET peripheral base address. + * param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) +{ + /* Restart PTP 1588 timer, master clock. */ + base->ATCR = ENET_ATCR_RESTART_MASK; + + /* Initializes PTP 1588 timer. */ + base->ATINC = ENET_ATINC_INC(ENET_NANOSECOND_ONE_SECOND / ptpClkSrc); + base->ATPER = ENET_NANOSECOND_ONE_SECOND; + /* Sets periodical event and the event signal output assertion and Actives PTP 1588 timer. */ + base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; +} + +/*! + * brief Gets the current ENET time from the PTP 1588 timer. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + uint16_t count = ENET_1588TIME_DELAY_COUNT; + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get the current PTP time. */ + ptpTime->second = handle->msTimerSecond; + /* Get the nanosecond from the master timer. */ + base->ATCR |= ENET_ATCR_CAPTURE_MASK; + /* Add at least six clock cycle delay to get accurate time. + It's the requirement when the 1588 clock source is slower + than the register clock. + */ + while (count--) + { + __NOP(); + } + /* Get the captured time. */ + ptpTime->nanosecond = base->ATVR; + + /* Get PTP timer wrap event. */ + if (base->EIR & kENET_TsTimerInterrupt) + { + ptpTime->second++; + } + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +/*! + * brief Sets the ENET PTP 1588 timer to the assigned time. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Sets PTP timer. */ + handle->msTimerSecond = ptpTime->second; + base->ATVR = ptpTime->nanosecond; + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +/*! + * brief Adjusts the ENET PTP 1588 timer. + * + * param base ENET peripheral base address. + * param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) +{ + /* Set correction for PTP timer increment. */ + base->ATINC = (base->ATINC & ~ENET_ATINC_INC_CORR_MASK) | (corrIncrease << ENET_ATINC_INC_CORR_SHIFT); + /* Set correction for PTP timer period. */ + base->ATCOR = (base->ATCOR & ~ENET_ATCOR_COR_MASK) | (corrPeriod << ENET_ATCOR_COR_SHIFT); +} + +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimeData); + + uint16_t usedBuffer = 0; + + /* Check if the buffers ring is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == (ptpTsDataRing->size - 1)) + { + /* Ptp timestamp ring full, drop one in the front. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % ptpTsDataRing->size; + } + + /* Copy the new data into the buffer. */ + memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); + + /* Increase the buffer pointer to the next empty one. */ + ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; + + return kStatus_Success; +} + +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimedata); + + uint32_t index; + uint32_t size; + uint16_t usedBuffer = 0; + bool isRingBufferFull = false; + + /* Check the PTP 1588 timestamp ring. */ + if (ptpTsDataRing->front == ptpTsDataRing->end) + { + return kStatus_ENET_PtpTsRingEmpty; + } + + /* Check if buffers is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == (ptpTsDataRing->size-1)) + { + isRingBufferFull = true; + } + + /* Search the element in the ring buffer */ + index = ptpTsDataRing->front; + size = ptpTsDataRing->size; + while (index != ptpTsDataRing->end) + { + if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && + (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && + ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && + ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) + { + break; + } + + /* Increase the ptp ring index. */ + index = (index + 1) % size; + } + + if (index == ptpTsDataRing->end) + { + if (isRingBufferFull == true) + { + /* PTP timestamp buffer ring full, data in index ptpTsDataRing->end is valid. */ + if (((ptpTsDataRing->ptpTsData + index)->sequenceId != ptpTimedata->sequenceId) || + (memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) || + ((ptpTsDataRing->ptpTsData + index)->version != ptpTimedata->version) || + ((ptpTsDataRing->ptpTsData + index)->messageType != ptpTimedata->messageType)) + { + return kStatus_ENET_PtpTsRingFull; + } + } + else + { + return kStatus_ENET_PtpTsRingFull; + } + } + + /* Get the right timestamp of the required ptp messag. */ + ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; + ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; + + if( isRingBufferFull == true) + { + /* If ring buffer full, move front pointer to next pointer behind end pointer, then next + read will still read whole ring. */ + ptpTsDataRing->end = index; + } + + /* Drop previous ptp stamp. */ + ptpTsDataRing->front = (index + 1) % size; + + return kStatus_Success; +} + +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + enet_ptp_time_t ptpTimer; + + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimer); + + /* Get transmit time stamp second. */ + if (ptpTimer.nanosecond >= ptpTimeData->timeStamp.nanosecond) + { + ptpTimeData->timeStamp.second = ptpTimer.second; + } + else + { + ptpTimeData->timeStamp.second = ptpTimer.second - 1; + } + + /* Store the timestamp to the receive time stamp ring. */ + /* Check if the buffers ring is full. */ + return ENET_Ptp1588UpdateTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +{ + assert(handle); + + bool isPtpEventMessage = false; + enet_ptp_time_data_t ptpTimeData; + volatile enet_tx_bd_struct_t *curBuffDescrip; + volatile enet_tx_bd_struct_t *endBuffDescrip; + uint32_t address; + bool isReadLastBd = false; + bool readLastBd = false; + + /* Treat the txBdCurrent[ringId] as the tx bd write buffer pointer, + txBdDirtyTime[ringId] as the tx bd read buffer pointer. Considering + that the tx frame time read is driven by tx frame send, so the read + pointer txBdDirtyTime[ringId] should always behind write pointer + txBdDirtyTime[ringId]. Then if the read pointer equals write pointer, + we could treat the tx bd buffer is full. We could read out all + available bds. */ + if(handle->txBdDirtyTime[ringId] == handle->txBdCurrent[ringId]) + { + isReadLastBd = true; + if(handle->txBdDirtyTime[ringId] == handle->txBdBase[ringId]) + { + endBuffDescrip = handle->txBdDirtyTime[ringId] + 3; + } + else + { + endBuffDescrip = handle->txBdDirtyTime[ringId] - 1; + } + } + else + { + endBuffDescrip = handle->txBdCurrent[ringId]; + } + + /* Read tx bd buffer until read pointer txBdDirtyTime[ringId] equals to the end pointer of + tx bd buffer. */ + while((handle->txBdDirtyTime[ringId] != endBuffDescrip) || (readLastBd == true)) + { + curBuffDescrip = handle->txBdDirtyTime[ringId]; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + + /* Parse the PTP message. */ + #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); + #else + address = (uint32_t)curBuffDescrip->buffer; + #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); + if (isPtpEventMessage) + { + /* Only store tx timestamp for ptp event message. */ + /* Increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + + /* Do time stamp check on the last buffer descriptor of the frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimeData.timeStamp); + + /* Get transmit time stamp second. */ + if (ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp) + { + ptpTimeData.timeStamp.second--; + } + + /* Save transmit time stamp nanosecond. */ + ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp; + + /* Store the timestamp to the transmit timestamp ring. */ + ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData); + } + } + else + { + /* Only increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + } + + if(readLastBd == true) + { + break; + } + + /* If if read pointer equals write pointer, the end pointer is set at the pointer before + current write pointer and the buffer in the end pointer is available, so read last bd at + the end pointer. */ + if((isReadLastBd == true) && (handle->txBdDirtyTime[ringId] == endBuffDescrip)) + { + readLastBd = true; + } + } + return kStatus_Success; +} + +/*! + * brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); +} + +/*! + * brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config The ENET AVB feature configuration structure. + */ +void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config) +{ + assert(config); + + uint8_t count = 0; + + for (count = 0; count < FSL_FEATURE_ENET_QUEUE - 1; count++) + { + /* Set the AVB receive ring classification match when the match is not 0. */ + if (config->rxClassifyMatch[count]) + { + base->RCMR[count] = (config->rxClassifyMatch[count] & 0xFFFF) | ENET_RCMR_MATCHEN_MASK; + } + /* Set the dma controller for the extended ring. */ + base->DMACFG[count] |= ENET_DMACFG_IDLE_SLOPE(config->idleSlope[count]); + } + + /* Shall use the credit-based scheme for avb. */ + base->QOS &= ~ENET_QOS_TX_SCHEME_MASK; + base->QOS |= ENET_QOS_RX_FLUSH0_MASK; +} +#endif /* FSL_FETAURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +#else +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +{ + assert(handle); + uint32_t mask = kENET_TxBufferInterrupt | kENET_TxFrameInterrupt; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) || (FSL_FEATURE_ENET_QUEUE > 1) + uint32_t index = 0; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTORMODE || (FSL_FEATURE_ENET_QUEUE > 1) */ + +/* Check if the transmit interrupt happen. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + switch (ringId) + { + case kENET_Ring1: + mask = (kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt); + break; + case kENET_Ring2: + mask = (kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt); + break; + default: + break; + } + index = ringId; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + while (mask & base->EIR) + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (base->EIR & kENET_TxFrameInterrupt) + { + /* Store the transmit timestamp from the buffer descriptor should be done here. */ + ENET_StoreTxFrameTime(base, handle, index); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Clear the transmit interrupt event. */ + base->EIR = mask; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, index, kENET_TxEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TxEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +#else +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +{ + assert(handle); + uint32_t mask = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt; + +/* Check if the receive interrupt happen. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + switch (ringId) + { + case kENET_Ring1: + mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); + break; + case kENET_Ring2: + mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); + break; + default: + break; + } +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + while (mask & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = mask; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, ringId, kENET_RxEvent, handle->userData); +#else + handle->callback(base, handle, kENET_RxEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +} + +/*! + * brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; + + /* Check if the error interrupt happen. */ + if (kENET_WakeupInterrupt & base->EIR) + { + /* Clear the wakeup interrupt. */ + base->EIR = kENET_WakeupInterrupt; + /* wake up and enter the normal mode. */ + ENET_EnableSleepMode(base, false); + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_WakeUpEvent, handle->userData); +#else + handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + else + { + /* Clear the error interrupt event status. */ + errMask &= base->EIR; + base->EIR = errMask; + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_ErrEvent, handle->userData); +#else + handle->callback(base, handle, kENET_ErrEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief The IEEE 1588 PTP time stamp interrupt handler. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + /* Check if the PTP time stamp interrupt happen. */ + if (kENET_TsTimerInterrupt & base->EIR) + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsTimerInterrupt; + + /* Increase timer second counter. */ + handle->msTimerSecond++; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_TimeStampEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TimeStampEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + else + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsAvailInterrupt; + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_TimeStampAvailEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TimeStampAvailEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBufferInterrupt | kENET_TxFrameInterrupt)) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + s_enetTxIsr(base, s_ENETHandle[instance], 0); +#else + s_enetTxIsr(base, s_ENETHandle[instance]); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + + if (event & (kENET_RxBufferInterrupt | kENET_RxFrameInterrupt)) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + s_enetRxIsr(base, s_ENETHandle[instance], 0); +#else + s_enetRxIsr(base, s_ENETHandle[instance]); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + + if (event & ENET_TS_INTERRUPT) + { + s_enetTsIsr(base, s_ENETHandle[instance]); + } + if (event & ENET_ERR_INTERRUPT) + { + s_enetErrIsr(base, s_ENETHandle[instance]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * param base ENET peripheral base address. + */ +void ENET_CommonFrame1IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBuffer1Interrupt | kENET_TxFrame1Interrupt)) + { + s_enetTxIsr(base, s_ENETHandle[instance], 1); + } + + if (event & (kENET_RxBuffer1Interrupt | kENET_RxFrame1Interrupt)) + { + s_enetRxIsr(base, s_ENETHandle[instance], 1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * param base ENET peripheral base address. + */ +void ENET_CommonFrame2IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBuffer2Interrupt | kENET_TxFrame2Interrupt)) + { + s_enetTxIsr(base, s_ENETHandle[instance], 2); + } + + if (event & (kENET_RxBuffer2Interrupt | kENET_RxFrame2Interrupt)) + { + s_enetRxIsr(base, s_ENETHandle[instance], 2); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +#if defined(ENET) +void ENET_Transmit_IRQHandler(void) +{ + s_enetTxIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_Receive_IRQHandler(void) +{ + s_enetRxIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_Error_IRQHandler(void) +{ + s_enetErrIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_1588_Timer_IRQHandler(void) +{ + s_enetTsIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +//void ENET_DriverIRQHandler(void) +void ENET_DriverIRQHandler(int vector, void *param) +{ + ENET_CommonFrame0IRQHandler(ENET); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +DECLARE_HW_IRQ(ENET_IRQn, ENET_DriverIRQHandler, NONE); + +#endif + +#if defined(ENET1) +void ENET1_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ENET2) +void ENET2_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CONNECTIVITY__ENET0) +void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#if FSL_FEATURE_ENET_QUEUE > 1 +void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#if defined(CONNECTIVITY__ENET1) +void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#if FSL_FEATURE_ENET_QUEUE > 1 +void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/Makefile new file mode 100755 index 000000000..b6d80e5ea --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/Makefile @@ -0,0 +1,2 @@ +SRC_FILES := fsl_phy.c +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c new file mode 100644 index 000000000..1017aa038 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c @@ -0,0 +1,324 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_phy.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x3FFFFFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) +{ + uint32_t bssReg; + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; + uint32_t instance = ENET_GetInstance(base); + uint32_t timeDelay; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI(base, srcClock_Hz, false); + + /* Initialization after PHY stars to work. */ + while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) + { + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + counter --; + } + + if (!counter) + { + return kStatus_Fail; + } + + /* Reset PHY. */ + counter = PHY_TIMEOUT_COUNT; + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { + + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter --) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { + if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) + { + /* Wait a moment for Phy status stable. */ + for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) + { + __ASM("nop"); + } + break; + } + } + + if (!counter) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + } + + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + assert(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + if (speed == kPHY_Speed100M) + { + data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data | PHY_CTL1_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + data &= ~PHY_BCTL_LOOP_MASK; + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data & ~PHY_CTL1_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + assert(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); + if (result == kStatus_Success) + { + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = kPHY_FullDuplex; + } + else + { + /* Half duplex. */ + *duplex = kPHY_HalfDuplex; + } + + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = kPHY_Speed100M; + } + else + { /* 10M speed. */ + *speed = kPHY_Speed10M; + } + } + + return result; +} diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h new file mode 100644 index 000000000..3e2a93cb1 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h @@ -0,0 +1,225 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1FU /*!< The PHY control one register. */ + +#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ +#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL1_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +//#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the PHY status. */ +enum _phy_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c index a61d7d035..ddf1ed881 100755 --- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c @@ -78,6 +78,7 @@ const struct PinMask pin_mask[] = struct PinIrqHdr pin_irq_hdr_tab[] = { /* GPIO1 */ + {-1, 0, NONE, NONE},//1 {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, @@ -108,9 +109,9 @@ struct PinIrqHdr pin_irq_hdr_tab[] = {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//32 /* GPIO2 */ + {-1, 0, NONE, NONE},//33 {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, @@ -141,9 +142,9 @@ struct PinIrqHdr pin_irq_hdr_tab[] = {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//64 /* GPIO3 */ + {-1, 0, NONE, NONE},//65 {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, @@ -174,8 +175,7 @@ struct PinIrqHdr pin_irq_hdr_tab[] = {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//96 /* GPIO4 */ {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, @@ -208,11 +208,25 @@ struct PinIrqHdr pin_irq_hdr_tab[] = {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, + {-1, 0, NONE, NONE},//128 /* GPIO5 */ + {-1, 0, NONE, NONE},//129 {-1, 0, NONE, NONE}, {-1, 0, NONE, NONE}, - {-1, 0, NONE, NONE}, +}; + +#define MUX_BASE 0x401f8014 +#define CONFIG_BASE 0x401f8204 + +#define GPIO5_MUX_BASE 0x400A8000 +#define GPIO5_CONFIG_BASE 0x400A8018 + +const uint8_t reg_offset[] = +{ + 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105, + 112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, }; static int GetPin(struct PinIndex *pin_index, uint8_t pin) @@ -229,39 +243,52 @@ static int GetPin(struct PinIndex *pin_index, uint8_t pin) return 0; } -static int32 GpioConfigMode(int mode, struct PinIndex *index) +static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin) { gpio_pin_config_t gpio_config; - NULL_PARAM_CHECK(index); + uint32_t config_value = 0; + NULL_PARAM_CHECK(pin_index); gpio_config.outputLogic = 0; + gpio_config.interruptMode = kGPIO_NoIntmode; switch (mode) { case GPIO_CFG_OUTPUT: gpio_config.direction = kGPIO_DigitalOutput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x0030U; /* Drive Strength R0/6 */ break; case GPIO_CFG_INPUT: gpio_config.direction = kGPIO_DigitalInput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x0830U; /* Open Drain Enable */ break; case GPIO_CFG_INPUT_PULLUP: gpio_config.direction = kGPIO_DigitalInput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0xB030U; /* 100K Ohm Pull Up */ break; case GPIO_CFG_INPUT_PULLDOWN: gpio_config.direction = kGPIO_DigitalInput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x3030U; /* 100K Ohm Pull Down */ break; case GPIO_CFG_OUTPUT_OD: gpio_config.direction = kGPIO_DigitalOutput; - gpio_config.interruptMode = kGPIO_NoIntmode; + config_value = 0x0830U; /* Open Drain Enable */ break; default: break; } - GPIO_PinInit(index->gpio, index->pin, &gpio_config); + + if (pin_mask[pin_index->index].gpio != GPIO5) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1); + IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value); + } else { + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1); + IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value); + } + + GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config); return EOK; } @@ -392,7 +419,7 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param) switch(param->cmd) { case GPIO_CONFIG_MODE: - GpioConfigMode(param->mode, &pin_index); + GpioConfigMode(param->mode, &pin_index, param->pin); break; case GPIO_IRQ_REGISTER: ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args); @@ -554,6 +581,9 @@ static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Ty if (isr_status & (1 << i)) { GPIO_PortClearInterruptFlags(gpio, (1 << i)); + + __DSB(); + pin = index_offset + i; if (pin_irq_hdr_tab[pin].hdr) { pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args); @@ -705,21 +735,6 @@ void GpioLedTest(void) KPrintf("initialize %s failed!\n", PIN_BUS_NAME); return; } - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ struct PinParam led_gpio_param; struct PinStat led_gpio_stat; @@ -762,4 +777,3 @@ void GpioLedTest(void) SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED); #endif - diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h new file mode 100755 index 000000000..2944ed0a2 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h @@ -0,0 +1,273 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ch438.h +* @brief define imxrt1052-board ch438 function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef CONNECT_CH438_H +#define CONNECT_CH438_H + +#include +#include +#include + +#define CH438_BUFFSIZE 255 + +/******************************************************************************************/ + +/* chip definition */ +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + +#define Fpclk 1843200 /* Define the internal clock frequency */ + +#define CH438_D0_PIN IMXRT_GET_PIN(1, 25) +#define CH438_D1_PIN IMXRT_GET_PIN(1, 24) +#define CH438_D2_PIN IMXRT_GET_PIN(1, 20) +#define CH438_D3_PIN IMXRT_GET_PIN(1, 21) +#define CH438_D4_PIN IMXRT_GET_PIN(1, 31) +#define CH438_D5_PIN IMXRT_GET_PIN(1, 28) +#define CH438_D6_PIN IMXRT_GET_PIN(1, 30) +#define CH438_D7_PIN IMXRT_GET_PIN(1, 29) +#define CH438_NWR_PIN IMXRT_GET_PIN(3, 4) +#define CH438_NRD_PIN IMXRT_GET_PIN(3, 5) +#define CH438_ALE_PIN IMXRT_GET_PIN(3, 2) +#define CH438_INT_PIN IMXRT_GET_PIN(3, 3) + +int Imxrt1052HwCh438Init(void); + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ethernet.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ethernet.h new file mode 100755 index 000000000..376c004fe --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ethernet.h @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2021 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_ethernet.h +* @brief Adapted network software protocol stack and hardware operation functions +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-12-7 +*/ + +#ifndef __CONNECT_ETHERNET_H_ +#define __CONNECT_ETHERNET_H_ + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifndef sourceClock +#define sourceClock CLOCK_GetFreq(kCLOCK_CoreSysClk) +#endif + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif.h new file mode 100755 index 000000000..8416d75bc --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif.h + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + + +#ifndef ENET_ETHERNETIF_H +#define ENET_ETHERNETIF_H + +#include "lwip/err.h" +#include "lwip/netif.h" +#include "fsl_enet.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef ENET_RXBD_NUM + #define ENET_RXBD_NUM (5) +#endif +#ifndef ENET_TXBD_NUM +#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0) + #define ENET_TXBD_NUM (5) +#else + #define ENET_TXBD_NUM (3) +#endif +#endif +#ifndef ENET_RXBUFF_SIZE +#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0) + #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN + ETH_PAD_SIZE) +#else + #define ENET_RXBUFF_SIZE ENET_FRAME_MAX_FRAMELEN +#endif +#endif + +#ifndef ENET_TXBUFF_SIZE + #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) +#endif + +#define ENET_TIMEOUT (0xFFFU) + +/* ENET IRQ priority. Used in FreeRTOS. */ +/* Interrupt priorities. */ +#ifdef __CA7_REV +#ifndef ENET_PRIORITY + #define ENET_PRIORITY (21U) +#endif +#ifndef ENET_1588_PRIORITY + #define ENET_1588_PRIORITY (20U) +#endif +#else +#ifndef ENET_PRIORITY + #define ENET_PRIORITY (15U)//(6U) +#endif +#ifndef ENET_1588_PRIORITY + #define ENET_1588_PRIORITY (5U) +#endif +#endif + +/* Defines Ethernet Autonegotiation Timeout during initialization. + * Set it to 0 to disable the waiting. */ +#ifndef ENET_ATONEGOTIATION_TIMEOUT + #define ENET_ATONEGOTIATION_TIMEOUT (0xFFFU) +#endif + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) \ + && ((!defined(FSL_SDK_DISBLE_L2CACHE_PRESENT)) || (FSL_SDK_DISBLE_L2CACHE_PRESENT == 0)) + #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) + #define FSL_CACHE_LINESIZE_MAX MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) + #define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_CACHE_LINESIZE_MAX) + #else + #define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) + #endif + #elif defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) + #define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) + #else + #define FSL_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT + #endif +#else + #define FSL_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT +#endif + +#define ENET_RING_NUM 1U + +typedef uint8_t rx_buffer_t[SDK_SIZEALIGN(ENET_RXBUFF_SIZE, FSL_ENET_BUFF_ALIGNMENT)]; +typedef uint8_t tx_buffer_t[SDK_SIZEALIGN(ENET_TXBUFF_SIZE, FSL_ENET_BUFF_ALIGNMENT)]; + +#if (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)) +typedef struct mem_range +{ + uint32_t start; + uint32_t end; +} mem_range_t; +#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */ + +/** + * Helper struct to hold data for configuration of ethernet interface. + */ +typedef struct ethernetif_config +{ + uint32_t phyAddress; + clock_name_t clockName; + uint8_t macAddress[NETIF_MAX_HWADDR_LEN]; +#if (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)) + const mem_range_t *non_dma_memory; +#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */ +} ethernetif_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * This function should be passed as a parameter to netif_add() + * if you initialize the first ENET interface. + */ +err_t ethernetif0_init(struct netif *netif); + +#if (defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 1)) \ + || (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 1)) +/** + * This function should be passed as a parameter to netif_add() + * if you initialize the second ENET interface. + */ +err_t ethernetif1_init(struct netif *netif); +#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */ + +/** + * This function should be called when a packet is ready to be read + * from the interface. + * It is used by bare-metal applications. + * + * @param netif the lwip network interface structure for this ethernetif + */ +void ethernetif_input( struct netif *netif); + +void ETH_BSP_Config(void); + +int32 lwip_obtain_semaphore(struct netif *netif); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* ENET_ETHERNETIF_H */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif_priv.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif_priv.h new file mode 100755 index 000000000..559466736 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/enet_ethernetif_priv.h @@ -0,0 +1,82 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file enet_ethernetif_priv.h + * @brief ethernet drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + + +#ifndef ENET_ETHERNETIF_PRIV_H +#define ENET_ETHERNETIF_PRIV_H + +#include "lwip/err.h" + +struct ethernetif; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +err_t ethernetif_init(struct netif *netif, struct ethernetif *ethernetif, + const uint8_t enetIdx, + const ethernetif_config_t *ethernetifConfig); + +void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig); + +void ethernetif_phy_init(struct ethernetif *ethernetif, + const ethernetif_config_t *ethernetifConfig, + enet_config_t *config); + +ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif); + +#if LWIP_IPV4 && LWIP_IGMP +err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group, + enum netif_mac_filter_action action); +#endif + +#if LWIP_IPV6 && LWIP_IPV6_MLD +err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group, + enum netif_mac_filter_action action); +#endif + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +struct pbuf *ethernetif_linkinput(struct netif *netif); + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ +err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* ENET_ETHERNETIF_PRIV_H */ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h new file mode 100644 index 000000000..75704eadf --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_semc.h @@ -0,0 +1,830 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SEMC_H_ +#define _FSL_SEMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup semc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMC driver version 2.0.4. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief SEMC status. */ +enum _semc_status +{ + kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), + kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), + kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), + kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), + kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), + kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), + kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), + kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), + kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), + kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), + kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), + kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), +}; + +/*! @brief SEMC memory device type. */ +typedef enum _semc_mem_type +{ + kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ + kSEMC_MemType_SRAM, /*!< SRAM */ + kSEMC_MemType_NOR, /*!< NOR */ + kSEMC_MemType_NAND, /*!< NAND */ + kSEMC_MemType_8080 /*!< 8080. */ +} semc_mem_type_t; + +/*! @brief SEMC WAIT/RDY polarity. */ +typedef enum _semc_waitready_polarity +{ + kSEMC_LowActive = 0, /*!< Low active. */ + kSEMC_HighActive, /*!< High active. */ +} semc_waitready_polarity_t; + +/*! @brief SEMC SDRAM Chip selection . */ +typedef enum _semc_sdram_cs +{ + kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ + kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ + kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ + kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ +} semc_sdram_cs_t; + +/*! @brief SEMC NAND device type. */ +typedef enum _semc_nand_access_type +{ + kSEMC_NAND_ACCESS_BY_AXI = 0, + kSEMC_NAND_ACCESS_BY_IPCMD, +} semc_nand_access_type_t; + +/*! @brief SEMC interrupts . */ +typedef enum _semc_interrupt_enable +{ + kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ + kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ + kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ + kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ +} semc_interrupt_enable_t; + +/*! @brief SEMC IP command data size in bytes. */ +typedef enum _semc_ipcmd_datasize +{ + kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ + kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ + kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ + kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ +} semc_ipcmd_datasize_t; + +/*! @brief SEMC auto-refresh timing. */ +typedef enum _semc_refresh_time +{ + kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ + kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ + kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ +} semc_refresh_time_t; + +/*! @brief CAS latency */ +typedef enum _semc_caslatency +{ + kSEMC_LatencyOne = 1, /*!< Latency 1. */ + kSEMC_LatencyTwo, /*!< Latency 2. */ + kSEMC_LatencyThree, /*!< Latency 3. */ +} semc_caslatency_t; + +/*! @brief SEMC sdram column address bit number. */ +typedef enum _semc_sdram_column_bit_num +{ + kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_SdramColunm_11bit, /*!< 11 bit. */ + kSEMC_SdramColunm_10bit, /*!< 10 bit. */ + kSEMC_SdramColunm_9bit, /*!< 9 bit. */ +} semc_sdram_column_bit_num_t; + +/*! @brief SEMC sdram burst length. */ +typedef enum _semc_sdram_burst_len +{ + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ + kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ + kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ +} sem_sdram_burst_len_t; + +/*! @brief SEMC nand column address bit number. */ +typedef enum _semc_nand_column_bit_num +{ + kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ + kSEMC_NandColum_15bit, /*!< 15 bit. */ + kSEMC_NandColum_14bit, /*!< 14 bit. */ + kSEMC_NandColum_13bit, /*!< 13 bit. */ + kSEMC_NandColum_12bit, /*!< 12 bit. */ + kSEMC_NandColum_11bit, /*!< 11 bit. */ + kSEMC_NandColum_10bit, /*!< 10 bit. */ + kSEMC_NandColum_9bit, /*!< 9 bit. */ +} semc_nand_column_bit_num_t; + +/*! @brief SEMC nand burst length. */ +typedef enum _semc_nand_burst_len +{ + kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ +} sem_nand_burst_len_t; + +/*! @brief SEMC nor/sram column address bit number. */ +typedef enum _semc_norsram_column_bit_num +{ + kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_NorColum_11bit, /*!< 11 bit. */ + kSEMC_NorColum_10bit, /*!< 10 bit. */ + kSEMC_NorColum_9bit, /*!< 9 bit. */ + kSEMC_NorColum_8bit, /*!< 8 bit. */ + kSEMC_NorColum_7bit, /*!< 7 bit. */ + kSEMC_NorColum_6bit, /*!< 6 bit. */ + kSEMC_NorColum_5bit, /*!< 5 bit. */ + kSEMC_NorColum_4bit, /*!< 4 bit. */ + kSEMC_NorColum_3bit, /*!< 3 bit. */ + kSEMC_NorColum_2bit /*!< 2 bit. */ +} semc_norsram_column_bit_num_t; + +/*! @brief SEMC nor/sram burst length. */ +typedef enum _semc_norsram_burst_len +{ + kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ +} sem_norsram_burst_len_t; + +/*! @brief SEMC dbi column address bit number. */ +typedef enum _semc_dbi_column_bit_num +{ + kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ + kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ + kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ + kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ + kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ + kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ + kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ + kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ + kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ + kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ +} semc_dbi_column_bit_num_t; + +/*! @brief SEMC dbi burst length. */ +typedef enum _semc_dbi_burst_len +{ + kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ + kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ + kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ + kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ + kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ + kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ +} sem_dbi_burst_len_t; + +/*! @brief SEMC IOMUXC. */ +typedef enum _semc_iomux_pin +{ + kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ + kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ + kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ + kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ + kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_pin; + +/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ +typedef enum _semc_iomux_nora27_pin +{ + kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ + kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_nora27_pin; + +/*! @brief SEMC port size. */ +typedef enum _semc_port_size +{ + kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ + kSEMC_PortSize16Bit /*!< 16-Bit port size. */ +} smec_port_size_t; + +/*! @brief SEMC address mode. */ +typedef enum _semc_addr_mode +{ + kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ + kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ + kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ +} semc_addr_mode_t; + +/*! @brief SEMC DQS read strobe mode. */ +typedef enum _semc_dqs_mode +{ + kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ + kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ +} semc_dqs_mode_t; + +/*! @brief SEMC ADV signal active polarity. */ +typedef enum _semc_adv_polarity +{ + kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ + kSEMC_AdvActivehigh, /*!< Adv active low. */ +} semc_adv_polarity_t; + +/*! @brief SEMC RDY signal active polarity. */ +typedef enum _semc_rdy_polarity +{ + kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ + kSEMC_RdyActivehigh, /*!< Adv active low. */ +} semc_rdy_polarity_t; + +/*! @brief SEMC IP command for NAND: address mode. */ +typedef enum _semc_ipcmd_nand_addrmode +{ + kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ + kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ + kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ + kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ + kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ + kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ +} semc_ipcmd_nand_addrmode_t; + +/*! @brief SEMC IP command for NAND： command mode. */ +typedef enum _semc_ipcmd_nand_cmdmode +{ + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ + kSEMC_NANDCM_CommandHold, /*!< Command hold. */ + kSEMC_NANDCM_CommandAddress, /*!< Command address. */ + kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ + kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ + kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ + kSEMC_NANDCM_CommandRead, /*!< Command read. */ + kSEMC_NANDCM_CommandWrite, /*!< Command write. */ + kSEMC_NANDCM_Read, /*!< Read. */ + kSEMC_NANDCM_Write /*!< Write. */ +} semc_ipcmd_nand_cmdmode_t; + +/*! @brief SEMC NAND address option. */ +typedef enum _semc_nand_address_option +{ + kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ + kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ + kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ + kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ +} semc_nand_address_option_t; + +/*! @brief SEMC IP command for NOR. */ +typedef enum _semc_ipcmd_nor_dbi +{ + kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ + kSEMC_NORDBICM_Write /*!< NOR write. */ +} semc_ipcmd_nor_dbi_t; + +/*! @brief SEMC IP command for SRAM. */ +typedef enum _semc_ipcmd_sram +{ + kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ + kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ + kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ + kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ +} semc_ipcmd_sram_t; + +/*! @brief SEMC IP command for SDARM. */ +typedef enum _semc_ipcmd_sdram +{ + kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ + kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ + kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ + kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ + kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ + kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ + kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ + kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ +} semc_ipcmd_sdram_t; + +/*! @brief SEMC SDRAM configuration structure. + * + * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes + * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. + * Take refer to BR0~BR3 register in RM for details. + * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, + * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, + * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. + * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are + * similar to prescalePeriod_N16Cycle. + * + */ +typedef struct _semc_sdram_config +{ + semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + smec_port_size_t portSize; /*!< Port size. */ + sem_sdram_burst_len_t burstLen; /*!< Burst length. */ + semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_caslatency_t casLatency; /*!< CAS latency. */ + uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ + uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ + uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ + uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ + uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ + uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ + uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ + uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ + uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ + uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ + uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ + uint8_t refreshBurstLen; /*!< Refresh burst length. */ +} semc_sdram_config_t; + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + +/*! @brief SEMC NAND configuration structure. */ +typedef struct _semc_nand_config +{ + semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ + uint32_t axiAddress; /*!< The base address for AXI nand. */ + uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ + uint32_t ipgAddress; /*!< The base address for IPG nand . */ + uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + bool edoModeEnabled; /*!< EDO mode enabled. */ + semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ + sem_nand_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ +} semc_nand_config_t; + +/*! @brief SEMC NOR configuration structure. */ +typedef struct _semc_nor_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ + semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ +#endif + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_nor_config_t; + +/*! @brief SEMC SRAM configuration structure. */ +typedef struct _semc_sram_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_sram_config_t; + +/*! @brief SEMC DBI configuration structure. */ +typedef struct _semc_dbi_config +{ + semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ + semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + sem_dbi_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ + uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ + uint8_t tWexLow_Ns; /*!< WEX low time. */ + uint8_t tWexHigh_Ns; /*!< WEX high time. */ + uint8_t tRdxLow_Ns; /*!< RDX low time. */ + uint8_t tRdxHigh_Ns; /*!< RDX high time. */ + uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ +} semc_dbi_config_t; + +/*! @brief SEMC AXI queue a weight setting structure. */ +typedef struct _semc_queuea_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 0 . */ + uint32_t aging : 4; /*!< weight of aging for queue 0.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ + uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ +} semc_queuea_weight_struct_t; + +/*! @brief SEMC AXI queue a weight setting union. */ +typedef union _semc_queuea_weight +{ + semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */ + uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */ +} semc_queuea_weight_t; + +/*! @brief SEMC AXI queue b weight setting structure. */ +typedef struct _semc_queueb_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 1. */ + uint32_t aging : 4; /*!< weight of aging for queue 1.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ + uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ + uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ +} semc_queueb_weight_struct_t; + +/*! @brief SEMC AXI queue b weight setting union. */ +typedef union _semc_queueb_weight +{ + semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */ + uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */ +} semc_queueb_weight_t; + +/*! @brief SEMC AXI queue weight setting. */ +typedef struct _semc_axi_queueweight +{ + semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */ + semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */ +} semc_axi_queueweight_t; + +/*! + * @brief SEMC configuration structure. + * + * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is + * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. + * cmdTimeoutCycles: is used for command execution timeout cycles. it's + * similar to the busTimeoutCycles. + */ +typedef struct _semc_config_t +{ + semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ + uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ + uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ + semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ +} semc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMC Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + @code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + @endcode + * @param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config); + +/*! + * @brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * @param base SEMC peripheral base address. + * @param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure); + +/*! + * @brief Deinitializes the SEMC module and gates the clock. + * + * This function gates the SEMC clock. As a result, the SEMC module doesn't work after + * calling this function, for some IDE, calling this API may cause the next downloading + * operation failed. so, please call this API cautiously. Additional, users can + * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control + * operation in drivers. + * + * @param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base); + +/* @} */ + +/*! + * @name SEMC Configuration Operation For Each Memory Type + * @{ + */ + +/*! + * @brief Configures SDRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param cs The chip selection. + * @param config The sdram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NAND controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nand configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NOR controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nor configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures SRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The sram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures DBI controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The dbi configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); + +/* @} */ + +/*! + * @name SEMC Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the SEMC interrupt. + * + * This function enables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to enable the IP command done and error interrupt, do the following. + * @code + * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to enable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disables the SEMC interrupt. + * + * This function disables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to disable the IP command done and error interrupt, do the following. + * @code + * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to disable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/*! + * @brief Gets the SEMC status. + * + * This function gets the SEMC interrupts event status. + * User can use the a logical OR of enumeration member as a mask. + * See @ref semc_interrupt_enable_t. + * + * @param base SEMC peripheral base address. + * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. + */ +static inline bool SEMC_GetStatusFlag(SEMC_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Clears the SEMC status flag state. + * + * The following status register flags can be cleared SEMC interrupt status. + * + * @param base SEMC base pointer + * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. + */ +static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +/* @} */ + +/*! + * @name SEMC Memory Access Operation + * @{ + */ + +/*! + * @brief Check if SEMC is in idle. + * + * @param base SEMC peripheral base address. + * @return True SEMC is in idle, false is not in idle. + */ +static inline bool SEMC_IsInIdle(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false; +} + +/*! + * @brief SEMC IP command access. + * + * @param base SEMC peripheral base address. + * @param type SEMC memory type. refer to "semc_mem_type_t" + * @param address SEMC device address. + * @param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * @param write Data for write access. + * @param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read); + +/*! + * @brief Build SEMC IP command for NAND. + * + * This function build SEMC NAND IP command. The command is build of user command code, + * SEMC address mode and SEMC command mode. + * + * @param userCommand NAND device normal command. + * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". + * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". + */ +static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, + semc_ipcmd_nand_addrmode_t addrMode, + semc_ipcmd_nand_cmdmode_t cmdMode) +{ + return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu); +} + +/*! + * @brief Check if the NAND device is ready. + * + * @param base SEMC peripheral base address. + * @return True NAND is ready, false NAND is not ready. + */ +static inline bool SEMC_IsNandReady(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false; +} + +/*! + * @brief SEMC NAND device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NAND device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SEMC_H_*/ diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig new file mode 100644 index 000000000..f081299fb --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig @@ -0,0 +1,9 @@ +config BSP_USING_EXTSRAM + bool "config semc extern sram" + default n + select MEM_EXTERN_SRAM + if BSP_USING_EXTSRAM + config EXTSRAM_MAX_NUM + int "config extsram chip num" + default 4 + endif diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile new file mode 100644 index 000000000..6438aa6ea --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := connect_semc.c fsl_semc.c semc_externsdram_test.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c new file mode 100644 index 000000000..2477fb2f6 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c @@ -0,0 +1,57 @@ +#include "fsl_semc.h" +#include "clock_config.h" +#include + +#define EXAMPLE_SEMC SEMC +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) +#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk) +#define SEMC_SRAM_SIZE (32 * 1024 * 1024) + +status_t BOARD_InitSEMC(void) +{ + semc_config_t config; + semc_sdram_config_t sdramconfig; + uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ; + + /* Initializes the MAC configure structure to zero. */ + memset(&config, 0, sizeof(semc_config_t)); + memset(&sdramconfig, 0, sizeof(semc_sdram_config_t)); + + /* Initialize SEMC. */ + SEMC_GetDefaultConfig(&config); + config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */ + SEMC_Init(SEMC, &config); + + /* Configure SDRAM. */ + sdramconfig.csxPinMux = kSEMC_MUXCSX0; + sdramconfig.address = 0x80000000; + sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/ + sdramconfig.portSize = kSEMC_PortSize16Bit; + sdramconfig.burstLen = kSEMC_Sdram_BurstLen8; + sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit; + sdramconfig.casLatency = kSEMC_LatencyThree; + sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */ + sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */ + sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */ + sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */ + sdramconfig.tCkeOff_Ns = + 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/ + sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */ + sdramconfig.tSelfRefRecovery_Ns = 67; + sdramconfig.tRefresh2Refresh_Ns = 60; + sdramconfig.tAct2Act_Ns = 60; + sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq); + sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */ + sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow; + sdramconfig.refreshBurstLen = 1; + return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq); +} + +#ifdef BSP_USING_EXTSRAM +int ExtSramInit(void) +{ + extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx); + ExtSramInitBoardMemory((void*)(EXAMPLE_SEMC_START_ADDRESS), (void*)((EXAMPLE_SEMC_START_ADDRESS + SEMC_SRAM_SIZE)), kSEMC_SDRAM_CS0); + return 0; +} +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/fsl_semc.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/fsl_semc.c new file mode 100644 index 000000000..be3f225e7 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/fsl_semc.c @@ -0,0 +1,1066 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_semc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.semc" +#endif + +/*! @brief Define macros for SEMC driver. */ +#define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U) +#define SEMC_IPCOMMANDMAGICKEY (0xA55A) +#define SEMC_IOCR_PINMUXBITWIDTH (0x3U) +#define SEMC_IOCR_NAND_CE (4U) +#define SEMC_IOCR_NOR_CE (5U) +#define SEMC_IOCR_NOR_CE_A8 (2U) +#define SEMC_IOCR_PSRAM_CE (6U) +#define SEMC_IOCR_PSRAM_CE_A8 (3U) +#define SEMC_IOCR_DBI_CSX (7U) +#define SEMC_IOCR_DBI_CSX_A8 (4U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX (28U) +#define SEMC_BMCR0_TYPICAL_WQOS (5U) +#define SEMC_BMCR0_TYPICAL_WAGE (8U) +#define SEMC_BMCR0_TYPICAL_WSH (0x40U) +#define SEMC_BMCR0_TYPICAL_WRWS (0x10U) +#define SEMC_BMCR1_TYPICAL_WQOS (5U) +#define SEMC_BMCR1_TYPICAL_WAGE (8U) +#define SEMC_BMCR1_TYPICAL_WPH (0x60U) +#define SEMC_BMCR1_TYPICAL_WBR (0x40U) +#define SEMC_BMCR1_TYPICAL_WRWS (0x24U) +#define SEMC_STARTADDRESS (0x80000000U) +#define SEMC_ENDADDRESS (0xDFFFFFFFU) +#define SEMC_BR_MEMSIZE_MIN (4) +#define SEMC_BR_MEMSIZE_OFFSET (2) +#define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024) +#define SEMC_SDRAM_MODESETCAL_OFFSET (4) +#define SEMC_BR_REG_NUM (9) +#define SEMC_BYTE_NUMBIT (8) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for SEMC module. + * + * @param base SEMC peripheral base address + */ +static uint32_t SEMC_GetInstance(SEMC_Type *base); + +/*! + * @brief Covert the input memory size to internal register set value. + * + * @param base SEMC peripheral base address + * @param size_kbytes SEMC memory size in unit of kbytes. + * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F. + * @return Execution status. + */ +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted); + +/*! + * @brief Covert the external timing nanosecond to internal clock cycle. + * + * @param time_ns SEMC external time interval in unit of nanosecond. + * @param clkSrc_Hz SEMC clock source frequency. + * @return The changed internal clock cycle. + */ +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz); + +/*! + * @brief Configure IP command. + * + * @param base SEMC peripheral base address. + * @param size_bytes SEMC IP command data size. + * @return Execution status. + */ +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes); + +/*! + * @brief Check if the IP command has finished. + * + * @param base SEMC peripheral base address. + * @return Execution status. + */ +static status_t SEMC_IsIPCommandDone(SEMC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SEMC clocks for each instance. */ +static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS; +static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to SEMC bases for each instance. */ +static SEMC_Type *const s_semcBases[] = SEMC_BASE_PTRS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SEMC_GetInstance(SEMC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_semcBases); instance++) + { + if (s_semcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_semcBases)); + + return instance; +} + +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted) +{ + assert(sizeConverted); + uint32_t memsize; + + if ((size_kbytes < SEMC_BR_MEMSIZE_MIN) || (size_kbytes > SEMC_BR_MEMSIZE_MAX)) + { + return kStatus_SEMC_InvalidMemorySize; + } + + *sizeConverted = 0; + memsize = size_kbytes / 8; + while (memsize) + { + memsize >>= 1; + (*sizeConverted)++; + } + return kStatus_Success; +} + +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz) +{ + assert(clkSrc_Hz); + + uint8_t clockCycles = 0; + uint32_t tClk_us; + + clkSrc_Hz /= 1000000; + tClk_us = 1000000 / clkSrc_Hz; + + while (tClk_us * clockCycles < (time_ns * 1000)) + { + clockCycles++; + } + + return clockCycles; +} + +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes) +{ + if ((size_bytes > SEMC_IPCOMMANDDATASIZEBYTEMAX) || (!size_bytes)) + { + return kStatus_SEMC_InvalidIpcmdDataSize; + } + + /* Set data size. */ + /* Note: It is better to set data size as the device data port width when transfering + * device command data. but for device memory data transfer, it can be set freely. + * Note: If the data size is greater than data port width, for example, datsz = 4, data port = 16bit, + * then the 4-byte data transfer will be split into two 2-byte transfer, the slave address + * will be switched automatically according to connected device type*/ + base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); + /* Clear data size. */ + base->IPCR2 = 0; + /* Set data size. */ + if (size_bytes < 4) + { + base->IPCR2 |= SEMC_IPCR2_BM3_MASK; + } + if (size_bytes < 3) + { + base->IPCR2 |= SEMC_IPCR2_BM2_MASK; + } + if (size_bytes < 2) + { + base->IPCR2 |= SEMC_IPCR2_BM1_MASK; + } + return kStatus_Success; +} + +static status_t SEMC_IsIPCommandDone(SEMC_Type *base) +{ + /* Poll status bit till command is done*/ + while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK)) + { + }; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + + /* Check error status */ + if (base->INTR & SEMC_INTR_IPCMDERR_MASK) + { + base->INTR |= SEMC_INTR_IPCMDERR_MASK; + return kStatus_SEMC_IpCommandExecutionError; + } + + return kStatus_Success; +} + +/*! + * brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + endcode + * param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + semc_queuea_weight_struct_t *queueaWeight = &(config->queueWeight.queueaWeight.queueaConfig); + semc_queueb_weight_struct_t *queuebWeight = &(config->queueWeight.queuebWeight.queuebConfig); + + /* Get default settings. */ + config->dqsMode = kSEMC_Loopbackinternal; + config->cmdTimeoutCycles = 0; + config->busTimeoutCycles = 0x1F; + + queueaWeight->qos = SEMC_BMCR0_TYPICAL_WQOS; + queueaWeight->aging = SEMC_BMCR0_TYPICAL_WAGE; + queueaWeight->slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH; + queueaWeight->slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS; + queuebWeight->qos = SEMC_BMCR1_TYPICAL_WQOS; + queuebWeight->aging = SEMC_BMCR1_TYPICAL_WAGE; + queuebWeight->slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS; + queuebWeight->weightPagehit = SEMC_BMCR1_TYPICAL_WPH; + queuebWeight->bankRotation = SEMC_BMCR1_TYPICAL_WBR; +} + +/*! + * brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * param base SEMC peripheral base address. + * param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure) +{ + assert(configure); + + uint8_t index = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate sdram controller clock. */ + CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Initialize all BR to zero due to the default base address set. */ + for (index = 0; index < SEMC_BR_REG_NUM; index++) + { + base->BR[index] = 0; + } + + /* Software reset for SEMC internal logical . */ + base->MCR = SEMC_MCR_SWRST_MASK; + while (base->MCR & SEMC_MCR_SWRST_MASK) + { + } + + /* Configure, disable module first. */ + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_BTO(configure->busTimeoutCycles) | + SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode); + + /* Configure Queue 0/1 for AXI bus. */ + base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight.queueaValue); + base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight.queuebValue); + + /* Enable SEMC. */ + base->MCR &= ~SEMC_MCR_MDIS_MASK; +} + +/*! + * brief Deinitializes the SEMC module and gates the clock. + * This function gates the SEMC clock. As a result, the SEMC + * module doesn't work after calling this function. + * + * param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base) +{ + /* Disable module. Check there is no pending command before disable module. */ + while (!(base->STS0 & SEMC_STS0_IDLE_MASK)) + { + ; + } + + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SDRAM clock. */ + CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures SDRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param cs The chip selection. + * param config The sdram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(clkSrc_Hz); + assert(config->refreshBurstLen); + + uint8_t memsize; + status_t result = kStatus_Success; + uint16_t prescale = config->tPrescalePeriod_Ns / 16 / (1000000000 / clkSrc_Hz); + uint16_t refresh; + uint16_t urgentRef; + uint16_t idle; + uint16_t mode; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->csxPinMux == kSEMC_MUXA8) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (prescale > 256) + { + return kStatus_SEMC_InvalidTimerSetting; + } + + refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns; + urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns; + idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns; + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + + base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | + SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency); + /* IOMUX setting. */ + if (cs) + { + base->IOCR = iocReg | (cs << config->csxPinMux); + } + + base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK; + + /* Timing setting. */ + base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1); + base->SDRAMCR2 = + SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR2_REF2REF( + SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ITO(idle); + base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) | + /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */ + SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef); + + SEMC->IPCR1 = 0x2; + SEMC->IPCR2 = 0; + + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Prechargeall, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Mode setting value. */ + mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET); + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Enables refresh */ + base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; + + return kStatus_Success; +} + +/*! + * brief Configures NAND controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nand configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(config->timingConfig); + + uint8_t memsize; + status_t result; + + if ((config->axiAddress < SEMC_STARTADDRESS) || (config->axiAddress > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->cePinMux == kSEMC_MUXRDY) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + uint32_t iocReg = base->IOCR & ~((SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux) | SEMC_IOCR_MUX_RDY_MASK); + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL1_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL1_MASK; + } + result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + /* IOMUX setting. */ + if (config->cePinMux) + { + base->IOCR = iocReg | (SEMC_IOCR_NAND_CE << config->cePinMux); + } + else + { + base->IOCR = iocReg | (1U << config->cePinMux); + } + + base->NANDCR0 = SEMC_NANDCR0_PS(config->portSize) | SEMC_NANDCR0_BL(config->burstLen) | + SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1); + base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1); + base->NANDCR3 = config->arrayAddrOption; + return kStatus_Success; +} + +/*! + * brief Configures NOR controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nor configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_NOR_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL0_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL0_MASK; + } + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) | + SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) | + SEMC_NORCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NORCR1 = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + base->NORCR2 = +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | +#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | +#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME */ + SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) | + SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +/*! + * brief Configures SRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The sram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result = kStatus_Success; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_PSRAM_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[6] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SRAMCR0 = SEMC_SRAMCR0_PS(config->portSize) | SEMC_SRAMCR0_BL(config->burstLen) | + SEMC_SRAMCR0_AM(config->addrMode) | SEMC_SRAMCR0_ADVP(config->advActivePolarity) | + SEMC_SRAMCR0_COL_MASK; + + /* Timing setting. */ + base->SRAMCR1 = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + + base->SRAMCR2 = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD(config->readCycle) | + SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return result; +} + +/*! + * brief Configures DBI controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The dbi configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_DBI_CSX - 1 : + ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCsx << config->csxPinMux); + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->DBICR0 = + SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz) - 1); + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +/*! + * brief SEMC IP command access. + * + * param base SEMC peripheral base address. + * param type SEMC memory type. refer to "semc_mem_type_t" + * param address SEMC device address. + * param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * param write Data for write access. + * param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) +{ + uint32_t cmdMode; + bool readCmd = 0; + bool writeCmd = 0; + status_t result; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + /* Set address. */ + base->IPCR0 = address; + + /* Check command mode. */ + cmdMode = command & 0xFU; + switch (type) + { + case kSEMC_MemType_NAND: + readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || (cmdMode == kSEMC_NANDCM_CommandRead) || + (cmdMode == kSEMC_NANDCM_Read); + writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || (cmdMode == kSEMC_NANDCM_CommandWrite) || + (cmdMode == kSEMC_NANDCM_Write); + break; + case kSEMC_MemType_NOR: + case kSEMC_MemType_8080: + readCmd = (cmdMode == kSEMC_NORDBICM_Read); + writeCmd = (cmdMode == kSEMC_NORDBICM_Write); + break; + case kSEMC_MemType_SRAM: + readCmd = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead); + writeCmd = (cmdMode == kSEMC_SRAMCM_ArrayWrite) || (cmdMode == kSEMC_SRAMCM_RegWrite); + break; + case kSEMC_MemType_SDRAM: + readCmd = (cmdMode == kSEMC_SDRAMCM_Read); + writeCmd = (cmdMode == kSEMC_SDRAMCM_Write) || (cmdMode == kSEMC_SDRAMCM_Modeset); + break; + default: + break; + } + + if (writeCmd) + { + /* Set data. */ + base->IPTXDAT = write; + } + + /* Set command code. */ + base->IPCMD = command | SEMC_IPCMD_KEY(SEMC_IPCOMMANDMAGICKEY); + /* Wait for command done. */ + result = SEMC_IsIPCommandDone(base); + if (result != kStatus_Success) + { + return result; + } + + if (readCmd) + { + /* Get the read data */ + *read = base->IPRXDAT; + } + + return kStatus_Success; +} + +/*! + * brief SEMC NAND device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data for write access. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Write command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Write); + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL); + } + + return result; +} + +/*! + * brief SEMC NAND device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + /* Read command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Read); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, &tempData); + + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + return result; +} + +/*! + * brief SEMC NOR device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData); + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + SEMC_ConfigureIPCommand(base, dataSize); + return result; +} + +/*! + * brief SEMC NOR device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data for write access. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Write command built */ + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, tempData, NULL); + } + SEMC_ConfigureIPCommand(base, dataSize); + + return result; +} diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c new file mode 100644 index 000000000..c09b6dc27 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c @@ -0,0 +1,180 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "board.h" + +#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U) + +#define SEMC_EXAMPLE_DATALEN (0x1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void SEMC_SDRAMReadWrite32Bit(void); +static void SEMC_SDRAMReadWrite16Bit(void); +static void SEMC_SDRAMReadWrite8Bit(void); +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN]; +uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN]; + +/*! + * @brief Main function + */ +int semc_externsram_test(void) +{ + KPrintf("\r\n SEMC SDRAM Example Start!\r\n"); + + /* 32Bit data read and write. */ + SEMC_SDRAMReadWrite32Bit(); + /* 16Bit data read and write. */ + SEMC_SDRAMReadWrite16Bit(); + /* 8Bit data read and write. */ + SEMC_SDRAMReadWrite8Bit(); + + KPrintf("\r\n SEMC SDRAM Example End.\r\n"); + +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),semc_externsram_test, semc_externsram_test, semc_externsram_test ); + +void SEMC_SDRAMReadWrite32Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite16Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0xFFFF; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n"); + } +} + +static void SEMC_SDRAMReadWrite8Bit(void) +{ + uint32_t index; + uint32_t datalen = SEMC_EXAMPLE_DATALEN; + uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */ + int result = 0; + + KPrintf("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + + memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer)); + memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer)); + + /* Prepare data and write to SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_writeBuffer[index] = index % 0x100; + sdram[index] = sdram_writeBuffer[index]; + } + + KPrintf("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen); + /* Read data from the SDRAM. */ + for (index = 0; index < datalen; index++) + { + sdram_readBuffer[index] = sdram[index]; + } + + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n"); + /* Compare the two buffers. */ + while (datalen--) + { + if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen]) + { + result = -1; + break; + } + } + + if (result < 0) + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n"); + } + else + { + KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n"); + } +} diff --git a/Ubiquitous/XiZi/board/xidatong/xip/Makefile b/Ubiquitous/XiZi/board/xidatong/xip/Makefile new file mode 100755 index 000000000..e27f9550a --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 000000000..503d56845 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,1149 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.c +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif + +const uint8_t dcd_sdram[1072] = { + /*0000*/ 0xD2, + 0x04, + 0x30, + 0x41, + 0xCC, + 0x03, + 0xAC, + 0x04, + 0x40, + 0x0F, + 0xC0, + 0x68, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0010*/ 0x40, + 0x0F, + 0xC0, + 0x6C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x70, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0020*/ 0x40, + 0x0F, + 0xC0, + 0x74, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x78, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0030*/ 0x40, + 0x0F, + 0xC0, + 0x7C, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x0F, + 0xC0, + 0x80, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + /*0040*/ 0x40, + 0x0D, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0D, + 0x81, + 0x00, + 0x00, + 0x1D, + 0x00, + 0x00, + /*0050*/ 0x40, + 0x0F, + 0xC0, + 0x14, + 0x00, + 0x01, + 0x0D, + 0x40, + 0x40, + 0x1F, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /*0060*/ 0x40, + 0x1F, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x1C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0070*/ 0x40, + 0x1F, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /*0080*/ 0x40, + 0x1F, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x2C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0090*/ 0x40, + 0x1F, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /*00a0*/ 0x40, + 0x1F, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00b0*/ 0x40, + 0x1F, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /*00c0*/ 0x40, + 0x1F, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x4C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00d0*/ 0x40, + 0x1F, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /*00e0*/ 0x40, + 0x1F, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x5C, + 0x00, + 0x00, + 0x00, + 0x00, + /*00f0*/ 0x40, + 0x1F, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /*0100*/ 0x40, + 0x1F, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x6C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0110*/ 0x40, + 0x1F, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /*0120*/ 0x40, + 0x1F, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x7C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0130*/ 0x40, + 0x1F, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /*0140*/ 0x40, + 0x1F, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x8C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0150*/ 0x40, + 0x1F, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /*0160*/ 0x40, + 0x1F, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0x9C, + 0x00, + 0x00, + 0x00, + 0x00, + /*0170*/ 0x40, + 0x1F, + 0x80, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xA4, + 0x00, + 0x00, + 0x00, + 0x00, + /*0180*/ 0x40, + 0x1F, + 0x80, + 0xA8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x80, + 0xAC, + 0x00, + 0x00, + 0x00, + 0x00, + /*0190*/ 0x40, + 0x1F, + 0x80, + 0xB0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1F, + 0x80, + 0xB4, + 0x00, + 0x00, + 0x00, + 0x00, + /*01a0*/ 0x40, + 0x1F, + 0x80, + 0xB8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1F, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01b0*/ 0x40, + 0x1F, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x0C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01c0*/ 0x40, + 0x1F, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01d0*/ 0x40, + 0x1F, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x1C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01e0*/ 0x40, + 0x1F, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xF9, + /*01f0*/ 0x40, + 0x1F, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x2C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0200*/ 0x40, + 0x1F, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0210*/ 0x40, + 0x1F, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x3C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0220*/ 0x40, + 0x1F, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0230*/ 0x40, + 0x1F, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x4C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0240*/ 0x40, + 0x1F, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0250*/ 0x40, + 0x1F, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x5C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0260*/ 0x40, + 0x1F, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0270*/ 0x40, + 0x1F, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x6C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0280*/ 0x40, + 0x1F, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xF9, + /*0290*/ 0x40, + 0x1F, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x7C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02a0*/ 0x40, + 0x1F, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02b0*/ 0x40, + 0x1F, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x8C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02c0*/ 0x40, + 0x1F, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02d0*/ 0x40, + 0x1F, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0x9C, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02e0*/ 0x40, + 0x1F, + 0x82, + 0xA0, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x1F, + 0x82, + 0xA4, + 0x00, + 0x01, + 0x10, + 0xF9, + /*02f0*/ 0x40, + 0x1F, + 0x82, + 0xA8, + 0x00, + 0x01, + 0x10, + 0xF9, + 0x40, + 0x2F, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /*0300*/ 0x40, + 0x2F, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2F, + 0x00, + 0x0C, + 0x06, + 0x03, + 0x05, + 0x24, + /*0310*/ 0x40, + 0x2F, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1B, + /*0320*/ 0x40, + 0x2F, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1B, + 0x40, + 0x2F, + 0x00, + 0x1C, + 0x86, + 0x00, + 0x00, + 0x1B, + /*0330*/ 0x40, + 0x2F, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x24, + 0xA0, + 0x00, + 0x00, + 0x19, + /*0340*/ 0x40, + 0x2F, + 0x00, + 0x28, + 0xA8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2F, + 0x00, + 0x2C, + 0xA9, + 0x00, + 0x00, + 0x1B, + /*0350*/ 0x40, + 0x2F, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xA8, + /*0360*/ 0x40, + 0x2F, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0F, + 0x31, + 0x40, + 0x2F, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /*0370*/ 0x40, + 0x2F, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x21, + 0x0A, + 0x08, + /*0380*/ 0x40, + 0x2F, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2F, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /*0390*/ 0x40, + 0x2F, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2F, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /*03a0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0F, + /*03b0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03c0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03d0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x14, + 0x04, + /*03e0*/ 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0C, + /*03f0*/ 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x1C, + 0x04, + /*0400*/ 0x40, + 0x2F, + 0x00, + 0xA0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2F, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /*0410*/ 0x40, + 0x2F, + 0x00, + 0x9C, + 0xA5, + 0x5A, + 0x00, + 0x0A, + 0xCF, + 0x00, + 0x0C, + 0x1C, + 0x40, + 0x2F, + 0x00, + 0x3C, + /*0420*/ 0x00, + 0x00, + 0x00, + 0x01, + 0xCC, + 0x00, + 0x0C, + 0x04, + 0x40, + 0x2F, + 0x00, + 0x4C, + 0x50, + 0x07, + 0x0A, + 0x09, +}; diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 000000000..b6677b274 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,123 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_boot.h +* @brief support to register flexspi image vector table +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +//extern const uint8_t dcd_sdram[1044]; +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 000000000..c5cc52dbc --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,88 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.c +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t Qspiflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3u, + .csSetupTime = 3u, + .deviceModeCfgEnable = true, + .deviceModeType = 1,//Quad Enable command + .deviceModeSeq.seqNum = 1, + .deviceModeSeq.seqId = 4, + .deviceModeArg = 0x000200,//Set QE + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI + .sflashA1Size = 16u * 1024u * 1024u,//4MBytes + .dataValidTime = {16u, 16u}, + .lookupTable = + { +// //Fast Read Sequence +// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18), +// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08), +// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0), + //Quad Input/output read sequence + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), + //Read Status + [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + //Write Enable + [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0), + //Write status + [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, +}; diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 000000000..73d4547b7 --- /dev/null +++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** +* @file fsl_flexspi_nor_flash.h +* @brief support to define flexspi flash config +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-22 +*/ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__ diff --git a/Ubiquitous/XiZi/kernel/kernel_test/test_ch438.c b/Ubiquitous/XiZi/kernel/kernel_test/test_ch438.c index 7802334f4..a63a7e54e 100644 --- a/Ubiquitous/XiZi/kernel/kernel_test/test_ch438.c +++ b/Ubiquitous/XiZi/kernel/kernel_test/test_ch438.c @@ -12,7 +12,7 @@ /** * @file TestCh438.c -* @brief support to test ch438 function +* @brief support to test ch438 function, only support aiit_arm32_board and aiit_riscv64-board * @version 1.0 * @author AIIT XUOS Lab * @date 2021-04-24 diff --git a/Ubiquitous/XiZi/path_kernel.mk b/Ubiquitous/XiZi/path_kernel.mk index 6e90d6c27..3b6f53047 100755 --- a/Ubiquitous/XiZi/path_kernel.mk +++ b/Ubiquitous/XiZi/path_kernel.mk @@ -13,12 +13,24 @@ KERNELPATHS :=-I$(BSP_ROOT) \ -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/include \ -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/osa \ -I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/phy \ + -I$(BSP_ROOT)/third_party_driver/ethernet \ + -I$(BSP_ROOT)/third_party_driver/ethernet/lan8720 \ -I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \ -I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \ -I$(BSP_ROOT)/third_party_driver/CMSIS/Include \ -I$(KERNEL_ROOT)/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \ -I$(KERNEL_ROOT)/resources/include \ - -I$(BSP_ROOT)/include # + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/xip # endif ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/kd233) @@ -225,7 +237,8 @@ KERNELPATHS :=-I$(BSP_ROOT) \ -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \ -I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \ -I$(KERNEL_ROOT)/resources/include \ - -I$(BSP_ROOT)/include # + -I$(BSP_ROOT)/include \ + -I$(BSP_ROOT)/xip # endif ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f103-nano)