forked from xuos/xiuos
Wang_Weigen
80833 lines
4.0 MiB
Plaintext
80833 lines
4.0 MiB
Plaintext
/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_IPU_REGISTERS_H__
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#define __HW_IPU_REGISTERS_H__
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#include "regs.h"
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/*
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* i.MX6DQ IPU
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*
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* IPU Registers
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*
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* Registers defined in this header file:
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* - HW_IPU_CONF - Configuration Register
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* - HW_IPU_SISG_CTRL0 - SISG Control 0 Register
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* - HW_IPU_SISG_CTRL1 - SISG Control 1 Register
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* - HW_IPU_SISG_SET_I - SISG Set<i> Register
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* - HW_IPU_SISG_CLR_I - SISG Clear <i> Register
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* - HW_IPU_INT_CTRL_1 - Interrupt Control Register 1
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* - HW_IPU_INT_CTRL_2 - Interrupt Control Register 2
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* - HW_IPU_INT_CTRL_3 - Interrupt Control Register 3
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* - HW_IPU_INT_CTRL_4 - Interrupt Control Register 4
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* - HW_IPU_INT_CTRL_5 - Interrupt Control Register 5
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* - HW_IPU_INT_CTRL_6 - Interrupt Control Register 6
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* - HW_IPU_INT_CTRL_7 - Interrupt Control Register 7
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* - HW_IPU_INT_CTRL_8 - Interrupt Control Register 8
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* - HW_IPU_INT_CTRL_9 - Interrupt Control Register 9
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* - HW_IPU_INT_CTRL_10 - Interrupt Control Register 10
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* - HW_IPU_INT_CTRL_11 - Interrupt Control Register 11
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* - HW_IPU_INT_CTRL_12 - Interrupt Control Register 12
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* - HW_IPU_INT_CTRL_13 - Interrupt Control Register 13
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* - HW_IPU_INT_CTRL_14 - Interrupt Control Register 14
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* - HW_IPU_INT_CTRL_15 - Interrupt Control Register15
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* - HW_IPU_SDMA_EVENT_1 - SDMA Event Control Register 1
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* - HW_IPU_SDMA_EVENT_2 - SDMA Event Control Register 2
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* - HW_IPU_SDMA_EVENT_3 - SDMA Event Control Register 3
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* - HW_IPU_SDMA_EVENT_4 - SDMA Event Control Register 4
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* - HW_IPU_SDMA_EVENT_7 - SDMA Event Control Register 7
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* - HW_IPU_SDMA_EVENT_8 - SDMA Event Control Register 8
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* - HW_IPU_SDMA_EVENT_11 - SDMA Event Control Register 11
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* - HW_IPU_SDMA_EVENT_12 - SDMA Event Control Register 12
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* - HW_IPU_SDMA_EVENT_13 - SDMA Event Control Register 13
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* - HW_IPU_SDMA_EVENT_14 - SDMA Event Control Register 14
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* - HW_IPU_SRM_PRI1 - Shadow Registers Memory Priority 1 Register
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* - HW_IPU_SRM_PRI2 - Shadow Registers Memory Priority 2 Register
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* - HW_IPU_FS_PROC_FLOW1 - FSU Processing Flow 1 Register
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* - HW_IPU_FS_PROC_FLOW2 - FSU Processing Flow 2 Register
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* - HW_IPU_FS_PROC_FLOW3 - FSU Processing Flow 3 Register
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* - HW_IPU_FS_DISP_FLOW1 - FSU Displaying Flow 1 Register
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* - HW_IPU_FS_DISP_FLOW2 - FSU Displaying Flow 2 Register
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* - HW_IPU_SKIP - SKIP Register
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* - HW_IPU_DISP_ALT_CONF - Display Alternate Configuration Register
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* - HW_IPU_DISP_GEN - Display General Control Register
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* - HW_IPU_DISP_ALT1 - Display Alternate Flow Control Register 1
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* - HW_IPU_DISP_ALT2 - Display Alternate Flow Control Register 2
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* - HW_IPU_DISP_ALT3 - Display Alternate Flow Control Register 3
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* - HW_IPU_DISP_ALT4 - Display Alternate Flow Control Register 4
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* - HW_IPU_MEM_RST - Memory Reset Control Register
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* - HW_IPU_PM - Power Modes Control Register
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* - HW_IPU_GPR - General Purpose Register
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* - HW_IPU_CH_DB_MODE_SEL1 - Channel Double Buffer Mode Select 1 Register
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* - HW_IPU_ALT_CH_DB_MODE_SEL0 - Alternate Channel Double Buffer Mode Select 0 Register
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* - HW_IPU_ALT_CH_DB_MODE_SEL1 - Alternate Channel Double Buffer Mode Select1 Register
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* - HW_IPU_ALT_CH_TRB_MODE_SEL0 - Alternate Channel Triple Buffer Mode Select 0 Register
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* - HW_IPU_ALT_CH_TRB_MODE_SEL1 - Alternate Channel Triple Buffer Mode Select 1 Register
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* - HW_IPU_INT_STAT_1 - Interrupt Status Register 1
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* - HW_IPU_INT_STAT_2 - Interrupt Status Register2
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* - HW_IPU_INT_STAT_3 - Interrupt Status Register 3
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* - HW_IPU_INT_STAT_4 - Interrupt Status Register 4
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* - HW_IPU_INT_STAT_5 - Interrupt Status Register 5
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* - HW_IPU_INT_STAT_6 - Interrupt Status Register 6
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* - HW_IPU_INT_STAT_7 - Interrupt Status Register7 1
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* - HW_IPU_INT_STAT_8 - Interrupt Status Register 8
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* - HW_IPU_INT_STAT_9 - Interrupt Status Register 9
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* - HW_IPU_INT_STAT_10 - Interrupt Status Register 10
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* - HW_IPU_INT_STAT_11 - Interrupt Status Register 11
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* - HW_IPU_INT_STAT_12 - Interrupt Status Register 12
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* - HW_IPU_INT_STAT_13 - Interrupt Status Register 13
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* - HW_IPU_INT_STAT_14 - Interrupt Status Register 14
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* - HW_IPU_INT_STAT_15 - Interrupt Status Register 15
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* - HW_IPU_CUR_BUF_0 - Current Buffer Register 0
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* - HW_IPU_CUR_BUF_1 - Current Buffer Register 1
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* - HW_IPU_ALT_CUR_0 - Alternate Current Buffer Register 0
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* - HW_IPU_ALT_CUR_1 - Alternate Current Buffer Register 1
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* - HW_IPU_SRM_STAT - Shadow Registers Memory Status Register
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* - HW_IPU_PROC_TASKS_STAT - Processing Status Tasks Register
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* - HW_IPU_DISP_TASKS_STAT - Display Tasks Status Register
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* - HW_IPU_TRIPLE_CUR_BUF_0 - Triple Current Buffer Register 0
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* - HW_IPU_TRIPLE_CUR_BUF_1 - Triple Current Buffer Register 1
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* - HW_IPU_TRIPLE_CUR_BUF_2 - Triple Current Buffer Register 2
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* - HW_IPU_TRIPLE_CUR_BUF_3 - Triple Current Buffer Register 3
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* - HW_IPU_CH_BUF0_RDY0 - IPU Channels Buffer 0 Ready 0 Register
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* - HW_IPU_CH_BUF0_RDY1 - IPU Channels Buffer 0 Ready 1 Register
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* - HW_IPU_CH_BUF1_RDY0 - IPU Channels Buffer 1 Ready 0 Register
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* - HW_IPU_CH_BUF1_RDY1 - IPU Channels Buffer 1 Ready 1Register
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* - HW_IPU_ALT_CH_BUF0_RDY0 - IPU Alternate Channels Buffer 0 Ready 0 Register
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* - HW_IPU_ALT_CH_BUF0_RDY1 - IPU Alternate Channels Buffer 0 Ready 1 Register
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* - HW_IPU_ALT_CH_BUF1_RDY0 - IPU Alternate Channels Buffer1 Ready 0 Register
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* - HW_IPU_ALT_CH_BUF1_RDY1 - IPU Alternate Channels Buffer 1 Ready 1 Register
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* - HW_IPU_CH_BUF2_RDY0 - IPU Channels Buffer 2 Ready 0 Register
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* - HW_IPU_CH_BUF2_RDY1 - IPU Channels Buffer 2 Ready 1 Register
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* - HW_IPU_IDMAC_CONF - IDMAC Configuration Register
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* - HW_IPU_IDMAC_CH_EN_1 - IDMAC Channel Enable 1 Register
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* - HW_IPU_IDMAC_CH_EN_2 - IDMAC Channel Enable 2 Register
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* - HW_IPU_IDMAC_ALT_SEP_ALPHA - IDMAC Alternate Separate Alpha Indication Register
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* - HW_IPU_IDMAC_CH_PRI_1 - IDMAC Channel Priority 1 Register
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* - HW_IPU_IDMAC_CH_PRI_2 - IDMAC Channel Priority 2 Register
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* - HW_IPU_IDMAC_WM_EN_2 - IDMAC Channel Watermark Enable 2 Register
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* - HW_IPU_IDMAC_LOCK_EN_1 - IDMAC Channel Lock Enable 1Register
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* - HW_IPU_IDMAC_LOCK_EN_2 - IDMAC Channel Lock Enable 2Register
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* - HW_IPU_IDMAC_SUB_ADDR_1 - IDMAC Channel Alternate Address 1 Register
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* - HW_IPU_IDMAC_SUB_ADDR_2 - IDMAC Channel Alternate Address 2 Register
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* - HW_IPU_IDMAC_SUB_ADDR_3 - IDMAC Channel Alternate Address 3 Register
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* - HW_IPU_IDMAC_BNDM_EN_1 - IDMAC Band Mode Enable 1 Register
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* - HW_IPU_IDMAC_BNDM_EN_2 - IDMAC Band Mode Enable 2 Register
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* - HW_IPU_IDMAC_SC_CORD - IDMAC Scroll Coordinations Register
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* - HW_IPU_IDMAC_CH_BUSY_1 - IDMAC Channel Busy 1 Register
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* - HW_IPU_IDMAC_CH_BUSY_2 - IDMAC Channel Busy 2 Register
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* - HW_IPU_IDMAC_SEP_ALPHA - IDMAC Separate Alpha Indication Register
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* - HW_IPU_IDMAC_WM_EN_1 - IDMAC Channel Watermark Enable 1 Register
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* - HW_IPU_IDMAC_SUB_ADDR_0 - IDMAC Channel Alternate Address 0 Register
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* - HW_IPU_IDMAC_SUB_ADDR_4 - IDMAC Channel Alternate Address 4 Register
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* - HW_IPU_IDMAC_SC_CORD_1 - IDMAC Scroll Coordinations Register 1
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* - HW_IPU_DP_COM_CONF_SYNC - DP Common Configuration Sync Flow Register
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* - HW_IPU_DP_GRAPH_WIND_CTRL_SYNC - DP Graphic Window Control Sync Flow Register
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* - HW_IPU_DP_FG_POS_SYNC - DP Partial Plane Window Position Sync Flow Register
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* - HW_IPU_DP_CUR_POS_SYNC - DP Cursor Position and Size Sync Flow Register
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* - HW_IPU_DP_CUR_MAP_SYNC - DP Color Cursor Mapping Sync Flow Register
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* - HW_IPU_DP_GAMMA_C_SYNC_I - DP Gamma Constants Sync Flow Register i
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* - HW_IPU_DP_GAMMA_S_SYNC_I - DP Gamma Correction Slope Sync Flow Register i
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* - HW_IPU_DP_CSCA_SYNC_I - DP Color Space Conversion Control Sync Flow Registers
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* - HW_IPU_DP_SCS_SYNC_0 - DP Color Conversion Control Sync Flow Register 0
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* - HW_IPU_DP_SCS_SYNC_1 - DP Color Conversion Control Sync Flow Register 1
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* - HW_IPU_DP_CUR_POS_ALT - DP Cursor Position and Size Alternate Register
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* - HW_IPU_DP_COM_CONF_ASYNC0 - DP Common Configuration Async 0 Flow Register
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* - HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0 - DP Graphic Window Control Async 0 Flow Register
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* - HW_IPU_DP_FG_POS_ASYNC0 - DP Partial Plane Window Position Async 0 Flow Register
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* - HW_IPU_DP_CUR_POS_ASYNC0 - DP Cursor Position and Size Async 0 Flow Register
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* - HW_IPU_DP_CUR_MAP_ASYNC0 - DP Color Cursor Mapping Async 0 Flow Register
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* - HW_IPU_DP_GAMMA_C_ASYNC0_I - DP Gamma Constant Async 0 Flow Register i
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* - HW_IPU_DP_GAMMA_S_ASYNC0_I - DP Gamma Correction Slope Async 0 Flow Register i
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* - HW_IPU_DP_CSCA_ASYNC0_I - DP Color Space Conversion Control Async 0 Flow Register i
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* - HW_IPU_DP_CSC_ASYNC0_0 - DP Color Conversion Control Async 0 Flow Register 0
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* - HW_IPU_DP_CSC_ASYNC_1 - DP Color Conversion Control Async 1 Flow Register
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* - HW_IPU_DP_COM_CONF_ASYNC1 - DP Common Configuration Async 1 Flow Register
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* - HW_IPU_DP_DEBUG_CNT - DP Debug Control Register
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* - HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1 - DP Graphic Window Control Async 1 Flow Register
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* - HW_IPU_DP_DEBUG_STAT - DP Debug Status Register
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* - HW_IPU_DP_FG_POS_ASYNC1 - DP Partial Plane Window Position Async 1 Flow Register
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* - HW_IPU_DP_CUR_POS_ASYNC1 - DP Cursor Postion and Size Async 1 Flow Register
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* - HW_IPU_DP_CUR_MAP_ASYNC1 - DP Color Cursor Mapping Async 1 Flow Register
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* - HW_IPU_DP_GAMMA_C_ASYNC1_I - DP Gamma Constants Async 1 Flow Register i
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* - HW_IPU_DP_GAMMA_S_ASYN1_I - DP Gamma Correction Slope Async 1 Flow Register i
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* - HW_IPU_DP_CSCA_ASYNC1_I - DP Color Space Converstion Control Async 1 Flow Register i
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* - HW_IPU_DP_CSC_ASYNC1_0 - DP Color Conversion Control Async 1 Flow Register 0
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* - HW_IPU_DP_CSC_ASYNC1_1 - DP Color Conversion Control Async 1 Flow Register 1
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* - HW_IPU_IC_CONF - IC Configuration Register
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* - HW_IPU_IC_PRP_ENC_RSC - IC Preprocessing Encoder Resizing Coefficients Register
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* - HW_IPU_IC_PRP_VF_RSC - IC Preprocessing View-Finder Resizing Coefficients Register
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* - HW_IPU_IC_PP_RSC - IC Postprocessing Encoder Resizing Coefficients Register
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* - HW_IPU_IC_CMBP_1 - IC Combining Parameters Register 1
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* - HW_IPU_IC_CMBP_2 - IC Combining Parameters Register 2
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* - HW_IPU_IC_IDMAC_1 - IC IDMAC Parameters 1 Register
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* - HW_IPU_IC_IDMAC_2 - IC IDMAC Parameters 2 Register
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* - HW_IPU_IC_IDMAC_3 - IC IDMAC Parameters 3Register
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* - HW_IPU_IC_IDMAC_4 - IC IDMAC Parameters 4 Register
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* - HW_IPU_CSI0_SENS_CONF - CSI0 Sensor Configuration Register
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* - HW_IPU_CSI0_SENS_FRM_SIZE - CSI0 Sense Frame Size Register
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* - HW_IPU_CSI0_ACT_FRM_SIZE - CSI0 Actual Frame Size Register
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* - HW_IPU_CSI0_OUT_FRM_CTRL - CSI0 Output Control Register
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* - HW_IPU_CSI0_TST_CTRL - CSIO Test Control Register
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* - HW_IPU_CSI0_CCIR_CODE_1 - CSIO CCIR Code Register 1
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* - HW_IPU_CSI0_CCIR_CODE_2 - CSIO CCIR Code Register 2
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* - HW_IPU_CSI0_CCIR_CODE_3 - CSIO CCIR Code Register 3
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* - HW_IPU_CSI0_DI - CSI0 Data Identifier Register
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* - HW_IPU_CSI0_SKIP - CSI0 SKIP Register
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* - HW_IPU_CSIO_CPD_CTRL - CSI0 Compander Control Register
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* - HW_IPU_CSIO_CPD_RC_I - CSI0 Red Component Compander Constants Register <i>
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* - HW_IPU_CSIO_CPD_RS_I - CSI0 Red Component Compander SLOPE Register <i>
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* - HW_IPU_CSIO_CPD_GRC_I - CSI0 GR Component Compander Constants Register <i>
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* - HW_IPU_CSIO_CPD_GRS_I - CSI0 GR Component Compander SLOPE Register <i>
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* - HW_IPU_CSIO_CPD_GBC_I - CSI0 GB Component Compander Constants Register <i>
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* - HW_IPU_CSIO_CPD_GBS_I - CSI0 GB Component Compander SLOPE Register <i>
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* - HW_IPU_CSIO_CPD_BC_I - CSI0 Blue Component Compander Constants Register <i>
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* - HW_IPU_CSIO_CPD_BS_I - CSI0 Blue Component Compander SLOPE Register <i>
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* - HW_IPU_CSI0_CPD_OFFSET1 - CSI0 Compander Offset Register 1
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* - HW_IPU_CSI0_CPD_OFFSET2 - CSI0 Compander Offset Register 2
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* - HW_IPU_CSI1_SENS_CONF - CSI1 Sensor Configuration Register
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* - HW_IPU_CSI1_SENS_FRM_SIZE - CSI1 Sense Frame Size Register
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* - HW_IPU_CSI1_ACT_FRM_SIZE - CSI1 Actual Frame Size Register
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* - HW_IPU_CSI1_OUT_FRM_CTRL - CSI1 Output Control Register
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* - HW_IPU_CSI1_TST_CTRL - CSI1 Test Control Register
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* - HW_IPU_CSI1_CCIR_CODE_1 - CSI1 CCIR Code Register 1
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* - HW_IPU_CSI1_CCIR_CODE_2 - CSI1 CCIR Code Register 2
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* - HW_IPU_CSI1_CCIR_CODE_3 - CSI1 CCIR Code Register 3
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* - HW_IPU_CSI1_DI - CSI1 Data Identifier Register
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* - HW_IPU_CSI1_SKIP - CSI1 SKIP Register
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* - HW_IPU_CSI1_CPD_CTRL - CSI1 Compander Control Register
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* - HW_IPU_CSI1_CPD_RC_I - CSI1 Red Component Compander Constants Register <i>
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* - HW_IPU_CSI1_CPD_RS_I - CSI1 Red Component Compander SLOPE Register <i>
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* - HW_IPU_CSI1_CPD_GRC_I - CSI1 GR Component Compander Constants Register <i>
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* - HW_IPU_CSI1_CPD_GRS_I - CSI1 GR Component Compander SLOPE Register <i>
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* - HW_IPU_CSI1_CPD_GBC_I - CSI1 GB Component Compander Constants Register <i>
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* - HW_IPU_CSI1_CPD_GBS_I - CSI1 GB Component Compander SLOPE Register <i>
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* - HW_IPU_CSI1_CPD_BC_I - CSI1 Blue Component Compander Constants Register <i>
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* - HW_IPU_CSI1_CPD_BS_I - CSI1 Blue Component Compander SLOPE Register <i>
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* - HW_IPU_CSI1_CPD_OFFSET1 - CSI1 Compander Offset Register 1
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* - HW_IPU_CSI1_CPD_OFFSET2 - CSI1 Compander Offset Register 2
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* - HW_IPU_DI0_GENERAL - DI0 General Register
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* - HW_IPU_DI0_BS_CLKGEN0 - DI0 Base Sync Clock Gen 0 Register
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* - HW_IPU_DI0_BS_CLKGEN1 - DI0 Base Sync Clock Gen 1 Register
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* - HW_IPU_DI0_SW_GEN0_1 - DI0 Sync Wave Gen 1 Register 0
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* - HW_IPU_DI0_SW_GEN0_2 - DI0 Sync Wave Gen 2 Register 0
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* - HW_IPU_DI0_SW_GEN0_3 - DI0 Sync Wave Gen 3 Register 0
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* - HW_IPU_DI0_SW_GEN0_4 - DI0 Sync Wave Gen 4 Register 0
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* - HW_IPU_DI0_SW_GEN0_5 - DI0 Sync Wave Gen 5 Register 0
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* - HW_IPU_DI0_SW_GEN0_6 - DI0 Sync Wave Gen 6 Register 0
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* - HW_IPU_DI0_SW_GEN0_7 - DI0 Sync Wave Gen 7 Register 0
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* - HW_IPU_DI0_SW_GEN0_8 - DI0 Sync Wave Gen 8 Register 0
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* - HW_IPU_DI0_SW_GEN0_9 - DI0 Sync Wave Gen 9 Register 0
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* - HW_IPU_DI0_SW_GEN1_1 - DI0 Sync Wave Gen 1 Register 1
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* - HW_IPU_DI0_SW_GEN1_2 - DI0 Sync Wave Gen 2 Register 1
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* - HW_IPU_DI0_SW_GEN1_3 - DI0 Sync Wave Gen 3 Register 1
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* - HW_IPU_DI0_SW_GEN1_4 - DI0 Sync Wave Gen 4 Register 1
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* - HW_IPU_DI0_SW_GEN1_5 - DI0 Sync Wave Gen 5 Register 1
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* - HW_IPU_DI0_SW_GEN1_6 - DI0 Sync Wave Gen 6 Register 1
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* - HW_IPU_DI0_SW_GEN1_7 - DI0 Sync Wave Gen 7 Register 1
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* - HW_IPU_DI0_SW_GEN1_8 - DI0 Sync Wave Gen 8 Register 1
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* - HW_IPU_DI0_SW_GEN1_9 - DI0 Sync Wave Gen 9 Register 1
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* - HW_IPU_DI0_SYNC_AS_GEN - DI0 Sync Assistance Gen Register
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* - HW_IPU_DI0_DW_GEN_I - DI0 Data Wave Gen <i> Register
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* - HW_IPU_DI0_DW_SET0_I - DI0 Data Wave Set 0 <i> Register
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* - HW_IPU_DI0_DW_SET1_I - DI0 Data Wave Set 1 <i> Register
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* - HW_IPU_DI0_DW_SET2_I - DI0 Data Wave Set 2 <i> Register
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* - HW_IPU_DI0_DW_SET3_I - DI0 Data Wave Set 3 <i> Register
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* - HW_IPU_DI0_STP_REP_I - DI0 Step Repeat <i> Registers
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* - HW_IPU_DI0_STP_REP_9 - DI0 Step Repeat 9 Registers
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* - HW_IPU_DI0_SER_CONF - DI0 Serial Display Control Register
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* - HW_IPU_DI0_SSC - DI0 Special Signals Control Register
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* - HW_IPU_DI0_POL - DI0 Polarity Register
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* - HW_IPU_DI0_AW0 - DI0 Active Window 0 Register
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* - HW_IPU_DI0_AW1 - DI0 Active Window 1 Register
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* - HW_IPU_DI0_SCR_CONF - DI0 Screen Configuration Register
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* - HW_IPU_DI0_STAT - DI0 Status Register
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* - HW_IPU_DI1_GENERAL - DI1General Register
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* - HW_IPU_DI1_BS_CLKGEN0 - DI1 Base Sync Clock Gen 0 Register
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* - HW_IPU_DI1_BS_CLKGEN1 - DI1 Base Sync Clock Gen 1 Register
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* - HW_IPU_DI1_SW_GEN0_1 - DI1 Sync Wave Gen 1 Register 0
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* - HW_IPU_DI1_SW_GEN0_2 - DI1 Sync Wave Gen 2 Register 0
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* - HW_IPU_DI1_SW_GEN0_3 - DI1 Sync Wave Gen 3 Register 0
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* - HW_IPU_DI1_SW_GEN0_4 - DI1 Sync Wave Gen 4 Register 0
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* - HW_IPU_DI1_SW_GEN0_5 - DI1 Sync Wave Gen 5 Register 0
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* - HW_IPU_DI1_SW_GEN0_6 - DI1 Sync Wave Gen 6 Register 0
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* - HW_IPU_DI1_SW_GEN0_7 - DI1 Sync Wave Gen 7 Register 0
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* - HW_IPU_DI1_SW_GEN0_8 - DI1 Sync Wave Gen 8 Register 0
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* - HW_IPU_DI1_SW_GEN0_9 - DI1Sync Wave Gen 9 Register 0
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* - HW_IPU_DI1_SW_GEN1_1 - DI1 Sync Wave Gen 1 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_2 - DI1 Sync Wave Gen 2 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_3 - DI1 Sync Wave Gen 3 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_4 - DI1 Sync Wave Gen 4 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_5 - DI1 Sync Wave Gen 5 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_6 - DI1 Sync Wave Gen 6 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_7 - DI1Sync Wave Gen 7 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_8 - DI1 Sync Wave Gen 8 Register 1
|
|
* - HW_IPU_DI1_SW_GEN1_9 - DI1 Sync Wave Gen 9 Register 1
|
|
* - HW_IPU_DI1_SYNC_AS_GEN - DI1 Sync Assistance Gen Register
|
|
* - HW_IPU_DI1_DW_GEN_I - DI1 Data Wave Gen <i> Register
|
|
* - HW_IPU_DI1_DW_SET0_I - DI1 Data Wave Set 0 <i> Register
|
|
* - HW_IPU_DI1_DW_SET1_I - DI1 Data Wave Set 1 <i> Register
|
|
* - HW_IPU_DI1_DW_SET2_I - DI1 Data Wave Set 2 <i> Register
|
|
* - HW_IPU_DI1_DW_SET3_I - DI1 Data Wave Set 3 <i> Register
|
|
* - HW_IPU_D1_STP_REP_I - DI1 Step Repeat <i> Registers
|
|
* - HW_IPU_DI1_STP_REP_9 - DI1Step Repeat 9 Registers
|
|
* - HW_IPU_DI1_SER_CONF - DI1 Serial Display Control Register
|
|
* - HW_IPU_DI1_SSC - DI1 Special Signals Control Register
|
|
* - HW_IPU_DI1_POL - DI1 Polarity Register
|
|
* - HW_IPU_DI1_AW0 - DI1Active Window 0 Register
|
|
* - HW_IPU_DI1_AW1 - DI1 Active Window 1 Register
|
|
* - HW_IPU_DI1_SCR_CONF - DI1 Screen Configuration Register
|
|
* - HW_IPU_DI1_STAT - DI1 Status Register
|
|
* - HW_IPU_SMFC_MAP - SMFC Mapping Register
|
|
* - HW_IPU_SMFC_WMC - SMFC Watermark Control Register
|
|
* - HW_IPU_SMFC_BS - SMFC Burst Size Register
|
|
* - HW_IPU_DC_READ_CH_CONF - DC Read Channel Configuration Register
|
|
* - HW_IPU_DC_READ_SH_ADDR - DC Read Channel Start Address Register
|
|
* - HW_IPU_DC_RL0_CH_0 - DC Routine Link Register 0 Channel 0
|
|
* - HW_IPU_DC_RL1_CH_0 - DC Routine Link Register 1 Channel 0
|
|
* - HW_IPU_DC_RL2_CH_0 - DC Routine Link Register2 Channel 0
|
|
* - HW_IPU_DC_RL3_CH_0 - DC Routine Link Registe3 Channel 0
|
|
* - HW_IPU_DC_RL4_CH_0 - DC Routine Link Register 4 Channel 0
|
|
* - HW_IPU_DC_WR_CH_CONF_1 - DC Write Channel 1 Configuration Register
|
|
* - HW_IPU_DC_WR_CH_ADDR_1 - DC Write Channel 1 Address Configuration Register
|
|
* - HW_IPU_DC_RL0_CH_1 - DC Routine Link Register 0 Channel 1
|
|
* - HW_IPU_DC_RL1_CH_1 - DC Routine Link Register 1 Channel 1
|
|
* - HW_IPU_DC_RL2_CH_1 - DC Routine Link Register 2 Channel 1
|
|
* - HW_IPU_DC_RL3_CH_1 - DC Routine Link Register 3 Channel 1
|
|
* - HW_IPU_DC_RL4_CH_1 - DC Routine Link Register 4 Channel 1
|
|
* - HW_IPU_DC_WR_CH_CONF_2 - DC Write Channel 2 Configuration Register
|
|
* - HW_IPU_DC_WR_CH_ADDR_2 - DC Write Channel 2 Address Configuration Register
|
|
* - HW_IPU_DC_RL0_CH_2 - DC Routine Link Register 0 Channel 2
|
|
* - HW_IPU_DC_RL1_CH_2 - DC Routine Link Register 1 Channel 2
|
|
* - HW_IPU_DC_RL2_CH_2 - DC Routine Link Register 2 Channel 2
|
|
* - HW_IPU_DC_RL3_CH_2 - DC Routine Link Register 3 Channel 2
|
|
* - HW_IPU_DC_RL4_CH_2 - DC Routine Link Register 4 Channel 2
|
|
* - HW_IPU_DC_CMD_CH_CONF_3 - DC Command Channel 3 Configuration Register
|
|
* - HW_IPU_DC_CMD_CH_CONF_4 - DC Command Channel 4 Configuration Register
|
|
* - HW_IPU_DC_WR_CH_CONF_5 - DC Write Channel 5Configuration Register
|
|
* - HW_IPU_DC_WR_CH_ADDR_5 - DC Write Channel 5Address Configuration Register
|
|
* - HW_IPU_DC_RL0_CH_5 - DC Routine Link Register 0 Channel 5
|
|
* - HW_IPU_DC_RL1_CH_5 - DC Routine Link Register 1 Channel 5
|
|
* - HW_IPU_DC_RL2_CH_5 - DC Routine Link Register 2 Channel 5
|
|
* - HW_IPU_DC_RL3_CH_5 - DC Routine Link Register3 Channel 5
|
|
* - HW_IPU_DC_RL4_CH_5 - DC Routine Link Register 4 Channel 5
|
|
* - HW_IPU_DC_WR_CH_CONF_6 - DC Write Channel 6 Configuration Register
|
|
* - HW_IPU_DC_WR_CH_ADDR_6 - DC Write Channel 6 Address Configuration Register
|
|
* - HW_IPU_DC_RL0_CH_6 - DC Routine Link Register 0Channel 6
|
|
* - HW_IPU_DC_RL1_CH_6 - DC Routine Link Register 1 Channel 6
|
|
* - HW_IPU_DC_RL2_CH_6 - DC Routine Link Register 2 Channel 6
|
|
* - HW_IPU_DC_RL3_CH_6 - DC Routine Link Register 3 Channel 6
|
|
* - HW_IPU_DC_RL4_CH_6 - DC Routine Link Register 4 Channel 6
|
|
* - HW_IPU_DC_WR_CH_CONF1_8 - DC Write Channel 8 Configuration 1Register
|
|
* - HW_IPU_DC_WR_CH_CONF2_8 - DC Write Channel 8 Configuration 2 Register
|
|
* - HW_IPU_DC_RL1_CH_8 - DC Routine Link Register 1 Channel 8
|
|
* - HW_IPU_DC_RL2_CH_8 - DC Routine Link Register 2 Channel 8
|
|
* - HW_IPU_DC_RL3_CH_8 - DC Routine Link Register 3 Channel 8
|
|
* - HW_IPU_DC_RL4_CH_8 - DC Routine Link Register 4 Channel 8
|
|
* - HW_IPU_DC_RL5_CH_8 - DC Routine Link Register 5 Channel 8
|
|
* - HW_IPU_DC_RL6_CH_8 - DC Routine Link Register 6 Channel 8
|
|
* - HW_IPU_DC_WR_CH_CONF1_9 - DC Write Channel 9 Configuration 1Register
|
|
* - HW_IPU_DC_WR_CH_CONF2_9 - DC Write Channel 9Configuration 2Register
|
|
* - HW_IPU_DC_RL1_CH_9 - DC Routine Link Register 1 Channel 9
|
|
* - HW_IPU_DC_RL2_CH_9 - DC Routine Link Register 2 Channel 9
|
|
* - HW_IPU_DC_RL3_CH_9 - DC Routine Link Register 3Channel 9
|
|
* - HW_IPU_DC_RL4_CH_9 - DC Routine Link Register 4 Channel 9
|
|
* - HW_IPU_DC_RL5_CH_9 - DC Routine Link Register 5 Channel 9
|
|
* - HW_IPU_DC_RL6_CH_9 - DC Routine Link Register 6 Channel 9
|
|
* - HW_IPU_DC_GEN - DC General Register
|
|
* - HW_IPU_DC_DISP_CONF1_0 - DC Display Configuration 1 Register 0
|
|
* - HW_IPU_DC_DISP_CONF1_1 - DC Display Configuration 1 Register 1
|
|
* - HW_IPU_DC_DISP_CONF1_2 - DC Display Configuration 1 Register 2
|
|
* - HW_IPU_DC_DISP_CONF1_3 - DC Display Configuration 1 Register 3
|
|
* - HW_IPU_DC_DISP_CONF2_0 - DC Display Configuration 2 Register 0
|
|
* - HW_IPU_DC_DISP_CONF2_1 - DC Display Configuration 2 Register 1
|
|
* - HW_IPU_DC_DISP_CONF2_2 - DC Display Configuration 2 Register 2
|
|
* - HW_IPU_DC_DISP_CONF2_3 - DC Display Configuration 2 Register 3
|
|
* - HW_IPU_DC_DI0_CONF_1 - DC DI0Configuration Register 1
|
|
* - HW_IPU_DC_DI0_CONF_2 - DC DI0Configuration Register 2
|
|
* - HW_IPU_DC_DI1_CONF_1 - DC DI1Configuration Register 1
|
|
* - HW_IPU_DC_DI1_CONF_2 - DC DI1Configuration Register 2
|
|
* - HW_IPU_DC_MAP_CONF_0 - DC Mapping Configuration Register 0
|
|
* - HW_IPU_DC_MAP_CONF_1 - DC Mapping Configuration Register 1
|
|
* - HW_IPU_DC_MAP_CONF_2 - DC Mapping Configuration Register 2
|
|
* - HW_IPU_DC_MAP_CONF_3 - DC Mapping Configuration Register 3
|
|
* - HW_IPU_DC_MAP_CONF_4 - DC Mapping Configuration Register 4
|
|
* - HW_IPU_DC_MAP_CONF_5 - DC Mapping Configuration Register 5
|
|
* - HW_IPU_DC_MAP_CONF_6 - DC Mapping Configuration Register 6
|
|
* - HW_IPU_DC_MAP_CONF_7 - DC Mapping Configuration Register 7
|
|
* - HW_IPU_DC_MAP_CONF_8 - DC Mapping Configuration Register 8
|
|
* - HW_IPU_DC_MAP_CONF_9 - DC Mapping Configuration Register 9
|
|
* - HW_IPU_DC_MAP_CONF_10 - DC Mapping Configuration Register 10
|
|
* - HW_IPU_DC_MAP_CONF_11 - DC Mapping Configuration Register 11
|
|
* - HW_IPU_DC_MAP_CONF_12 - DC Mapping Configuration Register 12
|
|
* - HW_IPU_DC_MAP_CONF_13 - DC Mapping Configuration Register 13
|
|
* - HW_IPU_DC_MAP_CONF_14 - DC Mapping Configuration Register 14
|
|
* - HW_IPU_DC_MAP_CONF_15 - DC Mapping Configuration Register 15
|
|
* - HW_IPU_DC_MAP_CONF_16 - DC Mapping Configuration Register 16
|
|
* - HW_IPU_DC_MAP_CONF_17 - DC Mapping Configuration Register 17
|
|
* - HW_IPU_DC_MAP_CONF_18 - DC Mapping Configuration Register 18
|
|
* - HW_IPU_DC_MAP_CONF_19 - DC Mapping Configuration Register 19
|
|
* - HW_IPU_DC_MAP_CONF_20 - DC Mapping Configuration Register 20
|
|
* - HW_IPU_DC_MAP_CONF_21 - DC Mapping Configuration Register 21
|
|
* - HW_IPU_DC_MAP_CONF_22 - DC Mapping Configuration Register 22
|
|
* - HW_IPU_DC_MAP_CONF_23 - DC Mapping Configuration Register 23
|
|
* - HW_IPU_DC_MAP_CONF_24 - DC Mapping Configuration Register 24
|
|
* - HW_IPU_DC_MAP_CONF_25 - DC Mapping Configuration Register 25
|
|
* - HW_IPU_DC_MAP_CONF_26 - DC Mapping Configuration Register 26
|
|
* - HW_IPU_DC_UGDE0_0 - DC User General Data Event 0 Register 0
|
|
* - HW_IPU_DC_UGDE0_1 - DC User General Data Event 0 Register 1
|
|
* - HW_IPU_DC_UGDE0_2 - DC User General Data Event 0 Register2
|
|
* - HW_IPU_DC_UGDE0_3 - DC User General Data Event 0 Register 3
|
|
* - HW_IPU_DC_UGDE1_0 - DC User General Data Event 1Register0
|
|
* - HW_IPU_DC_UGDE1_1 - DC User General Data Event 1 Register 1
|
|
* - HW_IPU_DC_UGDE1_2 - DC User General Data Event 1Register 2
|
|
* - HW_IPU_DC_UGDE1_3 - DC User General Data Event 1Register 3
|
|
* - HW_IPU_DC_UGDE2_0 - DC User General Data Event 2 Register 0
|
|
* - HW_IPU_DC_UGDE2_1 - DC User General Data Event 2 Register 1
|
|
* - HW_IPU_DC_UGDE2_2 - DC User General Data Event 2Register 2
|
|
* - HW_IPU_DC_UGDE2_3 - DC User General Data Event 2Register 3
|
|
* - HW_IPU_DC_UGDE3_0 - DC User General Data Event 3Register 0
|
|
* - HW_IPU_DC_UGDE3_1 - DC User General Data Event 3Register 1
|
|
* - HW_IPU_DC_UGDE3_2 - DC User General Data Event 3Register 2
|
|
* - HW_IPU_DC_UGDE3_3 - DC User General Data Event 3Register 2
|
|
* - HW_IPU_DC_LLA0 - DC Low Level Access Control Register 0
|
|
* - HW_IPU_DC_LLA1 - DC Low Level Access Control Register 1
|
|
* - HW_IPU_DC_R_LLA0 - DC Read Low Level Read Access Control Register 0
|
|
* - HW_IPU_DC_R_LLA1 - DC Read Low Level Read Access Control Register1
|
|
* - HW_IPU_DC_WR_CH_ADDR_5_ALT - DC Write Channel 5 Configuration Register
|
|
* - HW_IPU_DC_STAT - DC Status Register
|
|
* - HW_IPU_DMFC_RD_CHAN - DMFC Read Channel Register
|
|
* - HW_IPU_DMFC_WR_CHAN - DMFC Write Channel Register
|
|
* - HW_IPU_DMFC_WR_CHAN_DEF - DMFC Write Channel Definition Register
|
|
* - HW_IPU_DMFC_DP_CHAN - DMFC Display Processor Channel Register
|
|
* - HW_IPU_DMFC_DP_CHAN_DEF - DMFC Display Processor Channel Definition Register
|
|
* - HW_IPU_DMFC_GENERAL_1 - DMFC General 1 Register
|
|
* - HW_IPU_DMFC_GENERAL_2 - DMFC General 2 Register
|
|
* - HW_IPU_DMFC_IC_CTRL - DMFC IC Interface Control Register
|
|
* - HW_IPU_DMFC_WR_CHAN_ALT - DMFC Write Channel Alternate Register
|
|
* - HW_IPU_DMFC_WR_CHAN_DEF_ALT - DMFC Write Channel Definition Alternate Register
|
|
* - HW_IPU_DMFC_DP_CHAN_ALT - DMFC MFC Display Processor Channel Alternate Register
|
|
* - HW_IPU_DMFC_DP_CHAN_DEF_ALT - DMFC Display Channel Definition Alternate Register
|
|
* - HW_IPU_DMFC_GENERAL1_ALT - DMFC General 1 Alternate Register
|
|
* - HW_IPU_DMFC_STAT - DMFC Status Register
|
|
* - HW_IPU_VDI_FSIZE - VDI Field Size Register
|
|
* - HW_IPU_VDI_C - VDI Control Register
|
|
* - HW_IPU_VDI_C2 - VDI Control Register 2
|
|
* - HW_IPU_VDI_CMDP_1 - VDI Combining Parameters Register 1
|
|
* - HW_IPU_VDI_CMDP_2 - VDI Combining Parameters Register 2
|
|
* - HW_IPU_VDI_PS_1 - VDI Plane Size Register 1
|
|
* - HW_IPU_VDI_PS_2 - VDI Plane Size Register 2
|
|
* - HW_IPU_VDI_PS_3 - VDI Plane Size Register 3
|
|
* - HW_IPU_VDI_PS_4 - VDI Plane Size Register 4
|
|
*
|
|
* - hw_ipu_t - Struct containing all module registers.
|
|
*/
|
|
|
|
//! @name Module base addresses
|
|
//@{
|
|
#ifndef REGS_IPU_BASE
|
|
#define HW_IPU_INSTANCE_COUNT (2) //!< Number of instances of the IPU module.
|
|
#define HW_IPU1 (1) //!< Instance number for IPU1.
|
|
#define HW_IPU2 (2) //!< Instance number for IPU2.
|
|
#define REGS_IPU1_BASE (0x02400000) //!< Base address for IPU instance number 1.
|
|
#define REGS_IPU2_BASE (0x02800000) //!< Base address for IPU instance number 2.
|
|
|
|
//! @brief Get the base address of IPU by instance number.
|
|
//! @param x IPU instance number, from 1 through 2.
|
|
#define REGS_IPU_BASE(x) ( (x) == HW_IPU1 ? REGS_IPU1_BASE : (x) == HW_IPU2 ? REGS_IPU2_BASE : 0x00d00000)
|
|
|
|
//! @brief Get the instance number given a base address.
|
|
//! @param b Base address for an instance of IPU.
|
|
#define REGS_IPU_INSTANCE(b) ( (b) == REGS_IPU1_BASE ? HW_IPU1 : (b) == REGS_IPU2_BASE ? HW_IPU2 : 0)
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CONF - Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CONF - Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_conf_bitfields
|
|
{
|
|
unsigned CSI0_EN : 1; //!< [0] Camera Sensor Interface 0 Enable bit
|
|
unsigned CSI1_EN : 1; //!< [1] Camera Sensor Interface 1 Enable bit
|
|
unsigned IC_EN : 1; //!< [2] Image Conversion Sub-Block Enable bit
|
|
unsigned IRT_EN : 1; //!< [3] Image Rotation Sub-Block Enable bit
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved
|
|
unsigned DP_EN : 1; //!< [5] Display processor Sub-block Enable bit
|
|
unsigned DI0_EN : 1; //!< [6] Display interface Sub-block 0 Enable bit
|
|
unsigned DI1_EN : 1; //!< [7] Display Interface Sub-block 1 Enable bit
|
|
unsigned SMFC_EN : 1; //!< [8] Sensor's Multi FIFO Controller Sub-block (SMFC) Enable bit
|
|
unsigned DC_EN : 1; //!< [9] Display Controller sub-block (DC) Enable bit
|
|
unsigned DMFC_EN : 1; //!< [10] Display's Multi FIFO Controller sub-block (DMFC) Enable bit
|
|
unsigned SISG_EN : 1; //!< [11] Still Image Synchronization Generator (SISG) Enable bit
|
|
unsigned VDI_EN : 1; //!< [12] VDI enable bit.
|
|
unsigned RESERVED1 : 3; //!< [15:13] Reserved, should be cleared.
|
|
unsigned IPU_DIAGBUS_MODE : 5; //!< [20:16] IPU diagnostic bus mode.
|
|
unsigned IPU_DIAGBUS_ON : 1; //!< [21] IPU Diagnostics bus on
|
|
unsigned IDMAC_DISABLE : 1; //!< [22] Image DMA controller (IDMAC) disable bit.
|
|
unsigned RESERVED2 : 2; //!< [24:23] Reserved.
|
|
unsigned IC_DMFC_SEL : 1; //!< [25] IC to DMFC select
|
|
unsigned IC_DMFC_SYNC : 1; //!< [26] IC to DMFC Sync flow
|
|
unsigned VDI_DMFC_SYNC : 1; //!< [27] This bit enables the direct path VDI C -> IC_VF -> DMFC for sync flow.
|
|
unsigned CSI0_DATA_SOURCE : 1; //!< [28] CSI0 data Source
|
|
unsigned CSI1_DATA_SOURCE : 1; //!< [29] CSI1 data Source
|
|
unsigned IC_INPUT : 1; //!< [30] IC Input select bit.
|
|
unsigned CSI_SEL : 1; //!< [31] CSI select bit; This bit selects manually between the 2 CSI's.
|
|
} B;
|
|
} hw_ipu_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CONF(x) (*(volatile hw_ipu_conf_t *) HW_IPU_CONF_ADDR(x))
|
|
#define HW_IPU_CONF_RD(x) (HW_IPU_CONF(x).U)
|
|
#define HW_IPU_CONF_WR(x, v) (HW_IPU_CONF(x).U = (v))
|
|
#define HW_IPU_CONF_SET(x, v) (HW_IPU_CONF_WR(x, HW_IPU_CONF_RD(x) | (v)))
|
|
#define HW_IPU_CONF_CLR(x, v) (HW_IPU_CONF_WR(x, HW_IPU_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_CONF_TOG(x, v) (HW_IPU_CONF_WR(x, HW_IPU_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CONF, field CSI0_EN[0] (RW)
|
|
*
|
|
* Camera Sensor Interface 0 Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - CSI0 is disabled
|
|
* - 1 - CSI0 is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_CSI0_EN (0) //!< Bit position for IPU_CONF_CSI0_EN.
|
|
#define BM_IPU_CONF_CSI0_EN (0x00000001) //!< Bit mask for IPU_CONF_CSI0_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_CSI0_EN from a register value.
|
|
#define BG_IPU_CONF_CSI0_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_CSI0_EN) >> BP_IPU_CONF_CSI0_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_CSI0_EN.
|
|
#define BF_IPU_CONF_CSI0_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_CSI0_EN) & BM_IPU_CONF_CSI0_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_EN field to a new value.
|
|
#define BW_IPU_CONF_CSI0_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_CSI0_EN) | BF_IPU_CONF_CSI0_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field CSI1_EN[1] (RW)
|
|
*
|
|
* Camera Sensor Interface 1 Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - CSI1 is disabled
|
|
* - 1 - CSI1 is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_CSI1_EN (1) //!< Bit position for IPU_CONF_CSI1_EN.
|
|
#define BM_IPU_CONF_CSI1_EN (0x00000002) //!< Bit mask for IPU_CONF_CSI1_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_CSI1_EN from a register value.
|
|
#define BG_IPU_CONF_CSI1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_CSI1_EN) >> BP_IPU_CONF_CSI1_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_CSI1_EN.
|
|
#define BF_IPU_CONF_CSI1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_CSI1_EN) & BM_IPU_CONF_CSI1_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_EN field to a new value.
|
|
#define BW_IPU_CONF_CSI1_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_CSI1_EN) | BF_IPU_CONF_CSI1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IC_EN[2] (RW)
|
|
*
|
|
* Image Conversion Sub-Block Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - IC is disabled
|
|
* - 1 - IC is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IC_EN (2) //!< Bit position for IPU_CONF_IC_EN.
|
|
#define BM_IPU_CONF_IC_EN (0x00000004) //!< Bit mask for IPU_CONF_IC_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_IC_EN from a register value.
|
|
#define BG_IPU_CONF_IC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IC_EN) >> BP_IPU_CONF_IC_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IC_EN.
|
|
#define BF_IPU_CONF_IC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IC_EN) & BM_IPU_CONF_IC_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_EN field to a new value.
|
|
#define BW_IPU_CONF_IC_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IC_EN) | BF_IPU_CONF_IC_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IRT_EN[3] (RW)
|
|
*
|
|
* Image Rotation Sub-Block Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - IRT is disabled
|
|
* - 1 - IRT is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IRT_EN (3) //!< Bit position for IPU_CONF_IRT_EN.
|
|
#define BM_IPU_CONF_IRT_EN (0x00000008) //!< Bit mask for IPU_CONF_IRT_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_IRT_EN from a register value.
|
|
#define BG_IPU_CONF_IRT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IRT_EN) >> BP_IPU_CONF_IRT_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IRT_EN.
|
|
#define BF_IPU_CONF_IRT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IRT_EN) & BM_IPU_CONF_IRT_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IRT_EN field to a new value.
|
|
#define BW_IPU_CONF_IRT_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IRT_EN) | BF_IPU_CONF_IRT_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field DP_EN[5] (RW)
|
|
*
|
|
* Display processor Sub-block Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - DP is disabled
|
|
* - 1 - DP is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_DP_EN (5) //!< Bit position for IPU_CONF_DP_EN.
|
|
#define BM_IPU_CONF_DP_EN (0x00000020) //!< Bit mask for IPU_CONF_DP_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_DP_EN from a register value.
|
|
#define BG_IPU_CONF_DP_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_DP_EN) >> BP_IPU_CONF_DP_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_DP_EN.
|
|
#define BF_IPU_CONF_DP_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_DP_EN) & BM_IPU_CONF_DP_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_EN field to a new value.
|
|
#define BW_IPU_CONF_DP_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_DP_EN) | BF_IPU_CONF_DP_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field DI0_EN[6] (RW)
|
|
*
|
|
* Display interface Sub-block 0 Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - DI0 is disabled
|
|
* - 1 - DI0 is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_DI0_EN (6) //!< Bit position for IPU_CONF_DI0_EN.
|
|
#define BM_IPU_CONF_DI0_EN (0x00000040) //!< Bit mask for IPU_CONF_DI0_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_DI0_EN from a register value.
|
|
#define BG_IPU_CONF_DI0_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_DI0_EN) >> BP_IPU_CONF_DI0_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_DI0_EN.
|
|
#define BF_IPU_CONF_DI0_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_DI0_EN) & BM_IPU_CONF_DI0_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_EN field to a new value.
|
|
#define BW_IPU_CONF_DI0_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_DI0_EN) | BF_IPU_CONF_DI0_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field DI1_EN[7] (RW)
|
|
*
|
|
* Display Interface Sub-block 1 Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - DI1 is disabled
|
|
* - 1 - DI1 is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_DI1_EN (7) //!< Bit position for IPU_CONF_DI1_EN.
|
|
#define BM_IPU_CONF_DI1_EN (0x00000080) //!< Bit mask for IPU_CONF_DI1_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_DI1_EN from a register value.
|
|
#define BG_IPU_CONF_DI1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_DI1_EN) >> BP_IPU_CONF_DI1_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_DI1_EN.
|
|
#define BF_IPU_CONF_DI1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_DI1_EN) & BM_IPU_CONF_DI1_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_EN field to a new value.
|
|
#define BW_IPU_CONF_DI1_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_DI1_EN) | BF_IPU_CONF_DI1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field SMFC_EN[8] (RW)
|
|
*
|
|
* Sensor's Multi FIFO Controller Sub-block (SMFC) Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - SMFC is disabled
|
|
* - 1 - SMFC is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_SMFC_EN (8) //!< Bit position for IPU_CONF_SMFC_EN.
|
|
#define BM_IPU_CONF_SMFC_EN (0x00000100) //!< Bit mask for IPU_CONF_SMFC_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_SMFC_EN from a register value.
|
|
#define BG_IPU_CONF_SMFC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_SMFC_EN) >> BP_IPU_CONF_SMFC_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_SMFC_EN.
|
|
#define BF_IPU_CONF_SMFC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_SMFC_EN) & BM_IPU_CONF_SMFC_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC_EN field to a new value.
|
|
#define BW_IPU_CONF_SMFC_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_SMFC_EN) | BF_IPU_CONF_SMFC_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field DC_EN[9] (RW)
|
|
*
|
|
* Display Controller sub-block (DC) Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - DC is disabled
|
|
* - 1 - DC is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_DC_EN (9) //!< Bit position for IPU_CONF_DC_EN.
|
|
#define BM_IPU_CONF_DC_EN (0x00000200) //!< Bit mask for IPU_CONF_DC_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_DC_EN from a register value.
|
|
#define BG_IPU_CONF_DC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_DC_EN) >> BP_IPU_CONF_DC_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_DC_EN.
|
|
#define BF_IPU_CONF_DC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_DC_EN) & BM_IPU_CONF_DC_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_EN field to a new value.
|
|
#define BW_IPU_CONF_DC_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_DC_EN) | BF_IPU_CONF_DC_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field DMFC_EN[10] (RW)
|
|
*
|
|
* Display's Multi FIFO Controller sub-block (DMFC) Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - DMFC is disabled
|
|
* - 1 - DMFC is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_DMFC_EN (10) //!< Bit position for IPU_CONF_DMFC_EN.
|
|
#define BM_IPU_CONF_DMFC_EN (0x00000400) //!< Bit mask for IPU_CONF_DMFC_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_DMFC_EN from a register value.
|
|
#define BG_IPU_CONF_DMFC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_DMFC_EN) >> BP_IPU_CONF_DMFC_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_DMFC_EN.
|
|
#define BF_IPU_CONF_DMFC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_DMFC_EN) & BM_IPU_CONF_DMFC_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_EN field to a new value.
|
|
#define BW_IPU_CONF_DMFC_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_DMFC_EN) | BF_IPU_CONF_DMFC_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field SISG_EN[11] (RW)
|
|
*
|
|
* Still Image Synchronization Generator (SISG) Enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - SISG is disabled
|
|
* - 1 - SISG is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_SISG_EN (11) //!< Bit position for IPU_CONF_SISG_EN.
|
|
#define BM_IPU_CONF_SISG_EN (0x00000800) //!< Bit mask for IPU_CONF_SISG_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_SISG_EN from a register value.
|
|
#define BG_IPU_CONF_SISG_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_SISG_EN) >> BP_IPU_CONF_SISG_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_SISG_EN.
|
|
#define BF_IPU_CONF_SISG_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_SISG_EN) & BM_IPU_CONF_SISG_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SISG_EN field to a new value.
|
|
#define BW_IPU_CONF_SISG_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_SISG_EN) | BF_IPU_CONF_SISG_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field VDI_EN[12] (RW)
|
|
*
|
|
* VDI enable bit. This bit must be cleared if the ISP_EN bit is set.
|
|
*
|
|
* Values:
|
|
* - 0 - VDI C is disabled
|
|
* - 1 - VDI C is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_VDI_EN (12) //!< Bit position for IPU_CONF_VDI_EN.
|
|
#define BM_IPU_CONF_VDI_EN (0x00001000) //!< Bit mask for IPU_CONF_VDI_EN.
|
|
|
|
//! @brief Get value of IPU_CONF_VDI_EN from a register value.
|
|
#define BG_IPU_CONF_VDI_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_VDI_EN) >> BP_IPU_CONF_VDI_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_VDI_EN.
|
|
#define BF_IPU_CONF_VDI_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_VDI_EN) & BM_IPU_CONF_VDI_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_EN field to a new value.
|
|
#define BW_IPU_CONF_VDI_EN(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_VDI_EN) | BF_IPU_CONF_VDI_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IPU_DIAGBUS_MODE[20:16] (RW)
|
|
*
|
|
* IPU diagnostic bus mode. This 5 bits select one of 16 groups of signals to be routed to the IPU's
|
|
* diagnostics bus 00000 Route group 0 to the IPU's diagnostics bus 00001 Route group 1 to the IPU's
|
|
* diagnostics bus 01111 Route group 15 to the IPU's diagnostics bus 10000 Route group 16 to the
|
|
* IPU's diagnostics bus 10001 Route group 17 to the IPU's diagnostics bus 10010-11111 Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IPU_DIAGBUS_MODE (16) //!< Bit position for IPU_CONF_IPU_DIAGBUS_MODE.
|
|
#define BM_IPU_CONF_IPU_DIAGBUS_MODE (0x001f0000) //!< Bit mask for IPU_CONF_IPU_DIAGBUS_MODE.
|
|
|
|
//! @brief Get value of IPU_CONF_IPU_DIAGBUS_MODE from a register value.
|
|
#define BG_IPU_CONF_IPU_DIAGBUS_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IPU_DIAGBUS_MODE) >> BP_IPU_CONF_IPU_DIAGBUS_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IPU_DIAGBUS_MODE.
|
|
#define BF_IPU_CONF_IPU_DIAGBUS_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IPU_DIAGBUS_MODE) & BM_IPU_CONF_IPU_DIAGBUS_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_DIAGBUS_MODE field to a new value.
|
|
#define BW_IPU_CONF_IPU_DIAGBUS_MODE(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IPU_DIAGBUS_MODE) | BF_IPU_CONF_IPU_DIAGBUS_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IPU_DIAGBUS_ON[21] (RW)
|
|
*
|
|
* IPU Diagnostics bus on This bit is connected to the IPU's output. it can be used by the SoC in
|
|
* order to control the IOMUX and bring the IPU's diagnostics bus to the SoC's pins.
|
|
*
|
|
* Values:
|
|
* - 0 - diagnostics bus is off
|
|
* - 1 - diagnostics bus is on
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IPU_DIAGBUS_ON (21) //!< Bit position for IPU_CONF_IPU_DIAGBUS_ON.
|
|
#define BM_IPU_CONF_IPU_DIAGBUS_ON (0x00200000) //!< Bit mask for IPU_CONF_IPU_DIAGBUS_ON.
|
|
|
|
//! @brief Get value of IPU_CONF_IPU_DIAGBUS_ON from a register value.
|
|
#define BG_IPU_CONF_IPU_DIAGBUS_ON(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IPU_DIAGBUS_ON) >> BP_IPU_CONF_IPU_DIAGBUS_ON)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IPU_DIAGBUS_ON.
|
|
#define BF_IPU_CONF_IPU_DIAGBUS_ON(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IPU_DIAGBUS_ON) & BM_IPU_CONF_IPU_DIAGBUS_ON)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_DIAGBUS_ON field to a new value.
|
|
#define BW_IPU_CONF_IPU_DIAGBUS_ON(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IPU_DIAGBUS_ON) | BF_IPU_CONF_IPU_DIAGBUS_ON(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IDMAC_DISABLE[22] (RW)
|
|
*
|
|
* Image DMA controller (IDMAC) disable bit. This bit allows the user to turn off the clock of the
|
|
* IDMAC if the use case permits it. By default the IDMAC is enabled.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC is enabled
|
|
* - 1 - IDMAC is disabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IDMAC_DISABLE (22) //!< Bit position for IPU_CONF_IDMAC_DISABLE.
|
|
#define BM_IPU_CONF_IDMAC_DISABLE (0x00400000) //!< Bit mask for IPU_CONF_IDMAC_DISABLE.
|
|
|
|
//! @brief Get value of IPU_CONF_IDMAC_DISABLE from a register value.
|
|
#define BG_IPU_CONF_IDMAC_DISABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IDMAC_DISABLE) >> BP_IPU_CONF_IDMAC_DISABLE)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IDMAC_DISABLE.
|
|
#define BF_IPU_CONF_IDMAC_DISABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IDMAC_DISABLE) & BM_IPU_CONF_IDMAC_DISABLE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_DISABLE field to a new value.
|
|
#define BW_IPU_CONF_IDMAC_DISABLE(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IDMAC_DISABLE) | BF_IPU_CONF_IDMAC_DISABLE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IC_DMFC_SEL[25] (RW)
|
|
*
|
|
* IC to DMFC select Selects the DMAIC_1 (channel 21) channel's connectivity between the IC and the
|
|
* DMFC
|
|
*
|
|
* Values:
|
|
* - 0 - DMAIC_1 (channel 21) is routed to the IDMAC
|
|
* - 1 - DMAIC_1 (channel 21) is routed to DMFC In case DMFC was selected the IDMAC_CH_EN[21] must be clear.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IC_DMFC_SEL (25) //!< Bit position for IPU_CONF_IC_DMFC_SEL.
|
|
#define BM_IPU_CONF_IC_DMFC_SEL (0x02000000) //!< Bit mask for IPU_CONF_IC_DMFC_SEL.
|
|
|
|
//! @brief Get value of IPU_CONF_IC_DMFC_SEL from a register value.
|
|
#define BG_IPU_CONF_IC_DMFC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IC_DMFC_SEL) >> BP_IPU_CONF_IC_DMFC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IC_DMFC_SEL.
|
|
#define BF_IPU_CONF_IC_DMFC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IC_DMFC_SEL) & BM_IPU_CONF_IC_DMFC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_DMFC_SEL field to a new value.
|
|
#define BW_IPU_CONF_IC_DMFC_SEL(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IC_DMFC_SEL) | BF_IPU_CONF_IC_DMFC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IC_DMFC_SYNC[26] (RW)
|
|
*
|
|
* IC to DMFC Sync flow This bit defines if the direct flow between IC to DMFC is synchronous or
|
|
* asynchronous
|
|
*
|
|
* Values:
|
|
* - 0 - async flow
|
|
* - 1 - Sync flow
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IC_DMFC_SYNC (26) //!< Bit position for IPU_CONF_IC_DMFC_SYNC.
|
|
#define BM_IPU_CONF_IC_DMFC_SYNC (0x04000000) //!< Bit mask for IPU_CONF_IC_DMFC_SYNC.
|
|
|
|
//! @brief Get value of IPU_CONF_IC_DMFC_SYNC from a register value.
|
|
#define BG_IPU_CONF_IC_DMFC_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IC_DMFC_SYNC) >> BP_IPU_CONF_IC_DMFC_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IC_DMFC_SYNC.
|
|
#define BF_IPU_CONF_IC_DMFC_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IC_DMFC_SYNC) & BM_IPU_CONF_IC_DMFC_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_DMFC_SYNC field to a new value.
|
|
#define BW_IPU_CONF_IC_DMFC_SYNC(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IC_DMFC_SYNC) | BF_IPU_CONF_IC_DMFC_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field VDI_DMFC_SYNC[27] (RW)
|
|
*
|
|
* This bit enables the direct path VDI C -> IC_VF -> DMFC for sync flow. If this bit is set
|
|
* IC_DMFC_SEL must be set.
|
|
*
|
|
* Values:
|
|
* - 0 - the flow is disabled
|
|
* - 1 - the flow is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_VDI_DMFC_SYNC (27) //!< Bit position for IPU_CONF_VDI_DMFC_SYNC.
|
|
#define BM_IPU_CONF_VDI_DMFC_SYNC (0x08000000) //!< Bit mask for IPU_CONF_VDI_DMFC_SYNC.
|
|
|
|
//! @brief Get value of IPU_CONF_VDI_DMFC_SYNC from a register value.
|
|
#define BG_IPU_CONF_VDI_DMFC_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_VDI_DMFC_SYNC) >> BP_IPU_CONF_VDI_DMFC_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_VDI_DMFC_SYNC.
|
|
#define BF_IPU_CONF_VDI_DMFC_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_VDI_DMFC_SYNC) & BM_IPU_CONF_VDI_DMFC_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_DMFC_SYNC field to a new value.
|
|
#define BW_IPU_CONF_VDI_DMFC_SYNC(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_VDI_DMFC_SYNC) | BF_IPU_CONF_VDI_DMFC_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field CSI0_DATA_SOURCE[28] (RW)
|
|
*
|
|
* CSI0 data Source This bit selects what is the data source for the CSI0. This is a static mux that
|
|
* should not be changed while CSI0 is working. Data is handles differently if the source is MCT
|
|
* (MIPI) or parallel interface.
|
|
*
|
|
* Values:
|
|
* - 0 - Parallel interface is connected to CSI0
|
|
* - 1 - MCT (MIPI) is connected to CSI0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_CSI0_DATA_SOURCE (28) //!< Bit position for IPU_CONF_CSI0_DATA_SOURCE.
|
|
#define BM_IPU_CONF_CSI0_DATA_SOURCE (0x10000000) //!< Bit mask for IPU_CONF_CSI0_DATA_SOURCE.
|
|
|
|
//! @brief Get value of IPU_CONF_CSI0_DATA_SOURCE from a register value.
|
|
#define BG_IPU_CONF_CSI0_DATA_SOURCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_CSI0_DATA_SOURCE) >> BP_IPU_CONF_CSI0_DATA_SOURCE)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_CSI0_DATA_SOURCE.
|
|
#define BF_IPU_CONF_CSI0_DATA_SOURCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_CSI0_DATA_SOURCE) & BM_IPU_CONF_CSI0_DATA_SOURCE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DATA_SOURCE field to a new value.
|
|
#define BW_IPU_CONF_CSI0_DATA_SOURCE(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_CSI0_DATA_SOURCE) | BF_IPU_CONF_CSI0_DATA_SOURCE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field CSI1_DATA_SOURCE[29] (RW)
|
|
*
|
|
* CSI1 data Source This bit selects what is the data source for the CSI1. This is a static mux that
|
|
* should not be changed while CSI1 is working. Data is handles differently if the source is MCT
|
|
* (MIPI) or parallel interface.
|
|
*
|
|
* Values:
|
|
* - 0 - Parallel interface is connected to CSI1
|
|
* - 1 - MCT (MIPI) is connected to CSI1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_CSI1_DATA_SOURCE (29) //!< Bit position for IPU_CONF_CSI1_DATA_SOURCE.
|
|
#define BM_IPU_CONF_CSI1_DATA_SOURCE (0x20000000) //!< Bit mask for IPU_CONF_CSI1_DATA_SOURCE.
|
|
|
|
//! @brief Get value of IPU_CONF_CSI1_DATA_SOURCE from a register value.
|
|
#define BG_IPU_CONF_CSI1_DATA_SOURCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_CSI1_DATA_SOURCE) >> BP_IPU_CONF_CSI1_DATA_SOURCE)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_CSI1_DATA_SOURCE.
|
|
#define BF_IPU_CONF_CSI1_DATA_SOURCE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_CSI1_DATA_SOURCE) & BM_IPU_CONF_CSI1_DATA_SOURCE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_DATA_SOURCE field to a new value.
|
|
#define BW_IPU_CONF_CSI1_DATA_SOURCE(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_CSI1_DATA_SOURCE) | BF_IPU_CONF_CSI1_DATA_SOURCE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field IC_INPUT[30] (RW)
|
|
*
|
|
* IC Input select bit. This bit selects manually between the 2 inputs to the IC
|
|
*
|
|
* Values:
|
|
* - 1 - VDI
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_IC_INPUT (30) //!< Bit position for IPU_CONF_IC_INPUT.
|
|
#define BM_IPU_CONF_IC_INPUT (0x40000000) //!< Bit mask for IPU_CONF_IC_INPUT.
|
|
|
|
//! @brief Get value of IPU_CONF_IC_INPUT from a register value.
|
|
#define BG_IPU_CONF_IC_INPUT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_IC_INPUT) >> BP_IPU_CONF_IC_INPUT)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_IC_INPUT.
|
|
#define BF_IPU_CONF_IC_INPUT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_IC_INPUT) & BM_IPU_CONF_IC_INPUT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_INPUT field to a new value.
|
|
#define BW_IPU_CONF_IC_INPUT(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_IC_INPUT) | BF_IPU_CONF_IC_INPUT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CONF, field CSI_SEL[31] (RW)
|
|
*
|
|
* CSI select bit; This bit selects manually between the 2 CSI's. This bit defines which CSI is the
|
|
* input to the IC. This bit is effective only if IC_INPUT is bit cleared
|
|
*
|
|
* Values:
|
|
* - 0 - CSI0 is selected
|
|
* - 1 - CSI1 is selected
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CONF_CSI_SEL (31) //!< Bit position for IPU_CONF_CSI_SEL.
|
|
#define BM_IPU_CONF_CSI_SEL (0x80000000) //!< Bit mask for IPU_CONF_CSI_SEL.
|
|
|
|
//! @brief Get value of IPU_CONF_CSI_SEL from a register value.
|
|
#define BG_IPU_CONF_CSI_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CONF_CSI_SEL) >> BP_IPU_CONF_CSI_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_CONF_CSI_SEL.
|
|
#define BF_IPU_CONF_CSI_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CONF_CSI_SEL) & BM_IPU_CONF_CSI_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI_SEL field to a new value.
|
|
#define BW_IPU_CONF_CSI_SEL(x, v) (HW_IPU_CONF_WR(x, (HW_IPU_CONF_RD(x) & ~BM_IPU_CONF_CSI_SEL) | BF_IPU_CONF_CSI_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SISG_CTRL0 - SISG Control 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SISG_CTRL0 - SISG Control 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_sisg_ctrl0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sisg_ctrl0_bitfields
|
|
{
|
|
unsigned VSYNC_RST_CNT : 1; //!< [0] VSYNC Resets counters
|
|
unsigned NO_VSYNC_2_STRT_CNT : 3; //!< [3:1] VSYCs to Start Counter
|
|
unsigned VAL_STOP_SISG_COUNTER : 25; //!< [28:4] SISG Stop Counters value.
|
|
unsigned MCU_ACTV_TRIG : 1; //!< [29] Reserved, should be cleared.
|
|
unsigned EXT_ACTV : 1; //!< [30] External Active
|
|
unsigned RESERVED0 : 1; //!< [31] Reserved
|
|
} B;
|
|
} hw_ipu_sisg_ctrl0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SISG_CTRL0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SISG_CTRL0_ADDR(x) (REGS_IPU_BASE(x) + 0x4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SISG_CTRL0(x) (*(volatile hw_ipu_sisg_ctrl0_t *) HW_IPU_SISG_CTRL0_ADDR(x))
|
|
#define HW_IPU_SISG_CTRL0_RD(x) (HW_IPU_SISG_CTRL0(x).U)
|
|
#define HW_IPU_SISG_CTRL0_WR(x, v) (HW_IPU_SISG_CTRL0(x).U = (v))
|
|
#define HW_IPU_SISG_CTRL0_SET(x, v) (HW_IPU_SISG_CTRL0_WR(x, HW_IPU_SISG_CTRL0_RD(x) | (v)))
|
|
#define HW_IPU_SISG_CTRL0_CLR(x, v) (HW_IPU_SISG_CTRL0_WR(x, HW_IPU_SISG_CTRL0_RD(x) & ~(v)))
|
|
#define HW_IPU_SISG_CTRL0_TOG(x, v) (HW_IPU_SISG_CTRL0_WR(x, HW_IPU_SISG_CTRL0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SISG_CTRL0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SISG_CTRL0, field VSYNC_RST_CNT[0] (RW)
|
|
*
|
|
* VSYNC Resets counters Defines if the counters are stooped following VSYNC or when the counters
|
|
* reach a pre defined value (VAL_STOP_SISG_COUNTER)
|
|
*
|
|
* Values:
|
|
* - 0 - The counters are stooped when the counters reach the VAL_STOP_SISG_COUNTER value.
|
|
* - 1 - The counters are stopped at VSYNC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL0_VSYNC_RST_CNT (0) //!< Bit position for IPU_SISG_CTRL0_VSYNC_RST_CNT.
|
|
#define BM_IPU_SISG_CTRL0_VSYNC_RST_CNT (0x00000001) //!< Bit mask for IPU_SISG_CTRL0_VSYNC_RST_CNT.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL0_VSYNC_RST_CNT from a register value.
|
|
#define BG_IPU_SISG_CTRL0_VSYNC_RST_CNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL0_VSYNC_RST_CNT) >> BP_IPU_SISG_CTRL0_VSYNC_RST_CNT)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL0_VSYNC_RST_CNT.
|
|
#define BF_IPU_SISG_CTRL0_VSYNC_RST_CNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL0_VSYNC_RST_CNT) & BM_IPU_SISG_CTRL0_VSYNC_RST_CNT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VSYNC_RST_CNT field to a new value.
|
|
#define BW_IPU_SISG_CTRL0_VSYNC_RST_CNT(x, v) (HW_IPU_SISG_CTRL0_WR(x, (HW_IPU_SISG_CTRL0_RD(x) & ~BM_IPU_SISG_CTRL0_VSYNC_RST_CNT) | BF_IPU_SISG_CTRL0_VSYNC_RST_CNT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SISG_CTRL0, field NO_VSYNC_2_STRT_CNT[3:1] (RW)
|
|
*
|
|
* VSYCs to Start Counter This bits define how many VSYNCs signals will be counter before activating
|
|
* the SISG counters. If set to 0 starts immediately. If set to N (1..7) starts after N VSYNCs.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT (1) //!< Bit position for IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT.
|
|
#define BM_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT (0x0000000e) //!< Bit mask for IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT from a register value.
|
|
#define BG_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT) >> BP_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT.
|
|
#define BF_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT) & BM_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NO_VSYNC_2_STRT_CNT field to a new value.
|
|
#define BW_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT(x, v) (HW_IPU_SISG_CTRL0_WR(x, (HW_IPU_SISG_CTRL0_RD(x) & ~BM_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT) | BF_IPU_SISG_CTRL0_NO_VSYNC_2_STRT_CNT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SISG_CTRL0, field VAL_STOP_SISG_COUNTER[28:4] (RW)
|
|
*
|
|
* SISG Stop Counters value. This is a predefined value that stops the SISG counters. The user
|
|
* should write to this field the N-1 value of the desired value.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER (4) //!< Bit position for IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER.
|
|
#define BM_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER (0x1ffffff0) //!< Bit mask for IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER from a register value.
|
|
#define BG_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER) >> BP_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER.
|
|
#define BF_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER) & BM_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VAL_STOP_SISG_COUNTER field to a new value.
|
|
#define BW_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER(x, v) (HW_IPU_SISG_CTRL0_WR(x, (HW_IPU_SISG_CTRL0_RD(x) & ~BM_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER) | BF_IPU_SISG_CTRL0_VAL_STOP_SISG_COUNTER(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SISG_CTRL0, field MCU_ACTV_TRIG[29] (RW)
|
|
*
|
|
* Reserved, should be cleared.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL0_MCU_ACTV_TRIG (29) //!< Bit position for IPU_SISG_CTRL0_MCU_ACTV_TRIG.
|
|
#define BM_IPU_SISG_CTRL0_MCU_ACTV_TRIG (0x20000000) //!< Bit mask for IPU_SISG_CTRL0_MCU_ACTV_TRIG.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL0_MCU_ACTV_TRIG from a register value.
|
|
#define BG_IPU_SISG_CTRL0_MCU_ACTV_TRIG(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL0_MCU_ACTV_TRIG) >> BP_IPU_SISG_CTRL0_MCU_ACTV_TRIG)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL0_MCU_ACTV_TRIG.
|
|
#define BF_IPU_SISG_CTRL0_MCU_ACTV_TRIG(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL0_MCU_ACTV_TRIG) & BM_IPU_SISG_CTRL0_MCU_ACTV_TRIG)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_ACTV_TRIG field to a new value.
|
|
#define BW_IPU_SISG_CTRL0_MCU_ACTV_TRIG(x, v) (HW_IPU_SISG_CTRL0_WR(x, (HW_IPU_SISG_CTRL0_RD(x) & ~BM_IPU_SISG_CTRL0_MCU_ACTV_TRIG) | BF_IPU_SISG_CTRL0_MCU_ACTV_TRIG(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SISG_CTRL0, field EXT_ACTV[30] (RW)
|
|
*
|
|
* External Active Define if an external active trigger will start the counters. The external active
|
|
* trigger is an input signal to the IPU called ext_actv_trig
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL0_EXT_ACTV (30) //!< Bit position for IPU_SISG_CTRL0_EXT_ACTV.
|
|
#define BM_IPU_SISG_CTRL0_EXT_ACTV (0x40000000) //!< Bit mask for IPU_SISG_CTRL0_EXT_ACTV.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL0_EXT_ACTV from a register value.
|
|
#define BG_IPU_SISG_CTRL0_EXT_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL0_EXT_ACTV) >> BP_IPU_SISG_CTRL0_EXT_ACTV)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL0_EXT_ACTV.
|
|
#define BF_IPU_SISG_CTRL0_EXT_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL0_EXT_ACTV) & BM_IPU_SISG_CTRL0_EXT_ACTV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the EXT_ACTV field to a new value.
|
|
#define BW_IPU_SISG_CTRL0_EXT_ACTV(x, v) (HW_IPU_SISG_CTRL0_WR(x, (HW_IPU_SISG_CTRL0_RD(x) & ~BM_IPU_SISG_CTRL0_EXT_ACTV) | BF_IPU_SISG_CTRL0_EXT_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SISG_CTRL1 - SISG Control 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SISG_CTRL1 - SISG Control 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_sisg_ctrl1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sisg_ctrl1_bitfields
|
|
{
|
|
unsigned SISG_STROBE_CNT : 5; //!< [4:0] SISG Strobe Count
|
|
unsigned RESERVED0 : 3; //!< [7:5] Reserved, should be cleared.
|
|
unsigned SISG_OUT_POL : 6; //!< [13:8] SISG_OUT_POL
|
|
unsigned RESERVED1 : 18; //!< [31:14] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_sisg_ctrl1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SISG_CTRL1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SISG_CTRL1_ADDR(x) (REGS_IPU_BASE(x) + 0x8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SISG_CTRL1(x) (*(volatile hw_ipu_sisg_ctrl1_t *) HW_IPU_SISG_CTRL1_ADDR(x))
|
|
#define HW_IPU_SISG_CTRL1_RD(x) (HW_IPU_SISG_CTRL1(x).U)
|
|
#define HW_IPU_SISG_CTRL1_WR(x, v) (HW_IPU_SISG_CTRL1(x).U = (v))
|
|
#define HW_IPU_SISG_CTRL1_SET(x, v) (HW_IPU_SISG_CTRL1_WR(x, HW_IPU_SISG_CTRL1_RD(x) | (v)))
|
|
#define HW_IPU_SISG_CTRL1_CLR(x, v) (HW_IPU_SISG_CTRL1_WR(x, HW_IPU_SISG_CTRL1_RD(x) & ~(v)))
|
|
#define HW_IPU_SISG_CTRL1_TOG(x, v) (HW_IPU_SISG_CTRL1_WR(x, HW_IPU_SISG_CTRL1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SISG_CTRL1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SISG_CTRL1, field SISG_STROBE_CNT[4:0] (RW)
|
|
*
|
|
* SISG Strobe Count The SISG can repeat the sequence for up to 32 cycles; this is used for
|
|
* generating a train of pulses.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL1_SISG_STROBE_CNT (0) //!< Bit position for IPU_SISG_CTRL1_SISG_STROBE_CNT.
|
|
#define BM_IPU_SISG_CTRL1_SISG_STROBE_CNT (0x0000001f) //!< Bit mask for IPU_SISG_CTRL1_SISG_STROBE_CNT.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL1_SISG_STROBE_CNT from a register value.
|
|
#define BG_IPU_SISG_CTRL1_SISG_STROBE_CNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL1_SISG_STROBE_CNT) >> BP_IPU_SISG_CTRL1_SISG_STROBE_CNT)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL1_SISG_STROBE_CNT.
|
|
#define BF_IPU_SISG_CTRL1_SISG_STROBE_CNT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL1_SISG_STROBE_CNT) & BM_IPU_SISG_CTRL1_SISG_STROBE_CNT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SISG_STROBE_CNT field to a new value.
|
|
#define BW_IPU_SISG_CTRL1_SISG_STROBE_CNT(x, v) (HW_IPU_SISG_CTRL1_WR(x, (HW_IPU_SISG_CTRL1_RD(x) & ~BM_IPU_SISG_CTRL1_SISG_STROBE_CNT) | BF_IPU_SISG_CTRL1_SISG_STROBE_CNT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SISG_CTRL1, field SISG_OUT_POL[13:8] (RW)
|
|
*
|
|
* SISG_OUT_POL This bits defines the polarity of the SISG output signals
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CTRL1_SISG_OUT_POL (8) //!< Bit position for IPU_SISG_CTRL1_SISG_OUT_POL.
|
|
#define BM_IPU_SISG_CTRL1_SISG_OUT_POL (0x00003f00) //!< Bit mask for IPU_SISG_CTRL1_SISG_OUT_POL.
|
|
|
|
//! @brief Get value of IPU_SISG_CTRL1_SISG_OUT_POL from a register value.
|
|
#define BG_IPU_SISG_CTRL1_SISG_OUT_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CTRL1_SISG_OUT_POL) >> BP_IPU_SISG_CTRL1_SISG_OUT_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CTRL1_SISG_OUT_POL.
|
|
#define BF_IPU_SISG_CTRL1_SISG_OUT_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CTRL1_SISG_OUT_POL) & BM_IPU_SISG_CTRL1_SISG_OUT_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SISG_OUT_POL field to a new value.
|
|
#define BW_IPU_SISG_CTRL1_SISG_OUT_POL(x, v) (HW_IPU_SISG_CTRL1_WR(x, (HW_IPU_SISG_CTRL1_RD(x) & ~BM_IPU_SISG_CTRL1_SISG_OUT_POL) | BF_IPU_SISG_CTRL1_SISG_OUT_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SISG_SET_I - SISG Set<i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SISG_SET_I - SISG Set<i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_sisg_set_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sisg_set_i_bitfields
|
|
{
|
|
unsigned SISG_SET_I : 25; //!< [24:0] SISG SET <i> value
|
|
unsigned RESERVED0 : 7; //!< [31:25] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_sisg_set_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SISG_SET_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SISG_SET_I_ADDR(x) (REGS_IPU_BASE(x) + 0xc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SISG_SET_I(x) (*(volatile hw_ipu_sisg_set_i_t *) HW_IPU_SISG_SET_I_ADDR(x))
|
|
#define HW_IPU_SISG_SET_I_RD(x) (HW_IPU_SISG_SET_I(x).U)
|
|
#define HW_IPU_SISG_SET_I_WR(x, v) (HW_IPU_SISG_SET_I(x).U = (v))
|
|
#define HW_IPU_SISG_SET_I_SET(x, v) (HW_IPU_SISG_SET_I_WR(x, HW_IPU_SISG_SET_I_RD(x) | (v)))
|
|
#define HW_IPU_SISG_SET_I_CLR(x, v) (HW_IPU_SISG_SET_I_WR(x, HW_IPU_SISG_SET_I_RD(x) & ~(v)))
|
|
#define HW_IPU_SISG_SET_I_TOG(x, v) (HW_IPU_SISG_SET_I_WR(x, HW_IPU_SISG_SET_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SISG_SET_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SISG_SET_I, field SISG_SET_I[24:0] (RW)
|
|
*
|
|
* SISG SET <i> value These bits define the set value of the SISG counter #<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_SET_I_SISG_SET_I (0) //!< Bit position for IPU_SISG_SET_I_SISG_SET_I.
|
|
#define BM_IPU_SISG_SET_I_SISG_SET_I (0x01ffffff) //!< Bit mask for IPU_SISG_SET_I_SISG_SET_I.
|
|
|
|
//! @brief Get value of IPU_SISG_SET_I_SISG_SET_I from a register value.
|
|
#define BG_IPU_SISG_SET_I_SISG_SET_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_SET_I_SISG_SET_I) >> BP_IPU_SISG_SET_I_SISG_SET_I)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_SET_I_SISG_SET_I.
|
|
#define BF_IPU_SISG_SET_I_SISG_SET_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_SET_I_SISG_SET_I) & BM_IPU_SISG_SET_I_SISG_SET_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SISG_SET_I field to a new value.
|
|
#define BW_IPU_SISG_SET_I_SISG_SET_I(x, v) (HW_IPU_SISG_SET_I_WR(x, (HW_IPU_SISG_SET_I_RD(x) & ~BM_IPU_SISG_SET_I_SISG_SET_I) | BF_IPU_SISG_SET_I_SISG_SET_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SISG_CLR_I - SISG Clear <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SISG_CLR_I - SISG Clear <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_sisg_clr_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sisg_clr_i_bitfields
|
|
{
|
|
unsigned SISG_CLEAR_I : 25; //!< [24:0] SISG CLR <i> value
|
|
unsigned RESERVED0 : 7; //!< [31:25] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_sisg_clr_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SISG_CLR_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SISG_CLR_I_ADDR(x) (REGS_IPU_BASE(x) + 0x24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SISG_CLR_I(x) (*(volatile hw_ipu_sisg_clr_i_t *) HW_IPU_SISG_CLR_I_ADDR(x))
|
|
#define HW_IPU_SISG_CLR_I_RD(x) (HW_IPU_SISG_CLR_I(x).U)
|
|
#define HW_IPU_SISG_CLR_I_WR(x, v) (HW_IPU_SISG_CLR_I(x).U = (v))
|
|
#define HW_IPU_SISG_CLR_I_SET(x, v) (HW_IPU_SISG_CLR_I_WR(x, HW_IPU_SISG_CLR_I_RD(x) | (v)))
|
|
#define HW_IPU_SISG_CLR_I_CLR(x, v) (HW_IPU_SISG_CLR_I_WR(x, HW_IPU_SISG_CLR_I_RD(x) & ~(v)))
|
|
#define HW_IPU_SISG_CLR_I_TOG(x, v) (HW_IPU_SISG_CLR_I_WR(x, HW_IPU_SISG_CLR_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SISG_CLR_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SISG_CLR_I, field SISG_CLEAR_I[24:0] (RW)
|
|
*
|
|
* SISG CLR <i> value These bits define the clear value of the SISG counter #<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SISG_CLR_I_SISG_CLEAR_I (0) //!< Bit position for IPU_SISG_CLR_I_SISG_CLEAR_I.
|
|
#define BM_IPU_SISG_CLR_I_SISG_CLEAR_I (0x01ffffff) //!< Bit mask for IPU_SISG_CLR_I_SISG_CLEAR_I.
|
|
|
|
//! @brief Get value of IPU_SISG_CLR_I_SISG_CLEAR_I from a register value.
|
|
#define BG_IPU_SISG_CLR_I_SISG_CLEAR_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SISG_CLR_I_SISG_CLEAR_I) >> BP_IPU_SISG_CLR_I_SISG_CLEAR_I)
|
|
|
|
//! @brief Format value for bitfield IPU_SISG_CLR_I_SISG_CLEAR_I.
|
|
#define BF_IPU_SISG_CLR_I_SISG_CLEAR_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SISG_CLR_I_SISG_CLEAR_I) & BM_IPU_SISG_CLR_I_SISG_CLEAR_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SISG_CLEAR_I field to a new value.
|
|
#define BW_IPU_SISG_CLR_I_SISG_CLEAR_I(x, v) (HW_IPU_SISG_CLR_I_WR(x, (HW_IPU_SISG_CLR_I_RD(x) & ~BM_IPU_SISG_CLR_I_SISG_CLEAR_I) | BF_IPU_SISG_CLR_I_SISG_CLEAR_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_1 - Interrupt Control Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_1 - Interrupt Control Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of EOF (end of frame) of DMA
|
|
* Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_1_bitfields
|
|
{
|
|
unsigned IDMAC_EOF_EN_0 : 1; //!< [0] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_1 : 1; //!< [1] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_2 : 1; //!< [2] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_3 : 1; //!< [3] Enable End of Frame of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_EOF_EN_5 : 1; //!< [5] Enable End of Frame of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_EOF_EN_8 : 1; //!< [8] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_9 : 1; //!< [9] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_10 : 1; //!< [10] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_11 : 1; //!< [11] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_12 : 1; //!< [12] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_13 : 1; //!< [13] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_14 : 1; //!< [14] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_15 : 1; //!< [15] Enable End of Frame of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_EOF_EN_17 : 1; //!< [17] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_18 : 1; //!< [18] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_19 : 1; //!< [19] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_20 : 1; //!< [20] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_21 : 1; //!< [21] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_22 : 1; //!< [22] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_23 : 1; //!< [23] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_24 : 1; //!< [24] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_25 : 1; //!< [25] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_26 : 1; //!< [26] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_27 : 1; //!< [27] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_28 : 1; //!< [28] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_29 : 1; //!< [29] Enable End of Frame of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_EOF_EN_31 : 1; //!< [31] Enable End of Frame of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_ctrl_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_1_ADDR(x) (REGS_IPU_BASE(x) + 0x3c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_1(x) (*(volatile hw_ipu_int_ctrl_1_t *) HW_IPU_INT_CTRL_1_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_1_RD(x) (HW_IPU_INT_CTRL_1(x).U)
|
|
#define HW_IPU_INT_CTRL_1_WR(x, v) (HW_IPU_INT_CTRL_1(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_1_SET(x, v) (HW_IPU_INT_CTRL_1_WR(x, HW_IPU_INT_CTRL_1_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_1_CLR(x, v) (HW_IPU_INT_CTRL_1_WR(x, HW_IPU_INT_CTRL_1_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_1_TOG(x, v) (HW_IPU_INT_CTRL_1_WR(x, HW_IPU_INT_CTRL_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_0[0] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_0 (0) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_0.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_0 (0x00000001) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_0.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_0 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_0) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_0.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_0) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_0 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_0(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_0) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_1[1] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_1 (1) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_1.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_1 (0x00000002) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_1.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_1 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_1) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_1.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_1) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_1 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_1(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_1) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_2[2] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_2 (2) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_2.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_2 (0x00000004) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_2.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_2 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_2) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_2.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_2) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_2 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_2(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_2) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_3[3] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_3 (3) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_3.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_3 (0x00000008) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_3.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_3 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_3) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_3.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_3) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_3 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_3(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_3) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_5[5] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_5 (5) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_5.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_5 (0x00000020) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_5.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_5 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_5) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_5.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_5) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_5 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_5(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_5) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_8[8] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_8 (8) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_8.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_8 (0x00000100) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_8.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_8 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_8) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_8.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_8) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_8 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_8(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_8) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_9[9] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_9 (9) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_9.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_9 (0x00000200) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_9.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_9 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_9) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_9.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_9) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_9 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_9(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_9) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_10[10] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_10 (10) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_10.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_10 (0x00000400) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_10.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_10 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_10) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_10.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_10) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_10 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_10(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_10) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_11[11] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_11 (11) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_11.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_11 (0x00000800) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_11.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_11 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_11) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_11.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_11) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_11 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_11(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_11) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_12[12] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_12 (12) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_12.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_12 (0x00001000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_12.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_12 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_12) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_12.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_12) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_12 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_12(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_12) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_13[13] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_13 (13) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_13.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_13 (0x00002000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_13.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_13 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_13) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_13.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_13) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_13 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_13(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_13) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_14[14] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_14 (14) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_14.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_14 (0x00004000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_14.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_14 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_14) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_14.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_14) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_14 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_14(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_14) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_15[15] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_15 (15) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_15.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_15 (0x00008000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_15.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_15 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_15) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_15.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_15) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_15 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_15(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_15) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_17[17] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_17 (17) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_17.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_17 (0x00020000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_17.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_17 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_17) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_17)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_17.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_17) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_17 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_17(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_17) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_18[18] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_18 (18) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_18.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_18 (0x00040000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_18.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_18 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_18) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_18.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_18) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_18 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_18(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_18) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_19[19] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_19 (19) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_19.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_19 (0x00080000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_19.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_19 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_19) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_19.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_19) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_19 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_19(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_19) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_20[20] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_20 (20) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_20.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_20 (0x00100000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_20.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_20 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_20) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_20.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_20) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_20 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_20(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_20) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_21[21] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_21 (21) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_21.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_21 (0x00200000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_21.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_21 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_21) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_21.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_21) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_21 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_21(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_21) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_22[22] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_22 (22) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_22.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_22 (0x00400000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_22.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_22 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_22) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_22.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_22) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_22 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_22(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_22) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_23[23] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_23 (23) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_23.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_23 (0x00800000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_23.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_23 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_23) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_23.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_23) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_23 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_23(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_23) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_24[24] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_24 (24) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_24.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_24 (0x01000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_24.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_24 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_24) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_24.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_24) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_24 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_24(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_24) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_25[25] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_25 (25) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_25.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_25 (0x02000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_25 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_25) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_25.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_25) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_25 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_25(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_25) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_26[26] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_26 (26) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_26.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_26 (0x04000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_26 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_26) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_26.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_26) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_26 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_26(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_26) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_27[27] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_27 (27) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_27.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_27 (0x08000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_27.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_27 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_27) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_27)
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|
|
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//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_27.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_27) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_27)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_27 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_27(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_27) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_28[28] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_28 (28) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_28.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_28 (0x10000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_28.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_28 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_28) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_28)
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|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_28.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_28) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_28)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_28 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_28(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_28) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_28(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_29[29] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_29 (29) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_29.
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|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_29 (0x20000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_29.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_29 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_29) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_29)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_29.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_29) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_29 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_29(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_29) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_1, field IDMAC_EOF_EN_31[31] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_31 (31) //!< Bit position for IPU_INT_CTRL_1_IDMAC_EOF_EN_31.
|
|
#define BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_31 (0x80000000) //!< Bit mask for IPU_INT_CTRL_1_IDMAC_EOF_EN_31.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_1_IDMAC_EOF_EN_31 from a register value.
|
|
#define BG_IPU_INT_CTRL_1_IDMAC_EOF_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_31) >> BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_1_IDMAC_EOF_EN_31.
|
|
#define BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_1_IDMAC_EOF_EN_31) & BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_31 field to a new value.
|
|
#define BW_IPU_INT_CTRL_1_IDMAC_EOF_EN_31(x, v) (HW_IPU_INT_CTRL_1_WR(x, (HW_IPU_INT_CTRL_1_RD(x) & ~BM_IPU_INT_CTRL_1_IDMAC_EOF_EN_31) | BF_IPU_INT_CTRL_1_IDMAC_EOF_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_2 - Interrupt Control Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_2 - Interrupt Control Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of EOF (end of frame) of DMA
|
|
* Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_EOF_EN_33 : 1; //!< [1] Enable End of Frame of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_EOF_EN_40 : 1; //!< [8] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_41 : 1; //!< [9] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_42 : 1; //!< [10] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_43 : 1; //!< [11] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_44 : 1; //!< [12] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_45 : 1; //!< [13] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_46 : 1; //!< [14] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_47 : 1; //!< [15] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_48 : 1; //!< [16] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_49 : 1; //!< [17] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_50 : 1; //!< [18] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_51 : 1; //!< [19] Enable End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_EN_52 : 1; //!< [20] Enable End of Frame of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_2_ADDR(x) (REGS_IPU_BASE(x) + 0x40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_2(x) (*(volatile hw_ipu_int_ctrl_2_t *) HW_IPU_INT_CTRL_2_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_2_RD(x) (HW_IPU_INT_CTRL_2(x).U)
|
|
#define HW_IPU_INT_CTRL_2_WR(x, v) (HW_IPU_INT_CTRL_2(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_2_SET(x, v) (HW_IPU_INT_CTRL_2_WR(x, HW_IPU_INT_CTRL_2_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_2_CLR(x, v) (HW_IPU_INT_CTRL_2_WR(x, HW_IPU_INT_CTRL_2_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_2_TOG(x, v) (HW_IPU_INT_CTRL_2_WR(x, HW_IPU_INT_CTRL_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_33[1] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_33 (1) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_33.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_33 (0x00000002) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_33.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_33 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_33) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_33.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_33) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_33 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_33(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_33) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_40[8] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_40 (8) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_40.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_40 (0x00000100) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_40.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_40 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_40) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_40.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_40) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_40 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_40(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_40) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_41[9] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_41 (9) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_41.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_41 (0x00000200) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_41.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_41 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_41) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_41.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_41) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_41 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_41(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_41) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_42[10] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_42 (10) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_42.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_42 (0x00000400) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_42.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_42 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_42) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_42.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_42) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_42 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_42(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_42) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_43[11] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_43 (11) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_43.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_43 (0x00000800) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_43.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_43 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_43) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_43.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_43) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_43 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_43(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_43) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_44[12] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_44 (12) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_44.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_44 (0x00001000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_44.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_44 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_44) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_44.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_44) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_44 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_44(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_44) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_45[13] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_45 (13) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_45.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_45 (0x00002000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_45.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_45 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_45) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_45.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_45) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_45 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_45(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_45) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_46[14] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_46 (14) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_46.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_46 (0x00004000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_46.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_46 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_46) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_46.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_46) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_46 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_46(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_46) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_47[15] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_47 (15) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_47.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_47 (0x00008000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_47.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_47 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_47) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_47.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_47) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_47 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_47(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_47) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_48[16] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_48 (16) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_48.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_48 (0x00010000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_48.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_48 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_48) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_48.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_48) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_48 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_48(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_48) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_49[17] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_49 (17) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_49.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_49 (0x00020000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_49.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_49 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_49) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_49.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_49) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_49 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_49(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_49) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_50[18] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_50 (18) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_50.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_50 (0x00040000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_50.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_50 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_50) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_50.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_50) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_50 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_50(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_50) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_51[19] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_51 (19) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_51.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_51 (0x00080000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_51.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_51 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_51) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_51.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_51) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_51 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_51(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_51) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_2, field IDMAC_EOF_EN_52[20] (RW)
|
|
*
|
|
* Enable End of Frame of Channel interrupt. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_52 (20) //!< Bit position for IPU_INT_CTRL_2_IDMAC_EOF_EN_52.
|
|
#define BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_52 (0x00100000) //!< Bit mask for IPU_INT_CTRL_2_IDMAC_EOF_EN_52.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_2_IDMAC_EOF_EN_52 from a register value.
|
|
#define BG_IPU_INT_CTRL_2_IDMAC_EOF_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_52) >> BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_2_IDMAC_EOF_EN_52.
|
|
#define BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_2_IDMAC_EOF_EN_52) & BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_EN_52 field to a new value.
|
|
#define BW_IPU_INT_CTRL_2_IDMAC_EOF_EN_52(x, v) (HW_IPU_INT_CTRL_2_WR(x, (HW_IPU_INT_CTRL_2_RD(x) & ~BM_IPU_INT_CTRL_2_IDMAC_EOF_EN_52) | BF_IPU_INT_CTRL_2_IDMAC_EOF_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_3 - Interrupt Control Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_3 - Interrupt Control Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of NFACK (New Frame Ack) of
|
|
* DMA Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_3_bitfields
|
|
{
|
|
unsigned IDMAC_NFACK_EN_0 : 1; //!< [0] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_1 : 1; //!< [1] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_2 : 1; //!< [2] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_3 : 1; //!< [3] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_NFACK_EN_5 : 1; //!< [5] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_NFACK_EN_8 : 1; //!< [8] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_9 : 1; //!< [9] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_10 : 1; //!< [10] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_11 : 1; //!< [11] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_12 : 1; //!< [12] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_13 : 1; //!< [13] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_14 : 1; //!< [14] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_15 : 1; //!< [15] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_NFACK_EN_17 : 1; //!< [17] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_18 : 1; //!< [18] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_19 : 1; //!< [19] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_20 : 1; //!< [20] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_21 : 1; //!< [21] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_22 : 1; //!< [22] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_23 : 1; //!< [23] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_24 : 1; //!< [24] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_25 : 1; //!< [25] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_26 : 1; //!< [26] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_27 : 1; //!< [27] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_28 : 1; //!< [28] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_29 : 1; //!< [29] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_NFACK_EN_31 : 1; //!< [31] Enable New Frame Ack of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_ctrl_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_3_ADDR(x) (REGS_IPU_BASE(x) + 0x44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_3(x) (*(volatile hw_ipu_int_ctrl_3_t *) HW_IPU_INT_CTRL_3_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_3_RD(x) (HW_IPU_INT_CTRL_3(x).U)
|
|
#define HW_IPU_INT_CTRL_3_WR(x, v) (HW_IPU_INT_CTRL_3(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_3_SET(x, v) (HW_IPU_INT_CTRL_3_WR(x, HW_IPU_INT_CTRL_3_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_3_CLR(x, v) (HW_IPU_INT_CTRL_3_WR(x, HW_IPU_INT_CTRL_3_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_3_TOG(x, v) (HW_IPU_INT_CTRL_3_WR(x, HW_IPU_INT_CTRL_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_0[0] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0 (0) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_0.
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#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0 (0x00000001) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_0.
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//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_0 from a register value.
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#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0)
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//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_0.
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#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_EN_0 field to a new value.
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#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_0(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_1[1] (RW)
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*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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|
//@{
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|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1 (1) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_1.
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#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1 (0x00000002) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_1.
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//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_1 from a register value.
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#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1)
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//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_1.
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#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_EN_1 field to a new value.
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#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_1(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_2[2] (RW)
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*
|
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* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
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* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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//@{
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#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2 (2) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_2.
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#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2 (0x00000004) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_2.
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//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_2 from a register value.
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#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2)
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//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_2.
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|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFACK_EN_2 field to a new value.
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|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_3[3] (RW)
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*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3 (3) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_3.
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#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3 (0x00000008) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_3.
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//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_3 from a register value.
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|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3)
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|
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//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_3.
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|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_3 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_3(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_5[5] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5 (5) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_5.
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|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5 (0x00000020) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_5.
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|
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|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_5 from a register value.
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|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_5.
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|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_5 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_5(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_8[8] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8 (8) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_8.
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|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8 (0x00000100) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_8.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_8 from a register value.
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|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8)
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|
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|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_8.
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|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_8 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_8(v)))
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|
#endif
|
|
//@}
|
|
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|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_9[9] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9 (9) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_9.
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|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9 (0x00000200) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_9.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_9 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_9.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_9 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_10[10] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10 (10) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_10.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10 (0x00000400) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_10.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_10 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_10.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_10 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_11[11] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11 (11) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_11.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11 (0x00000800) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_11.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_11 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_11.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_11 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_12[12] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12 (12) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_12.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12 (0x00001000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_12.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_12 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_12.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_12 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_13[13] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13 (13) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_13.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13 (0x00002000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_13.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_13 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_13.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_13 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_14[14] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14 (14) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_14.
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|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14 (0x00004000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_14.
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|
|
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//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_14 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14)
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|
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//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_14.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_14 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_14(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_15[15] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15 (15) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_15.
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#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15 (0x00008000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_15.
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|
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//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_15 from a register value.
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|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15)
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//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_15.
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|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_15 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_15(v)))
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|
#endif
|
|
//@}
|
|
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/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_17[17] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17 (17) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_17.
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#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17 (0x00020000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_17.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_17 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_17.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_17 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_18[18] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18 (18) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_18.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18 (0x00040000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_18.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_18 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_18.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_18 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_19[19] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19 (19) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_19.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19 (0x00080000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_19.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_19 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_19.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_19 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_20[20] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20 (20) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_20.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20 (0x00100000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_20.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_20 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_20.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_20 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_21[21] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21 (21) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_21.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21 (0x00200000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_21.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_21 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_21.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_21 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_22[22] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22 (22) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_22.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22 (0x00400000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_22.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_22 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_22.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_22 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_23[23] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23 (23) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_23.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23 (0x00800000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_23.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_23 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_23.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_23 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_24[24] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24 (24) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_24.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24 (0x01000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_24.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_24 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_24.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_24 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_25[25] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25 (25) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_25.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25 (0x02000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_25 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_25.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_25 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_26[26] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26 (26) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_26.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26 (0x04000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_26 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_26.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_26 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_27[27] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27 (27) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_27.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27 (0x08000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_27.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_27 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_27.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_27 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_28[28] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28 (28) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_28.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28 (0x10000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_28.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_28 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_28.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_28 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_29[29] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29 (29) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_29.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29 (0x20000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_29.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_29 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_29.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_29 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_3, field IDMAC_NFACK_EN_31[31] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31 (31) //!< Bit position for IPU_INT_CTRL_3_IDMAC_NFACK_EN_31.
|
|
#define BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31 (0x80000000) //!< Bit mask for IPU_INT_CTRL_3_IDMAC_NFACK_EN_31.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_3_IDMAC_NFACK_EN_31 from a register value.
|
|
#define BG_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31) >> BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_3_IDMAC_NFACK_EN_31.
|
|
#define BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31) & BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_31 field to a new value.
|
|
#define BW_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31(x, v) (HW_IPU_INT_CTRL_3_WR(x, (HW_IPU_INT_CTRL_3_RD(x) & ~BM_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31) | BF_IPU_INT_CTRL_3_IDMAC_NFACK_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_4 - Interrupt Control Register 4
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_4 - Interrupt Control Register 4 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of NFACK (New Frame Ack) of
|
|
* DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_4_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_NFACK_EN_33 : 1; //!< [1] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_NFACK_EN_40 : 1; //!< [8] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_41 : 1; //!< [9] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_42 : 1; //!< [10] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_43 : 1; //!< [11] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_44 : 1; //!< [12] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_45 : 1; //!< [13] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_46 : 1; //!< [14] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_47 : 1; //!< [15] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_48 : 1; //!< [16] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_49 : 1; //!< [17] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_50 : 1; //!< [18] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_51 : 1; //!< [19] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_EN_52 : 1; //!< [20] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_4_ADDR(x) (REGS_IPU_BASE(x) + 0x48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_4(x) (*(volatile hw_ipu_int_ctrl_4_t *) HW_IPU_INT_CTRL_4_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_4_RD(x) (HW_IPU_INT_CTRL_4(x).U)
|
|
#define HW_IPU_INT_CTRL_4_WR(x, v) (HW_IPU_INT_CTRL_4(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_4_SET(x, v) (HW_IPU_INT_CTRL_4_WR(x, HW_IPU_INT_CTRL_4_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_4_CLR(x, v) (HW_IPU_INT_CTRL_4_WR(x, HW_IPU_INT_CTRL_4_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_4_TOG(x, v) (HW_IPU_INT_CTRL_4_WR(x, HW_IPU_INT_CTRL_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_33[1] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33 (1) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_33.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33 (0x00000002) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_33.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_33 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_33.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_33 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_40[8] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40 (8) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_40.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40 (0x00000100) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_40.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_40 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_40.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_40 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_41[9] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41 (9) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_41.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41 (0x00000200) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_41.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_41 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_41.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_41 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_42[10] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42 (10) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_42.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42 (0x00000400) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_42.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_42 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_42.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_42 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_43[11] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43 (11) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_43.
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#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43 (0x00000800) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_43.
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//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_43 from a register value.
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#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43)
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//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_43.
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|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFACK_EN_43 field to a new value.
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|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_43(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_44[12] (RW)
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*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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|
//@{
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|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44 (12) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_44.
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#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44 (0x00001000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_44.
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//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_44 from a register value.
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#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44)
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//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_44.
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#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_EN_44 field to a new value.
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#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_44(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_45[13] (RW)
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*
|
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* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
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* - 1 - Interrupt is enabled.
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|
*/
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//@{
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#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45 (13) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_45.
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#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45 (0x00002000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_45.
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//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_45 from a register value.
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#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45)
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//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_45.
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|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFACK_EN_45 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_45(v)))
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#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_46[14] (RW)
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*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46 (14) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_46.
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|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46 (0x00004000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_46.
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|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_46 from a register value.
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|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_46.
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|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_46 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_46(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_47[15] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47 (15) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_47.
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|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47 (0x00008000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_47.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_47 from a register value.
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|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_47.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_47 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_47(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_48[16] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48 (16) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_48.
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|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48 (0x00010000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_48.
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|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_48 from a register value.
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|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48)
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|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_48.
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|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_48 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_48(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_49[17] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49 (17) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_49.
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|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49 (0x00020000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_49.
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|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_49 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_49.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_49 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_50[18] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50 (18) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_50.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50 (0x00040000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_50.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_50 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_50.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_50 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_51[19] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51 (19) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_51.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51 (0x00080000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_51.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_51 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_51.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_51 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_4, field IDMAC_NFACK_EN_52[20] (RW)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the control of New Frame Ack of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52 (20) //!< Bit position for IPU_INT_CTRL_4_IDMAC_NFACK_EN_52.
|
|
#define BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52 (0x00100000) //!< Bit mask for IPU_INT_CTRL_4_IDMAC_NFACK_EN_52.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_4_IDMAC_NFACK_EN_52 from a register value.
|
|
#define BG_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52) >> BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_4_IDMAC_NFACK_EN_52.
|
|
#define BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52) & BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_EN_52 field to a new value.
|
|
#define BW_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52(x, v) (HW_IPU_INT_CTRL_4_WR(x, (HW_IPU_INT_CTRL_4_RD(x) & ~BM_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52) | BF_IPU_INT_CTRL_4_IDMAC_NFACK_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_5 - Interrupt Control Register 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_5 - Interrupt Control Register 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of the New-frame before end-
|
|
* of-frame indication (NFB4EOF) of DMA Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_5_bitfields
|
|
{
|
|
unsigned IDMAC_NFB4EOF_EN_0 : 1; //!< [0] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_1 : 1; //!< [1] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_2 : 1; //!< [2] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_3 : 1; //!< [3] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_NFB4EOF_EN_5 : 1; //!< [5] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_NFB4EOF_EN_8 : 1; //!< [8] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_9 : 1; //!< [9] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_10 : 1; //!< [10] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_11 : 1; //!< [11] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_12 : 1; //!< [12] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_13 : 1; //!< [13] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_14 : 1; //!< [14] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_15 : 1; //!< [15] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_NFB4EOF_EN_17 : 1; //!< [17] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_18 : 1; //!< [18] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_19 : 1; //!< [19] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_20 : 1; //!< [20] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_21 : 1; //!< [21] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_22 : 1; //!< [22] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_23 : 1; //!< [23] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_24 : 1; //!< [24] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_25 : 1; //!< [25] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_26 : 1; //!< [26] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_27 : 1; //!< [27] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_28 : 1; //!< [28] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_29 : 1; //!< [29] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_NFB4EOF_EN_31 : 1; //!< [31] New Frame before end-of-frame error indication of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_ctrl_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_5_ADDR(x) (REGS_IPU_BASE(x) + 0x4c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_5(x) (*(volatile hw_ipu_int_ctrl_5_t *) HW_IPU_INT_CTRL_5_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_5_RD(x) (HW_IPU_INT_CTRL_5(x).U)
|
|
#define HW_IPU_INT_CTRL_5_WR(x, v) (HW_IPU_INT_CTRL_5(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_5_SET(x, v) (HW_IPU_INT_CTRL_5_WR(x, HW_IPU_INT_CTRL_5_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_5_CLR(x, v) (HW_IPU_INT_CTRL_5_WR(x, HW_IPU_INT_CTRL_5_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_5_TOG(x, v) (HW_IPU_INT_CTRL_5_WR(x, HW_IPU_INT_CTRL_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_0[0] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0 (0) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0 (0x00000001) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_0 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_1[1] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1 (1) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1 (0x00000002) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_1 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_2[2] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2 (2) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2 (0x00000004) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_2 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_3[3] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3 (3) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3 (0x00000008) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_3 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_5[5] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5 (5) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5 (0x00000020) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_5 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_8[8] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8 (8) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8 (0x00000100) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_8 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_9[9] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9 (9) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9 (0x00000200) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_9 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_10[10] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10 (10) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10 (0x00000400) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_10 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_11[11] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11 (11) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11 (0x00000800) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_11 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_12[12] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12 (12) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12.
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#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12 (0x00001000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12.
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|
|
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//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12)
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|
|
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//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12.
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|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_12 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_12(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_13[13] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13 (13) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13.
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#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13 (0x00002000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13)
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|
|
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//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_13 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_14[14] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14 (14) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14 (0x00004000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_14 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_15[15] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15 (15) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15 (0x00008000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_15 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_17[17] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17 (17) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17 (0x00020000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_17 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_18[18] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18 (18) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18 (0x00040000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_18 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_19[19] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19 (19) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19 (0x00080000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_19 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_20[20] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20 (20) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20 (0x00100000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_20 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_21[21] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21 (21) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21 (0x00200000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_21 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_22[22] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22 (22) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22 (0x00400000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_22 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_23[23] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23 (23) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23 (0x00800000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_23 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_24[24] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24 (24) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24 (0x01000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_24 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_25[25] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25 (25) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25 (0x02000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_25 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_26[26] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26 (26) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26 (0x04000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_26 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_27[27] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27 (27) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27 (0x08000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_27 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_28[28] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28 (28) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28 (0x10000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_28 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_29[29] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29 (29) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29 (0x20000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_29 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_5, field IDMAC_NFB4EOF_EN_31[31] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31 (31) //!< Bit position for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31.
|
|
#define BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31 (0x80000000) //!< Bit mask for IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31 from a register value.
|
|
#define BG_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31) >> BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31.
|
|
#define BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31) & BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_31 field to a new value.
|
|
#define BW_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31(x, v) (HW_IPU_INT_CTRL_5_WR(x, (HW_IPU_INT_CTRL_5_RD(x) & ~BM_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31) | BF_IPU_INT_CTRL_5_IDMAC_NFB4EOF_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_6 - Interrupt Control Register 6
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_6 - Interrupt Control Register 6 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of the New-frame before end-
|
|
* of-frame indication (NFB4EOF_ERR) of DMA Channels interrupts [63:32] can be found in this
|
|
* register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_6_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_NFB4EOF_EN_33 : 1; //!< [1] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_NFB4EOF_EN_40 : 1; //!< [8] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_41 : 1; //!< [9] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_42 : 1; //!< [10] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_43 : 1; //!< [11] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_44 : 1; //!< [12] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_45 : 1; //!< [13] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_46 : 1; //!< [14] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_47 : 1; //!< [15] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_48 : 1; //!< [16] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_49 : 1; //!< [17] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_50 : 1; //!< [18] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_51 : 1; //!< [19] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_EN_52 : 1; //!< [20] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_6_ADDR(x) (REGS_IPU_BASE(x) + 0x50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_6(x) (*(volatile hw_ipu_int_ctrl_6_t *) HW_IPU_INT_CTRL_6_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_6_RD(x) (HW_IPU_INT_CTRL_6(x).U)
|
|
#define HW_IPU_INT_CTRL_6_WR(x, v) (HW_IPU_INT_CTRL_6(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_6_SET(x, v) (HW_IPU_INT_CTRL_6_WR(x, HW_IPU_INT_CTRL_6_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_6_CLR(x, v) (HW_IPU_INT_CTRL_6_WR(x, HW_IPU_INT_CTRL_6_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_6_TOG(x, v) (HW_IPU_INT_CTRL_6_WR(x, HW_IPU_INT_CTRL_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_33[1] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33 (1) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33 (0x00000002) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_33 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_40[8] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40 (8) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40 (0x00000100) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_40 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_41[9] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41 (9) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41 (0x00000200) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_41 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_42[10] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42 (10) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42 (0x00000400) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_42 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_43[11] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43 (11) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43 (0x00000800) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_43 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_44[12] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44 (12) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44 (0x00001000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_44 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_45[13] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45 (13) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45 (0x00002000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_45 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_46[14] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46 (14) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46 (0x00004000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_46 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_47[15] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47 (15) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47 (0x00008000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_47 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_48[16] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48 (16) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48 (0x00010000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_48 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_49[17] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49 (17) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49 (0x00020000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49)
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|
|
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//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_49 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_49(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_50[18] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50 (18) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50.
|
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#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50 (0x00040000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50)
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|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_50 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_50(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_51[19] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51 (19) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51 (0x00080000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_51 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_6, field IDMAC_NFB4EOF_EN_52[20] (RW)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the control of
|
|
* New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52 (20) //!< Bit position for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52.
|
|
#define BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52 (0x00100000) //!< Bit mask for IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52 from a register value.
|
|
#define BG_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52) >> BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52.
|
|
#define BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52) & BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_EN_52 field to a new value.
|
|
#define BW_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52(x, v) (HW_IPU_INT_CTRL_6_WR(x, (HW_IPU_INT_CTRL_6_RD(x) & ~BM_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52) | BF_IPU_INT_CTRL_6_IDMAC_NFB4EOF_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_7 - Interrupt Control Register 7
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_7 - Interrupt Control Register 7 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPUIPU interrupts controls. The controls of the End-of-Scroll
|
|
* indication (EOS) of DMA Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_7_bitfields
|
|
{
|
|
unsigned RESERVED0 : 19; //!< [18:0] Reserved.
|
|
unsigned IDMAC_EOS_EN_19 : 1; //!< [19] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED1 : 3; //!< [22:20] Reserved.
|
|
unsigned IDMAC_EOS_EN_23 : 1; //!< [23] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_24 : 1; //!< [24] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_25 : 1; //!< [25] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_26 : 1; //!< [26] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_27 : 1; //!< [27] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_28 : 1; //!< [28] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_29 : 1; //!< [29] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_EOS_EN_31 : 1; //!< [31] End of Scroll indication of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_ctrl_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_7_ADDR(x) (REGS_IPU_BASE(x) + 0x54)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_7(x) (*(volatile hw_ipu_int_ctrl_7_t *) HW_IPU_INT_CTRL_7_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_7_RD(x) (HW_IPU_INT_CTRL_7(x).U)
|
|
#define HW_IPU_INT_CTRL_7_WR(x, v) (HW_IPU_INT_CTRL_7(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_7_SET(x, v) (HW_IPU_INT_CTRL_7_WR(x, HW_IPU_INT_CTRL_7_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_7_CLR(x, v) (HW_IPU_INT_CTRL_7_WR(x, HW_IPU_INT_CTRL_7_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_7_TOG(x, v) (HW_IPU_INT_CTRL_7_WR(x, HW_IPU_INT_CTRL_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_19[19] (RW)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_19 (19) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_19.
|
|
#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_19 (0x00080000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_19.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_19 from a register value.
|
|
#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_19) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_19.
|
|
#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_19) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_19 field to a new value.
|
|
#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_19(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_19) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_23[23] (RW)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_23 (23) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_23.
|
|
#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_23 (0x00800000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_23.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_23 from a register value.
|
|
#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_23) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_23.
|
|
#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_23) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_23 field to a new value.
|
|
#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_23(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_23) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_24[24] (RW)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_24 (24) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_24.
|
|
#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_24 (0x01000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_24.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_24 from a register value.
|
|
#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_24) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_24.
|
|
#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_24) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_24 field to a new value.
|
|
#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_24(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_24) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_25[25] (RW)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_25 (25) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_25.
|
|
#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_25 (0x02000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_25 from a register value.
|
|
#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_25) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_25.
|
|
#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_25) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_25 field to a new value.
|
|
#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_25(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_25) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_26[26] (RW)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_26 (26) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_26.
|
|
#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_26 (0x04000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_26 from a register value.
|
|
#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_26) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_26.
|
|
#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_26) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_26 field to a new value.
|
|
#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_26(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_26) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_27[27] (RW)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_27 (27) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_27.
|
|
#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_27 (0x08000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_27.
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//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_27 from a register value.
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#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_27) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_27)
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//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_27.
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#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_27) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_27)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOS_EN_27 field to a new value.
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#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_27(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_27) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_27(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_28[28] (RW)
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*
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* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
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* of Channel #n. n Indicates the corresponding DMA channel number.
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*
|
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* Values:
|
|
* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_28 (28) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_28.
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#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_28 (0x10000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_28.
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//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_28 from a register value.
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#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_28) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_28)
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//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_28.
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#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_28) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_28)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOS_EN_28 field to a new value.
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#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_28(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_28) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_28(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_29[29] (RW)
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*
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* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
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* of Channel #n. n Indicates the corresponding DMA channel number.
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*
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* Values:
|
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_29 (29) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_29.
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#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_29 (0x20000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_29.
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//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_29 from a register value.
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#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_29) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_29)
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//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_29.
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#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_29) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_29)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOS_EN_29 field to a new value.
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#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_29(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_29) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_29(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_7, field IDMAC_EOS_EN_31[31] (RW)
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*
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* End of Scroll indication of Channel interrupt. This bit is the control of End of Scroll interrupt
|
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* of Channel #n. n Indicates the corresponding DMA channel number.
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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|
*/
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//@{
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#define BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_31 (31) //!< Bit position for IPU_INT_CTRL_7_IDMAC_EOS_EN_31.
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#define BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_31 (0x80000000) //!< Bit mask for IPU_INT_CTRL_7_IDMAC_EOS_EN_31.
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//! @brief Get value of IPU_INT_CTRL_7_IDMAC_EOS_EN_31 from a register value.
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#define BG_IPU_INT_CTRL_7_IDMAC_EOS_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_31) >> BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_31)
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//! @brief Format value for bitfield IPU_INT_CTRL_7_IDMAC_EOS_EN_31.
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#define BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_7_IDMAC_EOS_EN_31) & BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_31)
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|
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOS_EN_31 field to a new value.
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|
#define BW_IPU_INT_CTRL_7_IDMAC_EOS_EN_31(x, v) (HW_IPU_INT_CTRL_7_WR(x, (HW_IPU_INT_CTRL_7_RD(x) & ~BM_IPU_INT_CTRL_7_IDMAC_EOS_EN_31) | BF_IPU_INT_CTRL_7_IDMAC_EOS_EN_31(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_INT_CTRL_8 - Interrupt Control Register 8
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_INT_CTRL_8 - Interrupt Control Register 8 (RW)
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*
|
|
* Reset value: 0x00000000
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*
|
|
* This register contains part of IPU interrupts controls. The controls of the End of Scroll
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* indication (EOS) of DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
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|
typedef union _hw_ipu_int_ctrl_8
|
|
{
|
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reg32_t U;
|
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struct _hw_ipu_int_ctrl_8_bitfields
|
|
{
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|
unsigned RESERVED0 : 1; //!< [0] Reserved.
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unsigned IDMAC_EOS_EN_33 : 1; //!< [1] End of Scroll of Channel interrupt.
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unsigned RESERVED1 : 7; //!< [8:2] Reserved.
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unsigned IDMAC_EOS_EN_41 : 1; //!< [9] End of Scroll of Channel interrupt.
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unsigned IDMAC_EOS_EN_42 : 1; //!< [10] End of Scroll of Channel interrupt.
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unsigned IDMAC_EOS_EN_43 : 1; //!< [11] End of Scroll of Channel interrupt.
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unsigned IDMAC_EOS_EN_44 : 1; //!< [12] End of Scroll of Channel interrupt.
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unsigned RESERVED2 : 6; //!< [18:13] Reserved.
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unsigned IDMAC_EOS_EN_51 : 1; //!< [19] End of Scroll of Channel interrupt.
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unsigned IDMAC_EOS_EN_52 : 1; //!< [20] End of Scroll of Channel interrupt.
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|
unsigned RESERVED3 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_8_t;
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|
#endif
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|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_8 register
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|
*/
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|
//@{
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|
#define HW_IPU_INT_CTRL_8_ADDR(x) (REGS_IPU_BASE(x) + 0x58)
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|
|
#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_INT_CTRL_8(x) (*(volatile hw_ipu_int_ctrl_8_t *) HW_IPU_INT_CTRL_8_ADDR(x))
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#define HW_IPU_INT_CTRL_8_RD(x) (HW_IPU_INT_CTRL_8(x).U)
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#define HW_IPU_INT_CTRL_8_WR(x, v) (HW_IPU_INT_CTRL_8(x).U = (v))
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#define HW_IPU_INT_CTRL_8_SET(x, v) (HW_IPU_INT_CTRL_8_WR(x, HW_IPU_INT_CTRL_8_RD(x) | (v)))
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#define HW_IPU_INT_CTRL_8_CLR(x, v) (HW_IPU_INT_CTRL_8_WR(x, HW_IPU_INT_CTRL_8_RD(x) & ~(v)))
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#define HW_IPU_INT_CTRL_8_TOG(x, v) (HW_IPU_INT_CTRL_8_WR(x, HW_IPU_INT_CTRL_8_RD(x) ^ (v)))
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|
#endif
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|
//@}
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|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_8 bitfields
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|
*/
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|
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/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_33[1] (RW)
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|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_33 (1) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_33.
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|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_33 (0x00000002) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_33.
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|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_33 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_33) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_33)
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|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_33.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_33) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_33)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_33 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_33(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_33) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_33(v)))
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|
#endif
|
|
//@}
|
|
|
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/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_41[9] (RW)
|
|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_41 (9) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_41.
|
|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_41 (0x00000200) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_41.
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|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_41 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_41) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_41.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_41) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_41 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_41(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_41) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_42[10] (RW)
|
|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_42 (10) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_42.
|
|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_42 (0x00000400) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_42.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_42 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_42) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_42.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_42) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_42 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_42(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_42) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_43[11] (RW)
|
|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_43 (11) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_43.
|
|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_43 (0x00000800) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_43.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_43 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_43) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_43.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_43) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_43 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_43(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_43) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_44[12] (RW)
|
|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_44 (12) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_44.
|
|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_44 (0x00001000) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_44.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_44 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_44) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_44.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_44) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_44 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_44(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_44) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_51[19] (RW)
|
|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_51 (19) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_51.
|
|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_51 (0x00080000) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_51.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_51 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_51) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_51.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_51) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_51 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_51(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_51) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_8, field IDMAC_EOS_EN_52[20] (RW)
|
|
*
|
|
* End of Scroll of Channel interrupt. This bit is the control of End Of Scroll interrupt of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_52 (20) //!< Bit position for IPU_INT_CTRL_8_IDMAC_EOS_EN_52.
|
|
#define BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_52 (0x00100000) //!< Bit mask for IPU_INT_CTRL_8_IDMAC_EOS_EN_52.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_8_IDMAC_EOS_EN_52 from a register value.
|
|
#define BG_IPU_INT_CTRL_8_IDMAC_EOS_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_52) >> BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_8_IDMAC_EOS_EN_52.
|
|
#define BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_8_IDMAC_EOS_EN_52) & BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_52 field to a new value.
|
|
#define BW_IPU_INT_CTRL_8_IDMAC_EOS_EN_52(x, v) (HW_IPU_INT_CTRL_8_WR(x, (HW_IPU_INT_CTRL_8_RD(x) & ~BM_IPU_INT_CTRL_8_IDMAC_EOS_EN_52) | BF_IPU_INT_CTRL_8_IDMAC_EOS_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_9 - Interrupt Control Register 9
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_9 - Interrupt Control Register 9 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. This register controls error interrupt
|
|
* signals coming from different sub-blocks within
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_9_bitfields
|
|
{
|
|
unsigned VDI_FIFO1_OVF_EN : 1; //!< [0] FIFO1 overflow Interrupt1 Enable
|
|
unsigned RESERVED0 : 25; //!< [25:1] Reserved
|
|
unsigned IC_BAYER_BUF_OVF_EN : 1; //!< [26] This bit enables an interrupt that is a result of the IC Buffer overflow for bayer coming from the IC.
|
|
unsigned IC_ENC_BUF_OVF_EN : 1; //!< [27] This bit enables an interrupt that is a result of the IC Buffer overflow for encoding coming from the IC.
|
|
unsigned IC_VF_BUF_OVF_EN : 1; //!< [28] This bit enables an interrupt that is a result of the IC Buffer overflow for view finder coming from the IC.
|
|
unsigned RESERVED1 : 1; //!< [29] Reserved
|
|
unsigned CSI0_PUPE_EN : 1; //!< [30] CSI0_PUPE_EN - CSI0 parameters update error interrupt enable.
|
|
unsigned CSI1_PUPE_EN : 1; //!< [31] CSI1_PUPE_EN - CSI1 parameters update error interrupt enable.
|
|
} B;
|
|
} hw_ipu_int_ctrl_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_9_ADDR(x) (REGS_IPU_BASE(x) + 0x5c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_9(x) (*(volatile hw_ipu_int_ctrl_9_t *) HW_IPU_INT_CTRL_9_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_9_RD(x) (HW_IPU_INT_CTRL_9(x).U)
|
|
#define HW_IPU_INT_CTRL_9_WR(x, v) (HW_IPU_INT_CTRL_9(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_9_SET(x, v) (HW_IPU_INT_CTRL_9_WR(x, HW_IPU_INT_CTRL_9_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_9_CLR(x, v) (HW_IPU_INT_CTRL_9_WR(x, HW_IPU_INT_CTRL_9_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_9_TOG(x, v) (HW_IPU_INT_CTRL_9_WR(x, HW_IPU_INT_CTRL_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_9, field VDI_FIFO1_OVF_EN[0] (RW)
|
|
*
|
|
* FIFO1 overflow Interrupt1 Enable The VDI C generates FIFO1 overflow interrupt1 when the write
|
|
* pointer of FIFO1 overruns read pointer.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN (0) //!< Bit position for IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN.
|
|
#define BM_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN (0x00000001) //!< Bit mask for IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN) >> BP_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN.
|
|
#define BF_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN) & BM_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FIFO1_OVF_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN(x, v) (HW_IPU_INT_CTRL_9_WR(x, (HW_IPU_INT_CTRL_9_RD(x) & ~BM_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN) | BF_IPU_INT_CTRL_9_VDI_FIFO1_OVF_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_9, field IC_BAYER_BUF_OVF_EN[26] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of the IC Buffer overflow for bayer coming from
|
|
* the IC. The user needs to write 1 to this bit in order to clear it.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN (26) //!< Bit position for IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN.
|
|
#define BM_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN (0x04000000) //!< Bit mask for IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN) >> BP_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN.
|
|
#define BF_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN) & BM_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_BAYER_BUF_OVF_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN(x, v) (HW_IPU_INT_CTRL_9_WR(x, (HW_IPU_INT_CTRL_9_RD(x) & ~BM_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN) | BF_IPU_INT_CTRL_9_IC_BAYER_BUF_OVF_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_9, field IC_ENC_BUF_OVF_EN[27] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of the IC Buffer overflow for encoding coming from
|
|
* the IC. The user needs to write 1 to this bit in order to clear it.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN (27) //!< Bit position for IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN.
|
|
#define BM_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN (0x08000000) //!< Bit mask for IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN) >> BP_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN.
|
|
#define BF_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN) & BM_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_ENC_BUF_OVF_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN(x, v) (HW_IPU_INT_CTRL_9_WR(x, (HW_IPU_INT_CTRL_9_RD(x) & ~BM_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN) | BF_IPU_INT_CTRL_9_IC_ENC_BUF_OVF_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_9, field IC_VF_BUF_OVF_EN[28] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of the IC Buffer overflow for view finder coming
|
|
* from the IC. The user needs to write 1 to this bit in order to clear it.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN (28) //!< Bit position for IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN.
|
|
#define BM_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN (0x10000000) //!< Bit mask for IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN) >> BP_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN.
|
|
#define BF_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN) & BM_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_VF_BUF_OVF_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN(x, v) (HW_IPU_INT_CTRL_9_WR(x, (HW_IPU_INT_CTRL_9_RD(x) & ~BM_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN) | BF_IPU_INT_CTRL_9_IC_VF_BUF_OVF_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_9, field CSI0_PUPE_EN[30] (RW)
|
|
*
|
|
* CSI0_PUPE_EN - CSI0 parameters update error interrupt enable. This bit enables an interrupt that
|
|
* is a result of an error generated by the CSI0. The error is generated in case where new frame
|
|
* arrived from the CSI0 before the completion of the CSI0's parameters update by the SRM
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_9_CSI0_PUPE_EN (30) //!< Bit position for IPU_INT_CTRL_9_CSI0_PUPE_EN.
|
|
#define BM_IPU_INT_CTRL_9_CSI0_PUPE_EN (0x40000000) //!< Bit mask for IPU_INT_CTRL_9_CSI0_PUPE_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_9_CSI0_PUPE_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_9_CSI0_PUPE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_9_CSI0_PUPE_EN) >> BP_IPU_INT_CTRL_9_CSI0_PUPE_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_9_CSI0_PUPE_EN.
|
|
#define BF_IPU_INT_CTRL_9_CSI0_PUPE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_9_CSI0_PUPE_EN) & BM_IPU_INT_CTRL_9_CSI0_PUPE_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_PUPE_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_9_CSI0_PUPE_EN(x, v) (HW_IPU_INT_CTRL_9_WR(x, (HW_IPU_INT_CTRL_9_RD(x) & ~BM_IPU_INT_CTRL_9_CSI0_PUPE_EN) | BF_IPU_INT_CTRL_9_CSI0_PUPE_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_9, field CSI1_PUPE_EN[31] (RW)
|
|
*
|
|
* CSI1_PUPE_EN - CSI1 parameters update error interrupt enable. This bit enables an interrupt that
|
|
* is a result of an error generated by the CSI1. The error is generated in case where new frame
|
|
* arrived from the CSI1 before the completion of the CSI1's parameters update by the SRM
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_9_CSI1_PUPE_EN (31) //!< Bit position for IPU_INT_CTRL_9_CSI1_PUPE_EN.
|
|
#define BM_IPU_INT_CTRL_9_CSI1_PUPE_EN (0x80000000) //!< Bit mask for IPU_INT_CTRL_9_CSI1_PUPE_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_9_CSI1_PUPE_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_9_CSI1_PUPE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_9_CSI1_PUPE_EN) >> BP_IPU_INT_CTRL_9_CSI1_PUPE_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_9_CSI1_PUPE_EN.
|
|
#define BF_IPU_INT_CTRL_9_CSI1_PUPE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_9_CSI1_PUPE_EN) & BM_IPU_INT_CTRL_9_CSI1_PUPE_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_PUPE_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_9_CSI1_PUPE_EN(x, v) (HW_IPU_INT_CTRL_9_WR(x, (HW_IPU_INT_CTRL_9_RD(x) & ~BM_IPU_INT_CTRL_9_CSI1_PUPE_EN) | BF_IPU_INT_CTRL_9_CSI1_PUPE_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_10 - Interrupt Control Register 10
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_10 - Interrupt Control Register 10 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. This register controls error interrupt
|
|
* signals coming from different modules within
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_10
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_10_bitfields
|
|
{
|
|
unsigned SMFC0_FRM_LOST_EN : 1; //!< [0] Frame Lost of SMFC channel 0 interrupt enable bit
|
|
unsigned SMFC1_FRM_LOST_EN : 1; //!< [1] Frame Lost of SMFC channel 1 interrupt enable bit
|
|
unsigned SMFC2_FRM_LOST_EN : 1; //!< [2] Frame Lost of SMFC channel 2 interrupt enable bit
|
|
unsigned SMFC3_FRM_LOST_EN : 1; //!< [3] Frame Lost of SMFC channel 3 interrupt enable bit
|
|
unsigned RESERVED0 : 12; //!< [15:4] Reserved
|
|
unsigned DC_TEARING_ERR_1_EN : 1; //!< [16] Tearing Error #1 enable
|
|
unsigned DC_TEARING_ERR_2_EN : 1; //!< [17] Tearing Error #2 enable
|
|
unsigned DC_TEARING_ERR_6_EN : 1; //!< [18] Tearing Error #6 enable
|
|
unsigned DI0_SYNC_DISP_ERR_EN : 1; //!< [19] DI0 Synchronous display error enable
|
|
unsigned DI1_SYNC_DISP_ERR_EN : 1; //!< [20] DI1 Synchronous display error enable
|
|
unsigned DI0_TIME_OUT_ERR_EN : 1; //!< [21] DI0 time outwore interrupt enable
|
|
unsigned DI1_TIME_OUT_ERR_EN : 1; //!< [22] DI1 time out error interrupt enable
|
|
unsigned RESERVED1 : 1; //!< [23] Reserved
|
|
unsigned IC_VF_FRM_LOST_ERR_EN : 1; //!< [24] This bit enables an interrupt that is a result of IC's view finder frame lost.
|
|
unsigned IC_ENC_FRM_LOST_ERR_EN : 1; //!< [25] This bit enables an interrupt that is a result of IC's encoding frame lost.
|
|
unsigned IC_BAYER_FRM_LOST_ERR_EN : 1; //!< [26] This bit enables an interrupt that is a result of IC's Bayer frame lost.
|
|
unsigned RESERVED2 : 1; //!< [27] Reserved
|
|
unsigned NON_PRIVILEGED_ACC_ERR_EN : 1; //!< [28] Non Privileged Access Error interrupt enable.
|
|
unsigned AXIW_ERR_EN : 1; //!< [29] This bit enables an interrupt that is a result of AXI write access resulted with error response.
|
|
unsigned AXIR_ERR_EN : 1; //!< [30] This bit enables an interrupt that is a result of AXI read access resulted with error response.
|
|
unsigned RESERVED3 : 1; //!< [31] Reserved
|
|
} B;
|
|
} hw_ipu_int_ctrl_10_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_10 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_10_ADDR(x) (REGS_IPU_BASE(x) + 0x60)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_10(x) (*(volatile hw_ipu_int_ctrl_10_t *) HW_IPU_INT_CTRL_10_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_10_RD(x) (HW_IPU_INT_CTRL_10(x).U)
|
|
#define HW_IPU_INT_CTRL_10_WR(x, v) (HW_IPU_INT_CTRL_10(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_10_SET(x, v) (HW_IPU_INT_CTRL_10_WR(x, HW_IPU_INT_CTRL_10_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_10_CLR(x, v) (HW_IPU_INT_CTRL_10_WR(x, HW_IPU_INT_CTRL_10_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_10_TOG(x, v) (HW_IPU_INT_CTRL_10_WR(x, HW_IPU_INT_CTRL_10_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_10 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field SMFC0_FRM_LOST_EN[0] (RW)
|
|
*
|
|
* Frame Lost of SMFC channel 0 interrupt enable bit This bit enables an interrupt that is a result
|
|
* of a Frame Lost of SMFC channel 0.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN (0) //!< Bit position for IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN.
|
|
#define BM_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN (0x00000001) //!< Bit mask for IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN) >> BP_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN.
|
|
#define BF_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN) & BM_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC0_FRM_LOST_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN) | BF_IPU_INT_CTRL_10_SMFC0_FRM_LOST_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field SMFC1_FRM_LOST_EN[1] (RW)
|
|
*
|
|
* Frame Lost of SMFC channel 1 interrupt enable bit This bit enables an interrupt that is a result
|
|
* of a Frame Lost of SMFC channel 1.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN (1) //!< Bit position for IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN.
|
|
#define BM_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN (0x00000002) //!< Bit mask for IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN) >> BP_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN.
|
|
#define BF_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN) & BM_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC1_FRM_LOST_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN) | BF_IPU_INT_CTRL_10_SMFC1_FRM_LOST_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field SMFC2_FRM_LOST_EN[2] (RW)
|
|
*
|
|
* Frame Lost of SMFC channel 2 interrupt enable bit This bit enables an interrupt that is a result
|
|
* of a Frame Lost of SMFC channel 2.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN (2) //!< Bit position for IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN.
|
|
#define BM_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN (0x00000004) //!< Bit mask for IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN) >> BP_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN.
|
|
#define BF_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN) & BM_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC2_FRM_LOST_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN) | BF_IPU_INT_CTRL_10_SMFC2_FRM_LOST_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field SMFC3_FRM_LOST_EN[3] (RW)
|
|
*
|
|
* Frame Lost of SMFC channel 3 interrupt enable bit This bit enables an interrupt that is a result
|
|
* of a Frame Lost of SMFC channel 3.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN (3) //!< Bit position for IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN.
|
|
#define BM_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN (0x00000008) //!< Bit mask for IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN) >> BP_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN.
|
|
#define BF_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN) & BM_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC3_FRM_LOST_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN) | BF_IPU_INT_CTRL_10_SMFC3_FRM_LOST_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DC_TEARING_ERR_1_EN[16] (RW)
|
|
*
|
|
* Tearing Error #1 enable This bit enables the interrupt that is a result of tearing error while
|
|
* the anti tearing mechanism is activated for DC channel 1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN (16) //!< Bit position for IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN.
|
|
#define BM_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN (0x00010000) //!< Bit mask for IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN) >> BP_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN.
|
|
#define BF_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN) & BM_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_TEARING_ERR_1_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN) | BF_IPU_INT_CTRL_10_DC_TEARING_ERR_1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DC_TEARING_ERR_2_EN[17] (RW)
|
|
*
|
|
* Tearing Error #2 enable This bit enables the interrupt that is a result of tearing error while
|
|
* the anti tearing mechanism is activated for DC channel 2
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN (17) //!< Bit position for IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN.
|
|
#define BM_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN (0x00020000) //!< Bit mask for IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN) >> BP_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN.
|
|
#define BF_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN) & BM_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_TEARING_ERR_2_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN) | BF_IPU_INT_CTRL_10_DC_TEARING_ERR_2_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DC_TEARING_ERR_6_EN[18] (RW)
|
|
*
|
|
* Tearing Error #6 enable This bit enables the interrupt that is a result of tearing error while
|
|
* the anti tearing mechanism is activated for DC channel 6
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN (18) //!< Bit position for IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN.
|
|
#define BM_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN (0x00040000) //!< Bit mask for IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN) >> BP_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN.
|
|
#define BF_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN) & BM_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_TEARING_ERR_6_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN) | BF_IPU_INT_CTRL_10_DC_TEARING_ERR_6_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DI0_SYNC_DISP_ERR_EN[19] (RW)
|
|
*
|
|
* DI0 Synchronous display error enable This bit enables the interrupt that is a result of an error
|
|
* during access to a synchronous display via DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN (19) //!< Bit position for IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN.
|
|
#define BM_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN (0x00080000) //!< Bit mask for IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN) >> BP_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN) & BM_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SYNC_DISP_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN) | BF_IPU_INT_CTRL_10_DI0_SYNC_DISP_ERR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DI1_SYNC_DISP_ERR_EN[20] (RW)
|
|
*
|
|
* DI1 Synchronous display error enable This bit enables the interrupt that is a result of an error
|
|
* during access to a synchronous display via DI1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN (20) //!< Bit position for IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN.
|
|
#define BM_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN (0x00100000) //!< Bit mask for IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN) >> BP_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN) & BM_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SYNC_DISP_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN) | BF_IPU_INT_CTRL_10_DI1_SYNC_DISP_ERR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DI0_TIME_OUT_ERR_EN[21] (RW)
|
|
*
|
|
* DI0 time outwore interrupt enable This bit enables the interrupt that is a result of a time out
|
|
* error during a read access via DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN (21) //!< Bit position for IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN.
|
|
#define BM_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN (0x00200000) //!< Bit mask for IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN) >> BP_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN) & BM_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_TIME_OUT_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN) | BF_IPU_INT_CTRL_10_DI0_TIME_OUT_ERR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field DI1_TIME_OUT_ERR_EN[22] (RW)
|
|
*
|
|
* DI1 time out error interrupt enable This bit enables the interrupt that is a result of a time out
|
|
* error during a read access via DI1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN (22) //!< Bit position for IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN.
|
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#define BM_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN (0x00400000) //!< Bit mask for IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN.
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|
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//! @brief Get value of IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN) >> BP_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN) & BM_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_TIME_OUT_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN) | BF_IPU_INT_CTRL_10_DI1_TIME_OUT_ERR_EN(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_10, field IC_VF_FRM_LOST_ERR_EN[24] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of IC's view finder frame lost.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN (24) //!< Bit position for IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN.
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|
#define BM_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN (0x01000000) //!< Bit mask for IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN.
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|
|
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//! @brief Get value of IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN) >> BP_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN) & BM_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_VF_FRM_LOST_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN) | BF_IPU_INT_CTRL_10_IC_VF_FRM_LOST_ERR_EN(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_10, field IC_ENC_FRM_LOST_ERR_EN[25] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of IC's encoding frame lost.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN (25) //!< Bit position for IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN.
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|
#define BM_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN (0x02000000) //!< Bit mask for IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN.
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|
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//! @brief Get value of IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN) >> BP_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN)
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|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN) & BM_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_ENC_FRM_LOST_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN) | BF_IPU_INT_CTRL_10_IC_ENC_FRM_LOST_ERR_EN(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_CTRL_10, field IC_BAYER_FRM_LOST_ERR_EN[26] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of IC's Bayer frame lost.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN (26) //!< Bit position for IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN.
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|
#define BM_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN (0x04000000) //!< Bit mask for IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN.
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|
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|
//! @brief Get value of IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN from a register value.
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|
#define BG_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN) >> BP_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN)
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|
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|
//! @brief Format value for bitfield IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN) & BM_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_BAYER_FRM_LOST_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN) | BF_IPU_INT_CTRL_10_IC_BAYER_FRM_LOST_ERR_EN(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field NON_PRIVILEGED_ACC_ERR_EN[28] (RW)
|
|
*
|
|
* Non Privileged Access Error interrupt enable. The CPMEM and the DP can be accessed by the ARM
|
|
* platform in privileged mode only HPROT[1] =1. An attempt to access these regions in user mode
|
|
* will issue an interrupt. This bit enables the interrupt.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN (28) //!< Bit position for IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN.
|
|
#define BM_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN (0x10000000) //!< Bit mask for IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN) >> BP_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN) & BM_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NON_PRIVILEGED_ACC_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN) | BF_IPU_INT_CTRL_10_NON_PRIVILEGED_ACC_ERR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field AXIW_ERR_EN[29] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of AXI write access resulted with error response.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_AXIW_ERR_EN (29) //!< Bit position for IPU_INT_CTRL_10_AXIW_ERR_EN.
|
|
#define BM_IPU_INT_CTRL_10_AXIW_ERR_EN (0x20000000) //!< Bit mask for IPU_INT_CTRL_10_AXIW_ERR_EN.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_10_AXIW_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_AXIW_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_AXIW_ERR_EN) >> BP_IPU_INT_CTRL_10_AXIW_ERR_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_AXIW_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_AXIW_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_AXIW_ERR_EN) & BM_IPU_INT_CTRL_10_AXIW_ERR_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AXIW_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_AXIW_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_AXIW_ERR_EN) | BF_IPU_INT_CTRL_10_AXIW_ERR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_10, field AXIR_ERR_EN[30] (RW)
|
|
*
|
|
* This bit enables an interrupt that is a result of AXI read access resulted with error response.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_10_AXIR_ERR_EN (30) //!< Bit position for IPU_INT_CTRL_10_AXIR_ERR_EN.
|
|
#define BM_IPU_INT_CTRL_10_AXIR_ERR_EN (0x40000000) //!< Bit mask for IPU_INT_CTRL_10_AXIR_ERR_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_10_AXIR_ERR_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_10_AXIR_ERR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_10_AXIR_ERR_EN) >> BP_IPU_INT_CTRL_10_AXIR_ERR_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_10_AXIR_ERR_EN.
|
|
#define BF_IPU_INT_CTRL_10_AXIR_ERR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_10_AXIR_ERR_EN) & BM_IPU_INT_CTRL_10_AXIR_ERR_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AXIR_ERR_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_10_AXIR_ERR_EN(x, v) (HW_IPU_INT_CTRL_10_WR(x, (HW_IPU_INT_CTRL_10_RD(x) & ~BM_IPU_INT_CTRL_10_AXIR_ERR_EN) | BF_IPU_INT_CTRL_10_AXIR_ERR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_11 - Interrupt Control Register 11
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_11 - Interrupt Control Register 11 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of the end-of-band
|
|
* indication (EOBND) of DMA Channels interrupts [31:0] can be found in this register. Hide
|
|
* VDOA_SYNC for all versions Show VDOA_SYNC for IPUv3H version. The table below tagged with other
|
|
* settings (like IPU3M_only) should be hidden in IPUv3H version.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_11
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_11_bitfields
|
|
{
|
|
unsigned IDMAC_EOBND_EN_0 : 1; //!< [0] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_1 : 1; //!< [1] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_2 : 1; //!< [2] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_3 : 1; //!< [3] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_EOBND_EN_5 : 1; //!< [5] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED1 : 5; //!< [10:6] Reserved.
|
|
unsigned IDMAC_EOBND_EN_11 : 1; //!< [11] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_12 : 1; //!< [12] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED2 : 7; //!< [19:13] Reserved.
|
|
unsigned IDMAC_EOBND_EN_20 : 1; //!< [20] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_21 : 1; //!< [21] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_22 : 1; //!< [22] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED3 : 2; //!< [24:23] Reserved.
|
|
unsigned IDMAC_EOBND_EN_25 : 1; //!< [25] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_26 : 1; //!< [26] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED4 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_11_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_11 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_11_ADDR(x) (REGS_IPU_BASE(x) + 0x64)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_11(x) (*(volatile hw_ipu_int_ctrl_11_t *) HW_IPU_INT_CTRL_11_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_11_RD(x) (HW_IPU_INT_CTRL_11(x).U)
|
|
#define HW_IPU_INT_CTRL_11_WR(x, v) (HW_IPU_INT_CTRL_11(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_11_SET(x, v) (HW_IPU_INT_CTRL_11_WR(x, HW_IPU_INT_CTRL_11_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_11_CLR(x, v) (HW_IPU_INT_CTRL_11_WR(x, HW_IPU_INT_CTRL_11_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_11_TOG(x, v) (HW_IPU_INT_CTRL_11_WR(x, HW_IPU_INT_CTRL_11_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_11 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_0[0] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0 (0) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_0.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0 (0x00000001) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_0.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_0 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_0.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_0 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_1[1] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1 (1) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_1.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1 (0x00000002) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_1.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_1 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_1.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_1 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_2[2] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2 (2) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_2.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2 (0x00000004) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_2.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_2 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_2.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_2 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_3[3] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3 (3) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_3.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3 (0x00000008) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_3.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_3 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_3.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_3 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_5[5] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5 (5) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_5.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5 (0x00000020) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_5.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_5 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_5.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_5 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_11[11] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11 (11) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_11.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11 (0x00000800) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_11.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_11 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_11.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_11 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_12[12] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12 (12) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_12.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12 (0x00001000) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_12.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_12 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_12.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_12 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_20[20] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20 (20) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_20.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20 (0x00100000) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_20.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_20 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_20.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_20 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_21[21] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21 (21) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_21.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21 (0x00200000) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_21.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_21 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_21.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_21 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_22[22] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22 (22) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_22.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22 (0x00400000) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_22.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_22 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_22.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_22 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_25[25] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25 (25) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_25.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25 (0x02000000) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_25 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_25.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_25 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_11, field IDMAC_EOBND_EN_26[26] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control of end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26 (26) //!< Bit position for IPU_INT_CTRL_11_IDMAC_EOBND_EN_26.
|
|
#define BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26 (0x04000000) //!< Bit mask for IPU_INT_CTRL_11_IDMAC_EOBND_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_11_IDMAC_EOBND_EN_26 from a register value.
|
|
#define BG_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26) >> BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_11_IDMAC_EOBND_EN_26.
|
|
#define BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26) & BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_26 field to a new value.
|
|
#define BW_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26(x, v) (HW_IPU_INT_CTRL_11_WR(x, (HW_IPU_INT_CTRL_11_RD(x) & ~BM_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26) | BF_IPU_INT_CTRL_11_IDMAC_EOBND_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_12 - Interrupt Control Register 12
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_12 - Interrupt Control Register 12 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of the end-of-band
|
|
* indication (EOBND) of DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_12
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_12_bitfields
|
|
{
|
|
unsigned RESERVED0 : 13; //!< [12:0] Reserved.
|
|
unsigned IDMAC_EOBND_EN_45 : 1; //!< [13] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_46 : 1; //!< [14] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_47 : 1; //!< [15] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_48 : 1; //!< [16] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_49 : 1; //!< [17] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_50 : 1; //!< [18] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_12_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_12 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_12_ADDR(x) (REGS_IPU_BASE(x) + 0x68)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_12(x) (*(volatile hw_ipu_int_ctrl_12_t *) HW_IPU_INT_CTRL_12_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_12_RD(x) (HW_IPU_INT_CTRL_12(x).U)
|
|
#define HW_IPU_INT_CTRL_12_WR(x, v) (HW_IPU_INT_CTRL_12(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_12_SET(x, v) (HW_IPU_INT_CTRL_12_WR(x, HW_IPU_INT_CTRL_12_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_12_CLR(x, v) (HW_IPU_INT_CTRL_12_WR(x, HW_IPU_INT_CTRL_12_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_12_TOG(x, v) (HW_IPU_INT_CTRL_12_WR(x, HW_IPU_INT_CTRL_12_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_12 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_12, field IDMAC_EOBND_EN_45[13] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45 (13) //!< Bit position for IPU_INT_CTRL_12_IDMAC_EOBND_EN_45.
|
|
#define BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45 (0x00002000) //!< Bit mask for IPU_INT_CTRL_12_IDMAC_EOBND_EN_45.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_12_IDMAC_EOBND_EN_45 from a register value.
|
|
#define BG_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45) >> BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_12_IDMAC_EOBND_EN_45.
|
|
#define BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_45 field to a new value.
|
|
#define BW_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45(x, v) (HW_IPU_INT_CTRL_12_WR(x, (HW_IPU_INT_CTRL_12_RD(x) & ~BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45) | BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_12, field IDMAC_EOBND_EN_46[14] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46 (14) //!< Bit position for IPU_INT_CTRL_12_IDMAC_EOBND_EN_46.
|
|
#define BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46 (0x00004000) //!< Bit mask for IPU_INT_CTRL_12_IDMAC_EOBND_EN_46.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_12_IDMAC_EOBND_EN_46 from a register value.
|
|
#define BG_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46) >> BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_12_IDMAC_EOBND_EN_46.
|
|
#define BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_46 field to a new value.
|
|
#define BW_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46(x, v) (HW_IPU_INT_CTRL_12_WR(x, (HW_IPU_INT_CTRL_12_RD(x) & ~BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46) | BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_12, field IDMAC_EOBND_EN_47[15] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47 (15) //!< Bit position for IPU_INT_CTRL_12_IDMAC_EOBND_EN_47.
|
|
#define BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47 (0x00008000) //!< Bit mask for IPU_INT_CTRL_12_IDMAC_EOBND_EN_47.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_12_IDMAC_EOBND_EN_47 from a register value.
|
|
#define BG_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47) >> BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_12_IDMAC_EOBND_EN_47.
|
|
#define BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_47 field to a new value.
|
|
#define BW_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47(x, v) (HW_IPU_INT_CTRL_12_WR(x, (HW_IPU_INT_CTRL_12_RD(x) & ~BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47) | BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_12, field IDMAC_EOBND_EN_48[16] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48 (16) //!< Bit position for IPU_INT_CTRL_12_IDMAC_EOBND_EN_48.
|
|
#define BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48 (0x00010000) //!< Bit mask for IPU_INT_CTRL_12_IDMAC_EOBND_EN_48.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_12_IDMAC_EOBND_EN_48 from a register value.
|
|
#define BG_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48) >> BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_12_IDMAC_EOBND_EN_48.
|
|
#define BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_48 field to a new value.
|
|
#define BW_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48(x, v) (HW_IPU_INT_CTRL_12_WR(x, (HW_IPU_INT_CTRL_12_RD(x) & ~BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48) | BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_12, field IDMAC_EOBND_EN_49[17] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49 (17) //!< Bit position for IPU_INT_CTRL_12_IDMAC_EOBND_EN_49.
|
|
#define BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49 (0x00020000) //!< Bit mask for IPU_INT_CTRL_12_IDMAC_EOBND_EN_49.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_12_IDMAC_EOBND_EN_49 from a register value.
|
|
#define BG_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49) >> BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_12_IDMAC_EOBND_EN_49.
|
|
#define BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_49 field to a new value.
|
|
#define BW_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49(x, v) (HW_IPU_INT_CTRL_12_WR(x, (HW_IPU_INT_CTRL_12_RD(x) & ~BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49) | BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_12, field IDMAC_EOBND_EN_50[18] (RW)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the control end-of-band interrupt of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50 (18) //!< Bit position for IPU_INT_CTRL_12_IDMAC_EOBND_EN_50.
|
|
#define BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50 (0x00040000) //!< Bit mask for IPU_INT_CTRL_12_IDMAC_EOBND_EN_50.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_12_IDMAC_EOBND_EN_50 from a register value.
|
|
#define BG_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50) >> BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_12_IDMAC_EOBND_EN_50.
|
|
#define BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50) & BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_50 field to a new value.
|
|
#define BW_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50(x, v) (HW_IPU_INT_CTRL_12_WR(x, (HW_IPU_INT_CTRL_12_RD(x) & ~BM_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50) | BF_IPU_INT_CTRL_12_IDMAC_EOBND_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_13 - Interrupt Control Register 13
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_13 - Interrupt Control Register 13 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of the threshold crossing
|
|
* indication (TH) of DMA Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_13
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_13_bitfields
|
|
{
|
|
unsigned IDMAC_TH_EN_0 : 1; //!< [0] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_1 : 1; //!< [1] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_2 : 1; //!< [2] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_3 : 1; //!< [3] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_TH_EN_5 : 1; //!< [5] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_TH_EN_8 : 1; //!< [8] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_9 : 1; //!< [9] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_10 : 1; //!< [10] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_11 : 1; //!< [11] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_12 : 1; //!< [12] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_13 : 1; //!< [13] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_14 : 1; //!< [14] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_15 : 1; //!< [15] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_TH_EN_17 : 1; //!< [17] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_18 : 1; //!< [18] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_19 : 1; //!< [19] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_20 : 1; //!< [20] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_21 : 1; //!< [21] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_22 : 1; //!< [22] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_23 : 1; //!< [23] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_24 : 1; //!< [24] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_25 : 1; //!< [25] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_26 : 1; //!< [26] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_27 : 1; //!< [27] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_28 : 1; //!< [28] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_29 : 1; //!< [29] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_TH_EN_31 : 1; //!< [31] Threshold crossing indication of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_ctrl_13_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_13 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_13_ADDR(x) (REGS_IPU_BASE(x) + 0x6c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_13(x) (*(volatile hw_ipu_int_ctrl_13_t *) HW_IPU_INT_CTRL_13_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_13_RD(x) (HW_IPU_INT_CTRL_13(x).U)
|
|
#define HW_IPU_INT_CTRL_13_WR(x, v) (HW_IPU_INT_CTRL_13(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_13_SET(x, v) (HW_IPU_INT_CTRL_13_WR(x, HW_IPU_INT_CTRL_13_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_13_CLR(x, v) (HW_IPU_INT_CTRL_13_WR(x, HW_IPU_INT_CTRL_13_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_13_TOG(x, v) (HW_IPU_INT_CTRL_13_WR(x, HW_IPU_INT_CTRL_13_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_13 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_0[0] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_0 (0) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_0.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_0 (0x00000001) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_0.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_0 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_0) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_0.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_0) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_0 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_0(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_0) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_1[1] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_1 (1) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_1.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_1 (0x00000002) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_1.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_1 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_1) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_1)
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//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_1.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_1) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_1 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_1(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_1) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_1(v)))
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|
#endif
|
|
//@}
|
|
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/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_2[2] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_2 (2) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_2.
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#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_2 (0x00000004) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_2.
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|
|
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//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_2 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_2) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_2)
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//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_2.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_2) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_2 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_2(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_2) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_2(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_3[3] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_3 (3) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_3.
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#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_3 (0x00000008) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_3.
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|
|
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//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_3 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_3) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_3)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_3.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_3) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_3 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_3(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_3) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_5[5] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_5 (5) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_5.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_5 (0x00000020) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_5.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_5 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_5) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_5.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_5) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_5 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_5(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_5) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_8[8] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_8 (8) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_8.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_8 (0x00000100) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_8.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_8 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_8) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_8.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_8) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_8 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_8(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_8) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_9[9] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_9 (9) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_9.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_9 (0x00000200) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_9.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_9 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_9) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_9.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_9) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_9 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_9(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_9) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_10[10] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_10 (10) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_10.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_10 (0x00000400) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_10.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_10 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_10) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_10.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_10) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_10 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_10(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_10) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_11[11] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_11 (11) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_11.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_11 (0x00000800) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_11.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_11 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_11) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_11.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_11) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_11 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_11(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_11) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_12[12] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_12 (12) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_12.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_12 (0x00001000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_12.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_12 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_12) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_12.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_12) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_12 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_12(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_12) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_13[13] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_13 (13) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_13.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_13 (0x00002000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_13.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_13 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_13) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_13.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_13) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_13 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_13(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_13) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_14[14] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_14 (14) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_14.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_14 (0x00004000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_14.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_14 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_14) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_14.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_14) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_14 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_14(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_14) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_15[15] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_15 (15) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_15.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_15 (0x00008000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_15.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_15 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_15) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_15.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_15) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_15)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_15 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_15(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_15) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_17[17] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_17 (17) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_17.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_17 (0x00020000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_17.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_17 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_17) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_17)
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|
|
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//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_17.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_17) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_17)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_17 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_17(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_17) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_17(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_18[18] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_18 (18) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_18.
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|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_18 (0x00040000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_18.
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|
|
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//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_18 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_18) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_18)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_18.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_18) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_18)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_18 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_18(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_18) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_19[19] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_19 (19) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_19.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_19 (0x00080000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_19.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_19 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_19) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_19)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_19.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_19) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_19 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_19(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_19) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_20[20] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_20 (20) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_20.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_20 (0x00100000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_20.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_20 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_20) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_20.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_20) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_20 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_20(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_20) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_21[21] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_21 (21) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_21.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_21 (0x00200000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_21.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_21 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_21) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_21.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_21) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_21 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_21(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_21) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_22[22] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_22 (22) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_22.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_22 (0x00400000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_22.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_22 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_22) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_22.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_22) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_22 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_22(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_22) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_23[23] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_23 (23) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_23.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_23 (0x00800000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_23.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_23 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_23) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_23.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_23) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_23 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_23(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_23) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_24[24] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_24 (24) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_24.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_24 (0x01000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_24.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_24 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_24) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_24.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_24) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_24 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_24(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_24) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_25[25] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_25 (25) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_25.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_25 (0x02000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_25 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_25) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_25.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_25) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_25 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_25(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_25) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_26[26] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_26 (26) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_26.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_26 (0x04000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_26 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_26) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_26.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_26) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_26 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_26(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_26) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_27[27] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_27 (27) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_27.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_27 (0x08000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_27.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_27 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_27) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_27.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_27) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_27 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_27(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_27) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_28[28] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_28 (28) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_28.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_28 (0x10000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_28.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_28 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_28) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_28.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_28) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_28 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_28(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_28) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_29[29] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_29 (29) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_29.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_29 (0x20000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_29.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_29 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_29) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_29.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_29) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_29 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_29(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_29) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_13, field IDMAC_TH_EN_31[31] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control of Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_13_IDMAC_TH_EN_31 (31) //!< Bit position for IPU_INT_CTRL_13_IDMAC_TH_EN_31.
|
|
#define BM_IPU_INT_CTRL_13_IDMAC_TH_EN_31 (0x80000000) //!< Bit mask for IPU_INT_CTRL_13_IDMAC_TH_EN_31.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_13_IDMAC_TH_EN_31 from a register value.
|
|
#define BG_IPU_INT_CTRL_13_IDMAC_TH_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_31) >> BP_IPU_INT_CTRL_13_IDMAC_TH_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_13_IDMAC_TH_EN_31.
|
|
#define BF_IPU_INT_CTRL_13_IDMAC_TH_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_13_IDMAC_TH_EN_31) & BM_IPU_INT_CTRL_13_IDMAC_TH_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_31 field to a new value.
|
|
#define BW_IPU_INT_CTRL_13_IDMAC_TH_EN_31(x, v) (HW_IPU_INT_CTRL_13_WR(x, (HW_IPU_INT_CTRL_13_RD(x) & ~BM_IPU_INT_CTRL_13_IDMAC_TH_EN_31) | BF_IPU_INT_CTRL_13_IDMAC_TH_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_14 - Interrupt Control Register 14
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_14 - Interrupt Control Register 14 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of the Threshold crossing
|
|
* indication (TH) of DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_14
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_14_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_TH_EN_33 : 1; //!< [1] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_TH_EN_40 : 1; //!< [8] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_41 : 1; //!< [9] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_42 : 1; //!< [10] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_43 : 1; //!< [11] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_44 : 1; //!< [12] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_45 : 1; //!< [13] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_46 : 1; //!< [14] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_47 : 1; //!< [15] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_48 : 1; //!< [16] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_49 : 1; //!< [17] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_50 : 1; //!< [18] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_51 : 1; //!< [19] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_EN_52 : 1; //!< [20] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_ctrl_14_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_14 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_14_ADDR(x) (REGS_IPU_BASE(x) + 0x70)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_14(x) (*(volatile hw_ipu_int_ctrl_14_t *) HW_IPU_INT_CTRL_14_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_14_RD(x) (HW_IPU_INT_CTRL_14(x).U)
|
|
#define HW_IPU_INT_CTRL_14_WR(x, v) (HW_IPU_INT_CTRL_14(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_14_SET(x, v) (HW_IPU_INT_CTRL_14_WR(x, HW_IPU_INT_CTRL_14_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_14_CLR(x, v) (HW_IPU_INT_CTRL_14_WR(x, HW_IPU_INT_CTRL_14_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_14_TOG(x, v) (HW_IPU_INT_CTRL_14_WR(x, HW_IPU_INT_CTRL_14_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_14 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_33[1] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_33 (1) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_33.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_33 (0x00000002) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_33.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_33 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_33) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_33.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_33) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_33 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_33(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_33) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_40[8] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_40 (8) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_40.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_40 (0x00000100) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_40.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_40 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_40) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_40.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_40) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_40 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_40(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_40) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_41[9] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_41 (9) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_41.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_41 (0x00000200) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_41.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_41 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_41) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_41.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_41) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_41 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_41(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_41) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_42[10] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_42 (10) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_42.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_42 (0x00000400) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_42.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_42 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_42) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_42.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_42) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_42 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_42(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_42) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_43[11] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_43 (11) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_43.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_43 (0x00000800) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_43.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_43 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_43) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_43.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_43) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_43 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_43(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_43) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_44[12] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_44 (12) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_44.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_44 (0x00001000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_44.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_44 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_44) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_44.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_44) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_44 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_44(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_44) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_45[13] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_45 (13) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_45.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_45 (0x00002000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_45.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_45 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_45) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_45.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_45) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_45 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_45(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_45) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_46[14] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_46 (14) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_46.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_46 (0x00004000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_46.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_46 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_46) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_46.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_46) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_46 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_46(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_46) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_47[15] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_47 (15) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_47.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_47 (0x00008000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_47.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_47 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_47) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_47.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_47) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_47 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_47(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_47) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_48[16] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_48 (16) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_48.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_48 (0x00010000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_48.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_48 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_48) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_48.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_48) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_48 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_48(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_48) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_49[17] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_49 (17) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_49.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_49 (0x00020000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_49.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_49 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_49) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_49.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_49) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_49 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_49(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_49) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_50[18] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_50 (18) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_50.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_50 (0x00040000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_50.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_50 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_50) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_50.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_50) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_50 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_50(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_50) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_51[19] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_51 (19) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_51.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_51 (0x00080000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_51.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_51 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_51) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_51.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_51) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_51 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_51(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_51) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_14, field IDMAC_TH_EN_52[20] (RW)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the control Threshold crossing
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_14_IDMAC_TH_EN_52 (20) //!< Bit position for IPU_INT_CTRL_14_IDMAC_TH_EN_52.
|
|
#define BM_IPU_INT_CTRL_14_IDMAC_TH_EN_52 (0x00100000) //!< Bit mask for IPU_INT_CTRL_14_IDMAC_TH_EN_52.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_14_IDMAC_TH_EN_52 from a register value.
|
|
#define BG_IPU_INT_CTRL_14_IDMAC_TH_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_52) >> BP_IPU_INT_CTRL_14_IDMAC_TH_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_14_IDMAC_TH_EN_52.
|
|
#define BF_IPU_INT_CTRL_14_IDMAC_TH_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_14_IDMAC_TH_EN_52) & BM_IPU_INT_CTRL_14_IDMAC_TH_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_EN_52 field to a new value.
|
|
#define BW_IPU_INT_CTRL_14_IDMAC_TH_EN_52(x, v) (HW_IPU_INT_CTRL_14_WR(x, (HW_IPU_INT_CTRL_14_RD(x) & ~BM_IPU_INT_CTRL_14_IDMAC_TH_EN_52) | BF_IPU_INT_CTRL_14_IDMAC_TH_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_CTRL_15 - Interrupt Control Register15
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_CTRL_15 - Interrupt Control Register15 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU interrupts controls. The controls of general purpose
|
|
* interrupts can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_ctrl_15
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_ctrl_15_bitfields
|
|
{
|
|
unsigned SNOOPING1_INT_EN : 1; //!< [0] IPU snooping 1 interrupt enable bit.
|
|
unsigned SNOOPING2_INT_EN : 1; //!< [1] IPU snooping 2 interrupt enable bit.
|
|
unsigned DP_SF_START_EN : 1; //!< [2] DP Sync Flow Start enable bit.
|
|
unsigned DP_SF_END_EN : 1; //!< [3] DP Sync Flow End enable bit.
|
|
unsigned DP_ASF_START_EN : 1; //!< [4] DP Async Flow Start enable bit.
|
|
unsigned DP_ASF_END_EN : 1; //!< [5] DP Async Flow End enable bit.
|
|
unsigned DP_SF_BRAKE_EN : 1; //!< [6] DP Sync Flow Brake enable bit.
|
|
unsigned DP_ASF_BRAKE_EN : 1; //!< [7] DP Async Flow Brake enable bit.
|
|
unsigned DC_FC_0_EN : 1; //!< [8] This bit enables they'd Frame Complete on channel #0 interrupt
|
|
unsigned DC_FC_1_EN : 1; //!< [9] This bit enables they'd Frame Complete on channel #1 interrupt
|
|
unsigned DC_FC_2_EN : 1; //!< [10] This bit enables the DC Frame Complete on channel #2 interrupt
|
|
unsigned DC_FC_3_EN : 1; //!< [11] This bit enables the DC Frame Complete on channel #3 interrupt
|
|
unsigned DC_FC_4_EN : 1; //!< [12] This bit enables the DC Frame Complete on channel #4 interrupt
|
|
unsigned DC_FC_6_EN : 1; //!< [13] This bit enables the DC Frame Complete on channel #6 interrupt
|
|
unsigned DI_VSYNC_PRE_0_EN : 1; //!< [14] This bit enables the DI0 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC sent to the display
|
|
unsigned DI_VSYNC_PRE_1_EN : 1; //!< [15] This bit enables the DI1 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC sent to the display
|
|
unsigned DC_DP_START_EN : 1; //!< [16] This bit enables the interrupt asserted anytime the DP start a new sync or async flow or when an async flow is interrupted by a sync flow
|
|
unsigned DC_ASYNC_STOP_EN : 1; //!< [17] This bit enables the interrupt asserted anytime the DP stops an async flow and moves to a sync flow
|
|
unsigned DI0_CNT_EN_PRE_0_EN : 1; //!< [18] This bit enables the interrupt that is a result of a trigger generated by counter #0 of DI0
|
|
unsigned DI0_CNT_EN_PRE_1_EN : 1; //!< [19] This bit enables the interrupt that is a result of a trigger generated by counter #1 of DI0
|
|
unsigned DI0_CNT_EN_PRE_2_EN : 1; //!< [20] This bit enables the interrupt that is a result of a trigger generated by counter #2 of DI0
|
|
unsigned DI0_CNT_EN_PRE_3_EN : 1; //!< [21] This bit enables the interrupt that is a result of a trigger generated by counter #3 of DI0
|
|
unsigned DI0_CNT_EN_PRE_4_EN : 1; //!< [22] This bit enables the interrupt that is a result of a trigger generated by counter #4 of DI0
|
|
unsigned DI0_CNT_EN_PRE_5_EN : 1; //!< [23] This bit enables the interrupt that is a result of a trigger generated by counter #5 of DI0
|
|
unsigned DI0_CNT_EN_PRE_6_EN : 1; //!< [24] This bit enables the interrupt that is a result of a trigger generated by counter #6 of DI0
|
|
unsigned DI0_CNT_EN_PRE_7_EN : 1; //!< [25] This bit enables the interrupt that is a result of a trigger generated by counter #7 of DI0
|
|
unsigned DI0_CNT_EN_PRE_8_EN : 1; //!< [26] This bit enables the interrupt that is a result of a trigger generated by counter #8 of DI0
|
|
unsigned DI0_CNT_EN_PRE_9_EN : 1; //!< [27] This bit enables the interrupt that is a result of a trigger generated by counter #9 of DI0
|
|
unsigned DI0_CNT_EN_PRE_10_EN : 1; //!< [28] This bit enables the interrupt that is a result of a trigger generated by counter #10 of DI0
|
|
unsigned DI1_DISP_CLK_EN_PRE_EN : 1; //!< [29] DI1_DISP_CLK_EN_PRE_EN
|
|
unsigned DI1_CNT_EN_PRE_3_EN : 1; //!< [30] This bit enables the interrupt that is a result of a trigger generated by counter #3 of DI1
|
|
unsigned DI1_CNT_EN_PRE_8_EN : 1; //!< [31] This bit enables the interrupt that is a result of a trigger generated by counter #8 of DI1
|
|
} B;
|
|
} hw_ipu_int_ctrl_15_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_CTRL_15 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_CTRL_15_ADDR(x) (REGS_IPU_BASE(x) + 0x74)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_CTRL_15(x) (*(volatile hw_ipu_int_ctrl_15_t *) HW_IPU_INT_CTRL_15_ADDR(x))
|
|
#define HW_IPU_INT_CTRL_15_RD(x) (HW_IPU_INT_CTRL_15(x).U)
|
|
#define HW_IPU_INT_CTRL_15_WR(x, v) (HW_IPU_INT_CTRL_15(x).U = (v))
|
|
#define HW_IPU_INT_CTRL_15_SET(x, v) (HW_IPU_INT_CTRL_15_WR(x, HW_IPU_INT_CTRL_15_RD(x) | (v)))
|
|
#define HW_IPU_INT_CTRL_15_CLR(x, v) (HW_IPU_INT_CTRL_15_WR(x, HW_IPU_INT_CTRL_15_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_CTRL_15_TOG(x, v) (HW_IPU_INT_CTRL_15_WR(x, HW_IPU_INT_CTRL_15_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_CTRL_15 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field SNOOPING1_INT_EN[0] (RW)
|
|
*
|
|
* IPU snooping 1 interrupt enable bit. This bit enables the interrupt that is a result of the
|
|
* detection of a snooping 1 signal assertion coming to the IPU
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_SNOOPING1_INT_EN (0) //!< Bit position for IPU_INT_CTRL_15_SNOOPING1_INT_EN.
|
|
#define BM_IPU_INT_CTRL_15_SNOOPING1_INT_EN (0x00000001) //!< Bit mask for IPU_INT_CTRL_15_SNOOPING1_INT_EN.
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//! @brief Get value of IPU_INT_CTRL_15_SNOOPING1_INT_EN from a register value.
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#define BG_IPU_INT_CTRL_15_SNOOPING1_INT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_SNOOPING1_INT_EN) >> BP_IPU_INT_CTRL_15_SNOOPING1_INT_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_SNOOPING1_INT_EN.
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#define BF_IPU_INT_CTRL_15_SNOOPING1_INT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_SNOOPING1_INT_EN) & BM_IPU_INT_CTRL_15_SNOOPING1_INT_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SNOOPING1_INT_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_SNOOPING1_INT_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_SNOOPING1_INT_EN) | BF_IPU_INT_CTRL_15_SNOOPING1_INT_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field SNOOPING2_INT_EN[1] (RW)
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*
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* IPU snooping 2 interrupt enable bit. This bit enables the interrupt that is a result of the
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* detection of a snooping 2 signal assertion coming to the IPU
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_SNOOPING2_INT_EN (1) //!< Bit position for IPU_INT_CTRL_15_SNOOPING2_INT_EN.
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#define BM_IPU_INT_CTRL_15_SNOOPING2_INT_EN (0x00000002) //!< Bit mask for IPU_INT_CTRL_15_SNOOPING2_INT_EN.
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//! @brief Get value of IPU_INT_CTRL_15_SNOOPING2_INT_EN from a register value.
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#define BG_IPU_INT_CTRL_15_SNOOPING2_INT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_SNOOPING2_INT_EN) >> BP_IPU_INT_CTRL_15_SNOOPING2_INT_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_SNOOPING2_INT_EN.
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#define BF_IPU_INT_CTRL_15_SNOOPING2_INT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_SNOOPING2_INT_EN) & BM_IPU_INT_CTRL_15_SNOOPING2_INT_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SNOOPING2_INT_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_SNOOPING2_INT_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_SNOOPING2_INT_EN) | BF_IPU_INT_CTRL_15_SNOOPING2_INT_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DP_SF_START_EN[2] (RW)
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*
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* DP Sync Flow Start enable bit. This bit enables the interrupt that is a result of the Sync flow
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* start at the DP
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DP_SF_START_EN (2) //!< Bit position for IPU_INT_CTRL_15_DP_SF_START_EN.
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#define BM_IPU_INT_CTRL_15_DP_SF_START_EN (0x00000004) //!< Bit mask for IPU_INT_CTRL_15_DP_SF_START_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DP_SF_START_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DP_SF_START_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DP_SF_START_EN) >> BP_IPU_INT_CTRL_15_DP_SF_START_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DP_SF_START_EN.
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#define BF_IPU_INT_CTRL_15_DP_SF_START_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DP_SF_START_EN) & BM_IPU_INT_CTRL_15_DP_SF_START_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_SF_START_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DP_SF_START_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DP_SF_START_EN) | BF_IPU_INT_CTRL_15_DP_SF_START_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DP_SF_END_EN[3] (RW)
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*
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* DP Sync Flow End enable bit. This bit enables the interrupt that is a result of the Sync flow end
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* at the DP
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DP_SF_END_EN (3) //!< Bit position for IPU_INT_CTRL_15_DP_SF_END_EN.
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#define BM_IPU_INT_CTRL_15_DP_SF_END_EN (0x00000008) //!< Bit mask for IPU_INT_CTRL_15_DP_SF_END_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DP_SF_END_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DP_SF_END_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DP_SF_END_EN) >> BP_IPU_INT_CTRL_15_DP_SF_END_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DP_SF_END_EN.
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#define BF_IPU_INT_CTRL_15_DP_SF_END_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DP_SF_END_EN) & BM_IPU_INT_CTRL_15_DP_SF_END_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_SF_END_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DP_SF_END_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DP_SF_END_EN) | BF_IPU_INT_CTRL_15_DP_SF_END_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DP_ASF_START_EN[4] (RW)
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*
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* DP Async Flow Start enable bit. This bit enables the interrupt that is a result of the Async flow
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* start at the DP
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DP_ASF_START_EN (4) //!< Bit position for IPU_INT_CTRL_15_DP_ASF_START_EN.
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#define BM_IPU_INT_CTRL_15_DP_ASF_START_EN (0x00000010) //!< Bit mask for IPU_INT_CTRL_15_DP_ASF_START_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DP_ASF_START_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DP_ASF_START_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DP_ASF_START_EN) >> BP_IPU_INT_CTRL_15_DP_ASF_START_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DP_ASF_START_EN.
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#define BF_IPU_INT_CTRL_15_DP_ASF_START_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DP_ASF_START_EN) & BM_IPU_INT_CTRL_15_DP_ASF_START_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_ASF_START_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DP_ASF_START_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DP_ASF_START_EN) | BF_IPU_INT_CTRL_15_DP_ASF_START_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DP_ASF_END_EN[5] (RW)
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*
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* DP Async Flow End enable bit. This bit enables the interrupt that is a result of the Async flow
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* end at the DP
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DP_ASF_END_EN (5) //!< Bit position for IPU_INT_CTRL_15_DP_ASF_END_EN.
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#define BM_IPU_INT_CTRL_15_DP_ASF_END_EN (0x00000020) //!< Bit mask for IPU_INT_CTRL_15_DP_ASF_END_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DP_ASF_END_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DP_ASF_END_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DP_ASF_END_EN) >> BP_IPU_INT_CTRL_15_DP_ASF_END_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DP_ASF_END_EN.
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#define BF_IPU_INT_CTRL_15_DP_ASF_END_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DP_ASF_END_EN) & BM_IPU_INT_CTRL_15_DP_ASF_END_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_ASF_END_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DP_ASF_END_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DP_ASF_END_EN) | BF_IPU_INT_CTRL_15_DP_ASF_END_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DP_SF_BRAKE_EN[6] (RW)
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*
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* DP Sync Flow Brake enable bit. This bit enables the interrupt that is a result of the Sync flow
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* brake at the DP
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DP_SF_BRAKE_EN (6) //!< Bit position for IPU_INT_CTRL_15_DP_SF_BRAKE_EN.
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#define BM_IPU_INT_CTRL_15_DP_SF_BRAKE_EN (0x00000040) //!< Bit mask for IPU_INT_CTRL_15_DP_SF_BRAKE_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DP_SF_BRAKE_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DP_SF_BRAKE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DP_SF_BRAKE_EN) >> BP_IPU_INT_CTRL_15_DP_SF_BRAKE_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DP_SF_BRAKE_EN.
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#define BF_IPU_INT_CTRL_15_DP_SF_BRAKE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DP_SF_BRAKE_EN) & BM_IPU_INT_CTRL_15_DP_SF_BRAKE_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_SF_BRAKE_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DP_SF_BRAKE_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DP_SF_BRAKE_EN) | BF_IPU_INT_CTRL_15_DP_SF_BRAKE_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DP_ASF_BRAKE_EN[7] (RW)
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*
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* DP Async Flow Brake enable bit. This bit enables the interrupt that is a result of the async flow
|
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* brake at the DP
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*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
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|
* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN (7) //!< Bit position for IPU_INT_CTRL_15_DP_ASF_BRAKE_EN.
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#define BM_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN (0x00000080) //!< Bit mask for IPU_INT_CTRL_15_DP_ASF_BRAKE_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DP_ASF_BRAKE_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN) >> BP_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DP_ASF_BRAKE_EN.
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#define BF_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN) & BM_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_ASF_BRAKE_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN) | BF_IPU_INT_CTRL_15_DP_ASF_BRAKE_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DC_FC_0_EN[8] (RW)
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*
|
|
* This bit enables they'd Frame Complete on channel #0 interrupt
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*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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//@{
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#define BP_IPU_INT_CTRL_15_DC_FC_0_EN (8) //!< Bit position for IPU_INT_CTRL_15_DC_FC_0_EN.
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#define BM_IPU_INT_CTRL_15_DC_FC_0_EN (0x00000100) //!< Bit mask for IPU_INT_CTRL_15_DC_FC_0_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DC_FC_0_EN from a register value.
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|
#define BG_IPU_INT_CTRL_15_DC_FC_0_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_FC_0_EN) >> BP_IPU_INT_CTRL_15_DC_FC_0_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_FC_0_EN.
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#define BF_IPU_INT_CTRL_15_DC_FC_0_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_FC_0_EN) & BM_IPU_INT_CTRL_15_DC_FC_0_EN)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DC_FC_0_EN field to a new value.
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|
#define BW_IPU_INT_CTRL_15_DC_FC_0_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_FC_0_EN) | BF_IPU_INT_CTRL_15_DC_FC_0_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DC_FC_1_EN[9] (RW)
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*
|
|
* This bit enables they'd Frame Complete on channel #1 interrupt
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_FC_1_EN (9) //!< Bit position for IPU_INT_CTRL_15_DC_FC_1_EN.
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|
#define BM_IPU_INT_CTRL_15_DC_FC_1_EN (0x00000200) //!< Bit mask for IPU_INT_CTRL_15_DC_FC_1_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DC_FC_1_EN from a register value.
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|
#define BG_IPU_INT_CTRL_15_DC_FC_1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_FC_1_EN) >> BP_IPU_INT_CTRL_15_DC_FC_1_EN)
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|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_FC_1_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_FC_1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_FC_1_EN) & BM_IPU_INT_CTRL_15_DC_FC_1_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_1_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_FC_1_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_FC_1_EN) | BF_IPU_INT_CTRL_15_DC_FC_1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DC_FC_2_EN[10] (RW)
|
|
*
|
|
* This bit enables the DC Frame Complete on channel #2 interrupt
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_FC_2_EN (10) //!< Bit position for IPU_INT_CTRL_15_DC_FC_2_EN.
|
|
#define BM_IPU_INT_CTRL_15_DC_FC_2_EN (0x00000400) //!< Bit mask for IPU_INT_CTRL_15_DC_FC_2_EN.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DC_FC_2_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DC_FC_2_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_FC_2_EN) >> BP_IPU_INT_CTRL_15_DC_FC_2_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_FC_2_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_FC_2_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_FC_2_EN) & BM_IPU_INT_CTRL_15_DC_FC_2_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_2_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_FC_2_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_FC_2_EN) | BF_IPU_INT_CTRL_15_DC_FC_2_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DC_FC_3_EN[11] (RW)
|
|
*
|
|
* This bit enables the DC Frame Complete on channel #3 interrupt
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_FC_3_EN (11) //!< Bit position for IPU_INT_CTRL_15_DC_FC_3_EN.
|
|
#define BM_IPU_INT_CTRL_15_DC_FC_3_EN (0x00000800) //!< Bit mask for IPU_INT_CTRL_15_DC_FC_3_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DC_FC_3_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DC_FC_3_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_FC_3_EN) >> BP_IPU_INT_CTRL_15_DC_FC_3_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_FC_3_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_FC_3_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_FC_3_EN) & BM_IPU_INT_CTRL_15_DC_FC_3_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_3_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_FC_3_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_FC_3_EN) | BF_IPU_INT_CTRL_15_DC_FC_3_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DC_FC_4_EN[12] (RW)
|
|
*
|
|
* This bit enables the DC Frame Complete on channel #4 interrupt
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_FC_4_EN (12) //!< Bit position for IPU_INT_CTRL_15_DC_FC_4_EN.
|
|
#define BM_IPU_INT_CTRL_15_DC_FC_4_EN (0x00001000) //!< Bit mask for IPU_INT_CTRL_15_DC_FC_4_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DC_FC_4_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DC_FC_4_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_FC_4_EN) >> BP_IPU_INT_CTRL_15_DC_FC_4_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_FC_4_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_FC_4_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_FC_4_EN) & BM_IPU_INT_CTRL_15_DC_FC_4_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_4_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_FC_4_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_FC_4_EN) | BF_IPU_INT_CTRL_15_DC_FC_4_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DC_FC_6_EN[13] (RW)
|
|
*
|
|
* This bit enables the DC Frame Complete on channel #6 interrupt
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_FC_6_EN (13) //!< Bit position for IPU_INT_CTRL_15_DC_FC_6_EN.
|
|
#define BM_IPU_INT_CTRL_15_DC_FC_6_EN (0x00002000) //!< Bit mask for IPU_INT_CTRL_15_DC_FC_6_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DC_FC_6_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DC_FC_6_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_FC_6_EN) >> BP_IPU_INT_CTRL_15_DC_FC_6_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_FC_6_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_FC_6_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_FC_6_EN) & BM_IPU_INT_CTRL_15_DC_FC_6_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_6_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_FC_6_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_FC_6_EN) | BF_IPU_INT_CTRL_15_DC_FC_6_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI_VSYNC_PRE_0_EN[14] (RW)
|
|
*
|
|
* This bit enables the DI0 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC
|
|
* sent to the display
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN (14) //!< Bit position for IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN (0x00004000) //!< Bit mask for IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN) >> BP_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN) & BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_VSYNC_PRE_0_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN) | BF_IPU_INT_CTRL_15_DI_VSYNC_PRE_0_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI_VSYNC_PRE_1_EN[15] (RW)
|
|
*
|
|
* This bit enables the DI1 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC
|
|
* sent to the display
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN (15) //!< Bit position for IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN (0x00008000) //!< Bit mask for IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN) >> BP_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN) & BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_VSYNC_PRE_1_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN) | BF_IPU_INT_CTRL_15_DI_VSYNC_PRE_1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DC_DP_START_EN[16] (RW)
|
|
*
|
|
* This bit enables the interrupt asserted anytime the DP start a new sync or async flow or when an
|
|
* async flow is interrupted by a sync flow
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_DP_START_EN (16) //!< Bit position for IPU_INT_CTRL_15_DC_DP_START_EN.
|
|
#define BM_IPU_INT_CTRL_15_DC_DP_START_EN (0x00010000) //!< Bit mask for IPU_INT_CTRL_15_DC_DP_START_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DC_DP_START_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DC_DP_START_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_DP_START_EN) >> BP_IPU_INT_CTRL_15_DC_DP_START_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_DP_START_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_DP_START_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_DP_START_EN) & BM_IPU_INT_CTRL_15_DC_DP_START_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_DP_START_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_DP_START_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_DP_START_EN) | BF_IPU_INT_CTRL_15_DC_DP_START_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DC_ASYNC_STOP_EN[17] (RW)
|
|
*
|
|
* This bit enables the interrupt asserted anytime the DP stops an async flow and moves to a sync
|
|
* flow
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN (17) //!< Bit position for IPU_INT_CTRL_15_DC_ASYNC_STOP_EN.
|
|
#define BM_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN (0x00020000) //!< Bit mask for IPU_INT_CTRL_15_DC_ASYNC_STOP_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DC_ASYNC_STOP_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN) >> BP_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DC_ASYNC_STOP_EN.
|
|
#define BF_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN) & BM_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_ASYNC_STOP_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN) | BF_IPU_INT_CTRL_15_DC_ASYNC_STOP_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_0_EN[18] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #0 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN (18) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN (0x00040000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_0_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_0_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_1_EN[19] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #1 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN (19) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN (0x00080000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_1_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_2_EN[20] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #2 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN (20) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN (0x00100000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_2_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_2_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_3_EN[21] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #3 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN (21) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN (0x00200000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_3_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_3_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_4_EN[22] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #4 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN (22) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN (0x00400000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_4_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_4_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_5_EN[23] (RW)
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*
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* This bit enables the interrupt that is a result of a trigger generated by counter #5 of DI0
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN (23) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN.
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#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN (0x00800000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN.
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#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_5_EN field to a new value.
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#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_5_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_6_EN[24] (RW)
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*
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* This bit enables the interrupt that is a result of a trigger generated by counter #6 of DI0
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*
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* Values:
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* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN (24) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN.
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#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN (0x01000000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN.
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#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_6_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_6_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_7_EN[25] (RW)
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*
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* This bit enables the interrupt that is a result of a trigger generated by counter #7 of DI0
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*
|
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* Values:
|
|
* - 0 - Interrupt is disabled.
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* - 1 - Interrupt is enabled.
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*/
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//@{
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#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN (25) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN.
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#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN (0x02000000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN.
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#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_EN_PRE_7_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_7_EN(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_8_EN[26] (RW)
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|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #8 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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|
//@{
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|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN (26) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN.
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#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN (0x04000000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN)
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|
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_8_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_8_EN(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_9_EN[27] (RW)
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|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #9 of DI0
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN (27) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN.
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|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN (0x08000000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN.
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//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN from a register value.
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#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_9_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_9_EN(v)))
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|
#endif
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|
//@}
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|
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/*! @name Register IPU_INT_CTRL_15, field DI0_CNT_EN_PRE_10_EN[28] (RW)
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|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #10 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN (28) //!< Bit position for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN (0x10000000) //!< Bit mask for IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN.
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|
//! @brief Get value of IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN from a register value.
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|
#define BG_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN) >> BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN)
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//! @brief Format value for bitfield IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN) & BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_10_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN) | BF_IPU_INT_CTRL_15_DI0_CNT_EN_PRE_10_EN(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_CTRL_15, field DI1_DISP_CLK_EN_PRE_EN[29] (RW)
|
|
*
|
|
* DI1_DISP_CLK_EN_PRE_EN
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
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|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN (29) //!< Bit position for IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN.
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|
#define BM_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN (0x20000000) //!< Bit mask for IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN) >> BP_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN)
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|
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|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN) & BM_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLK_EN_PRE_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN) | BF_IPU_INT_CTRL_15_DI1_DISP_CLK_EN_PRE_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI1_CNT_EN_PRE_3_EN[30] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #3 of DI1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN (30) //!< Bit position for IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN (0x40000000) //!< Bit mask for IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN.
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|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN) >> BP_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN) & BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_EN_PRE_3_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN) | BF_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_3_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_CTRL_15, field DI1_CNT_EN_PRE_8_EN[31] (RW)
|
|
*
|
|
* This bit enables the interrupt that is a result of a trigger generated by counter #8 of DI1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN (31) //!< Bit position for IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN.
|
|
#define BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN (0x80000000) //!< Bit mask for IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN.
|
|
|
|
//! @brief Get value of IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN from a register value.
|
|
#define BG_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN) >> BP_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN.
|
|
#define BF_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN) & BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_EN_PRE_8_EN field to a new value.
|
|
#define BW_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN(x, v) (HW_IPU_INT_CTRL_15_WR(x, (HW_IPU_INT_CTRL_15_RD(x) & ~BM_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN) | BF_IPU_INT_CTRL_15_DI1_CNT_EN_PRE_8_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_1 - SDMA Event Control Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_1 - SDMA Event Control Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of EOF (end of frame) of
|
|
* DMA Channels SDMA events [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_1_bitfields
|
|
{
|
|
unsigned IDMAC_EOF_SDMA_EN_0 : 1; //!< [0] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_1 : 1; //!< [1] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_2 : 1; //!< [2] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_3 : 1; //!< [3] Enable End of Frame of Channel SDMA event.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_EOF_SDMA_EN_5 : 1; //!< [5] Enable End of Frame of Channel SDMA event.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_EOF_SDMA_EN_8 : 1; //!< [8] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_9 : 1; //!< [9] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_10 : 1; //!< [10] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_11 : 1; //!< [11] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_12 : 1; //!< [12] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_13 : 1; //!< [13] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_14 : 1; //!< [14] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_15 : 1; //!< [15] Enable End of Frame of Channel SDMA event.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_EOF_SDMA_EN_17 : 1; //!< [17] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_18 : 1; //!< [18] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_19 : 1; //!< [19] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_20 : 1; //!< [20] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_21 : 1; //!< [21] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_22 : 1; //!< [22] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_23 : 1; //!< [23] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_24 : 1; //!< [24] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_25 : 1; //!< [25] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_26 : 1; //!< [26] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_27 : 1; //!< [27] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_28 : 1; //!< [28] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_29 : 1; //!< [29] Enable End of Frame of Channel SDMA event.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_EOF_SDMA_EN_31 : 1; //!< [31] Enable End of Frame of Channel SDMA event.
|
|
} B;
|
|
} hw_ipu_sdma_event_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_1_ADDR(x) (REGS_IPU_BASE(x) + 0x78)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_1(x) (*(volatile hw_ipu_sdma_event_1_t *) HW_IPU_SDMA_EVENT_1_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_1_RD(x) (HW_IPU_SDMA_EVENT_1(x).U)
|
|
#define HW_IPU_SDMA_EVENT_1_WR(x, v) (HW_IPU_SDMA_EVENT_1(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_1_SET(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, HW_IPU_SDMA_EVENT_1_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_1_CLR(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, HW_IPU_SDMA_EVENT_1_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_1_TOG(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, HW_IPU_SDMA_EVENT_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_0[0] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0 (0) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0 (0x00000001) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_0 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_1[1] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1 (1) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_1 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_2[2] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2 (2) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2 (0x00000004) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_2 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_3[3] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3 (3) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3 (0x00000008) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_3 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_5[5] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5 (5) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5 (0x00000020) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_5 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_8[8] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8 (8) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8 (0x00000100) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_8 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_9[9] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9 (9) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_9 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_10[10] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10 (10) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_10 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_11[11] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11 (11) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_11 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_12[12] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12 (12) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_12 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_13[13] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13 (13) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_13 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_14[14] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14 (14) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_14 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_15[15] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15 (15) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_15 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_17[17] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17 (17) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_17 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_18[18] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18 (18) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_18 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_19[19] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19 (19) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_19 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_20[20] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20 (20) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_20 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_21[21] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21 (21) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21 (0x00200000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_21 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_22[22] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22 (22) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22 (0x00400000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_22 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_23[23] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23 (23) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23 (0x00800000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_23 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_24[24] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24 (24) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24 (0x01000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_24 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_25[25] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25 (25) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25 (0x02000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_25 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_26[26] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26 (26) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26 (0x04000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_26 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_27[27] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27 (27) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27 (0x08000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_27 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_28[28] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28 (28) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28 (0x10000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_28 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_29[29] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29 (29) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29 (0x20000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_29 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_1, field IDMAC_EOF_SDMA_EN_31[31] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31 (31) //!< Bit position for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31.
|
|
#define BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31 (0x80000000) //!< Bit mask for IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31) >> BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31.
|
|
#define BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31) & BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_31 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31(x, v) (HW_IPU_SDMA_EVENT_1_WR(x, (HW_IPU_SDMA_EVENT_1_RD(x) & ~BM_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31) | BF_IPU_SDMA_EVENT_1_IDMAC_EOF_SDMA_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_2 - SDMA Event Control Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_2 - SDMA Event Control Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of EOF (end of frame) of
|
|
* DMA Channels SDMA events [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_EOF_SDMA_EN_33 : 1; //!< [1] Enable End of Frame of Channel SDMA event.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_EOF_SDMA_EN_40 : 1; //!< [8] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_41 : 1; //!< [9] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_42 : 1; //!< [10] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_43 : 1; //!< [11] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_44 : 1; //!< [12] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_45 : 1; //!< [13] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_46 : 1; //!< [14] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_47 : 1; //!< [15] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_48 : 1; //!< [16] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_49 : 1; //!< [17] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_50 : 1; //!< [18] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_51 : 1; //!< [19] Enable End of Frame of Channel SDMA event.
|
|
unsigned IDMAC_EOF_SDMA_EN_52 : 1; //!< [20] Enable End of Frame of Channel SDMA event.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_sdma_event_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_2_ADDR(x) (REGS_IPU_BASE(x) + 0x7c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_2(x) (*(volatile hw_ipu_sdma_event_2_t *) HW_IPU_SDMA_EVENT_2_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_2_RD(x) (HW_IPU_SDMA_EVENT_2(x).U)
|
|
#define HW_IPU_SDMA_EVENT_2_WR(x, v) (HW_IPU_SDMA_EVENT_2(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_2_SET(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, HW_IPU_SDMA_EVENT_2_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_2_CLR(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, HW_IPU_SDMA_EVENT_2_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_2_TOG(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, HW_IPU_SDMA_EVENT_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_33[1] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33 (1) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33.
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#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_33 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_33(v)))
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#endif
|
|
//@}
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|
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/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_40[8] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40 (8) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40.
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#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40 (0x00000100) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40.
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//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40 from a register value.
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#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40.
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#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_40 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_40(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_41[9] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
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|
*/
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//@{
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#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41 (9) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41.
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#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41.
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//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41 from a register value.
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#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41.
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|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_41 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_41(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_42[10] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42 (10) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42.
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#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42.
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|
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|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42)
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|
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//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42.
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|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_42 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_42(v)))
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|
#endif
|
|
//@}
|
|
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|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_43[11] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43 (11) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43.
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|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_43 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_44[12] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44 (12) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44.
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|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_44 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_45[13] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45 (13) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_45 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_46[14] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46 (14) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_46 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_47[15] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47 (15) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_47 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_48[16] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48 (16) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48 (0x00010000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_48 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_49[17] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49 (17) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49)
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|
|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_49 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_49(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_50[18] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50 (18) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50.
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#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50.
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//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50 from a register value.
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#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50.
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|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_50 field to a new value.
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|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_50(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_51[19] (RW)
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|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51 (19) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51.
|
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#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_51 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_2, field IDMAC_EOF_SDMA_EN_52[20] (RW)
|
|
*
|
|
* Enable End of Frame of Channel SDMA event. This bit is the control of End Of Frame of Channel #n.
|
|
* n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52 (20) //!< Bit position for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52.
|
|
#define BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52) >> BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52.
|
|
#define BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52) & BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_SDMA_EN_52 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52(x, v) (HW_IPU_SDMA_EVENT_2_WR(x, (HW_IPU_SDMA_EVENT_2_RD(x) & ~BM_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52) | BF_IPU_SDMA_EVENT_2_IDMAC_EOF_SDMA_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_3 - SDMA Event Control Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_3 - SDMA Event Control Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of NFACK (New Frame
|
|
* Acknowledge) of DMA Channels SDMA events [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_3_bitfields
|
|
{
|
|
unsigned IDMAC_NFACK_SDMA_EN_0 : 1; //!< [0] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_1 : 1; //!< [1] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_2 : 1; //!< [2] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_3 : 1; //!< [3] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_NFACK_SDMA_EN_5 : 1; //!< [5] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_NFACK_SDMA_EN_8 : 1; //!< [8] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_9 : 1; //!< [9] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_10 : 1; //!< [10] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_11 : 1; //!< [11] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_12 : 1; //!< [12] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_13 : 1; //!< [13] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_14 : 1; //!< [14] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_15 : 1; //!< [15] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_NFACK_SDMA_EN_17 : 1; //!< [17] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_18 : 1; //!< [18] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_19 : 1; //!< [19] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_20 : 1; //!< [20] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_21 : 1; //!< [21] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_22 : 1; //!< [22] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_23 : 1; //!< [23] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_24 : 1; //!< [24] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_25 : 1; //!< [25] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_26 : 1; //!< [26] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_27 : 1; //!< [27] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_28 : 1; //!< [28] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_29 : 1; //!< [29] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_NFACK_SDMA_EN_31 : 1; //!< [31] Enable New Frame Acknowledge of Channel SDMA event.
|
|
} B;
|
|
} hw_ipu_sdma_event_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_3_ADDR(x) (REGS_IPU_BASE(x) + 0x80)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_3(x) (*(volatile hw_ipu_sdma_event_3_t *) HW_IPU_SDMA_EVENT_3_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_3_RD(x) (HW_IPU_SDMA_EVENT_3(x).U)
|
|
#define HW_IPU_SDMA_EVENT_3_WR(x, v) (HW_IPU_SDMA_EVENT_3(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_3_SET(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, HW_IPU_SDMA_EVENT_3_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_3_CLR(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, HW_IPU_SDMA_EVENT_3_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_3_TOG(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, HW_IPU_SDMA_EVENT_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_0[0] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0 (0) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0 (0x00000001) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_0 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_1[1] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1 (1) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_1 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_2[2] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2 (2) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2 (0x00000004) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_2 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_3[3] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3 (3) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3 (0x00000008) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_3 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_5[5] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5 (5) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5 (0x00000020) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_5 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_8[8] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8 (8) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8 (0x00000100) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_8 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_9[9] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9 (9) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_9 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_10[10] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10 (10) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_10 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_11[11] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11 (11) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_11 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_12[12] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12 (12) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_12 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_13[13] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13 (13) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_13 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_14[14] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14 (14) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_14 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_15[15] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15 (15) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_15 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_17[17] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17 (17) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_17 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_18[18] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18 (18) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_18 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_19[19] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19 (19) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_19 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_20[20] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20 (20) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_20 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_21[21] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21 (21) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21 (0x00200000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_21 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_22[22] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22 (22) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22 (0x00400000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_22 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_23[23] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23 (23) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23 (0x00800000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_23 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_24[24] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24 (24) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24 (0x01000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_24 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_25[25] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25 (25) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25 (0x02000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_25 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_26[26] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26 (26) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26 (0x04000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_26 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_27[27] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27 (27) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27.
|
|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27 (0x08000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_27 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_28[28] (RW)
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|
*
|
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* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
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|
*/
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//@{
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|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28 (28) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28.
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#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28 (0x10000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28.
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//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28 from a register value.
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#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28.
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#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_SDMA_EN_28 field to a new value.
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|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_28(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_29[29] (RW)
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|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
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* - 1 - SDMA event is enabled.
|
|
*/
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//@{
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|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29 (29) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29.
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#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29 (0x20000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29.
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//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29 from a register value.
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|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29.
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|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_29 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_29(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_SDMA_EVENT_3, field IDMAC_NFACK_SDMA_EN_31[31] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31 (31) //!< Bit position for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31.
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|
#define BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31 (0x80000000) //!< Bit mask for IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31) >> BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31)
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|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31.
|
|
#define BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31) & BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_31 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31(x, v) (HW_IPU_SDMA_EVENT_3_WR(x, (HW_IPU_SDMA_EVENT_3_RD(x) & ~BM_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31) | BF_IPU_SDMA_EVENT_3_IDMAC_NFACK_SDMA_EN_31(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_4 - SDMA Event Control Register 4
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_4 - SDMA Event Control Register 4 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of NFACK (New Frame
|
|
* Acknowledge) of DMA Channels SDMA events [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_4_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_NFACK_SDMA_EN_33 : 1; //!< [1] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_NFACK_SDMA_EN_40 : 1; //!< [8] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_41 : 1; //!< [9] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_42 : 1; //!< [10] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_43 : 1; //!< [11] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_44 : 1; //!< [12] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_45 : 1; //!< [13] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_46 : 1; //!< [14] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_47 : 1; //!< [15] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_48 : 1; //!< [16] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_49 : 1; //!< [17] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_50 : 1; //!< [18] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_51 : 1; //!< [19] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned IDMAC_NFACK_SDMA_EN_52 : 1; //!< [20] Enable New Frame Acknowledge of Channel SDMA event.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_sdma_event_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_4_ADDR(x) (REGS_IPU_BASE(x) + 0x84)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_4(x) (*(volatile hw_ipu_sdma_event_4_t *) HW_IPU_SDMA_EVENT_4_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_4_RD(x) (HW_IPU_SDMA_EVENT_4(x).U)
|
|
#define HW_IPU_SDMA_EVENT_4_WR(x, v) (HW_IPU_SDMA_EVENT_4(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_4_SET(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, HW_IPU_SDMA_EVENT_4_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_4_CLR(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, HW_IPU_SDMA_EVENT_4_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_4_TOG(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, HW_IPU_SDMA_EVENT_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_33[1] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33 (1) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_33 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_40[8] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40 (8) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40 (0x00000100) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_40 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_41[9] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41 (9) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_41 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_42[10] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42 (10) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_42 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_43[11] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43 (11) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_43 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_44[12] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44 (12) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_44 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_45[13] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45 (13) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_45 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_46[14] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46 (14) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_46 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_47[15] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47 (15) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_47 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_48[16] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48 (16) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48 (0x00010000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_48 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_49[17] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49 (17) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_49 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_50[18] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50 (18) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_50 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_51[19] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51 (19) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_51 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_4, field IDMAC_NFACK_SDMA_EN_52[20] (RW)
|
|
*
|
|
* Enable New Frame Acknowledge of Channel SDMA event. This bit is the control of New Frame
|
|
* Acknowledge of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52 (20) //!< Bit position for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52.
|
|
#define BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52) >> BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52.
|
|
#define BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52) & BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_SDMA_EN_52 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52(x, v) (HW_IPU_SDMA_EVENT_4_WR(x, (HW_IPU_SDMA_EVENT_4_RD(x) & ~BM_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52) | BF_IPU_SDMA_EVENT_4_IDMAC_NFACK_SDMA_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_7 - SDMA Event Control Register 7
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_7 - SDMA Event Control Register 7 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of EOS (End of Scroll) of
|
|
* DMA Channels SDMA events [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_7_bitfields
|
|
{
|
|
unsigned RESERVED0 : 19; //!< [18:0] Reserved.
|
|
unsigned IDMAC_EOS_SDMA_EN_19 : 1; //!< [19] Enable End of Scroll of Channel SDMA event.
|
|
unsigned RESERVED1 : 3; //!< [22:20] Reserved.
|
|
unsigned IDMAC_EOS_SDMA_EN_23 : 1; //!< [23] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_24 : 1; //!< [24] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_25 : 1; //!< [25] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_26 : 1; //!< [26] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_27 : 1; //!< [27] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_28 : 1; //!< [28] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_29 : 1; //!< [29] Enable End of Scroll of Channel SDMA event.
|
|
unsigned RESERVED2 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_EOS_SDMA_EN_31 : 1; //!< [31] Enable End of Scroll of Channel SDMA event.
|
|
} B;
|
|
} hw_ipu_sdma_event_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_7_ADDR(x) (REGS_IPU_BASE(x) + 0x88)
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#ifndef __LANGUAGE_ASM__
|
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#define HW_IPU_SDMA_EVENT_7(x) (*(volatile hw_ipu_sdma_event_7_t *) HW_IPU_SDMA_EVENT_7_ADDR(x))
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#define HW_IPU_SDMA_EVENT_7_RD(x) (HW_IPU_SDMA_EVENT_7(x).U)
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#define HW_IPU_SDMA_EVENT_7_WR(x, v) (HW_IPU_SDMA_EVENT_7(x).U = (v))
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#define HW_IPU_SDMA_EVENT_7_SET(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, HW_IPU_SDMA_EVENT_7_RD(x) | (v)))
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#define HW_IPU_SDMA_EVENT_7_CLR(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, HW_IPU_SDMA_EVENT_7_RD(x) & ~(v)))
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#define HW_IPU_SDMA_EVENT_7_TOG(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, HW_IPU_SDMA_EVENT_7_RD(x) ^ (v)))
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#endif
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//@}
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/*
|
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* constants & macros for individual IPU_SDMA_EVENT_7 bitfields
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*/
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/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_19[19] (RW)
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*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19 (19) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19.
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#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19.
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//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19 from a register value.
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#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19.
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#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOS_SDMA_EN_19 field to a new value.
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#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_19(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_23[23] (RW)
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*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23 (23) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23.
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#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23 (0x00800000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23.
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//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23 from a register value.
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#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23.
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#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOS_SDMA_EN_23 field to a new value.
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|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_23(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_24[24] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24 (24) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24.
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#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24 (0x01000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24.
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//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24.
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|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24)
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|
|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_EOS_SDMA_EN_24 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_24(v)))
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|
#endif
|
|
//@}
|
|
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|
/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_25[25] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25 (25) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25.
|
|
#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25 (0x02000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25.
|
|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_25 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_26[26] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26 (26) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26.
|
|
#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26 (0x04000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26.
|
|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_26 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_27[27] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27 (27) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27.
|
|
#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27 (0x08000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27.
|
|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_27 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_28[28] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28 (28) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28.
|
|
#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28 (0x10000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28.
|
|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_28 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_29[29] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29 (29) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29.
|
|
#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29 (0x20000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29.
|
|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_29 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_7, field IDMAC_EOS_SDMA_EN_31[31] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31 (31) //!< Bit position for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31.
|
|
#define BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31 (0x80000000) //!< Bit mask for IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31) >> BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31.
|
|
#define BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31) & BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_31 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31(x, v) (HW_IPU_SDMA_EVENT_7_WR(x, (HW_IPU_SDMA_EVENT_7_RD(x) & ~BM_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31) | BF_IPU_SDMA_EVENT_7_IDMAC_EOS_SDMA_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_8 - SDMA Event Control Register 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_8 - SDMA Event Control Register 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of EOS (End of Scroll) of
|
|
* DMA Channels SDMA events [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_8_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_EOS_SDMA_EN_33 : 1; //!< [1] Enable End of Scroll of Channel SDMA event.
|
|
unsigned RESERVED1 : 7; //!< [8:2] Reserved.
|
|
unsigned IDMAC_EOS_SDMA_EN_41 : 1; //!< [9] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_42 : 1; //!< [10] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_43 : 1; //!< [11] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_44 : 1; //!< [12] Enable End of Scroll of Channel SDMA event.
|
|
unsigned RESERVED2 : 6; //!< [18:13] Reserved.
|
|
unsigned IDMAC_EOS_SDMA_EN_51 : 1; //!< [19] Enable End of Scroll of Channel SDMA event.
|
|
unsigned IDMAC_EOS_SDMA_EN_52 : 1; //!< [20] Enable End of Scroll of Channel SDMA event.
|
|
unsigned RESERVED3 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_sdma_event_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_8_ADDR(x) (REGS_IPU_BASE(x) + 0x8c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_8(x) (*(volatile hw_ipu_sdma_event_8_t *) HW_IPU_SDMA_EVENT_8_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_8_RD(x) (HW_IPU_SDMA_EVENT_8(x).U)
|
|
#define HW_IPU_SDMA_EVENT_8_WR(x, v) (HW_IPU_SDMA_EVENT_8(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_8_SET(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, HW_IPU_SDMA_EVENT_8_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_8_CLR(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, HW_IPU_SDMA_EVENT_8_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_8_TOG(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, HW_IPU_SDMA_EVENT_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_33[1] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33 (1) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_33 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_41[9] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41 (9) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_41 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_42[10] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42 (10) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_42 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_43[11] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43 (11) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_43 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_44[12] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44 (12) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_44 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_51[19] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51 (19) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_51 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_8, field IDMAC_EOS_SDMA_EN_52[20] (RW)
|
|
*
|
|
* Enable End of Scroll of Channel SDMA event. This bit is the control of End Of Scroll of Channel
|
|
* #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52 (20) //!< Bit position for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52.
|
|
#define BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52) >> BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52.
|
|
#define BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52) & BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_SDMA_EN_52 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52(x, v) (HW_IPU_SDMA_EVENT_8_WR(x, (HW_IPU_SDMA_EVENT_8_RD(x) & ~BM_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52) | BF_IPU_SDMA_EVENT_8_IDMAC_EOS_SDMA_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_11 - SDMA Event Control Register 11
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_11 - SDMA Event Control Register 11 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of EOBND (End of Band) of
|
|
* DMA Channels SDMA events [31:0] can be found in this register. Hide VDOA_SYNC for all versions
|
|
* Show VDOA_SYNC for IPUv3H version. The table below tagged with other settings (like IPU3M_only)
|
|
* should be hidden in IPUv3H version.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_11
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_11_bitfields
|
|
{
|
|
unsigned IDMAC_EOBND_SDMA_EN_0 : 1; //!< [0] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_1 : 1; //!< [1] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_2 : 1; //!< [2] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_3 : 1; //!< [3] Enable End of Band of Channel SDMA event.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_EOBND_SDMA_EN_5 : 1; //!< [5] Enable End of Band of Channel SDMA event.
|
|
unsigned RESERVED1 : 5; //!< [10:6] Reserved.
|
|
unsigned IDMAC_EOBND_SDMA_EN_11 : 1; //!< [11] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_12 : 1; //!< [12] Enable End of Band of Channel SDMA event.
|
|
unsigned RESERVED2 : 7; //!< [19:13] Reserved.
|
|
unsigned IDMAC_EOBND_SDMA_EN_20 : 1; //!< [20] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_21 : 1; //!< [21] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_22 : 1; //!< [22] Enable End of Band of Channel SDMA event.
|
|
unsigned RESERVED3 : 2; //!< [24:23] Reserved.
|
|
unsigned IDMAC_EOBND_SDMA_EN_25 : 1; //!< [25] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_26 : 1; //!< [26] Enable End of Band of Channel SDMA event.
|
|
unsigned RESERVED4 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_sdma_event_11_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_11 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_11_ADDR(x) (REGS_IPU_BASE(x) + 0x90)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_11(x) (*(volatile hw_ipu_sdma_event_11_t *) HW_IPU_SDMA_EVENT_11_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_11_RD(x) (HW_IPU_SDMA_EVENT_11(x).U)
|
|
#define HW_IPU_SDMA_EVENT_11_WR(x, v) (HW_IPU_SDMA_EVENT_11(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_11_SET(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, HW_IPU_SDMA_EVENT_11_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_11_CLR(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, HW_IPU_SDMA_EVENT_11_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_11_TOG(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, HW_IPU_SDMA_EVENT_11_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
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* constants & macros for individual IPU_SDMA_EVENT_11 bitfields
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*/
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_0[0] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0 (0) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0 (0x00000001) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_0 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_0(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_1[1] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1 (1) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_1 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_1(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_2[2] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2 (2) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2 (0x00000004) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_2 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_3[3] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3 (3) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3 (0x00000008) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_3 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_3(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_5[5] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5 (5) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5 (0x00000020) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_5 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_5(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_11[11] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11 (11) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_11 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_11(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_12[12] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12 (12) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_12 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_12(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_20[20] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20 (20) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_20 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_20(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_21[21] (RW)
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*
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21 (21) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21 (0x00200000) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_EOBND_SDMA_EN_21 field to a new value.
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#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_21(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_22[22] (RW)
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*
|
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* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22 (22) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22.
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#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22 (0x00400000) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22 from a register value.
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#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22.
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#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_22 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_22(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_25[25] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25 (25) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25.
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|
#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25 (0x02000000) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25.
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25.
|
|
#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_25 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_25(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_11, field IDMAC_EOBND_SDMA_EN_26[26] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
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|
//@{
|
|
#define BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26 (26) //!< Bit position for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26.
|
|
#define BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26 (0x04000000) //!< Bit mask for IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26.
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|
|
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//! @brief Get value of IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26) >> BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26.
|
|
#define BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26) & BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_26 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26(x, v) (HW_IPU_SDMA_EVENT_11_WR(x, (HW_IPU_SDMA_EVENT_11_RD(x) & ~BM_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26) | BF_IPU_SDMA_EVENT_11_IDMAC_EOBND_SDMA_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_12 - SDMA Event Control Register 12
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_12 - SDMA Event Control Register 12 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of EOBND (End of Band) of
|
|
* DMA Channels SDMA events [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_12
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_12_bitfields
|
|
{
|
|
unsigned RESERVED0 : 13; //!< [12:0] Reserved.
|
|
unsigned IDMAC_EOBND_SDMA_EN_45 : 1; //!< [13] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_46 : 1; //!< [14] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_47 : 1; //!< [15] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_48 : 1; //!< [16] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_49 : 1; //!< [17] Enable End of Band of Channel SDMA event.
|
|
unsigned IDMAC_EOBND_SDMA_EN_50 : 1; //!< [18] Enable End of Band of Channel SDMA event.
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved.
|
|
} B;
|
|
} hw_ipu_sdma_event_12_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_12 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_12_ADDR(x) (REGS_IPU_BASE(x) + 0x94)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_12(x) (*(volatile hw_ipu_sdma_event_12_t *) HW_IPU_SDMA_EVENT_12_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_12_RD(x) (HW_IPU_SDMA_EVENT_12(x).U)
|
|
#define HW_IPU_SDMA_EVENT_12_WR(x, v) (HW_IPU_SDMA_EVENT_12(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_12_SET(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, HW_IPU_SDMA_EVENT_12_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_12_CLR(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, HW_IPU_SDMA_EVENT_12_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_12_TOG(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, HW_IPU_SDMA_EVENT_12_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_12 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_12, field IDMAC_EOBND_SDMA_EN_45[13] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45 (13) //!< Bit position for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45.
|
|
#define BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45) >> BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45.
|
|
#define BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_45 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, (HW_IPU_SDMA_EVENT_12_RD(x) & ~BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45) | BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_12, field IDMAC_EOBND_SDMA_EN_46[14] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46 (14) //!< Bit position for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46.
|
|
#define BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46) >> BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46.
|
|
#define BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_46 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, (HW_IPU_SDMA_EVENT_12_RD(x) & ~BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46) | BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_12, field IDMAC_EOBND_SDMA_EN_47[15] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47 (15) //!< Bit position for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47.
|
|
#define BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47) >> BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47.
|
|
#define BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_47 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, (HW_IPU_SDMA_EVENT_12_RD(x) & ~BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47) | BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_12, field IDMAC_EOBND_SDMA_EN_48[16] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48 (16) //!< Bit position for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48.
|
|
#define BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48 (0x00010000) //!< Bit mask for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48) >> BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48.
|
|
#define BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_48 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, (HW_IPU_SDMA_EVENT_12_RD(x) & ~BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48) | BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_12, field IDMAC_EOBND_SDMA_EN_49[17] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49 (17) //!< Bit position for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49.
|
|
#define BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49) >> BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49.
|
|
#define BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_49 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, (HW_IPU_SDMA_EVENT_12_RD(x) & ~BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49) | BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_12, field IDMAC_EOBND_SDMA_EN_50[18] (RW)
|
|
*
|
|
* Enable End of Band of Channel SDMA event. This bit is the control of End Of Band of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50 (18) //!< Bit position for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50.
|
|
#define BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50) >> BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50.
|
|
#define BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50) & BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_SDMA_EN_50 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50(x, v) (HW_IPU_SDMA_EVENT_12_WR(x, (HW_IPU_SDMA_EVENT_12_RD(x) & ~BM_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50) | BF_IPU_SDMA_EVENT_12_IDMAC_EOBND_SDMA_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_13 - SDMA Event Control Register 13
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_13 - SDMA Event Control Register 13 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of TH (Threshold) of DMA
|
|
* Channels SDMA events [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_13
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_13_bitfields
|
|
{
|
|
unsigned IDMAC_TH_SDMA_EN_0 : 1; //!< [0] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_1 : 1; //!< [1] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_2 : 1; //!< [2] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_3 : 1; //!< [3] Enable Threshold of Channel SDMA event.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_TH_SDMA_EN_5 : 1; //!< [5] Enable Threshold of Channel SDMA event.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_TH_SDMA_EN_8 : 1; //!< [8] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_9 : 1; //!< [9] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_10 : 1; //!< [10] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_11 : 1; //!< [11] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_12 : 1; //!< [12] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_13 : 1; //!< [13] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_14 : 1; //!< [14] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_15 : 1; //!< [15] Enable Threshold of Channel SDMA event.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_TH_SDMA_EN_17 : 1; //!< [17] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_18 : 1; //!< [18] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_19 : 1; //!< [19] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_20 : 1; //!< [20] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_21 : 1; //!< [21] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_22 : 1; //!< [22] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_23 : 1; //!< [23] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_24 : 1; //!< [24] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_25 : 1; //!< [25] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_26 : 1; //!< [26] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_27 : 1; //!< [27] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_28 : 1; //!< [28] Enable Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_29 : 1; //!< [29] Enable Threshold of Channel SDMA event.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_TH_SDMA_EN_31 : 1; //!< [31] Enable Threshold of Channel SDMA event.
|
|
} B;
|
|
} hw_ipu_sdma_event_13_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_13 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_13_ADDR(x) (REGS_IPU_BASE(x) + 0x98)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SDMA_EVENT_13(x) (*(volatile hw_ipu_sdma_event_13_t *) HW_IPU_SDMA_EVENT_13_ADDR(x))
|
|
#define HW_IPU_SDMA_EVENT_13_RD(x) (HW_IPU_SDMA_EVENT_13(x).U)
|
|
#define HW_IPU_SDMA_EVENT_13_WR(x, v) (HW_IPU_SDMA_EVENT_13(x).U = (v))
|
|
#define HW_IPU_SDMA_EVENT_13_SET(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, HW_IPU_SDMA_EVENT_13_RD(x) | (v)))
|
|
#define HW_IPU_SDMA_EVENT_13_CLR(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, HW_IPU_SDMA_EVENT_13_RD(x) & ~(v)))
|
|
#define HW_IPU_SDMA_EVENT_13_TOG(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, HW_IPU_SDMA_EVENT_13_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SDMA_EVENT_13 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_0[0] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0 (0) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0 (0x00000001) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_0 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_1[1] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1 (1) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_1 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_2[2] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2 (2) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2 (0x00000004) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_2 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_3[3] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3 (3) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3 (0x00000008) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_3 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_5[5] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5 (5) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5 (0x00000020) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_5 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_8[8] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8 (8) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8 (0x00000100) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_8 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_9[9] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9 (9) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_9 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_10[10] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10 (10) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_10 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_11[11] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11 (11) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_11 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_12[12] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12 (12) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_12 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_13[13] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13 (13) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_13 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_14[14] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14 (14) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_14 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_15[15] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15 (15) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_15 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_17[17] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17 (17) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_17 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_18[18] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18 (18) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_18 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_19[19] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19 (19) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_19 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_20[20] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20 (20) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_20 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_21[21] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21 (21) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21 (0x00200000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_21 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_22[22] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22 (22) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22 (0x00400000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_22 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_23[23] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23 (23) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23 (0x00800000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_23 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_24[24] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24 (24) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24 (0x01000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_24 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_25[25] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25 (25) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25 (0x02000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_25 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_26[26] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26 (26) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26 (0x04000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_26 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_27[27] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27 (27) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27 (0x08000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_27 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_28[28] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28 (28) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28 (0x10000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_28 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_29[29] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29 (29) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29 (0x20000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_29 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_13, field IDMAC_TH_SDMA_EN_31[31] (RW)
|
|
*
|
|
* Enable Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31 (31) //!< Bit position for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31.
|
|
#define BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31 (0x80000000) //!< Bit mask for IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31) >> BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31.
|
|
#define BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31) & BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_31 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31(x, v) (HW_IPU_SDMA_EVENT_13_WR(x, (HW_IPU_SDMA_EVENT_13_RD(x) & ~BM_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31) | BF_IPU_SDMA_EVENT_13_IDMAC_TH_SDMA_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SDMA_EVENT_14 - SDMA Event Control Register 14
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SDMA_EVENT_14 - SDMA Event Control Register 14 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains part of IPU SDMA events controls. The controls of TH (Threshold) of DMA
|
|
* Channels SDMA events [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_sdma_event_14
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_sdma_event_14_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_TH_SDMA_EN_33 : 1; //!< [1] Threshold of Channel SDMA event.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_TH_SDMA_EN_40 : 1; //!< [8] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_41 : 1; //!< [9] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_42 : 1; //!< [10] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_43 : 1; //!< [11] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_44 : 1; //!< [12] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_45 : 1; //!< [13] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_46 : 1; //!< [14] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_47 : 1; //!< [15] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_48 : 1; //!< [16] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_49 : 1; //!< [17] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_50 : 1; //!< [18] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_51 : 1; //!< [19] Threshold of Channel SDMA event.
|
|
unsigned IDMAC_TH_SDMA_EN_52 : 1; //!< [20] Threshold of Channel SDMA event.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_sdma_event_14_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SDMA_EVENT_14 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SDMA_EVENT_14_ADDR(x) (REGS_IPU_BASE(x) + 0x9c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
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#define HW_IPU_SDMA_EVENT_14(x) (*(volatile hw_ipu_sdma_event_14_t *) HW_IPU_SDMA_EVENT_14_ADDR(x))
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#define HW_IPU_SDMA_EVENT_14_RD(x) (HW_IPU_SDMA_EVENT_14(x).U)
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#define HW_IPU_SDMA_EVENT_14_WR(x, v) (HW_IPU_SDMA_EVENT_14(x).U = (v))
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#define HW_IPU_SDMA_EVENT_14_SET(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, HW_IPU_SDMA_EVENT_14_RD(x) | (v)))
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#define HW_IPU_SDMA_EVENT_14_CLR(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, HW_IPU_SDMA_EVENT_14_RD(x) & ~(v)))
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#define HW_IPU_SDMA_EVENT_14_TOG(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, HW_IPU_SDMA_EVENT_14_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_SDMA_EVENT_14 bitfields
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*/
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_33[1] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33 (1) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33 (0x00000002) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_33 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_33(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_40[8] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40 (8) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40 (0x00000100) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_40 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_40(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_41[9] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41 (9) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41 (0x00000200) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_41 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_41(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_42[10] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42 (10) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42 (0x00000400) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_42 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_42(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_43[11] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43 (11) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43 (0x00000800) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_43 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_43(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_44[12] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - SDMA event is disabled.
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44 (12) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44 (0x00001000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_44 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_44(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_45[13] (RW)
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*
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
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*
|
|
* Values:
|
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* - 0 - SDMA event is disabled.
|
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45 (13) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45 (0x00002000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_TH_SDMA_EN_45 field to a new value.
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#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_45(v)))
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#endif
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//@}
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_46[14] (RW)
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*
|
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* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
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* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
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* - 0 - SDMA event is disabled.
|
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* - 1 - SDMA event is enabled.
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*/
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//@{
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#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46 (14) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46.
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#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46 (0x00004000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46.
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46 from a register value.
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#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46.
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#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46)
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|
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_46 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_46(v)))
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|
#endif
|
|
//@}
|
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_47[15] (RW)
|
|
*
|
|
* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
|
* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47 (15) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47.
|
|
#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47 (0x00008000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47.
|
|
#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_47 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_48[16] (RW)
|
|
*
|
|
* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
|
* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48 (16) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48.
|
|
#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48 (0x00010000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48.
|
|
#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_48 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_48(v)))
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|
#endif
|
|
//@}
|
|
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/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_49[17] (RW)
|
|
*
|
|
* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
|
* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49 (17) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49.
|
|
#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49 (0x00020000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49.
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|
|
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//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49)
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//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49.
|
|
#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_49 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_49(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_50[18] (RW)
|
|
*
|
|
* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
|
* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50 (18) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50.
|
|
#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50 (0x00040000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50.
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|
|
|
//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50)
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|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50.
|
|
#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_50 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_51[19] (RW)
|
|
*
|
|
* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
|
* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51 (19) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51.
|
|
#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51 (0x00080000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51.
|
|
#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_51 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SDMA_EVENT_14, field IDMAC_TH_SDMA_EN_52[20] (RW)
|
|
*
|
|
* Threshold of Channel SDMA event. This bit is the control of Threshold of Channel #n. n Indicates
|
|
* the corresponding DMA channel number. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - SDMA event is disabled.
|
|
* - 1 - SDMA event is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52 (20) //!< Bit position for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52.
|
|
#define BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52 (0x00100000) //!< Bit mask for IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52.
|
|
|
|
//! @brief Get value of IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52 from a register value.
|
|
#define BG_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52) >> BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52.
|
|
#define BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52) & BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_SDMA_EN_52 field to a new value.
|
|
#define BW_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52(x, v) (HW_IPU_SDMA_EVENT_14_WR(x, (HW_IPU_SDMA_EVENT_14_RD(x) & ~BM_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52) | BF_IPU_SDMA_EVENT_14_IDMAC_TH_SDMA_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SRM_PRI1 - Shadow Registers Memory Priority 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SRM_PRI1 - Shadow Registers Memory Priority 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000100
|
|
*
|
|
* The register controls the priority of SRM updates. The priority level for each block that has a
|
|
* shadow of its registers in the SRM should be unique. The priority level defines the order of SRM
|
|
* updates. A block with priority set to 010 will be updated before a block with priority set to
|
|
* 001.
|
|
*/
|
|
typedef union _hw_ipu_srm_pri1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_srm_pri1_bitfields
|
|
{
|
|
unsigned CSI1_SRM_PRI : 3; //!< [2:0] CSI1 SRM priority
|
|
unsigned CSI1_SRM_MODE : 2; //!< [4:3] CSI1 SRM Mode
|
|
unsigned RESERVED0 : 3; //!< [7:5] Reserved
|
|
unsigned CSI0_SRM_PRI : 3; //!< [10:8] CSI0 SRM priority
|
|
unsigned CSI0_SRM_MODE : 2; //!< [12:11] CSI0 SRM Mode
|
|
unsigned RESERVED1 : 19; //!< [31:13] Reserved
|
|
} B;
|
|
} hw_ipu_srm_pri1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SRM_PRI1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SRM_PRI1_ADDR(x) (REGS_IPU_BASE(x) + 0xa0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SRM_PRI1(x) (*(volatile hw_ipu_srm_pri1_t *) HW_IPU_SRM_PRI1_ADDR(x))
|
|
#define HW_IPU_SRM_PRI1_RD(x) (HW_IPU_SRM_PRI1(x).U)
|
|
#define HW_IPU_SRM_PRI1_WR(x, v) (HW_IPU_SRM_PRI1(x).U = (v))
|
|
#define HW_IPU_SRM_PRI1_SET(x, v) (HW_IPU_SRM_PRI1_WR(x, HW_IPU_SRM_PRI1_RD(x) | (v)))
|
|
#define HW_IPU_SRM_PRI1_CLR(x, v) (HW_IPU_SRM_PRI1_WR(x, HW_IPU_SRM_PRI1_RD(x) & ~(v)))
|
|
#define HW_IPU_SRM_PRI1_TOG(x, v) (HW_IPU_SRM_PRI1_WR(x, HW_IPU_SRM_PRI1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SRM_PRI1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SRM_PRI1, field CSI1_SRM_PRI[2:0] (RW)
|
|
*
|
|
* CSI1 SRM priority This bits define the priority of the CSI0 module
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI1_CSI1_SRM_PRI (0) //!< Bit position for IPU_SRM_PRI1_CSI1_SRM_PRI.
|
|
#define BM_IPU_SRM_PRI1_CSI1_SRM_PRI (0x00000007) //!< Bit mask for IPU_SRM_PRI1_CSI1_SRM_PRI.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI1_CSI1_SRM_PRI from a register value.
|
|
#define BG_IPU_SRM_PRI1_CSI1_SRM_PRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI1_CSI1_SRM_PRI) >> BP_IPU_SRM_PRI1_CSI1_SRM_PRI)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI1_CSI1_SRM_PRI.
|
|
#define BF_IPU_SRM_PRI1_CSI1_SRM_PRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI1_CSI1_SRM_PRI) & BM_IPU_SRM_PRI1_CSI1_SRM_PRI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SRM_PRI field to a new value.
|
|
#define BW_IPU_SRM_PRI1_CSI1_SRM_PRI(x, v) (HW_IPU_SRM_PRI1_WR(x, (HW_IPU_SRM_PRI1_RD(x) & ~BM_IPU_SRM_PRI1_CSI1_SRM_PRI) | BF_IPU_SRM_PRI1_CSI1_SRM_PRI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI1, field CSI1_SRM_MODE[4:3] (RW)
|
|
*
|
|
* CSI1 SRM Mode This field controls the SRM logic that handles the CSI1 registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the CSI0's region in the RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI1_CSI1_SRM_MODE (3) //!< Bit position for IPU_SRM_PRI1_CSI1_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI1_CSI1_SRM_MODE (0x00000018) //!< Bit mask for IPU_SRM_PRI1_CSI1_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI1_CSI1_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI1_CSI1_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI1_CSI1_SRM_MODE) >> BP_IPU_SRM_PRI1_CSI1_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI1_CSI1_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI1_CSI1_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI1_CSI1_SRM_MODE) & BM_IPU_SRM_PRI1_CSI1_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI1_CSI1_SRM_MODE(x, v) (HW_IPU_SRM_PRI1_WR(x, (HW_IPU_SRM_PRI1_RD(x) & ~BM_IPU_SRM_PRI1_CSI1_SRM_MODE) | BF_IPU_SRM_PRI1_CSI1_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI1, field CSI0_SRM_PRI[10:8] (RW)
|
|
*
|
|
* CSI0 SRM priority This bits define the priority of the CSI1 block
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI1_CSI0_SRM_PRI (8) //!< Bit position for IPU_SRM_PRI1_CSI0_SRM_PRI.
|
|
#define BM_IPU_SRM_PRI1_CSI0_SRM_PRI (0x00000700) //!< Bit mask for IPU_SRM_PRI1_CSI0_SRM_PRI.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI1_CSI0_SRM_PRI from a register value.
|
|
#define BG_IPU_SRM_PRI1_CSI0_SRM_PRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI1_CSI0_SRM_PRI) >> BP_IPU_SRM_PRI1_CSI0_SRM_PRI)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI1_CSI0_SRM_PRI.
|
|
#define BF_IPU_SRM_PRI1_CSI0_SRM_PRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI1_CSI0_SRM_PRI) & BM_IPU_SRM_PRI1_CSI0_SRM_PRI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SRM_PRI field to a new value.
|
|
#define BW_IPU_SRM_PRI1_CSI0_SRM_PRI(x, v) (HW_IPU_SRM_PRI1_WR(x, (HW_IPU_SRM_PRI1_RD(x) & ~BM_IPU_SRM_PRI1_CSI0_SRM_PRI) | BF_IPU_SRM_PRI1_CSI0_SRM_PRI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI1, field CSI0_SRM_MODE[12:11] (RW)
|
|
*
|
|
* CSI0 SRM Mode This field controls the SRM logic that handles the CSI0 registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the CSI1's region in the RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM Platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI1_CSI0_SRM_MODE (11) //!< Bit position for IPU_SRM_PRI1_CSI0_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI1_CSI0_SRM_MODE (0x00001800) //!< Bit mask for IPU_SRM_PRI1_CSI0_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI1_CSI0_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI1_CSI0_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI1_CSI0_SRM_MODE) >> BP_IPU_SRM_PRI1_CSI0_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI1_CSI0_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI1_CSI0_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI1_CSI0_SRM_MODE) & BM_IPU_SRM_PRI1_CSI0_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI1_CSI0_SRM_MODE(x, v) (HW_IPU_SRM_PRI1_WR(x, (HW_IPU_SRM_PRI1_RD(x) & ~BM_IPU_SRM_PRI1_CSI0_SRM_MODE) | BF_IPU_SRM_PRI1_CSI0_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SRM_PRI2 - Shadow Registers Memory Priority 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SRM_PRI2 - Shadow Registers Memory Priority 2 Register (RW)
|
|
*
|
|
* Reset value: 0x06050803
|
|
*
|
|
* The register controls the priority of SRM updates. The priority level for each block that has a
|
|
* shadow of its registers in the SRM should be unique. The priority level defines the order of SRM
|
|
* updates. a block with priority set to 010 will be updated before a block with priority set to
|
|
* 001.
|
|
*/
|
|
typedef union _hw_ipu_srm_pri2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_srm_pri2_bitfields
|
|
{
|
|
unsigned DP_SRM_PRI : 3; //!< [2:0] DP SRM priority
|
|
unsigned DP_S_SRM_MODE : 2; //!< [4:3] DP sync flow SRM Mode
|
|
unsigned DP_A0_SRM_MODE : 2; //!< [6:5] DP Async flow #0 SRM Mode
|
|
unsigned DP_A1_SRM_MODE : 2; //!< [8:7] DP Async flow #1 SRM Mode
|
|
unsigned DC_SRM_PRI : 3; //!< [11:9] DC SRM priority
|
|
unsigned DC_2_SRM_MODE : 2; //!< [13:12] DC Group #2 SRM Mode
|
|
unsigned DC_6_SRM_MODE : 2; //!< [15:14] DC Group #6 SRM Mode
|
|
unsigned DI0_SRM_PRI : 3; //!< [18:16] DI0 SRM priority
|
|
unsigned DI0_SRM_MCU_USE : 2; //!< [20:19] DI0 SRM is used by ARM platform
|
|
unsigned RESERVED0 : 3; //!< [23:21] Reserved
|
|
unsigned DI1_SRM_PRI : 3; //!< [26:24] DI1 SRM priority
|
|
unsigned DI1_SRM_MODE : 2; //!< [28:27] DCI1 SRM Mode
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved
|
|
} B;
|
|
} hw_ipu_srm_pri2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SRM_PRI2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SRM_PRI2_ADDR(x) (REGS_IPU_BASE(x) + 0xa4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SRM_PRI2(x) (*(volatile hw_ipu_srm_pri2_t *) HW_IPU_SRM_PRI2_ADDR(x))
|
|
#define HW_IPU_SRM_PRI2_RD(x) (HW_IPU_SRM_PRI2(x).U)
|
|
#define HW_IPU_SRM_PRI2_WR(x, v) (HW_IPU_SRM_PRI2(x).U = (v))
|
|
#define HW_IPU_SRM_PRI2_SET(x, v) (HW_IPU_SRM_PRI2_WR(x, HW_IPU_SRM_PRI2_RD(x) | (v)))
|
|
#define HW_IPU_SRM_PRI2_CLR(x, v) (HW_IPU_SRM_PRI2_WR(x, HW_IPU_SRM_PRI2_RD(x) & ~(v)))
|
|
#define HW_IPU_SRM_PRI2_TOG(x, v) (HW_IPU_SRM_PRI2_WR(x, HW_IPU_SRM_PRI2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SRM_PRI2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DP_SRM_PRI[2:0] (RW)
|
|
*
|
|
* DP SRM priority This bits define the priority of the DP module
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DP_SRM_PRI (0) //!< Bit position for IPU_SRM_PRI2_DP_SRM_PRI.
|
|
#define BM_IPU_SRM_PRI2_DP_SRM_PRI (0x00000007) //!< Bit mask for IPU_SRM_PRI2_DP_SRM_PRI.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DP_SRM_PRI from a register value.
|
|
#define BG_IPU_SRM_PRI2_DP_SRM_PRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DP_SRM_PRI) >> BP_IPU_SRM_PRI2_DP_SRM_PRI)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DP_SRM_PRI.
|
|
#define BF_IPU_SRM_PRI2_DP_SRM_PRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DP_SRM_PRI) & BM_IPU_SRM_PRI2_DP_SRM_PRI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_SRM_PRI field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DP_SRM_PRI(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DP_SRM_PRI) | BF_IPU_SRM_PRI2_DP_SRM_PRI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DP_S_SRM_MODE[4:3] (RW)
|
|
*
|
|
* DP sync flow SRM Mode This field controls the SRM logic that handles the DP sync flow registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the DP sync flow region in the RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done on the next frame.
|
|
* - 10 - Reserved
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DP_S_SRM_MODE (3) //!< Bit position for IPU_SRM_PRI2_DP_S_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI2_DP_S_SRM_MODE (0x00000018) //!< Bit mask for IPU_SRM_PRI2_DP_S_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DP_S_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DP_S_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DP_S_SRM_MODE) >> BP_IPU_SRM_PRI2_DP_S_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DP_S_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI2_DP_S_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DP_S_SRM_MODE) & BM_IPU_SRM_PRI2_DP_S_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_S_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DP_S_SRM_MODE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DP_S_SRM_MODE) | BF_IPU_SRM_PRI2_DP_S_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DP_A0_SRM_MODE[6:5] (RW)
|
|
*
|
|
* DP Async flow #0 SRM Mode This field controls the SRM logic that handles the DP Async flow #0
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the DP Async flow #0 region in the
|
|
* RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DP_A0_SRM_MODE (5) //!< Bit position for IPU_SRM_PRI2_DP_A0_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI2_DP_A0_SRM_MODE (0x00000060) //!< Bit mask for IPU_SRM_PRI2_DP_A0_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DP_A0_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DP_A0_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DP_A0_SRM_MODE) >> BP_IPU_SRM_PRI2_DP_A0_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DP_A0_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI2_DP_A0_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DP_A0_SRM_MODE) & BM_IPU_SRM_PRI2_DP_A0_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_A0_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DP_A0_SRM_MODE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DP_A0_SRM_MODE) | BF_IPU_SRM_PRI2_DP_A0_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DP_A1_SRM_MODE[8:7] (RW)
|
|
*
|
|
* DP Async flow #1 SRM Mode This field controls the SRM logic that handles the DP Async flow #1
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the DP Async flow #1 region in the
|
|
* RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DP_A1_SRM_MODE (7) //!< Bit position for IPU_SRM_PRI2_DP_A1_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI2_DP_A1_SRM_MODE (0x00000180) //!< Bit mask for IPU_SRM_PRI2_DP_A1_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DP_A1_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DP_A1_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DP_A1_SRM_MODE) >> BP_IPU_SRM_PRI2_DP_A1_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DP_A1_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI2_DP_A1_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DP_A1_SRM_MODE) & BM_IPU_SRM_PRI2_DP_A1_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_A1_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DP_A1_SRM_MODE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DP_A1_SRM_MODE) | BF_IPU_SRM_PRI2_DP_A1_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DC_SRM_PRI[11:9] (RW)
|
|
*
|
|
* DC SRM priority This bits define the priority of the DC module
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DC_SRM_PRI (9) //!< Bit position for IPU_SRM_PRI2_DC_SRM_PRI.
|
|
#define BM_IPU_SRM_PRI2_DC_SRM_PRI (0x00000e00) //!< Bit mask for IPU_SRM_PRI2_DC_SRM_PRI.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DC_SRM_PRI from a register value.
|
|
#define BG_IPU_SRM_PRI2_DC_SRM_PRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DC_SRM_PRI) >> BP_IPU_SRM_PRI2_DC_SRM_PRI)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DC_SRM_PRI.
|
|
#define BF_IPU_SRM_PRI2_DC_SRM_PRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DC_SRM_PRI) & BM_IPU_SRM_PRI2_DC_SRM_PRI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_SRM_PRI field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DC_SRM_PRI(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DC_SRM_PRI) | BF_IPU_SRM_PRI2_DC_SRM_PRI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DC_2_SRM_MODE[13:12] (RW)
|
|
*
|
|
* DC Group #2 SRM Mode This field controls the SRM logic that handles the DC Group #2 registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the DC Group #2's region in the
|
|
* RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DC_2_SRM_MODE (12) //!< Bit position for IPU_SRM_PRI2_DC_2_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI2_DC_2_SRM_MODE (0x00003000) //!< Bit mask for IPU_SRM_PRI2_DC_2_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DC_2_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DC_2_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DC_2_SRM_MODE) >> BP_IPU_SRM_PRI2_DC_2_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DC_2_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI2_DC_2_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DC_2_SRM_MODE) & BM_IPU_SRM_PRI2_DC_2_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_2_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DC_2_SRM_MODE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DC_2_SRM_MODE) | BF_IPU_SRM_PRI2_DC_2_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DC_6_SRM_MODE[15:14] (RW)
|
|
*
|
|
* DC Group #6 SRM Mode This field controls the SRM logic that handles the DC Group #6 registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the DC Group #6's region in the
|
|
* RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DC_6_SRM_MODE (14) //!< Bit position for IPU_SRM_PRI2_DC_6_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI2_DC_6_SRM_MODE (0x0000c000) //!< Bit mask for IPU_SRM_PRI2_DC_6_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DC_6_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DC_6_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DC_6_SRM_MODE) >> BP_IPU_SRM_PRI2_DC_6_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DC_6_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI2_DC_6_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DC_6_SRM_MODE) & BM_IPU_SRM_PRI2_DC_6_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_6_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DC_6_SRM_MODE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DC_6_SRM_MODE) | BF_IPU_SRM_PRI2_DC_6_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DI0_SRM_PRI[18:16] (RW)
|
|
*
|
|
* DI0 SRM priority This bits define the priority of the DI0 module
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DI0_SRM_PRI (16) //!< Bit position for IPU_SRM_PRI2_DI0_SRM_PRI.
|
|
#define BM_IPU_SRM_PRI2_DI0_SRM_PRI (0x00070000) //!< Bit mask for IPU_SRM_PRI2_DI0_SRM_PRI.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DI0_SRM_PRI from a register value.
|
|
#define BG_IPU_SRM_PRI2_DI0_SRM_PRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DI0_SRM_PRI) >> BP_IPU_SRM_PRI2_DI0_SRM_PRI)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DI0_SRM_PRI.
|
|
#define BF_IPU_SRM_PRI2_DI0_SRM_PRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DI0_SRM_PRI) & BM_IPU_SRM_PRI2_DI0_SRM_PRI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SRM_PRI field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DI0_SRM_PRI(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DI0_SRM_PRI) | BF_IPU_SRM_PRI2_DI0_SRM_PRI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DI0_SRM_MCU_USE[20:19] (RW)
|
|
*
|
|
* DI0 SRM is used by ARM platform This bit indicates that the registers of the DI0 are currently
|
|
* being updated by the ARM platform. The ARM platform should set this bit before accessing the SRM
|
|
* part that is relevant to the DI0. The ARM platform should clear this bit when the update
|
|
* procedure is finished. When this bit is set the SRM mechanism will not update the DI0's registers
|
|
* to avoid data coherency problems.
|
|
*
|
|
* Values:
|
|
* - 0 - DI0 SRM s currently not updated by the ARM platform
|
|
* - 1 - DI0 SRM is currently updated by the ARM platform
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DI0_SRM_MCU_USE (19) //!< Bit position for IPU_SRM_PRI2_DI0_SRM_MCU_USE.
|
|
#define BM_IPU_SRM_PRI2_DI0_SRM_MCU_USE (0x00180000) //!< Bit mask for IPU_SRM_PRI2_DI0_SRM_MCU_USE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DI0_SRM_MCU_USE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DI0_SRM_MCU_USE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DI0_SRM_MCU_USE) >> BP_IPU_SRM_PRI2_DI0_SRM_MCU_USE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DI0_SRM_MCU_USE.
|
|
#define BF_IPU_SRM_PRI2_DI0_SRM_MCU_USE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DI0_SRM_MCU_USE) & BM_IPU_SRM_PRI2_DI0_SRM_MCU_USE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SRM_MCU_USE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DI0_SRM_MCU_USE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DI0_SRM_MCU_USE) | BF_IPU_SRM_PRI2_DI0_SRM_MCU_USE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DI1_SRM_PRI[26:24] (RW)
|
|
*
|
|
* DI1 SRM priority This bits define the priority of the DI1 module
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DI1_SRM_PRI (24) //!< Bit position for IPU_SRM_PRI2_DI1_SRM_PRI.
|
|
#define BM_IPU_SRM_PRI2_DI1_SRM_PRI (0x07000000) //!< Bit mask for IPU_SRM_PRI2_DI1_SRM_PRI.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DI1_SRM_PRI from a register value.
|
|
#define BG_IPU_SRM_PRI2_DI1_SRM_PRI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DI1_SRM_PRI) >> BP_IPU_SRM_PRI2_DI1_SRM_PRI)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DI1_SRM_PRI.
|
|
#define BF_IPU_SRM_PRI2_DI1_SRM_PRI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DI1_SRM_PRI) & BM_IPU_SRM_PRI2_DI1_SRM_PRI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SRM_PRI field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DI1_SRM_PRI(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DI1_SRM_PRI) | BF_IPU_SRM_PRI2_DI1_SRM_PRI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_PRI2, field DI1_SRM_MODE[28:27] (RW)
|
|
*
|
|
* DCI1 SRM Mode This field controls the SRM logic that handles the DI1 registers
|
|
*
|
|
* Values:
|
|
* - 00 - Automatic swapping is disabled; ARM platform is allowed to access the DI1 region in the RAM
|
|
* - 01 - The SRM logic is controlled by the FSU. The update will be done of the next frame.
|
|
* - 10 - The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame
|
|
* - 11 - Update now. The SRM is controlled by the ARM platform. The Register will be update now
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_PRI2_DI1_SRM_MODE (27) //!< Bit position for IPU_SRM_PRI2_DI1_SRM_MODE.
|
|
#define BM_IPU_SRM_PRI2_DI1_SRM_MODE (0x18000000) //!< Bit mask for IPU_SRM_PRI2_DI1_SRM_MODE.
|
|
|
|
//! @brief Get value of IPU_SRM_PRI2_DI1_SRM_MODE from a register value.
|
|
#define BG_IPU_SRM_PRI2_DI1_SRM_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_PRI2_DI1_SRM_MODE) >> BP_IPU_SRM_PRI2_DI1_SRM_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_SRM_PRI2_DI1_SRM_MODE.
|
|
#define BF_IPU_SRM_PRI2_DI1_SRM_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SRM_PRI2_DI1_SRM_MODE) & BM_IPU_SRM_PRI2_DI1_SRM_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SRM_MODE field to a new value.
|
|
#define BW_IPU_SRM_PRI2_DI1_SRM_MODE(x, v) (HW_IPU_SRM_PRI2_WR(x, (HW_IPU_SRM_PRI2_RD(x) & ~BM_IPU_SRM_PRI2_DI1_SRM_MODE) | BF_IPU_SRM_PRI2_DI1_SRM_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_FS_PROC_FLOW1 - FSU Processing Flow 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_FS_PROC_FLOW1 - FSU Processing Flow 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contain controls for IPU's tasks.
|
|
*/
|
|
typedef union _hw_ipu_fs_proc_flow1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_fs_proc_flow1_bitfields
|
|
{
|
|
unsigned PRPENC_ROT_SRC_SEL : 4; //!< [3:0] Source select for the encoding task of the IRT
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved
|
|
unsigned PRPVF_ROT_SRC_SEL : 4; //!< [11:8] Source select for the view finder task of the IRT
|
|
unsigned PP_SRC_SEL : 4; //!< [15:12] Source select for the pre processing task of the IC
|
|
unsigned PP_ROT_SRC_SEL : 4; //!< [19:16] Source select for the pre processing task of the IRT (CH 50)
|
|
unsigned VDI1_SRC_SEL : 2; //!< [21:20] Source select for the VDIC plane #1 (IDMAC's CH26)
|
|
unsigned VDI3_SRC_SEL : 2; //!< [23:22] Source select for the VDIC plane #3 (IDMAC's CH 25)
|
|
unsigned PRP_SRC_SEL : 4; //!< [27:24] Source select for the Pre Processing Task
|
|
unsigned VDI_SRC_SEL : 2; //!< [29:28] Source select for the VDI C
|
|
unsigned ENC_IN_VALID : 1; //!< [30] Encoding Input valid.
|
|
unsigned VF_IN_VALID : 1; //!< [31] View-finder Input valid.
|
|
} B;
|
|
} hw_ipu_fs_proc_flow1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_FS_PROC_FLOW1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_FS_PROC_FLOW1_ADDR(x) (REGS_IPU_BASE(x) + 0xa8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_FS_PROC_FLOW1(x) (*(volatile hw_ipu_fs_proc_flow1_t *) HW_IPU_FS_PROC_FLOW1_ADDR(x))
|
|
#define HW_IPU_FS_PROC_FLOW1_RD(x) (HW_IPU_FS_PROC_FLOW1(x).U)
|
|
#define HW_IPU_FS_PROC_FLOW1_WR(x, v) (HW_IPU_FS_PROC_FLOW1(x).U = (v))
|
|
#define HW_IPU_FS_PROC_FLOW1_SET(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, HW_IPU_FS_PROC_FLOW1_RD(x) | (v)))
|
|
#define HW_IPU_FS_PROC_FLOW1_CLR(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, HW_IPU_FS_PROC_FLOW1_RD(x) & ~(v)))
|
|
#define HW_IPU_FS_PROC_FLOW1_TOG(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, HW_IPU_FS_PROC_FLOW1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_FS_PROC_FLOW1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field PRPENC_ROT_SRC_SEL[3:0] (RW)
|
|
*
|
|
* Source select for the encoding task of the IRT
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture1 (smfc1)
|
|
* - 0011 - capture2 (smfc2)
|
|
* - 0100 - capture3 (smfc3)
|
|
* - 0101 - IC direct (cb7)
|
|
* - 0110 - Reserved
|
|
* - 0111 - encoding
|
|
* - 1000 - Reserved
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL (0) //!< Bit position for IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL (0x0000000f) //!< Bit mask for IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_ROT_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_PRPENC_ROT_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field PRPVF_ROT_SRC_SEL[11:8] (RW)
|
|
*
|
|
* Source select for the view finder task of the IRT 0000 ARM platform
|
|
*
|
|
* Values:
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture1 (smfc1)
|
|
* - 0011 - capture2 (smfc2)
|
|
* - 0100 - capture3 (smfc3)
|
|
* - 0101 - IC direct (cb7)
|
|
* - 0110 - Reserved
|
|
* - 0111 - Reserved
|
|
* - 1000 - View-finder
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL (8) //!< Bit position for IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL (0x00000f00) //!< Bit mask for IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_ROT_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_PRPVF_ROT_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field PP_SRC_SEL[15:12] (RW)
|
|
*
|
|
* Source select for the pre processing task of the IC
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - Reserved
|
|
* - 0011 - capture2 (smfc2)
|
|
* - 0100 - Reserved
|
|
* - 0101 - Reserved
|
|
* - 0110 - Rotation for post-processing
|
|
* - 0111 - Reserved
|
|
* - 1000 - Reserved
|
|
* - 1000 - VDOA
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_PP_SRC_SEL (12) //!< Bit position for IPU_FS_PROC_FLOW1_PP_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_PP_SRC_SEL (0x0000f000) //!< Bit mask for IPU_FS_PROC_FLOW1_PP_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_PP_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_PP_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_PP_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_PP_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_PP_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_PP_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_PP_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_PP_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_PP_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_PP_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_PP_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field PP_ROT_SRC_SEL[19:16] (RW)
|
|
*
|
|
* Source select for the pre processing task of the IRT (CH 50)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - Reserved
|
|
* - 0011 - capture2 (smfc2)
|
|
* - 0100 - Reserved
|
|
* - 0101 - Post-processing
|
|
* - 0110 - Reserved
|
|
* - 0111 - Reserved
|
|
* - 1000 - Reserved
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL (16) //!< Bit position for IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL (0x000f0000) //!< Bit mask for IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_ROT_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_PP_ROT_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field VDI1_SRC_SEL[21:20] (RW)
|
|
*
|
|
* Source select for the VDIC plane #1 (IDMAC's CH26) This field is relevant only if the VDIC works
|
|
* in combining mode (VDI_CMB_EN bit is set)
|
|
*
|
|
* Values:
|
|
* - 00 - ARM platform
|
|
* - 01 - IRT viewfinder
|
|
* - 10 - IRT playback
|
|
* - 11 - post-processing
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL (20) //!< Bit position for IPU_FS_PROC_FLOW1_VDI1_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL (0x00300000) //!< Bit mask for IPU_FS_PROC_FLOW1_VDI1_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_VDI1_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_VDI1_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI1_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_VDI1_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field VDI3_SRC_SEL[23:22] (RW)
|
|
*
|
|
* Source select for the VDIC plane #3 (IDMAC's CH 25)
|
|
*
|
|
* Values:
|
|
* - 00 - ARM platform This field is relevant only if the VDIC works in combining mode (VDI_CMB_EN bit is set)
|
|
* - 01 - IRT viewfinder (ch 49)
|
|
* - 10 - IRT playback (ch 50)
|
|
* - 11 - post-processing (ch 22)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL (22) //!< Bit position for IPU_FS_PROC_FLOW1_VDI3_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL (0x00c00000) //!< Bit mask for IPU_FS_PROC_FLOW1_VDI3_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_VDI3_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_VDI3_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI3_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_VDI3_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field PRP_SRC_SEL[27:24] (RW)
|
|
*
|
|
* Source select for the Pre Processing Task 0000 ARM platform
|
|
*
|
|
* Values:
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0011 - capture2 (smfc2)
|
|
* - 0101 - IC direct (cb7)
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - Reserved
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_PRP_SRC_SEL (24) //!< Bit position for IPU_FS_PROC_FLOW1_PRP_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_PRP_SRC_SEL (0x0f000000) //!< Bit mask for IPU_FS_PROC_FLOW1_PRP_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_PRP_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_PRP_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_PRP_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_PRP_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_PRP_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_PRP_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_PRP_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_PRP_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRP_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_PRP_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_PRP_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_PRP_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field VDI_SRC_SEL[29:28] (RW)
|
|
*
|
|
* Source select for the VDI C This field is relevant if the VDIC works in de-interlacing mode (when
|
|
* VDI_CMB_EN bit is clear)
|
|
*
|
|
* Values:
|
|
* - 00 - ARM platform
|
|
* - 01 - CSI direct (cb7)
|
|
* - 10 - Reserved
|
|
* - 10 - VDOA
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_VDI_SRC_SEL (28) //!< Bit position for IPU_FS_PROC_FLOW1_VDI_SRC_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW1_VDI_SRC_SEL (0x30000000) //!< Bit mask for IPU_FS_PROC_FLOW1_VDI_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_VDI_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_VDI_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_VDI_SRC_SEL) >> BP_IPU_FS_PROC_FLOW1_VDI_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_VDI_SRC_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW1_VDI_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_VDI_SRC_SEL) & BM_IPU_FS_PROC_FLOW1_VDI_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_VDI_SRC_SEL(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_VDI_SRC_SEL) | BF_IPU_FS_PROC_FLOW1_VDI_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field ENC_IN_VALID[30] (RW)
|
|
*
|
|
* Encoding Input valid. Setting this bit indicates that the buffer in memory for encoding is
|
|
* validated by the ARM platform (valid only when RWS_EN is '1').
|
|
*
|
|
* Values:
|
|
* - 0 - Encoding should skip buffer in memory.
|
|
* - 1 - Encoding should use buffer in memory.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_ENC_IN_VALID (30) //!< Bit position for IPU_FS_PROC_FLOW1_ENC_IN_VALID.
|
|
#define BM_IPU_FS_PROC_FLOW1_ENC_IN_VALID (0x40000000) //!< Bit mask for IPU_FS_PROC_FLOW1_ENC_IN_VALID.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_ENC_IN_VALID from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_ENC_IN_VALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_ENC_IN_VALID) >> BP_IPU_FS_PROC_FLOW1_ENC_IN_VALID)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_ENC_IN_VALID.
|
|
#define BF_IPU_FS_PROC_FLOW1_ENC_IN_VALID(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_ENC_IN_VALID) & BM_IPU_FS_PROC_FLOW1_ENC_IN_VALID)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ENC_IN_VALID field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_ENC_IN_VALID(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_ENC_IN_VALID) | BF_IPU_FS_PROC_FLOW1_ENC_IN_VALID(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW1, field VF_IN_VALID[31] (RW)
|
|
*
|
|
* View-finder Input valid. Setting this bit indicates that the buffer in memory for viewfinder is
|
|
* validated by the ARM platform (valid only when RWS_EN is '1').
|
|
*
|
|
* Values:
|
|
* - 0 - View-finder should skip buffer in memory.
|
|
* - 1 - View-finder should use buffer in memory.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW1_VF_IN_VALID (31) //!< Bit position for IPU_FS_PROC_FLOW1_VF_IN_VALID.
|
|
#define BM_IPU_FS_PROC_FLOW1_VF_IN_VALID (0x80000000) //!< Bit mask for IPU_FS_PROC_FLOW1_VF_IN_VALID.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW1_VF_IN_VALID from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW1_VF_IN_VALID(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW1_VF_IN_VALID) >> BP_IPU_FS_PROC_FLOW1_VF_IN_VALID)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW1_VF_IN_VALID.
|
|
#define BF_IPU_FS_PROC_FLOW1_VF_IN_VALID(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW1_VF_IN_VALID) & BM_IPU_FS_PROC_FLOW1_VF_IN_VALID)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VF_IN_VALID field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW1_VF_IN_VALID(x, v) (HW_IPU_FS_PROC_FLOW1_WR(x, (HW_IPU_FS_PROC_FLOW1_RD(x) & ~BM_IPU_FS_PROC_FLOW1_VF_IN_VALID) | BF_IPU_FS_PROC_FLOW1_VF_IN_VALID(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_FS_PROC_FLOW2 - FSU Processing Flow 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_FS_PROC_FLOW2 - FSU Processing Flow 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains controls for IPU's tasks.
|
|
*/
|
|
typedef union _hw_ipu_fs_proc_flow2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_fs_proc_flow2_bitfields
|
|
{
|
|
unsigned PRP_ENC_DEST_SEL : 4; //!< [3:0] Destination select for Encoding task
|
|
unsigned PRPVF_DEST_SEL : 4; //!< [7:4] Destination select for View finder task
|
|
unsigned PRPVF_ROT_DEST_SEL : 4; //!< [11:8] Destination select for Rotation task coming from the View finder input
|
|
unsigned PP_DEST_SEL : 4; //!< [15:12] Destination select for post processing task
|
|
unsigned PP_ROT_DEST_SEL : 4; //!< [19:16] Destination select for Rotation task coming from the Post Processing input
|
|
unsigned PRPENC_ROT_DEST_SEL : 4; //!< [23:20] Destination select for Rotation task coming from the Encoding input
|
|
unsigned PRP_DEST_SEL : 4; //!< [27:24] Pre processing destination select (for channel DMAIC_7)
|
|
unsigned RESERVED0 : 4; //!< [31:28] Reserved
|
|
} B;
|
|
} hw_ipu_fs_proc_flow2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_FS_PROC_FLOW2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_FS_PROC_FLOW2_ADDR(x) (REGS_IPU_BASE(x) + 0xac)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_FS_PROC_FLOW2(x) (*(volatile hw_ipu_fs_proc_flow2_t *) HW_IPU_FS_PROC_FLOW2_ADDR(x))
|
|
#define HW_IPU_FS_PROC_FLOW2_RD(x) (HW_IPU_FS_PROC_FLOW2(x).U)
|
|
#define HW_IPU_FS_PROC_FLOW2_WR(x, v) (HW_IPU_FS_PROC_FLOW2(x).U = (v))
|
|
#define HW_IPU_FS_PROC_FLOW2_SET(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, HW_IPU_FS_PROC_FLOW2_RD(x) | (v)))
|
|
#define HW_IPU_FS_PROC_FLOW2_CLR(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, HW_IPU_FS_PROC_FLOW2_RD(x) & ~(v)))
|
|
#define HW_IPU_FS_PROC_FLOW2_TOG(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, HW_IPU_FS_PROC_FLOW2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_FS_PROC_FLOW2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PRP_ENC_DEST_SEL[3:0] (RW)
|
|
*
|
|
* Destination select for Encoding task
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - IRT Encoding
|
|
* - 0010 - Reserved
|
|
* - 0011 - Reserved
|
|
* - 0100 - Reserved
|
|
* - 0101 - Reserved
|
|
* - 0110 - Reserved
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL (0) //!< Bit position for IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL (0x0000000f) //!< Bit mask for IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRP_ENC_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PRP_ENC_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PRPVF_DEST_SEL[7:4] (RW)
|
|
*
|
|
* Destination select for View finder task
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - IRT viewfinder
|
|
* - 0010 - Reserved
|
|
* - 0011 - Reserved
|
|
* - 0100 - Reserved
|
|
* - 0101 - Reserved
|
|
* - 0110 - Reserved
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL (4) //!< Bit position for IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL (0x000000f0) //!< Bit mask for IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PRPVF_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PRPVF_ROT_DEST_SEL[11:8] (RW)
|
|
*
|
|
* Destination select for Rotation task coming from the View finder input
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - Reserved
|
|
* - 0010 - Reserved
|
|
* - 0011 - VDI_PLANE3 (Ch 25)
|
|
* - 0100 - VDI_PLANE1 (Ch 26)
|
|
* - 0101 - IC Pre Processing
|
|
* - 0110 - Reserved
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL (8) //!< Bit position for IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL (0x00000f00) //!< Bit mask for IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_ROT_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PRPVF_ROT_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PP_DEST_SEL[15:12] (RW)
|
|
*
|
|
* Destination select for post processing task
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - Reserved
|
|
* - 0010 - Reserved
|
|
* - 0011 - IRT playback
|
|
* - 0100 - VDI_PLANE3 (Ch 25)
|
|
* - 0101 - VDI_PLANE1 (Ch 26)
|
|
* - 0110 - Reserved
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PP_DEST_SEL (12) //!< Bit position for IPU_FS_PROC_FLOW2_PP_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PP_DEST_SEL (0x0000f000) //!< Bit mask for IPU_FS_PROC_FLOW2_PP_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PP_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PP_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PP_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PP_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PP_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PP_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PP_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PP_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PP_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PP_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PP_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PP_ROT_DEST_SEL[19:16] (RW)
|
|
*
|
|
* Destination select for Rotation task coming from the Post Processing input
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - Reserved
|
|
* - 0010 - Reserved
|
|
* - 0011 - Reserved
|
|
* - 0100 - IC Playback (Post Processing)
|
|
* - 0101 - VDI_PLANE3 (Ch 25)
|
|
* - 0110 - VDI_PLANE1 (Ch 26)
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL (16) //!< Bit position for IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL (0x000f0000) //!< Bit mask for IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_ROT_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PP_ROT_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PRPENC_ROT_DEST_SEL[23:20] (RW)
|
|
*
|
|
* Destination select for Rotation task coming from the Encoding input
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - Reserved
|
|
* - 0010 - Reserved
|
|
* - 0011 - Reserved
|
|
* - 0100 - Reserved
|
|
* - 0101 - IC Pre Processing
|
|
* - 0110 - Reserved
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL (20) //!< Bit position for IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL (0x00f00000) //!< Bit mask for IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_ROT_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PRPENC_ROT_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW2, field PRP_DEST_SEL[27:24] (RW)
|
|
*
|
|
* Pre processing destination select (for channel DMAIC_7)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - IC input buffer (ch12)
|
|
* - 0010 - PP (ch11)
|
|
* - 0011 - PP_ROT (ch47)
|
|
* - 0100 - DC1 (ch28)
|
|
* - 0101 - DC2 (ch41)
|
|
* - 0110 - DP_ASYNC1 (ch24)
|
|
* - 0111 - DP_ASYNC0 (ch29)
|
|
* - 1000 - DP_SYNC1 (ch27)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - Alt DC2 (ch41)
|
|
* - 1011 - Alt DP_ASYNC1 (ch24)
|
|
* - 1100 - Alt DP_ASYNC0 (ch29)
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW2_PRP_DEST_SEL (24) //!< Bit position for IPU_FS_PROC_FLOW2_PRP_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW2_PRP_DEST_SEL (0x0f000000) //!< Bit mask for IPU_FS_PROC_FLOW2_PRP_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW2_PRP_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW2_PRP_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW2_PRP_DEST_SEL) >> BP_IPU_FS_PROC_FLOW2_PRP_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW2_PRP_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW2_PRP_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW2_PRP_DEST_SEL) & BM_IPU_FS_PROC_FLOW2_PRP_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRP_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW2_PRP_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW2_WR(x, (HW_IPU_FS_PROC_FLOW2_RD(x) & ~BM_IPU_FS_PROC_FLOW2_PRP_DEST_SEL) | BF_IPU_FS_PROC_FLOW2_PRP_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_FS_PROC_FLOW3 - FSU Processing Flow 3 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_FS_PROC_FLOW3 - FSU Processing Flow 3 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains controls for IPU's tasks. Hide VPU_SUB_FRAME_SYNC for all versions Show
|
|
* VPU_SUB_FRAME_SYNC for IPUv3H version. The table below tagged with other settings (like
|
|
* IPU3M_only) should be hidden in IPUv3H version. This requires some sophisticated conditional tag
|
|
* settings
|
|
*/
|
|
typedef union _hw_ipu_fs_proc_flow3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_fs_proc_flow3_bitfields
|
|
{
|
|
unsigned SMFC0_DEST_SEL : 4; //!< [3:0] Destination select for SMFC0
|
|
unsigned SMFC1_DEST_SEL : 3; //!< [6:4] Destination select for SMFC1
|
|
unsigned SMFC2_DEST_SEL : 4; //!< [10:7] Destination select for SMFC2
|
|
unsigned SMFC3_DEST_SEL : 3; //!< [13:11] Destination select for SMFC3
|
|
unsigned RESERVED0 : 2; //!< [15:14] Reserved
|
|
unsigned VDOA_DEST_SEL : 2; //!< [17:16] Destination select for VDOA
|
|
unsigned RESERVED1 : 2; //!< [19:18] Reserved
|
|
unsigned EXT_SRC1_DEST_SEL : 2; //!< [21:20] Destination select for External Source 1
|
|
unsigned EXT_SRC2_DEST_SEL : 2; //!< [23:22] Destination select for External Source 2
|
|
unsigned VPU_DEST_SEL : 2; //!< [25:24] This bits selects the corresponding IDMAC channel's EOL indication to be used for sub frame synchronization with the VPU.
|
|
unsigned RESERVED2 : 6; //!< [31:26] Reserved
|
|
} B;
|
|
} hw_ipu_fs_proc_flow3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_FS_PROC_FLOW3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_FS_PROC_FLOW3_ADDR(x) (REGS_IPU_BASE(x) + 0xb0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_FS_PROC_FLOW3(x) (*(volatile hw_ipu_fs_proc_flow3_t *) HW_IPU_FS_PROC_FLOW3_ADDR(x))
|
|
#define HW_IPU_FS_PROC_FLOW3_RD(x) (HW_IPU_FS_PROC_FLOW3(x).U)
|
|
#define HW_IPU_FS_PROC_FLOW3_WR(x, v) (HW_IPU_FS_PROC_FLOW3(x).U = (v))
|
|
#define HW_IPU_FS_PROC_FLOW3_SET(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, HW_IPU_FS_PROC_FLOW3_RD(x) | (v)))
|
|
#define HW_IPU_FS_PROC_FLOW3_CLR(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, HW_IPU_FS_PROC_FLOW3_RD(x) & ~(v)))
|
|
#define HW_IPU_FS_PROC_FLOW3_TOG(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, HW_IPU_FS_PROC_FLOW3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_FS_PROC_FLOW3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field SMFC0_DEST_SEL[3:0] (RW)
|
|
*
|
|
* Destination select for SMFC0
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - IRT Encoding
|
|
* - 0010 - IRT viewfinder
|
|
* - 0011 - IRT playback
|
|
* - 0100 - IC Playback (Post Processing)
|
|
* - 0101 - IC Pre Processing
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL (0) //!< Bit position for IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL (0x0000000f) //!< Bit mask for IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC0_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_SMFC0_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field SMFC1_DEST_SEL[6:4] (RW)
|
|
*
|
|
* Destination select for SMFC1
|
|
*
|
|
* Values:
|
|
* - 000 - ARM platform
|
|
* - 001 - IRT Encoding
|
|
* - 010 - IRT viewfinder
|
|
* - 011 - IRT playback
|
|
* - 100 - IC Playback (Post Processing)
|
|
* - 101 - IC Pre Processing
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL (4) //!< Bit position for IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL (0x00000070) //!< Bit mask for IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC1_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_SMFC1_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field SMFC2_DEST_SEL[10:7] (RW)
|
|
*
|
|
* Destination select for SMFC2
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - IRT Encoding
|
|
* - 0010 - IRT viewfinder
|
|
* - 0011 - IRT playback
|
|
* - 0100 - IC Playback (Post Processing)
|
|
* - 0101 - IC Pre Processing
|
|
* - 0111 - DC1 (ch28)
|
|
* - 1000 - DC2 (ch41)
|
|
* - 1001 - DP_SYNC0 (ch23)
|
|
* - 1010 - DP_SYNC1 (ch27)
|
|
* - 1011 - DP_ASYNC1 (ch24)
|
|
* - 1100 - DP_ASYNC0 (ch29)
|
|
* - 1101 - Alt DC2 (ch41)
|
|
* - 1110 - Alt DP_ASYNC1 (ch24)
|
|
* - 1111 - Alt DP_ASYNC0 (ch29)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL (7) //!< Bit position for IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL (0x00000780) //!< Bit mask for IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC2_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_SMFC2_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field SMFC3_DEST_SEL[13:11] (RW)
|
|
*
|
|
* Destination select for SMFC3
|
|
*
|
|
* Values:
|
|
* - 000 - ARM platform
|
|
* - 001 - IRT Encoding
|
|
* - 010 - IRT viewfinder
|
|
* - 011 - IRT playback
|
|
* - 100 - IC Playback (Post Processing)
|
|
* - 101 - IC Pre Processing
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL (11) //!< Bit position for IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL (0x00003800) //!< Bit mask for IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC3_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_SMFC3_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field VDOA_DEST_SEL[17:16] (RW)
|
|
*
|
|
* Destination select for VDOA
|
|
*
|
|
* Values:
|
|
* - 00 - disabled
|
|
* - 01 - IC Playback (Post Processing)
|
|
* - 10 - VDI (ch8,ch9 & ch10 or ch9 according to VDI_MOT_SEL settings)
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL (16) //!< Bit position for IPU_FS_PROC_FLOW3_VDOA_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL (0x00030000) //!< Bit mask for IPU_FS_PROC_FLOW3_VDOA_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_VDOA_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_VDOA_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDOA_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_VDOA_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field EXT_SRC1_DEST_SEL[21:20] (RW)
|
|
*
|
|
* Destination select for External Source 1
|
|
*
|
|
* Values:
|
|
* - 00 - disabled
|
|
* - 01 - DP_SYNC0 (ch23)
|
|
* - 10 - DP_SYNC1 (ch27)
|
|
* - 11 - DC1 (ch28)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL (20) //!< Bit position for IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL (0x00300000) //!< Bit mask for IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL.
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|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL)
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|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the EXT_SRC1_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_EXT_SRC1_DEST_SEL(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field EXT_SRC2_DEST_SEL[23:22] (RW)
|
|
*
|
|
* Destination select for External Source 2
|
|
*
|
|
* Values:
|
|
* - 00 - disabled
|
|
* - 01 - DP_SYNC0 (ch23)
|
|
* - 10 - DP_SYNC1 (ch27)
|
|
* - 11 - DC1 (ch28)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL (22) //!< Bit position for IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL (0x00c00000) //!< Bit mask for IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL.
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|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL)
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|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the EXT_SRC2_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_EXT_SRC2_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_PROC_FLOW3, field VPU_DEST_SEL[25:24] (RW)
|
|
*
|
|
* This bits selects the corresponding IDMAC channel's EOL indication to be used for sub frame
|
|
* synchronization with the VPU. The corresponding IDMAC channel's EOLI bit at the CPMEM has to be
|
|
* set as well.
|
|
*
|
|
* Values:
|
|
* - 00 - disabled
|
|
* - 01 - capture0 (smfc0) (ch0)
|
|
* - 10 - capture2 (smfc2) (ch2)
|
|
* - 11 - IC viewfinder (ch21)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_PROC_FLOW3_VPU_DEST_SEL (24) //!< Bit position for IPU_FS_PROC_FLOW3_VPU_DEST_SEL.
|
|
#define BM_IPU_FS_PROC_FLOW3_VPU_DEST_SEL (0x03000000) //!< Bit mask for IPU_FS_PROC_FLOW3_VPU_DEST_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_PROC_FLOW3_VPU_DEST_SEL from a register value.
|
|
#define BG_IPU_FS_PROC_FLOW3_VPU_DEST_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_PROC_FLOW3_VPU_DEST_SEL) >> BP_IPU_FS_PROC_FLOW3_VPU_DEST_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_PROC_FLOW3_VPU_DEST_SEL.
|
|
#define BF_IPU_FS_PROC_FLOW3_VPU_DEST_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_PROC_FLOW3_VPU_DEST_SEL) & BM_IPU_FS_PROC_FLOW3_VPU_DEST_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VPU_DEST_SEL field to a new value.
|
|
#define BW_IPU_FS_PROC_FLOW3_VPU_DEST_SEL(x, v) (HW_IPU_FS_PROC_FLOW3_WR(x, (HW_IPU_FS_PROC_FLOW3_RD(x) & ~BM_IPU_FS_PROC_FLOW3_VPU_DEST_SEL) | BF_IPU_FS_PROC_FLOW3_VPU_DEST_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_FS_DISP_FLOW1 - FSU Displaying Flow 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_FS_DISP_FLOW1 - FSU Displaying Flow 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains controls for IPU's tasks.
|
|
*/
|
|
typedef union _hw_ipu_fs_disp_flow1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_fs_disp_flow1_bitfields
|
|
{
|
|
unsigned DP_SYNC0_SRC_SEL : 4; //!< [3:0] Source select for DS2 - MG (graphics) plane (ch23)
|
|
unsigned DP_SYNC1_SRC_SEL : 4; //!< [7:4] Source select for DS1/DS2 - Vx (video) plane (ch27)
|
|
unsigned DP_ASYNC0_SRC_SEL : 4; //!< [11:8] Source select for DS2 - MG (graphics) plane (ch29)
|
|
unsigned DP_ASYNC1_SRC_SEL : 4; //!< [15:12] Source select for DS1/DS2 - Vx (video) plane (ch24)
|
|
unsigned DC2_SRC_SEL : 4; //!< [19:16] Source select for DS3 (ch41)
|
|
unsigned DC1_SRC_SEL : 4; //!< [23:20] Source select for DS1/DS2 - MG (graphics) plane (ch28)
|
|
unsigned RESERVED0 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_fs_disp_flow1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_FS_DISP_FLOW1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_FS_DISP_FLOW1_ADDR(x) (REGS_IPU_BASE(x) + 0xb4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_FS_DISP_FLOW1(x) (*(volatile hw_ipu_fs_disp_flow1_t *) HW_IPU_FS_DISP_FLOW1_ADDR(x))
|
|
#define HW_IPU_FS_DISP_FLOW1_RD(x) (HW_IPU_FS_DISP_FLOW1(x).U)
|
|
#define HW_IPU_FS_DISP_FLOW1_WR(x, v) (HW_IPU_FS_DISP_FLOW1(x).U = (v))
|
|
#define HW_IPU_FS_DISP_FLOW1_SET(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, HW_IPU_FS_DISP_FLOW1_RD(x) | (v)))
|
|
#define HW_IPU_FS_DISP_FLOW1_CLR(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, HW_IPU_FS_DISP_FLOW1_RD(x) & ~(v)))
|
|
#define HW_IPU_FS_DISP_FLOW1_TOG(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, HW_IPU_FS_DISP_FLOW1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_FS_DISP_FLOW1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW1, field DP_SYNC0_SRC_SEL[3:0] (RW)
|
|
*
|
|
* Source select for DS2 - MG (graphics) plane (ch23)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL (0) //!< Bit position for IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL (0x0000000f) //!< Bit mask for IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL) >> BP_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL) & BM_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_SYNC0_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, (HW_IPU_FS_DISP_FLOW1_RD(x) & ~BM_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL) | BF_IPU_FS_DISP_FLOW1_DP_SYNC0_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW1, field DP_SYNC1_SRC_SEL[7:4] (RW)
|
|
*
|
|
* Source select for DS1/DS2 - Vx (video) plane (ch27)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL (4) //!< Bit position for IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL (0x000000f0) //!< Bit mask for IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL) >> BP_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL) & BM_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_SYNC1_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, (HW_IPU_FS_DISP_FLOW1_RD(x) & ~BM_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL) | BF_IPU_FS_DISP_FLOW1_DP_SYNC1_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW1, field DP_ASYNC0_SRC_SEL[11:8] (RW)
|
|
*
|
|
* Source select for DS2 - MG (graphics) plane (ch29)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL (8) //!< Bit position for IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL (0x00000f00) //!< Bit mask for IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL) >> BP_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL) & BM_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASYNC0_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, (HW_IPU_FS_DISP_FLOW1_RD(x) & ~BM_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL) | BF_IPU_FS_DISP_FLOW1_DP_ASYNC0_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW1, field DP_ASYNC1_SRC_SEL[15:12] (RW)
|
|
*
|
|
* Source select for DS1/DS2 - Vx (video) plane (ch24)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL (12) //!< Bit position for IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL (0x0000f000) //!< Bit mask for IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL) >> BP_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL) & BM_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASYNC1_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, (HW_IPU_FS_DISP_FLOW1_RD(x) & ~BM_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL) | BF_IPU_FS_DISP_FLOW1_DP_ASYNC1_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW1, field DC2_SRC_SEL[19:16] (RW)
|
|
*
|
|
* Source select for DS3 (ch41)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW1_DC2_SRC_SEL (16) //!< Bit position for IPU_FS_DISP_FLOW1_DC2_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW1_DC2_SRC_SEL (0x000f0000) //!< Bit mask for IPU_FS_DISP_FLOW1_DC2_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW1_DC2_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW1_DC2_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW1_DC2_SRC_SEL) >> BP_IPU_FS_DISP_FLOW1_DC2_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW1_DC2_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW1_DC2_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW1_DC2_SRC_SEL) & BM_IPU_FS_DISP_FLOW1_DC2_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC2_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW1_DC2_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, (HW_IPU_FS_DISP_FLOW1_RD(x) & ~BM_IPU_FS_DISP_FLOW1_DC2_SRC_SEL) | BF_IPU_FS_DISP_FLOW1_DC2_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW1, field DC1_SRC_SEL[23:20] (RW)
|
|
*
|
|
* Source select for DS1/DS2 - MG (graphics) plane (ch28)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - External source #1 (e.g. an external block like GPU)
|
|
* - 1110 - snoop1
|
|
* - 1111 - External source #2 (e.g. an external block like GPU)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW1_DC1_SRC_SEL (20) //!< Bit position for IPU_FS_DISP_FLOW1_DC1_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW1_DC1_SRC_SEL (0x00f00000) //!< Bit mask for IPU_FS_DISP_FLOW1_DC1_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW1_DC1_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW1_DC1_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW1_DC1_SRC_SEL) >> BP_IPU_FS_DISP_FLOW1_DC1_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW1_DC1_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW1_DC1_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW1_DC1_SRC_SEL) & BM_IPU_FS_DISP_FLOW1_DC1_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC1_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW1_DC1_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW1_WR(x, (HW_IPU_FS_DISP_FLOW1_RD(x) & ~BM_IPU_FS_DISP_FLOW1_DC1_SRC_SEL) | BF_IPU_FS_DISP_FLOW1_DC1_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_FS_DISP_FLOW2 - FSU Displaying Flow 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_FS_DISP_FLOW2 - FSU Displaying Flow 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains controls for IPU's tasks.
|
|
*/
|
|
typedef union _hw_ipu_fs_disp_flow2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_fs_disp_flow2_bitfields
|
|
{
|
|
unsigned DP_ASYNC0_ALT_SRC_SEL : 4; //!< [3:0] Source select for alternate DS2 - MG (graphics) plane (ch29)
|
|
unsigned DP_ASYNC1_ALT_SRC_SEL : 4; //!< [7:4] Source select for alternate DS1/DS2 - Vx (video) plane (ch24)
|
|
unsigned RESERVED0 : 8; //!< [15:8] Reserved
|
|
unsigned DC2_ALT_SRC_SEL : 4; //!< [19:16] Source select for Alternate DS3 (ch41)
|
|
unsigned RESERVED1 : 12; //!< [31:20] Reserved
|
|
} B;
|
|
} hw_ipu_fs_disp_flow2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_FS_DISP_FLOW2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_FS_DISP_FLOW2_ADDR(x) (REGS_IPU_BASE(x) + 0xb8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_FS_DISP_FLOW2(x) (*(volatile hw_ipu_fs_disp_flow2_t *) HW_IPU_FS_DISP_FLOW2_ADDR(x))
|
|
#define HW_IPU_FS_DISP_FLOW2_RD(x) (HW_IPU_FS_DISP_FLOW2(x).U)
|
|
#define HW_IPU_FS_DISP_FLOW2_WR(x, v) (HW_IPU_FS_DISP_FLOW2(x).U = (v))
|
|
#define HW_IPU_FS_DISP_FLOW2_SET(x, v) (HW_IPU_FS_DISP_FLOW2_WR(x, HW_IPU_FS_DISP_FLOW2_RD(x) | (v)))
|
|
#define HW_IPU_FS_DISP_FLOW2_CLR(x, v) (HW_IPU_FS_DISP_FLOW2_WR(x, HW_IPU_FS_DISP_FLOW2_RD(x) & ~(v)))
|
|
#define HW_IPU_FS_DISP_FLOW2_TOG(x, v) (HW_IPU_FS_DISP_FLOW2_WR(x, HW_IPU_FS_DISP_FLOW2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_FS_DISP_FLOW2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW2, field DP_ASYNC0_ALT_SRC_SEL[3:0] (RW)
|
|
*
|
|
* Source select for alternate DS2 - MG (graphics) plane (ch29)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL (0) //!< Bit position for IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL (0x0000000f) //!< Bit mask for IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL) >> BP_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL) & BM_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASYNC0_ALT_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW2_WR(x, (HW_IPU_FS_DISP_FLOW2_RD(x) & ~BM_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL) | BF_IPU_FS_DISP_FLOW2_DP_ASYNC0_ALT_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW2, field DP_ASYNC1_ALT_SRC_SEL[7:4] (RW)
|
|
*
|
|
* Source select for alternate DS1/DS2 - Vx (video) plane (ch24)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL (4) //!< Bit position for IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL (0x000000f0) //!< Bit mask for IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL) >> BP_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL) & BM_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASYNC1_ALT_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW2_WR(x, (HW_IPU_FS_DISP_FLOW2_RD(x) & ~BM_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL) | BF_IPU_FS_DISP_FLOW2_DP_ASYNC1_ALT_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_FS_DISP_FLOW2, field DC2_ALT_SRC_SEL[19:16] (RW)
|
|
*
|
|
* Source select for Alternate DS3 (ch41)
|
|
*
|
|
* Values:
|
|
* - 0000 - ARM platform
|
|
* - 0001 - capture0 (smfc0)
|
|
* - 0010 - capture2 (smfc2)
|
|
* - 0011 - IC encoding
|
|
* - 0100 - IC viewfinder
|
|
* - 0101 - IC playback
|
|
* - 0110 - IRT Encoding
|
|
* - 0111 - IRT viewfinder
|
|
* - 1000 - IRT playback
|
|
* - 1001 - Reserved
|
|
* - 1010 - Reserved
|
|
* - 1011 - autoref
|
|
* - 1100 - autoref+snoop1
|
|
* - 1101 - autoref+snoop2
|
|
* - 1110 - snoop1
|
|
* - 1111 - snoop2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL (16) //!< Bit position for IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL.
|
|
#define BM_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL (0x000f0000) //!< Bit mask for IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL.
|
|
|
|
//! @brief Get value of IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL from a register value.
|
|
#define BG_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL) >> BP_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL.
|
|
#define BF_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL) & BM_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC2_ALT_SRC_SEL field to a new value.
|
|
#define BW_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL(x, v) (HW_IPU_FS_DISP_FLOW2_WR(x, (HW_IPU_FS_DISP_FLOW2_RD(x) & ~BM_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL) | BF_IPU_FS_DISP_FLOW2_DC2_ALT_SRC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SKIP - SKIP Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SKIP - SKIP Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register controls the different frame skipping supported by the IPU.
|
|
*/
|
|
typedef union _hw_ipu_skip
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_skip_bitfields
|
|
{
|
|
unsigned CSI_MAX_RATIO_SKIP_IC_ENC : 3; //!< [2:0] CSI Maximum Ratio Skip for IC (encoding task)
|
|
unsigned CSI_SKIP_IC_ENC : 5; //!< [7:3] CSI SKIP IC_ENC
|
|
unsigned CSI_MAX_RATIO_SKIP_IC_VF : 3; //!< [10:8] CSI Maximum Ratio Skip for IC (view finder task)
|
|
unsigned CSI_SKIP_IC_VF : 5; //!< [15:11] CSI SKIP IC_VF
|
|
unsigned VDI_MAX_RATIO_SKIP : 4; //!< [19:16] Maximum Ratio Skip for VDI C
|
|
unsigned VDI_SKIP : 12; //!< [31:20] VDI_SKIP
|
|
} B;
|
|
} hw_ipu_skip_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SKIP register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SKIP_ADDR(x) (REGS_IPU_BASE(x) + 0xbc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SKIP(x) (*(volatile hw_ipu_skip_t *) HW_IPU_SKIP_ADDR(x))
|
|
#define HW_IPU_SKIP_RD(x) (HW_IPU_SKIP(x).U)
|
|
#define HW_IPU_SKIP_WR(x, v) (HW_IPU_SKIP(x).U = (v))
|
|
#define HW_IPU_SKIP_SET(x, v) (HW_IPU_SKIP_WR(x, HW_IPU_SKIP_RD(x) | (v)))
|
|
#define HW_IPU_SKIP_CLR(x, v) (HW_IPU_SKIP_WR(x, HW_IPU_SKIP_RD(x) & ~(v)))
|
|
#define HW_IPU_SKIP_TOG(x, v) (HW_IPU_SKIP_WR(x, HW_IPU_SKIP_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SKIP bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SKIP, field CSI_MAX_RATIO_SKIP_IC_ENC[2:0] (RW)
|
|
*
|
|
* CSI Maximum Ratio Skip for IC (encoding task) These bits define the number of frames in a
|
|
* skipping set. The maximum value of this bits is 4. When set to 0 the skipping is disabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC (0) //!< Bit position for IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC.
|
|
#define BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC (0x00000007) //!< Bit mask for IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC.
|
|
|
|
//! @brief Get value of IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC from a register value.
|
|
#define BG_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC) >> BP_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC)
|
|
|
|
//! @brief Format value for bitfield IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC.
|
|
#define BF_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC) & BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI_MAX_RATIO_SKIP_IC_ENC field to a new value.
|
|
#define BW_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC(x, v) (HW_IPU_SKIP_WR(x, (HW_IPU_SKIP_RD(x) & ~BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC) | BF_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_ENC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SKIP, field CSI_SKIP_IC_ENC[7:3] (RW)
|
|
*
|
|
* CSI SKIP IC_ENC These 5 bits define the skipping pattern of the frames send to the IC for
|
|
* encoding task from one of the CSIs as defined on the CSI_SEL and IC_INPUT bits Skipping is done
|
|
* for a set of frames. The number of frames in a set is defined at CSI_MAX_RATIO_SKIP_IC_ENC. when
|
|
* CSI_MAX_RATIO_SKIP_IC_ENC = 1 => CSI_SKIP_IC_ENC[1:0] are used; other bits are ignored when
|
|
* CSI_MAX_RATIO_SKIP_IC_ENC = 2 => CSI_SKIP_IC_ENC[2:0] are used; other bits are ignored when
|
|
* CSI_MAX_RATIO_SKIP_IC_ENC = 3 => CSI_SKIP_IC_ENC[3:0] are used; other bits are ignored when
|
|
* CSI_MAX_RATIO_SKIP_IC_ENC = 4 => CSI_SKIP_IC_ENC[4:0] are used; Setting bit #n of CSI_SKIP_IC_ENC
|
|
* means that the #n frame in the set is skipped. For example: if CSI_MAX_RATIO_SKIP_IC_ENC = 4 and
|
|
* CSI_SKIP_IC_ENC = 11010 Frames #0 & Frame #2 will not be skipped as bit0 and bit2 are cleared
|
|
* Frames #1 & Frame #3 will be skipped as bit1 and bit3 are set bit #4 is ignored as
|
|
* CSI_MAX_RATIO_SKIP_IC_ENC is set to 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SKIP_CSI_SKIP_IC_ENC (3) //!< Bit position for IPU_SKIP_CSI_SKIP_IC_ENC.
|
|
#define BM_IPU_SKIP_CSI_SKIP_IC_ENC (0x000000f8) //!< Bit mask for IPU_SKIP_CSI_SKIP_IC_ENC.
|
|
|
|
//! @brief Get value of IPU_SKIP_CSI_SKIP_IC_ENC from a register value.
|
|
#define BG_IPU_SKIP_CSI_SKIP_IC_ENC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SKIP_CSI_SKIP_IC_ENC) >> BP_IPU_SKIP_CSI_SKIP_IC_ENC)
|
|
|
|
//! @brief Format value for bitfield IPU_SKIP_CSI_SKIP_IC_ENC.
|
|
#define BF_IPU_SKIP_CSI_SKIP_IC_ENC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SKIP_CSI_SKIP_IC_ENC) & BM_IPU_SKIP_CSI_SKIP_IC_ENC)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI_SKIP_IC_ENC field to a new value.
|
|
#define BW_IPU_SKIP_CSI_SKIP_IC_ENC(x, v) (HW_IPU_SKIP_WR(x, (HW_IPU_SKIP_RD(x) & ~BM_IPU_SKIP_CSI_SKIP_IC_ENC) | BF_IPU_SKIP_CSI_SKIP_IC_ENC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SKIP, field CSI_MAX_RATIO_SKIP_IC_VF[10:8] (RW)
|
|
*
|
|
* CSI Maximum Ratio Skip for IC (view finder task) These bits define the number of frames in a
|
|
* skipping set. The maximum value of this bits is 4. When set to 0 the skipping is disabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF (8) //!< Bit position for IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF.
|
|
#define BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF (0x00000700) //!< Bit mask for IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF.
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|
|
|
//! @brief Get value of IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF from a register value.
|
|
#define BG_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF) >> BP_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF)
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|
|
|
//! @brief Format value for bitfield IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF.
|
|
#define BF_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF) & BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI_MAX_RATIO_SKIP_IC_VF field to a new value.
|
|
#define BW_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF(x, v) (HW_IPU_SKIP_WR(x, (HW_IPU_SKIP_RD(x) & ~BM_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF) | BF_IPU_SKIP_CSI_MAX_RATIO_SKIP_IC_VF(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SKIP, field CSI_SKIP_IC_VF[15:11] (RW)
|
|
*
|
|
* CSI SKIP IC_VF These 5 bits define the skipping pattern of the frames send to the IC for view
|
|
* finder task from one of the CSIs as defined on the CSI_SEL and IC_INPUT bits Skipping is done for
|
|
* a set of frames. The number of frames in a set is defined at CSI_MAX_RATIO_SKIP_IC_VF. when
|
|
* CSI_MAX_RATIO_SKIP_IC_VF = 1 => CSI_SKIP_IC_VF[1:0] are used; other bits are ignored when
|
|
* CSI_MAX_RATIO_SKIP_IC_VF = 2 => CSI_SKIP_IC_VF[2:0] are used; other bits are ignored when
|
|
* CSI_MAX_RATIO_SKIP_IC_VF =3 => CSI_SKIP_IC_VF[3:0] are used; other bits are ignored when
|
|
* CSI_MAX_RATIO_SKIP_IC_VF = 4 => CSI_SKIP_IC_VF[4:0] are used; Setting bit #n of CSI_SKIP_IC_VF
|
|
* means that the #n frame in the set is skipped. For example: if CSI_MAX_RATIO_SKIP_IC_VF = 4 and
|
|
* CSI_SKIP_IC_VF = 11010 Frames #0 & Frame #2 will not be skipped as bit0 and bit2 are cleared
|
|
* Frames #1 & Frame #3 will be skipped as bit1 and bit3 are set bit #4 is ignored as
|
|
* CSI_MAX_RATIO_SKIP_IC_VF is set to 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SKIP_CSI_SKIP_IC_VF (11) //!< Bit position for IPU_SKIP_CSI_SKIP_IC_VF.
|
|
#define BM_IPU_SKIP_CSI_SKIP_IC_VF (0x0000f800) //!< Bit mask for IPU_SKIP_CSI_SKIP_IC_VF.
|
|
|
|
//! @brief Get value of IPU_SKIP_CSI_SKIP_IC_VF from a register value.
|
|
#define BG_IPU_SKIP_CSI_SKIP_IC_VF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SKIP_CSI_SKIP_IC_VF) >> BP_IPU_SKIP_CSI_SKIP_IC_VF)
|
|
|
|
//! @brief Format value for bitfield IPU_SKIP_CSI_SKIP_IC_VF.
|
|
#define BF_IPU_SKIP_CSI_SKIP_IC_VF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SKIP_CSI_SKIP_IC_VF) & BM_IPU_SKIP_CSI_SKIP_IC_VF)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI_SKIP_IC_VF field to a new value.
|
|
#define BW_IPU_SKIP_CSI_SKIP_IC_VF(x, v) (HW_IPU_SKIP_WR(x, (HW_IPU_SKIP_RD(x) & ~BM_IPU_SKIP_CSI_SKIP_IC_VF) | BF_IPU_SKIP_CSI_SKIP_IC_VF(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SKIP, field VDI_MAX_RATIO_SKIP[19:16] (RW)
|
|
*
|
|
* Maximum Ratio Skip for VDI C These bits define the number of frames in a skipping set. The
|
|
* maximum value of this bits is 11. When set to 0 the skipping is disabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SKIP_VDI_MAX_RATIO_SKIP (16) //!< Bit position for IPU_SKIP_VDI_MAX_RATIO_SKIP.
|
|
#define BM_IPU_SKIP_VDI_MAX_RATIO_SKIP (0x000f0000) //!< Bit mask for IPU_SKIP_VDI_MAX_RATIO_SKIP.
|
|
|
|
//! @brief Get value of IPU_SKIP_VDI_MAX_RATIO_SKIP from a register value.
|
|
#define BG_IPU_SKIP_VDI_MAX_RATIO_SKIP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SKIP_VDI_MAX_RATIO_SKIP) >> BP_IPU_SKIP_VDI_MAX_RATIO_SKIP)
|
|
|
|
//! @brief Format value for bitfield IPU_SKIP_VDI_MAX_RATIO_SKIP.
|
|
#define BF_IPU_SKIP_VDI_MAX_RATIO_SKIP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SKIP_VDI_MAX_RATIO_SKIP) & BM_IPU_SKIP_VDI_MAX_RATIO_SKIP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_MAX_RATIO_SKIP field to a new value.
|
|
#define BW_IPU_SKIP_VDI_MAX_RATIO_SKIP(x, v) (HW_IPU_SKIP_WR(x, (HW_IPU_SKIP_RD(x) & ~BM_IPU_SKIP_VDI_MAX_RATIO_SKIP) | BF_IPU_SKIP_VDI_MAX_RATIO_SKIP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SKIP, field VDI_SKIP[31:20] (RW)
|
|
*
|
|
* VDI_SKIP These 12 bits define the skipping pattern of the frames send from the VDI C . The VDI C
|
|
* avoids reading fields from the memory if the output frame is skipped. Skipping is relevant only
|
|
* if the source to the VDI C is coming from the CSI. Skipping is done for a set of frames. The
|
|
* number of frames in a set is defined at VDI_MAX_RATIO_SKIP. when VDI_MAX_RATIO_SKIP = 1 =>
|
|
* VDI_SKIP[1:0] is used; other bits are ignored when VDI_MAX_RATIO_SKIP = 2 => VDI_SKIP[2:0] are
|
|
* used; other bits are ignored .. .. when VDI_MAX_RATIO_SKIP = 11 => VDI_SKIP[11:0] are used;
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SKIP_VDI_SKIP (20) //!< Bit position for IPU_SKIP_VDI_SKIP.
|
|
#define BM_IPU_SKIP_VDI_SKIP (0xfff00000) //!< Bit mask for IPU_SKIP_VDI_SKIP.
|
|
|
|
//! @brief Get value of IPU_SKIP_VDI_SKIP from a register value.
|
|
#define BG_IPU_SKIP_VDI_SKIP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SKIP_VDI_SKIP) >> BP_IPU_SKIP_VDI_SKIP)
|
|
|
|
//! @brief Format value for bitfield IPU_SKIP_VDI_SKIP.
|
|
#define BF_IPU_SKIP_VDI_SKIP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SKIP_VDI_SKIP) & BM_IPU_SKIP_VDI_SKIP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_SKIP field to a new value.
|
|
#define BW_IPU_SKIP_VDI_SKIP(x, v) (HW_IPU_SKIP_WR(x, (HW_IPU_SKIP_RD(x) & ~BM_IPU_SKIP_VDI_SKIP) | BF_IPU_SKIP_VDI_SKIP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_ALT_CONF - Display Alternate Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_ALT_CONF - Display Alternate Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register controls various parameters that are used for alternate flows related to the
|
|
* display modules.
|
|
*/
|
|
typedef union _hw_ipu_disp_alt_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_alt_conf_bitfields
|
|
{
|
|
unsigned RESERVED0 : 32; //!< [31:0] Reserved
|
|
} B;
|
|
} hw_ipu_disp_alt_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_ALT_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_ALT_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0xc0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_ALT_CONF(x) (*(volatile hw_ipu_disp_alt_conf_t *) HW_IPU_DISP_ALT_CONF_ADDR(x))
|
|
#define HW_IPU_DISP_ALT_CONF_RD(x) (HW_IPU_DISP_ALT_CONF(x).U)
|
|
#define HW_IPU_DISP_ALT_CONF_WR(x, v) (HW_IPU_DISP_ALT_CONF(x).U = (v))
|
|
#define HW_IPU_DISP_ALT_CONF_SET(x, v) (HW_IPU_DISP_ALT_CONF_WR(x, HW_IPU_DISP_ALT_CONF_RD(x) | (v)))
|
|
#define HW_IPU_DISP_ALT_CONF_CLR(x, v) (HW_IPU_DISP_ALT_CONF_WR(x, HW_IPU_DISP_ALT_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_DISP_ALT_CONF_TOG(x, v) (HW_IPU_DISP_ALT_CONF_WR(x, HW_IPU_DISP_ALT_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_ALT_CONF bitfields
|
|
*/
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_GEN - Display General Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_GEN - Display General Control Register (RW)
|
|
*
|
|
* Reset value: 0x00400000
|
|
*
|
|
* This register controls various aspects of the display port.
|
|
*/
|
|
typedef union _hw_ipu_disp_gen
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_gen_bitfields
|
|
{
|
|
unsigned DI0_DUAL_MODE : 1; //!< [0] DI0 dual mode control
|
|
unsigned DI1_DUAL_MODE : 1; //!< [1] DI1 dual mode control
|
|
unsigned DC2_DOUBLE_FLOW : 1; //!< [2] DC2 Double Flow.
|
|
unsigned DP_ASYNC_DOUBLE_FLOW : 1; //!< [3] DP Async Double Flow.
|
|
unsigned DP_FG_EN_ASYNC0 : 1; //!< [4] FG_EN - partial plane Enable for async flow 0.
|
|
unsigned DP_FG_EN_ASYNC1 : 1; //!< [5] FG_EN - partial plane Enable for async flow 1.
|
|
unsigned DP_PIPE_CLR : 1; //!< [6] DP Pipe Clear
|
|
unsigned RESERVED0 : 9; //!< [15:7] Reserved
|
|
unsigned MCU_DI_ID_8 : 1; //!< [16] MCU_DI_ID_8 - DI ID via DC channel 8.
|
|
unsigned MCU_DI_ID_9 : 1; //!< [17] MCU_DI_ID_9 - DI ID via DC channel 9.
|
|
unsigned MCU_T : 4; //!< [21:18] The address space for accesses through the AHB-lite slave port is MB and it is split internally (with 32MB resolution) according to bits [28:25] of the address.
|
|
unsigned MCU_MAX_BURST_STOP : 1; //!< [22] ARM platform Maximal burst
|
|
unsigned CSI_VSYNC_DEST : 1; //!< [23] CSI_VSYNC destination
|
|
unsigned DI0_COUNTER_RELEASE : 1; //!< [24] DI1 Counter release
|
|
unsigned DI1_COUNTER_RELEASE : 1; //!< [25] DI1 Counter release
|
|
unsigned RESERVED1 : 6; //!< [31:26] Reserved
|
|
} B;
|
|
} hw_ipu_disp_gen_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_GEN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_GEN_ADDR(x) (REGS_IPU_BASE(x) + 0xc4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_GEN(x) (*(volatile hw_ipu_disp_gen_t *) HW_IPU_DISP_GEN_ADDR(x))
|
|
#define HW_IPU_DISP_GEN_RD(x) (HW_IPU_DISP_GEN(x).U)
|
|
#define HW_IPU_DISP_GEN_WR(x, v) (HW_IPU_DISP_GEN(x).U = (v))
|
|
#define HW_IPU_DISP_GEN_SET(x, v) (HW_IPU_DISP_GEN_WR(x, HW_IPU_DISP_GEN_RD(x) | (v)))
|
|
#define HW_IPU_DISP_GEN_CLR(x, v) (HW_IPU_DISP_GEN_WR(x, HW_IPU_DISP_GEN_RD(x) & ~(v)))
|
|
#define HW_IPU_DISP_GEN_TOG(x, v) (HW_IPU_DISP_GEN_WR(x, HW_IPU_DISP_GEN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_GEN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DISP_GEN, field DI0_DUAL_MODE[0] (RW)
|
|
*
|
|
* DI0 dual mode control
|
|
*
|
|
* Values:
|
|
* - 0 - DI0 is not in dual mode
|
|
* - 1 - DI0 operates in dual mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DI0_DUAL_MODE (0) //!< Bit position for IPU_DISP_GEN_DI0_DUAL_MODE.
|
|
#define BM_IPU_DISP_GEN_DI0_DUAL_MODE (0x00000001) //!< Bit mask for IPU_DISP_GEN_DI0_DUAL_MODE.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_DI0_DUAL_MODE from a register value.
|
|
#define BG_IPU_DISP_GEN_DI0_DUAL_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DI0_DUAL_MODE) >> BP_IPU_DISP_GEN_DI0_DUAL_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_DI0_DUAL_MODE.
|
|
#define BF_IPU_DISP_GEN_DI0_DUAL_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DI0_DUAL_MODE) & BM_IPU_DISP_GEN_DI0_DUAL_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DUAL_MODE field to a new value.
|
|
#define BW_IPU_DISP_GEN_DI0_DUAL_MODE(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DI0_DUAL_MODE) | BF_IPU_DISP_GEN_DI0_DUAL_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field DI1_DUAL_MODE[1] (RW)
|
|
*
|
|
* DI1 dual mode control
|
|
*
|
|
* Values:
|
|
* - 0 - DI1 is not in dual mode
|
|
* - 1 - DI1 operates in dual mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DI1_DUAL_MODE (1) //!< Bit position for IPU_DISP_GEN_DI1_DUAL_MODE.
|
|
#define BM_IPU_DISP_GEN_DI1_DUAL_MODE (0x00000002) //!< Bit mask for IPU_DISP_GEN_DI1_DUAL_MODE.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_DI1_DUAL_MODE from a register value.
|
|
#define BG_IPU_DISP_GEN_DI1_DUAL_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DI1_DUAL_MODE) >> BP_IPU_DISP_GEN_DI1_DUAL_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_DI1_DUAL_MODE.
|
|
#define BF_IPU_DISP_GEN_DI1_DUAL_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DI1_DUAL_MODE) & BM_IPU_DISP_GEN_DI1_DUAL_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DUAL_MODE field to a new value.
|
|
#define BW_IPU_DISP_GEN_DI1_DUAL_MODE(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DI1_DUAL_MODE) | BF_IPU_DISP_GEN_DI1_DUAL_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field DC2_DOUBLE_FLOW[2] (RW)
|
|
*
|
|
* DC2 Double Flow. This bit define how many flows are currently handles via DC2 channel (ch41)
|
|
*
|
|
* Values:
|
|
* - 0 - single flow is handled via DC2
|
|
* - 1 - 2 flows are handled via DC2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DC2_DOUBLE_FLOW (2) //!< Bit position for IPU_DISP_GEN_DC2_DOUBLE_FLOW.
|
|
#define BM_IPU_DISP_GEN_DC2_DOUBLE_FLOW (0x00000004) //!< Bit mask for IPU_DISP_GEN_DC2_DOUBLE_FLOW.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_DC2_DOUBLE_FLOW from a register value.
|
|
#define BG_IPU_DISP_GEN_DC2_DOUBLE_FLOW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DC2_DOUBLE_FLOW) >> BP_IPU_DISP_GEN_DC2_DOUBLE_FLOW)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_DC2_DOUBLE_FLOW.
|
|
#define BF_IPU_DISP_GEN_DC2_DOUBLE_FLOW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DC2_DOUBLE_FLOW) & BM_IPU_DISP_GEN_DC2_DOUBLE_FLOW)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC2_DOUBLE_FLOW field to a new value.
|
|
#define BW_IPU_DISP_GEN_DC2_DOUBLE_FLOW(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DC2_DOUBLE_FLOW) | BF_IPU_DISP_GEN_DC2_DOUBLE_FLOW(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field DP_ASYNC_DOUBLE_FLOW[3] (RW)
|
|
*
|
|
* DP Async Double Flow. This bit define how many async flows are currently handles via DP channel
|
|
* (ch24+29)
|
|
*
|
|
* Values:
|
|
* - 0 - single flow is handled via DP
|
|
* - 1 - 2 flows are handled via DP
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW (3) //!< Bit position for IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW.
|
|
#define BM_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW (0x00000008) //!< Bit mask for IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW.
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|
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//! @brief Get value of IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW from a register value.
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|
#define BG_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW) >> BP_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW)
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//! @brief Format value for bitfield IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW.
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|
#define BF_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW) & BM_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASYNC_DOUBLE_FLOW field to a new value.
|
|
#define BW_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW) | BF_IPU_DISP_GEN_DP_ASYNC_DOUBLE_FLOW(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_DISP_GEN, field DP_FG_EN_ASYNC0[4] (RW)
|
|
*
|
|
* FG_EN - partial plane Enable for async flow 0. This bit enables the partial plane channel.
|
|
*
|
|
* Values:
|
|
* - 0 - partial plane channel is disabled.
|
|
* - 1 - partial plane channel is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DP_FG_EN_ASYNC0 (4) //!< Bit position for IPU_DISP_GEN_DP_FG_EN_ASYNC0.
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#define BM_IPU_DISP_GEN_DP_FG_EN_ASYNC0 (0x00000010) //!< Bit mask for IPU_DISP_GEN_DP_FG_EN_ASYNC0.
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//! @brief Get value of IPU_DISP_GEN_DP_FG_EN_ASYNC0 from a register value.
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|
#define BG_IPU_DISP_GEN_DP_FG_EN_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DP_FG_EN_ASYNC0) >> BP_IPU_DISP_GEN_DP_FG_EN_ASYNC0)
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//! @brief Format value for bitfield IPU_DISP_GEN_DP_FG_EN_ASYNC0.
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|
#define BF_IPU_DISP_GEN_DP_FG_EN_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DP_FG_EN_ASYNC0) & BM_IPU_DISP_GEN_DP_FG_EN_ASYNC0)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FG_EN_ASYNC0 field to a new value.
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|
#define BW_IPU_DISP_GEN_DP_FG_EN_ASYNC0(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DP_FG_EN_ASYNC0) | BF_IPU_DISP_GEN_DP_FG_EN_ASYNC0(v)))
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#endif
|
|
//@}
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/*! @name Register IPU_DISP_GEN, field DP_FG_EN_ASYNC1[5] (RW)
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|
*
|
|
* FG_EN - partial plane Enable for async flow 1. This bit enables the partial plane channel.
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|
*
|
|
* Values:
|
|
* - 0 - partial plane channel is disabled.
|
|
* - 1 - partial plane channel is enabled.
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|
*/
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|
//@{
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|
#define BP_IPU_DISP_GEN_DP_FG_EN_ASYNC1 (5) //!< Bit position for IPU_DISP_GEN_DP_FG_EN_ASYNC1.
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#define BM_IPU_DISP_GEN_DP_FG_EN_ASYNC1 (0x00000020) //!< Bit mask for IPU_DISP_GEN_DP_FG_EN_ASYNC1.
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//! @brief Get value of IPU_DISP_GEN_DP_FG_EN_ASYNC1 from a register value.
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|
#define BG_IPU_DISP_GEN_DP_FG_EN_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DP_FG_EN_ASYNC1) >> BP_IPU_DISP_GEN_DP_FG_EN_ASYNC1)
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//! @brief Format value for bitfield IPU_DISP_GEN_DP_FG_EN_ASYNC1.
|
|
#define BF_IPU_DISP_GEN_DP_FG_EN_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DP_FG_EN_ASYNC1) & BM_IPU_DISP_GEN_DP_FG_EN_ASYNC1)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FG_EN_ASYNC1 field to a new value.
|
|
#define BW_IPU_DISP_GEN_DP_FG_EN_ASYNC1(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DP_FG_EN_ASYNC1) | BF_IPU_DISP_GEN_DP_FG_EN_ASYNC1(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DISP_GEN, field DP_PIPE_CLR[6] (WORZ)
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|
*
|
|
* DP Pipe Clear This bit clears the internal pipe of the DP. The user may use this bit in case of
|
|
* an error condition This is a self clear bit
|
|
*
|
|
* Values:
|
|
* - 0 - Idle - does nothing
|
|
* - 1 - Clear the internal pipe of the DP
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DP_PIPE_CLR (6) //!< Bit position for IPU_DISP_GEN_DP_PIPE_CLR.
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|
#define BM_IPU_DISP_GEN_DP_PIPE_CLR (0x00000040) //!< Bit mask for IPU_DISP_GEN_DP_PIPE_CLR.
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|
//! @brief Get value of IPU_DISP_GEN_DP_PIPE_CLR from a register value.
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|
#define BG_IPU_DISP_GEN_DP_PIPE_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DP_PIPE_CLR) >> BP_IPU_DISP_GEN_DP_PIPE_CLR)
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|
//! @brief Format value for bitfield IPU_DISP_GEN_DP_PIPE_CLR.
|
|
#define BF_IPU_DISP_GEN_DP_PIPE_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DP_PIPE_CLR) & BM_IPU_DISP_GEN_DP_PIPE_CLR)
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|
//@}
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|
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/*! @name Register IPU_DISP_GEN, field MCU_DI_ID_8[16] (RW)
|
|
*
|
|
* MCU_DI_ID_8 - DI ID via DC channel 8. This bit defines the DI that the ARM platform DC's access
|
|
* via channel #8
|
|
*
|
|
* Values:
|
|
* - 0 - ARM platform accesses DC's channel #8 via DI0.
|
|
* - 1 - ARM platform accesses DC's channel #8 via DI1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_MCU_DI_ID_8 (16) //!< Bit position for IPU_DISP_GEN_MCU_DI_ID_8.
|
|
#define BM_IPU_DISP_GEN_MCU_DI_ID_8 (0x00010000) //!< Bit mask for IPU_DISP_GEN_MCU_DI_ID_8.
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|
|
|
//! @brief Get value of IPU_DISP_GEN_MCU_DI_ID_8 from a register value.
|
|
#define BG_IPU_DISP_GEN_MCU_DI_ID_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_MCU_DI_ID_8) >> BP_IPU_DISP_GEN_MCU_DI_ID_8)
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|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_MCU_DI_ID_8.
|
|
#define BF_IPU_DISP_GEN_MCU_DI_ID_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_MCU_DI_ID_8) & BM_IPU_DISP_GEN_MCU_DI_ID_8)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_DI_ID_8 field to a new value.
|
|
#define BW_IPU_DISP_GEN_MCU_DI_ID_8(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_MCU_DI_ID_8) | BF_IPU_DISP_GEN_MCU_DI_ID_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field MCU_DI_ID_9[17] (RW)
|
|
*
|
|
* MCU_DI_ID_9 - DI ID via DC channel 9. This bit defines the DI that the ARM platform DC's access
|
|
* via channel #9
|
|
*
|
|
* Values:
|
|
* - 0 - ARM platform accesses DC's channel #9 via DI0.
|
|
* - 1 - ARM platform accesses DC's channel #9 via DI1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_MCU_DI_ID_9 (17) //!< Bit position for IPU_DISP_GEN_MCU_DI_ID_9.
|
|
#define BM_IPU_DISP_GEN_MCU_DI_ID_9 (0x00020000) //!< Bit mask for IPU_DISP_GEN_MCU_DI_ID_9.
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|
|
|
//! @brief Get value of IPU_DISP_GEN_MCU_DI_ID_9 from a register value.
|
|
#define BG_IPU_DISP_GEN_MCU_DI_ID_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_MCU_DI_ID_9) >> BP_IPU_DISP_GEN_MCU_DI_ID_9)
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|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_MCU_DI_ID_9.
|
|
#define BF_IPU_DISP_GEN_MCU_DI_ID_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_MCU_DI_ID_9) & BM_IPU_DISP_GEN_MCU_DI_ID_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_DI_ID_9 field to a new value.
|
|
#define BW_IPU_DISP_GEN_MCU_DI_ID_9(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_MCU_DI_ID_9) | BF_IPU_DISP_GEN_MCU_DI_ID_9(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field MCU_T[21:18] (RW)
|
|
*
|
|
* The address space for accesses through the AHB-lite slave port is MB and it is split internally
|
|
* (with 32MB resolution) according to bits [28:25] of the address. Using the following notation:
|
|
* Address = (ID[31:29], MSB[28:25], LSB[24:0]) The address is used as follows ("T" is a
|
|
* configurable integer between 0 and 13): MSB<T: access to an external device, with address = (MSB,
|
|
* LSB) T<=MSB<14: access to an external device, with address (MSB-T, LSB)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_MCU_T (18) //!< Bit position for IPU_DISP_GEN_MCU_T.
|
|
#define BM_IPU_DISP_GEN_MCU_T (0x003c0000) //!< Bit mask for IPU_DISP_GEN_MCU_T.
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|
|
|
//! @brief Get value of IPU_DISP_GEN_MCU_T from a register value.
|
|
#define BG_IPU_DISP_GEN_MCU_T(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_MCU_T) >> BP_IPU_DISP_GEN_MCU_T)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_MCU_T.
|
|
#define BF_IPU_DISP_GEN_MCU_T(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_MCU_T) & BM_IPU_DISP_GEN_MCU_T)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_T field to a new value.
|
|
#define BW_IPU_DISP_GEN_MCU_T(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_MCU_T) | BF_IPU_DISP_GEN_MCU_T(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field MCU_MAX_BURST_STOP[22] (RW)
|
|
*
|
|
* ARM platform Maximal burst This bit limit the maximal unspecified length burst.
|
|
*
|
|
* Values:
|
|
* - 0 - The unspecified burst length is unlimited
|
|
* - 1 - The maximum unspecified burst length is 8-beat
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_MCU_MAX_BURST_STOP (22) //!< Bit position for IPU_DISP_GEN_MCU_MAX_BURST_STOP.
|
|
#define BM_IPU_DISP_GEN_MCU_MAX_BURST_STOP (0x00400000) //!< Bit mask for IPU_DISP_GEN_MCU_MAX_BURST_STOP.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_MCU_MAX_BURST_STOP from a register value.
|
|
#define BG_IPU_DISP_GEN_MCU_MAX_BURST_STOP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_MCU_MAX_BURST_STOP) >> BP_IPU_DISP_GEN_MCU_MAX_BURST_STOP)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_MCU_MAX_BURST_STOP.
|
|
#define BF_IPU_DISP_GEN_MCU_MAX_BURST_STOP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_MCU_MAX_BURST_STOP) & BM_IPU_DISP_GEN_MCU_MAX_BURST_STOP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_MAX_BURST_STOP field to a new value.
|
|
#define BW_IPU_DISP_GEN_MCU_MAX_BURST_STOP(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_MCU_MAX_BURST_STOP) | BF_IPU_DISP_GEN_MCU_MAX_BURST_STOP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field CSI_VSYNC_DEST[23] (RW)
|
|
*
|
|
* CSI_VSYNC destination This bit defines the destination of the VSYNC coming from the CSI's
|
|
*
|
|
* Values:
|
|
* - 0 - csi0_vsync is connected to DI0; csi1_vsync is connected to DI1
|
|
* - 1 - csi1_vsync is connected to DI0; csi0_vsync is connected to DI1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_CSI_VSYNC_DEST (23) //!< Bit position for IPU_DISP_GEN_CSI_VSYNC_DEST.
|
|
#define BM_IPU_DISP_GEN_CSI_VSYNC_DEST (0x00800000) //!< Bit mask for IPU_DISP_GEN_CSI_VSYNC_DEST.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_CSI_VSYNC_DEST from a register value.
|
|
#define BG_IPU_DISP_GEN_CSI_VSYNC_DEST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_CSI_VSYNC_DEST) >> BP_IPU_DISP_GEN_CSI_VSYNC_DEST)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_CSI_VSYNC_DEST.
|
|
#define BF_IPU_DISP_GEN_CSI_VSYNC_DEST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_CSI_VSYNC_DEST) & BM_IPU_DISP_GEN_CSI_VSYNC_DEST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI_VSYNC_DEST field to a new value.
|
|
#define BW_IPU_DISP_GEN_CSI_VSYNC_DEST(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_CSI_VSYNC_DEST) | BF_IPU_DISP_GEN_CSI_VSYNC_DEST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field DI0_COUNTER_RELEASE[24] (RW)
|
|
*
|
|
* DI1 Counter release By default the DI0 counters responsible for waveform generation for sync flow
|
|
* are frozen. For the first attempt to use the DI in sync flow the user should set this bit
|
|
*
|
|
* Values:
|
|
* - 0 - counter is cleared and stopped
|
|
* - 1 - counter is released and running
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DI0_COUNTER_RELEASE (24) //!< Bit position for IPU_DISP_GEN_DI0_COUNTER_RELEASE.
|
|
#define BM_IPU_DISP_GEN_DI0_COUNTER_RELEASE (0x01000000) //!< Bit mask for IPU_DISP_GEN_DI0_COUNTER_RELEASE.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_DI0_COUNTER_RELEASE from a register value.
|
|
#define BG_IPU_DISP_GEN_DI0_COUNTER_RELEASE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DI0_COUNTER_RELEASE) >> BP_IPU_DISP_GEN_DI0_COUNTER_RELEASE)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_DI0_COUNTER_RELEASE.
|
|
#define BF_IPU_DISP_GEN_DI0_COUNTER_RELEASE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DI0_COUNTER_RELEASE) & BM_IPU_DISP_GEN_DI0_COUNTER_RELEASE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_COUNTER_RELEASE field to a new value.
|
|
#define BW_IPU_DISP_GEN_DI0_COUNTER_RELEASE(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DI0_COUNTER_RELEASE) | BF_IPU_DISP_GEN_DI0_COUNTER_RELEASE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_GEN, field DI1_COUNTER_RELEASE[25] (RW)
|
|
*
|
|
* DI1 Counter release By default the DI0 counters responsible for waveform generation for sync flow
|
|
* are frozen. For the first attempt to use the DI in sync flow the user should set this bit
|
|
*
|
|
* Values:
|
|
* - 0 - counter is cleared and stopped
|
|
* - 1 - counter is released and running
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_GEN_DI1_COUNTER_RELEASE (25) //!< Bit position for IPU_DISP_GEN_DI1_COUNTER_RELEASE.
|
|
#define BM_IPU_DISP_GEN_DI1_COUNTER_RELEASE (0x02000000) //!< Bit mask for IPU_DISP_GEN_DI1_COUNTER_RELEASE.
|
|
|
|
//! @brief Get value of IPU_DISP_GEN_DI1_COUNTER_RELEASE from a register value.
|
|
#define BG_IPU_DISP_GEN_DI1_COUNTER_RELEASE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_GEN_DI1_COUNTER_RELEASE) >> BP_IPU_DISP_GEN_DI1_COUNTER_RELEASE)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_GEN_DI1_COUNTER_RELEASE.
|
|
#define BF_IPU_DISP_GEN_DI1_COUNTER_RELEASE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_GEN_DI1_COUNTER_RELEASE) & BM_IPU_DISP_GEN_DI1_COUNTER_RELEASE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_COUNTER_RELEASE field to a new value.
|
|
#define BW_IPU_DISP_GEN_DI1_COUNTER_RELEASE(x, v) (HW_IPU_DISP_GEN_WR(x, (HW_IPU_DISP_GEN_RD(x) & ~BM_IPU_DISP_GEN_DI1_COUNTER_RELEASE) | BF_IPU_DISP_GEN_DI1_COUNTER_RELEASE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_ALT1 - Display Alternate Flow Control Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_ALT1 - Display Alternate Flow Control Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00400000
|
|
*
|
|
* This register controls various aspects of the display port.
|
|
*/
|
|
typedef union _hw_ipu_disp_alt1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_alt1_bitfields
|
|
{
|
|
unsigned RUN_VALUE_M1_ALT_0 : 12; //!< [11:0] Counter pre defined value
|
|
unsigned CNT_CLR_SEL_ALT_0 : 3; //!< [14:12] Counter Clear select
|
|
unsigned CNT_AUTO_RELOAD_ALT_0 : 1; //!< [15] Counter auto reload mode
|
|
unsigned STEP_REPEAT_ALT_0 : 12; //!< [27:16] This fields defines the amount of repetitions that will be performed by the counter
|
|
unsigned SEL_ALT_0 : 4; //!< [31:28] Select alternative parameters instead of DI Sync Wave Gen counter#.
|
|
} B;
|
|
} hw_ipu_disp_alt1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_ALT1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_ALT1_ADDR(x) (REGS_IPU_BASE(x) + 0xc8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_ALT1(x) (*(volatile hw_ipu_disp_alt1_t *) HW_IPU_DISP_ALT1_ADDR(x))
|
|
#define HW_IPU_DISP_ALT1_RD(x) (HW_IPU_DISP_ALT1(x).U)
|
|
#define HW_IPU_DISP_ALT1_WR(x, v) (HW_IPU_DISP_ALT1(x).U = (v))
|
|
#define HW_IPU_DISP_ALT1_SET(x, v) (HW_IPU_DISP_ALT1_WR(x, HW_IPU_DISP_ALT1_RD(x) | (v)))
|
|
#define HW_IPU_DISP_ALT1_CLR(x, v) (HW_IPU_DISP_ALT1_WR(x, HW_IPU_DISP_ALT1_RD(x) & ~(v)))
|
|
#define HW_IPU_DISP_ALT1_TOG(x, v) (HW_IPU_DISP_ALT1_WR(x, HW_IPU_DISP_ALT1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_ALT1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DISP_ALT1, field RUN_VALUE_M1_ALT_0[11:0] (RW)
|
|
*
|
|
* Counter pre defined value This fields defines the counter pre defines value. real value- 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0 (0) //!< Bit position for IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0.
|
|
#define BM_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0 (0x00000fff) //!< Bit mask for IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0) >> BP_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0.
|
|
#define BF_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0) & BM_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RUN_VALUE_M1_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0(x, v) (HW_IPU_DISP_ALT1_WR(x, (HW_IPU_DISP_ALT1_RD(x) & ~BM_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0) | BF_IPU_DISP_ALT1_RUN_VALUE_M1_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT1, field CNT_CLR_SEL_ALT_0[14:12] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0 (12) //!< Bit position for IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0.
|
|
#define BM_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0 (0x00007000) //!< Bit mask for IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0) >> BP_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0.
|
|
#define BF_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0) & BM_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CNT_CLR_SEL_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0(x, v) (HW_IPU_DISP_ALT1_WR(x, (HW_IPU_DISP_ALT1_RD(x) & ~BM_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0) | BF_IPU_DISP_ALT1_CNT_CLR_SEL_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT1, field CNT_AUTO_RELOAD_ALT_0[15] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the step_repeat_alt_0 field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the step_repeat_alt_0
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0 (15) //!< Bit position for IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0.
|
|
#define BM_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0 (0x00008000) //!< Bit mask for IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0) >> BP_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0.
|
|
#define BF_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0) & BM_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CNT_AUTO_RELOAD_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0(x, v) (HW_IPU_DISP_ALT1_WR(x, (HW_IPU_DISP_ALT1_RD(x) & ~BM_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0) | BF_IPU_DISP_ALT1_CNT_AUTO_RELOAD_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT1, field STEP_REPEAT_ALT_0[27:16] (RW)
|
|
*
|
|
* This fields defines the amount of repetitions that will be performed by the counter
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT1_STEP_REPEAT_ALT_0 (16) //!< Bit position for IPU_DISP_ALT1_STEP_REPEAT_ALT_0.
|
|
#define BM_IPU_DISP_ALT1_STEP_REPEAT_ALT_0 (0x0fff0000) //!< Bit mask for IPU_DISP_ALT1_STEP_REPEAT_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT1_STEP_REPEAT_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT1_STEP_REPEAT_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT1_STEP_REPEAT_ALT_0) >> BP_IPU_DISP_ALT1_STEP_REPEAT_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT1_STEP_REPEAT_ALT_0.
|
|
#define BF_IPU_DISP_ALT1_STEP_REPEAT_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT1_STEP_REPEAT_ALT_0) & BM_IPU_DISP_ALT1_STEP_REPEAT_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_REPEAT_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT1_STEP_REPEAT_ALT_0(x, v) (HW_IPU_DISP_ALT1_WR(x, (HW_IPU_DISP_ALT1_RD(x) & ~BM_IPU_DISP_ALT1_STEP_REPEAT_ALT_0) | BF_IPU_DISP_ALT1_STEP_REPEAT_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT1, field SEL_ALT_0[31:28] (RW)
|
|
*
|
|
* Select alternative parameters instead of DI Sync Wave Gen counter#. The DI is selected according
|
|
* to DP's synchronous channel destination 0000-disable
|
|
*
|
|
* Values:
|
|
* - 0001 - instead of counter 1
|
|
* - 0010 - instead of counter 2
|
|
* - 1000 - instead of counter 8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT1_SEL_ALT_0 (28) //!< Bit position for IPU_DISP_ALT1_SEL_ALT_0.
|
|
#define BM_IPU_DISP_ALT1_SEL_ALT_0 (0xf0000000) //!< Bit mask for IPU_DISP_ALT1_SEL_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT1_SEL_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT1_SEL_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT1_SEL_ALT_0) >> BP_IPU_DISP_ALT1_SEL_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT1_SEL_ALT_0.
|
|
#define BF_IPU_DISP_ALT1_SEL_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT1_SEL_ALT_0) & BM_IPU_DISP_ALT1_SEL_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SEL_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT1_SEL_ALT_0(x, v) (HW_IPU_DISP_ALT1_WR(x, (HW_IPU_DISP_ALT1_RD(x) & ~BM_IPU_DISP_ALT1_SEL_ALT_0) | BF_IPU_DISP_ALT1_SEL_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_ALT2 - Display Alternate Flow Control Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_ALT2 - Display Alternate Flow Control Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register controls various aspects of the display port.
|
|
*/
|
|
typedef union _hw_ipu_disp_alt2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_alt2_bitfields
|
|
{
|
|
unsigned OFFSET_VALUE_ALT_0 : 12; //!< [11:0] Counter offset value
|
|
unsigned OFFSET_RESOLUTION_ALT_0 : 3; //!< [14:12] Counter offset Resolution
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned RUN_RESOLUTION_ALT_0 : 3; //!< [18:16] Counter Run Resolution
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved
|
|
} B;
|
|
} hw_ipu_disp_alt2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_ALT2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_ALT2_ADDR(x) (REGS_IPU_BASE(x) + 0xcc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_ALT2(x) (*(volatile hw_ipu_disp_alt2_t *) HW_IPU_DISP_ALT2_ADDR(x))
|
|
#define HW_IPU_DISP_ALT2_RD(x) (HW_IPU_DISP_ALT2(x).U)
|
|
#define HW_IPU_DISP_ALT2_WR(x, v) (HW_IPU_DISP_ALT2(x).U = (v))
|
|
#define HW_IPU_DISP_ALT2_SET(x, v) (HW_IPU_DISP_ALT2_WR(x, HW_IPU_DISP_ALT2_RD(x) | (v)))
|
|
#define HW_IPU_DISP_ALT2_CLR(x, v) (HW_IPU_DISP_ALT2_WR(x, HW_IPU_DISP_ALT2_RD(x) & ~(v)))
|
|
#define HW_IPU_DISP_ALT2_TOG(x, v) (HW_IPU_DISP_ALT2_WR(x, HW_IPU_DISP_ALT2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_ALT2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DISP_ALT2, field OFFSET_VALUE_ALT_0[11:0] (RW)
|
|
*
|
|
* Counter offset value The counter can start counting after a pre defined delay This field defines
|
|
* the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0 (0) //!< Bit position for IPU_DISP_ALT2_OFFSET_VALUE_ALT_0.
|
|
#define BM_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0 (0x00000fff) //!< Bit mask for IPU_DISP_ALT2_OFFSET_VALUE_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT2_OFFSET_VALUE_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0) >> BP_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT2_OFFSET_VALUE_ALT_0.
|
|
#define BF_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0) & BM_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_VALUE_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0(x, v) (HW_IPU_DISP_ALT2_WR(x, (HW_IPU_DISP_ALT2_RD(x) & ~BM_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0) | BF_IPU_DISP_ALT2_OFFSET_VALUE_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT2, field OFFSET_RESOLUTION_ALT_0[14:12] (RW)
|
|
*
|
|
* Counter offset Resolution This field defines the trigger causing the offset counter to increment
|
|
* The counter offset resolution should be defined in the same way as in original DI's counter#
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0 (12) //!< Bit position for IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0.
|
|
#define BM_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0 (0x00007000) //!< Bit mask for IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0) >> BP_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0.
|
|
#define BF_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0) & BM_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_RESOLUTION_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0(x, v) (HW_IPU_DISP_ALT2_WR(x, (HW_IPU_DISP_ALT2_RD(x) & ~BM_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0) | BF_IPU_DISP_ALT2_OFFSET_RESOLUTION_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT2, field RUN_RESOLUTION_ALT_0[18:16] (RW)
|
|
*
|
|
* Counter Run Resolution This field defines the trigger causing the counter to increment. The
|
|
* counter run resolution should be defined in the same way as in original DI's counter#
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0 (16) //!< Bit position for IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0.
|
|
#define BM_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0 (0x00070000) //!< Bit mask for IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0 from a register value.
|
|
#define BG_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0) >> BP_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0.
|
|
#define BF_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0) & BM_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RUN_RESOLUTION_ALT_0 field to a new value.
|
|
#define BW_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0(x, v) (HW_IPU_DISP_ALT2_WR(x, (HW_IPU_DISP_ALT2_RD(x) & ~BM_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0) | BF_IPU_DISP_ALT2_RUN_RESOLUTION_ALT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_ALT3 - Display Alternate Flow Control Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_ALT3 - Display Alternate Flow Control Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00400000
|
|
*
|
|
* This register controls various aspects of the display port.
|
|
*/
|
|
typedef union _hw_ipu_disp_alt3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_alt3_bitfields
|
|
{
|
|
unsigned RUN_VALUE_M1_ALT_1 : 12; //!< [11:0] Counter pre defined value
|
|
unsigned CNT_CLR_SEL_ALT_1 : 3; //!< [14:12] Counter Clear select
|
|
unsigned CNT_AUTO_RELOAD_ALT_1 : 1; //!< [15] Counter auto reload mode
|
|
unsigned STEP_REPEAT_ALT_1 : 12; //!< [27:16] This fields defines the amount of repetitions that will be performed by the counter
|
|
unsigned SEL_ALT_1 : 4; //!< [31:28] Select alternative parameters instead of DI Sync Wave Gen counter#.
|
|
} B;
|
|
} hw_ipu_disp_alt3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_ALT3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_ALT3_ADDR(x) (REGS_IPU_BASE(x) + 0xd0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_ALT3(x) (*(volatile hw_ipu_disp_alt3_t *) HW_IPU_DISP_ALT3_ADDR(x))
|
|
#define HW_IPU_DISP_ALT3_RD(x) (HW_IPU_DISP_ALT3(x).U)
|
|
#define HW_IPU_DISP_ALT3_WR(x, v) (HW_IPU_DISP_ALT3(x).U = (v))
|
|
#define HW_IPU_DISP_ALT3_SET(x, v) (HW_IPU_DISP_ALT3_WR(x, HW_IPU_DISP_ALT3_RD(x) | (v)))
|
|
#define HW_IPU_DISP_ALT3_CLR(x, v) (HW_IPU_DISP_ALT3_WR(x, HW_IPU_DISP_ALT3_RD(x) & ~(v)))
|
|
#define HW_IPU_DISP_ALT3_TOG(x, v) (HW_IPU_DISP_ALT3_WR(x, HW_IPU_DISP_ALT3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_ALT3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DISP_ALT3, field RUN_VALUE_M1_ALT_1[11:0] (RW)
|
|
*
|
|
* Counter pre defined value This fields defines the counter pre defines value. real value- 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1 (0) //!< Bit position for IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1.
|
|
#define BM_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1 (0x00000fff) //!< Bit mask for IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1) >> BP_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1.
|
|
#define BF_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1) & BM_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RUN_VALUE_M1_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1(x, v) (HW_IPU_DISP_ALT3_WR(x, (HW_IPU_DISP_ALT3_RD(x) & ~BM_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1) | BF_IPU_DISP_ALT3_RUN_VALUE_M1_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT3, field CNT_CLR_SEL_ALT_1[14:12] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1 (12) //!< Bit position for IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1.
|
|
#define BM_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1 (0x00007000) //!< Bit mask for IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1) >> BP_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1.
|
|
#define BF_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1) & BM_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CNT_CLR_SEL_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1(x, v) (HW_IPU_DISP_ALT3_WR(x, (HW_IPU_DISP_ALT3_RD(x) & ~BM_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1) | BF_IPU_DISP_ALT3_CNT_CLR_SEL_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT3, field CNT_AUTO_RELOAD_ALT_1[15] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the step_repeat_alt_0 field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the step_repeat_alt_0
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1 (15) //!< Bit position for IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1.
|
|
#define BM_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1 (0x00008000) //!< Bit mask for IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1) >> BP_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1.
|
|
#define BF_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1) & BM_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CNT_AUTO_RELOAD_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1(x, v) (HW_IPU_DISP_ALT3_WR(x, (HW_IPU_DISP_ALT3_RD(x) & ~BM_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1) | BF_IPU_DISP_ALT3_CNT_AUTO_RELOAD_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT3, field STEP_REPEAT_ALT_1[27:16] (RW)
|
|
*
|
|
* This fields defines the amount of repetitions that will be performed by the counter
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT3_STEP_REPEAT_ALT_1 (16) //!< Bit position for IPU_DISP_ALT3_STEP_REPEAT_ALT_1.
|
|
#define BM_IPU_DISP_ALT3_STEP_REPEAT_ALT_1 (0x0fff0000) //!< Bit mask for IPU_DISP_ALT3_STEP_REPEAT_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT3_STEP_REPEAT_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT3_STEP_REPEAT_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT3_STEP_REPEAT_ALT_1) >> BP_IPU_DISP_ALT3_STEP_REPEAT_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT3_STEP_REPEAT_ALT_1.
|
|
#define BF_IPU_DISP_ALT3_STEP_REPEAT_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT3_STEP_REPEAT_ALT_1) & BM_IPU_DISP_ALT3_STEP_REPEAT_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_REPEAT_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT3_STEP_REPEAT_ALT_1(x, v) (HW_IPU_DISP_ALT3_WR(x, (HW_IPU_DISP_ALT3_RD(x) & ~BM_IPU_DISP_ALT3_STEP_REPEAT_ALT_1) | BF_IPU_DISP_ALT3_STEP_REPEAT_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT3, field SEL_ALT_1[31:28] (RW)
|
|
*
|
|
* Select alternative parameters instead of DI Sync Wave Gen counter#. The DI is selected according
|
|
* to DP's synchronous channel destination
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - instead of counter 1
|
|
* - 0010 - instead of counter 2
|
|
* - 1000 - instead of counter 8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT3_SEL_ALT_1 (28) //!< Bit position for IPU_DISP_ALT3_SEL_ALT_1.
|
|
#define BM_IPU_DISP_ALT3_SEL_ALT_1 (0xf0000000) //!< Bit mask for IPU_DISP_ALT3_SEL_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT3_SEL_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT3_SEL_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT3_SEL_ALT_1) >> BP_IPU_DISP_ALT3_SEL_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT3_SEL_ALT_1.
|
|
#define BF_IPU_DISP_ALT3_SEL_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT3_SEL_ALT_1) & BM_IPU_DISP_ALT3_SEL_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SEL_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT3_SEL_ALT_1(x, v) (HW_IPU_DISP_ALT3_WR(x, (HW_IPU_DISP_ALT3_RD(x) & ~BM_IPU_DISP_ALT3_SEL_ALT_1) | BF_IPU_DISP_ALT3_SEL_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_ALT4 - Display Alternate Flow Control Register 4
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_ALT4 - Display Alternate Flow Control Register 4 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register controls various aspects of the display port.
|
|
*/
|
|
typedef union _hw_ipu_disp_alt4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_alt4_bitfields
|
|
{
|
|
unsigned OFFSET_VALUE_ALT_1 : 12; //!< [11:0] Counter offset value
|
|
unsigned OFFSET_RESOLUTION_ALT_1 : 3; //!< [14:12] Counter offset Resolution
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned RUN_RESOLUTION_ALT_1 : 3; //!< [18:16] Counter Run Resolution
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved
|
|
} B;
|
|
} hw_ipu_disp_alt4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_ALT4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_ALT4_ADDR(x) (REGS_IPU_BASE(x) + 0xd4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_ALT4(x) (*(volatile hw_ipu_disp_alt4_t *) HW_IPU_DISP_ALT4_ADDR(x))
|
|
#define HW_IPU_DISP_ALT4_RD(x) (HW_IPU_DISP_ALT4(x).U)
|
|
#define HW_IPU_DISP_ALT4_WR(x, v) (HW_IPU_DISP_ALT4(x).U = (v))
|
|
#define HW_IPU_DISP_ALT4_SET(x, v) (HW_IPU_DISP_ALT4_WR(x, HW_IPU_DISP_ALT4_RD(x) | (v)))
|
|
#define HW_IPU_DISP_ALT4_CLR(x, v) (HW_IPU_DISP_ALT4_WR(x, HW_IPU_DISP_ALT4_RD(x) & ~(v)))
|
|
#define HW_IPU_DISP_ALT4_TOG(x, v) (HW_IPU_DISP_ALT4_WR(x, HW_IPU_DISP_ALT4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_ALT4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DISP_ALT4, field OFFSET_VALUE_ALT_1[11:0] (RW)
|
|
*
|
|
* Counter offset value The counter can start counting after a pre defined delay This field defines
|
|
* the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1 (0) //!< Bit position for IPU_DISP_ALT4_OFFSET_VALUE_ALT_1.
|
|
#define BM_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1 (0x00000fff) //!< Bit mask for IPU_DISP_ALT4_OFFSET_VALUE_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT4_OFFSET_VALUE_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1) >> BP_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT4_OFFSET_VALUE_ALT_1.
|
|
#define BF_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1) & BM_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_VALUE_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1(x, v) (HW_IPU_DISP_ALT4_WR(x, (HW_IPU_DISP_ALT4_RD(x) & ~BM_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1) | BF_IPU_DISP_ALT4_OFFSET_VALUE_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT4, field OFFSET_RESOLUTION_ALT_1[14:12] (RW)
|
|
*
|
|
* Counter offset Resolution This field defines the trigger causing the offset counter to increment
|
|
* The counter offset resolution should be defined in the same way as in original DI's counter#
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1 (12) //!< Bit position for IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1.
|
|
#define BM_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1 (0x00007000) //!< Bit mask for IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1) >> BP_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1.
|
|
#define BF_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1) & BM_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_RESOLUTION_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1(x, v) (HW_IPU_DISP_ALT4_WR(x, (HW_IPU_DISP_ALT4_RD(x) & ~BM_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1) | BF_IPU_DISP_ALT4_OFFSET_RESOLUTION_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_ALT4, field RUN_RESOLUTION_ALT_1[18:16] (RW)
|
|
*
|
|
* Counter Run Resolution This field defines the trigger causing the counter to increment. The
|
|
* counter run resolution should be defined in the same way as in original DI's counter#
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1 (16) //!< Bit position for IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1.
|
|
#define BM_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1 (0x00070000) //!< Bit mask for IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1.
|
|
|
|
//! @brief Get value of IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1 from a register value.
|
|
#define BG_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1) >> BP_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1.
|
|
#define BF_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1) & BM_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RUN_RESOLUTION_ALT_1 field to a new value.
|
|
#define BW_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1(x, v) (HW_IPU_DISP_ALT4_WR(x, (HW_IPU_DISP_ALT4_RD(x) & ~BM_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1) | BF_IPU_DISP_ALT4_RUN_RESOLUTION_ALT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_MEM_RST - Memory Reset Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_MEM_RST - Memory Reset Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register controls the memory reset mechanism. IPU has a hardware mechanism for clearing the
|
|
* content of the internal memories. This allows the user to clear the content of or more of the
|
|
* internal memories without the need to perform write accesses to the memories.
|
|
*/
|
|
typedef union _hw_ipu_mem_rst
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_mem_rst_bitfields
|
|
{
|
|
unsigned RST_MEM_EN : 23; //!< [22:0] Reset Memory Enable
|
|
unsigned RESERVED0 : 8; //!< [30:23] Reserved
|
|
unsigned RST_MEM_START : 1; //!< [31] Memory Reset Start
|
|
} B;
|
|
} hw_ipu_mem_rst_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_MEM_RST register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_MEM_RST_ADDR(x) (REGS_IPU_BASE(x) + 0xdc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_MEM_RST(x) (*(volatile hw_ipu_mem_rst_t *) HW_IPU_MEM_RST_ADDR(x))
|
|
#define HW_IPU_MEM_RST_RD(x) (HW_IPU_MEM_RST(x).U)
|
|
#define HW_IPU_MEM_RST_WR(x, v) (HW_IPU_MEM_RST(x).U = (v))
|
|
#define HW_IPU_MEM_RST_SET(x, v) (HW_IPU_MEM_RST_WR(x, HW_IPU_MEM_RST_RD(x) | (v)))
|
|
#define HW_IPU_MEM_RST_CLR(x, v) (HW_IPU_MEM_RST_WR(x, HW_IPU_MEM_RST_RD(x) & ~(v)))
|
|
#define HW_IPU_MEM_RST_TOG(x, v) (HW_IPU_MEM_RST_WR(x, HW_IPU_MEM_RST_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_MEM_RST bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_MEM_RST, field RST_MEM_EN[22:0] (RW)
|
|
*
|
|
* Reset Memory Enable Each bit on this field enables the memory reset mechanism for a specific
|
|
* memory. The user should set the relevant bits for the memories that need to be cleared. Below is
|
|
* the list of memories and their corresponding bit. srm = rst_mem_en[0] alpha = rst_mem_en[1] cpmem
|
|
* = rst_mem_en[2] tpm = rst_mem_en[3] mpm = rst_mem_en[4] bm = rst_mem_en[5] rm = rst_mem_en[6]
|
|
* dstm = rst_mem_en[7] dsom = rst_mem_en[8] lut0 = rst_mem_en[9] lut1 = rst_mem_en[10] ram_smfc =
|
|
* rst_mem_en[11] vdi_fifo2 = rst_mem_en[12] vdi_fifo3 = rst_mem_en[13] icb = rst_mem_en[14]
|
|
* vdi_fifo1 = rst_mem_en[15] dc_template = rst_mem_en[20] dmfc_rd = rst_mem_en[21] dmfc_wr =
|
|
* rst_mem_en[22]
|
|
*/
|
|
//@{
|
|
#define BP_IPU_MEM_RST_RST_MEM_EN (0) //!< Bit position for IPU_MEM_RST_RST_MEM_EN.
|
|
#define BM_IPU_MEM_RST_RST_MEM_EN (0x007fffff) //!< Bit mask for IPU_MEM_RST_RST_MEM_EN.
|
|
|
|
//! @brief Get value of IPU_MEM_RST_RST_MEM_EN from a register value.
|
|
#define BG_IPU_MEM_RST_RST_MEM_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_MEM_RST_RST_MEM_EN) >> BP_IPU_MEM_RST_RST_MEM_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_MEM_RST_RST_MEM_EN.
|
|
#define BF_IPU_MEM_RST_RST_MEM_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_MEM_RST_RST_MEM_EN) & BM_IPU_MEM_RST_RST_MEM_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RST_MEM_EN field to a new value.
|
|
#define BW_IPU_MEM_RST_RST_MEM_EN(x, v) (HW_IPU_MEM_RST_WR(x, (HW_IPU_MEM_RST_RD(x) & ~BM_IPU_MEM_RST_RST_MEM_EN) | BF_IPU_MEM_RST_RST_MEM_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_MEM_RST, field RST_MEM_START[31] (RW)
|
|
*
|
|
* Memory Reset Start Writing one to this bit activate the memory reset mechanism. The memories that
|
|
* their corresponding RST_MEM_EN bit is set will be cleared. When the memory reset mechanism
|
|
* completes the memory clearing procedure this bit will be automatically cleared.
|
|
*
|
|
* Values:
|
|
* - 0 - Idle, the memory reset mechanism is not working.
|
|
* - 1 - The memory reset mechanism is activated and busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_MEM_RST_RST_MEM_START (31) //!< Bit position for IPU_MEM_RST_RST_MEM_START.
|
|
#define BM_IPU_MEM_RST_RST_MEM_START (0x80000000) //!< Bit mask for IPU_MEM_RST_RST_MEM_START.
|
|
|
|
//! @brief Get value of IPU_MEM_RST_RST_MEM_START from a register value.
|
|
#define BG_IPU_MEM_RST_RST_MEM_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_MEM_RST_RST_MEM_START) >> BP_IPU_MEM_RST_RST_MEM_START)
|
|
|
|
//! @brief Format value for bitfield IPU_MEM_RST_RST_MEM_START.
|
|
#define BF_IPU_MEM_RST_RST_MEM_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_MEM_RST_RST_MEM_START) & BM_IPU_MEM_RST_RST_MEM_START)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RST_MEM_START field to a new value.
|
|
#define BW_IPU_MEM_RST_RST_MEM_START(x, v) (HW_IPU_MEM_RST_WR(x, (HW_IPU_MEM_RST_RD(x) & ~BM_IPU_MEM_RST_RST_MEM_START) | BF_IPU_MEM_RST_RST_MEM_START(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_PM - Power Modes Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_PM - Power Modes Control Register (RW)
|
|
*
|
|
* Reset value: 0x08100810
|
|
*
|
|
* This register controls the automatic transitions of the IPU between different power modes of the
|
|
* SoC and handles the clock change modes.
|
|
*/
|
|
typedef union _hw_ipu_pm
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_pm_bitfields
|
|
{
|
|
unsigned DI0_CLK_PERIOD_0 : 7; //!< [6:0] DI0_CLK period option 0.
|
|
unsigned DI0_CLK_PERIOD_1 : 7; //!< [13:7] DI0_CLK period option 1.
|
|
unsigned DI0_SRM_CLOCK_CHANGE_MODE : 1; //!< [14] SRM clock change mode
|
|
unsigned CLCOK_MODE_STAT : 1; //!< [15] Clock mode status
|
|
unsigned DI1_CLK_PERIOD_0 : 7; //!< [22:16] DI1_CLK period option 0.
|
|
unsigned DI1_CLK_PERIOD_1 : 7; //!< [29:23] DI1_CLK period option 1.
|
|
unsigned DI1_SRM_CLOCK_CHANGE_MODE : 1; //!< [30] SRM clock change mode
|
|
unsigned LPSR_MODE : 1; //!< [31] LPSR Mode
|
|
} B;
|
|
} hw_ipu_pm_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_PM register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_PM_ADDR(x) (REGS_IPU_BASE(x) + 0xe0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_PM(x) (*(volatile hw_ipu_pm_t *) HW_IPU_PM_ADDR(x))
|
|
#define HW_IPU_PM_RD(x) (HW_IPU_PM(x).U)
|
|
#define HW_IPU_PM_WR(x, v) (HW_IPU_PM(x).U = (v))
|
|
#define HW_IPU_PM_SET(x, v) (HW_IPU_PM_WR(x, HW_IPU_PM_RD(x) | (v)))
|
|
#define HW_IPU_PM_CLR(x, v) (HW_IPU_PM_WR(x, HW_IPU_PM_RD(x) & ~(v)))
|
|
#define HW_IPU_PM_TOG(x, v) (HW_IPU_PM_WR(x, HW_IPU_PM_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_PM bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_PM, field DI0_CLK_PERIOD_0[6:0] (RW)
|
|
*
|
|
* DI0_CLK period option 0. This parameter defines the period of the clock that the DI0 works with.
|
|
* This parameter contains integer part (bits [6:4]) and fractional part (bits [3:0]). Setting this
|
|
* value to 1.0 (default) means that the DI0 works on the fastest possible clock. Setting a value
|
|
* smaller than 1.0 is not allowed. The value to be programmed to the DI0_CLK_PERIOD_1 field is
|
|
* equal to: Fast_freq/Target_freq Where: Target_freq = The frequency that the DI clock works with
|
|
* Fast_freq = fastest possible clock that the DI can work with
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_DI0_CLK_PERIOD_0 (0) //!< Bit position for IPU_PM_DI0_CLK_PERIOD_0.
|
|
#define BM_IPU_PM_DI0_CLK_PERIOD_0 (0x0000007f) //!< Bit mask for IPU_PM_DI0_CLK_PERIOD_0.
|
|
|
|
//! @brief Get value of IPU_PM_DI0_CLK_PERIOD_0 from a register value.
|
|
#define BG_IPU_PM_DI0_CLK_PERIOD_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_DI0_CLK_PERIOD_0) >> BP_IPU_PM_DI0_CLK_PERIOD_0)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_DI0_CLK_PERIOD_0.
|
|
#define BF_IPU_PM_DI0_CLK_PERIOD_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_DI0_CLK_PERIOD_0) & BM_IPU_PM_DI0_CLK_PERIOD_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CLK_PERIOD_0 field to a new value.
|
|
#define BW_IPU_PM_DI0_CLK_PERIOD_0(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_DI0_CLK_PERIOD_0) | BF_IPU_PM_DI0_CLK_PERIOD_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field DI0_CLK_PERIOD_1[13:7] (RW)
|
|
*
|
|
* DI0_CLK period option 1. This parameter defines the period of the clock that the DI0 works with.
|
|
* This parameter contains integer part (bits [6:4]) and fractional part (bits [3:0]). Setting this
|
|
* value to 1.0 (default) means that the DI0 works on the fastest possible clock. Setting a value
|
|
* smaller than 1.0 is not allowed. The value to be programmed to the DI0_CLK_PERIOD_1 field is
|
|
* equal to: Fast_freq/Target_freq Where: Target_freq = The frequency that the DI clock works with
|
|
* Fast_freq = fastest possible clock that the DI can work with
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_DI0_CLK_PERIOD_1 (7) //!< Bit position for IPU_PM_DI0_CLK_PERIOD_1.
|
|
#define BM_IPU_PM_DI0_CLK_PERIOD_1 (0x00003f80) //!< Bit mask for IPU_PM_DI0_CLK_PERIOD_1.
|
|
|
|
//! @brief Get value of IPU_PM_DI0_CLK_PERIOD_1 from a register value.
|
|
#define BG_IPU_PM_DI0_CLK_PERIOD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_DI0_CLK_PERIOD_1) >> BP_IPU_PM_DI0_CLK_PERIOD_1)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_DI0_CLK_PERIOD_1.
|
|
#define BF_IPU_PM_DI0_CLK_PERIOD_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_DI0_CLK_PERIOD_1) & BM_IPU_PM_DI0_CLK_PERIOD_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CLK_PERIOD_1 field to a new value.
|
|
#define BW_IPU_PM_DI0_CLK_PERIOD_1(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_DI0_CLK_PERIOD_1) | BF_IPU_PM_DI0_CLK_PERIOD_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field DI0_SRM_CLOCK_CHANGE_MODE[14] (RW)
|
|
*
|
|
* SRM clock change mode When the clock is going to be changed to any new ratio other then 1:1, 1:2.
|
|
* 1:4. The user needs to prepare an alternate set of DI setting in the SRM. This bit enable this
|
|
* mode. This bit is self cleared.
|
|
*
|
|
* Values:
|
|
* - 0 - SRM clock change mode is disabled.
|
|
* - 1 - SRM clock change mode is enabled; the next clock change will be done by updating the DI settings
|
|
* from the SRM
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE (14) //!< Bit position for IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE.
|
|
#define BM_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE (0x00004000) //!< Bit mask for IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE.
|
|
|
|
//! @brief Get value of IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE from a register value.
|
|
#define BG_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE) >> BP_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE.
|
|
#define BF_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE) & BM_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SRM_CLOCK_CHANGE_MODE field to a new value.
|
|
#define BW_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE) | BF_IPU_PM_DI0_SRM_CLOCK_CHANGE_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field CLCOK_MODE_STAT[15] (RO)
|
|
*
|
|
* Clock mode status This is a read only bit indicating what is the current clock mode
|
|
*
|
|
* Values:
|
|
* - 0 - current clock mode is 0
|
|
* - 1 - current clock mode is 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_CLCOK_MODE_STAT (15) //!< Bit position for IPU_PM_CLCOK_MODE_STAT.
|
|
#define BM_IPU_PM_CLCOK_MODE_STAT (0x00008000) //!< Bit mask for IPU_PM_CLCOK_MODE_STAT.
|
|
|
|
//! @brief Get value of IPU_PM_CLCOK_MODE_STAT from a register value.
|
|
#define BG_IPU_PM_CLCOK_MODE_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_CLCOK_MODE_STAT) >> BP_IPU_PM_CLCOK_MODE_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field DI1_CLK_PERIOD_0[22:16] (RW)
|
|
*
|
|
* DI1_CLK period option 0. This parameter defines the period of the clock that the DI1 works with.
|
|
* This parameter contains integer part (bits [6:4]) and fractional part (bits [3:0]). Setting this
|
|
* value to 1.0 (default) means that the DI1 works on the fastest possible clock. Setting a value
|
|
* smaller than 1.0 is not allowed. The value to be programmed to the DI1_CLK_PERIOD_1 field is
|
|
* equal to: Fast_freq/Target_freq Where: Target_freq = The frequency that the DI clock works with
|
|
* Fast_freq = fastest possible clock that the DI can work with
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_DI1_CLK_PERIOD_0 (16) //!< Bit position for IPU_PM_DI1_CLK_PERIOD_0.
|
|
#define BM_IPU_PM_DI1_CLK_PERIOD_0 (0x007f0000) //!< Bit mask for IPU_PM_DI1_CLK_PERIOD_0.
|
|
|
|
//! @brief Get value of IPU_PM_DI1_CLK_PERIOD_0 from a register value.
|
|
#define BG_IPU_PM_DI1_CLK_PERIOD_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_DI1_CLK_PERIOD_0) >> BP_IPU_PM_DI1_CLK_PERIOD_0)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_DI1_CLK_PERIOD_0.
|
|
#define BF_IPU_PM_DI1_CLK_PERIOD_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_DI1_CLK_PERIOD_0) & BM_IPU_PM_DI1_CLK_PERIOD_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CLK_PERIOD_0 field to a new value.
|
|
#define BW_IPU_PM_DI1_CLK_PERIOD_0(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_DI1_CLK_PERIOD_0) | BF_IPU_PM_DI1_CLK_PERIOD_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field DI1_CLK_PERIOD_1[29:23] (RW)
|
|
*
|
|
* DI1_CLK period option 1. This parameter defines the period of the clock that the DI1 works with.
|
|
* This parameter contains integer part (bits [6:4]) and fractional part (bits [3:0]). Setting this
|
|
* value to 1.0 (default) means that the DI1 works on the fastest possible clock. Setting a value
|
|
* smaller than 1.0 is not allowed. The value to be programmed to the DI1_CLK_PERIOD_1 field is
|
|
* equal to: Fast_freq/Target_freq Where: Target_freq = The frequency that the DI clock works with
|
|
* Fast_freq = fastest possible clock that the DI can work with
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_DI1_CLK_PERIOD_1 (23) //!< Bit position for IPU_PM_DI1_CLK_PERIOD_1.
|
|
#define BM_IPU_PM_DI1_CLK_PERIOD_1 (0x3f800000) //!< Bit mask for IPU_PM_DI1_CLK_PERIOD_1.
|
|
|
|
//! @brief Get value of IPU_PM_DI1_CLK_PERIOD_1 from a register value.
|
|
#define BG_IPU_PM_DI1_CLK_PERIOD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_DI1_CLK_PERIOD_1) >> BP_IPU_PM_DI1_CLK_PERIOD_1)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_DI1_CLK_PERIOD_1.
|
|
#define BF_IPU_PM_DI1_CLK_PERIOD_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_DI1_CLK_PERIOD_1) & BM_IPU_PM_DI1_CLK_PERIOD_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CLK_PERIOD_1 field to a new value.
|
|
#define BW_IPU_PM_DI1_CLK_PERIOD_1(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_DI1_CLK_PERIOD_1) | BF_IPU_PM_DI1_CLK_PERIOD_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field DI1_SRM_CLOCK_CHANGE_MODE[30] (RW)
|
|
*
|
|
* SRM clock change mode When the clock is going to be changed to any new ratio other then 1:1, 1:2.
|
|
* 1:4. The user needs to prepare an alternate set of DI setting in the SRM. This bit enable this
|
|
* mode. This bit is self cleared.
|
|
*
|
|
* Values:
|
|
* - 0 - SRM clock change mode is disabled.
|
|
* - 1 - SRM clock change mode is enabled; the next clock change will be done by updating the DI settings
|
|
* from the SRM
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE (30) //!< Bit position for IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE.
|
|
#define BM_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE (0x40000000) //!< Bit mask for IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE.
|
|
|
|
//! @brief Get value of IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE from a register value.
|
|
#define BG_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE) >> BP_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE.
|
|
#define BF_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE) & BM_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SRM_CLOCK_CHANGE_MODE field to a new value.
|
|
#define BW_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE) | BF_IPU_PM_DI1_SRM_CLOCK_CHANGE_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_PM, field LPSR_MODE[31] (RW)
|
|
*
|
|
* LPSR Mode This bit indicates that the next attempt for entering low power mode is an attempt to
|
|
* move to LPST mode. Setting this bit by the user is essential in order to assure proper response
|
|
* of the IPU to the assertion of the stop request from the CCM.
|
|
*
|
|
* Values:
|
|
* - 0 - Next low power mode is not LPSR
|
|
* - 1 - Next low power mode will be LPSR
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PM_LPSR_MODE (31) //!< Bit position for IPU_PM_LPSR_MODE.
|
|
#define BM_IPU_PM_LPSR_MODE (0x80000000) //!< Bit mask for IPU_PM_LPSR_MODE.
|
|
|
|
//! @brief Get value of IPU_PM_LPSR_MODE from a register value.
|
|
#define BG_IPU_PM_LPSR_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PM_LPSR_MODE) >> BP_IPU_PM_LPSR_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_PM_LPSR_MODE.
|
|
#define BF_IPU_PM_LPSR_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_PM_LPSR_MODE) & BM_IPU_PM_LPSR_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the LPSR_MODE field to a new value.
|
|
#define BW_IPU_PM_LPSR_MODE(x, v) (HW_IPU_PM_WR(x, (HW_IPU_PM_RD(x) & ~BM_IPU_PM_LPSR_MODE) | BF_IPU_PM_LPSR_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_GPR - General Purpose Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_GPR - General Purpose Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains general purpose bits.
|
|
*/
|
|
typedef union _hw_ipu_gpr
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_gpr_bitfields
|
|
{
|
|
unsigned IPU_GPN : 20; //!< [19:0] IPU General Purpose bit.
|
|
unsigned IPU_CH_BUF2_RDY0_CLR : 1; //!< [20] This bit defines the IPU_CH_BUF2_RDY0 properties.
|
|
unsigned IPU_CH_BUF2_RDY1_CLR : 1; //!< [21] This bit defines the IPU_CH_BUF2_RDY1 properties.
|
|
unsigned IPU_DI0_CLK_CHANGE_ACK_DIS : 1; //!< [22] Disable DI0's clock change mechanism.
|
|
unsigned IPU_DI1_CLK_CHANGE_ACK_DIS : 1; //!< [23] Disable DI1's clock change mechanism.
|
|
unsigned IPU_ALT_CH_BUF0_RDY0_CLR : 1; //!< [24] This bit defines the IPU_ALT_CH_BUF0_RDY0 properties.
|
|
unsigned IPU_ALT_CH_BUF0_RDY1_CLR : 1; //!< [25] This bit defines the IPU_ALT_CH_BUF0_RDY1 properties.
|
|
unsigned IPU_ALT_CH_BUF1_RDY0_CLR : 1; //!< [26] This bit defines the IPU_ALT_CH_BUF1_RDY0 properties.
|
|
unsigned IPU_ALT_CH_BUF1_RDY1_CLR : 1; //!< [27] This bit defines the IPU_ALT_CH_BUF1_RDY1 properties.
|
|
unsigned IPU_CH_BUF0_RDY0_CLR : 1; //!< [28] This bit defines the IPU_CH_BUF0_RDY0 properties.
|
|
unsigned IPU_CH_BUF0_RDY1_CLR : 1; //!< [29] This bit defines the IPU_CH_BUF0_RDY1 properties.
|
|
unsigned IPU_CH_BUF1_RDY0_CLR : 1; //!< [30] This bit defines the IPU_CH_BUF1_RDY0 properties.
|
|
unsigned IPU_CH_BUF1_RDY1_CLR : 1; //!< [31] This bit defines the IPU_CH_BUF1_RDY1 properties.
|
|
} B;
|
|
} hw_ipu_gpr_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_GPR register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_GPR_ADDR(x) (REGS_IPU_BASE(x) + 0xe4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_GPR(x) (*(volatile hw_ipu_gpr_t *) HW_IPU_GPR_ADDR(x))
|
|
#define HW_IPU_GPR_RD(x) (HW_IPU_GPR(x).U)
|
|
#define HW_IPU_GPR_WR(x, v) (HW_IPU_GPR(x).U = (v))
|
|
#define HW_IPU_GPR_SET(x, v) (HW_IPU_GPR_WR(x, HW_IPU_GPR_RD(x) | (v)))
|
|
#define HW_IPU_GPR_CLR(x, v) (HW_IPU_GPR_WR(x, HW_IPU_GPR_RD(x) & ~(v)))
|
|
#define HW_IPU_GPR_TOG(x, v) (HW_IPU_GPR_WR(x, HW_IPU_GPR_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_GPR bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_GPR, field IPU_GPN[19:0] (RW)
|
|
*
|
|
* IPU General Purpose bit. n Indicates the corresponding DMA channel number. This bits are general
|
|
* Read/Write bits, reserved for future use
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_GPN (0) //!< Bit position for IPU_GPR_IPU_GPN.
|
|
#define BM_IPU_GPR_IPU_GPN (0x000fffff) //!< Bit mask for IPU_GPR_IPU_GPN.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_GPN from a register value.
|
|
#define BG_IPU_GPR_IPU_GPN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_GPN) >> BP_IPU_GPR_IPU_GPN)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_GPN.
|
|
#define BF_IPU_GPR_IPU_GPN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_GPN) & BM_IPU_GPR_IPU_GPN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_GPN field to a new value.
|
|
#define BW_IPU_GPR_IPU_GPN(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_GPN) | BF_IPU_GPR_IPU_GPN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_CH_BUF2_RDY0_CLR[20] (RW)
|
|
*
|
|
* This bit defines the IPU_CH_BUF2_RDY0 properties. This register can be a write one to clear OR
|
|
* write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_CH_BUF2_RDY0 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_CH_BUF2_RDY0 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_CH_BUF2_RDY0_CLR (20) //!< Bit position for IPU_GPR_IPU_CH_BUF2_RDY0_CLR.
|
|
#define BM_IPU_GPR_IPU_CH_BUF2_RDY0_CLR (0x00100000) //!< Bit mask for IPU_GPR_IPU_CH_BUF2_RDY0_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_CH_BUF2_RDY0_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_CH_BUF2_RDY0_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_CH_BUF2_RDY0_CLR) >> BP_IPU_GPR_IPU_CH_BUF2_RDY0_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_CH_BUF2_RDY0_CLR.
|
|
#define BF_IPU_GPR_IPU_CH_BUF2_RDY0_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_CH_BUF2_RDY0_CLR) & BM_IPU_GPR_IPU_CH_BUF2_RDY0_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_CH_BUF2_RDY0_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_CH_BUF2_RDY0_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_CH_BUF2_RDY0_CLR) | BF_IPU_GPR_IPU_CH_BUF2_RDY0_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_CH_BUF2_RDY1_CLR[21] (RW)
|
|
*
|
|
* This bit defines the IPU_CH_BUF2_RDY1 properties. This register can be a write one to clear OR
|
|
* write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_CH_BUF2_RDY1 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_CH_BUF2_RDY1 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_CH_BUF2_RDY1_CLR (21) //!< Bit position for IPU_GPR_IPU_CH_BUF2_RDY1_CLR.
|
|
#define BM_IPU_GPR_IPU_CH_BUF2_RDY1_CLR (0x00200000) //!< Bit mask for IPU_GPR_IPU_CH_BUF2_RDY1_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_CH_BUF2_RDY1_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_CH_BUF2_RDY1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_CH_BUF2_RDY1_CLR) >> BP_IPU_GPR_IPU_CH_BUF2_RDY1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_CH_BUF2_RDY1_CLR.
|
|
#define BF_IPU_GPR_IPU_CH_BUF2_RDY1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_CH_BUF2_RDY1_CLR) & BM_IPU_GPR_IPU_CH_BUF2_RDY1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_CH_BUF2_RDY1_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_CH_BUF2_RDY1_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_CH_BUF2_RDY1_CLR) | BF_IPU_GPR_IPU_CH_BUF2_RDY1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_DI0_CLK_CHANGE_ACK_DIS[22] (RW)
|
|
*
|
|
* Disable DI0's clock change mechanism.
|
|
*
|
|
* Values:
|
|
* - 0 - clock change mechanism is disabled. DI performs the clock change procedure
|
|
* - 1 - clock change mechanism is disabled. DI automatically acknowledges a clock change request
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS (22) //!< Bit position for IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS.
|
|
#define BM_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS (0x00400000) //!< Bit mask for IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS from a register value.
|
|
#define BG_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS) >> BP_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS.
|
|
#define BF_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS) & BM_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_DI0_CLK_CHANGE_ACK_DIS field to a new value.
|
|
#define BW_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS) | BF_IPU_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_DI1_CLK_CHANGE_ACK_DIS[23] (RW)
|
|
*
|
|
* Disable DI1's clock change mechanism.
|
|
*
|
|
* Values:
|
|
* - 0 - clock change mechanism is disabled. DI performs the clock change procedure
|
|
* - 1 - clock change mechanism is disabled. DI automatically acknowledges a clock change request
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS (23) //!< Bit position for IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS.
|
|
#define BM_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS (0x00800000) //!< Bit mask for IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS from a register value.
|
|
#define BG_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS) >> BP_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS.
|
|
#define BF_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS) & BM_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_DI1_CLK_CHANGE_ACK_DIS field to a new value.
|
|
#define BW_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS) | BF_IPU_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_ALT_CH_BUF0_RDY0_CLR[24] (RW)
|
|
*
|
|
* This bit defines the IPU_ALT_CH_BUF0_RDY0 properties. This register can be a write one to clear
|
|
* OR write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_ALT_CH_BUF0_RDY0 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF0_RDY0 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR (24) //!< Bit position for IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR.
|
|
#define BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR (0x01000000) //!< Bit mask for IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR) >> BP_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR.
|
|
#define BF_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR) & BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_ALT_CH_BUF0_RDY0_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR) | BF_IPU_GPR_IPU_ALT_CH_BUF0_RDY0_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_ALT_CH_BUF0_RDY1_CLR[25] (RW)
|
|
*
|
|
* This bit defines the IPU_ALT_CH_BUF0_RDY1 properties. This register can be a write one to clear
|
|
* OR write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_ALT_CH_BUF0_RDY1 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF0_RDY1 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR (25) //!< Bit position for IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR.
|
|
#define BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR (0x02000000) //!< Bit mask for IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR) >> BP_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR.
|
|
#define BF_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR) & BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_ALT_CH_BUF0_RDY1_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR) | BF_IPU_GPR_IPU_ALT_CH_BUF0_RDY1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_ALT_CH_BUF1_RDY0_CLR[26] (RW)
|
|
*
|
|
* This bit defines the IPU_ALT_CH_BUF1_RDY0 properties. This register can be a write one to clear
|
|
* OR write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_ALT_CH_BUF1_RDY0 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF1_RDY0 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR (26) //!< Bit position for IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR.
|
|
#define BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR (0x04000000) //!< Bit mask for IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR) >> BP_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR.
|
|
#define BF_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR) & BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_ALT_CH_BUF1_RDY0_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR) | BF_IPU_GPR_IPU_ALT_CH_BUF1_RDY0_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_ALT_CH_BUF1_RDY1_CLR[27] (RW)
|
|
*
|
|
* This bit defines the IPU_ALT_CH_BUF1_RDY1 properties. This register can be a write one to clear
|
|
* OR write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_ALT_CH_BUF1_RDY1 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF1_RDY1 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR (27) //!< Bit position for IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR.
|
|
#define BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR (0x08000000) //!< Bit mask for IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR) >> BP_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR.
|
|
#define BF_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR) & BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_ALT_CH_BUF1_RDY1_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR) | BF_IPU_GPR_IPU_ALT_CH_BUF1_RDY1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_CH_BUF0_RDY0_CLR[28] (RW)
|
|
*
|
|
* This bit defines the IPU_CH_BUF0_RDY0 properties. This register can be a write one to clear OR
|
|
* write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_CH_BUF0_RDY0 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_CH_BUF0_RDY0 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_CH_BUF0_RDY0_CLR (28) //!< Bit position for IPU_GPR_IPU_CH_BUF0_RDY0_CLR.
|
|
#define BM_IPU_GPR_IPU_CH_BUF0_RDY0_CLR (0x10000000) //!< Bit mask for IPU_GPR_IPU_CH_BUF0_RDY0_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_CH_BUF0_RDY0_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_CH_BUF0_RDY0_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_CH_BUF0_RDY0_CLR) >> BP_IPU_GPR_IPU_CH_BUF0_RDY0_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_CH_BUF0_RDY0_CLR.
|
|
#define BF_IPU_GPR_IPU_CH_BUF0_RDY0_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_CH_BUF0_RDY0_CLR) & BM_IPU_GPR_IPU_CH_BUF0_RDY0_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_CH_BUF0_RDY0_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_CH_BUF0_RDY0_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_CH_BUF0_RDY0_CLR) | BF_IPU_GPR_IPU_CH_BUF0_RDY0_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_CH_BUF0_RDY1_CLR[29] (RW)
|
|
*
|
|
* This bit defines the IPU_CH_BUF0_RDY1 properties. This register can be a write one to clear OR
|
|
* write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_CH_BUF0_RDY1 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_CH_BUF0_RDY1 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_CH_BUF0_RDY1_CLR (29) //!< Bit position for IPU_GPR_IPU_CH_BUF0_RDY1_CLR.
|
|
#define BM_IPU_GPR_IPU_CH_BUF0_RDY1_CLR (0x20000000) //!< Bit mask for IPU_GPR_IPU_CH_BUF0_RDY1_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_CH_BUF0_RDY1_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_CH_BUF0_RDY1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_CH_BUF0_RDY1_CLR) >> BP_IPU_GPR_IPU_CH_BUF0_RDY1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_CH_BUF0_RDY1_CLR.
|
|
#define BF_IPU_GPR_IPU_CH_BUF0_RDY1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_CH_BUF0_RDY1_CLR) & BM_IPU_GPR_IPU_CH_BUF0_RDY1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_CH_BUF0_RDY1_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_CH_BUF0_RDY1_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_CH_BUF0_RDY1_CLR) | BF_IPU_GPR_IPU_CH_BUF0_RDY1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_CH_BUF1_RDY0_CLR[30] (RW)
|
|
*
|
|
* This bit defines the IPU_CH_BUF1_RDY0 properties. This register can be a write one to clear OR
|
|
* write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_CH_BUF1_RDY0 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_CH_BUF1_RDY0 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_CH_BUF1_RDY0_CLR (30) //!< Bit position for IPU_GPR_IPU_CH_BUF1_RDY0_CLR.
|
|
#define BM_IPU_GPR_IPU_CH_BUF1_RDY0_CLR (0x40000000) //!< Bit mask for IPU_GPR_IPU_CH_BUF1_RDY0_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_CH_BUF1_RDY0_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_CH_BUF1_RDY0_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_CH_BUF1_RDY0_CLR) >> BP_IPU_GPR_IPU_CH_BUF1_RDY0_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_CH_BUF1_RDY0_CLR.
|
|
#define BF_IPU_GPR_IPU_CH_BUF1_RDY0_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_CH_BUF1_RDY0_CLR) & BM_IPU_GPR_IPU_CH_BUF1_RDY0_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_CH_BUF1_RDY0_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_CH_BUF1_RDY0_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_CH_BUF1_RDY0_CLR) | BF_IPU_GPR_IPU_CH_BUF1_RDY0_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_GPR, field IPU_CH_BUF1_RDY1_CLR[31] (RW)
|
|
*
|
|
* This bit defines the IPU_CH_BUF1_RDY1 properties. This register can be a write one to clear OR
|
|
* write one to set.
|
|
*
|
|
* Values:
|
|
* - 0 - writing one to a bit of this register sets this bit IPU_CH_BUF1_RDY1 is w1s register
|
|
* - 1 - writing one to a bit of this register clears this bit; IPU_CH_BUF1_RDY1 is w1c register
|
|
*/
|
|
//@{
|
|
#define BP_IPU_GPR_IPU_CH_BUF1_RDY1_CLR (31) //!< Bit position for IPU_GPR_IPU_CH_BUF1_RDY1_CLR.
|
|
#define BM_IPU_GPR_IPU_CH_BUF1_RDY1_CLR (0x80000000) //!< Bit mask for IPU_GPR_IPU_CH_BUF1_RDY1_CLR.
|
|
|
|
//! @brief Get value of IPU_GPR_IPU_CH_BUF1_RDY1_CLR from a register value.
|
|
#define BG_IPU_GPR_IPU_CH_BUF1_RDY1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_GPR_IPU_CH_BUF1_RDY1_CLR) >> BP_IPU_GPR_IPU_CH_BUF1_RDY1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_GPR_IPU_CH_BUF1_RDY1_CLR.
|
|
#define BF_IPU_GPR_IPU_CH_BUF1_RDY1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_GPR_IPU_CH_BUF1_RDY1_CLR) & BM_IPU_GPR_IPU_CH_BUF1_RDY1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IPU_CH_BUF1_RDY1_CLR field to a new value.
|
|
#define BW_IPU_GPR_IPU_CH_BUF1_RDY1_CLR(x, v) (HW_IPU_GPR_WR(x, (HW_IPU_GPR_RD(x) & ~BM_IPU_GPR_IPU_CH_BUF1_RDY1_CLR) | BF_IPU_GPR_IPU_CH_BUF1_RDY1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CH_DB_MODE_SEL1 - Channel Double Buffer Mode Select 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CH_DB_MODE_SEL1 - Channel Double Buffer Mode Select 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains double buffer mode select control information for 32 IPU's DMA channels.
|
|
*/
|
|
typedef union _hw_ipu_ch_db_mode_sel1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ch_db_mode_sel1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned DMA_CH_DB_MODE_SEL_33 : 1; //!< [1] Double Buffer Mode Select.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned DMA_CH_DB_MODE_SEL_40 : 1; //!< [8] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_41 : 1; //!< [9] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_42 : 1; //!< [10] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_43 : 1; //!< [11] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_44 : 1; //!< [12] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_45 : 1; //!< [13] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_46 : 1; //!< [14] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_47 : 1; //!< [15] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_48 : 1; //!< [16] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_49 : 1; //!< [17] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_50 : 1; //!< [18] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_51 : 1; //!< [19] Double Buffer Mode Select.
|
|
unsigned DMA_CH_DB_MODE_SEL_52 : 1; //!< [20] Double Buffer Mode Select.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_ch_db_mode_sel1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_DB_MODE_SEL1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_DB_MODE_SEL1_ADDR(x) (REGS_IPU_BASE(x) + 0x154)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_DB_MODE_SEL1(x) (*(volatile hw_ipu_ch_db_mode_sel1_t *) HW_IPU_CH_DB_MODE_SEL1_ADDR(x))
|
|
#define HW_IPU_CH_DB_MODE_SEL1_RD(x) (HW_IPU_CH_DB_MODE_SEL1(x).U)
|
|
#define HW_IPU_CH_DB_MODE_SEL1_WR(x, v) (HW_IPU_CH_DB_MODE_SEL1(x).U = (v))
|
|
#define HW_IPU_CH_DB_MODE_SEL1_SET(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, HW_IPU_CH_DB_MODE_SEL1_RD(x) | (v)))
|
|
#define HW_IPU_CH_DB_MODE_SEL1_CLR(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_DB_MODE_SEL1_TOG(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, HW_IPU_CH_DB_MODE_SEL1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_DB_MODE_SEL1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_33[1] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33 (1) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33 (0x00000002) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_33 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_40[8] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40 (8) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40 (0x00000100) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_40 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_41[9] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41 (9) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41 (0x00000200) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_41 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_42[10] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42 (10) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42 (0x00000400) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_42 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_42(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_43[11] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43 (11) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43.
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|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43 (0x00000800) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43.
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|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43)
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|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_43 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_43(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_44[12] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44 (12) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44.
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|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44 (0x00001000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44.
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//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44)
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|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_44 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_45[13] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45 (13) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45 (0x00002000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45.
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|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_45 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_46[14] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46 (14) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46 (0x00004000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_46 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_47[15] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47 (15) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47 (0x00008000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_47 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_48[16] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48 (16) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48 (0x00010000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_48 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_49[17] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49 (17) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49 (0x00020000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_49 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_50[18] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50 (18) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50 (0x00040000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_50 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_51[19] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51 (19) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51 (0x00080000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51.
|
|
#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_DB_MODE_SEL_51 field to a new value.
|
|
#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_DB_MODE_SEL1, field DMA_CH_DB_MODE_SEL_52[20] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52 (20) //!< Bit position for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52.
|
|
#define BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52 (0x00100000) //!< Bit mask for IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52.
|
|
|
|
//! @brief Get value of IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52 from a register value.
|
|
#define BG_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52) >> BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52.
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#define BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52) & BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_DB_MODE_SEL_52 field to a new value.
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#define BW_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52(x, v) (HW_IPU_CH_DB_MODE_SEL1_WR(x, (HW_IPU_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52) | BF_IPU_CH_DB_MODE_SEL1_DMA_CH_DB_MODE_SEL_52(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_ALT_CH_DB_MODE_SEL0 - Alternate Channel Double Buffer Mode Select 0 Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_ALT_CH_DB_MODE_SEL0 - Alternate Channel Double Buffer Mode Select 0 Register (RW)
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*
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* Reset value: 0x00000000
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*
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* The register contains double buffer mode select control information for 32 IPU's DMA channels.
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*/
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typedef union _hw_ipu_alt_ch_db_mode_sel0
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{
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reg32_t U;
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struct _hw_ipu_alt_ch_db_mode_sel0_bitfields
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{
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unsigned RESERVED0 : 4; //!< [3:0] Reserved.
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unsigned DMA_CH_ALT_DB_MODE_SEL_4 : 1; //!< [4] Double Buffer Mode Select.
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unsigned DMA_CH_ALT_DB_MODE_SEL_5 : 1; //!< [5] Double Buffer Mode Select.
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unsigned DMA_CH_ALT_DB_MODE_SEL_6 : 1; //!< [6] Double Buffer Mode Select.
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unsigned DMA_CH_ALT_DB_MODE_SEL_7 : 1; //!< [7] Double Buffer Mode Select.
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unsigned RESERVED1 : 16; //!< [23:8] Reserved.
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unsigned DMA_CH_ALT_DB_MODE_SEL_24 : 1; //!< [24] Double Buffer Mode Select.
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unsigned RESERVED2 : 4; //!< [28:25] Reserved.
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unsigned DMA_CH_ALT_DB_MODE_SEL_29 : 1; //!< [29] Double Buffer Mode Select.
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unsigned RESERVED3 : 2; //!< [31:30] Reserved.
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} B;
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} hw_ipu_alt_ch_db_mode_sel0_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_ALT_CH_DB_MODE_SEL0 register
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*/
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//@{
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#define HW_IPU_ALT_CH_DB_MODE_SEL0_ADDR(x) (REGS_IPU_BASE(x) + 0x168)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_ALT_CH_DB_MODE_SEL0(x) (*(volatile hw_ipu_alt_ch_db_mode_sel0_t *) HW_IPU_ALT_CH_DB_MODE_SEL0_ADDR(x))
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#define HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) (HW_IPU_ALT_CH_DB_MODE_SEL0(x).U)
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#define HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0(x).U = (v))
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#define HW_IPU_ALT_CH_DB_MODE_SEL0_SET(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) | (v)))
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#define HW_IPU_ALT_CH_DB_MODE_SEL0_CLR(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~(v)))
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#define HW_IPU_ALT_CH_DB_MODE_SEL0_TOG(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_ALT_CH_DB_MODE_SEL0 bitfields
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*/
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL0, field DMA_CH_ALT_DB_MODE_SEL_4[4] (RW)
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*
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* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - Double buffer is not used for this channel.
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* - 1 - Double buffer is used for this channel.
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*/
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//@{
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#define BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4 (4) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4.
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#define BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4 (0x00000010) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4 from a register value.
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#define BG_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4) >> BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4.
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#define BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_4 field to a new value.
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#define BW_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4) | BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_4(v)))
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#endif
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//@}
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL0, field DMA_CH_ALT_DB_MODE_SEL_5[5] (RW)
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*
|
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* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
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* Indicates the corresponding DMA channel number.
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|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
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* - 1 - Double buffer is used for this channel.
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|
*/
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|
//@{
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|
#define BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5 (5) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5.
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#define BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5 (0x00000020) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5 from a register value.
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#define BG_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5) >> BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5.
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#define BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_5 field to a new value.
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|
#define BW_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5) | BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_5(v)))
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#endif
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|
//@}
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL0, field DMA_CH_ALT_DB_MODE_SEL_6[6] (RW)
|
|
*
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* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
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|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
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|
* - 1 - Double buffer is used for this channel.
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|
*/
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|
//@{
|
|
#define BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6 (6) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6.
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#define BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6 (0x00000040) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6 from a register value.
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#define BG_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6) >> BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6.
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#define BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_6 field to a new value.
|
|
#define BW_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6) | BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_6(v)))
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#endif
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|
//@}
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL0, field DMA_CH_ALT_DB_MODE_SEL_7[7] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
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|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7 (7) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7.
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#define BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7 (0x00000080) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7 from a register value.
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|
#define BG_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7) >> BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7.
|
|
#define BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_7 field to a new value.
|
|
#define BW_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7) | BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_DB_MODE_SEL0, field DMA_CH_ALT_DB_MODE_SEL_24[24] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24 (24) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24.
|
|
#define BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24 (0x01000000) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24.
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|
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24 from a register value.
|
|
#define BG_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24) >> BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24)
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|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24.
|
|
#define BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_24 field to a new value.
|
|
#define BW_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24) | BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_DB_MODE_SEL0, field DMA_CH_ALT_DB_MODE_SEL_29[29] (RW)
|
|
*
|
|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29 (29) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29.
|
|
#define BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29 (0x20000000) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29.
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|
|
|
//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29 from a register value.
|
|
#define BG_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29) >> BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29.
|
|
#define BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29) & BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_29 field to a new value.
|
|
#define BW_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29) | BF_IPU_ALT_CH_DB_MODE_SEL0_DMA_CH_ALT_DB_MODE_SEL_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CH_DB_MODE_SEL1 - Alternate Channel Double Buffer Mode Select1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CH_DB_MODE_SEL1 - Alternate Channel Double Buffer Mode Select1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains double buffer mode select control information for 32 IPU's DMA channels.
|
|
*/
|
|
typedef union _hw_ipu_alt_ch_db_mode_sel1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_ch_db_mode_sel1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned DMA_CH_ALT_DB_MODE_SEL_33 : 1; //!< [1] Double Buffer Mode Select.
|
|
unsigned RESERVED1 : 7; //!< [8:2] Reserved.
|
|
unsigned DMA_CH_ALT_DB_MODE_SEL_41 : 1; //!< [9] Double Buffer Mode Select.
|
|
unsigned RESERVED2 : 10; //!< [19:10] Reserved.
|
|
unsigned DMA_CH_ALT_DB_MODE_SEL_52 : 1; //!< [20] Double Buffer Mode Select.
|
|
unsigned RESERVED3 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_ch_db_mode_sel1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CH_DB_MODE_SEL1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1_ADDR(x) (REGS_IPU_BASE(x) + 0x16c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1(x) (*(volatile hw_ipu_alt_ch_db_mode_sel1_t *) HW_IPU_ALT_CH_DB_MODE_SEL1_ADDR(x))
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) (HW_IPU_ALT_CH_DB_MODE_SEL1(x).U)
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1(x).U = (v))
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1_SET(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) | (v)))
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1_CLR(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) & ~(v)))
|
|
#define HW_IPU_ALT_CH_DB_MODE_SEL1_TOG(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CH_DB_MODE_SEL1 bitfields
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*/
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL1, field DMA_CH_ALT_DB_MODE_SEL_33[1] (RW)
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*
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* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
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|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
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|
* - 1 - Double buffer is used for this channel.
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|
*/
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//@{
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|
#define BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33 (1) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33.
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#define BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33 (0x00000002) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33 from a register value.
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#define BG_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33) >> BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33.
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#define BF_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33) & BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_33 field to a new value.
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|
#define BW_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33) | BF_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_33(v)))
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#endif
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//@}
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL1, field DMA_CH_ALT_DB_MODE_SEL_41[9] (RW)
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*
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* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
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|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
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|
* - 1 - Double buffer is used for this channel.
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|
*/
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|
//@{
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|
#define BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41 (9) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41.
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#define BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41 (0x00000200) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41 from a register value.
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#define BG_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41) >> BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41.
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#define BF_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41) & BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_41 field to a new value.
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|
#define BW_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41) | BF_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_41(v)))
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#endif
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|
//@}
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/*! @name Register IPU_ALT_CH_DB_MODE_SEL1, field DMA_CH_ALT_DB_MODE_SEL_52[20] (RW)
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|
*
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|
* Double Buffer Mode Select. This bit indicates if a double buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Double buffer is not used for this channel.
|
|
* - 1 - Double buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52 (20) //!< Bit position for IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52.
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|
#define BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52 (0x00100000) //!< Bit mask for IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52.
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//! @brief Get value of IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52 from a register value.
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|
#define BG_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52) >> BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52)
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//! @brief Format value for bitfield IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52.
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|
#define BF_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52) & BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_DB_MODE_SEL_52 field to a new value.
|
|
#define BW_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52(x, v) (HW_IPU_ALT_CH_DB_MODE_SEL1_WR(x, (HW_IPU_ALT_CH_DB_MODE_SEL1_RD(x) & ~BM_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52) | BF_IPU_ALT_CH_DB_MODE_SEL1_DMA_CH_ALT_DB_MODE_SEL_52(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CH_TRB_MODE_SEL0 - Alternate Channel Triple Buffer Mode Select 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CH_TRB_MODE_SEL0 - Alternate Channel Triple Buffer Mode Select 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains triple buffer mode select control information for 32 IPU's DMA channels.
|
|
* When the channel is configured for triple buffer mode. The double buffer mode settings configured
|
|
* on the corresponding DB_MODE_SEL bit are overridden. Hide VPU_SUB_FRAME_SYNC for all versions
|
|
* Show VPU_SUB_FRAME_SYNC for IPUv3H version. The table below tagged with other settings (like
|
|
* IPU3M_only) should be hidden in IPUv3H version. This requires some sophisticated conditional tag
|
|
* settings
|
|
*/
|
|
typedef union _hw_ipu_alt_ch_trb_mode_sel0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_ch_trb_mode_sel0_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved.
|
|
unsigned DMA_CH_TRB_MODE_SEL_8 : 1; //!< [8] Triple Buffer Mode Select.
|
|
unsigned DMA_CH_TRB_MODE_SEL_9 : 1; //!< [9] Triple Buffer Mode Select.
|
|
unsigned DMA_CH_TRB_MODE_SEL_10 : 1; //!< [10] Triple Buffer Mode Select.
|
|
unsigned RESERVED1 : 2; //!< [12:11] Reserved.
|
|
unsigned DMA_CH_TRB_MODE_SEL_13 : 1; //!< [13] Triple Buffer Mode Select.
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|
unsigned RESERVED2 : 7; //!< [20:14] Reserved.
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|
unsigned DMA_CH_TRB_MODE_SEL_21 : 1; //!< [21] Triple Buffer Mode Select.
|
|
unsigned RESERVED3 : 1; //!< [22] Reserved.
|
|
unsigned DMA_CH_TRB_MODE_SEL_23 : 1; //!< [23] Triple Buffer Mode Select.
|
|
unsigned RESERVED4 : 3; //!< [26:24] Reserved.
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|
unsigned DMA_CH_TRB_MODE_SEL_27 : 1; //!< [27] Triple Buffer Mode Select.
|
|
unsigned DMA_CH_TRB_MODE_SEL_28 : 1; //!< [28] Triple Buffer Mode Select.
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|
unsigned RESERVED5 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_ch_trb_mode_sel0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CH_TRB_MODE_SEL0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0_ADDR(x) (REGS_IPU_BASE(x) + 0x178)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0(x) (*(volatile hw_ipu_alt_ch_trb_mode_sel0_t *) HW_IPU_ALT_CH_TRB_MODE_SEL0_ADDR(x))
|
|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) (HW_IPU_ALT_CH_TRB_MODE_SEL0(x).U)
|
|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0(x).U = (v))
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|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0_SET(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) | (v)))
|
|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0_CLR(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~(v)))
|
|
#define HW_IPU_ALT_CH_TRB_MODE_SEL0_TOG(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CH_TRB_MODE_SEL0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_8[8] (RW)
|
|
*
|
|
* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Triple buffer is not used for this channel.
|
|
* - 1 - Triple buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8 (8) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8.
|
|
#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8 (0x00000100) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8.
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|
|
|
//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8 from a register value.
|
|
#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8.
|
|
#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_TRB_MODE_SEL_8 field to a new value.
|
|
#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_9[9] (RW)
|
|
*
|
|
* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Triple buffer is not used for this channel.
|
|
* - 1 - Triple buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9 (9) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9.
|
|
#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9 (0x00000200) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9.
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|
|
|
//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9 from a register value.
|
|
#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9.
|
|
#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_TRB_MODE_SEL_9 field to a new value.
|
|
#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_10[10] (RW)
|
|
*
|
|
* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Triple buffer is not used for this channel.
|
|
* - 1 - Triple buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10 (10) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10.
|
|
#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10 (0x00000400) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10 from a register value.
|
|
#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10.
|
|
#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_TRB_MODE_SEL_10 field to a new value.
|
|
#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_13[13] (RW)
|
|
*
|
|
* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Triple buffer is not used for this channel.
|
|
* - 1 - Triple buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13 (13) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13.
|
|
#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13 (0x00002000) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13 from a register value.
|
|
#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13.
|
|
#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_TRB_MODE_SEL_13 field to a new value.
|
|
#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_21[21] (RW)
|
|
*
|
|
* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Triple buffer is not used for this channel.
|
|
* - 1 - Triple buffer is used for this channel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21 (21) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21.
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|
#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21 (0x00200000) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21.
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//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21 from a register value.
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#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21)
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//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21.
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#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_TRB_MODE_SEL_21 field to a new value.
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#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_21(v)))
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#endif
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//@}
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/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_23[23] (RW)
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*
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* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - Triple buffer is not used for this channel.
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* - 1 - Triple buffer is used for this channel.
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*/
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//@{
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#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23 (23) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23.
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#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23 (0x00800000) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23.
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//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23 from a register value.
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#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23)
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//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23.
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#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_TRB_MODE_SEL_23 field to a new value.
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#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_23(v)))
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#endif
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//@}
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/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_27[27] (RW)
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*
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* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - Triple buffer is not used for this channel.
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* - 1 - Triple buffer is used for this channel.
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*/
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//@{
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#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27 (27) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27.
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#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27 (0x08000000) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27.
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//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27 from a register value.
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#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27)
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//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27.
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#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_TRB_MODE_SEL_27 field to a new value.
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#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_27(v)))
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#endif
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//@}
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/*! @name Register IPU_ALT_CH_TRB_MODE_SEL0, field DMA_CH_TRB_MODE_SEL_28[28] (RW)
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*
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* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
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* Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - Triple buffer is not used for this channel.
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* - 1 - Triple buffer is used for this channel.
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*/
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//@{
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#define BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28 (28) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28.
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#define BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28 (0x10000000) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28.
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//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28 from a register value.
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#define BG_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28) >> BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28)
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//! @brief Format value for bitfield IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28.
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#define BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28) & BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_TRB_MODE_SEL_28 field to a new value.
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#define BW_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL0_WR(x, (HW_IPU_ALT_CH_TRB_MODE_SEL0_RD(x) & ~BM_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28) | BF_IPU_ALT_CH_TRB_MODE_SEL0_DMA_CH_TRB_MODE_SEL_28(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_ALT_CH_TRB_MODE_SEL1 - Alternate Channel Triple Buffer Mode Select 1 Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_ALT_CH_TRB_MODE_SEL1 - Alternate Channel Triple Buffer Mode Select 1 Register (RW)
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*
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* Reset value: 0x00000000
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*
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* The register contains triple buffer mode select control information for 32 IPU's DMA channels.
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* When the channel is configured for triple buffer mode. The double buffer mode settings configured
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* on the corresponding DB_MODE_SEL bit are overridden.
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*/
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typedef union _hw_ipu_alt_ch_trb_mode_sel1
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{
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reg32_t U;
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struct _hw_ipu_alt_ch_trb_mode_sel1_bitfields
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{
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unsigned DMA_CH_TRB_MODE_SEL_N : 32; //!< [31:0] Triple Buffer Mode Select.
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} B;
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} hw_ipu_alt_ch_trb_mode_sel1_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_ALT_CH_TRB_MODE_SEL1 register
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*/
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//@{
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1_ADDR(x) (REGS_IPU_BASE(x) + 0x17c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1(x) (*(volatile hw_ipu_alt_ch_trb_mode_sel1_t *) HW_IPU_ALT_CH_TRB_MODE_SEL1_ADDR(x))
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1_RD(x) (HW_IPU_ALT_CH_TRB_MODE_SEL1(x).U)
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1_WR(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL1(x).U = (v))
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1_SET(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL1_WR(x, HW_IPU_ALT_CH_TRB_MODE_SEL1_RD(x) | (v)))
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1_CLR(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL1_WR(x, HW_IPU_ALT_CH_TRB_MODE_SEL1_RD(x) & ~(v)))
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#define HW_IPU_ALT_CH_TRB_MODE_SEL1_TOG(x, v) (HW_IPU_ALT_CH_TRB_MODE_SEL1_WR(x, HW_IPU_ALT_CH_TRB_MODE_SEL1_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
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* constants & macros for individual IPU_ALT_CH_TRB_MODE_SEL1 bitfields
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*/
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/*! @name Register IPU_ALT_CH_TRB_MODE_SEL1, field DMA_CH_TRB_MODE_SEL_N[31:0] (ROZ)
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*
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|
* Triple Buffer Mode Select. This bit indicates if a triple buffer is used for this channel. n
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|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Triple buffer is not used for this channel.
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* - 1 - Triple buffer is used for this channel.
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*/
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//@{
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|
#define BP_IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N (0) //!< Bit position for IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N.
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#define BM_IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N (0xffffffff) //!< Bit mask for IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N.
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//! @brief Get value of IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N from a register value.
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#define BG_IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N) >> BP_IPU_ALT_CH_TRB_MODE_SEL1_DMA_CH_TRB_MODE_SEL_N)
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_INT_STAT_1 - Interrupt Status Register 1
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|
//-------------------------------------------------------------------------------------------
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|
#ifndef __LANGUAGE_ASM__
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|
/*!
|
|
* @brief HW_IPU_INT_STAT_1 - Interrupt Status Register 1 (W1C)
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|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of EOF (end of frame) of DMA Channels
|
|
* interrupts [31:0] can be found in this register.
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|
*/
|
|
typedef union _hw_ipu_int_stat_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_1_bitfields
|
|
{
|
|
unsigned IDMAC_EOF_0 : 1; //!< [0] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_1 : 1; //!< [1] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_2 : 1; //!< [2] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_3 : 1; //!< [3] End of Frame of Channel interrupt.
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|
unsigned RESERVED0 : 1; //!< [4] Reserved.
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unsigned IDMAC_EOF_5 : 1; //!< [5] End of Frame of Channel interrupt.
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|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
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|
unsigned IDMAC_EOF_8 : 1; //!< [8] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_9 : 1; //!< [9] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_10 : 1; //!< [10] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_11 : 1; //!< [11] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_12 : 1; //!< [12] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_13 : 1; //!< [13] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_14 : 1; //!< [14] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_15 : 1; //!< [15] End of Frame of Channel interrupt.
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|
unsigned RESERVED2 : 1; //!< [16] Reserved.
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|
unsigned IDMAC_EOF_17 : 1; //!< [17] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_18 : 1; //!< [18] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_19 : 1; //!< [19] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_20 : 1; //!< [20] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_21 : 1; //!< [21] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_22 : 1; //!< [22] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_23 : 1; //!< [23] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_24 : 1; //!< [24] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_25 : 1; //!< [25] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_26 : 1; //!< [26] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_27 : 1; //!< [27] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_28 : 1; //!< [28] End of Frame of Channel interrupt.
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|
unsigned IDMAC_EOF_29 : 1; //!< [29] End of Frame of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_EOF_31 : 1; //!< [31] End of Frame of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_stat_1_t;
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|
#endif
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|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_1 register
|
|
*/
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|
//@{
|
|
#define HW_IPU_INT_STAT_1_ADDR(x) (REGS_IPU_BASE(x) + 0x200)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_1(x) (*(volatile hw_ipu_int_stat_1_t *) HW_IPU_INT_STAT_1_ADDR(x))
|
|
#define HW_IPU_INT_STAT_1_RD(x) (HW_IPU_INT_STAT_1(x).U)
|
|
#define HW_IPU_INT_STAT_1_WR(x, v) (HW_IPU_INT_STAT_1(x).U = (v))
|
|
#define HW_IPU_INT_STAT_1_SET(x, v) (HW_IPU_INT_STAT_1_WR(x, HW_IPU_INT_STAT_1_RD(x) | (v)))
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|
#define HW_IPU_INT_STAT_1_CLR(x, v) (HW_IPU_INT_STAT_1_WR(x, HW_IPU_INT_STAT_1_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_1_TOG(x, v) (HW_IPU_INT_STAT_1_WR(x, HW_IPU_INT_STAT_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_0[0] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_0 (0) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_0.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_0 (0x00000001) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_0.
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|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_0 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_0) >> BP_IPU_INT_STAT_1_IDMAC_EOF_0)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_0.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_0) & BM_IPU_INT_STAT_1_IDMAC_EOF_0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_0(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_0) | BF_IPU_INT_STAT_1_IDMAC_EOF_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_1[1] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_1 (1) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_1.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_1 (0x00000002) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_1 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_1) >> BP_IPU_INT_STAT_1_IDMAC_EOF_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_1.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_1) & BM_IPU_INT_STAT_1_IDMAC_EOF_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_1(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_1) | BF_IPU_INT_STAT_1_IDMAC_EOF_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_2[2] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_2 (2) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_2.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_2 (0x00000004) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_2.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_2 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_2) >> BP_IPU_INT_STAT_1_IDMAC_EOF_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_2.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_2) & BM_IPU_INT_STAT_1_IDMAC_EOF_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_2 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_2(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_2) | BF_IPU_INT_STAT_1_IDMAC_EOF_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_3[3] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_3 (3) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_3.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_3 (0x00000008) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_3.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_3 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_3) >> BP_IPU_INT_STAT_1_IDMAC_EOF_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_3.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_3) & BM_IPU_INT_STAT_1_IDMAC_EOF_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_3 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_3(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_3) | BF_IPU_INT_STAT_1_IDMAC_EOF_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_5[5] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_5 (5) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_5.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_5 (0x00000020) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_5.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_5 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_5) >> BP_IPU_INT_STAT_1_IDMAC_EOF_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_5.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_5) & BM_IPU_INT_STAT_1_IDMAC_EOF_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_5 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_5(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_5) | BF_IPU_INT_STAT_1_IDMAC_EOF_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_8[8] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_8 (8) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_8.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_8 (0x00000100) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_8.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_8 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_8) >> BP_IPU_INT_STAT_1_IDMAC_EOF_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_8.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_8) & BM_IPU_INT_STAT_1_IDMAC_EOF_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_8 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_8(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_8) | BF_IPU_INT_STAT_1_IDMAC_EOF_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_9[9] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_9 (9) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_9.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_9 (0x00000200) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_9.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_9 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_9) >> BP_IPU_INT_STAT_1_IDMAC_EOF_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_9.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_9) & BM_IPU_INT_STAT_1_IDMAC_EOF_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_9 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_9(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_9) | BF_IPU_INT_STAT_1_IDMAC_EOF_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_10[10] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_10 (10) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_10.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_10 (0x00000400) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_10.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_10 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_10) >> BP_IPU_INT_STAT_1_IDMAC_EOF_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_10.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_10) & BM_IPU_INT_STAT_1_IDMAC_EOF_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_10 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_10(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_10) | BF_IPU_INT_STAT_1_IDMAC_EOF_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_11[11] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_11 (11) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_11.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_11 (0x00000800) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_11.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_11 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_11) >> BP_IPU_INT_STAT_1_IDMAC_EOF_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_11.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_11) & BM_IPU_INT_STAT_1_IDMAC_EOF_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_11 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_11(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_11) | BF_IPU_INT_STAT_1_IDMAC_EOF_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_12[12] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_12 (12) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_12.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_12 (0x00001000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_12.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_12 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_12) >> BP_IPU_INT_STAT_1_IDMAC_EOF_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_12.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_12) & BM_IPU_INT_STAT_1_IDMAC_EOF_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_12 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_12(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_12) | BF_IPU_INT_STAT_1_IDMAC_EOF_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_13[13] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_13 (13) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_13.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_13 (0x00002000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_13.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_13 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_13) >> BP_IPU_INT_STAT_1_IDMAC_EOF_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_13.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_13) & BM_IPU_INT_STAT_1_IDMAC_EOF_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_13 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_13(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_13) | BF_IPU_INT_STAT_1_IDMAC_EOF_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_14[14] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_14 (14) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_14.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_14 (0x00004000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_14.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_14 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_14) >> BP_IPU_INT_STAT_1_IDMAC_EOF_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_14.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_14) & BM_IPU_INT_STAT_1_IDMAC_EOF_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_14 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_14(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_14) | BF_IPU_INT_STAT_1_IDMAC_EOF_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_15[15] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_15 (15) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_15.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_15 (0x00008000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_15.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_15 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_15) >> BP_IPU_INT_STAT_1_IDMAC_EOF_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_15.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_15) & BM_IPU_INT_STAT_1_IDMAC_EOF_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_15 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_15(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_15) | BF_IPU_INT_STAT_1_IDMAC_EOF_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_17[17] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_17 (17) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_17.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_17 (0x00020000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_17.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_17 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_17) >> BP_IPU_INT_STAT_1_IDMAC_EOF_17)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_17.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_17) & BM_IPU_INT_STAT_1_IDMAC_EOF_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_17 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_17(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_17) | BF_IPU_INT_STAT_1_IDMAC_EOF_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_18[18] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_18 (18) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_18.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_18 (0x00040000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_18.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_18 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_18) >> BP_IPU_INT_STAT_1_IDMAC_EOF_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_18.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_18) & BM_IPU_INT_STAT_1_IDMAC_EOF_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_18 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_18(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_18) | BF_IPU_INT_STAT_1_IDMAC_EOF_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_19[19] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_19 (19) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_19.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_19 (0x00080000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_19.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_19 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_19) >> BP_IPU_INT_STAT_1_IDMAC_EOF_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_19.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_19) & BM_IPU_INT_STAT_1_IDMAC_EOF_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_19 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_19(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_19) | BF_IPU_INT_STAT_1_IDMAC_EOF_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_20[20] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_20 (20) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_20.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_20 (0x00100000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_20.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_20 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_20) >> BP_IPU_INT_STAT_1_IDMAC_EOF_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_20.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_20) & BM_IPU_INT_STAT_1_IDMAC_EOF_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_20 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_20(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_20) | BF_IPU_INT_STAT_1_IDMAC_EOF_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_21[21] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_21 (21) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_21.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_21 (0x00200000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_21.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_21 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_21) >> BP_IPU_INT_STAT_1_IDMAC_EOF_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_21.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_21) & BM_IPU_INT_STAT_1_IDMAC_EOF_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_21 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_21(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_21) | BF_IPU_INT_STAT_1_IDMAC_EOF_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_22[22] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_22 (22) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_22.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_22 (0x00400000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_22.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_22 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_22) >> BP_IPU_INT_STAT_1_IDMAC_EOF_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_22.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_22) & BM_IPU_INT_STAT_1_IDMAC_EOF_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_22 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_22(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_22) | BF_IPU_INT_STAT_1_IDMAC_EOF_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_23[23] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_23 (23) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_23.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_23 (0x00800000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_23.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_23 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_23) >> BP_IPU_INT_STAT_1_IDMAC_EOF_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_23.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_23) & BM_IPU_INT_STAT_1_IDMAC_EOF_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_23 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_23(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_23) | BF_IPU_INT_STAT_1_IDMAC_EOF_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_24[24] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_24 (24) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_24.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_24 (0x01000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_24.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_24 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_24) >> BP_IPU_INT_STAT_1_IDMAC_EOF_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_24.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_24) & BM_IPU_INT_STAT_1_IDMAC_EOF_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_24 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_24(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_24) | BF_IPU_INT_STAT_1_IDMAC_EOF_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_25[25] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_25 (25) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_25.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_25 (0x02000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_25.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_25 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_25) >> BP_IPU_INT_STAT_1_IDMAC_EOF_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_25.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_25) & BM_IPU_INT_STAT_1_IDMAC_EOF_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_25 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_25(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_25) | BF_IPU_INT_STAT_1_IDMAC_EOF_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_26[26] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_26 (26) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_26.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_26 (0x04000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_26.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_26 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_26) >> BP_IPU_INT_STAT_1_IDMAC_EOF_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_26.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_26) & BM_IPU_INT_STAT_1_IDMAC_EOF_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_26 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_26(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_26) | BF_IPU_INT_STAT_1_IDMAC_EOF_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_27[27] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_27 (27) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_27.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_27 (0x08000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_27.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_27 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_27) >> BP_IPU_INT_STAT_1_IDMAC_EOF_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_27.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_27) & BM_IPU_INT_STAT_1_IDMAC_EOF_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_27 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_27(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_27) | BF_IPU_INT_STAT_1_IDMAC_EOF_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_28[28] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_28 (28) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_28.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_28 (0x10000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_28.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_28 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_28) >> BP_IPU_INT_STAT_1_IDMAC_EOF_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_28.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_28) & BM_IPU_INT_STAT_1_IDMAC_EOF_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_28 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_28(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_28) | BF_IPU_INT_STAT_1_IDMAC_EOF_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_29[29] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_29 (29) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_29.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_29 (0x20000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_29.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_29 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_29) >> BP_IPU_INT_STAT_1_IDMAC_EOF_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_29.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_29) & BM_IPU_INT_STAT_1_IDMAC_EOF_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_29 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_29(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_29) | BF_IPU_INT_STAT_1_IDMAC_EOF_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_1, field IDMAC_EOF_31[31] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_1_IDMAC_EOF_31 (31) //!< Bit position for IPU_INT_STAT_1_IDMAC_EOF_31.
|
|
#define BM_IPU_INT_STAT_1_IDMAC_EOF_31 (0x80000000) //!< Bit mask for IPU_INT_STAT_1_IDMAC_EOF_31.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_1_IDMAC_EOF_31 from a register value.
|
|
#define BG_IPU_INT_STAT_1_IDMAC_EOF_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_1_IDMAC_EOF_31) >> BP_IPU_INT_STAT_1_IDMAC_EOF_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_1_IDMAC_EOF_31.
|
|
#define BF_IPU_INT_STAT_1_IDMAC_EOF_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_1_IDMAC_EOF_31) & BM_IPU_INT_STAT_1_IDMAC_EOF_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_31 field to a new value.
|
|
#define BW_IPU_INT_STAT_1_IDMAC_EOF_31(x, v) (HW_IPU_INT_STAT_1_WR(x, (HW_IPU_INT_STAT_1_RD(x) & ~BM_IPU_INT_STAT_1_IDMAC_EOF_31) | BF_IPU_INT_STAT_1_IDMAC_EOF_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_2 - Interrupt Status Register2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_2 - Interrupt Status Register2 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of EOF (end of frame) of DMA Channels
|
|
* interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_EOF_33 : 1; //!< [1] End of Frame of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_EOF_40 : 1; //!< [8] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_41 : 1; //!< [9] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_42 : 1; //!< [10] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_43 : 1; //!< [11] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_44 : 1; //!< [12] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_45 : 1; //!< [13] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_46 : 1; //!< [14] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_47 : 1; //!< [15] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_48 : 1; //!< [16] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_49 : 1; //!< [17] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_50 : 1; //!< [18] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_51 : 1; //!< [19] End of Frame of Channel interrupt.
|
|
unsigned IDMAC_EOF_52 : 1; //!< [20] End of Frame of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_2_ADDR(x) (REGS_IPU_BASE(x) + 0x204)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_2(x) (*(volatile hw_ipu_int_stat_2_t *) HW_IPU_INT_STAT_2_ADDR(x))
|
|
#define HW_IPU_INT_STAT_2_RD(x) (HW_IPU_INT_STAT_2(x).U)
|
|
#define HW_IPU_INT_STAT_2_WR(x, v) (HW_IPU_INT_STAT_2(x).U = (v))
|
|
#define HW_IPU_INT_STAT_2_SET(x, v) (HW_IPU_INT_STAT_2_WR(x, HW_IPU_INT_STAT_2_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_2_CLR(x, v) (HW_IPU_INT_STAT_2_WR(x, HW_IPU_INT_STAT_2_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_2_TOG(x, v) (HW_IPU_INT_STAT_2_WR(x, HW_IPU_INT_STAT_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_33[1] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_33 (1) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_33.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_33 (0x00000002) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_33.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_33 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_33) >> BP_IPU_INT_STAT_2_IDMAC_EOF_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_33.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_33) & BM_IPU_INT_STAT_2_IDMAC_EOF_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_33 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_33(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_33) | BF_IPU_INT_STAT_2_IDMAC_EOF_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_40[8] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_40 (8) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_40.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_40 (0x00000100) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_40.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_40 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_40) >> BP_IPU_INT_STAT_2_IDMAC_EOF_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_40.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_40) & BM_IPU_INT_STAT_2_IDMAC_EOF_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_40 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_40(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_40) | BF_IPU_INT_STAT_2_IDMAC_EOF_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_41[9] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_41 (9) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_41.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_41 (0x00000200) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_41.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_41 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_41) >> BP_IPU_INT_STAT_2_IDMAC_EOF_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_41.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_41) & BM_IPU_INT_STAT_2_IDMAC_EOF_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_41 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_41(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_41) | BF_IPU_INT_STAT_2_IDMAC_EOF_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_42[10] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_42 (10) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_42.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_42 (0x00000400) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_42.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_42 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_42) >> BP_IPU_INT_STAT_2_IDMAC_EOF_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_42.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_42) & BM_IPU_INT_STAT_2_IDMAC_EOF_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_42 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_42(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_42) | BF_IPU_INT_STAT_2_IDMAC_EOF_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_43[11] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_43 (11) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_43.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_43 (0x00000800) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_43.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_43 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_43) >> BP_IPU_INT_STAT_2_IDMAC_EOF_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_43.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_43) & BM_IPU_INT_STAT_2_IDMAC_EOF_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_43 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_43(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_43) | BF_IPU_INT_STAT_2_IDMAC_EOF_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_44[12] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_44 (12) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_44.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_44 (0x00001000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_44.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_44 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_44) >> BP_IPU_INT_STAT_2_IDMAC_EOF_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_44.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_44) & BM_IPU_INT_STAT_2_IDMAC_EOF_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_44 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_44(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_44) | BF_IPU_INT_STAT_2_IDMAC_EOF_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_45[13] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_45 (13) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_45.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_45 (0x00002000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_45.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_45 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_45) >> BP_IPU_INT_STAT_2_IDMAC_EOF_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_45.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_45) & BM_IPU_INT_STAT_2_IDMAC_EOF_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_45 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_45(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_45) | BF_IPU_INT_STAT_2_IDMAC_EOF_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_46[14] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_46 (14) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_46.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_46 (0x00004000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_46.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_46 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_46) >> BP_IPU_INT_STAT_2_IDMAC_EOF_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_46.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_46) & BM_IPU_INT_STAT_2_IDMAC_EOF_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_46 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_46(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_46) | BF_IPU_INT_STAT_2_IDMAC_EOF_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_47[15] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_47 (15) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_47.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_47 (0x00008000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_47.
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|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_47 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_47) >> BP_IPU_INT_STAT_2_IDMAC_EOF_47)
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|
|
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//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_47.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_47) & BM_IPU_INT_STAT_2_IDMAC_EOF_47)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_47 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_47(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_47) | BF_IPU_INT_STAT_2_IDMAC_EOF_47(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_48[16] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_48 (16) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_48.
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#define BM_IPU_INT_STAT_2_IDMAC_EOF_48 (0x00010000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_48.
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//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_48 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_48) >> BP_IPU_INT_STAT_2_IDMAC_EOF_48)
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//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_48.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_48) & BM_IPU_INT_STAT_2_IDMAC_EOF_48)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_48 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_48(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_48) | BF_IPU_INT_STAT_2_IDMAC_EOF_48(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_49[17] (W1C)
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*
|
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* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
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|
* - 1 - Interrupt is requested.
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|
*/
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|
//@{
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|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_49 (17) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_49.
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#define BM_IPU_INT_STAT_2_IDMAC_EOF_49 (0x00020000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_49.
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//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_49 from a register value.
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|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_49) >> BP_IPU_INT_STAT_2_IDMAC_EOF_49)
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//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_49.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_49) & BM_IPU_INT_STAT_2_IDMAC_EOF_49)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_49 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_49(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_49) | BF_IPU_INT_STAT_2_IDMAC_EOF_49(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_50[18] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_50 (18) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_50.
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|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_50 (0x00040000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_50.
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|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_50 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_50) >> BP_IPU_INT_STAT_2_IDMAC_EOF_50)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_50.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_50) & BM_IPU_INT_STAT_2_IDMAC_EOF_50)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_50 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_50(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_50) | BF_IPU_INT_STAT_2_IDMAC_EOF_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_51[19] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_51 (19) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_51.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_51 (0x00080000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_51.
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|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_51 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_51) >> BP_IPU_INT_STAT_2_IDMAC_EOF_51)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_51.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_51) & BM_IPU_INT_STAT_2_IDMAC_EOF_51)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_51 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_51(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_51) | BF_IPU_INT_STAT_2_IDMAC_EOF_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_2, field IDMAC_EOF_52[20] (W1C)
|
|
*
|
|
* End of Frame of Channel interrupt. This bit is the status bit of End Of Frame of Channel #n. n
|
|
* Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_2_IDMAC_EOF_52 (20) //!< Bit position for IPU_INT_STAT_2_IDMAC_EOF_52.
|
|
#define BM_IPU_INT_STAT_2_IDMAC_EOF_52 (0x00100000) //!< Bit mask for IPU_INT_STAT_2_IDMAC_EOF_52.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_2_IDMAC_EOF_52 from a register value.
|
|
#define BG_IPU_INT_STAT_2_IDMAC_EOF_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_2_IDMAC_EOF_52) >> BP_IPU_INT_STAT_2_IDMAC_EOF_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_2_IDMAC_EOF_52.
|
|
#define BF_IPU_INT_STAT_2_IDMAC_EOF_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_2_IDMAC_EOF_52) & BM_IPU_INT_STAT_2_IDMAC_EOF_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOF_52 field to a new value.
|
|
#define BW_IPU_INT_STAT_2_IDMAC_EOF_52(x, v) (HW_IPU_INT_STAT_2_WR(x, (HW_IPU_INT_STAT_2_RD(x) & ~BM_IPU_INT_STAT_2_IDMAC_EOF_52) | BF_IPU_INT_STAT_2_IDMAC_EOF_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_3 - Interrupt Status Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_3 - Interrupt Status Register 3 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of NFACK (New Frame Ack) of DMA Channels
|
|
* interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_3_bitfields
|
|
{
|
|
unsigned IDMAC_NFACK_0 : 1; //!< [0] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_1 : 1; //!< [1] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_2 : 1; //!< [2] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_3 : 1; //!< [3] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_NFACK_5 : 1; //!< [5] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_NFACK_8 : 1; //!< [8] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_9 : 1; //!< [9] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_10 : 1; //!< [10] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_11 : 1; //!< [11] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_12 : 1; //!< [12] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_13 : 1; //!< [13] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_14 : 1; //!< [14] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_15 : 1; //!< [15] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_NFACK_17 : 1; //!< [17] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_18 : 1; //!< [18] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_19 : 1; //!< [19] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_20 : 1; //!< [20] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_21 : 1; //!< [21] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_22 : 1; //!< [22] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_23 : 1; //!< [23] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_24 : 1; //!< [24] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_25 : 1; //!< [25] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_26 : 1; //!< [26] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_27 : 1; //!< [27] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_28 : 1; //!< [28] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_29 : 1; //!< [29] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_NFACK_31 : 1; //!< [31] Enable New Frame Ack of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_stat_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_3_ADDR(x) (REGS_IPU_BASE(x) + 0x208)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_3(x) (*(volatile hw_ipu_int_stat_3_t *) HW_IPU_INT_STAT_3_ADDR(x))
|
|
#define HW_IPU_INT_STAT_3_RD(x) (HW_IPU_INT_STAT_3(x).U)
|
|
#define HW_IPU_INT_STAT_3_WR(x, v) (HW_IPU_INT_STAT_3(x).U = (v))
|
|
#define HW_IPU_INT_STAT_3_SET(x, v) (HW_IPU_INT_STAT_3_WR(x, HW_IPU_INT_STAT_3_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_3_CLR(x, v) (HW_IPU_INT_STAT_3_WR(x, HW_IPU_INT_STAT_3_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_3_TOG(x, v) (HW_IPU_INT_STAT_3_WR(x, HW_IPU_INT_STAT_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_0[0] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_0 (0) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_0.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_0 (0x00000001) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_0 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_0) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_0.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_0) & BM_IPU_INT_STAT_3_IDMAC_NFACK_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_0(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_0) | BF_IPU_INT_STAT_3_IDMAC_NFACK_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_1[1] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_1 (1) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_1.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_1 (0x00000002) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_1 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_1) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_1.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_1) & BM_IPU_INT_STAT_3_IDMAC_NFACK_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_1(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_1) | BF_IPU_INT_STAT_3_IDMAC_NFACK_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_2[2] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_2 (2) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_2.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_2 (0x00000004) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_2.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_2 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_2) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_2.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_2) & BM_IPU_INT_STAT_3_IDMAC_NFACK_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_2 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_2(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_2) | BF_IPU_INT_STAT_3_IDMAC_NFACK_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_3[3] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_3 (3) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_3.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_3 (0x00000008) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_3.
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|
|
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_3 from a register value.
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|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_3) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_3)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_3.
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|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_3) & BM_IPU_INT_STAT_3_IDMAC_NFACK_3)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_3 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_3(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_3) | BF_IPU_INT_STAT_3_IDMAC_NFACK_3(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_5[5] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_5 (5) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_5.
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#define BM_IPU_INT_STAT_3_IDMAC_NFACK_5 (0x00000020) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_5.
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_5 from a register value.
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|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_5) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_5)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_5.
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#define BF_IPU_INT_STAT_3_IDMAC_NFACK_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_5) & BM_IPU_INT_STAT_3_IDMAC_NFACK_5)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFACK_5 field to a new value.
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|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_5(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_5) | BF_IPU_INT_STAT_3_IDMAC_NFACK_5(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_8[8] (W1C)
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*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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|
//@{
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|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_8 (8) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_8.
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#define BM_IPU_INT_STAT_3_IDMAC_NFACK_8 (0x00000100) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_8.
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_8 from a register value.
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|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_8) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_8)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_8.
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|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_8) & BM_IPU_INT_STAT_3_IDMAC_NFACK_8)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_8 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_8(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_8) | BF_IPU_INT_STAT_3_IDMAC_NFACK_8(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_9[9] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_9 (9) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_9.
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|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_9 (0x00000200) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_9.
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|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_9 from a register value.
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|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_9) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_9)
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|
|
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_9.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_9) & BM_IPU_INT_STAT_3_IDMAC_NFACK_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_9 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_9(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_9) | BF_IPU_INT_STAT_3_IDMAC_NFACK_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_10[10] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_10 (10) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_10.
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|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_10 (0x00000400) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_10.
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|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_10 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_10) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_10)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_10.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_10) & BM_IPU_INT_STAT_3_IDMAC_NFACK_10)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_10 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_10(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_10) | BF_IPU_INT_STAT_3_IDMAC_NFACK_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_11[11] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_11 (11) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_11.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_11 (0x00000800) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_11.
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|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_11 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_11) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_11.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_11) & BM_IPU_INT_STAT_3_IDMAC_NFACK_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_11 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_11(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_11) | BF_IPU_INT_STAT_3_IDMAC_NFACK_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_12[12] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_12 (12) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_12.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_12 (0x00001000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_12.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_12 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_12) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_12.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_12) & BM_IPU_INT_STAT_3_IDMAC_NFACK_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_12 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_12(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_12) | BF_IPU_INT_STAT_3_IDMAC_NFACK_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_13[13] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_13 (13) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_13.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_13 (0x00002000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_13.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_13 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_13) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_13.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_13) & BM_IPU_INT_STAT_3_IDMAC_NFACK_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_13 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_13(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_13) | BF_IPU_INT_STAT_3_IDMAC_NFACK_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_14[14] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_14 (14) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_14.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_14 (0x00004000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_14.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_14 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_14) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_14.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_14) & BM_IPU_INT_STAT_3_IDMAC_NFACK_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_14 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_14(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_14) | BF_IPU_INT_STAT_3_IDMAC_NFACK_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_15[15] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_15 (15) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_15.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_15 (0x00008000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_15.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_15 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_15) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_15.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_15) & BM_IPU_INT_STAT_3_IDMAC_NFACK_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_15 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_15(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_15) | BF_IPU_INT_STAT_3_IDMAC_NFACK_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_17[17] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_17 (17) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_17.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_17 (0x00020000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_17.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_17 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_17) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_17)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_17.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_17) & BM_IPU_INT_STAT_3_IDMAC_NFACK_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_17 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_17(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_17) | BF_IPU_INT_STAT_3_IDMAC_NFACK_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_18[18] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_18 (18) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_18.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_18 (0x00040000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_18.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_18 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_18) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_18.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_18) & BM_IPU_INT_STAT_3_IDMAC_NFACK_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
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//! @brief Set the IDMAC_NFACK_18 field to a new value.
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#define BW_IPU_INT_STAT_3_IDMAC_NFACK_18(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_18) | BF_IPU_INT_STAT_3_IDMAC_NFACK_18(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_19[19] (W1C)
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*
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* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
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|
* Channel #n. n Indicates the corresponding DMA channel number.
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|
*
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* Values:
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|
* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_3_IDMAC_NFACK_19 (19) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_19.
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#define BM_IPU_INT_STAT_3_IDMAC_NFACK_19 (0x00080000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_19.
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_19 from a register value.
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#define BG_IPU_INT_STAT_3_IDMAC_NFACK_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_19) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_19)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_19.
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#define BF_IPU_INT_STAT_3_IDMAC_NFACK_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_19) & BM_IPU_INT_STAT_3_IDMAC_NFACK_19)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_19 field to a new value.
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#define BW_IPU_INT_STAT_3_IDMAC_NFACK_19(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_19) | BF_IPU_INT_STAT_3_IDMAC_NFACK_19(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_20[20] (W1C)
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*
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* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
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* Channel #n. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_3_IDMAC_NFACK_20 (20) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_20.
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#define BM_IPU_INT_STAT_3_IDMAC_NFACK_20 (0x00100000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_20.
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_20 from a register value.
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#define BG_IPU_INT_STAT_3_IDMAC_NFACK_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_20) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_20)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_20.
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#define BF_IPU_INT_STAT_3_IDMAC_NFACK_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_20) & BM_IPU_INT_STAT_3_IDMAC_NFACK_20)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_20 field to a new value.
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#define BW_IPU_INT_STAT_3_IDMAC_NFACK_20(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_20) | BF_IPU_INT_STAT_3_IDMAC_NFACK_20(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_21[21] (W1C)
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*
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* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
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*
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* Values:
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* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_3_IDMAC_NFACK_21 (21) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_21.
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#define BM_IPU_INT_STAT_3_IDMAC_NFACK_21 (0x00200000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_21.
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_21 from a register value.
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#define BG_IPU_INT_STAT_3_IDMAC_NFACK_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_21) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_21)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_21.
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#define BF_IPU_INT_STAT_3_IDMAC_NFACK_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_21) & BM_IPU_INT_STAT_3_IDMAC_NFACK_21)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_NFACK_21 field to a new value.
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#define BW_IPU_INT_STAT_3_IDMAC_NFACK_21(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_21) | BF_IPU_INT_STAT_3_IDMAC_NFACK_21(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_22[22] (W1C)
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*
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|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
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|
* - 1 - Interrupt is requested.
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|
*/
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//@{
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#define BP_IPU_INT_STAT_3_IDMAC_NFACK_22 (22) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_22.
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#define BM_IPU_INT_STAT_3_IDMAC_NFACK_22 (0x00400000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_22.
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//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_22 from a register value.
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#define BG_IPU_INT_STAT_3_IDMAC_NFACK_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_22) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_22)
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//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_22.
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|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_22) & BM_IPU_INT_STAT_3_IDMAC_NFACK_22)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFACK_22 field to a new value.
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|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_22(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_22) | BF_IPU_INT_STAT_3_IDMAC_NFACK_22(v)))
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|
#endif
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|
//@}
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|
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/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_23[23] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
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|
*/
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|
//@{
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|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_23 (23) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_23.
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|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_23 (0x00800000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_23.
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|
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|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_23 from a register value.
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|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_23) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_23)
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|
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|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_23.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_23) & BM_IPU_INT_STAT_3_IDMAC_NFACK_23)
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|
|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFACK_23 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_23(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_23) | BF_IPU_INT_STAT_3_IDMAC_NFACK_23(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_24[24] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_24 (24) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_24.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_24 (0x01000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_24.
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|
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|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_24 from a register value.
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|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_24) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_24)
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|
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|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_24.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_24) & BM_IPU_INT_STAT_3_IDMAC_NFACK_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_24 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_24(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_24) | BF_IPU_INT_STAT_3_IDMAC_NFACK_24(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_25[25] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_25 (25) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_25.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_25 (0x02000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_25.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_25 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_25) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_25.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_25) & BM_IPU_INT_STAT_3_IDMAC_NFACK_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_25 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_25(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_25) | BF_IPU_INT_STAT_3_IDMAC_NFACK_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_26[26] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_26 (26) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_26.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_26 (0x04000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_26.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_26 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_26) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_26.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_26) & BM_IPU_INT_STAT_3_IDMAC_NFACK_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_26 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_26(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_26) | BF_IPU_INT_STAT_3_IDMAC_NFACK_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_27[27] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_27 (27) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_27.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_27 (0x08000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_27.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_27 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_27) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_27.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_27) & BM_IPU_INT_STAT_3_IDMAC_NFACK_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_27 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_27(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_27) | BF_IPU_INT_STAT_3_IDMAC_NFACK_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_28[28] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_28 (28) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_28.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_28 (0x10000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_28.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_28 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_28) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_28.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_28) & BM_IPU_INT_STAT_3_IDMAC_NFACK_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_28 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_28(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_28) | BF_IPU_INT_STAT_3_IDMAC_NFACK_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_29[29] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_29 (29) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_29.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_29 (0x20000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_29.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_29 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_29) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_29.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_29) & BM_IPU_INT_STAT_3_IDMAC_NFACK_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_29 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_29(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_29) | BF_IPU_INT_STAT_3_IDMAC_NFACK_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_3, field IDMAC_NFACK_31[31] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_3_IDMAC_NFACK_31 (31) //!< Bit position for IPU_INT_STAT_3_IDMAC_NFACK_31.
|
|
#define BM_IPU_INT_STAT_3_IDMAC_NFACK_31 (0x80000000) //!< Bit mask for IPU_INT_STAT_3_IDMAC_NFACK_31.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_3_IDMAC_NFACK_31 from a register value.
|
|
#define BG_IPU_INT_STAT_3_IDMAC_NFACK_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_3_IDMAC_NFACK_31) >> BP_IPU_INT_STAT_3_IDMAC_NFACK_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_3_IDMAC_NFACK_31.
|
|
#define BF_IPU_INT_STAT_3_IDMAC_NFACK_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_3_IDMAC_NFACK_31) & BM_IPU_INT_STAT_3_IDMAC_NFACK_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_31 field to a new value.
|
|
#define BW_IPU_INT_STAT_3_IDMAC_NFACK_31(x, v) (HW_IPU_INT_STAT_3_WR(x, (HW_IPU_INT_STAT_3_RD(x) & ~BM_IPU_INT_STAT_3_IDMAC_NFACK_31) | BF_IPU_INT_STAT_3_IDMAC_NFACK_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_4 - Interrupt Status Register 4
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_4 - Interrupt Status Register 4 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of NFACK (New Frame Ack) of DMA Channels
|
|
* interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_4_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_NFACK_33 : 1; //!< [1] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_NFACK_40 : 1; //!< [8] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_41 : 1; //!< [9] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_42 : 1; //!< [10] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_43 : 1; //!< [11] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_44 : 1; //!< [12] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_45 : 1; //!< [13] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_46 : 1; //!< [14] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_47 : 1; //!< [15] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_48 : 1; //!< [16] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_49 : 1; //!< [17] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_50 : 1; //!< [18] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_51 : 1; //!< [19] Enable New Frame Ack of Channel interrupt.
|
|
unsigned IDMAC_NFACK_52 : 1; //!< [20] Enable New Frame Ack of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_4_ADDR(x) (REGS_IPU_BASE(x) + 0x20c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_4(x) (*(volatile hw_ipu_int_stat_4_t *) HW_IPU_INT_STAT_4_ADDR(x))
|
|
#define HW_IPU_INT_STAT_4_RD(x) (HW_IPU_INT_STAT_4(x).U)
|
|
#define HW_IPU_INT_STAT_4_WR(x, v) (HW_IPU_INT_STAT_4(x).U = (v))
|
|
#define HW_IPU_INT_STAT_4_SET(x, v) (HW_IPU_INT_STAT_4_WR(x, HW_IPU_INT_STAT_4_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_4_CLR(x, v) (HW_IPU_INT_STAT_4_WR(x, HW_IPU_INT_STAT_4_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_4_TOG(x, v) (HW_IPU_INT_STAT_4_WR(x, HW_IPU_INT_STAT_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_33[1] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_33 (1) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_33.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_33 (0x00000002) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_33.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_33 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_33) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_33.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_33) & BM_IPU_INT_STAT_4_IDMAC_NFACK_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_33 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_33(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_33) | BF_IPU_INT_STAT_4_IDMAC_NFACK_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_40[8] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_40 (8) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_40.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_40 (0x00000100) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_40.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_40 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_40) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_40.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_40) & BM_IPU_INT_STAT_4_IDMAC_NFACK_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_40 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_40(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_40) | BF_IPU_INT_STAT_4_IDMAC_NFACK_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_41[9] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_41 (9) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_41.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_41 (0x00000200) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_41.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_41 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_41) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_41.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_41) & BM_IPU_INT_STAT_4_IDMAC_NFACK_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_41 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_41(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_41) | BF_IPU_INT_STAT_4_IDMAC_NFACK_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_42[10] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_42 (10) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_42.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_42 (0x00000400) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_42.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_42 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_42) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_42.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_42) & BM_IPU_INT_STAT_4_IDMAC_NFACK_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_42 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_42(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_42) | BF_IPU_INT_STAT_4_IDMAC_NFACK_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_43[11] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_43 (11) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_43.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_43 (0x00000800) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_43.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_43 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_43) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_43.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_43) & BM_IPU_INT_STAT_4_IDMAC_NFACK_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_43 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_43(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_43) | BF_IPU_INT_STAT_4_IDMAC_NFACK_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_44[12] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_44 (12) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_44.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_44 (0x00001000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_44.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_44 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_44) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_44.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_44) & BM_IPU_INT_STAT_4_IDMAC_NFACK_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_44 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_44(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_44) | BF_IPU_INT_STAT_4_IDMAC_NFACK_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_45[13] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_45 (13) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_45.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_45 (0x00002000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_45.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_45 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_45) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_45.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_45) & BM_IPU_INT_STAT_4_IDMAC_NFACK_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_45 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_45(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_45) | BF_IPU_INT_STAT_4_IDMAC_NFACK_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_46[14] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_46 (14) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_46.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_46 (0x00004000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_46.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_46 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_46) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_46.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_46) & BM_IPU_INT_STAT_4_IDMAC_NFACK_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_46 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_46(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_46) | BF_IPU_INT_STAT_4_IDMAC_NFACK_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_47[15] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_47 (15) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_47.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_47 (0x00008000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_47.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_47 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_47) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_47.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_47) & BM_IPU_INT_STAT_4_IDMAC_NFACK_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_47 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_47(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_47) | BF_IPU_INT_STAT_4_IDMAC_NFACK_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_48[16] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_48 (16) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_48.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_48 (0x00010000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_48.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_48 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_48) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_48)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_48.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_48) & BM_IPU_INT_STAT_4_IDMAC_NFACK_48)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_48 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_48(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_48) | BF_IPU_INT_STAT_4_IDMAC_NFACK_48(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_49[17] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_49 (17) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_49.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_49 (0x00020000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_49.
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|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_49 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_49) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_49)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_49.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_49) & BM_IPU_INT_STAT_4_IDMAC_NFACK_49)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_49 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_49(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_49) | BF_IPU_INT_STAT_4_IDMAC_NFACK_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_50[18] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_50 (18) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_50.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_50 (0x00040000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_50.
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|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_50 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_50) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_50.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_50) & BM_IPU_INT_STAT_4_IDMAC_NFACK_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_50 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_50(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_50) | BF_IPU_INT_STAT_4_IDMAC_NFACK_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_51[19] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_51 (19) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_51.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_51 (0x00080000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_51.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_51 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_51) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_51.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_51) & BM_IPU_INT_STAT_4_IDMAC_NFACK_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_51 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_51(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_51) | BF_IPU_INT_STAT_4_IDMAC_NFACK_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_4, field IDMAC_NFACK_52[20] (W1C)
|
|
*
|
|
* Enable New Frame Ack of Channel interrupt. This bit is the status bits of New Frame Ack of
|
|
* Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_4_IDMAC_NFACK_52 (20) //!< Bit position for IPU_INT_STAT_4_IDMAC_NFACK_52.
|
|
#define BM_IPU_INT_STAT_4_IDMAC_NFACK_52 (0x00100000) //!< Bit mask for IPU_INT_STAT_4_IDMAC_NFACK_52.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_4_IDMAC_NFACK_52 from a register value.
|
|
#define BG_IPU_INT_STAT_4_IDMAC_NFACK_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_4_IDMAC_NFACK_52) >> BP_IPU_INT_STAT_4_IDMAC_NFACK_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_4_IDMAC_NFACK_52.
|
|
#define BF_IPU_INT_STAT_4_IDMAC_NFACK_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_4_IDMAC_NFACK_52) & BM_IPU_INT_STAT_4_IDMAC_NFACK_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFACK_52 field to a new value.
|
|
#define BW_IPU_INT_STAT_4_IDMAC_NFACK_52(x, v) (HW_IPU_INT_STAT_4_WR(x, (HW_IPU_INT_STAT_4_RD(x) & ~BM_IPU_INT_STAT_4_IDMAC_NFACK_52) | BF_IPU_INT_STAT_4_IDMAC_NFACK_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_5 - Interrupt Status Register 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_5 - Interrupt Status Register 5 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the New-frame before end-of-frame
|
|
* indication (NFB4EOF_ERR) of DMA Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_5_bitfields
|
|
{
|
|
unsigned IDMAC_NFB4EOF_ERR_0 : 1; //!< [0] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_1 : 1; //!< [1] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_2 : 1; //!< [2] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_3 : 1; //!< [3] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_NFB4EOF_ERR_5 : 1; //!< [5] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_NFB4EOF_ERR_8 : 1; //!< [8] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_9 : 1; //!< [9] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_10 : 1; //!< [10] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_11 : 1; //!< [11] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_12 : 1; //!< [12] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_13 : 1; //!< [13] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_14 : 1; //!< [14] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_15 : 1; //!< [15] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_NFB4EOF_ERR_17 : 1; //!< [17] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_18 : 1; //!< [18] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_19 : 1; //!< [19] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_20 : 1; //!< [20] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_21 : 1; //!< [21] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_22 : 1; //!< [22] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_23 : 1; //!< [23] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_24 : 1; //!< [24] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_25 : 1; //!< [25] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_26 : 1; //!< [26] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_27 : 1; //!< [27] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_28 : 1; //!< [28] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_29 : 1; //!< [29] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_NFB4EOF_ERR_31 : 1; //!< [31] New Frame before end-of-frame error indication of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_stat_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_5_ADDR(x) (REGS_IPU_BASE(x) + 0x210)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_5(x) (*(volatile hw_ipu_int_stat_5_t *) HW_IPU_INT_STAT_5_ADDR(x))
|
|
#define HW_IPU_INT_STAT_5_RD(x) (HW_IPU_INT_STAT_5(x).U)
|
|
#define HW_IPU_INT_STAT_5_WR(x, v) (HW_IPU_INT_STAT_5(x).U = (v))
|
|
#define HW_IPU_INT_STAT_5_SET(x, v) (HW_IPU_INT_STAT_5_WR(x, HW_IPU_INT_STAT_5_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_5_CLR(x, v) (HW_IPU_INT_STAT_5_WR(x, HW_IPU_INT_STAT_5_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_5_TOG(x, v) (HW_IPU_INT_STAT_5_WR(x, HW_IPU_INT_STAT_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_0[0] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0 (0) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0 (0x00000001) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_1[1] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1 (1) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1 (0x00000002) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_2[2] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2 (2) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2 (0x00000004) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_2 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_2(v)))
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#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_3[3] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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//@{
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|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3 (3) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3.
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#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3 (0x00000008) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3.
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//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3 from a register value.
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#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3)
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//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3.
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#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_NFB4EOF_ERR_3 field to a new value.
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#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_3(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_5[5] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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//@{
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#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5 (5) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5.
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#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5 (0x00000020) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5.
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//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5 from a register value.
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#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5)
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//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5.
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|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5)
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|
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_5 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_5(v)))
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|
#endif
|
|
//@}
|
|
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/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_8[8] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8 (8) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8.
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#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8 (0x00000100) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8.
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|
|
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//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_8 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_9[9] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9 (9) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9 (0x00000200) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_9 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_10[10] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10 (10) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10 (0x00000400) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_10 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_11[11] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11 (11) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11 (0x00000800) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_11 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_12[12] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12 (12) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12 (0x00001000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_12 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_13[13] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13 (13) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13 (0x00002000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_13 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_14[14] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14 (14) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14 (0x00004000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_14 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_15[15] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15 (15) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15 (0x00008000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_15 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_17[17] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17 (17) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17 (0x00020000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_17 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_18[18] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18 (18) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18 (0x00040000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_18 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_19[19] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19 (19) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19 (0x00080000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_19 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_20[20] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20 (20) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20 (0x00100000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_20 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_21[21] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21 (21) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21 (0x00200000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_21 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_22[22] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22 (22) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22 (0x00400000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_22 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_23[23] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23 (23) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23 (0x00800000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_23 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_24[24] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24 (24) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24 (0x01000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_24 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_25[25] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25 (25) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25 (0x02000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_25 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_26[26] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26 (26) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26 (0x04000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_26 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_27[27] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27 (27) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27.
|
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#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27 (0x08000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27.
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|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27)
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|
|
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//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_27 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_28[28] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28 (28) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28.
|
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#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28 (0x10000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28.
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|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28)
|
|
|
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//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_28 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_29[29] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29 (29) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29 (0x20000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_29 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_5, field IDMAC_NFB4EOF_ERR_31[31] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31 (31) //!< Bit position for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31.
|
|
#define BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31 (0x80000000) //!< Bit mask for IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31 from a register value.
|
|
#define BG_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31) >> BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31.
|
|
#define BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31) & BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_31 field to a new value.
|
|
#define BW_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31(x, v) (HW_IPU_INT_STAT_5_WR(x, (HW_IPU_INT_STAT_5_RD(x) & ~BM_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31) | BF_IPU_INT_STAT_5_IDMAC_NFB4EOF_ERR_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_6 - Interrupt Status Register 6
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_6 - Interrupt Status Register 6 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the New-frame before end-of-frame
|
|
* indication (NFB4EOF_ERR) of DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_6_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_NFB4EOF_ERR_33 : 1; //!< [1] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_NFB4EOF_ERR_40 : 1; //!< [8] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_41 : 1; //!< [9] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_42 : 1; //!< [10] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_43 : 1; //!< [11] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_44 : 1; //!< [12] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_45 : 1; //!< [13] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_46 : 1; //!< [14] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_47 : 1; //!< [15] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_48 : 1; //!< [16] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_49 : 1; //!< [17] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_50 : 1; //!< [18] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_51 : 1; //!< [19] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned IDMAC_NFB4EOF_ERR_52 : 1; //!< [20] New Frame before end-of-frame error indication of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_6_ADDR(x) (REGS_IPU_BASE(x) + 0x214)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_6(x) (*(volatile hw_ipu_int_stat_6_t *) HW_IPU_INT_STAT_6_ADDR(x))
|
|
#define HW_IPU_INT_STAT_6_RD(x) (HW_IPU_INT_STAT_6(x).U)
|
|
#define HW_IPU_INT_STAT_6_WR(x, v) (HW_IPU_INT_STAT_6(x).U = (v))
|
|
#define HW_IPU_INT_STAT_6_SET(x, v) (HW_IPU_INT_STAT_6_WR(x, HW_IPU_INT_STAT_6_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_6_CLR(x, v) (HW_IPU_INT_STAT_6_WR(x, HW_IPU_INT_STAT_6_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_6_TOG(x, v) (HW_IPU_INT_STAT_6_WR(x, HW_IPU_INT_STAT_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_33[1] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33 (1) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33 (0x00000002) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_33 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_40[8] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40 (8) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40 (0x00000100) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_40 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_41[9] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41 (9) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41 (0x00000200) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_41 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_42[10] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42 (10) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42 (0x00000400) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_42 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_43[11] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43 (11) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43 (0x00000800) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_43 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_44[12] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44 (12) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44 (0x00001000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_44 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_45[13] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45 (13) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45 (0x00002000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_45 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_46[14] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46 (14) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46 (0x00004000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_46 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_47[15] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47 (15) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47 (0x00008000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_47 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_48[16] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48 (16) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48 (0x00010000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_48 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_49[17] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49 (17) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49 (0x00020000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_49 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_50[18] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50 (18) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50 (0x00040000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_50 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_51[19] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51 (19) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51 (0x00080000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_51 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_6, field IDMAC_NFB4EOF_ERR_52[20] (W1C)
|
|
*
|
|
* New Frame before end-of-frame error indication of Channel interrupt. This bit is the status bit
|
|
* of New Frame before end-of-frame error interrupt of Channel #n. n Indicates the corresponding DMA
|
|
* channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52 (20) //!< Bit position for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52.
|
|
#define BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52 (0x00100000) //!< Bit mask for IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52 from a register value.
|
|
#define BG_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52) >> BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52.
|
|
#define BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52) & BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_NFB4EOF_ERR_52 field to a new value.
|
|
#define BW_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52(x, v) (HW_IPU_INT_STAT_6_WR(x, (HW_IPU_INT_STAT_6_RD(x) & ~BM_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52) | BF_IPU_INT_STAT_6_IDMAC_NFB4EOF_ERR_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_7 - Interrupt Status Register7 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_7 - Interrupt Status Register7 1 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the End-of-Scroll indication (EOS) of DMA
|
|
* Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_7_bitfields
|
|
{
|
|
unsigned RESERVED0 : 19; //!< [18:0] Reserved.
|
|
unsigned IDMAC_EOS_EN_19 : 1; //!< [19] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED1 : 3; //!< [22:20] Reserved.
|
|
unsigned IDMAC_EOS_EN_23 : 1; //!< [23] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_24 : 1; //!< [24] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_25 : 1; //!< [25] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_26 : 1; //!< [26] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_27 : 1; //!< [27] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_28 : 1; //!< [28] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_29 : 1; //!< [29] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_EOS_EN_31 : 1; //!< [31] End of Scroll indication of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_stat_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_7_ADDR(x) (REGS_IPU_BASE(x) + 0x218)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_7(x) (*(volatile hw_ipu_int_stat_7_t *) HW_IPU_INT_STAT_7_ADDR(x))
|
|
#define HW_IPU_INT_STAT_7_RD(x) (HW_IPU_INT_STAT_7(x).U)
|
|
#define HW_IPU_INT_STAT_7_WR(x, v) (HW_IPU_INT_STAT_7(x).U = (v))
|
|
#define HW_IPU_INT_STAT_7_SET(x, v) (HW_IPU_INT_STAT_7_WR(x, HW_IPU_INT_STAT_7_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_7_CLR(x, v) (HW_IPU_INT_STAT_7_WR(x, HW_IPU_INT_STAT_7_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_7_TOG(x, v) (HW_IPU_INT_STAT_7_WR(x, HW_IPU_INT_STAT_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_19[19] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_19 (19) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_19.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_19 (0x00080000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_19.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_19 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_19) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_19.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_19) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_19 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_19(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_19) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_23[23] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_23 (23) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_23.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_23 (0x00800000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_23.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_23 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_23) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_23.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_23) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_23 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_23(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_23) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_24[24] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_24 (24) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_24.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_24 (0x01000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_24.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_24 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_24) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_24.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_24) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_24 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_24(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_24) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_25[25] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_25 (25) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_25.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_25 (0x02000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_25 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_25) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_25.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_25) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_25 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_25(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_25) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_26[26] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_26 (26) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_26.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_26 (0x04000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_26 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_26) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_26.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_26) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_26 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_26(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_26) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_27[27] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_27 (27) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_27.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_27 (0x08000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_27.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_27 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_27) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_27.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_27) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_27 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_27(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_27) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_28[28] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_28 (28) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_28.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_28 (0x10000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_28.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_28 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_28) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_28.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_28) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_28 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_28(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_28) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_29[29] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_29 (29) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_29.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_29 (0x20000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_29.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_29 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_29) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_29.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_29) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_29 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_29(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_29) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_7, field IDMAC_EOS_EN_31[31] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_7_IDMAC_EOS_EN_31 (31) //!< Bit position for IPU_INT_STAT_7_IDMAC_EOS_EN_31.
|
|
#define BM_IPU_INT_STAT_7_IDMAC_EOS_EN_31 (0x80000000) //!< Bit mask for IPU_INT_STAT_7_IDMAC_EOS_EN_31.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_7_IDMAC_EOS_EN_31 from a register value.
|
|
#define BG_IPU_INT_STAT_7_IDMAC_EOS_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_31) >> BP_IPU_INT_STAT_7_IDMAC_EOS_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_7_IDMAC_EOS_EN_31.
|
|
#define BF_IPU_INT_STAT_7_IDMAC_EOS_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_7_IDMAC_EOS_EN_31) & BM_IPU_INT_STAT_7_IDMAC_EOS_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_31 field to a new value.
|
|
#define BW_IPU_INT_STAT_7_IDMAC_EOS_EN_31(x, v) (HW_IPU_INT_STAT_7_WR(x, (HW_IPU_INT_STAT_7_RD(x) & ~BM_IPU_INT_STAT_7_IDMAC_EOS_EN_31) | BF_IPU_INT_STAT_7_IDMAC_EOS_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_8 - Interrupt Status Register 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_8 - Interrupt Status Register 8 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. All the status bits of the End of Scroll indication (EOS) of
|
|
* DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_8_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_EOS_EN_33 : 1; //!< [1] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED1 : 7; //!< [8:2] Reserved.
|
|
unsigned IDMAC_EOS_EN_41 : 1; //!< [9] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_42 : 1; //!< [10] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_43 : 1; //!< [11] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_44 : 1; //!< [12] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED2 : 6; //!< [18:13] Reserved.
|
|
unsigned IDMAC_EOS_EN_51 : 1; //!< [19] End of Scroll indication of Channel interrupt.
|
|
unsigned IDMAC_EOS_EN_52 : 1; //!< [20] End of Scroll indication of Channel interrupt.
|
|
unsigned RESERVED3 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_8_ADDR(x) (REGS_IPU_BASE(x) + 0x21c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_8(x) (*(volatile hw_ipu_int_stat_8_t *) HW_IPU_INT_STAT_8_ADDR(x))
|
|
#define HW_IPU_INT_STAT_8_RD(x) (HW_IPU_INT_STAT_8(x).U)
|
|
#define HW_IPU_INT_STAT_8_WR(x, v) (HW_IPU_INT_STAT_8(x).U = (v))
|
|
#define HW_IPU_INT_STAT_8_SET(x, v) (HW_IPU_INT_STAT_8_WR(x, HW_IPU_INT_STAT_8_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_8_CLR(x, v) (HW_IPU_INT_STAT_8_WR(x, HW_IPU_INT_STAT_8_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_8_TOG(x, v) (HW_IPU_INT_STAT_8_WR(x, HW_IPU_INT_STAT_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_33[1] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_33 (1) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_33.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_33 (0x00000002) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_33.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_33 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_33) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_33.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_33) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_33 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_33(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_33) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_41[9] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_41 (9) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_41.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_41 (0x00000200) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_41.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_41 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_41) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_41.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_41) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_41 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_41(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_41) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_42[10] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_42 (10) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_42.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_42 (0x00000400) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_42.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_42 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_42) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_42.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_42) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_42 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_42(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_42) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_43[11] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_43 (11) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_43.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_43 (0x00000800) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_43.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_43 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_43) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_43.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_43) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_43 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_43(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_43) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_44[12] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_44 (12) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_44.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_44 (0x00001000) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_44.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_44 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_44) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_44.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_44) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_44 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_44(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_44) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_51[19] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_51 (19) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_51.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_51 (0x00080000) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_51.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_51 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_51) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_51.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_51) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_51 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_51(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_51) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_8, field IDMAC_EOS_EN_52[20] (W1C)
|
|
*
|
|
* End of Scroll indication of Channel interrupt. This bit is the status bit of End of Scroll
|
|
* interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_8_IDMAC_EOS_EN_52 (20) //!< Bit position for IPU_INT_STAT_8_IDMAC_EOS_EN_52.
|
|
#define BM_IPU_INT_STAT_8_IDMAC_EOS_EN_52 (0x00100000) //!< Bit mask for IPU_INT_STAT_8_IDMAC_EOS_EN_52.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_8_IDMAC_EOS_EN_52 from a register value.
|
|
#define BG_IPU_INT_STAT_8_IDMAC_EOS_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_52) >> BP_IPU_INT_STAT_8_IDMAC_EOS_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_8_IDMAC_EOS_EN_52.
|
|
#define BF_IPU_INT_STAT_8_IDMAC_EOS_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_8_IDMAC_EOS_EN_52) & BM_IPU_INT_STAT_8_IDMAC_EOS_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOS_EN_52 field to a new value.
|
|
#define BW_IPU_INT_STAT_8_IDMAC_EOS_EN_52(x, v) (HW_IPU_INT_STAT_8_WR(x, (HW_IPU_INT_STAT_8_RD(x) & ~BM_IPU_INT_STAT_8_IDMAC_EOS_EN_52) | BF_IPU_INT_STAT_8_IDMAC_EOS_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_9 - Interrupt Status Register 9
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_9 - Interrupt Status Register 9 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. This register holds the error interrupt indications coming
|
|
* from different modules within All the bits in this register are write one to clear.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_9_bitfields
|
|
{
|
|
unsigned VDI_FIFO1_OVF : 1; //!< [0] FIFO1 overflow Interrupt1
|
|
unsigned RESERVED0 : 25; //!< [25:1] Reserved
|
|
unsigned IC_BAYER_BUF_OVF : 1; //!< [26] This bit indicates on an interrupt that is a result of the IC Buffer overflow for Bayer coming from the IC.
|
|
unsigned IC_ENC_BUF_OVF : 1; //!< [27] This bit indicates on an interrupt that is a result of the IC Buffer overflow for encoding coming from the IC.
|
|
unsigned IC_VF_BUF_OVF : 1; //!< [28] This bit indicates on an interrupt that is a result of the IC Buffer overflow for view finder coming from the IC.
|
|
unsigned RESERVED1 : 1; //!< [29] Reserved
|
|
unsigned CSI0_PUPE : 1; //!< [30] CSI0_PUPE - CSI0 parameters update error interrupt.
|
|
unsigned CSI1_PUPE : 1; //!< [31] CSI1_PUPE - CSI1 parameters update error interrupt.
|
|
} B;
|
|
} hw_ipu_int_stat_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_9_ADDR(x) (REGS_IPU_BASE(x) + 0x220)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_9(x) (*(volatile hw_ipu_int_stat_9_t *) HW_IPU_INT_STAT_9_ADDR(x))
|
|
#define HW_IPU_INT_STAT_9_RD(x) (HW_IPU_INT_STAT_9(x).U)
|
|
#define HW_IPU_INT_STAT_9_WR(x, v) (HW_IPU_INT_STAT_9(x).U = (v))
|
|
#define HW_IPU_INT_STAT_9_SET(x, v) (HW_IPU_INT_STAT_9_WR(x, HW_IPU_INT_STAT_9_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_9_CLR(x, v) (HW_IPU_INT_STAT_9_WR(x, HW_IPU_INT_STAT_9_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_9_TOG(x, v) (HW_IPU_INT_STAT_9_WR(x, HW_IPU_INT_STAT_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_9, field VDI_FIFO1_OVF[0] (W1C)
|
|
*
|
|
* FIFO1 overflow Interrupt1 The VDI C generate FIFO1 overflow interrupt1 when write pointer of
|
|
* FIFO1 overrun read pointer.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_9_VDI_FIFO1_OVF (0) //!< Bit position for IPU_INT_STAT_9_VDI_FIFO1_OVF.
|
|
#define BM_IPU_INT_STAT_9_VDI_FIFO1_OVF (0x00000001) //!< Bit mask for IPU_INT_STAT_9_VDI_FIFO1_OVF.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_9_VDI_FIFO1_OVF from a register value.
|
|
#define BG_IPU_INT_STAT_9_VDI_FIFO1_OVF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_9_VDI_FIFO1_OVF) >> BP_IPU_INT_STAT_9_VDI_FIFO1_OVF)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_9_VDI_FIFO1_OVF.
|
|
#define BF_IPU_INT_STAT_9_VDI_FIFO1_OVF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_9_VDI_FIFO1_OVF) & BM_IPU_INT_STAT_9_VDI_FIFO1_OVF)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FIFO1_OVF field to a new value.
|
|
#define BW_IPU_INT_STAT_9_VDI_FIFO1_OVF(x, v) (HW_IPU_INT_STAT_9_WR(x, (HW_IPU_INT_STAT_9_RD(x) & ~BM_IPU_INT_STAT_9_VDI_FIFO1_OVF) | BF_IPU_INT_STAT_9_VDI_FIFO1_OVF(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_9, field IC_BAYER_BUF_OVF[26] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt that is a result of the IC Buffer overflow for Bayer coming
|
|
* from the IC. The user needs to write 1 to this bit in order to clear it.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_9_IC_BAYER_BUF_OVF (26) //!< Bit position for IPU_INT_STAT_9_IC_BAYER_BUF_OVF.
|
|
#define BM_IPU_INT_STAT_9_IC_BAYER_BUF_OVF (0x04000000) //!< Bit mask for IPU_INT_STAT_9_IC_BAYER_BUF_OVF.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_9_IC_BAYER_BUF_OVF from a register value.
|
|
#define BG_IPU_INT_STAT_9_IC_BAYER_BUF_OVF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_9_IC_BAYER_BUF_OVF) >> BP_IPU_INT_STAT_9_IC_BAYER_BUF_OVF)
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//! @brief Format value for bitfield IPU_INT_STAT_9_IC_BAYER_BUF_OVF.
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#define BF_IPU_INT_STAT_9_IC_BAYER_BUF_OVF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_9_IC_BAYER_BUF_OVF) & BM_IPU_INT_STAT_9_IC_BAYER_BUF_OVF)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IC_BAYER_BUF_OVF field to a new value.
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|
#define BW_IPU_INT_STAT_9_IC_BAYER_BUF_OVF(x, v) (HW_IPU_INT_STAT_9_WR(x, (HW_IPU_INT_STAT_9_RD(x) & ~BM_IPU_INT_STAT_9_IC_BAYER_BUF_OVF) | BF_IPU_INT_STAT_9_IC_BAYER_BUF_OVF(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_9, field IC_ENC_BUF_OVF[27] (W1C)
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*
|
|
* This bit indicates on an interrupt that is a result of the IC Buffer overflow for encoding coming
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|
* from the IC. The user needs to write 1 to this bit in order to clear it.
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
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|
* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_9_IC_ENC_BUF_OVF (27) //!< Bit position for IPU_INT_STAT_9_IC_ENC_BUF_OVF.
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#define BM_IPU_INT_STAT_9_IC_ENC_BUF_OVF (0x08000000) //!< Bit mask for IPU_INT_STAT_9_IC_ENC_BUF_OVF.
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//! @brief Get value of IPU_INT_STAT_9_IC_ENC_BUF_OVF from a register value.
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#define BG_IPU_INT_STAT_9_IC_ENC_BUF_OVF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_9_IC_ENC_BUF_OVF) >> BP_IPU_INT_STAT_9_IC_ENC_BUF_OVF)
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//! @brief Format value for bitfield IPU_INT_STAT_9_IC_ENC_BUF_OVF.
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#define BF_IPU_INT_STAT_9_IC_ENC_BUF_OVF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_9_IC_ENC_BUF_OVF) & BM_IPU_INT_STAT_9_IC_ENC_BUF_OVF)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IC_ENC_BUF_OVF field to a new value.
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#define BW_IPU_INT_STAT_9_IC_ENC_BUF_OVF(x, v) (HW_IPU_INT_STAT_9_WR(x, (HW_IPU_INT_STAT_9_RD(x) & ~BM_IPU_INT_STAT_9_IC_ENC_BUF_OVF) | BF_IPU_INT_STAT_9_IC_ENC_BUF_OVF(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_9, field IC_VF_BUF_OVF[28] (W1C)
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*
|
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* This bit indicates on an interrupt that is a result of the IC Buffer overflow for view finder
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* coming from the IC. The user needs to write 1 to this bit in order to clear it.
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
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|
* - 1 - Interrupt is requested.
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*/
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|
//@{
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|
#define BP_IPU_INT_STAT_9_IC_VF_BUF_OVF (28) //!< Bit position for IPU_INT_STAT_9_IC_VF_BUF_OVF.
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#define BM_IPU_INT_STAT_9_IC_VF_BUF_OVF (0x10000000) //!< Bit mask for IPU_INT_STAT_9_IC_VF_BUF_OVF.
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//! @brief Get value of IPU_INT_STAT_9_IC_VF_BUF_OVF from a register value.
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#define BG_IPU_INT_STAT_9_IC_VF_BUF_OVF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_9_IC_VF_BUF_OVF) >> BP_IPU_INT_STAT_9_IC_VF_BUF_OVF)
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//! @brief Format value for bitfield IPU_INT_STAT_9_IC_VF_BUF_OVF.
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|
#define BF_IPU_INT_STAT_9_IC_VF_BUF_OVF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_9_IC_VF_BUF_OVF) & BM_IPU_INT_STAT_9_IC_VF_BUF_OVF)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IC_VF_BUF_OVF field to a new value.
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|
#define BW_IPU_INT_STAT_9_IC_VF_BUF_OVF(x, v) (HW_IPU_INT_STAT_9_WR(x, (HW_IPU_INT_STAT_9_RD(x) & ~BM_IPU_INT_STAT_9_IC_VF_BUF_OVF) | BF_IPU_INT_STAT_9_IC_VF_BUF_OVF(v)))
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#endif
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|
//@}
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/*! @name Register IPU_INT_STAT_9, field CSI0_PUPE[30] (W1C)
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*
|
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* CSI0_PUPE - CSI0 parameters update error interrupt. This bit indicates on an interrupt that is a
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* result of an error generated by the CSI0. The error is generated in case where new frame arrived
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* from the CSI0 before the completion of the CSI0's parameters update by the SRM
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
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|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_9_CSI0_PUPE (30) //!< Bit position for IPU_INT_STAT_9_CSI0_PUPE.
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|
#define BM_IPU_INT_STAT_9_CSI0_PUPE (0x40000000) //!< Bit mask for IPU_INT_STAT_9_CSI0_PUPE.
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//! @brief Get value of IPU_INT_STAT_9_CSI0_PUPE from a register value.
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|
#define BG_IPU_INT_STAT_9_CSI0_PUPE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_9_CSI0_PUPE) >> BP_IPU_INT_STAT_9_CSI0_PUPE)
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|
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//! @brief Format value for bitfield IPU_INT_STAT_9_CSI0_PUPE.
|
|
#define BF_IPU_INT_STAT_9_CSI0_PUPE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_9_CSI0_PUPE) & BM_IPU_INT_STAT_9_CSI0_PUPE)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_PUPE field to a new value.
|
|
#define BW_IPU_INT_STAT_9_CSI0_PUPE(x, v) (HW_IPU_INT_STAT_9_WR(x, (HW_IPU_INT_STAT_9_RD(x) & ~BM_IPU_INT_STAT_9_CSI0_PUPE) | BF_IPU_INT_STAT_9_CSI0_PUPE(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_INT_STAT_9, field CSI1_PUPE[31] (W1C)
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|
*
|
|
* CSI1_PUPE - CSI1 parameters update error interrupt. This bit indicates on an interrupt that is a
|
|
* result of an error generated by the CSI1. The error is generated in case where new frame arrived
|
|
* from the CSI1 before the completion of the CSI1's parameters update by the SRM
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
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|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_9_CSI1_PUPE (31) //!< Bit position for IPU_INT_STAT_9_CSI1_PUPE.
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|
#define BM_IPU_INT_STAT_9_CSI1_PUPE (0x80000000) //!< Bit mask for IPU_INT_STAT_9_CSI1_PUPE.
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|
|
|
//! @brief Get value of IPU_INT_STAT_9_CSI1_PUPE from a register value.
|
|
#define BG_IPU_INT_STAT_9_CSI1_PUPE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_9_CSI1_PUPE) >> BP_IPU_INT_STAT_9_CSI1_PUPE)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_9_CSI1_PUPE.
|
|
#define BF_IPU_INT_STAT_9_CSI1_PUPE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_9_CSI1_PUPE) & BM_IPU_INT_STAT_9_CSI1_PUPE)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_PUPE field to a new value.
|
|
#define BW_IPU_INT_STAT_9_CSI1_PUPE(x, v) (HW_IPU_INT_STAT_9_WR(x, (HW_IPU_INT_STAT_9_RD(x) & ~BM_IPU_INT_STAT_9_CSI1_PUPE) | BF_IPU_INT_STAT_9_CSI1_PUPE(v)))
|
|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_10 - Interrupt Status Register 10
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_10 - Interrupt Status Register 10 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. This register holds error interrupt indications coming from
|
|
* different modules within All the bits in this register are write one to clear.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_10
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_10_bitfields
|
|
{
|
|
unsigned SMFC0_FRM_LOST : 1; //!< [0] Frame Lost of SMFC channel 0 interrupt.
|
|
unsigned SMFC1_FRM_LOST : 1; //!< [1] Frame Lost of SMFC channel 1 interrupt.
|
|
unsigned SMFC2_FRM_LOST : 1; //!< [2] Frame Lost of SMFC channel 2 interrupt.
|
|
unsigned SMFC3_FRM_LOST : 1; //!< [3] Frame Lost of SMFC channel 3 interrupt.
|
|
unsigned RESERVED0 : 12; //!< [15:4] Reserved
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|
unsigned DC_TEARING_ERR_1 : 1; //!< [16] Tearing Error #1 interrupt
|
|
unsigned DC_TEARING_ERR_2 : 1; //!< [17] Tearing Error #2 interrupt
|
|
unsigned DC_TEARING_ERR_6 : 1; //!< [18] Tearing Error #6 interrupt
|
|
unsigned DI0_SYNC_DISP_ERR : 1; //!< [19] DI0 Synchronous display error interrupt
|
|
unsigned DI1_SYNC_DISP_ERR : 1; //!< [20] DI1 Synchronous display error interrupt
|
|
unsigned DI0_TIME_OUT_ERR : 1; //!< [21] DI0 time out error interrupt
|
|
unsigned DI1_TIME_OUT_ERR : 1; //!< [22] DI1 time out error interrupt
|
|
unsigned RESERVED1 : 1; //!< [23] Reserved
|
|
unsigned IC_VF_FRM_LOST_ERR : 1; //!< [24] This bit indicates on an interrupt that is a result of IC's view finder frame lost.
|
|
unsigned IC_ENC_FRM_LOST_ERR : 1; //!< [25] This bit indicates on an interrupt that is a result of IC's encoding frame lost.
|
|
unsigned IC_BAYER_FRM_LOST_ERR : 1; //!< [26] This bit indicates on an interrupt that is a result of IC's Bayer frame lost.
|
|
unsigned RESERVED2 : 1; //!< [27] Reserved
|
|
unsigned NON_PRIVILEGED_ACC_ERR : 1; //!< [28] Non Privileged Access Error interrupt.
|
|
unsigned AXIW_ERR : 1; //!< [29] This bit indicates on an interrupt that is a result of AXI write access resulted with error response.
|
|
unsigned AXIR_ERR : 1; //!< [30] This bit indicates on an interrupt that is a result of AXI read access resulted with error response.
|
|
unsigned RESERVED3 : 1; //!< [31] Reserved
|
|
} B;
|
|
} hw_ipu_int_stat_10_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_10 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_10_ADDR(x) (REGS_IPU_BASE(x) + 0x224)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_10(x) (*(volatile hw_ipu_int_stat_10_t *) HW_IPU_INT_STAT_10_ADDR(x))
|
|
#define HW_IPU_INT_STAT_10_RD(x) (HW_IPU_INT_STAT_10(x).U)
|
|
#define HW_IPU_INT_STAT_10_WR(x, v) (HW_IPU_INT_STAT_10(x).U = (v))
|
|
#define HW_IPU_INT_STAT_10_SET(x, v) (HW_IPU_INT_STAT_10_WR(x, HW_IPU_INT_STAT_10_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_10_CLR(x, v) (HW_IPU_INT_STAT_10_WR(x, HW_IPU_INT_STAT_10_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_10_TOG(x, v) (HW_IPU_INT_STAT_10_WR(x, HW_IPU_INT_STAT_10_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_10 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field SMFC0_FRM_LOST[0] (W1C)
|
|
*
|
|
* Frame Lost of SMFC channel 0 interrupt. This bit indicates on an interrupt that is a result of a
|
|
* result of a Frame Lost of SMFC channel 0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_SMFC0_FRM_LOST (0) //!< Bit position for IPU_INT_STAT_10_SMFC0_FRM_LOST.
|
|
#define BM_IPU_INT_STAT_10_SMFC0_FRM_LOST (0x00000001) //!< Bit mask for IPU_INT_STAT_10_SMFC0_FRM_LOST.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_SMFC0_FRM_LOST from a register value.
|
|
#define BG_IPU_INT_STAT_10_SMFC0_FRM_LOST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_SMFC0_FRM_LOST) >> BP_IPU_INT_STAT_10_SMFC0_FRM_LOST)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_SMFC0_FRM_LOST.
|
|
#define BF_IPU_INT_STAT_10_SMFC0_FRM_LOST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_SMFC0_FRM_LOST) & BM_IPU_INT_STAT_10_SMFC0_FRM_LOST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC0_FRM_LOST field to a new value.
|
|
#define BW_IPU_INT_STAT_10_SMFC0_FRM_LOST(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_SMFC0_FRM_LOST) | BF_IPU_INT_STAT_10_SMFC0_FRM_LOST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field SMFC1_FRM_LOST[1] (W1C)
|
|
*
|
|
* Frame Lost of SMFC channel 1 interrupt. This bit indicates on an interrupt that is a result of a
|
|
* result of a Frame Lost of SMFC channel 1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_SMFC1_FRM_LOST (1) //!< Bit position for IPU_INT_STAT_10_SMFC1_FRM_LOST.
|
|
#define BM_IPU_INT_STAT_10_SMFC1_FRM_LOST (0x00000002) //!< Bit mask for IPU_INT_STAT_10_SMFC1_FRM_LOST.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_SMFC1_FRM_LOST from a register value.
|
|
#define BG_IPU_INT_STAT_10_SMFC1_FRM_LOST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_SMFC1_FRM_LOST) >> BP_IPU_INT_STAT_10_SMFC1_FRM_LOST)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_SMFC1_FRM_LOST.
|
|
#define BF_IPU_INT_STAT_10_SMFC1_FRM_LOST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_SMFC1_FRM_LOST) & BM_IPU_INT_STAT_10_SMFC1_FRM_LOST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC1_FRM_LOST field to a new value.
|
|
#define BW_IPU_INT_STAT_10_SMFC1_FRM_LOST(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_SMFC1_FRM_LOST) | BF_IPU_INT_STAT_10_SMFC1_FRM_LOST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field SMFC2_FRM_LOST[2] (W1C)
|
|
*
|
|
* Frame Lost of SMFC channel 2 interrupt. This bit indicates on an interrupt that is a result of a
|
|
* result of a Frame Lost of SMFC channel 2
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_SMFC2_FRM_LOST (2) //!< Bit position for IPU_INT_STAT_10_SMFC2_FRM_LOST.
|
|
#define BM_IPU_INT_STAT_10_SMFC2_FRM_LOST (0x00000004) //!< Bit mask for IPU_INT_STAT_10_SMFC2_FRM_LOST.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_SMFC2_FRM_LOST from a register value.
|
|
#define BG_IPU_INT_STAT_10_SMFC2_FRM_LOST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_SMFC2_FRM_LOST) >> BP_IPU_INT_STAT_10_SMFC2_FRM_LOST)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_SMFC2_FRM_LOST.
|
|
#define BF_IPU_INT_STAT_10_SMFC2_FRM_LOST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_SMFC2_FRM_LOST) & BM_IPU_INT_STAT_10_SMFC2_FRM_LOST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC2_FRM_LOST field to a new value.
|
|
#define BW_IPU_INT_STAT_10_SMFC2_FRM_LOST(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_SMFC2_FRM_LOST) | BF_IPU_INT_STAT_10_SMFC2_FRM_LOST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field SMFC3_FRM_LOST[3] (W1C)
|
|
*
|
|
* Frame Lost of SMFC channel 3 interrupt. This bit indicates on an interrupt that is a result of a
|
|
* result of a Frame Lost of SMFC channel 3
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_SMFC3_FRM_LOST (3) //!< Bit position for IPU_INT_STAT_10_SMFC3_FRM_LOST.
|
|
#define BM_IPU_INT_STAT_10_SMFC3_FRM_LOST (0x00000008) //!< Bit mask for IPU_INT_STAT_10_SMFC3_FRM_LOST.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_SMFC3_FRM_LOST from a register value.
|
|
#define BG_IPU_INT_STAT_10_SMFC3_FRM_LOST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_SMFC3_FRM_LOST) >> BP_IPU_INT_STAT_10_SMFC3_FRM_LOST)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_SMFC3_FRM_LOST.
|
|
#define BF_IPU_INT_STAT_10_SMFC3_FRM_LOST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_SMFC3_FRM_LOST) & BM_IPU_INT_STAT_10_SMFC3_FRM_LOST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SMFC3_FRM_LOST field to a new value.
|
|
#define BW_IPU_INT_STAT_10_SMFC3_FRM_LOST(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_SMFC3_FRM_LOST) | BF_IPU_INT_STAT_10_SMFC3_FRM_LOST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field DC_TEARING_ERR_1[16] (W1C)
|
|
*
|
|
* Tearing Error #1 interrupt This bit indicates on the interrupt that is a result of tearing error
|
|
* while the anti tearing mechanism is activated for DC channel 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_DC_TEARING_ERR_1 (16) //!< Bit position for IPU_INT_STAT_10_DC_TEARING_ERR_1.
|
|
#define BM_IPU_INT_STAT_10_DC_TEARING_ERR_1 (0x00010000) //!< Bit mask for IPU_INT_STAT_10_DC_TEARING_ERR_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_DC_TEARING_ERR_1 from a register value.
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#define BG_IPU_INT_STAT_10_DC_TEARING_ERR_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DC_TEARING_ERR_1) >> BP_IPU_INT_STAT_10_DC_TEARING_ERR_1)
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//! @brief Format value for bitfield IPU_INT_STAT_10_DC_TEARING_ERR_1.
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#define BF_IPU_INT_STAT_10_DC_TEARING_ERR_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DC_TEARING_ERR_1) & BM_IPU_INT_STAT_10_DC_TEARING_ERR_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DC_TEARING_ERR_1 field to a new value.
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#define BW_IPU_INT_STAT_10_DC_TEARING_ERR_1(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DC_TEARING_ERR_1) | BF_IPU_INT_STAT_10_DC_TEARING_ERR_1(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_10, field DC_TEARING_ERR_2[17] (W1C)
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*
|
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* Tearing Error #2 interrupt This bit indicates on the interrupt that is a result of tearing error
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* while the anti tearing mechanism is activated for DC channel 2
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*/
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//@{
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#define BP_IPU_INT_STAT_10_DC_TEARING_ERR_2 (17) //!< Bit position for IPU_INT_STAT_10_DC_TEARING_ERR_2.
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#define BM_IPU_INT_STAT_10_DC_TEARING_ERR_2 (0x00020000) //!< Bit mask for IPU_INT_STAT_10_DC_TEARING_ERR_2.
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//! @brief Get value of IPU_INT_STAT_10_DC_TEARING_ERR_2 from a register value.
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#define BG_IPU_INT_STAT_10_DC_TEARING_ERR_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DC_TEARING_ERR_2) >> BP_IPU_INT_STAT_10_DC_TEARING_ERR_2)
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//! @brief Format value for bitfield IPU_INT_STAT_10_DC_TEARING_ERR_2.
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#define BF_IPU_INT_STAT_10_DC_TEARING_ERR_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DC_TEARING_ERR_2) & BM_IPU_INT_STAT_10_DC_TEARING_ERR_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DC_TEARING_ERR_2 field to a new value.
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#define BW_IPU_INT_STAT_10_DC_TEARING_ERR_2(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DC_TEARING_ERR_2) | BF_IPU_INT_STAT_10_DC_TEARING_ERR_2(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_10, field DC_TEARING_ERR_6[18] (W1C)
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*
|
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* Tearing Error #6 interrupt This bit indicates on the interrupt that is a result of tearing error
|
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* while the anti tearing mechanism is activated for DC channel 6
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*/
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//@{
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#define BP_IPU_INT_STAT_10_DC_TEARING_ERR_6 (18) //!< Bit position for IPU_INT_STAT_10_DC_TEARING_ERR_6.
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#define BM_IPU_INT_STAT_10_DC_TEARING_ERR_6 (0x00040000) //!< Bit mask for IPU_INT_STAT_10_DC_TEARING_ERR_6.
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//! @brief Get value of IPU_INT_STAT_10_DC_TEARING_ERR_6 from a register value.
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#define BG_IPU_INT_STAT_10_DC_TEARING_ERR_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DC_TEARING_ERR_6) >> BP_IPU_INT_STAT_10_DC_TEARING_ERR_6)
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//! @brief Format value for bitfield IPU_INT_STAT_10_DC_TEARING_ERR_6.
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#define BF_IPU_INT_STAT_10_DC_TEARING_ERR_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DC_TEARING_ERR_6) & BM_IPU_INT_STAT_10_DC_TEARING_ERR_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DC_TEARING_ERR_6 field to a new value.
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#define BW_IPU_INT_STAT_10_DC_TEARING_ERR_6(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DC_TEARING_ERR_6) | BF_IPU_INT_STAT_10_DC_TEARING_ERR_6(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_10, field DI0_SYNC_DISP_ERR[19] (W1C)
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*
|
|
* DI0 Synchronous display error interrupt This bit indicates on the interrupt that is a result of
|
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* an error during access to a synchronous display via DI0
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|
*/
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//@{
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#define BP_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR (19) //!< Bit position for IPU_INT_STAT_10_DI0_SYNC_DISP_ERR.
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#define BM_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR (0x00080000) //!< Bit mask for IPU_INT_STAT_10_DI0_SYNC_DISP_ERR.
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//! @brief Get value of IPU_INT_STAT_10_DI0_SYNC_DISP_ERR from a register value.
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#define BG_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR) >> BP_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR)
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//! @brief Format value for bitfield IPU_INT_STAT_10_DI0_SYNC_DISP_ERR.
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#define BF_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR) & BM_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SYNC_DISP_ERR field to a new value.
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|
#define BW_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR) | BF_IPU_INT_STAT_10_DI0_SYNC_DISP_ERR(v)))
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#endif
|
|
//@}
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/*! @name Register IPU_INT_STAT_10, field DI1_SYNC_DISP_ERR[20] (W1C)
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|
*
|
|
* DI1 Synchronous display error interrupt This bit indicates on the interrupt that is a result of
|
|
* an error during access to a synchronous display via DI1
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR (20) //!< Bit position for IPU_INT_STAT_10_DI1_SYNC_DISP_ERR.
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#define BM_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR (0x00100000) //!< Bit mask for IPU_INT_STAT_10_DI1_SYNC_DISP_ERR.
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//! @brief Get value of IPU_INT_STAT_10_DI1_SYNC_DISP_ERR from a register value.
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|
#define BG_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR) >> BP_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR)
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|
//! @brief Format value for bitfield IPU_INT_STAT_10_DI1_SYNC_DISP_ERR.
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|
#define BF_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR) & BM_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SYNC_DISP_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR) | BF_IPU_INT_STAT_10_DI1_SYNC_DISP_ERR(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_10, field DI0_TIME_OUT_ERR[21] (W1C)
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|
*
|
|
* DI0 time out error interrupt This bit indicates on the interrupt that is a result of a time out
|
|
* error during a read access via DI0
|
|
*/
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|
//@{
|
|
#define BP_IPU_INT_STAT_10_DI0_TIME_OUT_ERR (21) //!< Bit position for IPU_INT_STAT_10_DI0_TIME_OUT_ERR.
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|
#define BM_IPU_INT_STAT_10_DI0_TIME_OUT_ERR (0x00200000) //!< Bit mask for IPU_INT_STAT_10_DI0_TIME_OUT_ERR.
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|
//! @brief Get value of IPU_INT_STAT_10_DI0_TIME_OUT_ERR from a register value.
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|
#define BG_IPU_INT_STAT_10_DI0_TIME_OUT_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DI0_TIME_OUT_ERR) >> BP_IPU_INT_STAT_10_DI0_TIME_OUT_ERR)
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|
//! @brief Format value for bitfield IPU_INT_STAT_10_DI0_TIME_OUT_ERR.
|
|
#define BF_IPU_INT_STAT_10_DI0_TIME_OUT_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DI0_TIME_OUT_ERR) & BM_IPU_INT_STAT_10_DI0_TIME_OUT_ERR)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_TIME_OUT_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_DI0_TIME_OUT_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DI0_TIME_OUT_ERR) | BF_IPU_INT_STAT_10_DI0_TIME_OUT_ERR(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_10, field DI1_TIME_OUT_ERR[22] (W1C)
|
|
*
|
|
* DI1 time out error interrupt This bit indicates on the interrupt that is a result of a time out
|
|
* error during a read access via DI1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_DI1_TIME_OUT_ERR (22) //!< Bit position for IPU_INT_STAT_10_DI1_TIME_OUT_ERR.
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|
#define BM_IPU_INT_STAT_10_DI1_TIME_OUT_ERR (0x00400000) //!< Bit mask for IPU_INT_STAT_10_DI1_TIME_OUT_ERR.
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|
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|
//! @brief Get value of IPU_INT_STAT_10_DI1_TIME_OUT_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_DI1_TIME_OUT_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_DI1_TIME_OUT_ERR) >> BP_IPU_INT_STAT_10_DI1_TIME_OUT_ERR)
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|
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|
//! @brief Format value for bitfield IPU_INT_STAT_10_DI1_TIME_OUT_ERR.
|
|
#define BF_IPU_INT_STAT_10_DI1_TIME_OUT_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_DI1_TIME_OUT_ERR) & BM_IPU_INT_STAT_10_DI1_TIME_OUT_ERR)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_TIME_OUT_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_DI1_TIME_OUT_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_DI1_TIME_OUT_ERR) | BF_IPU_INT_STAT_10_DI1_TIME_OUT_ERR(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field IC_VF_FRM_LOST_ERR[24] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt that is a result of IC's view finder frame lost.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR (24) //!< Bit position for IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR.
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|
#define BM_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR (0x01000000) //!< Bit mask for IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR.
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|
|
|
//! @brief Get value of IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR) >> BP_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR.
|
|
#define BF_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR) & BM_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_VF_FRM_LOST_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR) | BF_IPU_INT_STAT_10_IC_VF_FRM_LOST_ERR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field IC_ENC_FRM_LOST_ERR[25] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt that is a result of IC's encoding frame lost.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR (25) //!< Bit position for IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR.
|
|
#define BM_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR (0x02000000) //!< Bit mask for IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR.
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|
|
|
//! @brief Get value of IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR) >> BP_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR.
|
|
#define BF_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR) & BM_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_ENC_FRM_LOST_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR) | BF_IPU_INT_STAT_10_IC_ENC_FRM_LOST_ERR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field IC_BAYER_FRM_LOST_ERR[26] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt that is a result of IC's Bayer frame lost.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is disabled.
|
|
* - 1 - Interrupt is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR (26) //!< Bit position for IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR.
|
|
#define BM_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR (0x04000000) //!< Bit mask for IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR) >> BP_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR.
|
|
#define BF_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR) & BM_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_BAYER_FRM_LOST_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR) | BF_IPU_INT_STAT_10_IC_BAYER_FRM_LOST_ERR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field NON_PRIVILEGED_ACC_ERR[28] (W1C)
|
|
*
|
|
* Non Privileged Access Error interrupt. This bit indicates on an interrupt that is a result of
|
|
* access the CPMEM or the DP memory in user mode
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR (28) //!< Bit position for IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR.
|
|
#define BM_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR (0x10000000) //!< Bit mask for IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR) >> BP_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR.
|
|
#define BF_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR) & BM_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NON_PRIVILEGED_ACC_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR) | BF_IPU_INT_STAT_10_NON_PRIVILEGED_ACC_ERR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field AXIW_ERR[29] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt that is a result of AXI write access resulted with error
|
|
* response. The user needs to write 1 to this bit in order to clear it.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_AXIW_ERR (29) //!< Bit position for IPU_INT_STAT_10_AXIW_ERR.
|
|
#define BM_IPU_INT_STAT_10_AXIW_ERR (0x20000000) //!< Bit mask for IPU_INT_STAT_10_AXIW_ERR.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_AXIW_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_AXIW_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_AXIW_ERR) >> BP_IPU_INT_STAT_10_AXIW_ERR)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_AXIW_ERR.
|
|
#define BF_IPU_INT_STAT_10_AXIW_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_AXIW_ERR) & BM_IPU_INT_STAT_10_AXIW_ERR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AXIW_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_AXIW_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_AXIW_ERR) | BF_IPU_INT_STAT_10_AXIW_ERR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_10, field AXIR_ERR[30] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt that is a result of AXI read access resulted with error
|
|
* response. The user needs to write 1 to this bit in order to clear it.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_10_AXIR_ERR (30) //!< Bit position for IPU_INT_STAT_10_AXIR_ERR.
|
|
#define BM_IPU_INT_STAT_10_AXIR_ERR (0x40000000) //!< Bit mask for IPU_INT_STAT_10_AXIR_ERR.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_10_AXIR_ERR from a register value.
|
|
#define BG_IPU_INT_STAT_10_AXIR_ERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_10_AXIR_ERR) >> BP_IPU_INT_STAT_10_AXIR_ERR)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_10_AXIR_ERR.
|
|
#define BF_IPU_INT_STAT_10_AXIR_ERR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_10_AXIR_ERR) & BM_IPU_INT_STAT_10_AXIR_ERR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AXIR_ERR field to a new value.
|
|
#define BW_IPU_INT_STAT_10_AXIR_ERR(x, v) (HW_IPU_INT_STAT_10_WR(x, (HW_IPU_INT_STAT_10_RD(x) & ~BM_IPU_INT_STAT_10_AXIR_ERR) | BF_IPU_INT_STAT_10_AXIR_ERR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_11 - Interrupt Status Register 11
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_11 - Interrupt Status Register 11 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the end-of-band indication (EOBND) of DMA
|
|
* Channels interrupts [31:0] can be found in this register. Hide VDOA_SYNC for all versions Show
|
|
* VDOA_SYNC for IPUv3H version. The table below tagged with other settings (like IPU3M_only) should
|
|
* be hidden in IPUv3H version.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_11
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_11_bitfields
|
|
{
|
|
unsigned IDMAC_EOBND_EN_0 : 1; //!< [0] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_1 : 1; //!< [1] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_2 : 1; //!< [2] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_3 : 1; //!< [3] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_EOBND_EN_5 : 1; //!< [5] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED1 : 5; //!< [10:6] Reserved.
|
|
unsigned IDMAC_EOBND_EN_11 : 1; //!< [11] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_12 : 1; //!< [12] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED2 : 7; //!< [19:13] Reserved.
|
|
unsigned IDMAC_EOBND_EN_20 : 1; //!< [20] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_21 : 1; //!< [21] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_22 : 1; //!< [22] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED3 : 2; //!< [24:23] Reserved.
|
|
unsigned IDMAC_EOBND_EN_25 : 1; //!< [25] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_26 : 1; //!< [26] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED4 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_11_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_11 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_11_ADDR(x) (REGS_IPU_BASE(x) + 0x228)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_11(x) (*(volatile hw_ipu_int_stat_11_t *) HW_IPU_INT_STAT_11_ADDR(x))
|
|
#define HW_IPU_INT_STAT_11_RD(x) (HW_IPU_INT_STAT_11(x).U)
|
|
#define HW_IPU_INT_STAT_11_WR(x, v) (HW_IPU_INT_STAT_11(x).U = (v))
|
|
#define HW_IPU_INT_STAT_11_SET(x, v) (HW_IPU_INT_STAT_11_WR(x, HW_IPU_INT_STAT_11_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_11_CLR(x, v) (HW_IPU_INT_STAT_11_WR(x, HW_IPU_INT_STAT_11_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_11_TOG(x, v) (HW_IPU_INT_STAT_11_WR(x, HW_IPU_INT_STAT_11_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_11 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_0[0] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_0 (0) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_0.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_0 (0x00000001) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_0 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_0) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_0.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_0) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_0(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_0) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_1[1] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_1 (1) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_1.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_1 (0x00000002) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_1 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_1) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_1.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_1) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_1(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_1) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_2[2] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_2 (2) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_2.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_2 (0x00000004) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_2.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_2 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_2) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_2.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_2) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_2 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_2(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_2) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_3[3] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_3 (3) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_3.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_3 (0x00000008) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_3.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_3 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_3) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_3.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_3) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_3 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_3(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_3) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_5[5] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_5 (5) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_5.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_5 (0x00000020) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_5.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_5 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_5) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_5.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_5) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_5 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_5(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_5) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_11[11] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_11 (11) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_11.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_11 (0x00000800) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_11.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_11 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_11) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_11.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_11) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_11 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_11(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_11) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_12[12] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_12 (12) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_12.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_12 (0x00001000) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_12.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_12 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_12) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_12.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_12) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_12 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_12(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_12) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_20[20] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_20 (20) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_20.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_20 (0x00100000) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_20.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_20 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_20) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_20.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_20) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_20)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_20 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_20(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_20) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_21[21] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_21 (21) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_21.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_21 (0x00200000) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_21.
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|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_21 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_21) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_21)
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|
|
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//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_21.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_21) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_21)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_21 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_21(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_21) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_21(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_22[22] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_22 (22) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_22.
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|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_22 (0x00400000) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_22.
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|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_22 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_22) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_22)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_22.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_22) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_22)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_22 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_22(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_22) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_25[25] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_25 (25) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_25.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_25 (0x02000000) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_25.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_25 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_25) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_25.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_25) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_25 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_25(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_25) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_11, field IDMAC_EOBND_EN_26[26] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_26 (26) //!< Bit position for IPU_INT_STAT_11_IDMAC_EOBND_EN_26.
|
|
#define BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_26 (0x04000000) //!< Bit mask for IPU_INT_STAT_11_IDMAC_EOBND_EN_26.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_11_IDMAC_EOBND_EN_26 from a register value.
|
|
#define BG_IPU_INT_STAT_11_IDMAC_EOBND_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_26) >> BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_11_IDMAC_EOBND_EN_26.
|
|
#define BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_11_IDMAC_EOBND_EN_26) & BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_26 field to a new value.
|
|
#define BW_IPU_INT_STAT_11_IDMAC_EOBND_EN_26(x, v) (HW_IPU_INT_STAT_11_WR(x, (HW_IPU_INT_STAT_11_RD(x) & ~BM_IPU_INT_STAT_11_IDMAC_EOBND_EN_26) | BF_IPU_INT_STAT_11_IDMAC_EOBND_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_12 - Interrupt Status Register 12
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_12 - Interrupt Status Register 12 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the end-of-band indication (EOBND) of DMA
|
|
* Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_12
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_12_bitfields
|
|
{
|
|
unsigned RESERVED0 : 13; //!< [12:0] Reserved.
|
|
unsigned IDMAC_EOBND_EN_45 : 1; //!< [13] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_46 : 1; //!< [14] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_47 : 1; //!< [15] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_48 : 1; //!< [16] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_49 : 1; //!< [17] end-of-band indication of Channel interrupt.
|
|
unsigned IDMAC_EOBND_EN_50 : 1; //!< [18] end-of-band indication of Channel interrupt.
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_12_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_12 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_12_ADDR(x) (REGS_IPU_BASE(x) + 0x22c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_12(x) (*(volatile hw_ipu_int_stat_12_t *) HW_IPU_INT_STAT_12_ADDR(x))
|
|
#define HW_IPU_INT_STAT_12_RD(x) (HW_IPU_INT_STAT_12(x).U)
|
|
#define HW_IPU_INT_STAT_12_WR(x, v) (HW_IPU_INT_STAT_12(x).U = (v))
|
|
#define HW_IPU_INT_STAT_12_SET(x, v) (HW_IPU_INT_STAT_12_WR(x, HW_IPU_INT_STAT_12_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_12_CLR(x, v) (HW_IPU_INT_STAT_12_WR(x, HW_IPU_INT_STAT_12_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_12_TOG(x, v) (HW_IPU_INT_STAT_12_WR(x, HW_IPU_INT_STAT_12_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_12 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_12, field IDMAC_EOBND_EN_45[13] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_45 (13) //!< Bit position for IPU_INT_STAT_12_IDMAC_EOBND_EN_45.
|
|
#define BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_45 (0x00002000) //!< Bit mask for IPU_INT_STAT_12_IDMAC_EOBND_EN_45.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_12_IDMAC_EOBND_EN_45 from a register value.
|
|
#define BG_IPU_INT_STAT_12_IDMAC_EOBND_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_45) >> BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_12_IDMAC_EOBND_EN_45.
|
|
#define BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_45) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_45 field to a new value.
|
|
#define BW_IPU_INT_STAT_12_IDMAC_EOBND_EN_45(x, v) (HW_IPU_INT_STAT_12_WR(x, (HW_IPU_INT_STAT_12_RD(x) & ~BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_45) | BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_12, field IDMAC_EOBND_EN_46[14] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_46 (14) //!< Bit position for IPU_INT_STAT_12_IDMAC_EOBND_EN_46.
|
|
#define BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_46 (0x00004000) //!< Bit mask for IPU_INT_STAT_12_IDMAC_EOBND_EN_46.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_12_IDMAC_EOBND_EN_46 from a register value.
|
|
#define BG_IPU_INT_STAT_12_IDMAC_EOBND_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_46) >> BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_12_IDMAC_EOBND_EN_46.
|
|
#define BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_46) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_46 field to a new value.
|
|
#define BW_IPU_INT_STAT_12_IDMAC_EOBND_EN_46(x, v) (HW_IPU_INT_STAT_12_WR(x, (HW_IPU_INT_STAT_12_RD(x) & ~BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_46) | BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_12, field IDMAC_EOBND_EN_47[15] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_47 (15) //!< Bit position for IPU_INT_STAT_12_IDMAC_EOBND_EN_47.
|
|
#define BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_47 (0x00008000) //!< Bit mask for IPU_INT_STAT_12_IDMAC_EOBND_EN_47.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_12_IDMAC_EOBND_EN_47 from a register value.
|
|
#define BG_IPU_INT_STAT_12_IDMAC_EOBND_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_47) >> BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_12_IDMAC_EOBND_EN_47.
|
|
#define BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_47) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_47 field to a new value.
|
|
#define BW_IPU_INT_STAT_12_IDMAC_EOBND_EN_47(x, v) (HW_IPU_INT_STAT_12_WR(x, (HW_IPU_INT_STAT_12_RD(x) & ~BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_47) | BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_12, field IDMAC_EOBND_EN_48[16] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_48 (16) //!< Bit position for IPU_INT_STAT_12_IDMAC_EOBND_EN_48.
|
|
#define BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_48 (0x00010000) //!< Bit mask for IPU_INT_STAT_12_IDMAC_EOBND_EN_48.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_12_IDMAC_EOBND_EN_48 from a register value.
|
|
#define BG_IPU_INT_STAT_12_IDMAC_EOBND_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_48) >> BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_12_IDMAC_EOBND_EN_48.
|
|
#define BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_48) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_48 field to a new value.
|
|
#define BW_IPU_INT_STAT_12_IDMAC_EOBND_EN_48(x, v) (HW_IPU_INT_STAT_12_WR(x, (HW_IPU_INT_STAT_12_RD(x) & ~BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_48) | BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_12, field IDMAC_EOBND_EN_49[17] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_49 (17) //!< Bit position for IPU_INT_STAT_12_IDMAC_EOBND_EN_49.
|
|
#define BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_49 (0x00020000) //!< Bit mask for IPU_INT_STAT_12_IDMAC_EOBND_EN_49.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_12_IDMAC_EOBND_EN_49 from a register value.
|
|
#define BG_IPU_INT_STAT_12_IDMAC_EOBND_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_49) >> BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_12_IDMAC_EOBND_EN_49.
|
|
#define BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_49) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_49 field to a new value.
|
|
#define BW_IPU_INT_STAT_12_IDMAC_EOBND_EN_49(x, v) (HW_IPU_INT_STAT_12_WR(x, (HW_IPU_INT_STAT_12_RD(x) & ~BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_49) | BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_12, field IDMAC_EOBND_EN_50[18] (W1C)
|
|
*
|
|
* end-of-band indication of Channel interrupt. This bit is the status bit of end-of-band interrupt
|
|
* of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_50 (18) //!< Bit position for IPU_INT_STAT_12_IDMAC_EOBND_EN_50.
|
|
#define BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_50 (0x00040000) //!< Bit mask for IPU_INT_STAT_12_IDMAC_EOBND_EN_50.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_12_IDMAC_EOBND_EN_50 from a register value.
|
|
#define BG_IPU_INT_STAT_12_IDMAC_EOBND_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_50) >> BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_12_IDMAC_EOBND_EN_50.
|
|
#define BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_12_IDMAC_EOBND_EN_50) & BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_EOBND_EN_50 field to a new value.
|
|
#define BW_IPU_INT_STAT_12_IDMAC_EOBND_EN_50(x, v) (HW_IPU_INT_STAT_12_WR(x, (HW_IPU_INT_STAT_12_RD(x) & ~BM_IPU_INT_STAT_12_IDMAC_EOBND_EN_50) | BF_IPU_INT_STAT_12_IDMAC_EOBND_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_13 - Interrupt Status Register 13
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_13 - Interrupt Status Register 13 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the Threshold crossing indication (TH) of
|
|
* DMA Channels interrupts [31:0] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_13
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_13_bitfields
|
|
{
|
|
unsigned IDMAC_TH_0 : 1; //!< [0] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_1 : 1; //!< [1] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_2 : 1; //!< [2] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_3 : 1; //!< [3] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_TH_5 : 1; //!< [5] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_TH_8 : 1; //!< [8] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_9 : 1; //!< [9] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_10 : 1; //!< [10] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_11 : 1; //!< [11] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_12 : 1; //!< [12] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_13 : 1; //!< [13] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_14 : 1; //!< [14] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_15 : 1; //!< [15] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_TH_17 : 1; //!< [17] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_18 : 1; //!< [18] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_19 : 1; //!< [19] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_20 : 1; //!< [20] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_21 : 1; //!< [21] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_22 : 1; //!< [22] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_23 : 1; //!< [23] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_24 : 1; //!< [24] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_25 : 1; //!< [25] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_26 : 1; //!< [26] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_27 : 1; //!< [27] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_28 : 1; //!< [28] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_29 : 1; //!< [29] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_TH_31 : 1; //!< [31] Threshold crossing indication of Channel interrupt.
|
|
} B;
|
|
} hw_ipu_int_stat_13_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_13 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_13_ADDR(x) (REGS_IPU_BASE(x) + 0x230)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_13(x) (*(volatile hw_ipu_int_stat_13_t *) HW_IPU_INT_STAT_13_ADDR(x))
|
|
#define HW_IPU_INT_STAT_13_RD(x) (HW_IPU_INT_STAT_13(x).U)
|
|
#define HW_IPU_INT_STAT_13_WR(x, v) (HW_IPU_INT_STAT_13(x).U = (v))
|
|
#define HW_IPU_INT_STAT_13_SET(x, v) (HW_IPU_INT_STAT_13_WR(x, HW_IPU_INT_STAT_13_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_13_CLR(x, v) (HW_IPU_INT_STAT_13_WR(x, HW_IPU_INT_STAT_13_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_13_TOG(x, v) (HW_IPU_INT_STAT_13_WR(x, HW_IPU_INT_STAT_13_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_13 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_0[0] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_0 (0) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_0.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_0 (0x00000001) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_0 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_0) >> BP_IPU_INT_STAT_13_IDMAC_TH_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_0.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_0) & BM_IPU_INT_STAT_13_IDMAC_TH_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_0(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_0) | BF_IPU_INT_STAT_13_IDMAC_TH_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_1[1] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_1 (1) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_1.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_1 (0x00000002) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_1 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_1) >> BP_IPU_INT_STAT_13_IDMAC_TH_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_1.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_1) & BM_IPU_INT_STAT_13_IDMAC_TH_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_1(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_1) | BF_IPU_INT_STAT_13_IDMAC_TH_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_2[2] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_2 (2) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_2.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_2 (0x00000004) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_2.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_2 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_2) >> BP_IPU_INT_STAT_13_IDMAC_TH_2)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_2.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_2) & BM_IPU_INT_STAT_13_IDMAC_TH_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_2 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_2(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_2) | BF_IPU_INT_STAT_13_IDMAC_TH_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_3[3] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_3 (3) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_3.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_3 (0x00000008) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_3.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_3 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_3) >> BP_IPU_INT_STAT_13_IDMAC_TH_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_3.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_3) & BM_IPU_INT_STAT_13_IDMAC_TH_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_3 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_3(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_3) | BF_IPU_INT_STAT_13_IDMAC_TH_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_5[5] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_5 (5) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_5.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_5 (0x00000020) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_5.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_5 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_5) >> BP_IPU_INT_STAT_13_IDMAC_TH_5)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_5.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_5) & BM_IPU_INT_STAT_13_IDMAC_TH_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_5 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_5(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_5) | BF_IPU_INT_STAT_13_IDMAC_TH_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_8[8] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_8 (8) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_8.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_8 (0x00000100) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_8.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_8 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_8) >> BP_IPU_INT_STAT_13_IDMAC_TH_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_8.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_8) & BM_IPU_INT_STAT_13_IDMAC_TH_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_8 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_8(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_8) | BF_IPU_INT_STAT_13_IDMAC_TH_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_9[9] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_9 (9) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_9.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_9 (0x00000200) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_9.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_9 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_9) >> BP_IPU_INT_STAT_13_IDMAC_TH_9)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_9.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_9) & BM_IPU_INT_STAT_13_IDMAC_TH_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_9 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_9(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_9) | BF_IPU_INT_STAT_13_IDMAC_TH_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_10[10] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_10 (10) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_10.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_10 (0x00000400) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_10.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_10 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_10) >> BP_IPU_INT_STAT_13_IDMAC_TH_10)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_10.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_10) & BM_IPU_INT_STAT_13_IDMAC_TH_10)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_10 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_10(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_10) | BF_IPU_INT_STAT_13_IDMAC_TH_10(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_11[11] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_11 (11) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_11.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_11 (0x00000800) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_11.
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|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_11 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_11) >> BP_IPU_INT_STAT_13_IDMAC_TH_11)
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|
|
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//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_11.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_11) & BM_IPU_INT_STAT_13_IDMAC_TH_11)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_11 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_11(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_11) | BF_IPU_INT_STAT_13_IDMAC_TH_11(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_12[12] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_12 (12) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_12.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_12 (0x00001000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_12.
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|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_12 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_12) >> BP_IPU_INT_STAT_13_IDMAC_TH_12)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_12.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_12) & BM_IPU_INT_STAT_13_IDMAC_TH_12)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_12 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_12(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_12) | BF_IPU_INT_STAT_13_IDMAC_TH_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_13[13] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_13 (13) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_13.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_13 (0x00002000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_13.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_13 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_13) >> BP_IPU_INT_STAT_13_IDMAC_TH_13)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_13.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_13) & BM_IPU_INT_STAT_13_IDMAC_TH_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_13 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_13(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_13) | BF_IPU_INT_STAT_13_IDMAC_TH_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_14[14] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_14 (14) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_14.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_14 (0x00004000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_14.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_14 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_14) >> BP_IPU_INT_STAT_13_IDMAC_TH_14)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_14.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_14) & BM_IPU_INT_STAT_13_IDMAC_TH_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_14 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_14(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_14) | BF_IPU_INT_STAT_13_IDMAC_TH_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_15[15] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_15 (15) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_15.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_15 (0x00008000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_15.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_15 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_15) >> BP_IPU_INT_STAT_13_IDMAC_TH_15)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_15.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_15) & BM_IPU_INT_STAT_13_IDMAC_TH_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_15 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_15(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_15) | BF_IPU_INT_STAT_13_IDMAC_TH_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_17[17] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_17 (17) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_17.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_17 (0x00020000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_17.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_17 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_17) >> BP_IPU_INT_STAT_13_IDMAC_TH_17)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_17.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_17) & BM_IPU_INT_STAT_13_IDMAC_TH_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_17 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_17(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_17) | BF_IPU_INT_STAT_13_IDMAC_TH_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_18[18] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_18 (18) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_18.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_18 (0x00040000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_18.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_18 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_18) >> BP_IPU_INT_STAT_13_IDMAC_TH_18)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_18.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_18) & BM_IPU_INT_STAT_13_IDMAC_TH_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_18 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_18(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_18) | BF_IPU_INT_STAT_13_IDMAC_TH_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_19[19] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_19 (19) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_19.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_19 (0x00080000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_19.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_19 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_19) >> BP_IPU_INT_STAT_13_IDMAC_TH_19)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_19.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_19) & BM_IPU_INT_STAT_13_IDMAC_TH_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_19 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_19(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_19) | BF_IPU_INT_STAT_13_IDMAC_TH_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_20[20] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_20 (20) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_20.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_20 (0x00100000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_20.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_20 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_20) >> BP_IPU_INT_STAT_13_IDMAC_TH_20)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_20.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_20) & BM_IPU_INT_STAT_13_IDMAC_TH_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_20 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_20(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_20) | BF_IPU_INT_STAT_13_IDMAC_TH_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_21[21] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_21 (21) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_21.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_21 (0x00200000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_21.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_21 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_21) >> BP_IPU_INT_STAT_13_IDMAC_TH_21)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_21.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_21) & BM_IPU_INT_STAT_13_IDMAC_TH_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_21 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_21(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_21) | BF_IPU_INT_STAT_13_IDMAC_TH_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_22[22] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_22 (22) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_22.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_22 (0x00400000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_22.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_22 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_22) >> BP_IPU_INT_STAT_13_IDMAC_TH_22)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_22.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_22) & BM_IPU_INT_STAT_13_IDMAC_TH_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_22 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_22(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_22) | BF_IPU_INT_STAT_13_IDMAC_TH_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_23[23] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_23 (23) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_23.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_23 (0x00800000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_23.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_23 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_23) >> BP_IPU_INT_STAT_13_IDMAC_TH_23)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_23.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_23) & BM_IPU_INT_STAT_13_IDMAC_TH_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_23 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_23(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_23) | BF_IPU_INT_STAT_13_IDMAC_TH_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_24[24] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_24 (24) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_24.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_24 (0x01000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_24.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_24 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_24) >> BP_IPU_INT_STAT_13_IDMAC_TH_24)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_24.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_24) & BM_IPU_INT_STAT_13_IDMAC_TH_24)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_24 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_24(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_24) | BF_IPU_INT_STAT_13_IDMAC_TH_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_25[25] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_25 (25) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_25.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_25 (0x02000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_25.
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|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_25 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_25) >> BP_IPU_INT_STAT_13_IDMAC_TH_25)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_25.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_25) & BM_IPU_INT_STAT_13_IDMAC_TH_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_25 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_25(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_25) | BF_IPU_INT_STAT_13_IDMAC_TH_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_26[26] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_26 (26) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_26.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_26 (0x04000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_26.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_26 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_26) >> BP_IPU_INT_STAT_13_IDMAC_TH_26)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_26.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_26) & BM_IPU_INT_STAT_13_IDMAC_TH_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_26 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_26(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_26) | BF_IPU_INT_STAT_13_IDMAC_TH_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_27[27] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_27 (27) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_27.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_27 (0x08000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_27.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_27 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_27) >> BP_IPU_INT_STAT_13_IDMAC_TH_27)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_27.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_27) & BM_IPU_INT_STAT_13_IDMAC_TH_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_27 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_27(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_27) | BF_IPU_INT_STAT_13_IDMAC_TH_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_28[28] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_28 (28) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_28.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_28 (0x10000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_28.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_28 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_28) >> BP_IPU_INT_STAT_13_IDMAC_TH_28)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_28.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_28) & BM_IPU_INT_STAT_13_IDMAC_TH_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_28 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_28(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_28) | BF_IPU_INT_STAT_13_IDMAC_TH_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_29[29] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_29 (29) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_29.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_29 (0x20000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_29.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_29 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_29) >> BP_IPU_INT_STAT_13_IDMAC_TH_29)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_29.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_29) & BM_IPU_INT_STAT_13_IDMAC_TH_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_29 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_29(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_29) | BF_IPU_INT_STAT_13_IDMAC_TH_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_13, field IDMAC_TH_31[31] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_13_IDMAC_TH_31 (31) //!< Bit position for IPU_INT_STAT_13_IDMAC_TH_31.
|
|
#define BM_IPU_INT_STAT_13_IDMAC_TH_31 (0x80000000) //!< Bit mask for IPU_INT_STAT_13_IDMAC_TH_31.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_13_IDMAC_TH_31 from a register value.
|
|
#define BG_IPU_INT_STAT_13_IDMAC_TH_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_13_IDMAC_TH_31) >> BP_IPU_INT_STAT_13_IDMAC_TH_31)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_13_IDMAC_TH_31.
|
|
#define BF_IPU_INT_STAT_13_IDMAC_TH_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_13_IDMAC_TH_31) & BM_IPU_INT_STAT_13_IDMAC_TH_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_31 field to a new value.
|
|
#define BW_IPU_INT_STAT_13_IDMAC_TH_31(x, v) (HW_IPU_INT_STAT_13_WR(x, (HW_IPU_INT_STAT_13_RD(x) & ~BM_IPU_INT_STAT_13_IDMAC_TH_31) | BF_IPU_INT_STAT_13_IDMAC_TH_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_14 - Interrupt Status Register 14
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_14 - Interrupt Status Register 14 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.This register contains
|
|
* part of IPU interrupts status bits. The status bits of the Threshold crossing indication (TH) of
|
|
* DMA Channels interrupts [63:32] can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_14
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_14_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_TH_33 : 1; //!< [1] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_TH_40 : 1; //!< [8] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_41 : 1; //!< [9] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_42 : 1; //!< [10] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_43 : 1; //!< [11] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_44 : 1; //!< [12] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_45 : 1; //!< [13] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_46 : 1; //!< [14] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_47 : 1; //!< [15] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_48 : 1; //!< [16] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_49 : 1; //!< [17] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_50 : 1; //!< [18] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_51 : 1; //!< [19] Threshold crossing indication of Channel interrupt.
|
|
unsigned IDMAC_TH_52 : 1; //!< [20] Threshold crossing indication of Channel interrupt.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_int_stat_14_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_14 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_14_ADDR(x) (REGS_IPU_BASE(x) + 0x234)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_14(x) (*(volatile hw_ipu_int_stat_14_t *) HW_IPU_INT_STAT_14_ADDR(x))
|
|
#define HW_IPU_INT_STAT_14_RD(x) (HW_IPU_INT_STAT_14(x).U)
|
|
#define HW_IPU_INT_STAT_14_WR(x, v) (HW_IPU_INT_STAT_14(x).U = (v))
|
|
#define HW_IPU_INT_STAT_14_SET(x, v) (HW_IPU_INT_STAT_14_WR(x, HW_IPU_INT_STAT_14_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_14_CLR(x, v) (HW_IPU_INT_STAT_14_WR(x, HW_IPU_INT_STAT_14_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_14_TOG(x, v) (HW_IPU_INT_STAT_14_WR(x, HW_IPU_INT_STAT_14_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_14 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_33[1] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_33 (1) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_33.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_33 (0x00000002) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_33.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_33 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_33) >> BP_IPU_INT_STAT_14_IDMAC_TH_33)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_33.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_33) & BM_IPU_INT_STAT_14_IDMAC_TH_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_33 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_33(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_33) | BF_IPU_INT_STAT_14_IDMAC_TH_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_40[8] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_40 (8) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_40.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_40 (0x00000100) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_40.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_40 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_40) >> BP_IPU_INT_STAT_14_IDMAC_TH_40)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_40.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_40) & BM_IPU_INT_STAT_14_IDMAC_TH_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_40 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_40(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_40) | BF_IPU_INT_STAT_14_IDMAC_TH_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_41[9] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_41 (9) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_41.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_41 (0x00000200) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_41.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_41 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_41) >> BP_IPU_INT_STAT_14_IDMAC_TH_41)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_41.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_41) & BM_IPU_INT_STAT_14_IDMAC_TH_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_41 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_41(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_41) | BF_IPU_INT_STAT_14_IDMAC_TH_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_42[10] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_42 (10) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_42.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_42 (0x00000400) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_42.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_42 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_42) >> BP_IPU_INT_STAT_14_IDMAC_TH_42)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_42.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_42) & BM_IPU_INT_STAT_14_IDMAC_TH_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_42 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_42(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_42) | BF_IPU_INT_STAT_14_IDMAC_TH_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_43[11] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_43 (11) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_43.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_43 (0x00000800) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_43.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_43 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_43) >> BP_IPU_INT_STAT_14_IDMAC_TH_43)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_43.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_43) & BM_IPU_INT_STAT_14_IDMAC_TH_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_43 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_43(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_43) | BF_IPU_INT_STAT_14_IDMAC_TH_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_44[12] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_44 (12) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_44.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_44 (0x00001000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_44.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_44 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_44) >> BP_IPU_INT_STAT_14_IDMAC_TH_44)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_44.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_44) & BM_IPU_INT_STAT_14_IDMAC_TH_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_44 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_44(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_44) | BF_IPU_INT_STAT_14_IDMAC_TH_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_45[13] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_45 (13) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_45.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_45 (0x00002000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_45.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_45 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_45) >> BP_IPU_INT_STAT_14_IDMAC_TH_45)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_45.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_45) & BM_IPU_INT_STAT_14_IDMAC_TH_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_45 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_45(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_45) | BF_IPU_INT_STAT_14_IDMAC_TH_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_46[14] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_46 (14) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_46.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_46 (0x00004000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_46.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_46 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_46) >> BP_IPU_INT_STAT_14_IDMAC_TH_46)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_46.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_46) & BM_IPU_INT_STAT_14_IDMAC_TH_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_46 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_46(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_46) | BF_IPU_INT_STAT_14_IDMAC_TH_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_47[15] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_47 (15) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_47.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_47 (0x00008000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_47.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_47 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_47) >> BP_IPU_INT_STAT_14_IDMAC_TH_47)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_47.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_47) & BM_IPU_INT_STAT_14_IDMAC_TH_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_47 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_47(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_47) | BF_IPU_INT_STAT_14_IDMAC_TH_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_48[16] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_48 (16) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_48.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_48 (0x00010000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_48.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_48 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_48) >> BP_IPU_INT_STAT_14_IDMAC_TH_48)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_48.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_48) & BM_IPU_INT_STAT_14_IDMAC_TH_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_48 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_48(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_48) | BF_IPU_INT_STAT_14_IDMAC_TH_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_49[17] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_49 (17) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_49.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_49 (0x00020000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_49.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_49 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_49) >> BP_IPU_INT_STAT_14_IDMAC_TH_49)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_49.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_49) & BM_IPU_INT_STAT_14_IDMAC_TH_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_49 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_49(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_49) | BF_IPU_INT_STAT_14_IDMAC_TH_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_50[18] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_50 (18) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_50.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_50 (0x00040000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_50.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_50 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_50) >> BP_IPU_INT_STAT_14_IDMAC_TH_50)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_50.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_50) & BM_IPU_INT_STAT_14_IDMAC_TH_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_50 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_50(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_50) | BF_IPU_INT_STAT_14_IDMAC_TH_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_51[19] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_51 (19) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_51.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_51 (0x00080000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_51.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_51 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_51) >> BP_IPU_INT_STAT_14_IDMAC_TH_51)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_51.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_51) & BM_IPU_INT_STAT_14_IDMAC_TH_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_51 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_51(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_51) | BF_IPU_INT_STAT_14_IDMAC_TH_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_14, field IDMAC_TH_52[20] (W1C)
|
|
*
|
|
* Threshold crossing indication of Channel interrupt. This bit is the status bit of Threshold
|
|
* crossing interrupt of Channel #n. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_14_IDMAC_TH_52 (20) //!< Bit position for IPU_INT_STAT_14_IDMAC_TH_52.
|
|
#define BM_IPU_INT_STAT_14_IDMAC_TH_52 (0x00100000) //!< Bit mask for IPU_INT_STAT_14_IDMAC_TH_52.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_14_IDMAC_TH_52 from a register value.
|
|
#define BG_IPU_INT_STAT_14_IDMAC_TH_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_14_IDMAC_TH_52) >> BP_IPU_INT_STAT_14_IDMAC_TH_52)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_14_IDMAC_TH_52.
|
|
#define BF_IPU_INT_STAT_14_IDMAC_TH_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_14_IDMAC_TH_52) & BM_IPU_INT_STAT_14_IDMAC_TH_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_TH_52 field to a new value.
|
|
#define BW_IPU_INT_STAT_14_IDMAC_TH_52(x, v) (HW_IPU_INT_STAT_14_WR(x, (HW_IPU_INT_STAT_14_RD(x) & ~BM_IPU_INT_STAT_14_IDMAC_TH_52) | BF_IPU_INT_STAT_14_IDMAC_TH_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_INT_STAT_15 - Interrupt Status Register 15
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_INT_STAT_15 - Interrupt Status Register 15 (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* IPU status registers are not stored in the SRM during power gating mode.IPU status registers are
|
|
* not stored in the SRM during power gating mode.This register contains part of IPU interrupts
|
|
* status bits. The status bits of general purpose interrupts can be found in this register.
|
|
*/
|
|
typedef union _hw_ipu_int_stat_15
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_int_stat_15_bitfields
|
|
{
|
|
unsigned SNOOPING1_INT : 1; //!< [0] IPU snooping 1 event indication interrupt.
|
|
unsigned SNOOPING2_INT : 1; //!< [1] IPU snooping 2 event indication interrupt.
|
|
unsigned DP_SF_START : 1; //!< [2] DP Sync Flow Start indication interrupt.
|
|
unsigned DP_SF_END : 1; //!< [3] DP Sync Flow End indication interrupt.
|
|
unsigned DP_ASF_START : 1; //!< [4] DP Async Flow Start indication interrupt.
|
|
unsigned DP_ASF_END : 1; //!< [5] DP Async Flow End indication interrupt.
|
|
unsigned DP_SF_BRAKE : 1; //!< [6] DP Sync Flow Brake indication interrupt.
|
|
unsigned DP_ASF_BRAKE : 1; //!< [7] DP Async Flow Brake indication interrupt.
|
|
unsigned DC_FC_0 : 1; //!< [8] DC Frame Complete on channel #0 interrupt indication
|
|
unsigned DC_FC_1 : 1; //!< [9] DC Frame Complete on channel #1 interrupt indication
|
|
unsigned DC_FC_2 : 1; //!< [10] DC Frame Complete on channel #2 interrupt indication
|
|
unsigned DC_FC_3 : 1; //!< [11] DC Frame Complete on channel #3 interrupt indication
|
|
unsigned DC_FC_4 : 1; //!< [12] DC Frame Complete on channel #4 interrupt indication
|
|
unsigned DC_FC_6 : 1; //!< [13] DC Frame Complete on channel #6 interrupt indication
|
|
unsigned DI_VSYNC_PRE_0 : 1; //!< [14] DI0 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC sent to the display
|
|
unsigned DI_VSYNC_PRE_1 : 1; //!< [15] DI1 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC sent to the display
|
|
unsigned DC_DP_START : 1; //!< [16] This bit indicates on an interrupt asserted anytime the DP start a new sync or async flow or when an async flow is interrupted by a sync flow
|
|
unsigned DC_ASYNC_STOP : 1; //!< [17] This bit indicates on an interrupt asserted anytime the DP stops an async flow and moves to a sync flow
|
|
unsigned DI0_CNT_EN_PRE_0 : 1; //!< [18] This bit indicates on the interrupt that is a result of a trigger generated by counter #0 of DI0
|
|
unsigned DI0_CNT_EN_PRE_1 : 1; //!< [19] This bit indicates on the interrupt that is a result of a trigger generated by counter #1 of DI0
|
|
unsigned DI0_CNT_EN_PRE_2 : 1; //!< [20] This bit indicates on the interrupt that is a result of a trigger generated by counter #2 of DI0
|
|
unsigned DI0_CNT_EN_PRE_3 : 1; //!< [21] This bit indicates on the interrupt that is a result of a trigger generated by counter #3 of DI0
|
|
unsigned DI0_CNT_EN_PRE_4 : 1; //!< [22] This bit indicates on the interrupt that is a result of a trigger generated by counter #4 of DI0
|
|
unsigned DI0_CNT_EN_PRE_5 : 1; //!< [23] This bit indicates on the interrupt that is a result of a trigger generated by counter #5 of DI0
|
|
unsigned DI0_CNT_EN_PRE_6 : 1; //!< [24] This bit indicates on the interrupt that is a result of a trigger generated by counter #6 of DI0
|
|
unsigned DI0_CNT_EN_PRE_7 : 1; //!< [25] This bit indicates on the interrupt that is a result of a trigger generated by counter #7 of DI0
|
|
unsigned DI0_CNT_EN_PRE_8 : 1; //!< [26] This bit indicates on the interrupt that is a result of a trigger generated by counter #8 of DI0
|
|
unsigned DI0_CNT_EN_PRE_9 : 1; //!< [27] This bit indicates on the interrupt that is a result of a trigger generated by counter #9 of DI0
|
|
unsigned DI0_CNT_EN_PRE_10 : 1; //!< [28] This bit indicates on the interrupt that is a result of a trigger generated by counter #10 of DI0
|
|
unsigned DI1_DISP_CLK_EN_PRE : 1; //!< [29] DI1_DISP_CLK_EN_PRE
|
|
unsigned DI1_CNT_EN_PRE_3 : 1; //!< [30] This bit indicates on the interrupt that is a result of a trigger generated by counter #3 of DI1
|
|
unsigned DI1_CNT_EN_PRE_8 : 1; //!< [31] This bit indicates on the interrupt that is a result of a trigger generated by counter #8 of DI1
|
|
} B;
|
|
} hw_ipu_int_stat_15_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_INT_STAT_15 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_INT_STAT_15_ADDR(x) (REGS_IPU_BASE(x) + 0x238)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_INT_STAT_15(x) (*(volatile hw_ipu_int_stat_15_t *) HW_IPU_INT_STAT_15_ADDR(x))
|
|
#define HW_IPU_INT_STAT_15_RD(x) (HW_IPU_INT_STAT_15(x).U)
|
|
#define HW_IPU_INT_STAT_15_WR(x, v) (HW_IPU_INT_STAT_15(x).U = (v))
|
|
#define HW_IPU_INT_STAT_15_SET(x, v) (HW_IPU_INT_STAT_15_WR(x, HW_IPU_INT_STAT_15_RD(x) | (v)))
|
|
#define HW_IPU_INT_STAT_15_CLR(x, v) (HW_IPU_INT_STAT_15_WR(x, HW_IPU_INT_STAT_15_RD(x) & ~(v)))
|
|
#define HW_IPU_INT_STAT_15_TOG(x, v) (HW_IPU_INT_STAT_15_WR(x, HW_IPU_INT_STAT_15_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_INT_STAT_15 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field SNOOPING1_INT[0] (W1C)
|
|
*
|
|
* IPU snooping 1 event indication interrupt. This bit indicates on the interrupt that is a result
|
|
* of the detection of a snooping 1 signal assertion coming to the
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_SNOOPING1_INT (0) //!< Bit position for IPU_INT_STAT_15_SNOOPING1_INT.
|
|
#define BM_IPU_INT_STAT_15_SNOOPING1_INT (0x00000001) //!< Bit mask for IPU_INT_STAT_15_SNOOPING1_INT.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_SNOOPING1_INT from a register value.
|
|
#define BG_IPU_INT_STAT_15_SNOOPING1_INT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_SNOOPING1_INT) >> BP_IPU_INT_STAT_15_SNOOPING1_INT)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_SNOOPING1_INT.
|
|
#define BF_IPU_INT_STAT_15_SNOOPING1_INT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_SNOOPING1_INT) & BM_IPU_INT_STAT_15_SNOOPING1_INT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SNOOPING1_INT field to a new value.
|
|
#define BW_IPU_INT_STAT_15_SNOOPING1_INT(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_SNOOPING1_INT) | BF_IPU_INT_STAT_15_SNOOPING1_INT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field SNOOPING2_INT[1] (W1C)
|
|
*
|
|
* IPU snooping 2 event indication interrupt. This bit indicates on the interrupt that is a result
|
|
* of the detection of a snooping 2 signal assertion coming to the IPU
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_SNOOPING2_INT (1) //!< Bit position for IPU_INT_STAT_15_SNOOPING2_INT.
|
|
#define BM_IPU_INT_STAT_15_SNOOPING2_INT (0x00000002) //!< Bit mask for IPU_INT_STAT_15_SNOOPING2_INT.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_SNOOPING2_INT from a register value.
|
|
#define BG_IPU_INT_STAT_15_SNOOPING2_INT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_SNOOPING2_INT) >> BP_IPU_INT_STAT_15_SNOOPING2_INT)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_SNOOPING2_INT.
|
|
#define BF_IPU_INT_STAT_15_SNOOPING2_INT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_SNOOPING2_INT) & BM_IPU_INT_STAT_15_SNOOPING2_INT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SNOOPING2_INT field to a new value.
|
|
#define BW_IPU_INT_STAT_15_SNOOPING2_INT(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_SNOOPING2_INT) | BF_IPU_INT_STAT_15_SNOOPING2_INT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DP_SF_START[2] (W1C)
|
|
*
|
|
* DP Sync Flow Start indication interrupt. This bit indicates on the interrupt that is a result of
|
|
* the Sync flow start at the DP
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DP_SF_START (2) //!< Bit position for IPU_INT_STAT_15_DP_SF_START.
|
|
#define BM_IPU_INT_STAT_15_DP_SF_START (0x00000004) //!< Bit mask for IPU_INT_STAT_15_DP_SF_START.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DP_SF_START from a register value.
|
|
#define BG_IPU_INT_STAT_15_DP_SF_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DP_SF_START) >> BP_IPU_INT_STAT_15_DP_SF_START)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DP_SF_START.
|
|
#define BF_IPU_INT_STAT_15_DP_SF_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DP_SF_START) & BM_IPU_INT_STAT_15_DP_SF_START)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_SF_START field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DP_SF_START(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DP_SF_START) | BF_IPU_INT_STAT_15_DP_SF_START(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DP_SF_END[3] (W1C)
|
|
*
|
|
* DP Sync Flow End indication interrupt. This bit indicates on the interrupt that is a result of
|
|
* the Sync flow end at the DP
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DP_SF_END (3) //!< Bit position for IPU_INT_STAT_15_DP_SF_END.
|
|
#define BM_IPU_INT_STAT_15_DP_SF_END (0x00000008) //!< Bit mask for IPU_INT_STAT_15_DP_SF_END.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DP_SF_END from a register value.
|
|
#define BG_IPU_INT_STAT_15_DP_SF_END(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DP_SF_END) >> BP_IPU_INT_STAT_15_DP_SF_END)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DP_SF_END.
|
|
#define BF_IPU_INT_STAT_15_DP_SF_END(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DP_SF_END) & BM_IPU_INT_STAT_15_DP_SF_END)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_SF_END field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DP_SF_END(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DP_SF_END) | BF_IPU_INT_STAT_15_DP_SF_END(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DP_ASF_START[4] (W1C)
|
|
*
|
|
* DP Async Flow Start indication interrupt. This bit indicates on the interrupt that is a result of
|
|
* the Async flow start at the DP
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DP_ASF_START (4) //!< Bit position for IPU_INT_STAT_15_DP_ASF_START.
|
|
#define BM_IPU_INT_STAT_15_DP_ASF_START (0x00000010) //!< Bit mask for IPU_INT_STAT_15_DP_ASF_START.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DP_ASF_START from a register value.
|
|
#define BG_IPU_INT_STAT_15_DP_ASF_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DP_ASF_START) >> BP_IPU_INT_STAT_15_DP_ASF_START)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DP_ASF_START.
|
|
#define BF_IPU_INT_STAT_15_DP_ASF_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DP_ASF_START) & BM_IPU_INT_STAT_15_DP_ASF_START)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASF_START field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DP_ASF_START(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DP_ASF_START) | BF_IPU_INT_STAT_15_DP_ASF_START(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DP_ASF_END[5] (W1C)
|
|
*
|
|
* DP Async Flow End indication interrupt. This bit indicates on the interrupt that is a result of
|
|
* the Async flow end at the DP
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DP_ASF_END (5) //!< Bit position for IPU_INT_STAT_15_DP_ASF_END.
|
|
#define BM_IPU_INT_STAT_15_DP_ASF_END (0x00000020) //!< Bit mask for IPU_INT_STAT_15_DP_ASF_END.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DP_ASF_END from a register value.
|
|
#define BG_IPU_INT_STAT_15_DP_ASF_END(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DP_ASF_END) >> BP_IPU_INT_STAT_15_DP_ASF_END)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DP_ASF_END.
|
|
#define BF_IPU_INT_STAT_15_DP_ASF_END(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DP_ASF_END) & BM_IPU_INT_STAT_15_DP_ASF_END)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASF_END field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DP_ASF_END(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DP_ASF_END) | BF_IPU_INT_STAT_15_DP_ASF_END(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DP_SF_BRAKE[6] (W1C)
|
|
*
|
|
* DP Sync Flow Brake indication interrupt. This bit indicates on the interrupt that is a result of
|
|
* the Sync flow brake at the DP
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DP_SF_BRAKE (6) //!< Bit position for IPU_INT_STAT_15_DP_SF_BRAKE.
|
|
#define BM_IPU_INT_STAT_15_DP_SF_BRAKE (0x00000040) //!< Bit mask for IPU_INT_STAT_15_DP_SF_BRAKE.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DP_SF_BRAKE from a register value.
|
|
#define BG_IPU_INT_STAT_15_DP_SF_BRAKE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DP_SF_BRAKE) >> BP_IPU_INT_STAT_15_DP_SF_BRAKE)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DP_SF_BRAKE.
|
|
#define BF_IPU_INT_STAT_15_DP_SF_BRAKE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DP_SF_BRAKE) & BM_IPU_INT_STAT_15_DP_SF_BRAKE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_SF_BRAKE field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DP_SF_BRAKE(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DP_SF_BRAKE) | BF_IPU_INT_STAT_15_DP_SF_BRAKE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DP_ASF_BRAKE[7] (W1C)
|
|
*
|
|
* DP Async Flow Brake indication interrupt. This bit indicates on the interrupt that is a result of
|
|
* the async flow brake at the DP
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DP_ASF_BRAKE (7) //!< Bit position for IPU_INT_STAT_15_DP_ASF_BRAKE.
|
|
#define BM_IPU_INT_STAT_15_DP_ASF_BRAKE (0x00000080) //!< Bit mask for IPU_INT_STAT_15_DP_ASF_BRAKE.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DP_ASF_BRAKE from a register value.
|
|
#define BG_IPU_INT_STAT_15_DP_ASF_BRAKE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DP_ASF_BRAKE) >> BP_IPU_INT_STAT_15_DP_ASF_BRAKE)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DP_ASF_BRAKE.
|
|
#define BF_IPU_INT_STAT_15_DP_ASF_BRAKE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DP_ASF_BRAKE) & BM_IPU_INT_STAT_15_DP_ASF_BRAKE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_ASF_BRAKE field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DP_ASF_BRAKE(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DP_ASF_BRAKE) | BF_IPU_INT_STAT_15_DP_ASF_BRAKE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DC_FC_0[8] (W1C)
|
|
*
|
|
* DC Frame Complete on channel #0 interrupt indication
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_FC_0 (8) //!< Bit position for IPU_INT_STAT_15_DC_FC_0.
|
|
#define BM_IPU_INT_STAT_15_DC_FC_0 (0x00000100) //!< Bit mask for IPU_INT_STAT_15_DC_FC_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DC_FC_0 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DC_FC_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_FC_0) >> BP_IPU_INT_STAT_15_DC_FC_0)
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|
|
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//! @brief Format value for bitfield IPU_INT_STAT_15_DC_FC_0.
|
|
#define BF_IPU_INT_STAT_15_DC_FC_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_FC_0) & BM_IPU_INT_STAT_15_DC_FC_0)
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|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_FC_0(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_FC_0) | BF_IPU_INT_STAT_15_DC_FC_0(v)))
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#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_15, field DC_FC_1[9] (W1C)
|
|
*
|
|
* DC Frame Complete on channel #1 interrupt indication
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_FC_1 (9) //!< Bit position for IPU_INT_STAT_15_DC_FC_1.
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#define BM_IPU_INT_STAT_15_DC_FC_1 (0x00000200) //!< Bit mask for IPU_INT_STAT_15_DC_FC_1.
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//! @brief Get value of IPU_INT_STAT_15_DC_FC_1 from a register value.
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|
#define BG_IPU_INT_STAT_15_DC_FC_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_FC_1) >> BP_IPU_INT_STAT_15_DC_FC_1)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DC_FC_1.
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|
#define BF_IPU_INT_STAT_15_DC_FC_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_FC_1) & BM_IPU_INT_STAT_15_DC_FC_1)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_FC_1(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_FC_1) | BF_IPU_INT_STAT_15_DC_FC_1(v)))
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#endif
|
|
//@}
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/*! @name Register IPU_INT_STAT_15, field DC_FC_2[10] (W1C)
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*
|
|
* DC Frame Complete on channel #2 interrupt indication
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
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|
*/
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//@{
|
|
#define BP_IPU_INT_STAT_15_DC_FC_2 (10) //!< Bit position for IPU_INT_STAT_15_DC_FC_2.
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#define BM_IPU_INT_STAT_15_DC_FC_2 (0x00000400) //!< Bit mask for IPU_INT_STAT_15_DC_FC_2.
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//! @brief Get value of IPU_INT_STAT_15_DC_FC_2 from a register value.
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|
#define BG_IPU_INT_STAT_15_DC_FC_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_FC_2) >> BP_IPU_INT_STAT_15_DC_FC_2)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DC_FC_2.
|
|
#define BF_IPU_INT_STAT_15_DC_FC_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_FC_2) & BM_IPU_INT_STAT_15_DC_FC_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_2 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_FC_2(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_FC_2) | BF_IPU_INT_STAT_15_DC_FC_2(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_15, field DC_FC_3[11] (W1C)
|
|
*
|
|
* DC Frame Complete on channel #3 interrupt indication
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_FC_3 (11) //!< Bit position for IPU_INT_STAT_15_DC_FC_3.
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|
#define BM_IPU_INT_STAT_15_DC_FC_3 (0x00000800) //!< Bit mask for IPU_INT_STAT_15_DC_FC_3.
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|
|
|
//! @brief Get value of IPU_INT_STAT_15_DC_FC_3 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DC_FC_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_FC_3) >> BP_IPU_INT_STAT_15_DC_FC_3)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DC_FC_3.
|
|
#define BF_IPU_INT_STAT_15_DC_FC_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_FC_3) & BM_IPU_INT_STAT_15_DC_FC_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_3 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_FC_3(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_FC_3) | BF_IPU_INT_STAT_15_DC_FC_3(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DC_FC_4[12] (W1C)
|
|
*
|
|
* DC Frame Complete on channel #4 interrupt indication
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_FC_4 (12) //!< Bit position for IPU_INT_STAT_15_DC_FC_4.
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|
#define BM_IPU_INT_STAT_15_DC_FC_4 (0x00001000) //!< Bit mask for IPU_INT_STAT_15_DC_FC_4.
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|
|
|
//! @brief Get value of IPU_INT_STAT_15_DC_FC_4 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DC_FC_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_FC_4) >> BP_IPU_INT_STAT_15_DC_FC_4)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DC_FC_4.
|
|
#define BF_IPU_INT_STAT_15_DC_FC_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_FC_4) & BM_IPU_INT_STAT_15_DC_FC_4)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_4 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_FC_4(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_FC_4) | BF_IPU_INT_STAT_15_DC_FC_4(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DC_FC_6[13] (W1C)
|
|
*
|
|
* DC Frame Complete on channel #6 interrupt indication
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_FC_6 (13) //!< Bit position for IPU_INT_STAT_15_DC_FC_6.
|
|
#define BM_IPU_INT_STAT_15_DC_FC_6 (0x00002000) //!< Bit mask for IPU_INT_STAT_15_DC_FC_6.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DC_FC_6 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DC_FC_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_FC_6) >> BP_IPU_INT_STAT_15_DC_FC_6)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DC_FC_6.
|
|
#define BF_IPU_INT_STAT_15_DC_FC_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_FC_6) & BM_IPU_INT_STAT_15_DC_FC_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_FC_6 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_FC_6(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_FC_6) | BF_IPU_INT_STAT_15_DC_FC_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI_VSYNC_PRE_0[14] (W1C)
|
|
*
|
|
* DI0 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC sent to the display
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI_VSYNC_PRE_0 (14) //!< Bit position for IPU_INT_STAT_15_DI_VSYNC_PRE_0.
|
|
#define BM_IPU_INT_STAT_15_DI_VSYNC_PRE_0 (0x00004000) //!< Bit mask for IPU_INT_STAT_15_DI_VSYNC_PRE_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI_VSYNC_PRE_0 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI_VSYNC_PRE_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI_VSYNC_PRE_0) >> BP_IPU_INT_STAT_15_DI_VSYNC_PRE_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI_VSYNC_PRE_0.
|
|
#define BF_IPU_INT_STAT_15_DI_VSYNC_PRE_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI_VSYNC_PRE_0) & BM_IPU_INT_STAT_15_DI_VSYNC_PRE_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_VSYNC_PRE_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI_VSYNC_PRE_0(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI_VSYNC_PRE_0) | BF_IPU_INT_STAT_15_DI_VSYNC_PRE_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI_VSYNC_PRE_1[15] (W1C)
|
|
*
|
|
* DI1 interrupt indicating of a VSYNC signal asserted 2 rows before the VSYNC sent to the display
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI_VSYNC_PRE_1 (15) //!< Bit position for IPU_INT_STAT_15_DI_VSYNC_PRE_1.
|
|
#define BM_IPU_INT_STAT_15_DI_VSYNC_PRE_1 (0x00008000) //!< Bit mask for IPU_INT_STAT_15_DI_VSYNC_PRE_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI_VSYNC_PRE_1 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI_VSYNC_PRE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI_VSYNC_PRE_1) >> BP_IPU_INT_STAT_15_DI_VSYNC_PRE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI_VSYNC_PRE_1.
|
|
#define BF_IPU_INT_STAT_15_DI_VSYNC_PRE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI_VSYNC_PRE_1) & BM_IPU_INT_STAT_15_DI_VSYNC_PRE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_VSYNC_PRE_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI_VSYNC_PRE_1(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI_VSYNC_PRE_1) | BF_IPU_INT_STAT_15_DI_VSYNC_PRE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DC_DP_START[16] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt asserted anytime the DP start a new sync or async flow or when
|
|
* an async flow is interrupted by a sync flow
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_DP_START (16) //!< Bit position for IPU_INT_STAT_15_DC_DP_START.
|
|
#define BM_IPU_INT_STAT_15_DC_DP_START (0x00010000) //!< Bit mask for IPU_INT_STAT_15_DC_DP_START.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DC_DP_START from a register value.
|
|
#define BG_IPU_INT_STAT_15_DC_DP_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_DP_START) >> BP_IPU_INT_STAT_15_DC_DP_START)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DC_DP_START.
|
|
#define BF_IPU_INT_STAT_15_DC_DP_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_DP_START) & BM_IPU_INT_STAT_15_DC_DP_START)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_DP_START field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_DP_START(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_DP_START) | BF_IPU_INT_STAT_15_DC_DP_START(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DC_ASYNC_STOP[17] (W1C)
|
|
*
|
|
* This bit indicates on an interrupt asserted anytime the DP stops an async flow and moves to a
|
|
* sync flow
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DC_ASYNC_STOP (17) //!< Bit position for IPU_INT_STAT_15_DC_ASYNC_STOP.
|
|
#define BM_IPU_INT_STAT_15_DC_ASYNC_STOP (0x00020000) //!< Bit mask for IPU_INT_STAT_15_DC_ASYNC_STOP.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DC_ASYNC_STOP from a register value.
|
|
#define BG_IPU_INT_STAT_15_DC_ASYNC_STOP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DC_ASYNC_STOP) >> BP_IPU_INT_STAT_15_DC_ASYNC_STOP)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DC_ASYNC_STOP.
|
|
#define BF_IPU_INT_STAT_15_DC_ASYNC_STOP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DC_ASYNC_STOP) & BM_IPU_INT_STAT_15_DC_ASYNC_STOP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_ASYNC_STOP field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DC_ASYNC_STOP(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DC_ASYNC_STOP) | BF_IPU_INT_STAT_15_DC_ASYNC_STOP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_0[18] (W1C)
|
|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #0 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0 (18) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_0.
|
|
#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0 (0x00040000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_0.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_0 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_0.
|
|
#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_0 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_1[19] (W1C)
|
|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #1 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1 (19) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_1.
|
|
#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1 (0x00080000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_1.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_1 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_1.
|
|
#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_1 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_2[20] (W1C)
|
|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #2 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2 (20) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_2.
|
|
#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2 (0x00100000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_2.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_2 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_2.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_2 field to a new value.
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#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_2(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_3[21] (W1C)
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*
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* This bit indicates on the interrupt that is a result of a trigger generated by counter #3 of DI0
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*
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* Values:
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* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3 (21) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_3.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3 (0x00200000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_3.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_3 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_3.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_3 field to a new value.
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#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_3(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_4[22] (W1C)
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*
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* This bit indicates on the interrupt that is a result of a trigger generated by counter #4 of DI0
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*
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* Values:
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* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4 (22) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_4.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4 (0x00400000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_4.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_4 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_4.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_4 field to a new value.
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#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_4(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_5[23] (W1C)
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*
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* This bit indicates on the interrupt that is a result of a trigger generated by counter #5 of DI0
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*
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* Values:
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* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5 (23) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_5.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5 (0x00800000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_5.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_5 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_5.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_5 field to a new value.
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#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_5(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_6[24] (W1C)
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*
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* This bit indicates on the interrupt that is a result of a trigger generated by counter #6 of DI0
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*
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* Values:
|
|
* - 0 - Interrupt is cleared.
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* - 1 - Interrupt is requested.
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*/
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//@{
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#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6 (24) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_6.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6 (0x01000000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_6.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_6 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_6.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_EN_PRE_6 field to a new value.
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|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_6(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_7[25] (W1C)
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*
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|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #7 of DI0
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
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|
* - 1 - Interrupt is requested.
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|
*/
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//@{
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#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7 (25) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_7.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7 (0x02000000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_7.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_7 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_7.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7)
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|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_EN_PRE_7 field to a new value.
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|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_7(v)))
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#endif
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//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_8[26] (W1C)
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|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #8 of DI0
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|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
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|
*/
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|
//@{
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|
#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8 (26) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_8.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8 (0x04000000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_8.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_8 from a register value.
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#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_8.
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#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_EN_PRE_8 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_8(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_9[27] (W1C)
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|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #9 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
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|
//@{
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|
#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9 (27) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_9.
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#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9 (0x08000000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_9.
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//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_9 from a register value.
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|
#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9)
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//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_9.
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|
#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_9 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_9(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_INT_STAT_15, field DI0_CNT_EN_PRE_10[28] (W1C)
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|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #10 of DI0
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10 (28) //!< Bit position for IPU_INT_STAT_15_DI0_CNT_EN_PRE_10.
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|
#define BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10 (0x10000000) //!< Bit mask for IPU_INT_STAT_15_DI0_CNT_EN_PRE_10.
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|
//! @brief Get value of IPU_INT_STAT_15_DI0_CNT_EN_PRE_10 from a register value.
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|
#define BG_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10) >> BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10)
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|
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|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI0_CNT_EN_PRE_10.
|
|
#define BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10) & BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_EN_PRE_10 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10) | BF_IPU_INT_STAT_15_DI0_CNT_EN_PRE_10(v)))
|
|
#endif
|
|
//@}
|
|
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|
/*! @name Register IPU_INT_STAT_15, field DI1_DISP_CLK_EN_PRE[29] (W1C)
|
|
*
|
|
* DI1_DISP_CLK_EN_PRE
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE (29) //!< Bit position for IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE.
|
|
#define BM_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE (0x20000000) //!< Bit mask for IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE) >> BP_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE)
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|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE.
|
|
#define BF_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE) & BM_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLK_EN_PRE field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE) | BF_IPU_INT_STAT_15_DI1_DISP_CLK_EN_PRE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI1_CNT_EN_PRE_3[30] (W1C)
|
|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #3 of DI1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3 (30) //!< Bit position for IPU_INT_STAT_15_DI1_CNT_EN_PRE_3.
|
|
#define BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3 (0x40000000) //!< Bit mask for IPU_INT_STAT_15_DI1_CNT_EN_PRE_3.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI1_CNT_EN_PRE_3 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3) >> BP_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI1_CNT_EN_PRE_3.
|
|
#define BF_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3) & BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_EN_PRE_3 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3) | BF_IPU_INT_STAT_15_DI1_CNT_EN_PRE_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_INT_STAT_15, field DI1_CNT_EN_PRE_8[31] (W1C)
|
|
*
|
|
* This bit indicates on the interrupt that is a result of a trigger generated by counter #8 of DI1
|
|
*
|
|
* Values:
|
|
* - 0 - Interrupt is cleared.
|
|
* - 1 - Interrupt is requested.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8 (31) //!< Bit position for IPU_INT_STAT_15_DI1_CNT_EN_PRE_8.
|
|
#define BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8 (0x80000000) //!< Bit mask for IPU_INT_STAT_15_DI1_CNT_EN_PRE_8.
|
|
|
|
//! @brief Get value of IPU_INT_STAT_15_DI1_CNT_EN_PRE_8 from a register value.
|
|
#define BG_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8) >> BP_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8)
|
|
|
|
//! @brief Format value for bitfield IPU_INT_STAT_15_DI1_CNT_EN_PRE_8.
|
|
#define BF_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8) & BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_EN_PRE_8 field to a new value.
|
|
#define BW_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8(x, v) (HW_IPU_INT_STAT_15_WR(x, (HW_IPU_INT_STAT_15_RD(x) & ~BM_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8) | BF_IPU_INT_STAT_15_DI1_CNT_EN_PRE_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CUR_BUF_0 - Current Buffer Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CUR_BUF_0 - Current Buffer Register 0 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information bit for each DMA channel.
|
|
*/
|
|
typedef union _hw_ipu_cur_buf_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_cur_buf_0_bitfields
|
|
{
|
|
unsigned DMA_CH_CUR_BUF_0 : 1; //!< [0] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_1 : 1; //!< [1] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_2 : 1; //!< [2] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_3 : 1; //!< [3] Current Buffer.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned DMA_CH_CUR_BUF_5 : 1; //!< [5] Current Buffer.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned DMA_CH_CUR_BUF_8 : 1; //!< [8] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_9 : 1; //!< [9] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_10 : 1; //!< [10] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_11 : 1; //!< [11] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_12 : 1; //!< [12] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_13 : 1; //!< [13] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_14 : 1; //!< [14] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_15 : 1; //!< [15] Current Buffer.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned DMA_CH_CUR_BUF_17 : 1; //!< [17] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_18 : 1; //!< [18] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_19 : 1; //!< [19] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_20 : 1; //!< [20] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_21 : 1; //!< [21] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_22 : 1; //!< [22] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_23 : 1; //!< [23] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_24 : 1; //!< [24] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_25 : 1; //!< [25] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_26 : 1; //!< [26] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_27 : 1; //!< [27] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_28 : 1; //!< [28] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_29 : 1; //!< [29] Current Buffer.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned DMA_CH_CUR_BUF_31 : 1; //!< [31] Current Buffer.
|
|
} B;
|
|
} hw_ipu_cur_buf_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CUR_BUF_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CUR_BUF_0_ADDR(x) (REGS_IPU_BASE(x) + 0x23c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CUR_BUF_0(x) (*(volatile hw_ipu_cur_buf_0_t *) HW_IPU_CUR_BUF_0_ADDR(x))
|
|
#define HW_IPU_CUR_BUF_0_RD(x) (HW_IPU_CUR_BUF_0(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CUR_BUF_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_0[0] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0 (0) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0 (0x00000001) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_1[1] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1 (1) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1 (0x00000002) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_2[2] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2 (2) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2 (0x00000004) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_2)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_3[3] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3 (3) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3 (0x00000008) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_3)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_5[5] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5 (5) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5 (0x00000020) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_5)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_8[8] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8 (8) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8 (0x00000100) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_8)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_9[9] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9 (9) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9 (0x00000200) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_9)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_10[10] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10 (10) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10 (0x00000400) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_10)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_11[11] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11 (11) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11 (0x00000800) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_11)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_12[12] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12 (12) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12 (0x00001000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_12)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_13[13] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13 (13) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13 (0x00002000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_13)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_14[14] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14 (14) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14 (0x00004000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_14)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_15[15] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15 (15) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15 (0x00008000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_15)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_17[17] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17 (17) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17 (0x00020000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_17)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_18[18] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18 (18) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18 (0x00040000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_18)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_19[19] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19 (19) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19 (0x00080000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_19)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_20[20] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20 (20) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20 (0x00100000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_20)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_21[21] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21 (21) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21 (0x00200000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_21)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_22[22] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22 (22) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22 (0x00400000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_22)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_23[23] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23 (23) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23 (0x00800000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_23)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_24[24] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24 (24) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24 (0x01000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_24)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_25[25] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25 (25) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25 (0x02000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_25)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_26[26] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26 (26) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26 (0x04000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_26)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_27[27] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27 (27) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27 (0x08000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_27)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_28[28] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28 (28) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28 (0x10000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_28)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_29[29] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29 (29) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29 (0x20000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_29)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_0, field DMA_CH_CUR_BUF_31[31] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31 (31) //!< Bit position for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31.
|
|
#define BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31 (0x80000000) //!< Bit mask for IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31 from a register value.
|
|
#define BG_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31) >> BP_IPU_CUR_BUF_0_DMA_CH_CUR_BUF_31)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CUR_BUF_1 - Current Buffer Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CUR_BUF_1 - Current Buffer Register 1 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information bit for each DMA channel.
|
|
*/
|
|
typedef union _hw_ipu_cur_buf_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_cur_buf_1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned DMA_CH_CUR_BUF_33 : 1; //!< [1] Current Buffer.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned DMA_CH_CUR_BUF_40 : 1; //!< [8] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_41 : 1; //!< [9] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_42 : 1; //!< [10] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_43 : 1; //!< [11] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_44 : 1; //!< [12] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_45 : 1; //!< [13] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_46 : 1; //!< [14] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_47 : 1; //!< [15] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_48 : 1; //!< [16] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_49 : 1; //!< [17] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_50 : 1; //!< [18] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_51 : 1; //!< [19] Current Buffer.
|
|
unsigned DMA_CH_CUR_BUF_52 : 1; //!< [20] Current Buffer.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_cur_buf_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CUR_BUF_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CUR_BUF_1_ADDR(x) (REGS_IPU_BASE(x) + 0x240)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CUR_BUF_1(x) (*(volatile hw_ipu_cur_buf_1_t *) HW_IPU_CUR_BUF_1_ADDR(x))
|
|
#define HW_IPU_CUR_BUF_1_RD(x) (HW_IPU_CUR_BUF_1(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CUR_BUF_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_33[1] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33 (1) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33 (0x00000002) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_33)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_40[8] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40 (8) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40 (0x00000100) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_40)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_41[9] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41 (9) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41 (0x00000200) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_41)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_42[10] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42 (10) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42 (0x00000400) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_42)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_43[11] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43 (11) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43 (0x00000800) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_43)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_44[12] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44 (12) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44 (0x00001000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_44)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_45[13] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45 (13) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45 (0x00002000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_45)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_46[14] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46 (14) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46 (0x00004000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_46)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_47[15] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47 (15) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47 (0x00008000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_47)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_48[16] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48 (16) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48 (0x00010000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_48)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_49[17] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49 (17) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49 (0x00020000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_49)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_50[18] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50 (18) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50 (0x00040000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_50)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_51[19] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51 (19) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51 (0x00080000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_51)
|
|
//@}
|
|
|
|
/*! @name Register IPU_CUR_BUF_1, field DMA_CH_CUR_BUF_52[20] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52 (20) //!< Bit position for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52.
|
|
#define BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52 (0x00100000) //!< Bit mask for IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52.
|
|
|
|
//! @brief Get value of IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52 from a register value.
|
|
#define BG_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52) >> BP_IPU_CUR_BUF_1_DMA_CH_CUR_BUF_52)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CUR_0 - Alternate Current Buffer Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CUR_0 - Alternate Current Buffer Register 0 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information bit for each DMA channel.
|
|
*/
|
|
typedef union _hw_ipu_alt_cur_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_cur_0_bitfields
|
|
{
|
|
unsigned RESERVED0 : 24; //!< [23:0] Reserved.
|
|
unsigned DMA_CH_ALT_CUR_BUF_24 : 1; //!< [24] Current Buffer.
|
|
unsigned RESERVED1 : 4; //!< [28:25] Reserved.
|
|
unsigned DMA_CH_ALT_CUR_BUF_29 : 1; //!< [29] Current Buffer.
|
|
unsigned RESERVED2 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_cur_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CUR_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CUR_0_ADDR(x) (REGS_IPU_BASE(x) + 0x244)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CUR_0(x) (*(volatile hw_ipu_alt_cur_0_t *) HW_IPU_ALT_CUR_0_ADDR(x))
|
|
#define HW_IPU_ALT_CUR_0_RD(x) (HW_IPU_ALT_CUR_0(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CUR_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_ALT_CUR_0, field DMA_CH_ALT_CUR_BUF_24[24] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24 (24) //!< Bit position for IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24.
|
|
#define BM_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24 (0x01000000) //!< Bit mask for IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24.
|
|
|
|
//! @brief Get value of IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24 from a register value.
|
|
#define BG_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24) >> BP_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_24)
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CUR_0, field DMA_CH_ALT_CUR_BUF_29[29] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29 (29) //!< Bit position for IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29.
|
|
#define BM_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29 (0x20000000) //!< Bit mask for IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29.
|
|
|
|
//! @brief Get value of IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29 from a register value.
|
|
#define BG_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29) >> BP_IPU_ALT_CUR_0_DMA_CH_ALT_CUR_BUF_29)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CUR_1 - Alternate Current Buffer Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CUR_1 - Alternate Current Buffer Register 1 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information bit for each DMA channel. The
|
|
* register is shown in VDI Plane Size Register 4 , and the register fields are described in VDI
|
|
* Plane Size Register 4 .
|
|
*/
|
|
typedef union _hw_ipu_alt_cur_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_cur_1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Current Buffer.
|
|
unsigned DMA_CH_ALT_CUR_BUF0_N : 1; //!< [1] Current Buffer.
|
|
unsigned RESERVED1 : 7; //!< [8:2] Current Buffer.
|
|
unsigned DMA_CH_ALT_CUR_BUF1_N : 1; //!< [9] Current Buffer.
|
|
unsigned RESERVED2 : 10; //!< [19:10] Current Buffer.
|
|
unsigned DMA_CH_ALT_CUR_BUF_52 : 1; //!< [20] Current Buffer.
|
|
unsigned RESERVED3 : 11; //!< [31:21] Current Buffer.
|
|
} B;
|
|
} hw_ipu_alt_cur_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CUR_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CUR_1_ADDR(x) (REGS_IPU_BASE(x) + 0x248)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CUR_1(x) (*(volatile hw_ipu_alt_cur_1_t *) HW_IPU_ALT_CUR_1_ADDR(x))
|
|
#define HW_IPU_ALT_CUR_1_RD(x) (HW_IPU_ALT_CUR_1(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CUR_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_ALT_CUR_1, field DMA_CH_ALT_CUR_BUF0_N[1] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N (1) //!< Bit position for IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N.
|
|
#define BM_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N (0x00000002) //!< Bit mask for IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N.
|
|
|
|
//! @brief Get value of IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N from a register value.
|
|
#define BG_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N) >> BP_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF0_N)
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CUR_1, field DMA_CH_ALT_CUR_BUF1_N[9] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N (9) //!< Bit position for IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N.
|
|
#define BM_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N (0x00000200) //!< Bit mask for IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N.
|
|
|
|
//! @brief Get value of IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N from a register value.
|
|
#define BG_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N) >> BP_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF1_N)
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CUR_1, field DMA_CH_ALT_CUR_BUF_52[20] (RO)
|
|
*
|
|
* Current Buffer. This bit indicates which buffer is in use by DMA when double buffer mode is
|
|
* selected. n Indicates the corresponding DMA channel number.
|
|
*
|
|
* Values:
|
|
* - 0 - Current buffer used by DMA is buffer 0.
|
|
* - 1 - Current buffer used by DMA is buffer 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52 (20) //!< Bit position for IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52.
|
|
#define BM_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52 (0x00100000) //!< Bit mask for IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52.
|
|
|
|
//! @brief Get value of IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52 from a register value.
|
|
#define BG_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52) >> BP_IPU_ALT_CUR_1_DMA_CH_ALT_CUR_BUF_52)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SRM_STAT - Shadow Registers Memory Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SRM_STAT - Shadow Registers Memory Status Register (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains status bits of SRM updates. There is a bit for each block. The bit is set
|
|
* when the SRM is currently updating the module's registers. When the SRM completes updating the
|
|
* registers of the block the bit is cleared. SW should not update the block's registers while it is
|
|
* being updated by the SRM.
|
|
*/
|
|
typedef union _hw_ipu_srm_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_srm_stat_bitfields
|
|
{
|
|
unsigned DP_S_SRM_STAT : 1; //!< [0] DP SYNC FLOW SRM STAT
|
|
unsigned DP_A0_SRM_STAT : 1; //!< [1] DP ASYNC0 FLOW SRM STAT
|
|
unsigned DP_A1_SRM_STAT : 1; //!< [2] DP ASYNC1 FLOW SRM STAT
|
|
unsigned RESERVED0 : 1; //!< [3] Reserved
|
|
unsigned DC_2_SRM_STAT : 1; //!< [4] DC group #2 SRM STAT
|
|
unsigned DC_6_SRM_STAT : 1; //!< [5] DC group #6 SRM STAT
|
|
unsigned CSI0_SRM_STAT : 1; //!< [6] CSI1_SRM_STAT
|
|
unsigned CSI1_SRM_STAT : 1; //!< [7] CSI1_SRM_STAT
|
|
unsigned DI0_SRM_STAT : 1; //!< [8] DI0 SRM STAT
|
|
unsigned DI1_SRM_STAT : 1; //!< [9] DI1 SRM STAT
|
|
unsigned RESERVED1 : 22; //!< [31:10] Reserved
|
|
} B;
|
|
} hw_ipu_srm_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SRM_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SRM_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x24c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SRM_STAT(x) (*(volatile hw_ipu_srm_stat_t *) HW_IPU_SRM_STAT_ADDR(x))
|
|
#define HW_IPU_SRM_STAT_RD(x) (HW_IPU_SRM_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SRM_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DP_S_SRM_STAT[0] (RO)
|
|
*
|
|
* DP SYNC FLOW SRM STAT This bit indicates that the SRM is currently updating the DP sync flow
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DP sync flow registers
|
|
* - 1 - SRM is busy updating the DP sync flow registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DP_S_SRM_STAT (0) //!< Bit position for IPU_SRM_STAT_DP_S_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DP_S_SRM_STAT (0x00000001) //!< Bit mask for IPU_SRM_STAT_DP_S_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DP_S_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DP_S_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DP_S_SRM_STAT) >> BP_IPU_SRM_STAT_DP_S_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DP_A0_SRM_STAT[1] (RO)
|
|
*
|
|
* DP ASYNC0 FLOW SRM STAT This bit indicates that the SRM is currently updating the DP async flow 0
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DP async flow 0 registers
|
|
* - 1 - SRM is busy updating the DP async flow 0 registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DP_A0_SRM_STAT (1) //!< Bit position for IPU_SRM_STAT_DP_A0_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DP_A0_SRM_STAT (0x00000002) //!< Bit mask for IPU_SRM_STAT_DP_A0_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DP_A0_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DP_A0_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DP_A0_SRM_STAT) >> BP_IPU_SRM_STAT_DP_A0_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DP_A1_SRM_STAT[2] (RO)
|
|
*
|
|
* DP ASYNC1 FLOW SRM STAT This bit indicates that the SRM is currently updating the DP async flow 1
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DP sync flow registers
|
|
* - 1 - SRM is busy updating the DP sync flow registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DP_A1_SRM_STAT (2) //!< Bit position for IPU_SRM_STAT_DP_A1_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DP_A1_SRM_STAT (0x00000004) //!< Bit mask for IPU_SRM_STAT_DP_A1_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DP_A1_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DP_A1_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DP_A1_SRM_STAT) >> BP_IPU_SRM_STAT_DP_A1_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DC_2_SRM_STAT[4] (RO)
|
|
*
|
|
* DC group #2 SRM STAT This bit indicates that the SRM is currently updating the DC group #2
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DC group #2 registers
|
|
* - 1 - SRM is busy updating the DC group #6 registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DC_2_SRM_STAT (4) //!< Bit position for IPU_SRM_STAT_DC_2_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DC_2_SRM_STAT (0x00000010) //!< Bit mask for IPU_SRM_STAT_DC_2_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DC_2_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DC_2_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DC_2_SRM_STAT) >> BP_IPU_SRM_STAT_DC_2_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DC_6_SRM_STAT[5] (RO)
|
|
*
|
|
* DC group #6 SRM STAT This bit indicates that the SRM is currently updating the DC group #6
|
|
* registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DC registers
|
|
* - 1 - SRM is busy updating the DC registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DC_6_SRM_STAT (5) //!< Bit position for IPU_SRM_STAT_DC_6_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DC_6_SRM_STAT (0x00000020) //!< Bit mask for IPU_SRM_STAT_DC_6_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DC_6_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DC_6_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DC_6_SRM_STAT) >> BP_IPU_SRM_STAT_DC_6_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field CSI0_SRM_STAT[6] (RO)
|
|
*
|
|
* CSI1_SRM_STAT
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_CSI0_SRM_STAT (6) //!< Bit position for IPU_SRM_STAT_CSI0_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_CSI0_SRM_STAT (0x00000040) //!< Bit mask for IPU_SRM_STAT_CSI0_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_CSI0_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_CSI0_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_CSI0_SRM_STAT) >> BP_IPU_SRM_STAT_CSI0_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field CSI1_SRM_STAT[7] (RO)
|
|
*
|
|
* CSI1_SRM_STAT
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_CSI1_SRM_STAT (7) //!< Bit position for IPU_SRM_STAT_CSI1_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_CSI1_SRM_STAT (0x00000080) //!< Bit mask for IPU_SRM_STAT_CSI1_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_CSI1_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_CSI1_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_CSI1_SRM_STAT) >> BP_IPU_SRM_STAT_CSI1_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DI0_SRM_STAT[8] (RO)
|
|
*
|
|
* DI0 SRM STAT This bit indicates that the SRM is currently updating the DI0 registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DI0 registers
|
|
* - 1 - SRM is busy updating the DI0 registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DI0_SRM_STAT (8) //!< Bit position for IPU_SRM_STAT_DI0_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DI0_SRM_STAT (0x00000100) //!< Bit mask for IPU_SRM_STAT_DI0_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DI0_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DI0_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DI0_SRM_STAT) >> BP_IPU_SRM_STAT_DI0_SRM_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_SRM_STAT, field DI1_SRM_STAT[9] (RO)
|
|
*
|
|
* DI1 SRM STAT This bit indicates that the SRM is currently updating the DI1 registers
|
|
*
|
|
* Values:
|
|
* - 0 - SRM is not updating the DI1 registers
|
|
* - 1 - SRM is busy updating the DI1 registers
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SRM_STAT_DI1_SRM_STAT (9) //!< Bit position for IPU_SRM_STAT_DI1_SRM_STAT.
|
|
#define BM_IPU_SRM_STAT_DI1_SRM_STAT (0x00000200) //!< Bit mask for IPU_SRM_STAT_DI1_SRM_STAT.
|
|
|
|
//! @brief Get value of IPU_SRM_STAT_DI1_SRM_STAT from a register value.
|
|
#define BG_IPU_SRM_STAT_DI1_SRM_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SRM_STAT_DI1_SRM_STAT) >> BP_IPU_SRM_STAT_DI1_SRM_STAT)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_PROC_TASKS_STAT - Processing Status Tasks Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_PROC_TASKS_STAT - Processing Status Tasks Register (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains status bits for IPU's tasks.
|
|
*/
|
|
typedef union _hw_ipu_proc_tasks_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_proc_tasks_stat_bitfields
|
|
{
|
|
unsigned ENC_TSTAT : 2; //!< [1:0] Status of the encoding task
|
|
unsigned VF_TSTAT : 2; //!< [3:2] Status of the viewfinder task
|
|
unsigned PP_TSTAT : 2; //!< [5:4] Status of the post processing task
|
|
unsigned ENC_ROT_TSTAT : 2; //!< [7:6] Status of the rotation for encoding task
|
|
unsigned VF_ROT_TSTAT : 2; //!< [9:8] Status of the rotation for viewfinder task
|
|
unsigned PP_ROT_TSTAT : 2; //!< [11:10] Status of the rotation for post processing task
|
|
unsigned MEM2PRP_TSTAT : 3; //!< [14:12] Status of the pre processing tasks (viewfinder and encoding) when the source is coming from the memory.
|
|
unsigned RESERVED0 : 17; //!< [31:15] Reserved
|
|
} B;
|
|
} hw_ipu_proc_tasks_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_PROC_TASKS_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_PROC_TASKS_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x250)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_PROC_TASKS_STAT(x) (*(volatile hw_ipu_proc_tasks_stat_t *) HW_IPU_PROC_TASKS_STAT_ADDR(x))
|
|
#define HW_IPU_PROC_TASKS_STAT_RD(x) (HW_IPU_PROC_TASKS_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_PROC_TASKS_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field ENC_TSTAT[1:0] (RO)
|
|
*
|
|
* Status of the encoding task
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - The primary flow of this task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_ENC_TSTAT (0) //!< Bit position for IPU_PROC_TASKS_STAT_ENC_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_ENC_TSTAT (0x00000003) //!< Bit mask for IPU_PROC_TASKS_STAT_ENC_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_ENC_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_ENC_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_ENC_TSTAT) >> BP_IPU_PROC_TASKS_STAT_ENC_TSTAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field VF_TSTAT[3:2] (RO)
|
|
*
|
|
* Status of the viewfinder task
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - The primary flow of this task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_VF_TSTAT (2) //!< Bit position for IPU_PROC_TASKS_STAT_VF_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_VF_TSTAT (0x0000000c) //!< Bit mask for IPU_PROC_TASKS_STAT_VF_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_VF_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_VF_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_VF_TSTAT) >> BP_IPU_PROC_TASKS_STAT_VF_TSTAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field PP_TSTAT[5:4] (RO)
|
|
*
|
|
* Status of the post processing task
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - The primary flow of this task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_PP_TSTAT (4) //!< Bit position for IPU_PROC_TASKS_STAT_PP_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_PP_TSTAT (0x00000030) //!< Bit mask for IPU_PROC_TASKS_STAT_PP_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_PP_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_PP_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_PP_TSTAT) >> BP_IPU_PROC_TASKS_STAT_PP_TSTAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field ENC_ROT_TSTAT[7:6] (RO)
|
|
*
|
|
* Status of the rotation for encoding task
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - The primary flow of this task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT (6) //!< Bit position for IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT (0x000000c0) //!< Bit mask for IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT) >> BP_IPU_PROC_TASKS_STAT_ENC_ROT_TSTAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field VF_ROT_TSTAT[9:8] (RO)
|
|
*
|
|
* Status of the rotation for viewfinder task
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - The primary flow of this task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_VF_ROT_TSTAT (8) //!< Bit position for IPU_PROC_TASKS_STAT_VF_ROT_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_VF_ROT_TSTAT (0x00000300) //!< Bit mask for IPU_PROC_TASKS_STAT_VF_ROT_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_VF_ROT_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_VF_ROT_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_VF_ROT_TSTAT) >> BP_IPU_PROC_TASKS_STAT_VF_ROT_TSTAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field PP_ROT_TSTAT[11:10] (RO)
|
|
*
|
|
* Status of the rotation for post processing task
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - The primary flow of this task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_PP_ROT_TSTAT (10) //!< Bit position for IPU_PROC_TASKS_STAT_PP_ROT_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_PP_ROT_TSTAT (0x00000c00) //!< Bit mask for IPU_PROC_TASKS_STAT_PP_ROT_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_PP_ROT_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_PP_ROT_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_PP_ROT_TSTAT) >> BP_IPU_PROC_TASKS_STAT_PP_ROT_TSTAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_PROC_TASKS_STAT, field MEM2PRP_TSTAT[14:12] (RO)
|
|
*
|
|
* Status of the pre processing tasks (viewfinder and encoding) when the source is coming from the
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 000 - IDLE - Both pre processing tasks are idle
|
|
* - 001 - BOTH_ACTIVE - Both pre processing tasks are idle
|
|
* - 010 - ENC_ACTIVE - Encoding task is active
|
|
* - 011 - VF_ACTIVE - View finder task is active
|
|
* - 100 - BOTH_PAUSE - both tasks are paused
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserve
|
|
*/
|
|
//@{
|
|
#define BP_IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT (12) //!< Bit position for IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT.
|
|
#define BM_IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT (0x00007000) //!< Bit mask for IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT.
|
|
|
|
//! @brief Get value of IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT from a register value.
|
|
#define BG_IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT) >> BP_IPU_PROC_TASKS_STAT_MEM2PRP_TSTAT)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DISP_TASKS_STAT - Display Tasks Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DISP_TASKS_STAT - Display Tasks Status Register (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains status bits for IPU's tasks.
|
|
*/
|
|
typedef union _hw_ipu_disp_tasks_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_disp_tasks_stat_bitfields
|
|
{
|
|
unsigned DP_ASYNC_STAT : 3; //!< [2:0] Status of the Asynchronous flow through the DP
|
|
unsigned DP_ASYNC_CUR_FLOW : 1; //!< [3] Current asynchronous flow via the DP
|
|
unsigned DC_ASYNC1_STAT : 2; //!< [5:4] Status of the Asynchronous flow #1 through the DC (ch 28)
|
|
unsigned RESERVED0 : 2; //!< [7:6] Reserved
|
|
unsigned DC_ASYNCH2_STAT : 3; //!< [10:8] Status of the Asynchronous flow #2 through the DC
|
|
unsigned DC_ASYNC2_CUR_FLOW : 1; //!< [11] Current asynchronous #2 flow via the DC
|
|
unsigned RESERVED1 : 20; //!< [31:12] Reserved
|
|
} B;
|
|
} hw_ipu_disp_tasks_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DISP_TASKS_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DISP_TASKS_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x254)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DISP_TASKS_STAT(x) (*(volatile hw_ipu_disp_tasks_stat_t *) HW_IPU_DISP_TASKS_STAT_ADDR(x))
|
|
#define HW_IPU_DISP_TASKS_STAT_RD(x) (HW_IPU_DISP_TASKS_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DISP_TASKS_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DISP_TASKS_STAT, field DP_ASYNC_STAT[2:0] (RO)
|
|
*
|
|
* Status of the Asynchronous flow through the DP
|
|
*
|
|
* Values:
|
|
* - 000 - IDLE - the task is idle
|
|
* - 001 - PRIM_ACTIVE - The primary flow of this task is currently active
|
|
* - 010 - ALT_ACTIVE - The alternate flow of this task is currently active
|
|
* - 011 - UPDATE_PARAM - The FSU is busy updating parameters from the SRM
|
|
* - 100 - PAUSE - The task is paused
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_TASKS_STAT_DP_ASYNC_STAT (0) //!< Bit position for IPU_DISP_TASKS_STAT_DP_ASYNC_STAT.
|
|
#define BM_IPU_DISP_TASKS_STAT_DP_ASYNC_STAT (0x00000007) //!< Bit mask for IPU_DISP_TASKS_STAT_DP_ASYNC_STAT.
|
|
|
|
//! @brief Get value of IPU_DISP_TASKS_STAT_DP_ASYNC_STAT from a register value.
|
|
#define BG_IPU_DISP_TASKS_STAT_DP_ASYNC_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_TASKS_STAT_DP_ASYNC_STAT) >> BP_IPU_DISP_TASKS_STAT_DP_ASYNC_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_TASKS_STAT, field DP_ASYNC_CUR_FLOW[3] (RO)
|
|
*
|
|
* Current asynchronous flow via the DP
|
|
*
|
|
* Values:
|
|
* - 0 - main flow
|
|
* - 1 - alternate flow
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW (3) //!< Bit position for IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW.
|
|
#define BM_IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW (0x00000008) //!< Bit mask for IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW.
|
|
|
|
//! @brief Get value of IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW from a register value.
|
|
#define BG_IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW) >> BP_IPU_DISP_TASKS_STAT_DP_ASYNC_CUR_FLOW)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_TASKS_STAT, field DC_ASYNC1_STAT[5:4] (RO)
|
|
*
|
|
* Status of the Asynchronous flow #1 through the DC (ch 28)
|
|
*
|
|
* Values:
|
|
* - 00 - IDLE - The task is idle
|
|
* - 01 - ACTIVE - This task is currently active
|
|
* - 10 - WAIT_FOR_ READY - The task is waiting for a buffer to be ready
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT (4) //!< Bit position for IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT.
|
|
#define BM_IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT (0x00000030) //!< Bit mask for IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT.
|
|
|
|
//! @brief Get value of IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT from a register value.
|
|
#define BG_IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT) >> BP_IPU_DISP_TASKS_STAT_DC_ASYNC1_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_TASKS_STAT, field DC_ASYNCH2_STAT[10:8] (RO)
|
|
*
|
|
* Status of the Asynchronous flow #2 through the DC
|
|
*
|
|
* Values:
|
|
* - 000 - IDLE - the task is idle
|
|
* - 001 - PRIM_ACTIVE - The primary flow of this task is currently active
|
|
* - 010 - ALT_ACTIVE - The alternate flow of this task is currently active
|
|
* - 011 - UPDATE_PARAM - The FSU is busy updating parameters from the SRM
|
|
* - 100 - PAUSE - The task is paused
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT (8) //!< Bit position for IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT.
|
|
#define BM_IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT (0x00000700) //!< Bit mask for IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT.
|
|
|
|
//! @brief Get value of IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT from a register value.
|
|
#define BG_IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT) >> BP_IPU_DISP_TASKS_STAT_DC_ASYNCH2_STAT)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DISP_TASKS_STAT, field DC_ASYNC2_CUR_FLOW[11] (RO)
|
|
*
|
|
* Current asynchronous #2 flow via the DC
|
|
*
|
|
* Values:
|
|
* - 0 - main flow
|
|
* - 1 - alternate flow
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW (11) //!< Bit position for IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW.
|
|
#define BM_IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW (0x00000800) //!< Bit mask for IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW.
|
|
|
|
//! @brief Get value of IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW from a register value.
|
|
#define BG_IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW) >> BP_IPU_DISP_TASKS_STAT_DC_ASYNC2_CUR_FLOW)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_TRIPLE_CUR_BUF_0 - Triple Current Buffer Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_TRIPLE_CUR_BUF_0 - Triple Current Buffer Register 0 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information for triple buffer mode for each DMA
|
|
* channel. Hide VPU_SUB_FRAME_SYNC for all versions Show VPU_SUB_FRAME_SYNC for IPUv3H version. The
|
|
* table below tagged with other settings (like IPU3M_only) should be hidden in IPUv3H version. This
|
|
* requires some sophisticated conditional tag settings
|
|
*/
|
|
typedef union _hw_ipu_triple_cur_buf_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_triple_cur_buf_0_bitfields
|
|
{
|
|
unsigned RESERVED0 : 16; //!< [15:0] Reserved.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_8 : 2; //!< [17:16] Current Buffer for triple buffer mode.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_9 : 2; //!< [19:18] Current Buffer for triple buffer mode.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_10 : 2; //!< [21:20] Current Buffer for triple buffer mode.
|
|
unsigned RESERVED1 : 4; //!< [25:22] Reserved.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_13 : 2; //!< [27:26] Current Buffer for triple buffer mode.
|
|
unsigned RESERVED2 : 4; //!< [31:28] Reserved.
|
|
} B;
|
|
} hw_ipu_triple_cur_buf_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_TRIPLE_CUR_BUF_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_TRIPLE_CUR_BUF_0_ADDR(x) (REGS_IPU_BASE(x) + 0x258)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_TRIPLE_CUR_BUF_0(x) (*(volatile hw_ipu_triple_cur_buf_0_t *) HW_IPU_TRIPLE_CUR_BUF_0_ADDR(x))
|
|
#define HW_IPU_TRIPLE_CUR_BUF_0_RD(x) (HW_IPU_TRIPLE_CUR_BUF_0(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_TRIPLE_CUR_BUF_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_0, field DMA_CH_TRIPLE_CUR_BUF_8[17:16] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8 (16) //!< Bit position for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8 (0x00030000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8) >> BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_8)
|
|
//@}
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_0, field DMA_CH_TRIPLE_CUR_BUF_9[19:18] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9 (18) //!< Bit position for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9 (0x000c0000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9) >> BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_9)
|
|
//@}
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_0, field DMA_CH_TRIPLE_CUR_BUF_10[21:20] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10 (20) //!< Bit position for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10 (0x00300000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10) >> BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_10)
|
|
//@}
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_0, field DMA_CH_TRIPLE_CUR_BUF_13[27:26] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13 (26) //!< Bit position for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13 (0x0c000000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13) >> BP_IPU_TRIPLE_CUR_BUF_0_DMA_CH_TRIPLE_CUR_BUF_13)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_TRIPLE_CUR_BUF_1 - Triple Current Buffer Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_TRIPLE_CUR_BUF_1 - Triple Current Buffer Register 1 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information for triple buffer mode for each DMA
|
|
* channel.
|
|
*/
|
|
typedef union _hw_ipu_triple_cur_buf_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_triple_cur_buf_1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 10; //!< [9:0] Reserved.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_21 : 2; //!< [11:10] Current Buffer for triple buffer mode.
|
|
unsigned RESERVED1 : 2; //!< [13:12] Reserved.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_23 : 2; //!< [15:14] Current Buffer for triple buffer mode.
|
|
unsigned RESERVED2 : 6; //!< [21:16] Reserved.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_27 : 2; //!< [23:22] Current Buffer for triple buffer mode.
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_28 : 2; //!< [25:24] Current Buffer for triple buffer mode.
|
|
unsigned RESERVED3 : 6; //!< [31:26] Reserved.
|
|
} B;
|
|
} hw_ipu_triple_cur_buf_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_TRIPLE_CUR_BUF_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_TRIPLE_CUR_BUF_1_ADDR(x) (REGS_IPU_BASE(x) + 0x25c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_TRIPLE_CUR_BUF_1(x) (*(volatile hw_ipu_triple_cur_buf_1_t *) HW_IPU_TRIPLE_CUR_BUF_1_ADDR(x))
|
|
#define HW_IPU_TRIPLE_CUR_BUF_1_RD(x) (HW_IPU_TRIPLE_CUR_BUF_1(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_TRIPLE_CUR_BUF_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_1, field DMA_CH_TRIPLE_CUR_BUF_21[11:10] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21 (10) //!< Bit position for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21 (0x00000c00) //!< Bit mask for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21) >> BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_21)
|
|
//@}
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_1, field DMA_CH_TRIPLE_CUR_BUF_23[15:14] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23 (14) //!< Bit position for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23 (0x0000c000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23) >> BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_23)
|
|
//@}
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_1, field DMA_CH_TRIPLE_CUR_BUF_27[23:22] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27 (22) //!< Bit position for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27 (0x00c00000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27) >> BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_27)
|
|
//@}
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_1, field DMA_CH_TRIPLE_CUR_BUF_28[25:24] (RO)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by the DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
* - 11 - NA
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28 (24) //!< Bit position for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28 (0x03000000) //!< Bit mask for IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28 from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28) >> BP_IPU_TRIPLE_CUR_BUF_1_DMA_CH_TRIPLE_CUR_BUF_28)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_TRIPLE_CUR_BUF_2 - Triple Current Buffer Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_TRIPLE_CUR_BUF_2 - Triple Current Buffer Register 2 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information for triple buffer mode for each DMA
|
|
* channel.
|
|
*/
|
|
typedef union _hw_ipu_triple_cur_buf_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_triple_cur_buf_2_bitfields
|
|
{
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_N : 32; //!< [31:0] Current Buffer for triple buffer mode.
|
|
} B;
|
|
} hw_ipu_triple_cur_buf_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_TRIPLE_CUR_BUF_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_TRIPLE_CUR_BUF_2_ADDR(x) (REGS_IPU_BASE(x) + 0x260)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_TRIPLE_CUR_BUF_2(x) (*(volatile hw_ipu_triple_cur_buf_2_t *) HW_IPU_TRIPLE_CUR_BUF_2_ADDR(x))
|
|
#define HW_IPU_TRIPLE_CUR_BUF_2_RD(x) (HW_IPU_TRIPLE_CUR_BUF_2(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_TRIPLE_CUR_BUF_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_2, field DMA_CH_TRIPLE_CUR_BUF_N[31:0] (ROZ)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N (0) //!< Bit position for IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N (0xffffffff) //!< Bit mask for IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N) >> BP_IPU_TRIPLE_CUR_BUF_2_DMA_CH_TRIPLE_CUR_BUF_N)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_TRIPLE_CUR_BUF_3 - Triple Current Buffer Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_TRIPLE_CUR_BUF_3 - Triple Current Buffer Register 3 (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains the current buffer status information for triple buffer mode for each DMA
|
|
* channel.
|
|
*/
|
|
typedef union _hw_ipu_triple_cur_buf_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_triple_cur_buf_3_bitfields
|
|
{
|
|
unsigned DMA_CH_TRIPLE_CUR_BUF_N : 32; //!< [31:0] Current Buffer for triple buffer mode.
|
|
} B;
|
|
} hw_ipu_triple_cur_buf_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_TRIPLE_CUR_BUF_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_TRIPLE_CUR_BUF_3_ADDR(x) (REGS_IPU_BASE(x) + 0x264)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_TRIPLE_CUR_BUF_3(x) (*(volatile hw_ipu_triple_cur_buf_3_t *) HW_IPU_TRIPLE_CUR_BUF_3_ADDR(x))
|
|
#define HW_IPU_TRIPLE_CUR_BUF_3_RD(x) (HW_IPU_TRIPLE_CUR_BUF_3(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_TRIPLE_CUR_BUF_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_TRIPLE_CUR_BUF_3, field DMA_CH_TRIPLE_CUR_BUF_N[31:0] (ROZ)
|
|
*
|
|
* Current Buffer for triple buffer mode. This bits indicate which buffer is in use by DMA when
|
|
* triple buffer mode is selected. Each pair of bits indicate the corresponding DMA channel (bits
|
|
* [1:0] correspond to ch #0; (bits [3:2] correspond to ch #1, etc.)
|
|
*
|
|
* Values:
|
|
* - 00 - Current buffer used by DMA is buffer 0.
|
|
* - 01 - Current buffer used by DMA is buffer 1.
|
|
* - 10 - Current buffer used by DMA is buffer 2.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N (0) //!< Bit position for IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N.
|
|
#define BM_IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N (0xffffffff) //!< Bit mask for IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N.
|
|
|
|
//! @brief Get value of IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N from a register value.
|
|
#define BG_IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N) >> BP_IPU_TRIPLE_CUR_BUF_3_DMA_CH_TRIPLE_CUR_BUF_N)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CH_BUF0_RDY0 - IPU Channels Buffer 0 Ready 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CH_BUF0_RDY0 - IPU Channels Buffer 0 Ready 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 0 ready control information for 32 IPU's DMA channels (31-0). This
|
|
* register can be a write one to set or a write one to clear according to the IPU_CH_BUF0_RDY0_CLR
|
|
* bit . The register is shown in , and the register fields are described in .
|
|
*/
|
|
typedef union _hw_ipu_ch_buf0_rdy0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ch_buf0_rdy0_bitfields
|
|
{
|
|
unsigned DMA_CH_BUF0_RDY_0 : 1; //!< [0] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_1 : 1; //!< [1] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_2 : 1; //!< [2] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_3 : 1; //!< [3] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_4 : 1; //!< [4] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_5 : 1; //!< [5] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_6 : 1; //!< [6] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_7 : 1; //!< [7] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_8 : 1; //!< [8] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_9 : 1; //!< [9] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_10 : 1; //!< [10] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_11 : 1; //!< [11] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_12 : 1; //!< [12] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_13 : 1; //!< [13] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_14 : 1; //!< [14] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_15 : 1; //!< [15] Buffer 0 is ready.
|
|
unsigned RESERVED0 : 1; //!< [16] Reserved.
|
|
unsigned DMA_CH_BUF0_RDY_17 : 1; //!< [17] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_18 : 1; //!< [18] Buffer 0 is ready.
|
|
unsigned RESERVED1 : 1; //!< [19] Reserved.
|
|
unsigned DMA_CH_BUF0_RDY_20 : 1; //!< [20] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_21 : 1; //!< [21] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_22 : 1; //!< [22] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_23 : 1; //!< [23] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_24 : 1; //!< [24] Buffer 0 is ready.
|
|
unsigned RESERVED2 : 2; //!< [26:25] Reserved.
|
|
unsigned DMA_CH_BUF0_RDY_27 : 1; //!< [27] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_28 : 1; //!< [28] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_29 : 1; //!< [29] Buffer 0 is ready.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned DMA_CH_BUF0_RDY_31 : 1; //!< [31] Buffer 0 is ready.
|
|
} B;
|
|
} hw_ipu_ch_buf0_rdy0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_BUF0_RDY0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_BUF0_RDY0_ADDR(x) (REGS_IPU_BASE(x) + 0x268)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_BUF0_RDY0(x) (*(volatile hw_ipu_ch_buf0_rdy0_t *) HW_IPU_CH_BUF0_RDY0_ADDR(x))
|
|
#define HW_IPU_CH_BUF0_RDY0_RD(x) (HW_IPU_CH_BUF0_RDY0(x).U)
|
|
#define HW_IPU_CH_BUF0_RDY0_WR(x, v) (HW_IPU_CH_BUF0_RDY0(x).U = (v))
|
|
#define HW_IPU_CH_BUF0_RDY0_SET(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, HW_IPU_CH_BUF0_RDY0_RD(x) | (v)))
|
|
#define HW_IPU_CH_BUF0_RDY0_CLR(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, HW_IPU_CH_BUF0_RDY0_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_BUF0_RDY0_TOG(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, HW_IPU_CH_BUF0_RDY0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_BUF0_RDY0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_0[0] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0 (0) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0 (0x00000001) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_0 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_1[1] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1 (1) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1 (0x00000002) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_1 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_2[2] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2 (2) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2 (0x00000004) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_2 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_3[3] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3 (3) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3 (0x00000008) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_3 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_4[4] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4 (4) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4 (0x00000010) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_4 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_5[5] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5 (5) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5 (0x00000020) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_5 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_6[6] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6 (6) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6 (0x00000040) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_6 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_7[7] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7 (7) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7 (0x00000080) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_7 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_8[8] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8 (8) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8 (0x00000100) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_8 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_9[9] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9 (9) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9 (0x00000200) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_9 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_10[10] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10 (10) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10 (0x00000400) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_10 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_11[11] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11 (11) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11 (0x00000800) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_11 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_12[12] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12 (12) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12 (0x00001000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12.
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|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_12 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_13[13] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13 (13) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13 (0x00002000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_13 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_14[14] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14 (14) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14 (0x00004000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_14 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_15[15] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15 (15) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15 (0x00008000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_15 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_17[17] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17 (17) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17 (0x00020000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_17 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_18[18] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18 (18) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18 (0x00040000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_18 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_20[20] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20 (20) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20 (0x00100000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_20 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_21[21] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21 (21) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21 (0x00200000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_21 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_22[22] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22 (22) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22 (0x00400000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_22 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_23[23] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23 (23) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23 (0x00800000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23.
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|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23)
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|
|
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//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_23 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_24[24] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24 (24) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24 (0x01000000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24.
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|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_24 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_27[27] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27 (27) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27 (0x08000000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27.
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|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_27 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_28[28] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28 (28) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28 (0x10000000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28.
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|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_28 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_29[29] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29 (29) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29 (0x20000000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_29 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY0, field DMA_CH_BUF0_RDY_31[31] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31 (31) //!< Bit position for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31.
|
|
#define BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31 (0x80000000) //!< Bit mask for IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31) >> BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31.
|
|
#define BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31) & BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_31 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31(x, v) (HW_IPU_CH_BUF0_RDY0_WR(x, (HW_IPU_CH_BUF0_RDY0_RD(x) & ~BM_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31) | BF_IPU_CH_BUF0_RDY0_DMA_CH_BUF0_RDY_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CH_BUF0_RDY1 - IPU Channels Buffer 0 Ready 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CH_BUF0_RDY1 - IPU Channels Buffer 0 Ready 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 0 ready control information for 32 IPU's DMA channels (63-32). This
|
|
* register can be a write one to set or a write one to clear according to the IPU_CH_BUF0_RDY1_CLR
|
|
* bit .
|
|
*/
|
|
typedef union _hw_ipu_ch_buf0_rdy1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ch_buf0_rdy1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned DMA_CH_BUF0_RDY_33 : 1; //!< [1] Buffer 0 is ready.
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned DMA_CH_BUF0_RDY_40 : 1; //!< [8] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_41 : 1; //!< [9] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_42 : 1; //!< [10] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_43 : 1; //!< [11] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_44 : 1; //!< [12] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_45 : 1; //!< [13] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_46 : 1; //!< [14] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_47 : 1; //!< [15] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_48 : 1; //!< [16] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_49 : 1; //!< [17] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_50 : 1; //!< [18] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_51 : 1; //!< [19] Buffer 0 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_52 : 1; //!< [20] Buffer 0 is ready.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_ch_buf0_rdy1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_BUF0_RDY1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_BUF0_RDY1_ADDR(x) (REGS_IPU_BASE(x) + 0x26c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_BUF0_RDY1(x) (*(volatile hw_ipu_ch_buf0_rdy1_t *) HW_IPU_CH_BUF0_RDY1_ADDR(x))
|
|
#define HW_IPU_CH_BUF0_RDY1_RD(x) (HW_IPU_CH_BUF0_RDY1(x).U)
|
|
#define HW_IPU_CH_BUF0_RDY1_WR(x, v) (HW_IPU_CH_BUF0_RDY1(x).U = (v))
|
|
#define HW_IPU_CH_BUF0_RDY1_SET(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, HW_IPU_CH_BUF0_RDY1_RD(x) | (v)))
|
|
#define HW_IPU_CH_BUF0_RDY1_CLR(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, HW_IPU_CH_BUF0_RDY1_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_BUF0_RDY1_TOG(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, HW_IPU_CH_BUF0_RDY1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_BUF0_RDY1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_33[1] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33 (1) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33 (0x00000002) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_33 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_40[8] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40 (8) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40 (0x00000100) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_40 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_41[9] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41 (9) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41 (0x00000200) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_41 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_42[10] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42 (10) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42 (0x00000400) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_42 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_43[11] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43 (11) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43 (0x00000800) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_43 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_44[12] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44 (12) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44 (0x00001000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_44 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_45[13] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45 (13) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45 (0x00002000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_45 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_46[14] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46 (14) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46 (0x00004000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_46 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_47[15] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47 (15) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47 (0x00008000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_47 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_48[16] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48 (16) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48 (0x00010000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_48 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_49[17] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49 (17) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49 (0x00020000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_49 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_50[18] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50 (18) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50 (0x00040000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_50 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_51[19] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51 (19) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51 (0x00080000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_51 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF0_RDY1, field DMA_CH_BUF0_RDY_52[20] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52 (20) //!< Bit position for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52.
|
|
#define BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52 (0x00100000) //!< Bit mask for IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52.
|
|
|
|
//! @brief Get value of IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52 from a register value.
|
|
#define BG_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52) >> BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52.
|
|
#define BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52) & BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_52 field to a new value.
|
|
#define BW_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52(x, v) (HW_IPU_CH_BUF0_RDY1_WR(x, (HW_IPU_CH_BUF0_RDY1_RD(x) & ~BM_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52) | BF_IPU_CH_BUF0_RDY1_DMA_CH_BUF0_RDY_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CH_BUF1_RDY0 - IPU Channels Buffer 1 Ready 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CH_BUF1_RDY0 - IPU Channels Buffer 1 Ready 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 1 ready control information for 32 IPU's DMA channels (31-0). This
|
|
* register can be a write one to set or a write one to clear according to the IPU_CH_BUF1_RDY0_CLR
|
|
* bit .
|
|
*/
|
|
typedef union _hw_ipu_ch_buf1_rdy0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ch_buf1_rdy0_bitfields
|
|
{
|
|
unsigned DMA_CH_BUF1_RDY_0 : 1; //!< [0] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_1 : 1; //!< [1] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_2 : 1; //!< [2] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_3 : 1; //!< [3] Buffer 1 is ready.
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned DMA_CH_BUF1_RDY_5 : 1; //!< [5] Buffer 1 is ready.
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned DMA_CH_BUF1_RDY_8 : 1; //!< [8] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_9 : 1; //!< [9] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_10 : 1; //!< [10] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY : 1; //!< [11] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_12 : 1; //!< [12] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_13 : 1; //!< [13] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_14 : 1; //!< [14] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_15 : 1; //!< [15] Buffer 1 is ready.
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned DMA_CH_BUF1_RDY_17 : 1; //!< [17] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_18 : 1; //!< [18] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_19 : 1; //!< [19] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_20 : 1; //!< [20] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_21 : 1; //!< [21] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_22 : 1; //!< [22] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_23 : 1; //!< [23] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_24 : 1; //!< [24] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_25 : 1; //!< [25] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_26 : 1; //!< [26] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_27 : 1; //!< [27] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_28 : 1; //!< [28] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF1_RDY_29 : 1; //!< [29] Buffer 1 is ready.
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned DMA_CH_BUF1_RDY_31 : 1; //!< [31] Buffer 1 is ready.
|
|
} B;
|
|
} hw_ipu_ch_buf1_rdy0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_BUF1_RDY0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_BUF1_RDY0_ADDR(x) (REGS_IPU_BASE(x) + 0x270)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_BUF1_RDY0(x) (*(volatile hw_ipu_ch_buf1_rdy0_t *) HW_IPU_CH_BUF1_RDY0_ADDR(x))
|
|
#define HW_IPU_CH_BUF1_RDY0_RD(x) (HW_IPU_CH_BUF1_RDY0(x).U)
|
|
#define HW_IPU_CH_BUF1_RDY0_WR(x, v) (HW_IPU_CH_BUF1_RDY0(x).U = (v))
|
|
#define HW_IPU_CH_BUF1_RDY0_SET(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, HW_IPU_CH_BUF1_RDY0_RD(x) | (v)))
|
|
#define HW_IPU_CH_BUF1_RDY0_CLR(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, HW_IPU_CH_BUF1_RDY0_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_BUF1_RDY0_TOG(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, HW_IPU_CH_BUF1_RDY0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_BUF1_RDY0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_0[0] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0 (0) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0 (0x00000001) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_0 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_1[1] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1 (1) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1 (0x00000002) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_1 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_2[2] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2 (2) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2 (0x00000004) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_2 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_3[3] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3 (3) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3 (0x00000008) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_3 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_5[5] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5 (5) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5 (0x00000020) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_5 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_8[8] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8 (8) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8 (0x00000100) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_8 field to a new value.
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#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_8(v)))
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#endif
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//@}
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_9[9] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
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//@{
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|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9 (9) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9 (0x00000200) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9 from a register value.
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#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9.
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#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_BUF1_RDY_9 field to a new value.
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#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_9(v)))
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#endif
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//@}
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_10[10] (RW)
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|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
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|
* - 1 - Buffer 0 is ready.
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|
*/
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//@{
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|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10 (10) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10 (0x00000400) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10 from a register value.
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#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10.
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#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10)
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|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_10 field to a new value.
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|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_10(v)))
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#endif
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//@}
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY[11] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
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|
*/
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//@{
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|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY (11) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY (0x00000800) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY.
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|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_12[12] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
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|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12 (12) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12.
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|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12 (0x00001000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12)
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|
|
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_12 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_12(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_13[13] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13 (13) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13.
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|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13 (0x00002000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_13 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_13(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_14[14] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14 (14) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14.
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|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14 (0x00004000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_14 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_15[15] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15 (15) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15 (0x00008000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_15 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_17[17] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17 (17) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17 (0x00020000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_17 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_18[18] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18 (18) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18 (0x00040000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_18 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_19[19] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19 (19) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19 (0x00080000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19.
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|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_BUF1_RDY_19 field to a new value.
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#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_19(v)))
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#endif
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//@}
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_20[20] (RW)
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*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
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|
*/
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//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20 (20) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20 (0x00100000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20 from a register value.
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#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20.
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#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMA_CH_BUF1_RDY_20 field to a new value.
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#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_20(v)))
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#endif
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//@}
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_21[21] (RW)
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|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
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|
* - 1 - Buffer 0 is ready.
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|
*/
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//@{
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|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21 (21) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21 (0x00200000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21 from a register value.
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#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21.
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#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_21 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_21(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_22[22] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
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|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22 (22) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22 (0x00400000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22 from a register value.
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|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_22 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_22(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_23[23] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
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|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23 (23) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23.
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|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23 (0x00800000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23)
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|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_23 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_23(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_24[24] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24 (24) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24.
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|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24 (0x01000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24)
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|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_24 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_24(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_25[25] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25 (25) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25.
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|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25 (0x02000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_25 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_26[26] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26 (26) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26 (0x04000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_26 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_27[27] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27 (27) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27 (0x08000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_27 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_28[28] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28 (28) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28 (0x10000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28.
|
|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_28 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_29[29] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29 (29) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29.
|
|
#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29 (0x20000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29.
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|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29)
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|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF1_RDY_29 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_29(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_CH_BUF1_RDY0, field DMA_CH_BUF1_RDY_31[31] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
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|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31 (31) //!< Bit position for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31.
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#define BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31 (0x80000000) //!< Bit mask for IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31.
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//! @brief Get value of IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31 from a register value.
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|
#define BG_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31) >> BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31.
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|
#define BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31) & BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DMA_CH_BUF1_RDY_31 field to a new value.
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|
#define BW_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31(x, v) (HW_IPU_CH_BUF1_RDY0_WR(x, (HW_IPU_CH_BUF1_RDY0_RD(x) & ~BM_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31) | BF_IPU_CH_BUF1_RDY0_DMA_CH_BUF1_RDY_31(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CH_BUF1_RDY1 - IPU Channels Buffer 1 Ready 1Register
|
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//-------------------------------------------------------------------------------------------
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|
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#ifndef __LANGUAGE_ASM__
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|
/*!
|
|
* @brief HW_IPU_CH_BUF1_RDY1 - IPU Channels Buffer 1 Ready 1Register (RW)
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|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 0 ready control information for 32 IPU's DMA channels (63-32). This
|
|
* register can be a write one to set or a write one to clear according to the IPU_CH_BUF1_RDY1_CLR
|
|
* bit . The register is shown in , and the register fields are described in .
|
|
*/
|
|
typedef union _hw_ipu_ch_buf1_rdy1
|
|
{
|
|
reg32_t U;
|
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struct _hw_ipu_ch_buf1_rdy1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
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unsigned DMA_CH_BUF0_RDY_33 : 1; //!< [1] Buffer 1 is ready.
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|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
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unsigned DMA_CH_BUF0_RDY_40 : 1; //!< [8] Buffer 1 is ready.
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unsigned DMA_CH_BUF0_RDY_41 : 1; //!< [9] Buffer 1 is ready.
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unsigned DMA_CH_BUF0_RDY_42 : 1; //!< [10] Buffer 1 is ready.
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unsigned DMA_CH_BUF0_RDY_43 : 1; //!< [11] Buffer 1 is ready.
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unsigned DMA_CH_BUF0_RDY_44 : 1; //!< [12] Buffer 1 is ready.
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unsigned DMA_CH_BUF0_RDY_45 : 1; //!< [13] Buffer 1 is ready.
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|
unsigned DMA_CH_BUF0_RDY_46 : 1; //!< [14] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_47 : 1; //!< [15] Buffer 1 is ready.
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unsigned DMA_CH_BUF0_RDY_48 : 1; //!< [16] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_49 : 1; //!< [17] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_50 : 1; //!< [18] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_51 : 1; //!< [19] Buffer 1 is ready.
|
|
unsigned DMA_CH_BUF0_RDY_52 : 1; //!< [20] Buffer 1 is ready.
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_ch_buf1_rdy1_t;
|
|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_BUF1_RDY1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_BUF1_RDY1_ADDR(x) (REGS_IPU_BASE(x) + 0x274)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_BUF1_RDY1(x) (*(volatile hw_ipu_ch_buf1_rdy1_t *) HW_IPU_CH_BUF1_RDY1_ADDR(x))
|
|
#define HW_IPU_CH_BUF1_RDY1_RD(x) (HW_IPU_CH_BUF1_RDY1(x).U)
|
|
#define HW_IPU_CH_BUF1_RDY1_WR(x, v) (HW_IPU_CH_BUF1_RDY1(x).U = (v))
|
|
#define HW_IPU_CH_BUF1_RDY1_SET(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, HW_IPU_CH_BUF1_RDY1_RD(x) | (v)))
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|
#define HW_IPU_CH_BUF1_RDY1_CLR(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, HW_IPU_CH_BUF1_RDY1_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_BUF1_RDY1_TOG(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, HW_IPU_CH_BUF1_RDY1_RD(x) ^ (v)))
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|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_BUF1_RDY1 bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_33[1] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33 (1) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33.
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|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33 (0x00000002) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_33 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_40[8] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40 (8) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40.
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|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40 (0x00000100) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_40 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_41[9] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41 (9) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41 (0x00000200) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_41 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_42[10] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42 (10) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42 (0x00000400) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_42 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_43[11] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43 (11) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43 (0x00000800) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_43 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_44[12] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44 (12) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44 (0x00001000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_44 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_45[13] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45 (13) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45 (0x00002000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45)
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|
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|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_45 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_45(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_46[14] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46 (14) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46.
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|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46 (0x00004000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46.
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//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46)
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//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_46 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_46(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_47[15] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47 (15) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47.
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#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47 (0x00008000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47.
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//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_47 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_47(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_48[16] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48 (16) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48.
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|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48 (0x00010000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48)
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|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_48 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_48(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_49[17] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49 (17) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49.
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|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49 (0x00020000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_49 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_50[18] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50 (18) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50.
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|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50 (0x00040000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50.
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|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_50 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_51[19] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51 (19) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51 (0x00080000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_51 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF1_RDY1, field DMA_CH_BUF0_RDY_52[20] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - Buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52 (20) //!< Bit position for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52.
|
|
#define BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52 (0x00100000) //!< Bit mask for IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52.
|
|
|
|
//! @brief Get value of IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52 from a register value.
|
|
#define BG_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52) >> BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52.
|
|
#define BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52) & BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF0_RDY_52 field to a new value.
|
|
#define BW_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52(x, v) (HW_IPU_CH_BUF1_RDY1_WR(x, (HW_IPU_CH_BUF1_RDY1_RD(x) & ~BM_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52) | BF_IPU_CH_BUF1_RDY1_DMA_CH_BUF0_RDY_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CH_BUF0_RDY0 - IPU Alternate Channels Buffer 0 Ready 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CH_BUF0_RDY0 - IPU Alternate Channels Buffer 0 Ready 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 0 ready control information for 32 IPU's DMA channels (31-0).
|
|
* Writing "1" to each field will set each bit. Writing "0" to each field simultaneously will clear
|
|
* all the bits.
|
|
*/
|
|
typedef union _hw_ipu_alt_ch_buf0_rdy0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_ch_buf0_rdy0_bitfields
|
|
{
|
|
unsigned RESERVED0 : 24; //!< [23:0] Reserved.
|
|
unsigned DMA_CH_ALT_BUF0_RDY_24 : 1; //!< [24] Buffer 0 is ready.
|
|
unsigned RESERVED1 : 4; //!< [28:25] Reserved.
|
|
unsigned DMA_CH_ALT_BUF0_RDY_29 : 1; //!< [29] Buffer 0 is ready.
|
|
unsigned RESERVED2 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_ch_buf0_rdy0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CH_BUF0_RDY0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0_ADDR(x) (REGS_IPU_BASE(x) + 0x278)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0(x) (*(volatile hw_ipu_alt_ch_buf0_rdy0_t *) HW_IPU_ALT_CH_BUF0_RDY0_ADDR(x))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0_RD(x) (HW_IPU_ALT_CH_BUF0_RDY0(x).U)
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0_WR(x, v) (HW_IPU_ALT_CH_BUF0_RDY0(x).U = (v))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0_SET(x, v) (HW_IPU_ALT_CH_BUF0_RDY0_WR(x, HW_IPU_ALT_CH_BUF0_RDY0_RD(x) | (v)))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0_CLR(x, v) (HW_IPU_ALT_CH_BUF0_RDY0_WR(x, HW_IPU_ALT_CH_BUF0_RDY0_RD(x) & ~(v)))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY0_TOG(x, v) (HW_IPU_ALT_CH_BUF0_RDY0_WR(x, HW_IPU_ALT_CH_BUF0_RDY0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CH_BUF0_RDY0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF0_RDY0, field DMA_CH_ALT_BUF0_RDY_24[24] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24 (24) //!< Bit position for IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24.
|
|
#define BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24 (0x01000000) //!< Bit mask for IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24) >> BP_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24.
|
|
#define BF_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24) & BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF0_RDY_24 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24(x, v) (HW_IPU_ALT_CH_BUF0_RDY0_WR(x, (HW_IPU_ALT_CH_BUF0_RDY0_RD(x) & ~BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24) | BF_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF0_RDY0, field DMA_CH_ALT_BUF0_RDY_29[29] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29 (29) //!< Bit position for IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29.
|
|
#define BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29 (0x20000000) //!< Bit mask for IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29) >> BP_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29.
|
|
#define BF_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29) & BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF0_RDY_29 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29(x, v) (HW_IPU_ALT_CH_BUF0_RDY0_WR(x, (HW_IPU_ALT_CH_BUF0_RDY0_RD(x) & ~BM_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29) | BF_IPU_ALT_CH_BUF0_RDY0_DMA_CH_ALT_BUF0_RDY_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CH_BUF0_RDY1 - IPU Alternate Channels Buffer 0 Ready 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CH_BUF0_RDY1 - IPU Alternate Channels Buffer 0 Ready 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 0 ready control information for 32 IPU's DMA channels (63-32).
|
|
* Writing "1" to each field will set each bit. Writing "0" to each field simultaneously will clear
|
|
* all the bits.
|
|
*/
|
|
typedef union _hw_ipu_alt_ch_buf0_rdy1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_ch_buf0_rdy1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned DMA_CH_ALT_BUF0_RDY_33 : 1; //!< [1] Buffer 0 is ready.
|
|
unsigned RESERVED1 : 7; //!< [8:2] Reserved.
|
|
unsigned DMA_CH_ALT_BUF0_RDY_41 : 1; //!< [9] Buffer 0 is ready.
|
|
unsigned RESERVED2 : 10; //!< [19:10] Reserved.
|
|
unsigned DMA_CH_ALT_BUF0_RDY_52 : 1; //!< [20] Buffer 0 is ready.
|
|
unsigned RESERVED3 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_ch_buf0_rdy1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CH_BUF0_RDY1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1_ADDR(x) (REGS_IPU_BASE(x) + 0x27c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1(x) (*(volatile hw_ipu_alt_ch_buf0_rdy1_t *) HW_IPU_ALT_CH_BUF0_RDY1_ADDR(x))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1_RD(x) (HW_IPU_ALT_CH_BUF0_RDY1(x).U)
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1_WR(x, v) (HW_IPU_ALT_CH_BUF0_RDY1(x).U = (v))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1_SET(x, v) (HW_IPU_ALT_CH_BUF0_RDY1_WR(x, HW_IPU_ALT_CH_BUF0_RDY1_RD(x) | (v)))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1_CLR(x, v) (HW_IPU_ALT_CH_BUF0_RDY1_WR(x, HW_IPU_ALT_CH_BUF0_RDY1_RD(x) & ~(v)))
|
|
#define HW_IPU_ALT_CH_BUF0_RDY1_TOG(x, v) (HW_IPU_ALT_CH_BUF0_RDY1_WR(x, HW_IPU_ALT_CH_BUF0_RDY1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CH_BUF0_RDY1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF0_RDY1, field DMA_CH_ALT_BUF0_RDY_33[1] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33 (1) //!< Bit position for IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33.
|
|
#define BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33 (0x00000002) //!< Bit mask for IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33) >> BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33.
|
|
#define BF_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33) & BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF0_RDY_33 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33(x, v) (HW_IPU_ALT_CH_BUF0_RDY1_WR(x, (HW_IPU_ALT_CH_BUF0_RDY1_RD(x) & ~BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33) | BF_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF0_RDY1, field DMA_CH_ALT_BUF0_RDY_41[9] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41 (9) //!< Bit position for IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41.
|
|
#define BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41 (0x00000200) //!< Bit mask for IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41) >> BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41.
|
|
#define BF_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41) & BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF0_RDY_41 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41(x, v) (HW_IPU_ALT_CH_BUF0_RDY1_WR(x, (HW_IPU_ALT_CH_BUF0_RDY1_RD(x) & ~BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41) | BF_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF0_RDY1, field DMA_CH_ALT_BUF0_RDY_52[20] (RW)
|
|
*
|
|
* Buffer 0 is ready. This bit indicates that ARM platform finished/writing reading buffer 0 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 0 is not ready.
|
|
* - 1 - Buffer 0 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52 (20) //!< Bit position for IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52.
|
|
#define BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52 (0x00100000) //!< Bit mask for IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52) >> BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52.
|
|
#define BF_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52) & BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF0_RDY_52 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52(x, v) (HW_IPU_ALT_CH_BUF0_RDY1_WR(x, (HW_IPU_ALT_CH_BUF0_RDY1_RD(x) & ~BM_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52) | BF_IPU_ALT_CH_BUF0_RDY1_DMA_CH_ALT_BUF0_RDY_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CH_BUF1_RDY0 - IPU Alternate Channels Buffer1 Ready 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CH_BUF1_RDY0 - IPU Alternate Channels Buffer1 Ready 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 1 ready control information for 32 IPU's DMA channels (31-0).
|
|
* Writing "1" to each field will set each bit. Writing "0" to each field simultaneously will clear
|
|
* all the bits. The register is shown in , and the register fields are described in .
|
|
*/
|
|
typedef union _hw_ipu_alt_ch_buf1_rdy0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_ch_buf1_rdy0_bitfields
|
|
{
|
|
unsigned RESERVED0 : 24; //!< [23:0] Reserved.
|
|
unsigned DMA_CH_ALT_BUF1_RDY_24 : 1; //!< [24] Buffer 1 is ready.
|
|
unsigned RESERVED1 : 4; //!< [28:25] Reserved.
|
|
unsigned DMA_CH_ALT_BUF1_RDY_29 : 1; //!< [29] Buffer 1 is ready.
|
|
unsigned RESERVED2 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_ch_buf1_rdy0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CH_BUF1_RDY0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0_ADDR(x) (REGS_IPU_BASE(x) + 0x280)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0(x) (*(volatile hw_ipu_alt_ch_buf1_rdy0_t *) HW_IPU_ALT_CH_BUF1_RDY0_ADDR(x))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0_RD(x) (HW_IPU_ALT_CH_BUF1_RDY0(x).U)
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0_WR(x, v) (HW_IPU_ALT_CH_BUF1_RDY0(x).U = (v))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0_SET(x, v) (HW_IPU_ALT_CH_BUF1_RDY0_WR(x, HW_IPU_ALT_CH_BUF1_RDY0_RD(x) | (v)))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0_CLR(x, v) (HW_IPU_ALT_CH_BUF1_RDY0_WR(x, HW_IPU_ALT_CH_BUF1_RDY0_RD(x) & ~(v)))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY0_TOG(x, v) (HW_IPU_ALT_CH_BUF1_RDY0_WR(x, HW_IPU_ALT_CH_BUF1_RDY0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CH_BUF1_RDY0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF1_RDY0, field DMA_CH_ALT_BUF1_RDY_24[24] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24 (24) //!< Bit position for IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24.
|
|
#define BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24 (0x01000000) //!< Bit mask for IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24) >> BP_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24.
|
|
#define BF_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24) & BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF1_RDY_24 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24(x, v) (HW_IPU_ALT_CH_BUF1_RDY0_WR(x, (HW_IPU_ALT_CH_BUF1_RDY0_RD(x) & ~BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24) | BF_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF1_RDY0, field DMA_CH_ALT_BUF1_RDY_29[29] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29 (29) //!< Bit position for IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29.
|
|
#define BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29 (0x20000000) //!< Bit mask for IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29) >> BP_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29.
|
|
#define BF_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29) & BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF1_RDY_29 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29(x, v) (HW_IPU_ALT_CH_BUF1_RDY0_WR(x, (HW_IPU_ALT_CH_BUF1_RDY0_RD(x) & ~BM_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29) | BF_IPU_ALT_CH_BUF1_RDY0_DMA_CH_ALT_BUF1_RDY_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_ALT_CH_BUF1_RDY1 - IPU Alternate Channels Buffer 1 Ready 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_ALT_CH_BUF1_RDY1 - IPU Alternate Channels Buffer 1 Ready 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 0 ready control information for 32 IPU's DMA channels (63-32).
|
|
* Writing "1" to each field will set each bit. Writing "0" to each field simultaneously will clear
|
|
* all the bits. The register is shown in , and the register fields are described in .
|
|
*/
|
|
typedef union _hw_ipu_alt_ch_buf1_rdy1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_alt_ch_buf1_rdy1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned DMA_CH_ALT_BUF1_RDY_33 : 1; //!< [1] Buffer 1 is ready.
|
|
unsigned RESERVED1 : 7; //!< [8:2] Reserved.
|
|
unsigned DMA_CH_ALT_BUF1_RDY_41 : 1; //!< [9] Buffer 1 is ready.
|
|
unsigned RESERVED2 : 10; //!< [19:10] Reserved.
|
|
unsigned DMA_CH_ALT_BUF1_RDY_52 : 1; //!< [20] Buffer 1 is ready.
|
|
unsigned RESERVED3 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_alt_ch_buf1_rdy1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_ALT_CH_BUF1_RDY1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_ALT_CH_BUF1_RDY1_ADDR(x) (REGS_IPU_BASE(x) + 0x284)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_ALT_CH_BUF1_RDY1(x) (*(volatile hw_ipu_alt_ch_buf1_rdy1_t *) HW_IPU_ALT_CH_BUF1_RDY1_ADDR(x))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY1_RD(x) (HW_IPU_ALT_CH_BUF1_RDY1(x).U)
|
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#define HW_IPU_ALT_CH_BUF1_RDY1_WR(x, v) (HW_IPU_ALT_CH_BUF1_RDY1(x).U = (v))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY1_SET(x, v) (HW_IPU_ALT_CH_BUF1_RDY1_WR(x, HW_IPU_ALT_CH_BUF1_RDY1_RD(x) | (v)))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY1_CLR(x, v) (HW_IPU_ALT_CH_BUF1_RDY1_WR(x, HW_IPU_ALT_CH_BUF1_RDY1_RD(x) & ~(v)))
|
|
#define HW_IPU_ALT_CH_BUF1_RDY1_TOG(x, v) (HW_IPU_ALT_CH_BUF1_RDY1_WR(x, HW_IPU_ALT_CH_BUF1_RDY1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_ALT_CH_BUF1_RDY1 bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_ALT_CH_BUF1_RDY1, field DMA_CH_ALT_BUF1_RDY_33[1] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33 (1) //!< Bit position for IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33.
|
|
#define BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33 (0x00000002) //!< Bit mask for IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33.
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|
|
|
//! @brief Get value of IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33) >> BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33.
|
|
#define BF_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33) & BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF1_RDY_33 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33(x, v) (HW_IPU_ALT_CH_BUF1_RDY1_WR(x, (HW_IPU_ALT_CH_BUF1_RDY1_RD(x) & ~BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33) | BF_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF1_RDY1, field DMA_CH_ALT_BUF1_RDY_41[9] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41 (9) //!< Bit position for IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41.
|
|
#define BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41 (0x00000200) //!< Bit mask for IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41) >> BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41.
|
|
#define BF_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41) & BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF1_RDY_41 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41(x, v) (HW_IPU_ALT_CH_BUF1_RDY1_WR(x, (HW_IPU_ALT_CH_BUF1_RDY1_RD(x) & ~BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41) | BF_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_ALT_CH_BUF1_RDY1, field DMA_CH_ALT_BUF1_RDY_52[20] (RW)
|
|
*
|
|
* Buffer 1 is ready. This bit indicates that ARM platform finished/writing reading buffer 1 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 1 is not ready.
|
|
* - 1 - buffer 1 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52 (20) //!< Bit position for IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52.
|
|
#define BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52 (0x00100000) //!< Bit mask for IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52.
|
|
|
|
//! @brief Get value of IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52 from a register value.
|
|
#define BG_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52) >> BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52)
|
|
|
|
//! @brief Format value for bitfield IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52.
|
|
#define BF_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52) & BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF1_RDY_52 field to a new value.
|
|
#define BW_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52(x, v) (HW_IPU_ALT_CH_BUF1_RDY1_WR(x, (HW_IPU_ALT_CH_BUF1_RDY1_RD(x) & ~BM_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52) | BF_IPU_ALT_CH_BUF1_RDY1_DMA_CH_ALT_BUF1_RDY_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CH_BUF2_RDY0 - IPU Channels Buffer 2 Ready 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CH_BUF2_RDY0 - IPU Channels Buffer 2 Ready 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 2 ready control information for 32 IPU's DMA channels (31-0). This
|
|
* register can be a write one to set or a write one to clear according to the IPU_CH_BUF2_RDY0_CLR
|
|
* bit . The register is shown in , and the register fields are described in .
|
|
*/
|
|
typedef union _hw_ipu_ch_buf2_rdy0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ch_buf2_rdy0_bitfields
|
|
{
|
|
unsigned DMA_CH_BUF2_RDY_0 : 1; //!< [0] Buffer 2 is ready.
|
|
unsigned RESERVED0 : 1; //!< [1] Reserved.
|
|
unsigned DMA_CH_BUF2_RDY_2 : 1; //!< [2] Buffer 2 is ready.
|
|
unsigned RESERVED1 : 5; //!< [7:3] Reserved.
|
|
unsigned DMA_CH_BUF2_RDY_8 : 1; //!< [8] Buffer 2 is ready.
|
|
unsigned DMA_CH_BUF2_RDY_9 : 1; //!< [9] Buffer 2 is ready.
|
|
unsigned DMA_CH_BUF2_RDY_10 : 1; //!< [10] Buffer 2 is ready.
|
|
unsigned RESERVED2 : 2; //!< [12:11] Reserved.
|
|
unsigned DMA_CH_BUF2_RDY_13 : 1; //!< [13] Buffer 2 is ready.
|
|
unsigned RESERVED3 : 7; //!< [20:14] Reserved.
|
|
unsigned DMA_CH_BUF2_RDY_21 : 1; //!< [21] Buffer 2 is ready.
|
|
unsigned RESERVED4 : 1; //!< [22] Reserved.
|
|
unsigned DMA_CH_BUF2_RDY_23 : 1; //!< [23] Buffer 2 is ready.
|
|
unsigned RESERVED5 : 3; //!< [26:24] Reserved.
|
|
unsigned DMA_CH_ALT_BUF1_RDY_27 : 1; //!< [27] buffer 2 is ready.
|
|
unsigned DMA_CH_BUF2_RDY_28 : 1; //!< [28] Buffer 2 is ready.
|
|
unsigned RESERVED6 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_ch_buf2_rdy0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_BUF2_RDY0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_BUF2_RDY0_ADDR(x) (REGS_IPU_BASE(x) + 0x288)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_BUF2_RDY0(x) (*(volatile hw_ipu_ch_buf2_rdy0_t *) HW_IPU_CH_BUF2_RDY0_ADDR(x))
|
|
#define HW_IPU_CH_BUF2_RDY0_RD(x) (HW_IPU_CH_BUF2_RDY0(x).U)
|
|
#define HW_IPU_CH_BUF2_RDY0_WR(x, v) (HW_IPU_CH_BUF2_RDY0(x).U = (v))
|
|
#define HW_IPU_CH_BUF2_RDY0_SET(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, HW_IPU_CH_BUF2_RDY0_RD(x) | (v)))
|
|
#define HW_IPU_CH_BUF2_RDY0_CLR(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, HW_IPU_CH_BUF2_RDY0_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_BUF2_RDY0_TOG(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, HW_IPU_CH_BUF2_RDY0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_BUF2_RDY0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_0[0] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0 (0) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0 (0x00000001) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_0 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_2[2] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2 (2) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2 (0x00000004) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_2 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_8[8] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8 (8) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8 (0x00000100) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_8 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_9[9] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9 (9) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9 (0x00000200) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_9 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_10[10] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10 (10) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10 (0x00000400) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10.
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|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_10 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_13[13] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13 (13) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13 (0x00002000) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13.
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|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13)
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|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_13 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_21[21] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21 (21) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21 (0x00200000) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_21 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_23[23] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23 (23) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23 (0x00800000) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_23 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_ALT_BUF1_RDY_27[27] (RW)
|
|
*
|
|
* buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - buffer 2 is not ready.
|
|
* - 1 - buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27 (27) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27 (0x08000000) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27) & BM_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_ALT_BUF1_RDY_27 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27) | BF_IPU_CH_BUF2_RDY0_DMA_CH_ALT_BUF1_RDY_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY0, field DMA_CH_BUF2_RDY_28[28] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28 (28) //!< Bit position for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28.
|
|
#define BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28 (0x10000000) //!< Bit mask for IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28 from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28) >> BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28.
|
|
#define BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28) & BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_28 field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28(x, v) (HW_IPU_CH_BUF2_RDY0_WR(x, (HW_IPU_CH_BUF2_RDY0_RD(x) & ~BM_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28) | BF_IPU_CH_BUF2_RDY0_DMA_CH_BUF2_RDY_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CH_BUF2_RDY1 - IPU Channels Buffer 2 Ready 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CH_BUF2_RDY1 - IPU Channels Buffer 2 Ready 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register contains buffer 2 ready control information for 32 IPU's DMA channels (63-32). This
|
|
* register can be a write one to set or a write one to clear according to the IPU_CH_BUF2_RDY1_CLR
|
|
* bit. The register is shown in , and the register fields are described in .
|
|
*/
|
|
typedef union _hw_ipu_ch_buf2_rdy1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ch_buf2_rdy1_bitfields
|
|
{
|
|
unsigned DMA_CH_BUF2_RDY_X : 32; //!< [31:0] Buffer 2 is ready.
|
|
} B;
|
|
} hw_ipu_ch_buf2_rdy1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CH_BUF2_RDY1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CH_BUF2_RDY1_ADDR(x) (REGS_IPU_BASE(x) + 0x28c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CH_BUF2_RDY1(x) (*(volatile hw_ipu_ch_buf2_rdy1_t *) HW_IPU_CH_BUF2_RDY1_ADDR(x))
|
|
#define HW_IPU_CH_BUF2_RDY1_RD(x) (HW_IPU_CH_BUF2_RDY1(x).U)
|
|
#define HW_IPU_CH_BUF2_RDY1_WR(x, v) (HW_IPU_CH_BUF2_RDY1(x).U = (v))
|
|
#define HW_IPU_CH_BUF2_RDY1_SET(x, v) (HW_IPU_CH_BUF2_RDY1_WR(x, HW_IPU_CH_BUF2_RDY1_RD(x) | (v)))
|
|
#define HW_IPU_CH_BUF2_RDY1_CLR(x, v) (HW_IPU_CH_BUF2_RDY1_WR(x, HW_IPU_CH_BUF2_RDY1_RD(x) & ~(v)))
|
|
#define HW_IPU_CH_BUF2_RDY1_TOG(x, v) (HW_IPU_CH_BUF2_RDY1_WR(x, HW_IPU_CH_BUF2_RDY1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CH_BUF2_RDY1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CH_BUF2_RDY1, field DMA_CH_BUF2_RDY_X[31:0] (RW)
|
|
*
|
|
* Buffer 2 is ready. This bit indicates that ARM platform finished/writing reading buffer 2 in
|
|
* memory.
|
|
*
|
|
* Values:
|
|
* - 0 - Buffer 2 is not ready.
|
|
* - 1 - Buffer 2 is ready.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X (0) //!< Bit position for IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X.
|
|
#define BM_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X (0xffffffff) //!< Bit mask for IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X.
|
|
|
|
//! @brief Get value of IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X from a register value.
|
|
#define BG_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X) >> BP_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X)
|
|
|
|
//! @brief Format value for bitfield IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X.
|
|
#define BF_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X) & BM_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMA_CH_BUF2_RDY_X field to a new value.
|
|
#define BW_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X(x, v) (HW_IPU_CH_BUF2_RDY1_WR(x, (HW_IPU_CH_BUF2_RDY1_RD(x) & ~BM_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X) | BF_IPU_CH_BUF2_RDY1_DMA_CH_BUF2_RDY_X(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CONF - IDMAC Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CONF - IDMAC Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x0000002f
|
|
*/
|
|
typedef union _hw_ipu_idmac_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_conf_bitfields
|
|
{
|
|
unsigned MAX_REQ_READ : 3; //!< [2:0] Maximum Read Requests.
|
|
unsigned WIDPT : 2; //!< [4:3] Write Interleaving Depth
|
|
unsigned RDI : 1; //!< [5] Read Data Interleaving.
|
|
unsigned RESERVED0 : 10; //!< [15:6] Reserved, should be cleared.
|
|
unsigned P_ENDIAN : 1; //!< [16] Pixel Endianness.
|
|
unsigned USED_BUFS_MAX_W : 3; //!< [19:17] Limit the number of pending non real time write requests.
|
|
unsigned USED_BUFS_EN_W : 1; //!< [20] Enables the limit on the number of pending non real time write requests.
|
|
unsigned USED_BUFS_MAX_R : 4; //!< [24:21] Limit the number of pending non real time read requests.
|
|
unsigned USED_BUFS_EN_R : 1; //!< [25] Enables the limit on the number of pending non real time read requests.
|
|
unsigned RESERVED1 : 6; //!< [31:26] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_idmac_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x1f40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CONF(x) (*(volatile hw_ipu_idmac_conf_t *) HW_IPU_IDMAC_CONF_ADDR(x))
|
|
#define HW_IPU_IDMAC_CONF_RD(x) (HW_IPU_IDMAC_CONF(x).U)
|
|
#define HW_IPU_IDMAC_CONF_WR(x, v) (HW_IPU_IDMAC_CONF(x).U = (v))
|
|
#define HW_IPU_IDMAC_CONF_SET(x, v) (HW_IPU_IDMAC_CONF_WR(x, HW_IPU_IDMAC_CONF_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_CONF_CLR(x, v) (HW_IPU_IDMAC_CONF_WR(x, HW_IPU_IDMAC_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_CONF_TOG(x, v) (HW_IPU_IDMAC_CONF_WR(x, HW_IPU_IDMAC_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field MAX_REQ_READ[2:0] (RW)
|
|
*
|
|
* Maximum Read Requests. This fields sets the maximum pending requests allowed in the AXI Read
|
|
* requests queue.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_MAX_REQ_READ (0) //!< Bit position for IPU_IDMAC_CONF_MAX_REQ_READ.
|
|
#define BM_IPU_IDMAC_CONF_MAX_REQ_READ (0x00000007) //!< Bit mask for IPU_IDMAC_CONF_MAX_REQ_READ.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_MAX_REQ_READ from a register value.
|
|
#define BG_IPU_IDMAC_CONF_MAX_REQ_READ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_MAX_REQ_READ) >> BP_IPU_IDMAC_CONF_MAX_REQ_READ)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_MAX_REQ_READ.
|
|
#define BF_IPU_IDMAC_CONF_MAX_REQ_READ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_MAX_REQ_READ) & BM_IPU_IDMAC_CONF_MAX_REQ_READ)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAX_REQ_READ field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_MAX_REQ_READ(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_MAX_REQ_READ) | BF_IPU_IDMAC_CONF_MAX_REQ_READ(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field WIDPT[4:3] (RW)
|
|
*
|
|
* Write Interleaving Depth These 2 bits define the Write Interleaving Depth of the AXI port. This
|
|
* bits should be configured by the user according to the AXI slave's Write Interleaving Depth.
|
|
* WIDPT defines the maximal number of active bursts (yet to be responded) with different IDs. IDMAC
|
|
* will block data phase if the next data's ID is new (no such ID active) and the number of active
|
|
* IDs is equal to WIDPT. 00 Write Interleaving Depth of 1 01 Write Interleaving Depth of 2 10 Write
|
|
* Interleaving Depth of 3 11 Write Interleaving Depth of 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_WIDPT (3) //!< Bit position for IPU_IDMAC_CONF_WIDPT.
|
|
#define BM_IPU_IDMAC_CONF_WIDPT (0x00000018) //!< Bit mask for IPU_IDMAC_CONF_WIDPT.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_WIDPT from a register value.
|
|
#define BG_IPU_IDMAC_CONF_WIDPT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_WIDPT) >> BP_IPU_IDMAC_CONF_WIDPT)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_WIDPT.
|
|
#define BF_IPU_IDMAC_CONF_WIDPT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_WIDPT) & BM_IPU_IDMAC_CONF_WIDPT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WIDPT field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_WIDPT(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_WIDPT) | BF_IPU_IDMAC_CONF_WIDPT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field RDI[5] (RW)
|
|
*
|
|
* Read Data Interleaving. This bit must match the slave read data interleaving support. If the AXI
|
|
* slave connected to the IPU supports read data interleaving then this bit must be set. If the AXI
|
|
* slave does not support read data interleaving then the IDMAC can utilize this and issue more
|
|
* address phases on read. In that case it is recommended to have this bit cleared. 0 The AXI slave
|
|
* does not support read data interleaving 1 The AXI slave supports read data interleaving
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_RDI (5) //!< Bit position for IPU_IDMAC_CONF_RDI.
|
|
#define BM_IPU_IDMAC_CONF_RDI (0x00000020) //!< Bit mask for IPU_IDMAC_CONF_RDI.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_RDI from a register value.
|
|
#define BG_IPU_IDMAC_CONF_RDI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_RDI) >> BP_IPU_IDMAC_CONF_RDI)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_RDI.
|
|
#define BF_IPU_IDMAC_CONF_RDI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_RDI) & BM_IPU_IDMAC_CONF_RDI)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RDI field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_RDI(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_RDI) | BF_IPU_IDMAC_CONF_RDI(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field P_ENDIAN[16] (RW)
|
|
*
|
|
* Pixel Endianness. The pixel Endianness must not be changed while any of the IDMAC channels is
|
|
* enabled. 0 little endian 1 Big endian
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_P_ENDIAN (16) //!< Bit position for IPU_IDMAC_CONF_P_ENDIAN.
|
|
#define BM_IPU_IDMAC_CONF_P_ENDIAN (0x00010000) //!< Bit mask for IPU_IDMAC_CONF_P_ENDIAN.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_P_ENDIAN from a register value.
|
|
#define BG_IPU_IDMAC_CONF_P_ENDIAN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_P_ENDIAN) >> BP_IPU_IDMAC_CONF_P_ENDIAN)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_P_ENDIAN.
|
|
#define BF_IPU_IDMAC_CONF_P_ENDIAN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_P_ENDIAN) & BM_IPU_IDMAC_CONF_P_ENDIAN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the P_ENDIAN field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_P_ENDIAN(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_P_ENDIAN) | BF_IPU_IDMAC_CONF_P_ENDIAN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field USED_BUFS_MAX_W[19:17] (RW)
|
|
*
|
|
* Limit the number of pending non real time write requests. The value can be between 0 to 6. This
|
|
* field has no affect if USED_BUFS_EN_W is cleared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_USED_BUFS_MAX_W (17) //!< Bit position for IPU_IDMAC_CONF_USED_BUFS_MAX_W.
|
|
#define BM_IPU_IDMAC_CONF_USED_BUFS_MAX_W (0x000e0000) //!< Bit mask for IPU_IDMAC_CONF_USED_BUFS_MAX_W.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_USED_BUFS_MAX_W from a register value.
|
|
#define BG_IPU_IDMAC_CONF_USED_BUFS_MAX_W(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_USED_BUFS_MAX_W) >> BP_IPU_IDMAC_CONF_USED_BUFS_MAX_W)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_USED_BUFS_MAX_W.
|
|
#define BF_IPU_IDMAC_CONF_USED_BUFS_MAX_W(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_USED_BUFS_MAX_W) & BM_IPU_IDMAC_CONF_USED_BUFS_MAX_W)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the USED_BUFS_MAX_W field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_USED_BUFS_MAX_W(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_USED_BUFS_MAX_W) | BF_IPU_IDMAC_CONF_USED_BUFS_MAX_W(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field USED_BUFS_EN_W[20] (RW)
|
|
*
|
|
* Enables the limit on the number of pending non real time write requests.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_USED_BUFS_EN_W (20) //!< Bit position for IPU_IDMAC_CONF_USED_BUFS_EN_W.
|
|
#define BM_IPU_IDMAC_CONF_USED_BUFS_EN_W (0x00100000) //!< Bit mask for IPU_IDMAC_CONF_USED_BUFS_EN_W.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_USED_BUFS_EN_W from a register value.
|
|
#define BG_IPU_IDMAC_CONF_USED_BUFS_EN_W(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_USED_BUFS_EN_W) >> BP_IPU_IDMAC_CONF_USED_BUFS_EN_W)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_USED_BUFS_EN_W.
|
|
#define BF_IPU_IDMAC_CONF_USED_BUFS_EN_W(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_USED_BUFS_EN_W) & BM_IPU_IDMAC_CONF_USED_BUFS_EN_W)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the USED_BUFS_EN_W field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_USED_BUFS_EN_W(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_USED_BUFS_EN_W) | BF_IPU_IDMAC_CONF_USED_BUFS_EN_W(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field USED_BUFS_MAX_R[24:21] (RW)
|
|
*
|
|
* Limit the number of pending non real time read requests. The value can be between 0 to 8. This
|
|
* field has no affect if USED_BUFS_EN_R is cleared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_USED_BUFS_MAX_R (21) //!< Bit position for IPU_IDMAC_CONF_USED_BUFS_MAX_R.
|
|
#define BM_IPU_IDMAC_CONF_USED_BUFS_MAX_R (0x01e00000) //!< Bit mask for IPU_IDMAC_CONF_USED_BUFS_MAX_R.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_USED_BUFS_MAX_R from a register value.
|
|
#define BG_IPU_IDMAC_CONF_USED_BUFS_MAX_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_USED_BUFS_MAX_R) >> BP_IPU_IDMAC_CONF_USED_BUFS_MAX_R)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_USED_BUFS_MAX_R.
|
|
#define BF_IPU_IDMAC_CONF_USED_BUFS_MAX_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_USED_BUFS_MAX_R) & BM_IPU_IDMAC_CONF_USED_BUFS_MAX_R)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the USED_BUFS_MAX_R field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_USED_BUFS_MAX_R(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_USED_BUFS_MAX_R) | BF_IPU_IDMAC_CONF_USED_BUFS_MAX_R(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CONF, field USED_BUFS_EN_R[25] (RW)
|
|
*
|
|
* Enables the limit on the number of pending non real time read requests.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CONF_USED_BUFS_EN_R (25) //!< Bit position for IPU_IDMAC_CONF_USED_BUFS_EN_R.
|
|
#define BM_IPU_IDMAC_CONF_USED_BUFS_EN_R (0x02000000) //!< Bit mask for IPU_IDMAC_CONF_USED_BUFS_EN_R.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CONF_USED_BUFS_EN_R from a register value.
|
|
#define BG_IPU_IDMAC_CONF_USED_BUFS_EN_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CONF_USED_BUFS_EN_R) >> BP_IPU_IDMAC_CONF_USED_BUFS_EN_R)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CONF_USED_BUFS_EN_R.
|
|
#define BF_IPU_IDMAC_CONF_USED_BUFS_EN_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CONF_USED_BUFS_EN_R) & BM_IPU_IDMAC_CONF_USED_BUFS_EN_R)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the USED_BUFS_EN_R field to a new value.
|
|
#define BW_IPU_IDMAC_CONF_USED_BUFS_EN_R(x, v) (HW_IPU_IDMAC_CONF_WR(x, (HW_IPU_IDMAC_CONF_RD(x) & ~BM_IPU_IDMAC_CONF_USED_BUFS_EN_R) | BF_IPU_IDMAC_CONF_USED_BUFS_EN_R(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CH_EN_1 - IDMAC Channel Enable 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CH_EN_1 - IDMAC Channel Enable 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_ch_en_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_ch_en_1_bitfields
|
|
{
|
|
unsigned IDMAC_CH_EN_0 : 1; //!< [0] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_1 : 1; //!< [1] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_2 : 1; //!< [2] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_3 : 1; //!< [3] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_CH_EN_5 : 1; //!< [5] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_CH_EN_8 : 1; //!< [8] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_9 : 1; //!< [9] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_10 : 1; //!< [10] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_11 : 1; //!< [11] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_12 : 1; //!< [12] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_13 : 1; //!< [13] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_14 : 1; //!< [14] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_15 : 1; //!< [15] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_CH_EN_17 : 1; //!< [17] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_18 : 1; //!< [18] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_19 : 1; //!< [19] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_20 : 1; //!< [20] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_21 : 1; //!< [21] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_22 : 1; //!< [22] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_23 : 1; //!< [23] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_24 : 1; //!< [24] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_25 : 1; //!< [25] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_26 : 1; //!< [26] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_27 : 1; //!< [27] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_28 : 1; //!< [28] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_29 : 1; //!< [29] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED3 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_CH_EN_31 : 1; //!< [31] IDMAC Channel enable bit [i]
|
|
} B;
|
|
} hw_ipu_idmac_ch_en_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CH_EN_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CH_EN_1_ADDR(x) (REGS_IPU_BASE(x) + 0x1f44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CH_EN_1(x) (*(volatile hw_ipu_idmac_ch_en_1_t *) HW_IPU_IDMAC_CH_EN_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_CH_EN_1_RD(x) (HW_IPU_IDMAC_CH_EN_1(x).U)
|
|
#define HW_IPU_IDMAC_CH_EN_1_WR(x, v) (HW_IPU_IDMAC_CH_EN_1(x).U = (v))
|
|
#define HW_IPU_IDMAC_CH_EN_1_SET(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, HW_IPU_IDMAC_CH_EN_1_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_CH_EN_1_CLR(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, HW_IPU_IDMAC_CH_EN_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_CH_EN_1_TOG(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, HW_IPU_IDMAC_CH_EN_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CH_EN_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_0[0] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0 (0) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0 (0x00000001) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_0 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_1[1] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1 (1) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1 (0x00000002) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1)
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//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1.
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|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_CH_EN_1 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_1(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_2[2] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2 (2) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2.
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#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2 (0x00000004) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2.
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//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2 from a register value.
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#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2)
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//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2.
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|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_CH_EN_2 field to a new value.
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#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_3[3] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
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|
*/
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//@{
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#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3 (3) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3.
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#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3 (0x00000008) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3.
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//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3 from a register value.
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#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3)
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//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3.
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|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_CH_EN_3 field to a new value.
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|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_3(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_5[5] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5 (5) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5.
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#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5 (0x00000020) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5.
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//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5 from a register value.
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|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5)
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|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5.
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|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_5 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_5(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_8[8] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
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|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8 (8) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8.
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|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8 (0x00000100) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_8 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_8(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_9[9] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9 (9) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9.
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|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9 (0x00000200) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_9 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_10[10] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10 (10) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10 (0x00000400) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_10 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_11[11] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11 (11) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11 (0x00000800) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_11 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_12[12] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12 (12) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12 (0x00001000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_12 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_13[13] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13 (13) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13 (0x00002000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_13 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_14[14] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14 (14) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14 (0x00004000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_14 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_15[15] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15 (15) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15 (0x00008000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_15 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_17[17] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17 (17) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17 (0x00020000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_17 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_17(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_18[18] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18 (18) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18 (0x00040000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_18 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_19[19] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19 (19) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19 (0x00080000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_19 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_20[20] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20 (20) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20 (0x00100000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_20 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_21[21] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21 (21) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21 (0x00200000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_21 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_22[22] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22 (22) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22 (0x00400000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_22 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_23[23] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23 (23) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23 (0x00800000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_23 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_24[24] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24 (24) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24 (0x01000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_24 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_25[25] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25 (25) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25 (0x02000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_25 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_26[26] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26 (26) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26 (0x04000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_26 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_27[27] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27 (27) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27 (0x08000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_27 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_27(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_28[28] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28 (28) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28.
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|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28 (0x10000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28.
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|
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//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28)
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|
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|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_CH_EN_28 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_28(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_29[29] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
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|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29 (29) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29.
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|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29 (0x20000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_29 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_29(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_1, field IDMAC_CH_EN_31[31] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31 (31) //!< Bit position for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31.
|
|
#define BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31 (0x80000000) //!< Bit mask for IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31) >> BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31.
|
|
#define BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31) & BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_31 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31(x, v) (HW_IPU_IDMAC_CH_EN_1_WR(x, (HW_IPU_IDMAC_CH_EN_1_RD(x) & ~BM_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31) | BF_IPU_IDMAC_CH_EN_1_IDMAC_CH_EN_31(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CH_EN_2 - IDMAC Channel Enable 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CH_EN_2 - IDMAC Channel Enable 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_ch_en_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_ch_en_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_CH_EN_33 : 1; //!< [1] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_CH_EN_40 : 1; //!< [8] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_41 : 1; //!< [9] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_42 : 1; //!< [10] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_43 : 1; //!< [11] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_44 : 1; //!< [12] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_45 : 1; //!< [13] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_46 : 1; //!< [14] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_47 : 1; //!< [15] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_48 : 1; //!< [16] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_49 : 1; //!< [17] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_50 : 1; //!< [18] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_51 : 1; //!< [19] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_EN_52 : 1; //!< [20] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_ch_en_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CH_EN_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CH_EN_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1f48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CH_EN_2(x) (*(volatile hw_ipu_idmac_ch_en_2_t *) HW_IPU_IDMAC_CH_EN_2_ADDR(x))
|
|
#define HW_IPU_IDMAC_CH_EN_2_RD(x) (HW_IPU_IDMAC_CH_EN_2(x).U)
|
|
#define HW_IPU_IDMAC_CH_EN_2_WR(x, v) (HW_IPU_IDMAC_CH_EN_2(x).U = (v))
|
|
#define HW_IPU_IDMAC_CH_EN_2_SET(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, HW_IPU_IDMAC_CH_EN_2_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_CH_EN_2_CLR(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, HW_IPU_IDMAC_CH_EN_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_CH_EN_2_TOG(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, HW_IPU_IDMAC_CH_EN_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CH_EN_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_33[1] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33 (1) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33 (0x00000002) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_33 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_33(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_40[8] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40 (8) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40 (0x00000100) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_40 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_40(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_41[9] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41 (9) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41 (0x00000200) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_41 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_42[10] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42 (10) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42 (0x00000400) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_42 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_42(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_43[11] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43 (11) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43 (0x00000800) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_43 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_43(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_44[12] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44 (12) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44 (0x00001000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_44 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_44(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_45[13] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45 (13) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45 (0x00002000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_45 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_46[14] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46 (14) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46 (0x00004000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_46 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_47[15] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47 (15) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47 (0x00008000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_47 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_48[16] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48 (16) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48 (0x00010000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_48 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_49[17] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49 (17) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49 (0x00020000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_49 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_50[18] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50 (18) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50 (0x00040000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_50 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_51[19] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51 (19) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51 (0x00080000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_51 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_EN_2, field IDMAC_CH_EN_52[20] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel is disabled
|
|
* - 1 - IDMAC channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52 (20) //!< Bit position for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52.
|
|
#define BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52 (0x00100000) //!< Bit mask for IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52 from a register value.
|
|
#define BG_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52) >> BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52.
|
|
#define BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52) & BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_EN_52 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52(x, v) (HW_IPU_IDMAC_CH_EN_2_WR(x, (HW_IPU_IDMAC_CH_EN_2_RD(x) & ~BM_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52) | BF_IPU_IDMAC_CH_EN_2_IDMAC_CH_EN_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_ALT_SEP_ALPHA - IDMAC Alternate Separate Alpha Indication Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_ALT_SEP_ALPHA - IDMAC Alternate Separate Alpha Indication Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_alt_sep_alpha
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_alt_sep_alpha_bitfields
|
|
{
|
|
unsigned RESERVED0 : 23; //!< [22:0] Reserved.
|
|
unsigned IDMAC_ALT_SEP_AL_23 : 1; //!< [23] IDMAC Alternate Separate alpha indication bit [i]
|
|
unsigned IDMAC_ALT_SEP_AL_24 : 1; //!< [24] IDMAC Alternate Separate alpha indication bit [i]
|
|
unsigned RESERVED1 : 4; //!< [28:25] Reserved.
|
|
unsigned IDMAC_ALT_SEP_AL_29 : 1; //!< [29] IDMAC Alternate Separate alpha indication bit [i]
|
|
unsigned RESERVED2 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_alt_sep_alpha_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_ALT_SEP_ALPHA register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA_ADDR(x) (REGS_IPU_BASE(x) + 0x1f4a)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA(x) (*(volatile hw_ipu_idmac_alt_sep_alpha_t *) HW_IPU_IDMAC_ALT_SEP_ALPHA_ADDR(x))
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) (HW_IPU_IDMAC_ALT_SEP_ALPHA(x).U)
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA(x).U = (v))
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA_SET(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA_CLR(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_ALT_SEP_ALPHA_TOG(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_ALT_SEP_ALPHA bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_ALT_SEP_ALPHA, field IDMAC_ALT_SEP_AL_23[23] (RW)
|
|
*
|
|
* IDMAC Alternate Separate alpha indication bit [i] A sub block may need to read data from the
|
|
* system's memory where the pixel data and the alpha transparency data are located in separate
|
|
* buffers. In that case the Alpha transparency data is read by the special Alpha channel. In a case
|
|
* where the alpha should be read from a separate buffer, the user should set the channels
|
|
* corresponding. For channels that may have alternate flow and may use separate alpha. This bit
|
|
* indicates the mode of the alpha for the alternate flow
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23 (23) //!< Bit position for IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23.
|
|
#define BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23 (0x00800000) //!< Bit mask for IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23 from a register value.
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|
#define BG_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23) >> BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23)
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//! @brief Format value for bitfield IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23.
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|
#define BF_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23) & BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_ALT_SEP_AL_23 field to a new value.
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|
#define BW_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23) | BF_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_23(v)))
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#endif
|
|
//@}
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|
|
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/*! @name Register IPU_IDMAC_ALT_SEP_ALPHA, field IDMAC_ALT_SEP_AL_24[24] (RW)
|
|
*
|
|
* IDMAC Alternate Separate alpha indication bit [i] A sub block may need to read data from the
|
|
* system's memory where the pixel data and the alpha transparency data are located in separate
|
|
* buffers. In that case the Alpha transparency data is read by the special Alpha channel. In a case
|
|
* where the alpha should be read from a separate buffer, the user should set the channels
|
|
* corresponding. For channels that may have alternate flow and may use separate alpha. This bit
|
|
* indicates the mode of the alpha for the alternate flow
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
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|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24 (24) //!< Bit position for IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24.
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|
#define BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24 (0x01000000) //!< Bit mask for IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24.
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//! @brief Get value of IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24 from a register value.
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|
#define BG_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24) >> BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24)
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//! @brief Format value for bitfield IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24.
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|
#define BF_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24) & BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_ALT_SEP_AL_24 field to a new value.
|
|
#define BW_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24) | BF_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_24(v)))
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#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_IDMAC_ALT_SEP_ALPHA, field IDMAC_ALT_SEP_AL_29[29] (RW)
|
|
*
|
|
* IDMAC Alternate Separate alpha indication bit [i] A sub block may need to read data from the
|
|
* system's memory where the pixel data and the alpha transparency data are located in separate
|
|
* buffers. In that case the Alpha transparency data is read by the special Alpha channel. In a case
|
|
* where the alpha should be read from a separate buffer, the user should set the channels
|
|
* corresponding. For channels that may have alternate flow and may use separate alpha. This bit
|
|
* indicates the mode of the alpha for the alternate flow
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29 (29) //!< Bit position for IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29.
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|
#define BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29 (0x20000000) //!< Bit mask for IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29.
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|
|
//! @brief Get value of IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29 from a register value.
|
|
#define BG_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29) >> BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29)
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|
|
//! @brief Format value for bitfield IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29.
|
|
#define BF_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29) & BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_ALT_SEP_AL_29 field to a new value.
|
|
#define BW_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29(x, v) (HW_IPU_IDMAC_ALT_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_ALT_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29) | BF_IPU_IDMAC_ALT_SEP_ALPHA_IDMAC_ALT_SEP_AL_29(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CH_PRI_1 - IDMAC Channel Priority 1 Register
|
|
//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CH_PRI_1 - IDMAC Channel Priority 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_ch_pri_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_ch_pri_1_bitfields
|
|
{
|
|
unsigned IDMAC_CH_PRI_0 : 1; //!< [0] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_1 : 1; //!< [1] IDMAC Channel enable bit [i]
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|
unsigned IDMAC_CH_PRI_2 : 1; //!< [2] IDMAC Channel enable bit [i]
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|
unsigned IDMAC_CH_PRI_3 : 1; //!< [3] IDMAC Channel enable bit [i]
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|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_CH_PRI_5 : 1; //!< [5] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
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|
unsigned IDMAC_CH_PRI_8 : 1; //!< [8] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_9 : 1; //!< [9] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_10 : 1; //!< [10] IDMAC Channel enable bit [i]
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|
unsigned IDMAC_CH_PRI_11 : 1; //!< [11] IDMAC Channel enable bit [i]
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|
unsigned IDMAC_CH_PRI_12 : 1; //!< [12] IDMAC Channel enable bit [i]
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|
unsigned IDMAC_CH_PRI_13 : 1; //!< [13] IDMAC Channel enable bit [i]
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|
unsigned IDMAC_CH_PRI_14 : 1; //!< [14] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_15 : 1; //!< [15] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED2 : 4; //!< [19:16] Reserved.
|
|
unsigned IDMAC_CH_PRI_20 : 1; //!< [20] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_21 : 1; //!< [21] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_22 : 1; //!< [22] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_23 : 1; //!< [23] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_24 : 1; //!< [24] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_25 : 1; //!< [25] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_26 : 1; //!< [26] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_27 : 1; //!< [27] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_28 : 1; //!< [28] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_29 : 1; //!< [29] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED3 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_ch_pri_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CH_PRI_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CH_PRI_1_ADDR(x) (REGS_IPU_BASE(x) + 0x1f4e)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CH_PRI_1(x) (*(volatile hw_ipu_idmac_ch_pri_1_t *) HW_IPU_IDMAC_CH_PRI_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_CH_PRI_1_RD(x) (HW_IPU_IDMAC_CH_PRI_1(x).U)
|
|
#define HW_IPU_IDMAC_CH_PRI_1_WR(x, v) (HW_IPU_IDMAC_CH_PRI_1(x).U = (v))
|
|
#define HW_IPU_IDMAC_CH_PRI_1_SET(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, HW_IPU_IDMAC_CH_PRI_1_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_CH_PRI_1_CLR(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~(v)))
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|
#define HW_IPU_IDMAC_CH_PRI_1_TOG(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, HW_IPU_IDMAC_CH_PRI_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CH_PRI_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_0[0] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0 (0) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0 (0x00000001) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_0 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_1[1] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1 (1) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1 (0x00000002) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_1 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_2[2] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2 (2) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2 (0x00000004) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_2 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_3[3] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3 (3) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3 (0x00000008) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_3 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_5[5] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5 (5) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5 (0x00000020) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_5 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_8[8] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8 (8) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8 (0x00000100) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_8 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_9[9] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9 (9) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9 (0x00000200) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_9 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_10[10] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10 (10) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10 (0x00000400) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_10 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_11[11] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11 (11) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11 (0x00000800) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_11 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_12[12] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12 (12) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12 (0x00001000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_12 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_13[13] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13 (13) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13 (0x00002000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_13 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_14[14] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14 (14) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14 (0x00004000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_14 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_15[15] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15 (15) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15 (0x00008000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_15 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_20[20] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20 (20) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20 (0x00100000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_20 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_21[21] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21 (21) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21 (0x00200000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_21 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_22[22] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22 (22) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22 (0x00400000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_22 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_23[23] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23 (23) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23 (0x00800000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_23 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_24[24] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24 (24) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24 (0x01000000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_24 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_25[25] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25 (25) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25 (0x02000000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_25 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_26[26] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26 (26) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26 (0x04000000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_26 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_27[27] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27 (27) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27 (0x08000000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_27 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_28[28] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28 (28) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28 (0x10000000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_28 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_1, field IDMAC_CH_PRI_29[29] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29 (29) //!< Bit position for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29.
|
|
#define BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29 (0x20000000) //!< Bit mask for IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29) >> BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29.
|
|
#define BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29) & BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_29 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29(x, v) (HW_IPU_IDMAC_CH_PRI_1_WR(x, (HW_IPU_IDMAC_CH_PRI_1_RD(x) & ~BM_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29) | BF_IPU_IDMAC_CH_PRI_1_IDMAC_CH_PRI_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CH_PRI_2 - IDMAC Channel Priority 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CH_PRI_2 - IDMAC Channel Priority 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_ch_pri_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_ch_pri_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved.
|
|
unsigned IDMAC_CH_PRI_8 : 1; //!< [8] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_9 : 1; //!< [9] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_10 : 1; //!< [10] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_11 : 1; //!< [11] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_12 : 1; //!< [12] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_13 : 1; //!< [13] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_14 : 1; //!< [14] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_15 : 1; //!< [15] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_16 : 1; //!< [16] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_17 : 1; //!< [17] IDMAC Channel enable bit [i]
|
|
unsigned IDMAC_CH_PRI_18 : 1; //!< [18] IDMAC Channel enable bit [i]
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_ch_pri_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CH_PRI_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CH_PRI_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1f52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CH_PRI_2(x) (*(volatile hw_ipu_idmac_ch_pri_2_t *) HW_IPU_IDMAC_CH_PRI_2_ADDR(x))
|
|
#define HW_IPU_IDMAC_CH_PRI_2_RD(x) (HW_IPU_IDMAC_CH_PRI_2(x).U)
|
|
#define HW_IPU_IDMAC_CH_PRI_2_WR(x, v) (HW_IPU_IDMAC_CH_PRI_2(x).U = (v))
|
|
#define HW_IPU_IDMAC_CH_PRI_2_SET(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, HW_IPU_IDMAC_CH_PRI_2_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_CH_PRI_2_CLR(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_CH_PRI_2_TOG(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, HW_IPU_IDMAC_CH_PRI_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CH_PRI_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_8[8] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8 (8) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8.
|
|
#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8 (0x00000100) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8.
|
|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8)
|
|
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_CH_PRI_8 field to a new value.
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#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_8(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_9[9] (RW)
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*
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* IDMAC Channel enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] is in low priority
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* - 1 - IDMAC channel [i] is in high priority
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*/
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//@{
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#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9 (9) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9 (0x00000200) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9.
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//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9 from a register value.
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#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9)
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//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9.
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#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_CH_PRI_9 field to a new value.
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#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_9(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_10[10] (RW)
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*
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* IDMAC Channel enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] is in low priority
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* - 1 - IDMAC channel [i] is in high priority
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*/
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//@{
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#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10 (10) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10 (0x00000400) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10.
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//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10 from a register value.
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#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10)
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//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10.
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#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_CH_PRI_10 field to a new value.
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#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_10(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_11[11] (RW)
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*
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* IDMAC Channel enable bit [i]
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*
|
|
* Values:
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* - 0 - IDMAC channel [i] is in low priority
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* - 1 - IDMAC channel [i] is in high priority
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*/
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//@{
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#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11 (11) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11 (0x00000800) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11.
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//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11 from a register value.
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#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11)
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//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11.
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#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_CH_PRI_11 field to a new value.
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#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_11(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_12[12] (RW)
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*
|
|
* IDMAC Channel enable bit [i]
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|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
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|
* - 1 - IDMAC channel [i] is in high priority
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|
*/
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//@{
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#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12 (12) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12 (0x00001000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12.
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//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12 from a register value.
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#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12)
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//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12.
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|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_12 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_12(v)))
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#endif
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|
//@}
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_13[13] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
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|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13 (13) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13 (0x00002000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13.
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//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13 from a register value.
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|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13)
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|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13.
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|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_13 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_13(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_14[14] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
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|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14 (14) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14 (0x00004000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14.
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|
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|
//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14.
|
|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_14 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_14(v)))
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|
#endif
|
|
//@}
|
|
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/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_15[15] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15 (15) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15.
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#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15 (0x00008000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15.
|
|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_15 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_16[16] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16 (16) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16.
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|
#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16 (0x00010000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16.
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|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16.
|
|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_16 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_17[17] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17 (17) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17.
|
|
#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17 (0x00020000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17.
|
|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_17 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_PRI_2, field IDMAC_CH_PRI_18[18] (RW)
|
|
*
|
|
* IDMAC Channel enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is in low priority
|
|
* - 1 - IDMAC channel [i] is in high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18 (18) //!< Bit position for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18.
|
|
#define BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18 (0x00040000) //!< Bit mask for IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18 from a register value.
|
|
#define BG_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18) >> BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18.
|
|
#define BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18) & BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_CH_PRI_18 field to a new value.
|
|
#define BW_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18(x, v) (HW_IPU_IDMAC_CH_PRI_2_WR(x, (HW_IPU_IDMAC_CH_PRI_2_RD(x) & ~BM_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18) | BF_IPU_IDMAC_CH_PRI_2_IDMAC_CH_PRI_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
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// HW_IPU_IDMAC_WM_EN_2 - IDMAC Channel Watermark Enable 2 Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_IDMAC_WM_EN_2 - IDMAC Channel Watermark Enable 2 Register (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_idmac_wm_en_2
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{
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reg32_t U;
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struct _hw_ipu_idmac_wm_en_2_bitfields
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{
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unsigned RESERVED0 : 8; //!< [7:0] Reserved.
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unsigned IDMAC_WM_EN_40 : 1; //!< [8] IDMAC Watermark enable bit [i]
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unsigned IDMAC_WM_EN_41 : 1; //!< [9] IDMAC Watermark enable bit [i]
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unsigned IDMAC_WM_EN_42 : 1; //!< [10] IDMAC Watermark enable bit [i]
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unsigned IDMAC_WM_EN_43 : 1; //!< [11] IDMAC Watermark enable bit [i]
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unsigned IDMAC_WM_EN_44 : 1; //!< [12] IDMAC Watermark enable bit [i]
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unsigned RESERVED1 : 19; //!< [31:13] Reserved.
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} B;
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} hw_ipu_idmac_wm_en_2_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_IDMAC_WM_EN_2 register
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*/
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//@{
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#define HW_IPU_IDMAC_WM_EN_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1f54)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_IDMAC_WM_EN_2(x) (*(volatile hw_ipu_idmac_wm_en_2_t *) HW_IPU_IDMAC_WM_EN_2_ADDR(x))
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#define HW_IPU_IDMAC_WM_EN_2_RD(x) (HW_IPU_IDMAC_WM_EN_2(x).U)
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#define HW_IPU_IDMAC_WM_EN_2_WR(x, v) (HW_IPU_IDMAC_WM_EN_2(x).U = (v))
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#define HW_IPU_IDMAC_WM_EN_2_SET(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, HW_IPU_IDMAC_WM_EN_2_RD(x) | (v)))
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#define HW_IPU_IDMAC_WM_EN_2_CLR(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, HW_IPU_IDMAC_WM_EN_2_RD(x) & ~(v)))
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#define HW_IPU_IDMAC_WM_EN_2_TOG(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, HW_IPU_IDMAC_WM_EN_2_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_IDMAC_WM_EN_2 bitfields
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*/
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/*! @name Register IPU_IDMAC_WM_EN_2, field IDMAC_WM_EN_40[8] (RW)
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*
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* IDMAC Watermark enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] watermark feature is disabled
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* - 1 - IDMAC channel [i] watermark feature is enabled
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*/
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//@{
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#define BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40 (8) //!< Bit position for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40.
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#define BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40 (0x00000100) //!< Bit mask for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40.
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//! @brief Get value of IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40 from a register value.
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#define BG_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40) >> BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40)
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//! @brief Format value for bitfield IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40.
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#define BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_WM_EN_40 field to a new value.
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#define BW_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, (HW_IPU_IDMAC_WM_EN_2_RD(x) & ~BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40) | BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_40(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_WM_EN_2, field IDMAC_WM_EN_41[9] (RW)
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*
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* IDMAC Watermark enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] watermark feature is disabled
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* - 1 - IDMAC channel [i] watermark feature is enabled
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*/
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//@{
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#define BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41 (9) //!< Bit position for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41.
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#define BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41 (0x00000200) //!< Bit mask for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41.
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//! @brief Get value of IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41 from a register value.
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#define BG_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41) >> BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41)
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//! @brief Format value for bitfield IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41.
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#define BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_WM_EN_41 field to a new value.
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#define BW_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, (HW_IPU_IDMAC_WM_EN_2_RD(x) & ~BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41) | BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_41(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_WM_EN_2, field IDMAC_WM_EN_42[10] (RW)
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*
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* IDMAC Watermark enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] watermark feature is disabled
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* - 1 - IDMAC channel [i] watermark feature is enabled
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*/
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//@{
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#define BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42 (10) //!< Bit position for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42.
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#define BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42 (0x00000400) //!< Bit mask for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42.
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//! @brief Get value of IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42 from a register value.
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#define BG_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42) >> BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42)
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//! @brief Format value for bitfield IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42.
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#define BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_WM_EN_42 field to a new value.
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#define BW_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, (HW_IPU_IDMAC_WM_EN_2_RD(x) & ~BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42) | BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_42(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_WM_EN_2, field IDMAC_WM_EN_43[11] (RW)
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*
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* IDMAC Watermark enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] watermark feature is disabled
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* - 1 - IDMAC channel [i] watermark feature is enabled
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*/
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//@{
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#define BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43 (11) //!< Bit position for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43.
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#define BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43 (0x00000800) //!< Bit mask for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43.
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//! @brief Get value of IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43 from a register value.
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#define BG_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43) >> BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43)
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//! @brief Format value for bitfield IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43.
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#define BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_WM_EN_43 field to a new value.
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#define BW_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, (HW_IPU_IDMAC_WM_EN_2_RD(x) & ~BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43) | BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_43(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_WM_EN_2, field IDMAC_WM_EN_44[12] (RW)
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*
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* IDMAC Watermark enable bit [i]
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*
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* Values:
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* - 0 - IDMAC channel [i] watermark feature is disabled
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* - 1 - IDMAC channel [i] watermark feature is enabled
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*/
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//@{
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#define BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44 (12) //!< Bit position for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44.
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#define BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44 (0x00001000) //!< Bit mask for IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44.
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//! @brief Get value of IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44 from a register value.
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#define BG_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44) >> BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44)
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//! @brief Format value for bitfield IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44.
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#define BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44) & BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_WM_EN_44 field to a new value.
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#define BW_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44(x, v) (HW_IPU_IDMAC_WM_EN_2_WR(x, (HW_IPU_IDMAC_WM_EN_2_RD(x) & ~BM_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44) | BF_IPU_IDMAC_WM_EN_2_IDMAC_WM_EN_44(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_IDMAC_LOCK_EN_1 - IDMAC Channel Lock Enable 1Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_IDMAC_LOCK_EN_1 - IDMAC Channel Lock Enable 1Register (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_idmac_lock_en_1
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{
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reg32_t U;
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struct _hw_ipu_idmac_lock_en_1_bitfields
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{
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unsigned IDMAC_LOCK_EN_5 : 2; //!< [1:0] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_11 : 2; //!< [3:2] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_12 : 2; //!< [5:4] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_14 : 2; //!< [7:6] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_15 : 2; //!< [9:8] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_20 : 2; //!< [11:10] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_21 : 2; //!< [13:12] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_22 : 2; //!< [15:14] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_23 : 2; //!< [17:16] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_27 : 2; //!< [19:18] IDMAC lock bits for channel [i]
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unsigned IDMAC_LOCK_EN_28 : 2; //!< [21:20] IDMAC lock bits for channel [i]
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unsigned RESERVED0 : 10; //!< [31:22] Reserved.
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} B;
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} hw_ipu_idmac_lock_en_1_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_IDMAC_LOCK_EN_1 register
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*/
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//@{
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#define HW_IPU_IDMAC_LOCK_EN_1_ADDR(x) (REGS_IPU_BASE(x) + 0x1f58)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_IDMAC_LOCK_EN_1(x) (*(volatile hw_ipu_idmac_lock_en_1_t *) HW_IPU_IDMAC_LOCK_EN_1_ADDR(x))
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#define HW_IPU_IDMAC_LOCK_EN_1_RD(x) (HW_IPU_IDMAC_LOCK_EN_1(x).U)
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#define HW_IPU_IDMAC_LOCK_EN_1_WR(x, v) (HW_IPU_IDMAC_LOCK_EN_1(x).U = (v))
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#define HW_IPU_IDMAC_LOCK_EN_1_SET(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, HW_IPU_IDMAC_LOCK_EN_1_RD(x) | (v)))
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#define HW_IPU_IDMAC_LOCK_EN_1_CLR(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~(v)))
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#define HW_IPU_IDMAC_LOCK_EN_1_TOG(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, HW_IPU_IDMAC_LOCK_EN_1_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_IDMAC_LOCK_EN_1 bitfields
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*/
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/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_5[1:0] (RW)
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*
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* IDMAC lock bits for channel [i]
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*
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* Values:
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* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
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* request.
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* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
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* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
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* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
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*/
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//@{
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#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5 (0) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5.
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#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5 (0x00000003) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5.
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//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5 from a register value.
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#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5)
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//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5.
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#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_LOCK_EN_5 field to a new value.
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#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_5(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_11[3:2] (RW)
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*
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* IDMAC lock bits for channel [i]
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*
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* Values:
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* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
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* request.
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* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
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* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
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* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
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*/
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//@{
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#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11 (2) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11.
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#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11 (0x0000000c) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11.
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//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11 from a register value.
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#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11)
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//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11.
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#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IDMAC_LOCK_EN_11 field to a new value.
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#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_11(v)))
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#endif
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//@}
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/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_12[5:4] (RW)
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*
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* IDMAC lock bits for channel [i]
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*
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* Values:
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* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
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* request.
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* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
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* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
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* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
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*/
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//@{
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#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12 (4) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12 (0x00000030) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_12 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_14[7:6] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14 (6) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14 (0x000000c0) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14.
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|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_14 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_15[9:8] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15 (8) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15 (0x00000300) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_15 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_20[11:10] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20 (10) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20 (0x00000c00) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_20 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_21[13:12] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21 (12) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21 (0x00003000) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_21 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_22[15:14] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22 (14) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22 (0x0000c000) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_22 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_23[17:16] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23 (16) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23 (0x00030000) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_23 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_27[19:18] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27 (18) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27 (0x000c0000) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_27 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_1, field IDMAC_LOCK_EN_28[21:20] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28 (20) //!< Bit position for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28.
|
|
#define BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28 (0x00300000) //!< Bit mask for IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28) >> BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28.
|
|
#define BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28) & BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_EN_28 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28(x, v) (HW_IPU_IDMAC_LOCK_EN_1_WR(x, (HW_IPU_IDMAC_LOCK_EN_1_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28) | BF_IPU_IDMAC_LOCK_EN_1_IDMAC_LOCK_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_LOCK_EN_2 - IDMAC Channel Lock Enable 2Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_LOCK_EN_2 - IDMAC Channel Lock Enable 2Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_lock_en_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_lock_en_2_bitfields
|
|
{
|
|
unsigned IDMAC_LOCK_45 : 2; //!< [1:0] IDMAC lock bits for channel [i]
|
|
unsigned IDMAC_LOCK_46 : 2; //!< [3:2] IDMAC lock bits for channel [i]
|
|
unsigned IDMAC_LOCK_47 : 2; //!< [5:4] IDMAC lock bits for channel [i]
|
|
unsigned IDMAC_LOCK_48 : 2; //!< [7:6] IDMAC lock bits for channel [i]
|
|
unsigned IDMAC_LOCK_49 : 2; //!< [9:8] IDMAC lock bits for channel [i]
|
|
unsigned IDMAC_LOCK_50 : 2; //!< [11:10] IDMAC lock bits for channel [i]
|
|
unsigned RESERVED0 : 20; //!< [31:12] Reserved
|
|
} B;
|
|
} hw_ipu_idmac_lock_en_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_LOCK_EN_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_LOCK_EN_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1f5c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_LOCK_EN_2(x) (*(volatile hw_ipu_idmac_lock_en_2_t *) HW_IPU_IDMAC_LOCK_EN_2_ADDR(x))
|
|
#define HW_IPU_IDMAC_LOCK_EN_2_RD(x) (HW_IPU_IDMAC_LOCK_EN_2(x).U)
|
|
#define HW_IPU_IDMAC_LOCK_EN_2_WR(x, v) (HW_IPU_IDMAC_LOCK_EN_2(x).U = (v))
|
|
#define HW_IPU_IDMAC_LOCK_EN_2_SET(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, HW_IPU_IDMAC_LOCK_EN_2_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_LOCK_EN_2_CLR(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_LOCK_EN_2_TOG(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, HW_IPU_IDMAC_LOCK_EN_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_LOCK_EN_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_2, field IDMAC_LOCK_45[1:0] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45 (0) //!< Bit position for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45.
|
|
#define BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45 (0x00000003) //!< Bit mask for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45) >> BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45.
|
|
#define BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_45 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, (HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45) | BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_2, field IDMAC_LOCK_46[3:2] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46 (2) //!< Bit position for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46.
|
|
#define BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46 (0x0000000c) //!< Bit mask for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46) >> BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46.
|
|
#define BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_46 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, (HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46) | BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_2, field IDMAC_LOCK_47[5:4] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47 (4) //!< Bit position for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47.
|
|
#define BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47 (0x00000030) //!< Bit mask for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47) >> BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47.
|
|
#define BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_47 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, (HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47) | BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_47(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_2, field IDMAC_LOCK_48[7:6] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48 (6) //!< Bit position for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48.
|
|
#define BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48 (0x000000c0) //!< Bit mask for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48) >> BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48.
|
|
#define BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_48 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, (HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48) | BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_48(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_2, field IDMAC_LOCK_49[9:8] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49 (8) //!< Bit position for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49.
|
|
#define BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49 (0x00000300) //!< Bit mask for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49) >> BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49.
|
|
#define BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_49 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, (HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49) | BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_49(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_LOCK_EN_2, field IDMAC_LOCK_50[11:10] (RW)
|
|
*
|
|
* IDMAC lock bits for channel [i]
|
|
*
|
|
* Values:
|
|
* - 00 - The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA
|
|
* request.
|
|
* - 01 - The IDMAC will generate two AXI bursts upon the assertion of the DMA request.
|
|
* - 10 - The IDMAC will generate four AXI bursts upon the assertion of the DMA request.
|
|
* - 11 - The IDMAC will generate eight AXI bursts upon the assertion of the DMA request.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50 (10) //!< Bit position for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50.
|
|
#define BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50 (0x00000c00) //!< Bit mask for IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50.
|
|
|
|
//! @brief Get value of IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50 from a register value.
|
|
#define BG_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50) >> BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50.
|
|
#define BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50) & BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_LOCK_50 field to a new value.
|
|
#define BW_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50(x, v) (HW_IPU_IDMAC_LOCK_EN_2_WR(x, (HW_IPU_IDMAC_LOCK_EN_2_RD(x) & ~BM_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50) | BF_IPU_IDMAC_LOCK_EN_2_IDMAC_LOCK_50(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SUB_ADDR_1 - IDMAC Channel Alternate Address 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SUB_ADDR_1 - IDMAC Channel Alternate Address 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sub_addr_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sub_addr_1_bitfields
|
|
{
|
|
unsigned IDMAC_SUB_ADDR_23 : 7; //!< [6:0] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_24 : 7; //!< [14:8] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED1 : 1; //!< [15] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_29 : 7; //!< [22:16] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED2 : 1; //!< [23] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_33 : 7; //!< [30:24] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED3 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_sub_addr_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SUB_ADDR_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1_ADDR(x) (REGS_IPU_BASE(x) + 0x1f5e)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1(x) (*(volatile hw_ipu_idmac_sub_addr_1_t *) HW_IPU_IDMAC_SUB_ADDR_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1_RD(x) (HW_IPU_IDMAC_SUB_ADDR_1(x).U)
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1_WR(x, v) (HW_IPU_IDMAC_SUB_ADDR_1(x).U = (v))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1_SET(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, HW_IPU_IDMAC_SUB_ADDR_1_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1_CLR(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, HW_IPU_IDMAC_SUB_ADDR_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_1_TOG(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, HW_IPU_IDMAC_SUB_ADDR_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SUB_ADDR_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_1, field IDMAC_SUB_ADDR_23[6:0] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23 (0) //!< Bit position for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23 (0x0000007f) //!< Bit mask for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23) >> BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_23 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, (HW_IPU_IDMAC_SUB_ADDR_1_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23) | BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_1, field IDMAC_SUB_ADDR_24[14:8] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24 (8) //!< Bit position for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24 (0x00007f00) //!< Bit mask for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24) >> BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_24 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, (HW_IPU_IDMAC_SUB_ADDR_1_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24) | BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_1, field IDMAC_SUB_ADDR_29[22:16] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29 (16) //!< Bit position for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29 (0x007f0000) //!< Bit mask for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29.
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|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29 from a register value.
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|
#define BG_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29) >> BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29)
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//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_29 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, (HW_IPU_IDMAC_SUB_ADDR_1_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29) | BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_29(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_1, field IDMAC_SUB_ADDR_33[30:24] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33 (24) //!< Bit position for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33.
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|
#define BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33 (0x7f000000) //!< Bit mask for IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33.
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|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33) >> BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33)
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//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33) & BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_33 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33(x, v) (HW_IPU_IDMAC_SUB_ADDR_1_WR(x, (HW_IPU_IDMAC_SUB_ADDR_1_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33) | BF_IPU_IDMAC_SUB_ADDR_1_IDMAC_SUB_ADDR_33(v)))
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|
#endif
|
|
//@}
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SUB_ADDR_2 - IDMAC Channel Alternate Address 2 Register
|
|
//-------------------------------------------------------------------------------------------
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SUB_ADDR_2 - IDMAC Channel Alternate Address 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sub_addr_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sub_addr_2_bitfields
|
|
{
|
|
unsigned IDMAC_SUB_ADDR_41 : 7; //!< [6:0] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_51 : 7; //!< [14:8] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED1 : 1; //!< [15] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_52 : 7; //!< [22:16] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED2 : 9; //!< [31:23] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_sub_addr_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SUB_ADDR_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1f62)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2(x) (*(volatile hw_ipu_idmac_sub_addr_2_t *) HW_IPU_IDMAC_SUB_ADDR_2_ADDR(x))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2_RD(x) (HW_IPU_IDMAC_SUB_ADDR_2(x).U)
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2_WR(x, v) (HW_IPU_IDMAC_SUB_ADDR_2(x).U = (v))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2_SET(x, v) (HW_IPU_IDMAC_SUB_ADDR_2_WR(x, HW_IPU_IDMAC_SUB_ADDR_2_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2_CLR(x, v) (HW_IPU_IDMAC_SUB_ADDR_2_WR(x, HW_IPU_IDMAC_SUB_ADDR_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_2_TOG(x, v) (HW_IPU_IDMAC_SUB_ADDR_2_WR(x, HW_IPU_IDMAC_SUB_ADDR_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SUB_ADDR_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_2, field IDMAC_SUB_ADDR_41[6:0] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41 (0) //!< Bit position for IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41 (0x0000007f) //!< Bit mask for IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41.
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|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41) >> BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41) & BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_41 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41(x, v) (HW_IPU_IDMAC_SUB_ADDR_2_WR(x, (HW_IPU_IDMAC_SUB_ADDR_2_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41) | BF_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_41(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_2, field IDMAC_SUB_ADDR_51[14:8] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51 (8) //!< Bit position for IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51 (0x00007f00) //!< Bit mask for IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51.
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|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51) >> BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51) & BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_51 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51(x, v) (HW_IPU_IDMAC_SUB_ADDR_2_WR(x, (HW_IPU_IDMAC_SUB_ADDR_2_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51) | BF_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_51(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_2, field IDMAC_SUB_ADDR_52[22:16] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52 (16) //!< Bit position for IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52 (0x007f0000) //!< Bit mask for IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52) >> BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52) & BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_52 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52(x, v) (HW_IPU_IDMAC_SUB_ADDR_2_WR(x, (HW_IPU_IDMAC_SUB_ADDR_2_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52) | BF_IPU_IDMAC_SUB_ADDR_2_IDMAC_SUB_ADDR_52(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SUB_ADDR_3 - IDMAC Channel Alternate Address 3 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SUB_ADDR_3 - IDMAC Channel Alternate Address 3 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sub_addr_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sub_addr_3_bitfields
|
|
{
|
|
unsigned IDMAC_SUB_ADDR_9 : 7; //!< [6:0] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_10 : 7; //!< [14:8] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED1 : 1; //!< [15] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_13 : 7; //!< [22:16] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED2 : 1; //!< [23] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_27 : 7; //!< [30:24] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED3 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_sub_addr_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SUB_ADDR_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3_ADDR(x) (REGS_IPU_BASE(x) + 0x1f66)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3(x) (*(volatile hw_ipu_idmac_sub_addr_3_t *) HW_IPU_IDMAC_SUB_ADDR_3_ADDR(x))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3_RD(x) (HW_IPU_IDMAC_SUB_ADDR_3(x).U)
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3_WR(x, v) (HW_IPU_IDMAC_SUB_ADDR_3(x).U = (v))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3_SET(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, HW_IPU_IDMAC_SUB_ADDR_3_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3_CLR(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, HW_IPU_IDMAC_SUB_ADDR_3_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_3_TOG(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, HW_IPU_IDMAC_SUB_ADDR_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SUB_ADDR_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_3, field IDMAC_SUB_ADDR_9[6:0] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9 (0) //!< Bit position for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9 (0x0000007f) //!< Bit mask for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9) >> BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_9 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, (HW_IPU_IDMAC_SUB_ADDR_3_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9) | BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_3, field IDMAC_SUB_ADDR_10[14:8] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10 (8) //!< Bit position for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10 (0x00007f00) //!< Bit mask for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10) >> BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_10 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, (HW_IPU_IDMAC_SUB_ADDR_3_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10) | BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_3, field IDMAC_SUB_ADDR_13[22:16] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13 (16) //!< Bit position for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13 (0x007f0000) //!< Bit mask for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13) >> BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_13 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, (HW_IPU_IDMAC_SUB_ADDR_3_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13) | BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_3, field IDMAC_SUB_ADDR_27[30:24] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27 (24) //!< Bit position for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27 (0x7f000000) //!< Bit mask for IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27) >> BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27) & BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_27 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27(x, v) (HW_IPU_IDMAC_SUB_ADDR_3_WR(x, (HW_IPU_IDMAC_SUB_ADDR_3_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27) | BF_IPU_IDMAC_SUB_ADDR_3_IDMAC_SUB_ADDR_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_BNDM_EN_1 - IDMAC Band Mode Enable 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_BNDM_EN_1 - IDMAC Band Mode Enable 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_bndm_en_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_bndm_en_1_bitfields
|
|
{
|
|
unsigned IDMAC_BNDM_EN_0 : 1; //!< [0] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_1 : 1; //!< [1] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_2 : 1; //!< [2] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_3 : 1; //!< [3] IDMAC Band Mode Enable bit [i]
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_BNDM_EN_5 : 1; //!< [5] IDMAC Band Mode Enable bit [i]
|
|
unsigned RESERVED1 : 5; //!< [10:6] Reserved.
|
|
unsigned IDMAC_BNDM_EN_11 : 1; //!< [11] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_12 : 1; //!< [12] IDMAC Band Mode Enable bit [i]
|
|
unsigned RESERVED2 : 7; //!< [19:13] Reserved.
|
|
unsigned IDMAC_BNDM_EN_20 : 1; //!< [20] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_21 : 1; //!< [21] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_22 : 1; //!< [22] IDMAC Band Mode Enable bit [i]
|
|
unsigned RESERVED3 : 2; //!< [24:23] Reserved.
|
|
unsigned IDMAC_BNDM_EN_25 : 1; //!< [25] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_26 : 1; //!< [26] IDMAC Band Mode Enable bit [i]
|
|
unsigned RESERVED4 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_bndm_en_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_BNDM_EN_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_BNDM_EN_1_ADDR(x) (REGS_IPU_BASE(x) + 0x1f68)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_BNDM_EN_1(x) (*(volatile hw_ipu_idmac_bndm_en_1_t *) HW_IPU_IDMAC_BNDM_EN_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_BNDM_EN_1_RD(x) (HW_IPU_IDMAC_BNDM_EN_1(x).U)
|
|
#define HW_IPU_IDMAC_BNDM_EN_1_WR(x, v) (HW_IPU_IDMAC_BNDM_EN_1(x).U = (v))
|
|
#define HW_IPU_IDMAC_BNDM_EN_1_SET(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, HW_IPU_IDMAC_BNDM_EN_1_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_BNDM_EN_1_CLR(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_BNDM_EN_1_TOG(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, HW_IPU_IDMAC_BNDM_EN_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_BNDM_EN_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_0[0] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0 (0) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0 (0x00000001) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_0 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_1[1] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1 (1) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1 (0x00000002) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_1 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_2[2] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2 (2) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2 (0x00000004) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_2 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_3[3] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3 (3) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3 (0x00000008) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_3 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_5[5] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5 (5) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5 (0x00000020) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_5 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_11[11] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11 (11) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11 (0x00000800) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_11 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_12[12] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12 (12) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12 (0x00001000) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12)
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//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12.
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|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_12 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_12(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_20[20] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
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|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20 (20) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20.
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|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20 (0x00100000) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20.
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//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20 from a register value.
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#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20)
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//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20.
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|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_BNDM_EN_20 field to a new value.
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|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_20(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_21[21] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
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|
* - 1 - IDMAC channel [i] is in band mode
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|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21 (21) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21.
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#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21 (0x00200000) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21.
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//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21 from a register value.
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|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21)
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//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21.
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|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21)
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|
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_BNDM_EN_21 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_21(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_22[22] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
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|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22 (22) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22.
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|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22 (0x00400000) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22.
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//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22 from a register value.
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|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22)
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|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_22 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_22(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_25[25] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25 (25) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25.
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|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25 (0x02000000) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25.
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|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_25 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_25(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_1, field IDMAC_BNDM_EN_26[26] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26 (26) //!< Bit position for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26.
|
|
#define BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26 (0x04000000) //!< Bit mask for IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26.
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|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26) >> BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26)
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|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26.
|
|
#define BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26) & BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_26 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26(x, v) (HW_IPU_IDMAC_BNDM_EN_1_WR(x, (HW_IPU_IDMAC_BNDM_EN_1_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26) | BF_IPU_IDMAC_BNDM_EN_1_IDMAC_BNDM_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_BNDM_EN_2 - IDMAC Band Mode Enable 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_BNDM_EN_2 - IDMAC Band Mode Enable 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_bndm_en_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_bndm_en_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 13; //!< [12:0] Reserved.
|
|
unsigned IDMAC_BNDM_EN_45 : 1; //!< [13] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_46 : 1; //!< [14] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_47 : 1; //!< [15] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_48 : 1; //!< [16] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_49 : 1; //!< [17] IDMAC Band Mode Enable bit [i]
|
|
unsigned IDMAC_BNDM_EN_50 : 1; //!< [18] IDMAC Band Mode Enable bit [i]
|
|
unsigned RESERVED1 : 13; //!< [31:19] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_bndm_en_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_BNDM_EN_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_BNDM_EN_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1f6c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_BNDM_EN_2(x) (*(volatile hw_ipu_idmac_bndm_en_2_t *) HW_IPU_IDMAC_BNDM_EN_2_ADDR(x))
|
|
#define HW_IPU_IDMAC_BNDM_EN_2_RD(x) (HW_IPU_IDMAC_BNDM_EN_2(x).U)
|
|
#define HW_IPU_IDMAC_BNDM_EN_2_WR(x, v) (HW_IPU_IDMAC_BNDM_EN_2(x).U = (v))
|
|
#define HW_IPU_IDMAC_BNDM_EN_2_SET(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, HW_IPU_IDMAC_BNDM_EN_2_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_BNDM_EN_2_CLR(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_BNDM_EN_2_TOG(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, HW_IPU_IDMAC_BNDM_EN_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_BNDM_EN_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_2, field IDMAC_BNDM_EN_45[13] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45 (13) //!< Bit position for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45.
|
|
#define BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45 (0x00002000) //!< Bit mask for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45) >> BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45.
|
|
#define BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_45 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, (HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45) | BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_45(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_2, field IDMAC_BNDM_EN_46[14] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46 (14) //!< Bit position for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46.
|
|
#define BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46 (0x00004000) //!< Bit mask for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46.
|
|
|
|
//! @brief Get value of IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46) >> BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46.
|
|
#define BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_46 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, (HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46) | BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_46(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_2, field IDMAC_BNDM_EN_47[15] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47 (15) //!< Bit position for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47.
|
|
#define BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47 (0x00008000) //!< Bit mask for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47.
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|
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//! @brief Get value of IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47) >> BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47)
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//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47.
|
|
#define BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_47 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, (HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47) | BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_47(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_2, field IDMAC_BNDM_EN_48[16] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48 (16) //!< Bit position for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48.
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|
#define BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48 (0x00010000) //!< Bit mask for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48.
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//! @brief Get value of IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48 from a register value.
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|
#define BG_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48) >> BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48)
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//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48.
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|
#define BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_48 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, (HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48) | BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_48(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_IDMAC_BNDM_EN_2, field IDMAC_BNDM_EN_49[17] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
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|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49 (17) //!< Bit position for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49.
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|
#define BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49 (0x00020000) //!< Bit mask for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49.
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|
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//! @brief Get value of IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49 from a register value.
|
|
#define BG_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49) >> BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49)
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|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49.
|
|
#define BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_49 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, (HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49) | BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_49(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_BNDM_EN_2, field IDMAC_BNDM_EN_50[18] (RW)
|
|
*
|
|
* IDMAC Band Mode Enable bit [i] This bit controls if the channel currently works in band mode.
|
|
* When alternate flow is running via this channel, both the main flow and the alternate flow should
|
|
* have the same band mode configuration.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not in band mode
|
|
* - 1 - IDMAC channel [i] is in band mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50 (18) //!< Bit position for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50.
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|
#define BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50 (0x00040000) //!< Bit mask for IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50.
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|
//! @brief Get value of IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50 from a register value.
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|
#define BG_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50) >> BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50)
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|
|
//! @brief Format value for bitfield IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50.
|
|
#define BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50) & BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_BNDM_EN_50 field to a new value.
|
|
#define BW_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50(x, v) (HW_IPU_IDMAC_BNDM_EN_2_WR(x, (HW_IPU_IDMAC_BNDM_EN_2_RD(x) & ~BM_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50) | BF_IPU_IDMAC_BNDM_EN_2_IDMAC_BNDM_EN_50(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SC_CORD - IDMAC Scroll Coordinations Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SC_CORD - IDMAC Scroll Coordinations Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sc_cord
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sc_cord_bitfields
|
|
{
|
|
unsigned SY0 : 11; //!< [10:0] Scroll Y coordination
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|
unsigned RESERVED0 : 5; //!< [15:11] Reserved, should be cleared.
|
|
unsigned SX0 : 12; //!< [27:16] Scroll X coordination
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_idmac_sc_cord_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SC_CORD register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SC_CORD_ADDR(x) (REGS_IPU_BASE(x) + 0x1f70)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SC_CORD(x) (*(volatile hw_ipu_idmac_sc_cord_t *) HW_IPU_IDMAC_SC_CORD_ADDR(x))
|
|
#define HW_IPU_IDMAC_SC_CORD_RD(x) (HW_IPU_IDMAC_SC_CORD(x).U)
|
|
#define HW_IPU_IDMAC_SC_CORD_WR(x, v) (HW_IPU_IDMAC_SC_CORD(x).U = (v))
|
|
#define HW_IPU_IDMAC_SC_CORD_SET(x, v) (HW_IPU_IDMAC_SC_CORD_WR(x, HW_IPU_IDMAC_SC_CORD_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SC_CORD_CLR(x, v) (HW_IPU_IDMAC_SC_CORD_WR(x, HW_IPU_IDMAC_SC_CORD_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SC_CORD_TOG(x, v) (HW_IPU_IDMAC_SC_CORD_WR(x, HW_IPU_IDMAC_SC_CORD_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SC_CORD bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SC_CORD, field SY0[10:0] (RW)
|
|
*
|
|
* Scroll Y coordination This field indicates the Y coordinate of the scroll. This parameter has an
|
|
* affect on continuos scroll mode only. Units are pixels. When the alpha buffer resides in a
|
|
* separate buffer and the alpha is different than 8 BPP this field should be 0.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SC_CORD_SY0 (0) //!< Bit position for IPU_IDMAC_SC_CORD_SY0.
|
|
#define BM_IPU_IDMAC_SC_CORD_SY0 (0x000007ff) //!< Bit mask for IPU_IDMAC_SC_CORD_SY0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SC_CORD_SY0 from a register value.
|
|
#define BG_IPU_IDMAC_SC_CORD_SY0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SC_CORD_SY0) >> BP_IPU_IDMAC_SC_CORD_SY0)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SC_CORD_SY0.
|
|
#define BF_IPU_IDMAC_SC_CORD_SY0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SC_CORD_SY0) & BM_IPU_IDMAC_SC_CORD_SY0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SY0 field to a new value.
|
|
#define BW_IPU_IDMAC_SC_CORD_SY0(x, v) (HW_IPU_IDMAC_SC_CORD_WR(x, (HW_IPU_IDMAC_SC_CORD_RD(x) & ~BM_IPU_IDMAC_SC_CORD_SY0) | BF_IPU_IDMAC_SC_CORD_SY0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SC_CORD, field SX0[27:16] (RW)
|
|
*
|
|
* Scroll X coordination This field indicates the X coordinate of the scroll. This parameter has an
|
|
* affect on continuos scroll mode only. Units are pixels. When the alpha buffer resides in a
|
|
* separate buffer and the alpha is different than 8 BPP this field should be 0.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SC_CORD_SX0 (16) //!< Bit position for IPU_IDMAC_SC_CORD_SX0.
|
|
#define BM_IPU_IDMAC_SC_CORD_SX0 (0x0fff0000) //!< Bit mask for IPU_IDMAC_SC_CORD_SX0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SC_CORD_SX0 from a register value.
|
|
#define BG_IPU_IDMAC_SC_CORD_SX0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SC_CORD_SX0) >> BP_IPU_IDMAC_SC_CORD_SX0)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SC_CORD_SX0.
|
|
#define BF_IPU_IDMAC_SC_CORD_SX0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SC_CORD_SX0) & BM_IPU_IDMAC_SC_CORD_SX0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SX0 field to a new value.
|
|
#define BW_IPU_IDMAC_SC_CORD_SX0(x, v) (HW_IPU_IDMAC_SC_CORD_WR(x, (HW_IPU_IDMAC_SC_CORD_RD(x) & ~BM_IPU_IDMAC_SC_CORD_SX0) | BF_IPU_IDMAC_SC_CORD_SX0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CH_BUSY_1 - IDMAC Channel Busy 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CH_BUSY_1 - IDMAC Channel Busy 1 Register (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_ch_busy_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_ch_busy_1_bitfields
|
|
{
|
|
unsigned IDMAC_CH_BUSY_0 : 1; //!< [0] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_1 : 1; //!< [1] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_2 : 1; //!< [2] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_3 : 1; //!< [3] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved.
|
|
unsigned IDMAC_CH_BUSY_5 : 1; //!< [5] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED1 : 2; //!< [7:6] Reserved.
|
|
unsigned IDMAC_CH_BUSY_8 : 1; //!< [8] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_9 : 1; //!< [9] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_10 : 1; //!< [10] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_11 : 1; //!< [11] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_12 : 1; //!< [12] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_13 : 1; //!< [13] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_14 : 1; //!< [14] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_15 : 1; //!< [15] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved.
|
|
unsigned IDMAC_CH_BUSY_17 : 1; //!< [17] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_18 : 1; //!< [18] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED3 : 1; //!< [19] Reserved.
|
|
unsigned IDMAC_CH_BUSY_20 : 1; //!< [20] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_21 : 1; //!< [21] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_22 : 1; //!< [22] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_23 : 1; //!< [23] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_24 : 1; //!< [24] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_25 : 1; //!< [25] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_26 : 1; //!< [26] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_27 : 1; //!< [27] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_28 : 1; //!< [28] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_29 : 1; //!< [29] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED4 : 1; //!< [30] Reserved.
|
|
unsigned IDMAC_CH_BUSY : 1; //!< [31] IDMAC Channel busy bit [i]
|
|
} B;
|
|
} hw_ipu_idmac_ch_busy_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CH_BUSY_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CH_BUSY_1_ADDR(x) (REGS_IPU_BASE(x) + 0x1fa4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CH_BUSY_1(x) (*(volatile hw_ipu_idmac_ch_busy_1_t *) HW_IPU_IDMAC_CH_BUSY_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_CH_BUSY_1_RD(x) (HW_IPU_IDMAC_CH_BUSY_1(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CH_BUSY_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_0[0] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0 (0) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0 (0x00000001) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_1[1] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1 (1) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1 (0x00000002) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_2[2] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2 (2) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2 (0x00000004) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_2)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_3[3] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3 (3) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3 (0x00000008) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_3)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_5[5] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5 (5) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5 (0x00000020) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_5)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_8[8] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8 (8) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8 (0x00000100) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_8)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_9[9] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9 (9) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9 (0x00000200) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_9)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_10[10] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10 (10) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10 (0x00000400) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_10)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_11[11] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11 (11) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11 (0x00000800) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_11)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_12[12] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12 (12) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12 (0x00001000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_12)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_13[13] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13 (13) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13 (0x00002000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_13)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_14[14] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14 (14) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14 (0x00004000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_14)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_15[15] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15 (15) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15 (0x00008000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_15)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_17[17] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17 (17) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17 (0x00020000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_17)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_18[18] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18 (18) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18 (0x00040000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_18)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_20[20] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20 (20) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20 (0x00100000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_20)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_21[21] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21 (21) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21 (0x00200000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_21)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_22[22] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22 (22) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22 (0x00400000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_22)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_23[23] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23 (23) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23 (0x00800000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_23)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_24[24] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24 (24) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24 (0x01000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_24)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_25[25] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25 (25) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25 (0x02000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_25)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_26[26] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26 (26) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26 (0x04000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_26)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_27[27] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27 (27) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27 (0x08000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_27)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_28[28] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28 (28) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28 (0x10000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_28)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY_29[29] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29 (29) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29 (0x20000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY_29)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_1, field IDMAC_CH_BUSY[31] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY (31) //!< Bit position for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY.
|
|
#define BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY (0x80000000) //!< Bit mask for IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY) >> BP_IPU_IDMAC_CH_BUSY_1_IDMAC_CH_BUSY)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_CH_BUSY_2 - IDMAC Channel Busy 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_CH_BUSY_2 - IDMAC Channel Busy 2 Register (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_ch_busy_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_ch_busy_2_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved.
|
|
unsigned IDMAC_CH_BUSY_33 : 1; //!< [1] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED1 : 6; //!< [7:2] Reserved.
|
|
unsigned IDMAC_CH_BUSY_40 : 1; //!< [8] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_41 : 1; //!< [9] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_42 : 1; //!< [10] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_43 : 1; //!< [11] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_44 : 1; //!< [12] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_45 : 1; //!< [13] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_46 : 1; //!< [14] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_47 : 1; //!< [15] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_48 : 1; //!< [16] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_49 : 1; //!< [17] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_50 : 1; //!< [18] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_51 : 1; //!< [19] IDMAC Channel busy bit [i]
|
|
unsigned IDMAC_CH_BUSY_52 : 1; //!< [20] IDMAC Channel busy bit [i]
|
|
unsigned RESERVED2 : 11; //!< [31:21] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_ch_busy_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_CH_BUSY_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_CH_BUSY_2_ADDR(x) (REGS_IPU_BASE(x) + 0x1fa8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_CH_BUSY_2(x) (*(volatile hw_ipu_idmac_ch_busy_2_t *) HW_IPU_IDMAC_CH_BUSY_2_ADDR(x))
|
|
#define HW_IPU_IDMAC_CH_BUSY_2_RD(x) (HW_IPU_IDMAC_CH_BUSY_2(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_CH_BUSY_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_33[1] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33 (1) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33 (0x00000002) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_33)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_40[8] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40 (8) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40 (0x00000100) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_40)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_41[9] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41 (9) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41 (0x00000200) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_41)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_42[10] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42 (10) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42 (0x00000400) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_42)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_43[11] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43 (11) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43 (0x00000800) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_43)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_44[12] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44 (12) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44 (0x00001000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_44)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_45[13] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45 (13) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45 (0x00002000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_45)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_46[14] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46 (14) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46 (0x00004000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_46)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_47[15] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47 (15) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47 (0x00008000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_47)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_48[16] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48 (16) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48 (0x00010000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_48)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_49[17] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49 (17) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49 (0x00020000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_49)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_50[18] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50 (18) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50 (0x00040000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_50)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_51[19] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51 (19) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51 (0x00080000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_51)
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_CH_BUSY_2, field IDMAC_CH_BUSY_52[20] (RO)
|
|
*
|
|
* IDMAC Channel busy bit [i] This bit indicates if the channel is currently served by the IDMAC.
|
|
* This bit is self cleared by the IDMAC.
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] is not busy
|
|
* - 1 - IDMAC channel [i] is busy
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52 (20) //!< Bit position for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52.
|
|
#define BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52 (0x00100000) //!< Bit mask for IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52.
|
|
|
|
//! @brief Get value of IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52 from a register value.
|
|
#define BG_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52) >> BP_IPU_IDMAC_CH_BUSY_2_IDMAC_CH_BUSY_52)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SEP_ALPHA - IDMAC Separate Alpha Indication Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SEP_ALPHA - IDMAC Separate Alpha Indication Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sep_alpha
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sep_alpha_bitfields
|
|
{
|
|
unsigned RESERVED0 : 14; //!< [13:0] Reserved.
|
|
unsigned IDMAC_SEP_AL_14 : 1; //!< [14] IDMAC Separate alpha indication bit [i]
|
|
unsigned IDMAC_SEP_AL_15 : 1; //!< [15] IDMAC Separate alpha indication bit [i]
|
|
unsigned RESERVED1 : 7; //!< [22:16] Reserved.
|
|
unsigned IDMAC_SEP_AL_23 : 1; //!< [23] IDMAC Separate alpha indication bit [i]
|
|
unsigned IDMAC_SEP_AL_24 : 1; //!< [24] IDMAC Separate alpha indication bit [i]
|
|
unsigned IDMAC_SEP_AL_25 : 1; //!< [25] IDMAC Separate alpha indication bit [i]
|
|
unsigned RESERVED2 : 1; //!< [26] Reserved.
|
|
unsigned IDMAC_SEP_AL_27 : 1; //!< [27] IDMAC Separate alpha indication bit [i]
|
|
unsigned RESERVED3 : 1; //!< [28] Reserved.
|
|
unsigned IDMAC_SEP_AL_29 : 1; //!< [29] IDMAC Separate alpha indication bit [i]
|
|
unsigned RESERVED4 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_sep_alpha_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SEP_ALPHA register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SEP_ALPHA_ADDR(x) (REGS_IPU_BASE(x) + 0x800c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SEP_ALPHA(x) (*(volatile hw_ipu_idmac_sep_alpha_t *) HW_IPU_IDMAC_SEP_ALPHA_ADDR(x))
|
|
#define HW_IPU_IDMAC_SEP_ALPHA_RD(x) (HW_IPU_IDMAC_SEP_ALPHA(x).U)
|
|
#define HW_IPU_IDMAC_SEP_ALPHA_WR(x, v) (HW_IPU_IDMAC_SEP_ALPHA(x).U = (v))
|
|
#define HW_IPU_IDMAC_SEP_ALPHA_SET(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, HW_IPU_IDMAC_SEP_ALPHA_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SEP_ALPHA_CLR(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SEP_ALPHA_TOG(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, HW_IPU_IDMAC_SEP_ALPHA_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SEP_ALPHA bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_14[14] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14 (14) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14.
|
|
#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14 (0x00004000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14 from a register value.
|
|
#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14.
|
|
#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SEP_AL_14 field to a new value.
|
|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_15[15] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15 (15) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15.
|
|
#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15 (0x00008000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15 from a register value.
|
|
#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15.
|
|
#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SEP_AL_15 field to a new value.
|
|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_23[23] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23 (23) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23.
|
|
#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23 (0x00800000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23 from a register value.
|
|
#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23.
|
|
#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SEP_AL_23 field to a new value.
|
|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_24[24] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24 (24) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24.
|
|
#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24 (0x01000000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24 from a register value.
|
|
#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24.
|
|
#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SEP_AL_24 field to a new value.
|
|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_25[25] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
|
|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25 (25) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25.
|
|
#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25 (0x02000000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25 from a register value.
|
|
#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25)
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//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25.
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|
#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_SEP_AL_25 field to a new value.
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|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_25(v)))
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#endif
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|
//@}
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|
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/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_27[27] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
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|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
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* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
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|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27 (27) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27.
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#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27 (0x08000000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27.
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//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27 from a register value.
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#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27)
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//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27.
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#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the IDMAC_SEP_AL_27 field to a new value.
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|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_27(v)))
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#endif
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|
//@}
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/*! @name Register IPU_IDMAC_SEP_ALPHA, field IDMAC_SEP_AL_29[29] (RW)
|
|
*
|
|
* IDMAC Separate alpha indication bit [i] A sub block may need to read data from the system's
|
|
* memory where the pixel data and the alpha transparency data are located in separate buffers. In
|
|
* that case the Alpha transparency data is read by the special Alpha channel. In a case where the
|
|
* alpha should be read from a separate buffer, the user should set the channels corresponding.
|
|
*
|
|
* Values:
|
|
* - 0 - Channel [i] does not read Alpha transparency data from a separate buffer.
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|
* - 1 - Channel [i] reads Alpha transparency data from a separate buffer.
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|
*/
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|
//@{
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|
#define BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29 (29) //!< Bit position for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29.
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|
#define BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29 (0x20000000) //!< Bit mask for IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29.
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|
|
//! @brief Get value of IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29 from a register value.
|
|
#define BG_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29) >> BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29)
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|
|
//! @brief Format value for bitfield IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29.
|
|
#define BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29) & BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SEP_AL_29 field to a new value.
|
|
#define BW_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29(x, v) (HW_IPU_IDMAC_SEP_ALPHA_WR(x, (HW_IPU_IDMAC_SEP_ALPHA_RD(x) & ~BM_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29) | BF_IPU_IDMAC_SEP_ALPHA_IDMAC_SEP_AL_29(v)))
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|
#endif
|
|
//@}
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|
|
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//-------------------------------------------------------------------------------------------
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// HW_IPU_IDMAC_WM_EN_1 - IDMAC Channel Watermark Enable 1 Register
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|
//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_WM_EN_1 - IDMAC Channel Watermark Enable 1 Register (RW)
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|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_wm_en_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_wm_en_1_bitfields
|
|
{
|
|
unsigned IDMAC_WM_EN_0 : 1; //!< [0] IDMAC Watermark enable bit [i]
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|
unsigned IDMAC_WM_EN_1 : 1; //!< [1] IDMAC Watermark enable bit [i]
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|
unsigned IDMAC_WM_EN_2 : 1; //!< [2] IDMAC Watermark enable bit [i]
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|
unsigned IDMAC_WM_EN_3 : 1; //!< [3] IDMAC Watermark enable bit [i]
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|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
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|
unsigned IDMAC_WM_EN_8 : 1; //!< [8] IDMAC Watermark enable bit [i]
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|
unsigned RESERVED1 : 1; //!< [9] Reserved.
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|
unsigned IDMAC_WM_EN_10 : 1; //!< [10] IDMAC Watermark enable bit [i]
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|
unsigned RESERVED2 : 1; //!< [11] Reserved.
|
|
unsigned IDMAC_WM_EN_12 : 1; //!< [12] IDMAC Watermark enable bit [i]
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|
unsigned IDMAC_WM_EN_13 : 1; //!< [13] IDMAC Watermark enable bit [i]
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|
unsigned IDMAC_WM_EN_14 : 1; //!< [14] IDMAC Watermark enable bit [i]
|
|
unsigned RESERVED3 : 8; //!< [22:15] Reserved.
|
|
unsigned IDMAC_WM_EN_23 : 1; //!< [23] IDMAC Watermark enable bit [i]
|
|
unsigned IDMAC_WM_EN_24 : 1; //!< [24] IDMAC Watermark enable bit [i]
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|
unsigned IDMAC_WM_EN_25 : 1; //!< [25] IDMAC Watermark enable bit [i]
|
|
unsigned IDMAC_WM_EN_26 : 1; //!< [26] IDMAC Watermark enable bit [i]
|
|
unsigned IDMAC_WM_EN_27 : 1; //!< [27] IDMAC Watermark enable bit [i]
|
|
unsigned IDMAC_WM_EN_28 : 1; //!< [28] IDMAC Watermark enable bit [i]
|
|
unsigned IDMAC_WM_EN_29 : 1; //!< [29] IDMAC Watermark enable bit [i]
|
|
unsigned RESERVED4 : 2; //!< [31:30] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_wm_en_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_WM_EN_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_WM_EN_1_ADDR(x) (REGS_IPU_BASE(x) + 0x801c)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_WM_EN_1(x) (*(volatile hw_ipu_idmac_wm_en_1_t *) HW_IPU_IDMAC_WM_EN_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_WM_EN_1_RD(x) (HW_IPU_IDMAC_WM_EN_1(x).U)
|
|
#define HW_IPU_IDMAC_WM_EN_1_WR(x, v) (HW_IPU_IDMAC_WM_EN_1(x).U = (v))
|
|
#define HW_IPU_IDMAC_WM_EN_1_SET(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, HW_IPU_IDMAC_WM_EN_1_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_WM_EN_1_CLR(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, HW_IPU_IDMAC_WM_EN_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_WM_EN_1_TOG(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, HW_IPU_IDMAC_WM_EN_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_WM_EN_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_0[0] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0 (0) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0 (0x00000001) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_0 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_1[1] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1 (1) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1 (0x00000002) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_1 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_2[2] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2 (2) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2 (0x00000004) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_2 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_3[3] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3 (3) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3 (0x00000008) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_3 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_8[8] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8 (8) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8 (0x00000100) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_8 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_10[10] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10 (10) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10 (0x00000400) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_10 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_12[12] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12 (12) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12 (0x00001000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_12 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_13[13] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13 (13) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13 (0x00002000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_13 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_14[14] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14 (14) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14 (0x00004000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_14 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_23[23] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23 (23) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23 (0x00800000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_23 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_24[24] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24 (24) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24 (0x01000000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_24 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_24(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_25[25] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25 (25) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25 (0x02000000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_25 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_25(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_26[26] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26 (26) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26 (0x04000000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_26 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_27[27] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27 (27) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27 (0x08000000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_27 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_28[28] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28 (28) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28 (0x10000000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_28 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_WM_EN_1, field IDMAC_WM_EN_29[29] (RW)
|
|
*
|
|
* IDMAC Watermark enable bit [i]
|
|
*
|
|
* Values:
|
|
* - 0 - IDMAC channel [i] watermark feature is disabled
|
|
* - 1 - IDMAC channel [i] watermark feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29 (29) //!< Bit position for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29.
|
|
#define BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29 (0x20000000) //!< Bit mask for IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29.
|
|
|
|
//! @brief Get value of IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29 from a register value.
|
|
#define BG_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29) >> BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29.
|
|
#define BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29) & BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_WM_EN_29 field to a new value.
|
|
#define BW_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29(x, v) (HW_IPU_IDMAC_WM_EN_1_WR(x, (HW_IPU_IDMAC_WM_EN_1_RD(x) & ~BM_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29) | BF_IPU_IDMAC_WM_EN_1_IDMAC_WM_EN_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SUB_ADDR_0 - IDMAC Channel Alternate Address 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SUB_ADDR_0 - IDMAC Channel Alternate Address 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sub_addr_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sub_addr_0_bitfields
|
|
{
|
|
unsigned IDMAC_SUB_ADDR_I : 32; //!< [31:0] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
} B;
|
|
} hw_ipu_idmac_sub_addr_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SUB_ADDR_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0_ADDR(x) (REGS_IPU_BASE(x) + 0x802c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0(x) (*(volatile hw_ipu_idmac_sub_addr_0_t *) HW_IPU_IDMAC_SUB_ADDR_0_ADDR(x))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0_RD(x) (HW_IPU_IDMAC_SUB_ADDR_0(x).U)
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0_WR(x, v) (HW_IPU_IDMAC_SUB_ADDR_0(x).U = (v))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0_SET(x, v) (HW_IPU_IDMAC_SUB_ADDR_0_WR(x, HW_IPU_IDMAC_SUB_ADDR_0_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0_CLR(x, v) (HW_IPU_IDMAC_SUB_ADDR_0_WR(x, HW_IPU_IDMAC_SUB_ADDR_0_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_0_TOG(x, v) (HW_IPU_IDMAC_SUB_ADDR_0_WR(x, HW_IPU_IDMAC_SUB_ADDR_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SUB_ADDR_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_0, field IDMAC_SUB_ADDR_I[31:0] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I (0) //!< Bit position for IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I (0xffffffff) //!< Bit mask for IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I) >> BP_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I) & BM_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_I field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I(x, v) (HW_IPU_IDMAC_SUB_ADDR_0_WR(x, (HW_IPU_IDMAC_SUB_ADDR_0_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I) | BF_IPU_IDMAC_SUB_ADDR_0_IDMAC_SUB_ADDR_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SUB_ADDR_4 - IDMAC Channel Alternate Address 4 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SUB_ADDR_4 - IDMAC Channel Alternate Address 4 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sub_addr_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sub_addr_4_bitfields
|
|
{
|
|
unsigned IDMAC_SUB_ADDR_28 : 7; //!< [6:0] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_8 : 7; //!< [14:8] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED1 : 1; //!< [15] Reserved.
|
|
unsigned IDMAC_SUB_ADDR_21 : 7; //!< [22:16] The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in IDMAC_SUB_ADDR_i.
|
|
unsigned RESERVED2 : 9; //!< [31:23] Reserved.
|
|
} B;
|
|
} hw_ipu_idmac_sub_addr_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SUB_ADDR_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4_ADDR(x) (REGS_IPU_BASE(x) + 0x803c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4(x) (*(volatile hw_ipu_idmac_sub_addr_4_t *) HW_IPU_IDMAC_SUB_ADDR_4_ADDR(x))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4_RD(x) (HW_IPU_IDMAC_SUB_ADDR_4(x).U)
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4_WR(x, v) (HW_IPU_IDMAC_SUB_ADDR_4(x).U = (v))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4_SET(x, v) (HW_IPU_IDMAC_SUB_ADDR_4_WR(x, HW_IPU_IDMAC_SUB_ADDR_4_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4_CLR(x, v) (HW_IPU_IDMAC_SUB_ADDR_4_WR(x, HW_IPU_IDMAC_SUB_ADDR_4_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SUB_ADDR_4_TOG(x, v) (HW_IPU_IDMAC_SUB_ADDR_4_WR(x, HW_IPU_IDMAC_SUB_ADDR_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SUB_ADDR_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_4, field IDMAC_SUB_ADDR_28[6:0] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28 (0) //!< Bit position for IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28 (0x0000007f) //!< Bit mask for IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28) >> BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28) & BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_28 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28(x, v) (HW_IPU_IDMAC_SUB_ADDR_4_WR(x, (HW_IPU_IDMAC_SUB_ADDR_4_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28) | BF_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_4, field IDMAC_SUB_ADDR_8[14:8] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8 (8) //!< Bit position for IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8 (0x00007f00) //!< Bit mask for IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8) >> BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8) & BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_8 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8(x, v) (HW_IPU_IDMAC_SUB_ADDR_4_WR(x, (HW_IPU_IDMAC_SUB_ADDR_4_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8) | BF_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SUB_ADDR_4, field IDMAC_SUB_ADDR_21[22:16] (RW)
|
|
*
|
|
* The CPMEM alternative entry [i] holds the parameters of the channel that is number appears in
|
|
* IDMAC_SUB_ADDR_i. The user must set each IDMAC_SUB_ADDR_i field to a unique channel. Alternative
|
|
* CPMEM entry is relevant only for channels supporting alternate flows.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21 (16) //!< Bit position for IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21.
|
|
#define BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21 (0x007f0000) //!< Bit mask for IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21 from a register value.
|
|
#define BG_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21) >> BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21.
|
|
#define BF_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21) & BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IDMAC_SUB_ADDR_21 field to a new value.
|
|
#define BW_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21(x, v) (HW_IPU_IDMAC_SUB_ADDR_4_WR(x, (HW_IPU_IDMAC_SUB_ADDR_4_RD(x) & ~BM_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21) | BF_IPU_IDMAC_SUB_ADDR_4_IDMAC_SUB_ADDR_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IDMAC_SC_CORD_1 - IDMAC Scroll Coordinations Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IDMAC_SC_CORD_1 - IDMAC Scroll Coordinations Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_idmac_sc_cord_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_idmac_sc_cord_1_bitfields
|
|
{
|
|
unsigned SY1 : 11; //!< [10:0] Scroll Y coordination (2nd set)
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved, should be cleared.
|
|
unsigned SX1 : 12; //!< [27:16] Scroll X coordination (2nd set)
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_idmac_sc_cord_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IDMAC_SC_CORD_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IDMAC_SC_CORD_1_ADDR(x) (REGS_IPU_BASE(x) + 0x804c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IDMAC_SC_CORD_1(x) (*(volatile hw_ipu_idmac_sc_cord_1_t *) HW_IPU_IDMAC_SC_CORD_1_ADDR(x))
|
|
#define HW_IPU_IDMAC_SC_CORD_1_RD(x) (HW_IPU_IDMAC_SC_CORD_1(x).U)
|
|
#define HW_IPU_IDMAC_SC_CORD_1_WR(x, v) (HW_IPU_IDMAC_SC_CORD_1(x).U = (v))
|
|
#define HW_IPU_IDMAC_SC_CORD_1_SET(x, v) (HW_IPU_IDMAC_SC_CORD_1_WR(x, HW_IPU_IDMAC_SC_CORD_1_RD(x) | (v)))
|
|
#define HW_IPU_IDMAC_SC_CORD_1_CLR(x, v) (HW_IPU_IDMAC_SC_CORD_1_WR(x, HW_IPU_IDMAC_SC_CORD_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IDMAC_SC_CORD_1_TOG(x, v) (HW_IPU_IDMAC_SC_CORD_1_WR(x, HW_IPU_IDMAC_SC_CORD_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IDMAC_SC_CORD_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IDMAC_SC_CORD_1, field SY1[10:0] (RW)
|
|
*
|
|
* Scroll Y coordination (2nd set) This field indicates the Y coordinate of the scroll. This
|
|
* parameter has an affect on continuos scroll mode only. Units are pixels. When the alpha buffer
|
|
* resides in a separate buffer and the alpha is different than 8 BPP this field should be 0.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SC_CORD_1_SY1 (0) //!< Bit position for IPU_IDMAC_SC_CORD_1_SY1.
|
|
#define BM_IPU_IDMAC_SC_CORD_1_SY1 (0x000007ff) //!< Bit mask for IPU_IDMAC_SC_CORD_1_SY1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SC_CORD_1_SY1 from a register value.
|
|
#define BG_IPU_IDMAC_SC_CORD_1_SY1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SC_CORD_1_SY1) >> BP_IPU_IDMAC_SC_CORD_1_SY1)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SC_CORD_1_SY1.
|
|
#define BF_IPU_IDMAC_SC_CORD_1_SY1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SC_CORD_1_SY1) & BM_IPU_IDMAC_SC_CORD_1_SY1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SY1 field to a new value.
|
|
#define BW_IPU_IDMAC_SC_CORD_1_SY1(x, v) (HW_IPU_IDMAC_SC_CORD_1_WR(x, (HW_IPU_IDMAC_SC_CORD_1_RD(x) & ~BM_IPU_IDMAC_SC_CORD_1_SY1) | BF_IPU_IDMAC_SC_CORD_1_SY1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IDMAC_SC_CORD_1, field SX1[27:16] (RW)
|
|
*
|
|
* Scroll X coordination (2nd set) This field indicates the X coordinate of the scroll. This
|
|
* parameter has an affect on continuos scroll mode only. Units are pixels. When the alpha buffer
|
|
* resides in a separate buffer and the alpha is different than 8 BPP this field should be 0.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IDMAC_SC_CORD_1_SX1 (16) //!< Bit position for IPU_IDMAC_SC_CORD_1_SX1.
|
|
#define BM_IPU_IDMAC_SC_CORD_1_SX1 (0x0fff0000) //!< Bit mask for IPU_IDMAC_SC_CORD_1_SX1.
|
|
|
|
//! @brief Get value of IPU_IDMAC_SC_CORD_1_SX1 from a register value.
|
|
#define BG_IPU_IDMAC_SC_CORD_1_SX1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IDMAC_SC_CORD_1_SX1) >> BP_IPU_IDMAC_SC_CORD_1_SX1)
|
|
|
|
//! @brief Format value for bitfield IPU_IDMAC_SC_CORD_1_SX1.
|
|
#define BF_IPU_IDMAC_SC_CORD_1_SX1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IDMAC_SC_CORD_1_SX1) & BM_IPU_IDMAC_SC_CORD_1_SX1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SX1 field to a new value.
|
|
#define BW_IPU_IDMAC_SC_CORD_1_SX1(x, v) (HW_IPU_IDMAC_SC_CORD_1_WR(x, (HW_IPU_IDMAC_SC_CORD_1_RD(x) & ~BM_IPU_IDMAC_SC_CORD_1_SX1) | BF_IPU_IDMAC_SC_CORD_1_SX1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_COM_CONF_SYNC - DP Common Configuration Sync Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_COM_CONF_SYNC - DP Common Configuration Sync Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains common configuration parameters for the DP.
|
|
*/
|
|
typedef union _hw_ipu_dp_com_conf_sync
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_com_conf_sync_bitfields
|
|
{
|
|
unsigned DP_FG_EN_SYNC : 1; //!< [0] FG_EN - partial plane Enable.
|
|
unsigned DP_GWSEL_SYNC : 1; //!< [1] GWSEL - Graphic Window Select
|
|
unsigned DP_GWAM_SYNC : 1; //!< [2] GWAM - Graphic Window Alpha Mode
|
|
unsigned DP_GWCKE_SYNC : 1; //!< [3] GWCKE - Graphic Window Color Keying Enable
|
|
unsigned DP_COC_SYNC : 3; //!< [6:4] COC - Cursor Operation Control
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved
|
|
unsigned DP_CSC_DEF_SYNC : 2; //!< [9:8] CSC_DEF
|
|
unsigned DP_CSC_GAMUT_SAT_EN_SYNC : 1; //!< [10] CSC_GAMUT_SAT_EN
|
|
unsigned DP_CSC_YUV_SAT_MODE_SYNC : 1; //!< [11] CSC_YUV_SAT_MODE
|
|
unsigned DP_GAMMA_EN_SYNC : 1; //!< [12] GAMMA_EN - Gamma correction block enable bit
|
|
unsigned DP_GAMMA_YUV_EN_SYNC : 1; //!< [13] GAMMA's YUV mode enable for sync flow
|
|
unsigned RESERVED1 : 18; //!< [31:14] Reserved
|
|
} B;
|
|
} hw_ipu_dp_com_conf_sync_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_COM_CONF_SYNC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_COM_CONF_SYNC_ADDR(x) (REGS_IPU_BASE(x) + 0x18000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_COM_CONF_SYNC(x) (*(volatile hw_ipu_dp_com_conf_sync_t *) HW_IPU_DP_COM_CONF_SYNC_ADDR(x))
|
|
#define HW_IPU_DP_COM_CONF_SYNC_RD(x) (HW_IPU_DP_COM_CONF_SYNC(x).U)
|
|
#define HW_IPU_DP_COM_CONF_SYNC_WR(x, v) (HW_IPU_DP_COM_CONF_SYNC(x).U = (v))
|
|
#define HW_IPU_DP_COM_CONF_SYNC_SET(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, HW_IPU_DP_COM_CONF_SYNC_RD(x) | (v)))
|
|
#define HW_IPU_DP_COM_CONF_SYNC_CLR(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~(v)))
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|
#define HW_IPU_DP_COM_CONF_SYNC_TOG(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, HW_IPU_DP_COM_CONF_SYNC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_COM_CONF_SYNC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_FG_EN_SYNC[0] (RW)
|
|
*
|
|
* FG_EN - partial plane Enable. This bit enables the partial plane channel.
|
|
*
|
|
* Values:
|
|
* - 0 - partial plane channel is disabled.
|
|
* - 1 - partial plane channel is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC (0) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC.
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|
#define BM_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC (0x00000001) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC.
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|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC)
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|
|
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//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FG_EN_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_FG_EN_SYNC(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_GWSEL_SYNC[1] (RW)
|
|
*
|
|
* GWSEL - Graphic Window Select Select graphic window to be on partial plane or full plane.
|
|
*
|
|
* Values:
|
|
* - 0 - Graphic window is full plane.
|
|
* - 1 - Graphic window is partial plane.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC (1) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC.
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|
#define BM_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC (0x00000002) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC.
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|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC)
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|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWSEL_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_GWSEL_SYNC(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_GWAM_SYNC[2] (RW)
|
|
*
|
|
* GWAM - Graphic Window Alpha Mode Select the use of Alpha to be global or local.
|
|
*
|
|
* Values:
|
|
* - 0 - Local Alpha.
|
|
* - 1 - Global Alpha.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC (2) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC (0x00000004) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWAM_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_GWAM_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_GWCKE_SYNC[3] (RW)
|
|
*
|
|
* GWCKE - Graphic Window Color Keying Enable Enable or disable graphic window color keying.
|
|
*
|
|
* Values:
|
|
* - 0 - Disable color keying of graphic window
|
|
* - 1 - Enable color keying of graphic window
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC (3) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC (0x00000008) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKE_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_GWCKE_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_COC_SYNC[6:4] (RW)
|
|
*
|
|
* COC - Cursor Operation Control Controls the format of the cursor and the type of arithmetic
|
|
* operations
|
|
*
|
|
* Values:
|
|
* - 000 - Transparent, cursor is disabled.
|
|
* - 001 - Full cursor.
|
|
* - 010 - Reversed cursor.
|
|
* - 011 - AND between full plane and cursor.
|
|
* - 100 - Reserved
|
|
* - 101 - OR between full plane and cursor.
|
|
* - 110 - XOR between full plane and cursor.
|
|
* - 111 - Reserved.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC (4) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_COC_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC (0x00000070) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_COC_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_COC_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_COC_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_COC_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_COC_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_CSC_DEF_SYNC[9:8] (RW)
|
|
*
|
|
* CSC_DEF Enable or disable Color Space Conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - CSC disable
|
|
* - 01 - CSC enable after combining
|
|
* - 10 - CSC enable before combining on BG channel
|
|
* - 11 - CSC enable before combining on FG channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC (8) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC (0x00000300) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_DEF_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_CSC_DEF_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_CSC_GAMUT_SAT_EN_SYNC[10] (RW)
|
|
*
|
|
* CSC_GAMUT_SAT_EN Indicate if GAMUT saturation is enabled
|
|
*
|
|
* Values:
|
|
* - 0 - disable GAMUT mapping
|
|
* - 1 - enable GAMUT mapping
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC (10) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC (0x00000400) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_GAMUT_SAT_EN_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_CSC_GAMUT_SAT_EN_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_CSC_YUV_SAT_MODE_SYNC[11] (RW)
|
|
*
|
|
* CSC_YUV_SAT_MODE YUV saturation mode for color space conversion
|
|
*
|
|
* Values:
|
|
* - 0 - Y/U/V range 0 -255
|
|
* - 1 - Y range 16-235, U/V range 16-240
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC (11) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC (0x00000800) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_YUV_SAT_MODE_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_CSC_YUV_SAT_MODE_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_GAMMA_EN_SYNC[12] (RW)
|
|
*
|
|
* GAMMA_EN - Gamma correction block enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - disable
|
|
* - 1 - enable
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC (12) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC (0x00001000) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_EN_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_GAMMA_EN_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_SYNC, field DP_GAMMA_YUV_EN_SYNC[13] (RW)
|
|
*
|
|
* GAMMA's YUV mode enable for sync flow
|
|
*
|
|
* Values:
|
|
* - 0 - YUV mode is OFF.
|
|
* - 1 - YUV mode is ON.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC (13) //!< Bit position for IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC.
|
|
#define BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC (0x00002000) //!< Bit mask for IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC from a register value.
|
|
#define BG_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC) >> BP_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC.
|
|
#define BF_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC) & BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_YUV_EN_SYNC field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC(x, v) (HW_IPU_DP_COM_CONF_SYNC_WR(x, (HW_IPU_DP_COM_CONF_SYNC_RD(x) & ~BM_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC) | BF_IPU_DP_COM_CONF_SYNC_DP_GAMMA_YUV_EN_SYNC(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_GRAPH_WIND_CTRL_SYNC - DP Graphic Window Control Sync Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_GRAPH_WIND_CTRL_SYNC - DP Graphic Window Control Sync Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains common configuration parameters for the DP.
|
|
*/
|
|
typedef union _hw_ipu_dp_graph_wind_ctrl_sync
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_graph_wind_ctrl_sync_bitfields
|
|
{
|
|
unsigned DP_GWCKB_SYNC : 8; //!< [7:0] GWCKB - Graphic Window Color Keying Blue Component
|
|
unsigned DP_GWCKG_SYNC : 8; //!< [15:8] GWCKG - Graphic Window Color Keying Green Component
|
|
unsigned DP_GWCKR_SYNC : 8; //!< [23:16] GWCKR - Graphic Window Color Keying Red Component
|
|
unsigned DP_GWAV_SYNC : 8; //!< [31:24] GWAV - Graphic Window Alpha Value
|
|
} B;
|
|
} hw_ipu_dp_graph_wind_ctrl_sync_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GRAPH_WIND_CTRL_SYNC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_ADDR(x) (REGS_IPU_BASE(x) + 0x18004)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC(x) (*(volatile hw_ipu_dp_graph_wind_ctrl_sync_t *) HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_ADDR(x))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC(x).U)
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC(x).U = (v))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_SET(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) | (v)))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_CLR(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) & ~(v)))
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|
#define HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_TOG(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DP_GRAPH_WIND_CTRL_SYNC bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_SYNC, field DP_GWCKB_SYNC[7:0] (RW)
|
|
*
|
|
* GWCKB - Graphic Window Color Keying Blue Component Defines the blue component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No blue
|
|
* - 11111111 - Full blue
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC (0) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC (0x000000ff) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC.
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|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC) >> BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC)
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|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKB_SYNC field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC) | BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKB_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_SYNC, field DP_GWCKG_SYNC[15:8] (RW)
|
|
*
|
|
* GWCKG - Graphic Window Color Keying Green Component Defines the green component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Green
|
|
* - 11111111 - Full Green
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC (8) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC (0x0000ff00) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC) >> BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKG_SYNC field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC) | BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKG_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_SYNC, field DP_GWCKR_SYNC[23:16] (RW)
|
|
*
|
|
* GWCKR - Graphic Window Color Keying Red Component Defines the red component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No red
|
|
* - 11111111 - Full red
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC (16) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC (0x00ff0000) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC) >> BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKR_SYNC field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC) | BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWCKR_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_SYNC, field DP_GWAV_SYNC[31:24] (RW)
|
|
*
|
|
* GWAV - Graphic Window Alpha Value Defines the alpha value of graphic window used for alpha
|
|
* blending between graphic window and full plane. The Value the number that writing to GWAV
|
|
* register. The Actual Value the number, that insert to calculation in Combining Module. If Value =
|
|
* < 0.5- 1/256 (01111111) then Actual Value = Value. If Value >= 0.5 (10000000), then Actual Value
|
|
* = Value + 1/256.
|
|
*
|
|
* Values:
|
|
* - 00000000 - Actual value is 00000000; Graphic window totally opaque i.e. overlay on LCD screen
|
|
* - 01111111 - Actual value is 01111111;
|
|
* - 10000000 - Actual value is 10000001
|
|
* - 10000001 - Actual value is 10000010
|
|
* - 11111110 - Actual value is 11111111
|
|
* - 11111111 - Actual value is 100000000;Graphic window totally transparent i.e. not displayed on LCD screen
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC (24) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC (0xff000000) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC) >> BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC) & BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWAV_SYNC field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_SYNC_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC) | BF_IPU_DP_GRAPH_WIND_CTRL_SYNC_DP_GWAV_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_FG_POS_SYNC - DP Partial Plane Window Position Sync Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_FG_POS_SYNC - DP Partial Plane Window Position Sync Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The DP partial plane Window Position Register is used to determine the starting position of the
|
|
* partial plane window relative to BG window position. This Register is used for the synchronous
|
|
* flow only.
|
|
*/
|
|
typedef union _hw_ipu_dp_fg_pos_sync
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_fg_pos_sync_bitfields
|
|
{
|
|
unsigned DP_FGYP_SYNC : 11; //!< [10:0] FGYP partial plane window Y position
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned DP_FGXP_SYNC : 11; //!< [26:16] FGXP partial plane Window X Position.
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved
|
|
} B;
|
|
} hw_ipu_dp_fg_pos_sync_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_FG_POS_SYNC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_FG_POS_SYNC_ADDR(x) (REGS_IPU_BASE(x) + 0x18008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_FG_POS_SYNC(x) (*(volatile hw_ipu_dp_fg_pos_sync_t *) HW_IPU_DP_FG_POS_SYNC_ADDR(x))
|
|
#define HW_IPU_DP_FG_POS_SYNC_RD(x) (HW_IPU_DP_FG_POS_SYNC(x).U)
|
|
#define HW_IPU_DP_FG_POS_SYNC_WR(x, v) (HW_IPU_DP_FG_POS_SYNC(x).U = (v))
|
|
#define HW_IPU_DP_FG_POS_SYNC_SET(x, v) (HW_IPU_DP_FG_POS_SYNC_WR(x, HW_IPU_DP_FG_POS_SYNC_RD(x) | (v)))
|
|
#define HW_IPU_DP_FG_POS_SYNC_CLR(x, v) (HW_IPU_DP_FG_POS_SYNC_WR(x, HW_IPU_DP_FG_POS_SYNC_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_FG_POS_SYNC_TOG(x, v) (HW_IPU_DP_FG_POS_SYNC_WR(x, HW_IPU_DP_FG_POS_SYNC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_FG_POS_SYNC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_FG_POS_SYNC, field DP_FGYP_SYNC[10:0] (RW)
|
|
*
|
|
* FGYP partial plane window Y position partial plane Window Y Position - Specifies the number of
|
|
* lines between the start of full plane windows Y position and the beginning of the first data.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC (0) //!< Bit position for IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC.
|
|
#define BM_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC (0x000007ff) //!< Bit mask for IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC from a register value.
|
|
#define BG_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC) >> BP_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC.
|
|
#define BF_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC) & BM_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FGYP_SYNC field to a new value.
|
|
#define BW_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC(x, v) (HW_IPU_DP_FG_POS_SYNC_WR(x, (HW_IPU_DP_FG_POS_SYNC_RD(x) & ~BM_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC) | BF_IPU_DP_FG_POS_SYNC_DP_FGYP_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_FG_POS_SYNC, field DP_FGXP_SYNC[26:16] (RW)
|
|
*
|
|
* FGXP partial plane Window X Position. partial plane Window X Position - Specifies the number of
|
|
* pixels between the start of full plane window X position and the beginning of the first data of
|
|
* new line.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC (16) //!< Bit position for IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC.
|
|
#define BM_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC (0x07ff0000) //!< Bit mask for IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC from a register value.
|
|
#define BG_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC) >> BP_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC.
|
|
#define BF_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC) & BM_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FGXP_SYNC field to a new value.
|
|
#define BW_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC(x, v) (HW_IPU_DP_FG_POS_SYNC_WR(x, (HW_IPU_DP_FG_POS_SYNC_RD(x) & ~BM_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC) | BF_IPU_DP_FG_POS_SYNC_DP_FGXP_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CUR_POS_SYNC - DP Cursor Position and Size Sync Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CUR_POS_SYNC - DP Cursor Position and Size Sync Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The LCD Cursor Position Register is used to determine the starting position of the cursor
|
|
* relative to BG windows position.
|
|
*/
|
|
typedef union _hw_ipu_dp_cur_pos_sync
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_cur_pos_sync_bitfields
|
|
{
|
|
unsigned DP_CXW_SYNC : 11; //!< [10:0] CXW - Cursor Width.
|
|
unsigned DP_CXP_SYNC : 5; //!< [15:11] CXP - Cursor X Position
|
|
unsigned DP_CYH_SYNC : 11; //!< [26:16] CYH - Cursor Height
|
|
unsigned DP_CYP_SYNC : 5; //!< [31:27] CYP - Cursor Y Position
|
|
} B;
|
|
} hw_ipu_dp_cur_pos_sync_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CUR_POS_SYNC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CUR_POS_SYNC_ADDR(x) (REGS_IPU_BASE(x) + 0x1800c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CUR_POS_SYNC(x) (*(volatile hw_ipu_dp_cur_pos_sync_t *) HW_IPU_DP_CUR_POS_SYNC_ADDR(x))
|
|
#define HW_IPU_DP_CUR_POS_SYNC_RD(x) (HW_IPU_DP_CUR_POS_SYNC(x).U)
|
|
#define HW_IPU_DP_CUR_POS_SYNC_WR(x, v) (HW_IPU_DP_CUR_POS_SYNC(x).U = (v))
|
|
#define HW_IPU_DP_CUR_POS_SYNC_SET(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, HW_IPU_DP_CUR_POS_SYNC_RD(x) | (v)))
|
|
#define HW_IPU_DP_CUR_POS_SYNC_CLR(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, HW_IPU_DP_CUR_POS_SYNC_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CUR_POS_SYNC_TOG(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, HW_IPU_DP_CUR_POS_SYNC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CUR_POS_SYNC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_SYNC, field DP_CXW_SYNC[10:0] (RW)
|
|
*
|
|
* CXW - Cursor Width. Specifies the width of the hardware cursor in pixels.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC (0) //!< Bit position for IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC.
|
|
#define BM_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC (0x000007ff) //!< Bit mask for IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC) >> BP_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC.
|
|
#define BF_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC) & BM_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CXW_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, (HW_IPU_DP_CUR_POS_SYNC_RD(x) & ~BM_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC) | BF_IPU_DP_CUR_POS_SYNC_DP_CXW_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_SYNC, field DP_CXP_SYNC[15:11] (RW)
|
|
*
|
|
* CXP - Cursor X Position Represents the cursors horizontal starting position X in pixel count
|
|
* (from 0 to CXW).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC (11) //!< Bit position for IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC.
|
|
#define BM_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC (0x0000f800) //!< Bit mask for IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC) >> BP_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC.
|
|
#define BF_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC) & BM_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CXP_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, (HW_IPU_DP_CUR_POS_SYNC_RD(x) & ~BM_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC) | BF_IPU_DP_CUR_POS_SYNC_DP_CXP_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_SYNC, field DP_CYH_SYNC[26:16] (RW)
|
|
*
|
|
* CYH - Cursor Height Specifies the height of the hardware cursor in pixels.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC (16) //!< Bit position for IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC.
|
|
#define BM_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC (0x07ff0000) //!< Bit mask for IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC) >> BP_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC.
|
|
#define BF_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC) & BM_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CYH_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, (HW_IPU_DP_CUR_POS_SYNC_RD(x) & ~BM_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC) | BF_IPU_DP_CUR_POS_SYNC_DP_CYH_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_SYNC, field DP_CYP_SYNC[31:27] (RW)
|
|
*
|
|
* CYP - Cursor Y Position Represents the cursors vertical starting position Y in pixel count (from
|
|
* 0 to CYH).Live View Resolution Mode.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC (27) //!< Bit position for IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC.
|
|
#define BM_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC (0xf8000000) //!< Bit mask for IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC) >> BP_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC.
|
|
#define BF_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC) & BM_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CYP_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC(x, v) (HW_IPU_DP_CUR_POS_SYNC_WR(x, (HW_IPU_DP_CUR_POS_SYNC_RD(x) & ~BM_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC) | BF_IPU_DP_CUR_POS_SYNC_DP_CYP_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CUR_MAP_SYNC - DP Color Cursor Mapping Sync Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CUR_MAP_SYNC - DP Color Cursor Mapping Sync Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The LCD Color Cursor Mapping Register defines the color of the cursor in passive or TFT color
|
|
* modes.
|
|
*/
|
|
typedef union _hw_ipu_dp_cur_map_sync
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_cur_map_sync_bitfields
|
|
{
|
|
unsigned DP_CUR_COL_R_SYNC : 8; //!< [7:0] CUR_COL_B - Cursor Red Field
|
|
unsigned DP_CUR_COL_G_SYNC : 8; //!< [15:8] CUR_COL_G - Cursor Green Field
|
|
unsigned DP_CUR_COL_B_SYNC : 8; //!< [23:16] CUR_COL_B - Cursor Blue Field
|
|
unsigned RESERVED0 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_dp_cur_map_sync_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CUR_MAP_SYNC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CUR_MAP_SYNC_ADDR(x) (REGS_IPU_BASE(x) + 0x18010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CUR_MAP_SYNC(x) (*(volatile hw_ipu_dp_cur_map_sync_t *) HW_IPU_DP_CUR_MAP_SYNC_ADDR(x))
|
|
#define HW_IPU_DP_CUR_MAP_SYNC_RD(x) (HW_IPU_DP_CUR_MAP_SYNC(x).U)
|
|
#define HW_IPU_DP_CUR_MAP_SYNC_WR(x, v) (HW_IPU_DP_CUR_MAP_SYNC(x).U = (v))
|
|
#define HW_IPU_DP_CUR_MAP_SYNC_SET(x, v) (HW_IPU_DP_CUR_MAP_SYNC_WR(x, HW_IPU_DP_CUR_MAP_SYNC_RD(x) | (v)))
|
|
#define HW_IPU_DP_CUR_MAP_SYNC_CLR(x, v) (HW_IPU_DP_CUR_MAP_SYNC_WR(x, HW_IPU_DP_CUR_MAP_SYNC_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CUR_MAP_SYNC_TOG(x, v) (HW_IPU_DP_CUR_MAP_SYNC_WR(x, HW_IPU_DP_CUR_MAP_SYNC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CUR_MAP_SYNC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CUR_MAP_SYNC, field DP_CUR_COL_R_SYNC[7:0] (RW)
|
|
*
|
|
* CUR_COL_B - Cursor Red Field Defines the Red component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Red.
|
|
* - 11111111 - Full Red.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC (0) //!< Bit position for IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC.
|
|
#define BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC (0x000000ff) //!< Bit mask for IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC) >> BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC.
|
|
#define BF_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC) & BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_R_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC(x, v) (HW_IPU_DP_CUR_MAP_SYNC_WR(x, (HW_IPU_DP_CUR_MAP_SYNC_RD(x) & ~BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC) | BF_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_R_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_MAP_SYNC, field DP_CUR_COL_G_SYNC[15:8] (RW)
|
|
*
|
|
* CUR_COL_G - Cursor Green Field Defines the Green component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Green.
|
|
* - 11111111 - Full Green.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC (8) //!< Bit position for IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC.
|
|
#define BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC (0x0000ff00) //!< Bit mask for IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC) >> BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC.
|
|
#define BF_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC) & BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_G_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC(x, v) (HW_IPU_DP_CUR_MAP_SYNC_WR(x, (HW_IPU_DP_CUR_MAP_SYNC_RD(x) & ~BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC) | BF_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_G_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_MAP_SYNC, field DP_CUR_COL_B_SYNC[23:16] (RW)
|
|
*
|
|
* CUR_COL_B - Cursor Blue Field Defines the Blue component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Blue.
|
|
* - 11111111 - Full Blue.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC (16) //!< Bit position for IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC.
|
|
#define BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC (0x00ff0000) //!< Bit mask for IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC from a register value.
|
|
#define BG_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC) >> BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC.
|
|
#define BF_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC) & BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_B_SYNC field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC(x, v) (HW_IPU_DP_CUR_MAP_SYNC_WR(x, (HW_IPU_DP_CUR_MAP_SYNC_RD(x) & ~BM_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC) | BF_IPU_DP_CUR_MAP_SYNC_DP_CUR_COL_B_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_GAMMA_C_SYNC_I - DP Gamma Constants Sync Flow Register i
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_GAMMA_C_SYNC_I - DP Gamma Constants Sync Flow Register i (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This registers contains CONSTANTi parameters used for gamma correction inside the display
|
|
* processor (DP).
|
|
*/
|
|
typedef union _hw_ipu_dp_gamma_c_sync_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_gamma_c_sync_i_bitfields
|
|
{
|
|
unsigned DP_GAMMA_C_SYNC_2I : 9; //!< [8:0] CONSTANTi parameter of Gamma Correction.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DP_GAMMA_C_SYNC_2I_1 : 9; //!< [24:16] CONSTANTi+1 parameter of Gamma Correction.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_dp_gamma_c_sync_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GAMMA_C_SYNC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x18014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I(x) (*(volatile hw_ipu_dp_gamma_c_sync_i_t *) HW_IPU_DP_GAMMA_C_SYNC_I_ADDR(x))
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I_RD(x) (HW_IPU_DP_GAMMA_C_SYNC_I(x).U)
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I_WR(x, v) (HW_IPU_DP_GAMMA_C_SYNC_I(x).U = (v))
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I_SET(x, v) (HW_IPU_DP_GAMMA_C_SYNC_I_WR(x, HW_IPU_DP_GAMMA_C_SYNC_I_RD(x) | (v)))
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I_CLR(x, v) (HW_IPU_DP_GAMMA_C_SYNC_I_WR(x, HW_IPU_DP_GAMMA_C_SYNC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_GAMMA_C_SYNC_I_TOG(x, v) (HW_IPU_DP_GAMMA_C_SYNC_I_WR(x, HW_IPU_DP_GAMMA_C_SYNC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_GAMMA_C_SYNC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_GAMMA_C_SYNC_I, field DP_GAMMA_C_SYNC_2I[8:0] (RW)
|
|
*
|
|
* CONSTANTi parameter of Gamma Correction.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I (0) //!< Bit position for IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I.
|
|
#define BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I (0x000001ff) //!< Bit mask for IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I.
|
|
|
|
//! @brief Get value of IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I from a register value.
|
|
#define BG_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I) >> BP_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I.
|
|
#define BF_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I) & BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_C_SYNC_2I field to a new value.
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#define BW_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I(x, v) (HW_IPU_DP_GAMMA_C_SYNC_I_WR(x, (HW_IPU_DP_GAMMA_C_SYNC_I_RD(x) & ~BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I) | BF_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_C_SYNC_I, field DP_GAMMA_C_SYNC_2I_1[24:16] (RW)
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*
|
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* CONSTANTi+1 parameter of Gamma Correction.
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*/
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//@{
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#define BP_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1 (16) //!< Bit position for IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1.
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#define BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1 (0x01ff0000) //!< Bit mask for IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1.
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//! @brief Get value of IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1 from a register value.
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#define BG_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1) >> BP_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1)
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//! @brief Format value for bitfield IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1.
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#define BF_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1) & BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_C_SYNC_2I_1 field to a new value.
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#define BW_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1(x, v) (HW_IPU_DP_GAMMA_C_SYNC_I_WR(x, (HW_IPU_DP_GAMMA_C_SYNC_I_RD(x) & ~BM_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1) | BF_IPU_DP_GAMMA_C_SYNC_I_DP_GAMMA_C_SYNC_2I_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_GAMMA_S_SYNC_I - DP Gamma Correction Slope Sync Flow Register i
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
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* @brief HW_IPU_DP_GAMMA_S_SYNC_I - DP Gamma Correction Slope Sync Flow Register i (RW)
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*
|
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* Reset value: 0x00000000
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*
|
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* This registers contains SLOPEi parameters used for Gamma Correction inside the display processor
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* (DP).
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*/
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typedef union _hw_ipu_dp_gamma_s_sync_i
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{
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reg32_t U;
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struct _hw_ipu_dp_gamma_s_sync_i_bitfields
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{
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unsigned DP_GAMMA_S_SYNC_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Gamma Correction.
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unsigned DP_GAMMA_S_SYNC_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Gamma Correction.
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unsigned DP_GAMMA_S_SYNC_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Gamma Correction.
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unsigned DP_GAMMA_S_SYNC_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Gamma Correction.
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} B;
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} hw_ipu_dp_gamma_s_sync_i_t;
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#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DP_GAMMA_S_SYNC_I register
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*/
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//@{
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#define HW_IPU_DP_GAMMA_S_SYNC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x18034)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DP_GAMMA_S_SYNC_I(x) (*(volatile hw_ipu_dp_gamma_s_sync_i_t *) HW_IPU_DP_GAMMA_S_SYNC_I_ADDR(x))
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#define HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) (HW_IPU_DP_GAMMA_S_SYNC_I(x).U)
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#define HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I(x).U = (v))
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#define HW_IPU_DP_GAMMA_S_SYNC_I_SET(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) | (v)))
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#define HW_IPU_DP_GAMMA_S_SYNC_I_CLR(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) & ~(v)))
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#define HW_IPU_DP_GAMMA_S_SYNC_I_TOG(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
|
|
* constants & macros for individual IPU_DP_GAMMA_S_SYNC_I bitfields
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*/
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/*! @name Register IPU_DP_GAMMA_S_SYNC_I, field DP_GAMMA_S_SYNC_4I[7:0] (RW)
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*
|
|
* SLOPE<4*i> parameter of Gamma Correction.
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*/
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//@{
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|
#define BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I (0) //!< Bit position for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I.
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#define BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I (0x000000ff) //!< Bit mask for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I.
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//! @brief Get value of IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I from a register value.
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#define BG_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I) >> BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I.
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#define BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I)
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|
|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DP_GAMMA_S_SYNC_4I field to a new value.
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|
#define BW_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, (HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) & ~BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I) | BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I(v)))
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|
#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_S_SYNC_I, field DP_GAMMA_S_SYNC_4I_1[15:8] (RW)
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|
*
|
|
* SLOPE<4*i+1> parameter of Gamma Correction.
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|
*/
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|
//@{
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|
#define BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1 (8) //!< Bit position for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1.
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#define BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1 (0x0000ff00) //!< Bit mask for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1.
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//! @brief Get value of IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1 from a register value.
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#define BG_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1) >> BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1.
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#define BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DP_GAMMA_S_SYNC_4I_1 field to a new value.
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|
#define BW_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, (HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) & ~BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1) | BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_1(v)))
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|
#endif
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|
//@}
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|
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|
/*! @name Register IPU_DP_GAMMA_S_SYNC_I, field DP_GAMMA_S_SYNC_4I_2[23:16] (RW)
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|
*
|
|
* SLOPE<4*i+2> parameter of Gamma Correction.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2 (16) //!< Bit position for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2.
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|
#define BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2 (0x00ff0000) //!< Bit mask for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2.
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//! @brief Get value of IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2 from a register value.
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#define BG_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2) >> BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2)
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|
|
//! @brief Format value for bitfield IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2.
|
|
#define BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_S_SYNC_4I_2 field to a new value.
|
|
#define BW_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, (HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) & ~BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2) | BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_2(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_DP_GAMMA_S_SYNC_I, field DP_GAMMA_S_SYNC_4I_3[31:24] (RW)
|
|
*
|
|
* SLOPE<4*i+3> parameter of Gamma Correction.
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|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3 (24) //!< Bit position for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3.
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|
#define BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3 (0xff000000) //!< Bit mask for IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3.
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|
//! @brief Get value of IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3 from a register value.
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|
#define BG_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3) >> BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3)
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|
|
//! @brief Format value for bitfield IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3.
|
|
#define BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3) & BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_S_SYNC_4I_3 field to a new value.
|
|
#define BW_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3(x, v) (HW_IPU_DP_GAMMA_S_SYNC_I_WR(x, (HW_IPU_DP_GAMMA_S_SYNC_I_RD(x) & ~BM_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3) | BF_IPU_DP_GAMMA_S_SYNC_I_DP_GAMMA_S_SYNC_4I_3(v)))
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|
#endif
|
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//@}
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|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CSCA_SYNC_I - DP Color Space Conversion Control Sync Flow Registers
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CSCA_SYNC_I - DP Color Space Conversion Control Sync Flow Registers (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_csca_sync_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_csca_sync_i_bitfields
|
|
{
|
|
unsigned DP_CSC_A_SYNC_2I : 10; //!< [9:0] A<2*i> parameter of color conversion.
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved.
|
|
unsigned DP_CSC_A_SYNC_2I_1 : 10; //!< [25:16] A<2*i+1> parameter of color conversion
|
|
unsigned RESERVED1 : 6; //!< [31:26] Reserved.
|
|
} B;
|
|
} hw_ipu_dp_csca_sync_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CSCA_SYNC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CSCA_SYNC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x18044)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CSCA_SYNC_I(x) (*(volatile hw_ipu_dp_csca_sync_i_t *) HW_IPU_DP_CSCA_SYNC_I_ADDR(x))
|
|
#define HW_IPU_DP_CSCA_SYNC_I_RD(x) (HW_IPU_DP_CSCA_SYNC_I(x).U)
|
|
#define HW_IPU_DP_CSCA_SYNC_I_WR(x, v) (HW_IPU_DP_CSCA_SYNC_I(x).U = (v))
|
|
#define HW_IPU_DP_CSCA_SYNC_I_SET(x, v) (HW_IPU_DP_CSCA_SYNC_I_WR(x, HW_IPU_DP_CSCA_SYNC_I_RD(x) | (v)))
|
|
#define HW_IPU_DP_CSCA_SYNC_I_CLR(x, v) (HW_IPU_DP_CSCA_SYNC_I_WR(x, HW_IPU_DP_CSCA_SYNC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CSCA_SYNC_I_TOG(x, v) (HW_IPU_DP_CSCA_SYNC_I_WR(x, HW_IPU_DP_CSCA_SYNC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CSCA_SYNC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CSCA_SYNC_I, field DP_CSC_A_SYNC_2I[9:0] (RW)
|
|
*
|
|
* A<2*i> parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I (0) //!< Bit position for IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I.
|
|
#define BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I (0x000003ff) //!< Bit mask for IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I.
|
|
|
|
//! @brief Get value of IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I from a register value.
|
|
#define BG_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I) >> BP_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I.
|
|
#define BF_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I) & BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_A_SYNC_2I field to a new value.
|
|
#define BW_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I(x, v) (HW_IPU_DP_CSCA_SYNC_I_WR(x, (HW_IPU_DP_CSCA_SYNC_I_RD(x) & ~BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I) | BF_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSCA_SYNC_I, field DP_CSC_A_SYNC_2I_1[25:16] (RW)
|
|
*
|
|
* A<2*i+1> parameter of color conversion
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1 (16) //!< Bit position for IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1.
|
|
#define BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1 (0x03ff0000) //!< Bit mask for IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1.
|
|
|
|
//! @brief Get value of IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1 from a register value.
|
|
#define BG_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1) >> BP_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1)
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//! @brief Format value for bitfield IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1.
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|
#define BF_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1) & BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_A_SYNC_2I_1 field to a new value.
|
|
#define BW_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1(x, v) (HW_IPU_DP_CSCA_SYNC_I_WR(x, (HW_IPU_DP_CSCA_SYNC_I_RD(x) & ~BM_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1) | BF_IPU_DP_CSCA_SYNC_I_DP_CSC_A_SYNC_2I_1(v)))
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#endif
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|
//@}
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_SCS_SYNC_0 - DP Color Conversion Control Sync Flow Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_DP_SCS_SYNC_0 - DP Color Conversion Control Sync Flow Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
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|
typedef union _hw_ipu_dp_scs_sync_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_scs_sync_0_bitfields
|
|
{
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unsigned DP_CSC_A8_SYNC : 10; //!< [9:0] A9 parameter of color conversion.
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unsigned RESERVED0 : 6; //!< [15:10] Reserved.
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unsigned DP_CSC_B0_SYNC : 14; //!< [29:16] B0 parameter of color conversion.
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unsigned DP_CSC_S0_SYNC : 2; //!< [31:30] S0 parameter of color conversion.
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} B;
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|
} hw_ipu_dp_scs_sync_0_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DP_SCS_SYNC_0 register
|
|
*/
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|
//@{
|
|
#define HW_IPU_DP_SCS_SYNC_0_ADDR(x) (REGS_IPU_BASE(x) + 0x18054)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DP_SCS_SYNC_0(x) (*(volatile hw_ipu_dp_scs_sync_0_t *) HW_IPU_DP_SCS_SYNC_0_ADDR(x))
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#define HW_IPU_DP_SCS_SYNC_0_RD(x) (HW_IPU_DP_SCS_SYNC_0(x).U)
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#define HW_IPU_DP_SCS_SYNC_0_WR(x, v) (HW_IPU_DP_SCS_SYNC_0(x).U = (v))
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#define HW_IPU_DP_SCS_SYNC_0_SET(x, v) (HW_IPU_DP_SCS_SYNC_0_WR(x, HW_IPU_DP_SCS_SYNC_0_RD(x) | (v)))
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#define HW_IPU_DP_SCS_SYNC_0_CLR(x, v) (HW_IPU_DP_SCS_SYNC_0_WR(x, HW_IPU_DP_SCS_SYNC_0_RD(x) & ~(v)))
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#define HW_IPU_DP_SCS_SYNC_0_TOG(x, v) (HW_IPU_DP_SCS_SYNC_0_WR(x, HW_IPU_DP_SCS_SYNC_0_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DP_SCS_SYNC_0 bitfields
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|
*/
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/*! @name Register IPU_DP_SCS_SYNC_0, field DP_CSC_A8_SYNC[9:0] (RW)
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*
|
|
* A9 parameter of color conversion.
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|
*/
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//@{
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|
#define BP_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC (0) //!< Bit position for IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC.
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#define BM_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC (0x000003ff) //!< Bit mask for IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC.
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//! @brief Get value of IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC from a register value.
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#define BG_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC) >> BP_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC)
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//! @brief Format value for bitfield IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC.
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|
#define BF_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC) & BM_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_A8_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_0_WR(x, (HW_IPU_DP_SCS_SYNC_0_RD(x) & ~BM_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC) | BF_IPU_DP_SCS_SYNC_0_DP_CSC_A8_SYNC(v)))
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|
#endif
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|
//@}
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|
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/*! @name Register IPU_DP_SCS_SYNC_0, field DP_CSC_B0_SYNC[29:16] (RW)
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|
*
|
|
* B0 parameter of color conversion.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC (16) //!< Bit position for IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC.
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|
#define BM_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC (0x3fff0000) //!< Bit mask for IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC.
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|
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|
//! @brief Get value of IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC from a register value.
|
|
#define BG_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC) >> BP_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC)
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|
//! @brief Format value for bitfield IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC.
|
|
#define BF_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC) & BM_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B0_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_0_WR(x, (HW_IPU_DP_SCS_SYNC_0_RD(x) & ~BM_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC) | BF_IPU_DP_SCS_SYNC_0_DP_CSC_B0_SYNC(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_SCS_SYNC_0, field DP_CSC_S0_SYNC[31:30] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0
|
|
* - 11 - scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC (30) //!< Bit position for IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC.
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|
#define BM_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC (0xc0000000) //!< Bit mask for IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC.
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|
|
|
//! @brief Get value of IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC from a register value.
|
|
#define BG_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC) >> BP_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC)
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|
|
|
//! @brief Format value for bitfield IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC.
|
|
#define BF_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC) & BM_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S0_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_0_WR(x, (HW_IPU_DP_SCS_SYNC_0_RD(x) & ~BM_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC) | BF_IPU_DP_SCS_SYNC_0_DP_CSC_S0_SYNC(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_SCS_SYNC_1 - DP Color Conversion Control Sync Flow Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_SCS_SYNC_1 - DP Color Conversion Control Sync Flow Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_scs_sync_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_scs_sync_1_bitfields
|
|
{
|
|
unsigned DP_CSC_B1_SYNC : 14; //!< [13:0] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S1_SYNC : 2; //!< [15:14] S0 parameter of color conversion.
|
|
unsigned DP_CSC_B2_SYNC : 14; //!< [29:16] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S2_SYNC : 2; //!< [31:30] S0 parameter of color conversion.
|
|
} B;
|
|
} hw_ipu_dp_scs_sync_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_SCS_SYNC_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_SCS_SYNC_1_ADDR(x) (REGS_IPU_BASE(x) + 0x18058)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_SCS_SYNC_1(x) (*(volatile hw_ipu_dp_scs_sync_1_t *) HW_IPU_DP_SCS_SYNC_1_ADDR(x))
|
|
#define HW_IPU_DP_SCS_SYNC_1_RD(x) (HW_IPU_DP_SCS_SYNC_1(x).U)
|
|
#define HW_IPU_DP_SCS_SYNC_1_WR(x, v) (HW_IPU_DP_SCS_SYNC_1(x).U = (v))
|
|
#define HW_IPU_DP_SCS_SYNC_1_SET(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, HW_IPU_DP_SCS_SYNC_1_RD(x) | (v)))
|
|
#define HW_IPU_DP_SCS_SYNC_1_CLR(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, HW_IPU_DP_SCS_SYNC_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_SCS_SYNC_1_TOG(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, HW_IPU_DP_SCS_SYNC_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_SCS_SYNC_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_SCS_SYNC_1, field DP_CSC_B1_SYNC[13:0] (RW)
|
|
*
|
|
* B0 parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC (0) //!< Bit position for IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC.
|
|
#define BM_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC (0x00003fff) //!< Bit mask for IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC from a register value.
|
|
#define BG_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC) >> BP_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC.
|
|
#define BF_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B1_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, (HW_IPU_DP_SCS_SYNC_1_RD(x) & ~BM_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC) | BF_IPU_DP_SCS_SYNC_1_DP_CSC_B1_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_SCS_SYNC_1, field DP_CSC_S1_SYNC[15:14] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0 11 scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC (14) //!< Bit position for IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC.
|
|
#define BM_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC (0x0000c000) //!< Bit mask for IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC from a register value.
|
|
#define BG_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC) >> BP_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC.
|
|
#define BF_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S1_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, (HW_IPU_DP_SCS_SYNC_1_RD(x) & ~BM_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC) | BF_IPU_DP_SCS_SYNC_1_DP_CSC_S1_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_SCS_SYNC_1, field DP_CSC_B2_SYNC[29:16] (RW)
|
|
*
|
|
* B0 parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC (16) //!< Bit position for IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC.
|
|
#define BM_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC (0x3fff0000) //!< Bit mask for IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC from a register value.
|
|
#define BG_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC) >> BP_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC.
|
|
#define BF_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B2_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, (HW_IPU_DP_SCS_SYNC_1_RD(x) & ~BM_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC) | BF_IPU_DP_SCS_SYNC_1_DP_CSC_B2_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_SCS_SYNC_1, field DP_CSC_S2_SYNC[31:30] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0 11 scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC (30) //!< Bit position for IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC.
|
|
#define BM_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC (0xc0000000) //!< Bit mask for IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC.
|
|
|
|
//! @brief Get value of IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC from a register value.
|
|
#define BG_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC) >> BP_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC.
|
|
#define BF_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC) & BM_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S2_SYNC field to a new value.
|
|
#define BW_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC(x, v) (HW_IPU_DP_SCS_SYNC_1_WR(x, (HW_IPU_DP_SCS_SYNC_1_RD(x) & ~BM_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC) | BF_IPU_DP_SCS_SYNC_1_DP_CSC_S2_SYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CUR_POS_ALT - DP Cursor Position and Size Alternate Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CUR_POS_ALT - DP Cursor Position and Size Alternate Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The LCD Cursor Position Register is used to determine the starting position of the cursor
|
|
* relative to BG windows position for the alternative flow.
|
|
*/
|
|
typedef union _hw_ipu_dp_cur_pos_alt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_cur_pos_alt_bitfields
|
|
{
|
|
unsigned DP_CXW_SYNC_ALT : 11; //!< [10:0] CXW_ALT - Cursor Width.
|
|
unsigned DP_CXP_SYNC_ALT : 5; //!< [15:11] CXP_ALT - Cursor X Position
|
|
unsigned DP_CYH_SYNC_ALT : 11; //!< [26:16] CYH_ALT - Cursor Height
|
|
unsigned DP_CYP_SYNC_ALT : 5; //!< [31:27] CYP_ALT - Cursor Y Position
|
|
} B;
|
|
} hw_ipu_dp_cur_pos_alt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CUR_POS_ALT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CUR_POS_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x1805c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CUR_POS_ALT(x) (*(volatile hw_ipu_dp_cur_pos_alt_t *) HW_IPU_DP_CUR_POS_ALT_ADDR(x))
|
|
#define HW_IPU_DP_CUR_POS_ALT_RD(x) (HW_IPU_DP_CUR_POS_ALT(x).U)
|
|
#define HW_IPU_DP_CUR_POS_ALT_WR(x, v) (HW_IPU_DP_CUR_POS_ALT(x).U = (v))
|
|
#define HW_IPU_DP_CUR_POS_ALT_SET(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, HW_IPU_DP_CUR_POS_ALT_RD(x) | (v)))
|
|
#define HW_IPU_DP_CUR_POS_ALT_CLR(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, HW_IPU_DP_CUR_POS_ALT_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CUR_POS_ALT_TOG(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, HW_IPU_DP_CUR_POS_ALT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CUR_POS_ALT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_ALT, field DP_CXW_SYNC_ALT[10:0] (RW)
|
|
*
|
|
* CXW_ALT - Cursor Width. Specifies the width of the hardware cursor in pixels for the alternative
|
|
* flow.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT (0) //!< Bit position for IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT.
|
|
#define BM_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT (0x000007ff) //!< Bit mask for IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT from a register value.
|
|
#define BG_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT) >> BP_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT.
|
|
#define BF_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT) & BM_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CXW_SYNC_ALT field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, (HW_IPU_DP_CUR_POS_ALT_RD(x) & ~BM_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT) | BF_IPU_DP_CUR_POS_ALT_DP_CXW_SYNC_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_ALT, field DP_CXP_SYNC_ALT[15:11] (RW)
|
|
*
|
|
* CXP_ALT - Cursor X Position Represents the cursors horizontal starting position X in pixel count
|
|
* (from 0 to CXW) for the alternative flow.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT (11) //!< Bit position for IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT.
|
|
#define BM_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT (0x0000f800) //!< Bit mask for IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT from a register value.
|
|
#define BG_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT) >> BP_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT.
|
|
#define BF_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT) & BM_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CXP_SYNC_ALT field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, (HW_IPU_DP_CUR_POS_ALT_RD(x) & ~BM_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT) | BF_IPU_DP_CUR_POS_ALT_DP_CXP_SYNC_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_ALT, field DP_CYH_SYNC_ALT[26:16] (RW)
|
|
*
|
|
* CYH_ALT - Cursor Height Specifies the height of the hardware cursor in pixels.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT (16) //!< Bit position for IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT.
|
|
#define BM_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT (0x07ff0000) //!< Bit mask for IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT from a register value.
|
|
#define BG_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT) >> BP_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT.
|
|
#define BF_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT) & BM_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CYH_SYNC_ALT field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, (HW_IPU_DP_CUR_POS_ALT_RD(x) & ~BM_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT) | BF_IPU_DP_CUR_POS_ALT_DP_CYH_SYNC_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_ALT, field DP_CYP_SYNC_ALT[31:27] (RW)
|
|
*
|
|
* CYP_ALT - Cursor Y Position Represents the cursors vertical starting position Y in pixel count
|
|
* (from 0 to CYH).Live View Resolution Mode for the alternative flow.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT (27) //!< Bit position for IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT.
|
|
#define BM_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT (0xf8000000) //!< Bit mask for IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT from a register value.
|
|
#define BG_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT) >> BP_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT.
|
|
#define BF_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT) & BM_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CYP_SYNC_ALT field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT(x, v) (HW_IPU_DP_CUR_POS_ALT_WR(x, (HW_IPU_DP_CUR_POS_ALT_RD(x) & ~BM_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT) | BF_IPU_DP_CUR_POS_ALT_DP_CYP_SYNC_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_COM_CONF_ASYNC0 - DP Common Configuration Async 0 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_COM_CONF_ASYNC0 - DP Common Configuration Async 0 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains common configuration parameters for the DP.
|
|
*/
|
|
typedef union _hw_ipu_dp_com_conf_async0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_com_conf_async0_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved
|
|
unsigned DP_GWSEL_ASYNC0 : 1; //!< [1] GWSEL - Graphic Window Select
|
|
unsigned DP_GWAM_ASYNC0 : 1; //!< [2] GWAM - Graphic Window Alpha Mode
|
|
unsigned DP_GWCKE_ASYNC0 : 1; //!< [3] GWCKE - Graphic Window Color Keying Enable
|
|
unsigned DP_COC_ASYNC0 : 3; //!< [6:4] COC - Cursor Operation Control
|
|
unsigned RESERVED1 : 1; //!< [7] Reserved
|
|
unsigned DP_CSC_DEF_ASYNC0 : 2; //!< [9:8] CSC_DEF
|
|
unsigned DP_CSC_GAMUT_SAT_EN_ASYNC0 : 1; //!< [10] CSC_GAMUT_SAT_EN
|
|
unsigned DP_CSC_YUV_SAT_MODE_ASYNC0 : 1; //!< [11] CSC_YUV_SAT_MODE
|
|
unsigned DP_GAMMA_EN_ASYNC0 : 1; //!< [12] GAMMA_EN - Gamma correction block enable bit
|
|
unsigned DP_GAMMA_YUV_EN_ASYNC0 : 1; //!< [13] GAMMA's YUV mode enable for async flow 0
|
|
unsigned RESERVED2 : 18; //!< [31:14] Reserved
|
|
} B;
|
|
} hw_ipu_dp_com_conf_async0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_COM_CONF_ASYNC0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0_ADDR(x) (REGS_IPU_BASE(x) + 0x18060)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0(x) (*(volatile hw_ipu_dp_com_conf_async0_t *) HW_IPU_DP_COM_CONF_ASYNC0_ADDR(x))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0_RD(x) (HW_IPU_DP_COM_CONF_ASYNC0(x).U)
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0_WR(x, v) (HW_IPU_DP_COM_CONF_ASYNC0(x).U = (v))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0_SET(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, HW_IPU_DP_COM_CONF_ASYNC0_RD(x) | (v)))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0_CLR(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC0_TOG(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, HW_IPU_DP_COM_CONF_ASYNC0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_COM_CONF_ASYNC0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_GWSEL_ASYNC0[1] (RW)
|
|
*
|
|
* GWSEL - Graphic Window Select Select graphic window to be on partial plane or full plane.
|
|
*
|
|
* Values:
|
|
* - 0 - Graphic window is full plane.5
|
|
* - 1 - Graphic window is partial plane.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0 (1) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0 (0x00000002) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWSEL_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_GWSEL_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_GWAM_ASYNC0[2] (RW)
|
|
*
|
|
* GWAM - Graphic Window Alpha Mode Select the use of Alpha to be global or local.
|
|
*
|
|
* Values:
|
|
* - 0 - Local Alpha.
|
|
* - 1 - Global Alpha.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0 (2) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0 (0x00000004) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWAM_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_GWAM_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_GWCKE_ASYNC0[3] (RW)
|
|
*
|
|
* GWCKE - Graphic Window Color Keying Enable Enable or disable graphic window color keying.
|
|
*
|
|
* Values:
|
|
* - 0 - Disable color keying of graphic window
|
|
* - 1 - Enable color keying of graphic window
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0 (3) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0 (0x00000008) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKE_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_GWCKE_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_COC_ASYNC0[6:4] (RW)
|
|
*
|
|
* COC - Cursor Operation Control Controls the format of the cursor and the type of arithmetic
|
|
* operations
|
|
*
|
|
* Values:
|
|
* - 000 - Transparent, cursor is disabled.
|
|
* - 001 - Full cursor.
|
|
* - 010 - Reversed cursor.
|
|
* - 011 - AND between full plane and cursor.
|
|
* - 100 - Reserved
|
|
* - 101 - OR between full plane and cursor.
|
|
* - 110 - XOR between full plane and cursor.
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0 (4) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0 (0x00000070) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0.
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#define BF_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_COC_ASYNC0 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_COC_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_CSC_DEF_ASYNC0[9:8] (RW)
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*
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* CSC_DEF Enable or disable Color Space Conversion.
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*
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* Values:
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* - 00 - CSC disable
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* - 01 - CSC enable after combining
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* - 10 - CSC enable before combining on BG channel
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* - 11 - CSC enable before combining on FG channel
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*/
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//@{
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#define BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0 (8) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0.
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#define BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0 (0x00000300) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0.
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#define BF_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_DEF_ASYNC0 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_CSC_DEF_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_CSC_GAMUT_SAT_EN_ASYNC0[10] (RW)
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*
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* CSC_GAMUT_SAT_EN Indicate if GAMUT saturation is enabled
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*
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* Values:
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* - 0 - disable GAMUT mapping
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* - 1 - enable GAMUT mapping
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*/
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//@{
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#define BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0 (10) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0.
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#define BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0 (0x00000400) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0.
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#define BF_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_GAMUT_SAT_EN_ASYNC0 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_CSC_GAMUT_SAT_EN_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_CSC_YUV_SAT_MODE_ASYNC0[11] (RW)
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*
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* CSC_YUV_SAT_MODE YUV saturation mode for color space conversion
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*
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* Values:
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* - 0 - Y/U/V range 0 -255
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* - 1 - Y range 16-235, U/V range 16-240
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*/
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//@{
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#define BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0 (11) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0.
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#define BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0 (0x00000800) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0.
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#define BF_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_YUV_SAT_MODE_ASYNC0 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_CSC_YUV_SAT_MODE_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_GAMMA_EN_ASYNC0[12] (RW)
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|
*
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|
* GAMMA_EN - Gamma correction block enable bit
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|
*
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|
* Values:
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|
* - 0 - disable
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|
* - 1 - enable
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|
*/
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//@{
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|
#define BP_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0 (12) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0.
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#define BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0 (0x00001000) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0.
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#define BF_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_EN_ASYNC0 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_EN_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_COM_CONF_ASYNC0, field DP_GAMMA_YUV_EN_ASYNC0[13] (RW)
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|
*
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|
* GAMMA's YUV mode enable for async flow 0
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|
*
|
|
* Values:
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|
* - 0 - YUV mode is OFF.
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* - 1 - YUV mode is ON.
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*/
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//@{
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|
#define BP_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0 (13) //!< Bit position for IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0.
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#define BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0 (0x00002000) //!< Bit mask for IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0) >> BP_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0.
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#define BF_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0) & BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DP_GAMMA_YUV_EN_ASYNC0 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0(x, v) (HW_IPU_DP_COM_CONF_ASYNC0_WR(x, (HW_IPU_DP_COM_CONF_ASYNC0_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0) | BF_IPU_DP_COM_CONF_ASYNC0_DP_GAMMA_YUV_EN_ASYNC0(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0 - DP Graphic Window Control Async 0 Flow Register
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//-------------------------------------------------------------------------------------------
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|
#ifndef __LANGUAGE_ASM__
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|
/*!
|
|
* @brief HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0 - DP Graphic Window Control Async 0 Flow Register (RW)
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|
*
|
|
* Reset value: 0x00000000
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|
*
|
|
* This register contains common configuration parameters for the DP.
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|
*/
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|
typedef union _hw_ipu_dp_graph_wind_ctrl_async0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_graph_wind_ctrl_async0_bitfields
|
|
{
|
|
unsigned DP_GWCKB_ASYNC0 : 8; //!< [7:0] GWCKB - Graphic Window Color Keying Blue Component
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unsigned DP_GWCKG_ASYNC0 : 8; //!< [15:8] GWCKG - Graphic Window Color Keying Green Component
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unsigned DP_GWCKR_ASYNC0 : 8; //!< [23:16] GWCKR - Graphic Window Color Keying Red Component
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unsigned DP_GWAV_ASYNC0 : 8; //!< [31:24] GWAV - Graphic Window Alpha Value
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} B;
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|
} hw_ipu_dp_graph_wind_ctrl_async0_t;
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|
#endif
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|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GRAPH_WIND_CTRL_ASYNC0 register
|
|
*/
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//@{
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_ADDR(x) (REGS_IPU_BASE(x) + 0x18064)
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|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0(x) (*(volatile hw_ipu_dp_graph_wind_ctrl_async0_t *) HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_ADDR(x))
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#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0(x).U)
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#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0(x).U = (v))
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#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_SET(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) | (v)))
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#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_CLR(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) & ~(v)))
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#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_TOG(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) ^ (v)))
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#endif
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//@}
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|
|
/*
|
|
* constants & macros for individual IPU_DP_GRAPH_WIND_CTRL_ASYNC0 bitfields
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|
*/
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/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC0, field DP_GWCKB_ASYNC0[7:0] (RW)
|
|
*
|
|
* GWCKB - Graphic Window Color Keying Blue Component Defines the blue component of graphic window
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|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No blue
|
|
* - 11111111 - Full blue
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0 (0) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0.
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#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0 (0x000000ff) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0.
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|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0 from a register value.
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|
#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0)
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|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0.
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|
#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKB_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKB_ASYNC0(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC0, field DP_GWCKG_ASYNC0[15:8] (RW)
|
|
*
|
|
* GWCKG - Graphic Window Color Keying Green Component Defines the green component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Green
|
|
* - 11111111 - Full Green
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0 (8) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0.
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|
#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0 (0x0000ff00) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0.
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|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0)
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|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKG_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKG_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC0, field DP_GWCKR_ASYNC0[23:16] (RW)
|
|
*
|
|
* GWCKR - Graphic Window Color Keying Red Component Defines the red component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No red
|
|
* - 11111111 - Full red
|
|
*/
|
|
//@{
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#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0 (16) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0.
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#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0 (0x00ff0000) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0.
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//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0 from a register value.
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#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0.
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#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GWCKR_ASYNC0 field to a new value.
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#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWCKR_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC0, field DP_GWAV_ASYNC0[31:24] (RW)
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*
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* GWAV - Graphic Window Alpha Value Defines the alpha value of graphic window used for alpha
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* blending between graphic window and full plane. The Value the number that writing to GWAV
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* register. The Actual Value the number, that insert to calculation in Combining Module. If Value =
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* < 0.5- 1/256 (01111111) then Actual Value = Value. If Value >= 0.5 (10000000), then Actual Value
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* = Value + 1/256.
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*
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* Values:
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* - 00000000 - Actual value is 00000000; Graphic window totally opaque i.e. overlay on LCD screen
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* - 01111111 - Actual value is 01111111;
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* - 10000000 - Actual value is 10000001
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* - 10000001 - Actual value is 10000010
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* - 11111110 - Actual value is 11111111
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* - 11111111 - Actual value is 100000000;Graphic window totally transparent i.e. not displayed on LCD screen
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*/
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//@{
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#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0 (24) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0.
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#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0 (0xff000000) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0.
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//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0 from a register value.
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#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0.
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#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GWAV_ASYNC0 field to a new value.
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#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC0_DP_GWAV_ASYNC0(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_FG_POS_ASYNC0 - DP Partial Plane Window Position Async 0 Flow Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DP_FG_POS_ASYNC0 - DP Partial Plane Window Position Async 0 Flow Register (RW)
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*
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* Reset value: 0x00000000
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*
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* The DP partial plane Window Position Register is used to determine the starting position of the
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* partial plane window relative to BG window position. This Register is used for the synchronous
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* flow only.
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*/
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typedef union _hw_ipu_dp_fg_pos_async0
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{
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reg32_t U;
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struct _hw_ipu_dp_fg_pos_async0_bitfields
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{
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unsigned DP_FGYP_ASYNC0 : 11; //!< [10:0] FGYP partial plane window Y position
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unsigned RESERVED0 : 5; //!< [15:11] Reserved
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unsigned DP_FGXP_ASYNC0 : 11; //!< [26:16] FGXP partial plane Window X Position.
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unsigned RESERVED1 : 5; //!< [31:27] Reserved
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} B;
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} hw_ipu_dp_fg_pos_async0_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DP_FG_POS_ASYNC0 register
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*/
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//@{
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#define HW_IPU_DP_FG_POS_ASYNC0_ADDR(x) (REGS_IPU_BASE(x) + 0x18068)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DP_FG_POS_ASYNC0(x) (*(volatile hw_ipu_dp_fg_pos_async0_t *) HW_IPU_DP_FG_POS_ASYNC0_ADDR(x))
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#define HW_IPU_DP_FG_POS_ASYNC0_RD(x) (HW_IPU_DP_FG_POS_ASYNC0(x).U)
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#define HW_IPU_DP_FG_POS_ASYNC0_WR(x, v) (HW_IPU_DP_FG_POS_ASYNC0(x).U = (v))
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#define HW_IPU_DP_FG_POS_ASYNC0_SET(x, v) (HW_IPU_DP_FG_POS_ASYNC0_WR(x, HW_IPU_DP_FG_POS_ASYNC0_RD(x) | (v)))
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#define HW_IPU_DP_FG_POS_ASYNC0_CLR(x, v) (HW_IPU_DP_FG_POS_ASYNC0_WR(x, HW_IPU_DP_FG_POS_ASYNC0_RD(x) & ~(v)))
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#define HW_IPU_DP_FG_POS_ASYNC0_TOG(x, v) (HW_IPU_DP_FG_POS_ASYNC0_WR(x, HW_IPU_DP_FG_POS_ASYNC0_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DP_FG_POS_ASYNC0 bitfields
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*/
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/*! @name Register IPU_DP_FG_POS_ASYNC0, field DP_FGYP_ASYNC0[10:0] (RW)
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*
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* FGYP partial plane window Y position partial plane Window Y Position - Specifies the number of
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* lines between the start of full plane windows Y position and the beginning of the first data.
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*/
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//@{
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#define BP_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0 (0) //!< Bit position for IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0.
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#define BM_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0 (0x000007ff) //!< Bit mask for IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0.
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//! @brief Get value of IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0 from a register value.
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#define BG_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0) >> BP_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0.
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#define BF_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0) & BM_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_FGYP_ASYNC0 field to a new value.
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#define BW_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0(x, v) (HW_IPU_DP_FG_POS_ASYNC0_WR(x, (HW_IPU_DP_FG_POS_ASYNC0_RD(x) & ~BM_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0) | BF_IPU_DP_FG_POS_ASYNC0_DP_FGYP_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_FG_POS_ASYNC0, field DP_FGXP_ASYNC0[26:16] (RW)
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*
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* FGXP partial plane Window X Position. partial plane Window X Position - Specifies the number of
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* pixels between the start of full plane window X position and the beginning of the first data of
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* new line.
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*/
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//@{
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#define BP_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0 (16) //!< Bit position for IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0.
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#define BM_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0 (0x07ff0000) //!< Bit mask for IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0.
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//! @brief Get value of IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0 from a register value.
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#define BG_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0) >> BP_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0.
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#define BF_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0) & BM_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_FGXP_ASYNC0 field to a new value.
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#define BW_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0(x, v) (HW_IPU_DP_FG_POS_ASYNC0_WR(x, (HW_IPU_DP_FG_POS_ASYNC0_RD(x) & ~BM_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0) | BF_IPU_DP_FG_POS_ASYNC0_DP_FGXP_ASYNC0(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_CUR_POS_ASYNC0 - DP Cursor Position and Size Async 0 Flow Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DP_CUR_POS_ASYNC0 - DP Cursor Position and Size Async 0 Flow Register (RW)
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*
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* Reset value: 0x00000000
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*
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* The LCD Cursor Position Register is used to determine the starting position of the cursor
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* relative to BG windows position.
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*/
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typedef union _hw_ipu_dp_cur_pos_async0
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{
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reg32_t U;
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struct _hw_ipu_dp_cur_pos_async0_bitfields
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{
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unsigned DP_CXW_ASYNC0 : 11; //!< [10:0] CXW - Cursor Width.
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unsigned DP_CXP_ASYNC0 : 5; //!< [15:11] CXP - Cursor X Position
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unsigned DP_CYH_ASYNC0 : 11; //!< [26:16] CYH - Cursor Height
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unsigned DP_CYP_ASYNC0 : 5; //!< [31:27] CYP - Cursor Y Position
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} B;
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} hw_ipu_dp_cur_pos_async0_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DP_CUR_POS_ASYNC0 register
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*/
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//@{
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#define HW_IPU_DP_CUR_POS_ASYNC0_ADDR(x) (REGS_IPU_BASE(x) + 0x1806c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DP_CUR_POS_ASYNC0(x) (*(volatile hw_ipu_dp_cur_pos_async0_t *) HW_IPU_DP_CUR_POS_ASYNC0_ADDR(x))
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#define HW_IPU_DP_CUR_POS_ASYNC0_RD(x) (HW_IPU_DP_CUR_POS_ASYNC0(x).U)
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#define HW_IPU_DP_CUR_POS_ASYNC0_WR(x, v) (HW_IPU_DP_CUR_POS_ASYNC0(x).U = (v))
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#define HW_IPU_DP_CUR_POS_ASYNC0_SET(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, HW_IPU_DP_CUR_POS_ASYNC0_RD(x) | (v)))
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#define HW_IPU_DP_CUR_POS_ASYNC0_CLR(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, HW_IPU_DP_CUR_POS_ASYNC0_RD(x) & ~(v)))
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#define HW_IPU_DP_CUR_POS_ASYNC0_TOG(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, HW_IPU_DP_CUR_POS_ASYNC0_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DP_CUR_POS_ASYNC0 bitfields
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*/
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/*! @name Register IPU_DP_CUR_POS_ASYNC0, field DP_CXW_ASYNC0[10:0] (RW)
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*
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* CXW - Cursor Width. Specifies the width of the hardware cursor in pixels.
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*/
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//@{
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#define BP_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0 (0) //!< Bit position for IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0.
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#define BM_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0 (0x000007ff) //!< Bit mask for IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0.
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//! @brief Get value of IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0 from a register value.
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#define BG_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0) >> BP_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0.
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#define BF_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CXW_ASYNC0 field to a new value.
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#define BW_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, (HW_IPU_DP_CUR_POS_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0) | BF_IPU_DP_CUR_POS_ASYNC0_DP_CXW_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CUR_POS_ASYNC0, field DP_CXP_ASYNC0[15:11] (RW)
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*
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* CXP - Cursor X Position Represents the cursors horizontal starting position X in pixel count
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* (from 0 to CXW).
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*/
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//@{
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#define BP_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0 (11) //!< Bit position for IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0.
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#define BM_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0 (0x0000f800) //!< Bit mask for IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0.
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//! @brief Get value of IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0 from a register value.
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#define BG_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0) >> BP_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0.
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#define BF_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DP_CXP_ASYNC0 field to a new value.
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|
#define BW_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, (HW_IPU_DP_CUR_POS_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0) | BF_IPU_DP_CUR_POS_ASYNC0_DP_CXP_ASYNC0(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DP_CUR_POS_ASYNC0, field DP_CYH_ASYNC0[26:16] (RW)
|
|
*
|
|
* CYH - Cursor Height Specifies the height of the hardware cursor in pixels.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0 (16) //!< Bit position for IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0.
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|
#define BM_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0 (0x07ff0000) //!< Bit mask for IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0.
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|
//! @brief Get value of IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0) >> BP_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0)
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|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0.
|
|
#define BF_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CYH_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, (HW_IPU_DP_CUR_POS_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0) | BF_IPU_DP_CUR_POS_ASYNC0_DP_CYH_ASYNC0(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_ASYNC0, field DP_CYP_ASYNC0[31:27] (RW)
|
|
*
|
|
* CYP - Cursor Y Position Represents the cursors vertical starting position Y in pixel count (from
|
|
* 0 to CYH).Live View Resolution Mode.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0 (27) //!< Bit position for IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0.
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|
#define BM_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0 (0xf8000000) //!< Bit mask for IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0.
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|
|
|
//! @brief Get value of IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0) >> BP_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0)
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|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0.
|
|
#define BF_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0) & BM_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CYP_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0(x, v) (HW_IPU_DP_CUR_POS_ASYNC0_WR(x, (HW_IPU_DP_CUR_POS_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0) | BF_IPU_DP_CUR_POS_ASYNC0_DP_CYP_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CUR_MAP_ASYNC0 - DP Color Cursor Mapping Async 0 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CUR_MAP_ASYNC0 - DP Color Cursor Mapping Async 0 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The LCD Color Cursor Mapping Register defines the color of the cursor in passive or TFT color
|
|
* modes.
|
|
*/
|
|
typedef union _hw_ipu_dp_cur_map_async0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_cur_map_async0_bitfields
|
|
{
|
|
unsigned DP_CUR_COL_R_ASYNC0 : 8; //!< [7:0] CUR_COL_R - Cursor Red Field
|
|
unsigned DP_CUR_COL_G_ASYNC0 : 8; //!< [15:8] CUR_COL_G - Cursor Green Field
|
|
unsigned DP_CUR_COL_B_ASYNC0 : 8; //!< [23:16] CUR_COL_B - Cursor Blue Field
|
|
unsigned RESERVED0 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_dp_cur_map_async0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CUR_MAP_ASYNC0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0_ADDR(x) (REGS_IPU_BASE(x) + 0x18070)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0(x) (*(volatile hw_ipu_dp_cur_map_async0_t *) HW_IPU_DP_CUR_MAP_ASYNC0_ADDR(x))
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) (HW_IPU_DP_CUR_MAP_ASYNC0(x).U)
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0(x).U = (v))
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0_SET(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) | (v)))
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0_CLR(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC0_TOG(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CUR_MAP_ASYNC0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CUR_MAP_ASYNC0, field DP_CUR_COL_R_ASYNC0[7:0] (RW)
|
|
*
|
|
* CUR_COL_R - Cursor Red Field Defines the Red component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Red.
|
|
* - 11111111 - Full Red.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0 (0) //!< Bit position for IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0.
|
|
#define BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0 (0x000000ff) //!< Bit mask for IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0.
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|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0) >> BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0.
|
|
#define BF_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0) & BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_R_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, (HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0) | BF_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_R_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_MAP_ASYNC0, field DP_CUR_COL_G_ASYNC0[15:8] (RW)
|
|
*
|
|
* CUR_COL_G - Cursor Green Field Defines the Green component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Green.
|
|
* - 11111111 - Full Green.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0 (8) //!< Bit position for IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0.
|
|
#define BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0 (0x0000ff00) //!< Bit mask for IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0) >> BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0.
|
|
#define BF_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0) & BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_G_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, (HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0) | BF_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_G_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CUR_MAP_ASYNC0, field DP_CUR_COL_B_ASYNC0[23:16] (RW)
|
|
*
|
|
* CUR_COL_B - Cursor Blue Field Defines the Blue component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Blue.
|
|
* - 11111111 - Full Blue.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0 (16) //!< Bit position for IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0.
|
|
#define BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0 (0x00ff0000) //!< Bit mask for IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0) >> BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0.
|
|
#define BF_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0) & BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_B_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0(x, v) (HW_IPU_DP_CUR_MAP_ASYNC0_WR(x, (HW_IPU_DP_CUR_MAP_ASYNC0_RD(x) & ~BM_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0) | BF_IPU_DP_CUR_MAP_ASYNC0_DP_CUR_COL_B_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_GAMMA_C_ASYNC0_I - DP Gamma Constant Async 0 Flow Register i
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_GAMMA_C_ASYNC0_I - DP Gamma Constant Async 0 Flow Register i (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This registers contains CONSTANTi parameters used for gamma correction inside the display
|
|
* processor (DP).
|
|
*/
|
|
typedef union _hw_ipu_dp_gamma_c_async0_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_gamma_c_async0_i_bitfields
|
|
{
|
|
unsigned DP_GAMMA_C_ASYNC0_2I : 9; //!< [8:0] CONSTANTi parameter of Gamma Correction.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DP_GAMMA_C_ASYNC0_2I_1 : 12; //!< [27:16] CONSTANTi+1 parameter of Gamma Correction.
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved.
|
|
} B;
|
|
} hw_ipu_dp_gamma_c_async0_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GAMMA_C_ASYNC0_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I_ADDR(x) (REGS_IPU_BASE(x) + 0x18074)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I(x) (*(volatile hw_ipu_dp_gamma_c_async0_i_t *) HW_IPU_DP_GAMMA_C_ASYNC0_I_ADDR(x))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I_RD(x) (HW_IPU_DP_GAMMA_C_ASYNC0_I(x).U)
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I_WR(x, v) (HW_IPU_DP_GAMMA_C_ASYNC0_I(x).U = (v))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I_SET(x, v) (HW_IPU_DP_GAMMA_C_ASYNC0_I_WR(x, HW_IPU_DP_GAMMA_C_ASYNC0_I_RD(x) | (v)))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I_CLR(x, v) (HW_IPU_DP_GAMMA_C_ASYNC0_I_WR(x, HW_IPU_DP_GAMMA_C_ASYNC0_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC0_I_TOG(x, v) (HW_IPU_DP_GAMMA_C_ASYNC0_I_WR(x, HW_IPU_DP_GAMMA_C_ASYNC0_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_GAMMA_C_ASYNC0_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_GAMMA_C_ASYNC0_I, field DP_GAMMA_C_ASYNC0_2I[8:0] (RW)
|
|
*
|
|
* CONSTANTi parameter of Gamma Correction.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I (0) //!< Bit position for IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I.
|
|
#define BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I (0x000001ff) //!< Bit mask for IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I.
|
|
|
|
//! @brief Get value of IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I from a register value.
|
|
#define BG_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I) >> BP_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I.
|
|
#define BF_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I) & BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_C_ASYNC0_2I field to a new value.
|
|
#define BW_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I(x, v) (HW_IPU_DP_GAMMA_C_ASYNC0_I_WR(x, (HW_IPU_DP_GAMMA_C_ASYNC0_I_RD(x) & ~BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I) | BF_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GAMMA_C_ASYNC0_I, field DP_GAMMA_C_ASYNC0_2I_1[27:16] (RW)
|
|
*
|
|
* CONSTANTi+1 parameter of Gamma Correction.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1 (16) //!< Bit position for IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1.
|
|
#define BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1 (0x0fff0000) //!< Bit mask for IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1.
|
|
|
|
//! @brief Get value of IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1 from a register value.
|
|
#define BG_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1) >> BP_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1.
|
|
#define BF_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1) & BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_C_ASYNC0_2I_1 field to a new value.
|
|
#define BW_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1(x, v) (HW_IPU_DP_GAMMA_C_ASYNC0_I_WR(x, (HW_IPU_DP_GAMMA_C_ASYNC0_I_RD(x) & ~BM_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1) | BF_IPU_DP_GAMMA_C_ASYNC0_I_DP_GAMMA_C_ASYNC0_2I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_GAMMA_S_ASYNC0_I - DP Gamma Correction Slope Async 0 Flow Register i
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_GAMMA_S_ASYNC0_I - DP Gamma Correction Slope Async 0 Flow Register i (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This registers contains SLOPEi parameters used for Gamma Correction inside the display processor
|
|
* (DP).
|
|
*/
|
|
typedef union _hw_ipu_dp_gamma_s_async0_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_gamma_s_async0_i_bitfields
|
|
{
|
|
unsigned DP_GAMMA_S_ASYNC0_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Gamma Correction.
|
|
unsigned DP_GAMMA_S_ASYNC0_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Gamma Correction.
|
|
unsigned DP_GAMMA_S_ASYNC0_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Gamma Correction.
|
|
unsigned DP_GAMMA_S_ASYNC0_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Gamma Correction.
|
|
} B;
|
|
} hw_ipu_dp_gamma_s_async0_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GAMMA_S_ASYNC0_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_GAMMA_S_ASYNC0_I_ADDR(x) (REGS_IPU_BASE(x) + 0x18094)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GAMMA_S_ASYNC0_I(x) (*(volatile hw_ipu_dp_gamma_s_async0_i_t *) HW_IPU_DP_GAMMA_S_ASYNC0_I_ADDR(x))
|
|
#define HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) (HW_IPU_DP_GAMMA_S_ASYNC0_I(x).U)
|
|
#define HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I(x).U = (v))
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#define HW_IPU_DP_GAMMA_S_ASYNC0_I_SET(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) | (v)))
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#define HW_IPU_DP_GAMMA_S_ASYNC0_I_CLR(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) & ~(v)))
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|
#define HW_IPU_DP_GAMMA_S_ASYNC0_I_TOG(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DP_GAMMA_S_ASYNC0_I bitfields
|
|
*/
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|
|
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/*! @name Register IPU_DP_GAMMA_S_ASYNC0_I, field DP_GAMMA_S_ASYNC0_4I[7:0] (RW)
|
|
*
|
|
* SLOPE<4*i> parameter of Gamma Correction.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I (0) //!< Bit position for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I.
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#define BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I (0x000000ff) //!< Bit mask for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I from a register value.
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#define BG_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I) >> BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I.
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#define BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_S_ASYNC0_4I field to a new value.
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|
#define BW_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I) | BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_S_ASYNC0_I, field DP_GAMMA_S_ASYNC0_4I_1[15:8] (RW)
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|
*
|
|
* SLOPE<4*i+1> parameter of Gamma Correction.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1 (8) //!< Bit position for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1.
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#define BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1 (0x0000ff00) //!< Bit mask for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1 from a register value.
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#define BG_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1) >> BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1.
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#define BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_S_ASYNC0_4I_1 field to a new value.
|
|
#define BW_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1) | BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_1(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DP_GAMMA_S_ASYNC0_I, field DP_GAMMA_S_ASYNC0_4I_2[23:16] (RW)
|
|
*
|
|
* SLOPE<4*i+2> parameter of Gamma Correction.
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|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2 (16) //!< Bit position for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2.
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#define BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2 (0x00ff0000) //!< Bit mask for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2 from a register value.
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|
#define BG_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2) >> BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2)
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|
//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2.
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|
#define BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_S_ASYNC0_4I_2 field to a new value.
|
|
#define BW_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2) | BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GAMMA_S_ASYNC0_I, field DP_GAMMA_S_ASYNC0_4I_3[31:24] (RW)
|
|
*
|
|
* SLOPE<4*i+3> parameter of Gamma Correction.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3 (24) //!< Bit position for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3.
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|
#define BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3 (0xff000000) //!< Bit mask for IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3.
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|
//! @brief Get value of IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3 from a register value.
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|
#define BG_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3) >> BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3)
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|
//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3.
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|
#define BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3) & BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_S_ASYNC0_4I_3 field to a new value.
|
|
#define BW_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3(x, v) (HW_IPU_DP_GAMMA_S_ASYNC0_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYNC0_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3) | BF_IPU_DP_GAMMA_S_ASYNC0_I_DP_GAMMA_S_ASYNC0_4I_3(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CSCA_ASYNC0_I - DP Color Space Conversion Control Async 0 Flow Register i
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CSCA_ASYNC0_I - DP Color Space Conversion Control Async 0 Flow Register i (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_csca_async0_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_csca_async0_i_bitfields
|
|
{
|
|
unsigned DP_CSC_A_ASYNC0_2I : 10; //!< [9:0] A<2*i> parameter of color conversion.
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved.
|
|
unsigned DP_CSC_A_ASYNC0_2I_1 : 10; //!< [25:16] A<2*i+1> parameter of color conversion
|
|
unsigned RESERVED1 : 6; //!< [31:26] Reserved.
|
|
} B;
|
|
} hw_ipu_dp_csca_async0_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CSCA_ASYNC0_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I_ADDR(x) (REGS_IPU_BASE(x) + 0x180a4)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I(x) (*(volatile hw_ipu_dp_csca_async0_i_t *) HW_IPU_DP_CSCA_ASYNC0_I_ADDR(x))
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I_RD(x) (HW_IPU_DP_CSCA_ASYNC0_I(x).U)
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I_WR(x, v) (HW_IPU_DP_CSCA_ASYNC0_I(x).U = (v))
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I_SET(x, v) (HW_IPU_DP_CSCA_ASYNC0_I_WR(x, HW_IPU_DP_CSCA_ASYNC0_I_RD(x) | (v)))
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I_CLR(x, v) (HW_IPU_DP_CSCA_ASYNC0_I_WR(x, HW_IPU_DP_CSCA_ASYNC0_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CSCA_ASYNC0_I_TOG(x, v) (HW_IPU_DP_CSCA_ASYNC0_I_WR(x, HW_IPU_DP_CSCA_ASYNC0_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CSCA_ASYNC0_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CSCA_ASYNC0_I, field DP_CSC_A_ASYNC0_2I[9:0] (RW)
|
|
*
|
|
* A<2*i> parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I (0) //!< Bit position for IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I.
|
|
#define BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I (0x000003ff) //!< Bit mask for IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I.
|
|
|
|
//! @brief Get value of IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I from a register value.
|
|
#define BG_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I) >> BP_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I.
|
|
#define BF_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I) & BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_A_ASYNC0_2I field to a new value.
|
|
#define BW_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I(x, v) (HW_IPU_DP_CSCA_ASYNC0_I_WR(x, (HW_IPU_DP_CSCA_ASYNC0_I_RD(x) & ~BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I) | BF_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSCA_ASYNC0_I, field DP_CSC_A_ASYNC0_2I_1[25:16] (RW)
|
|
*
|
|
* A<2*i+1> parameter of color conversion
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1 (16) //!< Bit position for IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1.
|
|
#define BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1 (0x03ff0000) //!< Bit mask for IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1.
|
|
|
|
//! @brief Get value of IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1 from a register value.
|
|
#define BG_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1) >> BP_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1.
|
|
#define BF_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1) & BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_A_ASYNC0_2I_1 field to a new value.
|
|
#define BW_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1(x, v) (HW_IPU_DP_CSCA_ASYNC0_I_WR(x, (HW_IPU_DP_CSCA_ASYNC0_I_RD(x) & ~BM_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1) | BF_IPU_DP_CSCA_ASYNC0_I_DP_CSC_A_ASYNC0_2I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CSC_ASYNC0_0 - DP Color Conversion Control Async 0 Flow Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CSC_ASYNC0_0 - DP Color Conversion Control Async 0 Flow Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_csc_async0_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_csc_async0_0_bitfields
|
|
{
|
|
unsigned DP_CSC_A8_ASYNC0 : 10; //!< [9:0] A9 parameter of color conversion.
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved.
|
|
unsigned DP_CSC_B0_ASYNC0 : 14; //!< [29:16] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S0_ASYNC0 : 2; //!< [31:30] S0 parameter of color conversion.
|
|
} B;
|
|
} hw_ipu_dp_csc_async0_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CSC_ASYNC0_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CSC_ASYNC0_0_ADDR(x) (REGS_IPU_BASE(x) + 0x180b4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CSC_ASYNC0_0(x) (*(volatile hw_ipu_dp_csc_async0_0_t *) HW_IPU_DP_CSC_ASYNC0_0_ADDR(x))
|
|
#define HW_IPU_DP_CSC_ASYNC0_0_RD(x) (HW_IPU_DP_CSC_ASYNC0_0(x).U)
|
|
#define HW_IPU_DP_CSC_ASYNC0_0_WR(x, v) (HW_IPU_DP_CSC_ASYNC0_0(x).U = (v))
|
|
#define HW_IPU_DP_CSC_ASYNC0_0_SET(x, v) (HW_IPU_DP_CSC_ASYNC0_0_WR(x, HW_IPU_DP_CSC_ASYNC0_0_RD(x) | (v)))
|
|
#define HW_IPU_DP_CSC_ASYNC0_0_CLR(x, v) (HW_IPU_DP_CSC_ASYNC0_0_WR(x, HW_IPU_DP_CSC_ASYNC0_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CSC_ASYNC0_0_TOG(x, v) (HW_IPU_DP_CSC_ASYNC0_0_WR(x, HW_IPU_DP_CSC_ASYNC0_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CSC_ASYNC0_0 bitfields
|
|
*/
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|
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/*! @name Register IPU_DP_CSC_ASYNC0_0, field DP_CSC_A8_ASYNC0[9:0] (RW)
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|
*
|
|
* A9 parameter of color conversion.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0 (0) //!< Bit position for IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0.
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#define BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0 (0x000003ff) //!< Bit mask for IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0.
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//! @brief Get value of IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0 from a register value.
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#define BG_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0) >> BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0.
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|
#define BF_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0) & BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_A8_ASYNC0 field to a new value.
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|
#define BW_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC0_0_WR(x, (HW_IPU_DP_CSC_ASYNC0_0_RD(x) & ~BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0) | BF_IPU_DP_CSC_ASYNC0_0_DP_CSC_A8_ASYNC0(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CSC_ASYNC0_0, field DP_CSC_B0_ASYNC0[29:16] (RW)
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*
|
|
* B0 parameter of color conversion.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0 (16) //!< Bit position for IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0.
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#define BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0 (0x3fff0000) //!< Bit mask for IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0.
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//! @brief Get value of IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0 from a register value.
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#define BG_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0) >> BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0.
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#define BF_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0) & BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_B0_ASYNC0 field to a new value.
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|
#define BW_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC0_0_WR(x, (HW_IPU_DP_CSC_ASYNC0_0_RD(x) & ~BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0) | BF_IPU_DP_CSC_ASYNC0_0_DP_CSC_B0_ASYNC0(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DP_CSC_ASYNC0_0, field DP_CSC_S0_ASYNC0[31:30] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0
|
|
* - 11 - scale factor of -1
|
|
*/
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|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0 (30) //!< Bit position for IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0.
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|
#define BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0 (0xc0000000) //!< Bit mask for IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0.
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//! @brief Get value of IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0 from a register value.
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|
#define BG_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0) >> BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0)
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0.
|
|
#define BF_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0) & BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S0_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC0_0_WR(x, (HW_IPU_DP_CSC_ASYNC0_0_RD(x) & ~BM_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0) | BF_IPU_DP_CSC_ASYNC0_0_DP_CSC_S0_ASYNC0(v)))
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|
#endif
|
|
//@}
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|
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|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CSC_ASYNC_1 - DP Color Conversion Control Async 1 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CSC_ASYNC_1 - DP Color Conversion Control Async 1 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_csc_async_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_csc_async_1_bitfields
|
|
{
|
|
unsigned DP_CSC_B1_ASYNC0 : 14; //!< [13:0] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S1_ASYNC0 : 2; //!< [15:14] S0 parameter of color conversion.
|
|
unsigned DP_CSC_B2_ASYNC0 : 14; //!< [29:16] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S2_ASYNC0 : 2; //!< [31:30] S0 parameter of color conversion.
|
|
} B;
|
|
} hw_ipu_dp_csc_async_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CSC_ASYNC_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CSC_ASYNC_1_ADDR(x) (REGS_IPU_BASE(x) + 0x180b8)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CSC_ASYNC_1(x) (*(volatile hw_ipu_dp_csc_async_1_t *) HW_IPU_DP_CSC_ASYNC_1_ADDR(x))
|
|
#define HW_IPU_DP_CSC_ASYNC_1_RD(x) (HW_IPU_DP_CSC_ASYNC_1(x).U)
|
|
#define HW_IPU_DP_CSC_ASYNC_1_WR(x, v) (HW_IPU_DP_CSC_ASYNC_1(x).U = (v))
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|
#define HW_IPU_DP_CSC_ASYNC_1_SET(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, HW_IPU_DP_CSC_ASYNC_1_RD(x) | (v)))
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|
#define HW_IPU_DP_CSC_ASYNC_1_CLR(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, HW_IPU_DP_CSC_ASYNC_1_RD(x) & ~(v)))
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|
#define HW_IPU_DP_CSC_ASYNC_1_TOG(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, HW_IPU_DP_CSC_ASYNC_1_RD(x) ^ (v)))
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|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CSC_ASYNC_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC_1, field DP_CSC_B1_ASYNC0[13:0] (RW)
|
|
*
|
|
* B0 parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0 (0) //!< Bit position for IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0.
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|
#define BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0 (0x00003fff) //!< Bit mask for IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0.
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|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0) >> BP_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0)
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|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0.
|
|
#define BF_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B1_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, (HW_IPU_DP_CSC_ASYNC_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0) | BF_IPU_DP_CSC_ASYNC_1_DP_CSC_B1_ASYNC0(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC_1, field DP_CSC_S1_ASYNC0[15:14] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0 11 scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0 (14) //!< Bit position for IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0.
|
|
#define BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0 (0x0000c000) //!< Bit mask for IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0) >> BP_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0.
|
|
#define BF_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S1_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, (HW_IPU_DP_CSC_ASYNC_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0) | BF_IPU_DP_CSC_ASYNC_1_DP_CSC_S1_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC_1, field DP_CSC_B2_ASYNC0[29:16] (RW)
|
|
*
|
|
* B0 parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0 (16) //!< Bit position for IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0.
|
|
#define BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0 (0x3fff0000) //!< Bit mask for IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0) >> BP_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0.
|
|
#define BF_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B2_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, (HW_IPU_DP_CSC_ASYNC_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0) | BF_IPU_DP_CSC_ASYNC_1_DP_CSC_B2_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC_1, field DP_CSC_S2_ASYNC0[31:30] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0 11 scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0 (30) //!< Bit position for IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0.
|
|
#define BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0 (0xc0000000) //!< Bit mask for IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0.
|
|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0) >> BP_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0.
|
|
#define BF_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0) & BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S2_ASYNC0 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0(x, v) (HW_IPU_DP_CSC_ASYNC_1_WR(x, (HW_IPU_DP_CSC_ASYNC_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0) | BF_IPU_DP_CSC_ASYNC_1_DP_CSC_S2_ASYNC0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_COM_CONF_ASYNC1 - DP Common Configuration Async 1 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_COM_CONF_ASYNC1 - DP Common Configuration Async 1 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains common configuration parameters for the DP.
|
|
*/
|
|
typedef union _hw_ipu_dp_com_conf_async1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_com_conf_async1_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved
|
|
unsigned DP_GWSEL_ASYNC1 : 1; //!< [1] GWSEL - Graphic Window Select
|
|
unsigned DP_GWAM_ASYNC1 : 1; //!< [2] GWAM - Graphic Window Alpha Mode
|
|
unsigned DP_GWCKE_ASYNC1 : 1; //!< [3] GWCKE - Graphic Window Color Keying Enable
|
|
unsigned DP_COC_ASYNC1 : 3; //!< [6:4] COC - Cursor Operation Control
|
|
unsigned RESERVED1 : 1; //!< [7] Reserved
|
|
unsigned DP_CSC_DEF_ASYNC1 : 2; //!< [9:8] CSC_DEF
|
|
unsigned DP_CSC_GAMUT_SAT_EN_ASYNC1 : 1; //!< [10] CSC_GAMUT_SAT_EN
|
|
unsigned DP_CSC_YUV_SAT_MODE_ASYNC1 : 1; //!< [11] CSC_YUV_SAT_MODE
|
|
unsigned DP_GAMMA_EN_ASYNC1 : 1; //!< [12] GAMMA_EN - Gamma correction block enable bit
|
|
unsigned DP_GAMMA_YUV_EN_ASYNC1 : 1; //!< [13] GAMMA's YUV mode enable for async flow 1
|
|
unsigned RESERVED2 : 18; //!< [31:14] Reserved
|
|
} B;
|
|
} hw_ipu_dp_com_conf_async1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_COM_CONF_ASYNC1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_COM_CONF_ASYNC1_ADDR(x) (REGS_IPU_BASE(x) + 0x180bc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_COM_CONF_ASYNC1(x) (*(volatile hw_ipu_dp_com_conf_async1_t *) HW_IPU_DP_COM_CONF_ASYNC1_ADDR(x))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC1_RD(x) (HW_IPU_DP_COM_CONF_ASYNC1(x).U)
|
|
#define HW_IPU_DP_COM_CONF_ASYNC1_WR(x, v) (HW_IPU_DP_COM_CONF_ASYNC1(x).U = (v))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC1_SET(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, HW_IPU_DP_COM_CONF_ASYNC1_RD(x) | (v)))
|
|
#define HW_IPU_DP_COM_CONF_ASYNC1_CLR(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~(v)))
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#define HW_IPU_DP_COM_CONF_ASYNC1_TOG(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, HW_IPU_DP_COM_CONF_ASYNC1_RD(x) ^ (v)))
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#endif
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|
//@}
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|
|
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/*
|
|
* constants & macros for individual IPU_DP_COM_CONF_ASYNC1 bitfields
|
|
*/
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|
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/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_GWSEL_ASYNC1[1] (RW)
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|
*
|
|
* GWSEL - Graphic Window Select Select graphic window to be on partial plane or full plane.
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|
*
|
|
* Values:
|
|
* - 0 - Graphic window is full plane.
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|
* - 1 - Graphic window is partial plane.
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|
*/
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//@{
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|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1 (1) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1.
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#define BM_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1 (0x00000002) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1.
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#define BF_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GWSEL_ASYNC1 field to a new value.
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#define BW_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_GWSEL_ASYNC1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_GWAM_ASYNC1[2] (RW)
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|
*
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|
* GWAM - Graphic Window Alpha Mode Select the use of Alpha to be global or local.
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*
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|
* Values:
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|
* - 0 - Local Alpha.
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|
* - 1 - Global Alpha.
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*/
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//@{
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|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1 (2) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1.
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#define BM_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1 (0x00000004) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1 from a register value.
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#define BG_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1.
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#define BF_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DP_GWAM_ASYNC1 field to a new value.
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|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_GWAM_ASYNC1(v)))
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|
#endif
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//@}
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|
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/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_GWCKE_ASYNC1[3] (RW)
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|
*
|
|
* GWCKE - Graphic Window Color Keying Enable Enable or disable graphic window color keying.
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|
*
|
|
* Values:
|
|
* - 0 - Disable color keying of graphic window
|
|
* - 1 - Enable color keying of graphic window
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1 (3) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1.
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#define BM_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1 (0x00000008) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1.
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//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1 from a register value.
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|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1)
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|
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//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1.
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|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKE_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_GWCKE_ASYNC1(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_COC_ASYNC1[6:4] (RW)
|
|
*
|
|
* COC - Cursor Operation Control Controls the format of the cursor and the type of arithmetic
|
|
* operations
|
|
*
|
|
* Values:
|
|
* - 000 - Transparent, cursor is disabled.
|
|
* - 001 - Full cursor.
|
|
* - 010 - Reversed cursor.
|
|
* - 011 - AND between full plane and cursor.
|
|
* - 100 - Reserved
|
|
* - 101 - OR between full plane and cursor.
|
|
* - 110 - XOR between full plane and cursor.
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1 (4) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1.
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|
#define BM_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1 (0x00000070) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1.
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|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_COC_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_COC_ASYNC1(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_CSC_DEF_ASYNC1[9:8] (RW)
|
|
*
|
|
* CSC_DEF Enable or disable Color Space Conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - CSC disable
|
|
* - 01 - CSC enable after combining
|
|
* - 10 - CSC enable before combining on BG channel
|
|
* - 11 - CSC enable before combining on FG channel
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|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1 (8) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1.
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|
#define BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1 (0x00000300) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1.
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|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_DEF_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_CSC_DEF_ASYNC1(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_CSC_GAMUT_SAT_EN_ASYNC1[10] (RW)
|
|
*
|
|
* CSC_GAMUT_SAT_EN Indicate if GAMUT saturation is enabled
|
|
*
|
|
* Values:
|
|
* - 0 - disable GAMUT mapping
|
|
* - 1 - enable GAMUT mapping
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1 (10) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1 (0x00000400) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_GAMUT_SAT_EN_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_CSC_GAMUT_SAT_EN_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_CSC_YUV_SAT_MODE_ASYNC1[11] (RW)
|
|
*
|
|
* CSC_YUV_SAT_MODE YUV saturation mode for color space conversion
|
|
*
|
|
* Values:
|
|
* - 0 - Y/U/V range 0 -255
|
|
* - 1 - Y range 16-235, U/V range 16-240
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1 (11) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1 (0x00000800) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_YUV_SAT_MODE_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_CSC_YUV_SAT_MODE_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_GAMMA_EN_ASYNC1[12] (RW)
|
|
*
|
|
* GAMMA_EN - Gamma correction block enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - disable
|
|
* - 1 - enable
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1 (12) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1 (0x00001000) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_EN_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_EN_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_COM_CONF_ASYNC1, field DP_GAMMA_YUV_EN_ASYNC1[13] (RW)
|
|
*
|
|
* GAMMA's YUV mode enable for async flow 1
|
|
*
|
|
* Values:
|
|
* - 0 - YUV mode is OFF.
|
|
* - 1 - YUV mode is ON.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1 (13) //!< Bit position for IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1.
|
|
#define BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1 (0x00002000) //!< Bit mask for IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1) >> BP_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1.
|
|
#define BF_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1) & BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GAMMA_YUV_EN_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1(x, v) (HW_IPU_DP_COM_CONF_ASYNC1_WR(x, (HW_IPU_DP_COM_CONF_ASYNC1_RD(x) & ~BM_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1) | BF_IPU_DP_COM_CONF_ASYNC1_DP_GAMMA_YUV_EN_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_DEBUG_CNT - DP Debug Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_DEBUG_CNT - DP Debug Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This is the debug unit control register. This register is not stored in the SRM.
|
|
*/
|
|
typedef union _hw_ipu_dp_debug_cnt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_debug_cnt_bitfields
|
|
{
|
|
unsigned BRAKE_STATUS_EN_0 : 1; //!< [0] This bit enables the break/status unit #0
|
|
unsigned BRAKE_CNT_0 : 3; //!< [3:1] The async flow can be broken multiple times.
|
|
unsigned BRAKE_STATUS_EN_1 : 1; //!< [4] This bit enables the break/status unit #1
|
|
unsigned BRAKE_CNT_1 : 3; //!< [7:5] The async flow can be broken multiple times.
|
|
unsigned RESERVED0 : 24; //!< [31:8] Reserved
|
|
} B;
|
|
} hw_ipu_dp_debug_cnt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_DEBUG_CNT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_DEBUG_CNT_ADDR(x) (REGS_IPU_BASE(x) + 0x180bc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_DEBUG_CNT(x) (*(volatile hw_ipu_dp_debug_cnt_t *) HW_IPU_DP_DEBUG_CNT_ADDR(x))
|
|
#define HW_IPU_DP_DEBUG_CNT_RD(x) (HW_IPU_DP_DEBUG_CNT(x).U)
|
|
#define HW_IPU_DP_DEBUG_CNT_WR(x, v) (HW_IPU_DP_DEBUG_CNT(x).U = (v))
|
|
#define HW_IPU_DP_DEBUG_CNT_SET(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, HW_IPU_DP_DEBUG_CNT_RD(x) | (v)))
|
|
#define HW_IPU_DP_DEBUG_CNT_CLR(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, HW_IPU_DP_DEBUG_CNT_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_DEBUG_CNT_TOG(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, HW_IPU_DP_DEBUG_CNT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_DEBUG_CNT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_DEBUG_CNT, field BRAKE_STATUS_EN_0[0] (RW)
|
|
*
|
|
* This bit enables the break/status unit #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0 (0) //!< Bit position for IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0.
|
|
#define BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0 (0x00000001) //!< Bit mask for IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0 from a register value.
|
|
#define BG_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0) >> BP_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0.
|
|
#define BF_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0) & BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BRAKE_STATUS_EN_0 field to a new value.
|
|
#define BW_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, (HW_IPU_DP_DEBUG_CNT_RD(x) & ~BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0) | BF_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_CNT, field BRAKE_CNT_0[3:1] (RW)
|
|
*
|
|
* The async flow can be broken multiple times. It possible to control which breaking event will
|
|
* cause the interrupt. This field counts the breaking events for unit #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_CNT_BRAKE_CNT_0 (1) //!< Bit position for IPU_DP_DEBUG_CNT_BRAKE_CNT_0.
|
|
#define BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_0 (0x0000000e) //!< Bit mask for IPU_DP_DEBUG_CNT_BRAKE_CNT_0.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_CNT_BRAKE_CNT_0 from a register value.
|
|
#define BG_IPU_DP_DEBUG_CNT_BRAKE_CNT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_0) >> BP_IPU_DP_DEBUG_CNT_BRAKE_CNT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_DEBUG_CNT_BRAKE_CNT_0.
|
|
#define BF_IPU_DP_DEBUG_CNT_BRAKE_CNT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_DEBUG_CNT_BRAKE_CNT_0) & BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BRAKE_CNT_0 field to a new value.
|
|
#define BW_IPU_DP_DEBUG_CNT_BRAKE_CNT_0(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, (HW_IPU_DP_DEBUG_CNT_RD(x) & ~BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_0) | BF_IPU_DP_DEBUG_CNT_BRAKE_CNT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_CNT, field BRAKE_STATUS_EN_1[4] (RW)
|
|
*
|
|
* This bit enables the break/status unit #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1 (4) //!< Bit position for IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1.
|
|
#define BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1 (0x00000010) //!< Bit mask for IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1 from a register value.
|
|
#define BG_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1) >> BP_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1.
|
|
#define BF_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1) & BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BRAKE_STATUS_EN_1 field to a new value.
|
|
#define BW_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, (HW_IPU_DP_DEBUG_CNT_RD(x) & ~BM_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1) | BF_IPU_DP_DEBUG_CNT_BRAKE_STATUS_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_CNT, field BRAKE_CNT_1[7:5] (RW)
|
|
*
|
|
* The async flow can be broken multiple times. It possible to control which breaking event will
|
|
* cause the interrupt. This field counts the breaking events for unit #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_CNT_BRAKE_CNT_1 (5) //!< Bit position for IPU_DP_DEBUG_CNT_BRAKE_CNT_1.
|
|
#define BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_1 (0x000000e0) //!< Bit mask for IPU_DP_DEBUG_CNT_BRAKE_CNT_1.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_CNT_BRAKE_CNT_1 from a register value.
|
|
#define BG_IPU_DP_DEBUG_CNT_BRAKE_CNT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_1) >> BP_IPU_DP_DEBUG_CNT_BRAKE_CNT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_DEBUG_CNT_BRAKE_CNT_1.
|
|
#define BF_IPU_DP_DEBUG_CNT_BRAKE_CNT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_DEBUG_CNT_BRAKE_CNT_1) & BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BRAKE_CNT_1 field to a new value.
|
|
#define BW_IPU_DP_DEBUG_CNT_BRAKE_CNT_1(x, v) (HW_IPU_DP_DEBUG_CNT_WR(x, (HW_IPU_DP_DEBUG_CNT_RD(x) & ~BM_IPU_DP_DEBUG_CNT_BRAKE_CNT_1) | BF_IPU_DP_DEBUG_CNT_BRAKE_CNT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1 - DP Graphic Window Control Async 1 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1 - DP Graphic Window Control Async 1 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains common configuration parameters for the DP.
|
|
*/
|
|
typedef union _hw_ipu_dp_graph_wind_ctrl_async1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_graph_wind_ctrl_async1_bitfields
|
|
{
|
|
unsigned DP_GWCKB_ASYNC1 : 8; //!< [7:0] GWCKB - Graphic Window Color Keying Blue Component
|
|
unsigned DP_GWCKG_ASYNC1 : 8; //!< [15:8] GWCKG - Graphic Window Color Keying Green Component
|
|
unsigned DP_GWCKR_ASYNC1 : 8; //!< [23:16] GWCKR - Graphic Window Color Keying Red Component
|
|
unsigned DP_GWAV_ASYNC1 : 8; //!< [31:24] GWAV - Graphic Window Alpha Value
|
|
} B;
|
|
} hw_ipu_dp_graph_wind_ctrl_async1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GRAPH_WIND_CTRL_ASYNC1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_ADDR(x) (REGS_IPU_BASE(x) + 0x180c0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1(x) (*(volatile hw_ipu_dp_graph_wind_ctrl_async1_t *) HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_ADDR(x))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1(x).U)
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1(x).U = (v))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_SET(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) | (v)))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_CLR(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_TOG(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_GRAPH_WIND_CTRL_ASYNC1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC1, field DP_GWCKB_ASYNC1[7:0] (RW)
|
|
*
|
|
* GWCKB - Graphic Window Color Keying Blue Component Defines the blue component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No blue
|
|
* - 11111111 - Full blue
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1 (0) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1 (0x000000ff) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKB_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKB_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC1, field DP_GWCKG_ASYNC1[15:8] (RW)
|
|
*
|
|
* GWCKG - Graphic Window Color Keying Green Component Defines the green component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Green
|
|
* - 11111111 - Full Green
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1 (8) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1 (0x0000ff00) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKG_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKG_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC1, field DP_GWCKR_ASYNC1[23:16] (RW)
|
|
*
|
|
* GWCKR - Graphic Window Color Keying Red Component Defines the red component of graphic window
|
|
* color keying.
|
|
*
|
|
* Values:
|
|
* - 00000000 - No red
|
|
* - 11111111 - Full red
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1 (16) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1 (0x00ff0000) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWCKR_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWCKR_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_GRAPH_WIND_CTRL_ASYNC1, field DP_GWAV_ASYNC1[31:24] (RW)
|
|
*
|
|
* GWAV - Graphic Window Alpha Value Defines the alpha value of graphic window used for alpha
|
|
* blending between graphic window and full plane. The Value the number that writing to GWAV
|
|
* register. The Actual Value the number, that insert to calculation in Combining Module. If Value =
|
|
* < 0.5- 1/256 (01111111) then Actual Value = Value. If Value >= 0.5 (10000000), then Actual Value
|
|
* = Value + 1/256.
|
|
*
|
|
* Values:
|
|
* - 00000000 - Actual value is 00000000; Graphic window totally opaque i.e. overlay on LCD screen
|
|
* - 01111111 - Actual value is 01111111;
|
|
* - 10000000 - Actual value is 10000001
|
|
* - 10000001 - Actual value is 10000010
|
|
* - 11111110 - Actual value is 11111111
|
|
* - 11111111 - Actual value is 100000000;Graphic window totally transparent i.e. not displayed on LCD screen
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1 (24) //!< Bit position for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1.
|
|
#define BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1 (0xff000000) //!< Bit mask for IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1) >> BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1.
|
|
#define BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1) & BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_GWAV_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1(x, v) (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_WR(x, (HW_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_RD(x) & ~BM_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1) | BF_IPU_DP_GRAPH_WIND_CTRL_ASYNC1_DP_GWAV_ASYNC1(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_DEBUG_STAT - DP Debug Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_DEBUG_STAT - DP Debug Status Register (RO)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_debug_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_debug_stat_bitfields
|
|
{
|
|
unsigned V_CNT_OLD_0 : 11; //!< [10:0] The exact row where the async flow has been broken (This filed is relevant for debug unit #0)
|
|
unsigned FG_ACTIVE_0 : 1; //!< [11] Displaying the partial frame has been started for async flow (This filed is relevant for debug unit #0)
|
|
unsigned COMBYP_EN_OLD_0 : 1; //!< [12] the async flow has been broken in the middle of combining (This filed is relevant for debug unit #0)
|
|
unsigned CYP_EN_OLD_0 : 1; //!< [13] The async flow has been broken in the middle of a cursor (This filed is relevant for debug unit #0)
|
|
unsigned RESERVED0 : 2; //!< [15:14] Reserved
|
|
unsigned V_CNT_OLD_1 : 11; //!< [26:16] The exact row where the async flow has been broken (This filed is relevant for debug unit #0)
|
|
unsigned FG_ACTIVE_1 : 1; //!< [27] Displaying the partial frame has been started (This filed is relevant for debug unit #1)
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|
unsigned COMBYP_EN_OLD_1 : 1; //!< [28] the async1 flow has been broken in the middle of combining (This filed is relevant for debug unit #1)
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|
unsigned CYP_EN_OLD_1 : 1; //!< [29] The async flow has been broken in the middle of a cursor (This filed is relevant for debug unit #1)
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|
unsigned RESERVED1 : 2; //!< [31:30] Reserved
|
|
} B;
|
|
} hw_ipu_dp_debug_stat_t;
|
|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_DEBUG_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_DEBUG_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x180c0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_DEBUG_STAT(x) (*(volatile hw_ipu_dp_debug_stat_t *) HW_IPU_DP_DEBUG_STAT_ADDR(x))
|
|
#define HW_IPU_DP_DEBUG_STAT_RD(x) (HW_IPU_DP_DEBUG_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_DEBUG_STAT bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field V_CNT_OLD_0[10:0] (RO)
|
|
*
|
|
* The exact row where the async flow has been broken (This filed is relevant for debug unit #0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_V_CNT_OLD_0 (0) //!< Bit position for IPU_DP_DEBUG_STAT_V_CNT_OLD_0.
|
|
#define BM_IPU_DP_DEBUG_STAT_V_CNT_OLD_0 (0x000007ff) //!< Bit mask for IPU_DP_DEBUG_STAT_V_CNT_OLD_0.
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|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_V_CNT_OLD_0 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_V_CNT_OLD_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_V_CNT_OLD_0) >> BP_IPU_DP_DEBUG_STAT_V_CNT_OLD_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field FG_ACTIVE_0[11] (RO)
|
|
*
|
|
* Displaying the partial frame has been started for async flow (This filed is relevant for debug
|
|
* unit #0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_FG_ACTIVE_0 (11) //!< Bit position for IPU_DP_DEBUG_STAT_FG_ACTIVE_0.
|
|
#define BM_IPU_DP_DEBUG_STAT_FG_ACTIVE_0 (0x00000800) //!< Bit mask for IPU_DP_DEBUG_STAT_FG_ACTIVE_0.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_FG_ACTIVE_0 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_FG_ACTIVE_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_FG_ACTIVE_0) >> BP_IPU_DP_DEBUG_STAT_FG_ACTIVE_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field COMBYP_EN_OLD_0[12] (RO)
|
|
*
|
|
* the async flow has been broken in the middle of combining (This filed is relevant for debug unit
|
|
* #0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0 (12) //!< Bit position for IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0.
|
|
#define BM_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0 (0x00001000) //!< Bit mask for IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0) >> BP_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field CYP_EN_OLD_0[13] (RO)
|
|
*
|
|
* The async flow has been broken in the middle of a cursor (This filed is relevant for debug unit
|
|
* #0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_CYP_EN_OLD_0 (13) //!< Bit position for IPU_DP_DEBUG_STAT_CYP_EN_OLD_0.
|
|
#define BM_IPU_DP_DEBUG_STAT_CYP_EN_OLD_0 (0x00002000) //!< Bit mask for IPU_DP_DEBUG_STAT_CYP_EN_OLD_0.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_CYP_EN_OLD_0 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_CYP_EN_OLD_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_CYP_EN_OLD_0) >> BP_IPU_DP_DEBUG_STAT_CYP_EN_OLD_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field V_CNT_OLD_1[26:16] (RO)
|
|
*
|
|
* The exact row where the async flow has been broken (This filed is relevant for debug unit #0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_V_CNT_OLD_1 (16) //!< Bit position for IPU_DP_DEBUG_STAT_V_CNT_OLD_1.
|
|
#define BM_IPU_DP_DEBUG_STAT_V_CNT_OLD_1 (0x07ff0000) //!< Bit mask for IPU_DP_DEBUG_STAT_V_CNT_OLD_1.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_V_CNT_OLD_1 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_V_CNT_OLD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_V_CNT_OLD_1) >> BP_IPU_DP_DEBUG_STAT_V_CNT_OLD_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field FG_ACTIVE_1[27] (RO)
|
|
*
|
|
* Displaying the partial frame has been started (This filed is relevant for debug unit #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_FG_ACTIVE_1 (27) //!< Bit position for IPU_DP_DEBUG_STAT_FG_ACTIVE_1.
|
|
#define BM_IPU_DP_DEBUG_STAT_FG_ACTIVE_1 (0x08000000) //!< Bit mask for IPU_DP_DEBUG_STAT_FG_ACTIVE_1.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_FG_ACTIVE_1 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_FG_ACTIVE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_FG_ACTIVE_1) >> BP_IPU_DP_DEBUG_STAT_FG_ACTIVE_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field COMBYP_EN_OLD_1[28] (RO)
|
|
*
|
|
* the async1 flow has been broken in the middle of combining (This filed is relevant for debug unit
|
|
* #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1 (28) //!< Bit position for IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1.
|
|
#define BM_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1 (0x10000000) //!< Bit mask for IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1) >> BP_IPU_DP_DEBUG_STAT_COMBYP_EN_OLD_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_DEBUG_STAT, field CYP_EN_OLD_1[29] (RO)
|
|
*
|
|
* The async flow has been broken in the middle of a cursor (This filed is relevant for debug unit
|
|
* #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_DEBUG_STAT_CYP_EN_OLD_1 (29) //!< Bit position for IPU_DP_DEBUG_STAT_CYP_EN_OLD_1.
|
|
#define BM_IPU_DP_DEBUG_STAT_CYP_EN_OLD_1 (0x20000000) //!< Bit mask for IPU_DP_DEBUG_STAT_CYP_EN_OLD_1.
|
|
|
|
//! @brief Get value of IPU_DP_DEBUG_STAT_CYP_EN_OLD_1 from a register value.
|
|
#define BG_IPU_DP_DEBUG_STAT_CYP_EN_OLD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_DEBUG_STAT_CYP_EN_OLD_1) >> BP_IPU_DP_DEBUG_STAT_CYP_EN_OLD_1)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_FG_POS_ASYNC1 - DP Partial Plane Window Position Async 1 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_FG_POS_ASYNC1 - DP Partial Plane Window Position Async 1 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The DP partial plane Window Position Register is used to determine the starting position of the
|
|
* partial plane window relative to BG window position. This Register is used for the synchronous
|
|
* flow only.
|
|
*/
|
|
typedef union _hw_ipu_dp_fg_pos_async1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_fg_pos_async1_bitfields
|
|
{
|
|
unsigned DP_FGYP_ASYNC1 : 11; //!< [10:0] FGYP partial plane window Y position
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned DP_FGXP_ASYNC1 : 11; //!< [26:16] FGXP partial plane Window X Position.
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved
|
|
} B;
|
|
} hw_ipu_dp_fg_pos_async1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_FG_POS_ASYNC1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_FG_POS_ASYNC1_ADDR(x) (REGS_IPU_BASE(x) + 0x180c4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_FG_POS_ASYNC1(x) (*(volatile hw_ipu_dp_fg_pos_async1_t *) HW_IPU_DP_FG_POS_ASYNC1_ADDR(x))
|
|
#define HW_IPU_DP_FG_POS_ASYNC1_RD(x) (HW_IPU_DP_FG_POS_ASYNC1(x).U)
|
|
#define HW_IPU_DP_FG_POS_ASYNC1_WR(x, v) (HW_IPU_DP_FG_POS_ASYNC1(x).U = (v))
|
|
#define HW_IPU_DP_FG_POS_ASYNC1_SET(x, v) (HW_IPU_DP_FG_POS_ASYNC1_WR(x, HW_IPU_DP_FG_POS_ASYNC1_RD(x) | (v)))
|
|
#define HW_IPU_DP_FG_POS_ASYNC1_CLR(x, v) (HW_IPU_DP_FG_POS_ASYNC1_WR(x, HW_IPU_DP_FG_POS_ASYNC1_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_FG_POS_ASYNC1_TOG(x, v) (HW_IPU_DP_FG_POS_ASYNC1_WR(x, HW_IPU_DP_FG_POS_ASYNC1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_FG_POS_ASYNC1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_FG_POS_ASYNC1, field DP_FGYP_ASYNC1[10:0] (RW)
|
|
*
|
|
* FGYP partial plane window Y position partial plane Window Y Position - Specifies the number of
|
|
* lines between the start of full plane windows Y position and the beginning of the first data.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1 (0) //!< Bit position for IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1.
|
|
#define BM_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1 (0x000007ff) //!< Bit mask for IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1) >> BP_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1.
|
|
#define BF_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1) & BM_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FGYP_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1(x, v) (HW_IPU_DP_FG_POS_ASYNC1_WR(x, (HW_IPU_DP_FG_POS_ASYNC1_RD(x) & ~BM_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1) | BF_IPU_DP_FG_POS_ASYNC1_DP_FGYP_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_FG_POS_ASYNC1, field DP_FGXP_ASYNC1[26:16] (RW)
|
|
*
|
|
* FGXP partial plane Window X Position. partial plane Window X Position - Specifies the number of
|
|
* pixels between the start of full plane window X position and the beginning of the first data of
|
|
* new line.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1 (16) //!< Bit position for IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1.
|
|
#define BM_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1 (0x07ff0000) //!< Bit mask for IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1) >> BP_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1.
|
|
#define BF_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1) & BM_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_FGXP_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1(x, v) (HW_IPU_DP_FG_POS_ASYNC1_WR(x, (HW_IPU_DP_FG_POS_ASYNC1_RD(x) & ~BM_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1) | BF_IPU_DP_FG_POS_ASYNC1_DP_FGXP_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CUR_POS_ASYNC1 - DP Cursor Postion and Size Async 1 Flow Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CUR_POS_ASYNC1 - DP Cursor Postion and Size Async 1 Flow Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The LCD Cursor Position Register is used to determine the starting position of the cursor
|
|
* relative to BG windows position.
|
|
*/
|
|
typedef union _hw_ipu_dp_cur_pos_async1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_cur_pos_async1_bitfields
|
|
{
|
|
unsigned DP_CXW_ASYNC1 : 11; //!< [10:0] CXW - Cursor Width.
|
|
unsigned DP_CXP_ASYNC1 : 5; //!< [15:11] CXP - Cursor X Position
|
|
unsigned DP_CYH_ASYNC1 : 11; //!< [26:16] CYH - Cursor Height
|
|
unsigned DP_CYP_ASYNC1 : 5; //!< [31:27] CYP - Cursor Y Position
|
|
} B;
|
|
} hw_ipu_dp_cur_pos_async1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CUR_POS_ASYNC1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1_ADDR(x) (REGS_IPU_BASE(x) + 0x180c8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1(x) (*(volatile hw_ipu_dp_cur_pos_async1_t *) HW_IPU_DP_CUR_POS_ASYNC1_ADDR(x))
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1_RD(x) (HW_IPU_DP_CUR_POS_ASYNC1(x).U)
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1_WR(x, v) (HW_IPU_DP_CUR_POS_ASYNC1(x).U = (v))
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1_SET(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, HW_IPU_DP_CUR_POS_ASYNC1_RD(x) | (v)))
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1_CLR(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, HW_IPU_DP_CUR_POS_ASYNC1_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CUR_POS_ASYNC1_TOG(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, HW_IPU_DP_CUR_POS_ASYNC1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CUR_POS_ASYNC1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CUR_POS_ASYNC1, field DP_CXW_ASYNC1[10:0] (RW)
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*
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* CXW - Cursor Width. Specifies the width of the hardware cursor in pixels.
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*/
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//@{
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#define BP_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1 (0) //!< Bit position for IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1.
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#define BM_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1 (0x000007ff) //!< Bit mask for IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1.
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//! @brief Get value of IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1 from a register value.
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#define BG_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1) >> BP_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1.
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#define BF_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CXW_ASYNC1 field to a new value.
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#define BW_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, (HW_IPU_DP_CUR_POS_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1) | BF_IPU_DP_CUR_POS_ASYNC1_DP_CXW_ASYNC1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CUR_POS_ASYNC1, field DP_CXP_ASYNC1[15:11] (RW)
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*
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* CXP - Cursor X Position Represents the cursors horizontal starting position X in pixel count
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* (from 0 to CXW).
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*/
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//@{
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#define BP_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1 (11) //!< Bit position for IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1.
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#define BM_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1 (0x0000f800) //!< Bit mask for IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1.
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//! @brief Get value of IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1 from a register value.
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#define BG_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1) >> BP_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1.
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#define BF_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CXP_ASYNC1 field to a new value.
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#define BW_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, (HW_IPU_DP_CUR_POS_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1) | BF_IPU_DP_CUR_POS_ASYNC1_DP_CXP_ASYNC1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CUR_POS_ASYNC1, field DP_CYH_ASYNC1[26:16] (RW)
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*
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* CYH - Cursor Height Specifies the height of the hardware cursor in pixels.
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*/
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//@{
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#define BP_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1 (16) //!< Bit position for IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1.
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#define BM_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1 (0x07ff0000) //!< Bit mask for IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1.
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//! @brief Get value of IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1 from a register value.
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#define BG_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1) >> BP_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1.
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#define BF_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CYH_ASYNC1 field to a new value.
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#define BW_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, (HW_IPU_DP_CUR_POS_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1) | BF_IPU_DP_CUR_POS_ASYNC1_DP_CYH_ASYNC1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CUR_POS_ASYNC1, field DP_CYP_ASYNC1[31:27] (RW)
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*
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* CYP - Cursor Y Position Represents the cursors vertical starting position Y in pixel count (from
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|
* 0 to CYH).Live View Resolution Mode.
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*/
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//@{
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|
#define BP_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1 (27) //!< Bit position for IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1.
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#define BM_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1 (0xf8000000) //!< Bit mask for IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1.
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//! @brief Get value of IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1 from a register value.
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#define BG_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1) >> BP_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1.
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#define BF_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1) & BM_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CYP_ASYNC1 field to a new value.
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|
#define BW_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1(x, v) (HW_IPU_DP_CUR_POS_ASYNC1_WR(x, (HW_IPU_DP_CUR_POS_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1) | BF_IPU_DP_CUR_POS_ASYNC1_DP_CYP_ASYNC1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_CUR_MAP_ASYNC1 - DP Color Cursor Mapping Async 1 Flow Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_DP_CUR_MAP_ASYNC1 - DP Color Cursor Mapping Async 1 Flow Register (RW)
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*
|
|
* Reset value: 0x00000000
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|
*
|
|
* The LCD Color Cursor Mapping Register defines the color of the cursor in passive or TFT color
|
|
* modes.
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|
*/
|
|
typedef union _hw_ipu_dp_cur_map_async1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_cur_map_async1_bitfields
|
|
{
|
|
unsigned DP_CUR_COL_R_ASYNC1 : 8; //!< [7:0] CUR_COL_R - Cursor Red Field
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|
unsigned DP_CUR_COL_G_ASYNC1 : 8; //!< [15:8] CUR_COL_G - Cursor Green Field
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|
unsigned DP_CUR_COL_B_ASYNC1 : 8; //!< [23:16] CUR_COL_B - Cursor Blue Field
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|
unsigned RESERVED0 : 8; //!< [31:24] Reserved
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|
} B;
|
|
} hw_ipu_dp_cur_map_async1_t;
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|
#endif
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|
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/*!
|
|
* @name Constants and macros for entire IPU_DP_CUR_MAP_ASYNC1 register
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|
*/
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//@{
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC1_ADDR(x) (REGS_IPU_BASE(x) + 0x180cc)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CUR_MAP_ASYNC1(x) (*(volatile hw_ipu_dp_cur_map_async1_t *) HW_IPU_DP_CUR_MAP_ASYNC1_ADDR(x))
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#define HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) (HW_IPU_DP_CUR_MAP_ASYNC1(x).U)
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#define HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1(x).U = (v))
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#define HW_IPU_DP_CUR_MAP_ASYNC1_SET(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) | (v)))
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#define HW_IPU_DP_CUR_MAP_ASYNC1_CLR(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) & ~(v)))
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#define HW_IPU_DP_CUR_MAP_ASYNC1_TOG(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
|
|
* constants & macros for individual IPU_DP_CUR_MAP_ASYNC1 bitfields
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|
*/
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/*! @name Register IPU_DP_CUR_MAP_ASYNC1, field DP_CUR_COL_R_ASYNC1[7:0] (RW)
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|
*
|
|
* CUR_COL_R - Cursor Red Field Defines the Red component of the cursor color in color mode
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|
*
|
|
* Values:
|
|
* - 00000000 - No Red.
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|
* - 11111111 - Full Red.
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|
*/
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|
//@{
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|
#define BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1 (0) //!< Bit position for IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1.
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#define BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1 (0x000000ff) //!< Bit mask for IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1.
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|
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//! @brief Get value of IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1 from a register value.
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|
#define BG_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1) >> BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1.
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|
#define BF_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1) & BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_R_ASYNC1 field to a new value.
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|
#define BW_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, (HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1) | BF_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_R_ASYNC1(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DP_CUR_MAP_ASYNC1, field DP_CUR_COL_G_ASYNC1[15:8] (RW)
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|
*
|
|
* CUR_COL_G - Cursor Green Field Defines the Green component of the cursor color in color mode
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|
*
|
|
* Values:
|
|
* - 00000000 - No Green.
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|
* - 11111111 - Full Green.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1 (8) //!< Bit position for IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1.
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|
#define BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1 (0x0000ff00) //!< Bit mask for IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1.
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|
|
//! @brief Get value of IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1 from a register value.
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|
#define BG_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1) >> BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1)
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|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1.
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|
#define BF_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1) & BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_G_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, (HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1) | BF_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_G_ASYNC1(v)))
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|
#endif
|
|
//@}
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|
|
/*! @name Register IPU_DP_CUR_MAP_ASYNC1, field DP_CUR_COL_B_ASYNC1[23:16] (RW)
|
|
*
|
|
* CUR_COL_B - Cursor Blue Field Defines the Blue component of the cursor color in color mode
|
|
*
|
|
* Values:
|
|
* - 00000000 - No Blue.
|
|
* - 11111111 - Full Blue.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1 (16) //!< Bit position for IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1.
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|
#define BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1 (0x00ff0000) //!< Bit mask for IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1.
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|
|
|
//! @brief Get value of IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1 from a register value.
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|
#define BG_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1) >> BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1.
|
|
#define BF_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1) & BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CUR_COL_B_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1(x, v) (HW_IPU_DP_CUR_MAP_ASYNC1_WR(x, (HW_IPU_DP_CUR_MAP_ASYNC1_RD(x) & ~BM_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1) | BF_IPU_DP_CUR_MAP_ASYNC1_DP_CUR_COL_B_ASYNC1(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_GAMMA_C_ASYNC1_I - DP Gamma Constants Async 1 Flow Register i
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_GAMMA_C_ASYNC1_I - DP Gamma Constants Async 1 Flow Register i (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This registers contains CONSTANTi parameters used for gamma correction inside the display
|
|
* processor (DP).
|
|
*/
|
|
typedef union _hw_ipu_dp_gamma_c_async1_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_gamma_c_async1_i_bitfields
|
|
{
|
|
unsigned DP_GAMMA_C_ASYNC1_2I : 9; //!< [8:0] CONSTANTi parameter of Gamma Correction.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DP_GAMMA_C_ASYNC1_2I_1 : 9; //!< [24:16] CONSTANTi+1 parameter of Gamma Correction.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_dp_gamma_c_async1_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_GAMMA_C_ASYNC1_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I_ADDR(x) (REGS_IPU_BASE(x) + 0x180d0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I(x) (*(volatile hw_ipu_dp_gamma_c_async1_i_t *) HW_IPU_DP_GAMMA_C_ASYNC1_I_ADDR(x))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I_RD(x) (HW_IPU_DP_GAMMA_C_ASYNC1_I(x).U)
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I_WR(x, v) (HW_IPU_DP_GAMMA_C_ASYNC1_I(x).U = (v))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I_SET(x, v) (HW_IPU_DP_GAMMA_C_ASYNC1_I_WR(x, HW_IPU_DP_GAMMA_C_ASYNC1_I_RD(x) | (v)))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I_CLR(x, v) (HW_IPU_DP_GAMMA_C_ASYNC1_I_WR(x, HW_IPU_DP_GAMMA_C_ASYNC1_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_GAMMA_C_ASYNC1_I_TOG(x, v) (HW_IPU_DP_GAMMA_C_ASYNC1_I_WR(x, HW_IPU_DP_GAMMA_C_ASYNC1_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_GAMMA_C_ASYNC1_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_GAMMA_C_ASYNC1_I, field DP_GAMMA_C_ASYNC1_2I[8:0] (RW)
|
|
*
|
|
* CONSTANTi parameter of Gamma Correction.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I (0) //!< Bit position for IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I.
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|
#define BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I (0x000001ff) //!< Bit mask for IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I.
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//! @brief Get value of IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I from a register value.
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#define BG_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I) >> BP_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I)
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//! @brief Format value for bitfield IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I.
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#define BF_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I) & BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_C_ASYNC1_2I field to a new value.
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#define BW_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I(x, v) (HW_IPU_DP_GAMMA_C_ASYNC1_I_WR(x, (HW_IPU_DP_GAMMA_C_ASYNC1_I_RD(x) & ~BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I) | BF_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_C_ASYNC1_I, field DP_GAMMA_C_ASYNC1_2I_1[24:16] (RW)
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*
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* CONSTANTi+1 parameter of Gamma Correction.
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*/
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//@{
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#define BP_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1 (16) //!< Bit position for IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1.
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#define BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1 (0x01ff0000) //!< Bit mask for IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1.
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//! @brief Get value of IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1 from a register value.
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#define BG_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1) >> BP_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1)
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//! @brief Format value for bitfield IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1.
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#define BF_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1) & BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_C_ASYNC1_2I_1 field to a new value.
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#define BW_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1(x, v) (HW_IPU_DP_GAMMA_C_ASYNC1_I_WR(x, (HW_IPU_DP_GAMMA_C_ASYNC1_I_RD(x) & ~BM_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1) | BF_IPU_DP_GAMMA_C_ASYNC1_I_DP_GAMMA_C_ASYNC1_2I_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_GAMMA_S_ASYN1_I - DP Gamma Correction Slope Async 1 Flow Register i
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DP_GAMMA_S_ASYN1_I - DP Gamma Correction Slope Async 1 Flow Register i (RW)
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*
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* Reset value: 0x00000000
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*
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* This registers contains SLOPEi parameters used for Gamma Correction inside the display processor
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* (DP).
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*/
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typedef union _hw_ipu_dp_gamma_s_asyn1_i
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{
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reg32_t U;
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struct _hw_ipu_dp_gamma_s_asyn1_i_bitfields
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{
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unsigned DP_GAMMA_S_ASYNC1_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Gamma Correction.
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unsigned DP_GAMMA_S_ASYNC1_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Gamma Correction.
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unsigned DP_GAMMA_S_ASYNC1_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Gamma Correction.
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unsigned DP_GAMMA_S_ASYNC1_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Gamma Correction.
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} B;
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} hw_ipu_dp_gamma_s_asyn1_i_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DP_GAMMA_S_ASYN1_I register
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*/
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//@{
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#define HW_IPU_DP_GAMMA_S_ASYN1_I_ADDR(x) (REGS_IPU_BASE(x) + 0x180f0)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DP_GAMMA_S_ASYN1_I(x) (*(volatile hw_ipu_dp_gamma_s_asyn1_i_t *) HW_IPU_DP_GAMMA_S_ASYN1_I_ADDR(x))
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#define HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) (HW_IPU_DP_GAMMA_S_ASYN1_I(x).U)
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#define HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I(x).U = (v))
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#define HW_IPU_DP_GAMMA_S_ASYN1_I_SET(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) | (v)))
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#define HW_IPU_DP_GAMMA_S_ASYN1_I_CLR(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) & ~(v)))
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#define HW_IPU_DP_GAMMA_S_ASYN1_I_TOG(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DP_GAMMA_S_ASYN1_I bitfields
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*/
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/*! @name Register IPU_DP_GAMMA_S_ASYN1_I, field DP_GAMMA_S_ASYNC1_4I[7:0] (RW)
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*
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* SLOPE<4*i> parameter of Gamma Correction.
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*/
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//@{
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#define BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I (0) //!< Bit position for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I.
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#define BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I (0x000000ff) //!< Bit mask for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I from a register value.
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#define BG_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I) >> BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I.
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#define BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_S_ASYNC1_4I field to a new value.
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#define BW_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I) | BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_S_ASYN1_I, field DP_GAMMA_S_ASYNC1_4I_1[15:8] (RW)
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*
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* SLOPE<4*i+1> parameter of Gamma Correction.
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*/
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//@{
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#define BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1 (8) //!< Bit position for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1.
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#define BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1 (0x0000ff00) //!< Bit mask for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1 from a register value.
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#define BG_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1) >> BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1.
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#define BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_S_ASYNC1_4I_1 field to a new value.
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#define BW_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1) | BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_S_ASYN1_I, field DP_GAMMA_S_ASYNC1_4I_2[23:16] (RW)
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*
|
|
* SLOPE<4*i+2> parameter of Gamma Correction.
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*/
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//@{
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|
#define BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2 (16) //!< Bit position for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2.
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#define BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2 (0x00ff0000) //!< Bit mask for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2 from a register value.
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#define BG_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2) >> BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2.
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#define BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_GAMMA_S_ASYNC1_4I_2 field to a new value.
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#define BW_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2) | BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_GAMMA_S_ASYN1_I, field DP_GAMMA_S_ASYNC1_4I_3[31:24] (RW)
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|
*
|
|
* SLOPE<4*i+3> parameter of Gamma Correction.
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3 (24) //!< Bit position for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3.
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#define BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3 (0xff000000) //!< Bit mask for IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3.
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//! @brief Get value of IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3 from a register value.
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#define BG_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3) >> BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3)
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//! @brief Format value for bitfield IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3.
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#define BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3) & BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DP_GAMMA_S_ASYNC1_4I_3 field to a new value.
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|
#define BW_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3(x, v) (HW_IPU_DP_GAMMA_S_ASYN1_I_WR(x, (HW_IPU_DP_GAMMA_S_ASYN1_I_RD(x) & ~BM_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3) | BF_IPU_DP_GAMMA_S_ASYN1_I_DP_GAMMA_S_ASYNC1_4I_3(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CSCA_ASYNC1_I - DP Color Space Converstion Control Async 1 Flow Register i
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CSCA_ASYNC1_I - DP Color Space Converstion Control Async 1 Flow Register i (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_csca_async1_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_csca_async1_i_bitfields
|
|
{
|
|
unsigned DP_CSC_A_ASYNC1_2I : 10; //!< [9:0] A<2*i> parameter of color conversion.
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved.
|
|
unsigned DP_CSC_A_ASYNC1_2I_1 : 10; //!< [25:16] A<2*i+1> parameter of color conversion.
|
|
unsigned RESERVED1 : 6; //!< [31:26] Reserved.
|
|
} B;
|
|
} hw_ipu_dp_csca_async1_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CSCA_ASYNC1_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I_ADDR(x) (REGS_IPU_BASE(x) + 0x18100)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I(x) (*(volatile hw_ipu_dp_csca_async1_i_t *) HW_IPU_DP_CSCA_ASYNC1_I_ADDR(x))
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I_RD(x) (HW_IPU_DP_CSCA_ASYNC1_I(x).U)
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I_WR(x, v) (HW_IPU_DP_CSCA_ASYNC1_I(x).U = (v))
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I_SET(x, v) (HW_IPU_DP_CSCA_ASYNC1_I_WR(x, HW_IPU_DP_CSCA_ASYNC1_I_RD(x) | (v)))
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I_CLR(x, v) (HW_IPU_DP_CSCA_ASYNC1_I_WR(x, HW_IPU_DP_CSCA_ASYNC1_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DP_CSCA_ASYNC1_I_TOG(x, v) (HW_IPU_DP_CSCA_ASYNC1_I_WR(x, HW_IPU_DP_CSCA_ASYNC1_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CSCA_ASYNC1_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CSCA_ASYNC1_I, field DP_CSC_A_ASYNC1_2I[9:0] (RW)
|
|
*
|
|
* A<2*i> parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I (0) //!< Bit position for IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I.
|
|
#define BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I (0x000003ff) //!< Bit mask for IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I.
|
|
|
|
//! @brief Get value of IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I from a register value.
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|
#define BG_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I) >> BP_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I)
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//! @brief Format value for bitfield IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I.
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#define BF_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I) & BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_A_ASYNC1_2I field to a new value.
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#define BW_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I(x, v) (HW_IPU_DP_CSCA_ASYNC1_I_WR(x, (HW_IPU_DP_CSCA_ASYNC1_I_RD(x) & ~BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I) | BF_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CSCA_ASYNC1_I, field DP_CSC_A_ASYNC1_2I_1[25:16] (RW)
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*
|
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* A<2*i+1> parameter of color conversion.
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*/
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//@{
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|
#define BP_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1 (16) //!< Bit position for IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1.
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#define BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1 (0x03ff0000) //!< Bit mask for IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1.
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//! @brief Get value of IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1 from a register value.
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#define BG_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1) >> BP_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1)
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//! @brief Format value for bitfield IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1.
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#define BF_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1) & BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_A_ASYNC1_2I_1 field to a new value.
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#define BW_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1(x, v) (HW_IPU_DP_CSCA_ASYNC1_I_WR(x, (HW_IPU_DP_CSCA_ASYNC1_I_RD(x) & ~BM_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1) | BF_IPU_DP_CSCA_ASYNC1_I_DP_CSC_A_ASYNC1_2I_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DP_CSC_ASYNC1_0 - DP Color Conversion Control Async 1 Flow Register 0
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DP_CSC_ASYNC1_0 - DP Color Conversion Control Async 1 Flow Register 0 (RW)
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*
|
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dp_csc_async1_0
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{
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reg32_t U;
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struct _hw_ipu_dp_csc_async1_0_bitfields
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{
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unsigned DP_CSC_A8_ASYNC1 : 10; //!< [9:0] A9 parameter of color conversion.
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unsigned RESERVED0 : 6; //!< [15:10] Reserved.
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unsigned DP_CSC_B0_ASYNC1 : 14; //!< [29:16] B0 parameter of color conversion.
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unsigned DP_CSC_S0_ASYNC1 : 2; //!< [31:30] S0 parameter of color conversion.
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} B;
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} hw_ipu_dp_csc_async1_0_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DP_CSC_ASYNC1_0 register
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*/
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//@{
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#define HW_IPU_DP_CSC_ASYNC1_0_ADDR(x) (REGS_IPU_BASE(x) + 0x18110)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DP_CSC_ASYNC1_0(x) (*(volatile hw_ipu_dp_csc_async1_0_t *) HW_IPU_DP_CSC_ASYNC1_0_ADDR(x))
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#define HW_IPU_DP_CSC_ASYNC1_0_RD(x) (HW_IPU_DP_CSC_ASYNC1_0(x).U)
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#define HW_IPU_DP_CSC_ASYNC1_0_WR(x, v) (HW_IPU_DP_CSC_ASYNC1_0(x).U = (v))
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#define HW_IPU_DP_CSC_ASYNC1_0_SET(x, v) (HW_IPU_DP_CSC_ASYNC1_0_WR(x, HW_IPU_DP_CSC_ASYNC1_0_RD(x) | (v)))
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#define HW_IPU_DP_CSC_ASYNC1_0_CLR(x, v) (HW_IPU_DP_CSC_ASYNC1_0_WR(x, HW_IPU_DP_CSC_ASYNC1_0_RD(x) & ~(v)))
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#define HW_IPU_DP_CSC_ASYNC1_0_TOG(x, v) (HW_IPU_DP_CSC_ASYNC1_0_WR(x, HW_IPU_DP_CSC_ASYNC1_0_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DP_CSC_ASYNC1_0 bitfields
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|
*/
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/*! @name Register IPU_DP_CSC_ASYNC1_0, field DP_CSC_A8_ASYNC1[9:0] (RW)
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*
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* A9 parameter of color conversion.
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*/
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//@{
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#define BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1 (0) //!< Bit position for IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1.
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#define BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1 (0x000003ff) //!< Bit mask for IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1.
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//! @brief Get value of IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1 from a register value.
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#define BG_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1.
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#define BF_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_A8_ASYNC1 field to a new value.
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#define BW_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_0_WR(x, (HW_IPU_DP_CSC_ASYNC1_0_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_0_DP_CSC_A8_ASYNC1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CSC_ASYNC1_0, field DP_CSC_B0_ASYNC1[29:16] (RW)
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|
*
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|
* B0 parameter of color conversion.
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|
*/
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|
//@{
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|
#define BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1 (16) //!< Bit position for IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1.
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#define BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1 (0x3fff0000) //!< Bit mask for IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1.
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//! @brief Get value of IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1 from a register value.
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#define BG_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1.
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#define BF_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DP_CSC_B0_ASYNC1 field to a new value.
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#define BW_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_0_WR(x, (HW_IPU_DP_CSC_ASYNC1_0_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_0_DP_CSC_B0_ASYNC1(v)))
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#endif
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//@}
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/*! @name Register IPU_DP_CSC_ASYNC1_0, field DP_CSC_S0_ASYNC1[31:30] (RW)
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|
*
|
|
* S0 parameter of color conversion.
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|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
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|
* - 01 - scale factor of 1
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|
* - 10 - scale factor of 0
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|
* - 11 - scale factor of -1
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|
*/
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|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1 (30) //!< Bit position for IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1.
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#define BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1 (0xc0000000) //!< Bit mask for IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1.
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|
//! @brief Get value of IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1 from a register value.
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|
#define BG_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1)
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1.
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#define BF_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S0_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_0_WR(x, (HW_IPU_DP_CSC_ASYNC1_0_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_0_DP_CSC_S0_ASYNC1(v)))
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#endif
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//@}
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|
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|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DP_CSC_ASYNC1_1 - DP Color Conversion Control Async 1 Flow Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DP_CSC_ASYNC1_1 - DP Color Conversion Control Async 1 Flow Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dp_csc_async1_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dp_csc_async1_1_bitfields
|
|
{
|
|
unsigned DP_CSC_B1_ASYNC1 : 14; //!< [13:0] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S1_ASYNC1 : 2; //!< [15:14] S0 parameter of color conversion.
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|
unsigned DP_CSC_B2_ASYNC1 : 14; //!< [29:16] B0 parameter of color conversion.
|
|
unsigned DP_CSC_S2_ASYNC1 : 2; //!< [31:30] S0 parameter of color conversion.
|
|
} B;
|
|
} hw_ipu_dp_csc_async1_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DP_CSC_ASYNC1_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DP_CSC_ASYNC1_1_ADDR(x) (REGS_IPU_BASE(x) + 0x18114)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DP_CSC_ASYNC1_1(x) (*(volatile hw_ipu_dp_csc_async1_1_t *) HW_IPU_DP_CSC_ASYNC1_1_ADDR(x))
|
|
#define HW_IPU_DP_CSC_ASYNC1_1_RD(x) (HW_IPU_DP_CSC_ASYNC1_1(x).U)
|
|
#define HW_IPU_DP_CSC_ASYNC1_1_WR(x, v) (HW_IPU_DP_CSC_ASYNC1_1(x).U = (v))
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|
#define HW_IPU_DP_CSC_ASYNC1_1_SET(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, HW_IPU_DP_CSC_ASYNC1_1_RD(x) | (v)))
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|
#define HW_IPU_DP_CSC_ASYNC1_1_CLR(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, HW_IPU_DP_CSC_ASYNC1_1_RD(x) & ~(v)))
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|
#define HW_IPU_DP_CSC_ASYNC1_1_TOG(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, HW_IPU_DP_CSC_ASYNC1_1_RD(x) ^ (v)))
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|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DP_CSC_ASYNC1_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC1_1, field DP_CSC_B1_ASYNC1[13:0] (RW)
|
|
*
|
|
* B0 parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1 (0) //!< Bit position for IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1.
|
|
#define BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1 (0x00003fff) //!< Bit mask for IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1.
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|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1.
|
|
#define BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B1_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, (HW_IPU_DP_CSC_ASYNC1_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_B1_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC1_1, field DP_CSC_S1_ASYNC1[15:14] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0 11 scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1 (14) //!< Bit position for IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1.
|
|
#define BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1 (0x0000c000) //!< Bit mask for IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1)
|
|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1.
|
|
#define BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S1_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, (HW_IPU_DP_CSC_ASYNC1_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_S1_ASYNC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DP_CSC_ASYNC1_1, field DP_CSC_B2_ASYNC1[29:16] (RW)
|
|
*
|
|
* B0 parameter of color conversion.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1 (16) //!< Bit position for IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1.
|
|
#define BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1 (0x3fff0000) //!< Bit mask for IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1.
|
|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1)
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|
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//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1.
|
|
#define BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_B2_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, (HW_IPU_DP_CSC_ASYNC1_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_B2_ASYNC1(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DP_CSC_ASYNC1_1, field DP_CSC_S2_ASYNC1[31:30] (RW)
|
|
*
|
|
* S0 parameter of color conversion.
|
|
*
|
|
* Values:
|
|
* - 00 - scale factor of 2
|
|
* - 01 - scale factor of 1
|
|
* - 10 - scale factor of 0 11 scale factor of -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1 (30) //!< Bit position for IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1.
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|
#define BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1 (0xc0000000) //!< Bit mask for IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1.
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|
|
|
//! @brief Get value of IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1 from a register value.
|
|
#define BG_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1) >> BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1)
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|
|
|
//! @brief Format value for bitfield IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1.
|
|
#define BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1) & BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DP_CSC_S2_ASYNC1 field to a new value.
|
|
#define BW_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1(x, v) (HW_IPU_DP_CSC_ASYNC1_1_WR(x, (HW_IPU_DP_CSC_ASYNC1_1_RD(x) & ~BM_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1) | BF_IPU_DP_CSC_ASYNC1_1_DP_CSC_S2_ASYNC1(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_CONF - IC Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_CONF - IC Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contains control parameter for IC 3 tasks (pre-processing for encoding, pre-
|
|
* processing for view-finder and post processing).
|
|
*/
|
|
typedef union _hw_ipu_ic_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_conf_bitfields
|
|
{
|
|
unsigned PRPENC_EN : 1; //!< [0] Preprocessing Task for encoding enable.
|
|
unsigned PRPENC_CSC1 : 1; //!< [1] Preprocessing Task for encoding color conversion enable.
|
|
unsigned PRPENC_ROT_EN : 1; //!< [2] Preprocessing Rotation Task for encoding enable.
|
|
unsigned RESERVED0 : 5; //!< [7:3] Reserved
|
|
unsigned PRPVF_EN : 1; //!< [8] Preprocessing Task for View-Finder enable.
|
|
unsigned PRPVF_CSC1 : 1; //!< [9] Pre-processing task for view-finder first color conversion enable.
|
|
unsigned PRPVF_CSC2 : 1; //!< [10] Reserved
|
|
unsigned PRPVF_CMB : 1; //!< [11] Preprocessing Task for View-Finder combining enable.
|
|
unsigned PRPVF_ROT_EN : 1; //!< [12] Preprocessing Rotation Task for viewfinder enable.
|
|
unsigned RESERVED1 : 3; //!< [15:13] Reserved
|
|
unsigned PP_EN : 1; //!< [16] Post-Processing Task enable.
|
|
unsigned PP_CSC1 : 1; //!< [17] Post-Processing Task color conversion YUV-->RGB enable.
|
|
unsigned PP_CSC2 : 1; //!< [18] Post-Processing Task color conversion RGB-->YUV enable.
|
|
unsigned PP_CMB : 1; //!< [19] Post-Processing Task combining enable.
|
|
unsigned PP_ROT_EN : 1; //!< [20] Post-Processing Rotation Task enable.
|
|
unsigned RESERVED2 : 7; //!< [27:21] Reserved
|
|
unsigned IC_GLB_LOC_A : 1; //!< [28] Global Alpha.
|
|
unsigned IC_KEY_COLOR_EN : 1; //!< [29] Key Color enable.
|
|
unsigned RWS_EN : 1; //!< [30] Raw sensor enable.
|
|
unsigned CSI_MEM_WR_EN : 1; //!< [31] CSI direct memory write enable.
|
|
} B;
|
|
} hw_ipu_ic_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x20000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_CONF(x) (*(volatile hw_ipu_ic_conf_t *) HW_IPU_IC_CONF_ADDR(x))
|
|
#define HW_IPU_IC_CONF_RD(x) (HW_IPU_IC_CONF(x).U)
|
|
#define HW_IPU_IC_CONF_WR(x, v) (HW_IPU_IC_CONF(x).U = (v))
|
|
#define HW_IPU_IC_CONF_SET(x, v) (HW_IPU_IC_CONF_WR(x, HW_IPU_IC_CONF_RD(x) | (v)))
|
|
#define HW_IPU_IC_CONF_CLR(x, v) (HW_IPU_IC_CONF_WR(x, HW_IPU_IC_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_CONF_TOG(x, v) (HW_IPU_IC_CONF_WR(x, HW_IPU_IC_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPENC_EN[0] (RW)
|
|
*
|
|
* Preprocessing Task for encoding enable. This bit enables the encoding task.
|
|
*
|
|
* Values:
|
|
* - 0 - Task is disabled.
|
|
* - 1 - Task is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPENC_EN (0) //!< Bit position for IPU_IC_CONF_PRPENC_EN.
|
|
#define BM_IPU_IC_CONF_PRPENC_EN (0x00000001) //!< Bit mask for IPU_IC_CONF_PRPENC_EN.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPENC_EN from a register value.
|
|
#define BG_IPU_IC_CONF_PRPENC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPENC_EN) >> BP_IPU_IC_CONF_PRPENC_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPENC_EN.
|
|
#define BF_IPU_IC_CONF_PRPENC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPENC_EN) & BM_IPU_IC_CONF_PRPENC_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_EN field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPENC_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPENC_EN) | BF_IPU_IC_CONF_PRPENC_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPENC_CSC1[1] (RW)
|
|
*
|
|
* Preprocessing Task for encoding color conversion enable. This bit enables color conversion.
|
|
*
|
|
* Values:
|
|
* - 0 - Color conversion is disabled.
|
|
* - 1 - Color conversion is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPENC_CSC1 (1) //!< Bit position for IPU_IC_CONF_PRPENC_CSC1.
|
|
#define BM_IPU_IC_CONF_PRPENC_CSC1 (0x00000002) //!< Bit mask for IPU_IC_CONF_PRPENC_CSC1.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPENC_CSC1 from a register value.
|
|
#define BG_IPU_IC_CONF_PRPENC_CSC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPENC_CSC1) >> BP_IPU_IC_CONF_PRPENC_CSC1)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPENC_CSC1.
|
|
#define BF_IPU_IC_CONF_PRPENC_CSC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPENC_CSC1) & BM_IPU_IC_CONF_PRPENC_CSC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_CSC1 field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPENC_CSC1(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPENC_CSC1) | BF_IPU_IC_CONF_PRPENC_CSC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPENC_ROT_EN[2] (RW)
|
|
*
|
|
* Preprocessing Rotation Task for encoding enable. This bit enable Preprocessing Rotation Task for
|
|
* encoding.
|
|
*
|
|
* Values:
|
|
* - 0 - Rotation is disabled.
|
|
* - 1 - Rotation is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPENC_ROT_EN (2) //!< Bit position for IPU_IC_CONF_PRPENC_ROT_EN.
|
|
#define BM_IPU_IC_CONF_PRPENC_ROT_EN (0x00000004) //!< Bit mask for IPU_IC_CONF_PRPENC_ROT_EN.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPENC_ROT_EN from a register value.
|
|
#define BG_IPU_IC_CONF_PRPENC_ROT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPENC_ROT_EN) >> BP_IPU_IC_CONF_PRPENC_ROT_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPENC_ROT_EN.
|
|
#define BF_IPU_IC_CONF_PRPENC_ROT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPENC_ROT_EN) & BM_IPU_IC_CONF_PRPENC_ROT_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_ROT_EN field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPENC_ROT_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPENC_ROT_EN) | BF_IPU_IC_CONF_PRPENC_ROT_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPVF_EN[8] (RW)
|
|
*
|
|
* Preprocessing Task for View-Finder enable. This bit enables the View-Finder task.
|
|
*
|
|
* Values:
|
|
* - 0 - Task is disabled.
|
|
* - 1 - Task is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPVF_EN (8) //!< Bit position for IPU_IC_CONF_PRPVF_EN.
|
|
#define BM_IPU_IC_CONF_PRPVF_EN (0x00000100) //!< Bit mask for IPU_IC_CONF_PRPVF_EN.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPVF_EN from a register value.
|
|
#define BG_IPU_IC_CONF_PRPVF_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPVF_EN) >> BP_IPU_IC_CONF_PRPVF_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPVF_EN.
|
|
#define BF_IPU_IC_CONF_PRPVF_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPVF_EN) & BM_IPU_IC_CONF_PRPVF_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_EN field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPVF_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPVF_EN) | BF_IPU_IC_CONF_PRPVF_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPVF_CSC1[9] (RW)
|
|
*
|
|
* Pre-processing task for view-finder first color conversion enable. This bit enables first color
|
|
* conversion.
|
|
*
|
|
* Values:
|
|
* - 0 - First color conversion is disabled.
|
|
* - 1 - First color conversion is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPVF_CSC1 (9) //!< Bit position for IPU_IC_CONF_PRPVF_CSC1.
|
|
#define BM_IPU_IC_CONF_PRPVF_CSC1 (0x00000200) //!< Bit mask for IPU_IC_CONF_PRPVF_CSC1.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPVF_CSC1 from a register value.
|
|
#define BG_IPU_IC_CONF_PRPVF_CSC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPVF_CSC1) >> BP_IPU_IC_CONF_PRPVF_CSC1)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPVF_CSC1.
|
|
#define BF_IPU_IC_CONF_PRPVF_CSC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPVF_CSC1) & BM_IPU_IC_CONF_PRPVF_CSC1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_CSC1 field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPVF_CSC1(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPVF_CSC1) | BF_IPU_IC_CONF_PRPVF_CSC1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPVF_CSC2[10] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPVF_CSC2 (10) //!< Bit position for IPU_IC_CONF_PRPVF_CSC2.
|
|
#define BM_IPU_IC_CONF_PRPVF_CSC2 (0x00000400) //!< Bit mask for IPU_IC_CONF_PRPVF_CSC2.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPVF_CSC2 from a register value.
|
|
#define BG_IPU_IC_CONF_PRPVF_CSC2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPVF_CSC2) >> BP_IPU_IC_CONF_PRPVF_CSC2)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPVF_CSC2.
|
|
#define BF_IPU_IC_CONF_PRPVF_CSC2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPVF_CSC2) & BM_IPU_IC_CONF_PRPVF_CSC2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_CSC2 field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPVF_CSC2(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPVF_CSC2) | BF_IPU_IC_CONF_PRPVF_CSC2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPVF_CMB[11] (RW)
|
|
*
|
|
* Preprocessing Task for View-Finder combining enable. This bit enables combining.
|
|
*
|
|
* Values:
|
|
* - 0 - Combining is disabled.
|
|
* - 1 - Combining is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPVF_CMB (11) //!< Bit position for IPU_IC_CONF_PRPVF_CMB.
|
|
#define BM_IPU_IC_CONF_PRPVF_CMB (0x00000800) //!< Bit mask for IPU_IC_CONF_PRPVF_CMB.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPVF_CMB from a register value.
|
|
#define BG_IPU_IC_CONF_PRPVF_CMB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPVF_CMB) >> BP_IPU_IC_CONF_PRPVF_CMB)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPVF_CMB.
|
|
#define BF_IPU_IC_CONF_PRPVF_CMB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPVF_CMB) & BM_IPU_IC_CONF_PRPVF_CMB)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_CMB field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPVF_CMB(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPVF_CMB) | BF_IPU_IC_CONF_PRPVF_CMB(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PRPVF_ROT_EN[12] (RW)
|
|
*
|
|
* Preprocessing Rotation Task for viewfinder enable. This bit enable Preprocessing Rotation Task
|
|
* for viewfinder.
|
|
*
|
|
* Values:
|
|
* - 0 - Rotation is disabled.
|
|
* - 1 - Rotation is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PRPVF_ROT_EN (12) //!< Bit position for IPU_IC_CONF_PRPVF_ROT_EN.
|
|
#define BM_IPU_IC_CONF_PRPVF_ROT_EN (0x00001000) //!< Bit mask for IPU_IC_CONF_PRPVF_ROT_EN.
|
|
|
|
//! @brief Get value of IPU_IC_CONF_PRPVF_ROT_EN from a register value.
|
|
#define BG_IPU_IC_CONF_PRPVF_ROT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PRPVF_ROT_EN) >> BP_IPU_IC_CONF_PRPVF_ROT_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CONF_PRPVF_ROT_EN.
|
|
#define BF_IPU_IC_CONF_PRPVF_ROT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PRPVF_ROT_EN) & BM_IPU_IC_CONF_PRPVF_ROT_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_ROT_EN field to a new value.
|
|
#define BW_IPU_IC_CONF_PRPVF_ROT_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PRPVF_ROT_EN) | BF_IPU_IC_CONF_PRPVF_ROT_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CONF, field PP_EN[16] (RW)
|
|
*
|
|
* Post-Processing Task enable. This bit enables the Post-Processing task.
|
|
*
|
|
* Values:
|
|
* - 0 - Task is disabled.
|
|
* - 1 - Task is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CONF_PP_EN (16) //!< Bit position for IPU_IC_CONF_PP_EN.
|
|
#define BM_IPU_IC_CONF_PP_EN (0x00010000) //!< Bit mask for IPU_IC_CONF_PP_EN.
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//! @brief Get value of IPU_IC_CONF_PP_EN from a register value.
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#define BG_IPU_IC_CONF_PP_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PP_EN) >> BP_IPU_IC_CONF_PP_EN)
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//! @brief Format value for bitfield IPU_IC_CONF_PP_EN.
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#define BF_IPU_IC_CONF_PP_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PP_EN) & BM_IPU_IC_CONF_PP_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PP_EN field to a new value.
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#define BW_IPU_IC_CONF_PP_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PP_EN) | BF_IPU_IC_CONF_PP_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field PP_CSC1[17] (RW)
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*
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* Post-Processing Task color conversion YUV-->RGB enable. This bit enables YUV-->RGB.
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*
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* Values:
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* - 0 - YUV-->RGB is disabled.
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* - 1 - YUV-->RGB is enabled.
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*/
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//@{
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#define BP_IPU_IC_CONF_PP_CSC1 (17) //!< Bit position for IPU_IC_CONF_PP_CSC1.
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#define BM_IPU_IC_CONF_PP_CSC1 (0x00020000) //!< Bit mask for IPU_IC_CONF_PP_CSC1.
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//! @brief Get value of IPU_IC_CONF_PP_CSC1 from a register value.
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#define BG_IPU_IC_CONF_PP_CSC1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PP_CSC1) >> BP_IPU_IC_CONF_PP_CSC1)
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//! @brief Format value for bitfield IPU_IC_CONF_PP_CSC1.
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#define BF_IPU_IC_CONF_PP_CSC1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PP_CSC1) & BM_IPU_IC_CONF_PP_CSC1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PP_CSC1 field to a new value.
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#define BW_IPU_IC_CONF_PP_CSC1(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PP_CSC1) | BF_IPU_IC_CONF_PP_CSC1(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field PP_CSC2[18] (RW)
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*
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* Post-Processing Task color conversion RGB-->YUV enable. This bit enables YUV-->RGB. Reserved
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*
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* Values:
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* - 0 - RGB-->YUV is disabled.
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* - 1 - RGB-->YUV is enabled.
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*/
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//@{
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#define BP_IPU_IC_CONF_PP_CSC2 (18) //!< Bit position for IPU_IC_CONF_PP_CSC2.
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#define BM_IPU_IC_CONF_PP_CSC2 (0x00040000) //!< Bit mask for IPU_IC_CONF_PP_CSC2.
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//! @brief Get value of IPU_IC_CONF_PP_CSC2 from a register value.
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#define BG_IPU_IC_CONF_PP_CSC2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PP_CSC2) >> BP_IPU_IC_CONF_PP_CSC2)
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//! @brief Format value for bitfield IPU_IC_CONF_PP_CSC2.
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#define BF_IPU_IC_CONF_PP_CSC2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PP_CSC2) & BM_IPU_IC_CONF_PP_CSC2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PP_CSC2 field to a new value.
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#define BW_IPU_IC_CONF_PP_CSC2(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PP_CSC2) | BF_IPU_IC_CONF_PP_CSC2(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field PP_CMB[19] (RW)
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*
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* Post-Processing Task combining enable. This bit enables combining.
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*
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* Values:
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* - 0 - Combining is disabled.
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* - 1 - Combining is enabled.
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*/
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//@{
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#define BP_IPU_IC_CONF_PP_CMB (19) //!< Bit position for IPU_IC_CONF_PP_CMB.
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#define BM_IPU_IC_CONF_PP_CMB (0x00080000) //!< Bit mask for IPU_IC_CONF_PP_CMB.
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//! @brief Get value of IPU_IC_CONF_PP_CMB from a register value.
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#define BG_IPU_IC_CONF_PP_CMB(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PP_CMB) >> BP_IPU_IC_CONF_PP_CMB)
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//! @brief Format value for bitfield IPU_IC_CONF_PP_CMB.
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#define BF_IPU_IC_CONF_PP_CMB(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PP_CMB) & BM_IPU_IC_CONF_PP_CMB)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PP_CMB field to a new value.
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#define BW_IPU_IC_CONF_PP_CMB(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PP_CMB) | BF_IPU_IC_CONF_PP_CMB(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field PP_ROT_EN[20] (RW)
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*
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* Post-Processing Rotation Task enable. This bit enable Post-Processing Rotation Task.
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*
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* Values:
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* - 0 - Rotation is disabled.
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* - 1 - Rotation is enabled.
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*/
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//@{
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#define BP_IPU_IC_CONF_PP_ROT_EN (20) //!< Bit position for IPU_IC_CONF_PP_ROT_EN.
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#define BM_IPU_IC_CONF_PP_ROT_EN (0x00100000) //!< Bit mask for IPU_IC_CONF_PP_ROT_EN.
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//! @brief Get value of IPU_IC_CONF_PP_ROT_EN from a register value.
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#define BG_IPU_IC_CONF_PP_ROT_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_PP_ROT_EN) >> BP_IPU_IC_CONF_PP_ROT_EN)
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//! @brief Format value for bitfield IPU_IC_CONF_PP_ROT_EN.
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#define BF_IPU_IC_CONF_PP_ROT_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_PP_ROT_EN) & BM_IPU_IC_CONF_PP_ROT_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PP_ROT_EN field to a new value.
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#define BW_IPU_IC_CONF_PP_ROT_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_PP_ROT_EN) | BF_IPU_IC_CONF_PP_ROT_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field IC_GLB_LOC_A[28] (RW)
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*
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* Global Alpha. This bit select the source of Alpha parameter.
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*
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* Values:
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* - 0 - Alpha parameter is local.
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* - 1 - Alpha parameter is global.
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*/
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//@{
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#define BP_IPU_IC_CONF_IC_GLB_LOC_A (28) //!< Bit position for IPU_IC_CONF_IC_GLB_LOC_A.
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#define BM_IPU_IC_CONF_IC_GLB_LOC_A (0x10000000) //!< Bit mask for IPU_IC_CONF_IC_GLB_LOC_A.
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//! @brief Get value of IPU_IC_CONF_IC_GLB_LOC_A from a register value.
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#define BG_IPU_IC_CONF_IC_GLB_LOC_A(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_IC_GLB_LOC_A) >> BP_IPU_IC_CONF_IC_GLB_LOC_A)
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//! @brief Format value for bitfield IPU_IC_CONF_IC_GLB_LOC_A.
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#define BF_IPU_IC_CONF_IC_GLB_LOC_A(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_IC_GLB_LOC_A) & BM_IPU_IC_CONF_IC_GLB_LOC_A)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IC_GLB_LOC_A field to a new value.
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#define BW_IPU_IC_CONF_IC_GLB_LOC_A(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_IC_GLB_LOC_A) | BF_IPU_IC_CONF_IC_GLB_LOC_A(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field IC_KEY_COLOR_EN[29] (RW)
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*
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* Key Color enable. This bit enables the key color feature.
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*
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* Values:
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* - 0 - Key color is disabled.
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* - 1 - Key color is enabled.
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*/
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//@{
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#define BP_IPU_IC_CONF_IC_KEY_COLOR_EN (29) //!< Bit position for IPU_IC_CONF_IC_KEY_COLOR_EN.
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#define BM_IPU_IC_CONF_IC_KEY_COLOR_EN (0x20000000) //!< Bit mask for IPU_IC_CONF_IC_KEY_COLOR_EN.
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//! @brief Get value of IPU_IC_CONF_IC_KEY_COLOR_EN from a register value.
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#define BG_IPU_IC_CONF_IC_KEY_COLOR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_IC_KEY_COLOR_EN) >> BP_IPU_IC_CONF_IC_KEY_COLOR_EN)
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//! @brief Format value for bitfield IPU_IC_CONF_IC_KEY_COLOR_EN.
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#define BF_IPU_IC_CONF_IC_KEY_COLOR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_IC_KEY_COLOR_EN) & BM_IPU_IC_CONF_IC_KEY_COLOR_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IC_KEY_COLOR_EN field to a new value.
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#define BW_IPU_IC_CONF_IC_KEY_COLOR_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_IC_KEY_COLOR_EN) | BF_IPU_IC_CONF_IC_KEY_COLOR_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field RWS_EN[30] (RW)
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*
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* Raw sensor enable. This bit indicate if a Raw sensor is attached (Bayer format). This bit is used
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* together with the CSI_MEM_WR_EN bit as follows: CSI_MEM_WR_EN=0, RWS_EN=0 - data is fed from the
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* CSI to the IC for processing; CSI_MEM_WR_EN=1, RWS_EN=0 - data is fed from the CSI to the IC for
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* processing and also for writing to the system memory; CSI_MEM_WR_EN=0, RWS_EN=1 - data is fed
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* from the CSI to the system memory (via the IC) and from the system memory to the IC for
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* processing; CSI_MEM_WR_EN=1, RWS_EN=1 - non-valid configuration.
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*
|
|
* Values:
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|
* - 0 - Raw sensor is not attached.
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* - 1 - Raw sensor is attached.
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*/
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//@{
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#define BP_IPU_IC_CONF_RWS_EN (30) //!< Bit position for IPU_IC_CONF_RWS_EN.
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#define BM_IPU_IC_CONF_RWS_EN (0x40000000) //!< Bit mask for IPU_IC_CONF_RWS_EN.
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//! @brief Get value of IPU_IC_CONF_RWS_EN from a register value.
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#define BG_IPU_IC_CONF_RWS_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_RWS_EN) >> BP_IPU_IC_CONF_RWS_EN)
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//! @brief Format value for bitfield IPU_IC_CONF_RWS_EN.
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#define BF_IPU_IC_CONF_RWS_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_RWS_EN) & BM_IPU_IC_CONF_RWS_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the RWS_EN field to a new value.
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#define BW_IPU_IC_CONF_RWS_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_RWS_EN) | BF_IPU_IC_CONF_RWS_EN(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_CONF, field CSI_MEM_WR_EN[31] (RW)
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*
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* CSI direct memory write enable. This bit enables writing data from sensor directly to memory even
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* when a raw sensor is not attached.
|
|
*
|
|
* Values:
|
|
* - 0 - CSI direct writing to memory is disabled.
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|
* - 1 - CSI direct writing to memory is enabled.
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*/
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//@{
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#define BP_IPU_IC_CONF_CSI_MEM_WR_EN (31) //!< Bit position for IPU_IC_CONF_CSI_MEM_WR_EN.
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#define BM_IPU_IC_CONF_CSI_MEM_WR_EN (0x80000000) //!< Bit mask for IPU_IC_CONF_CSI_MEM_WR_EN.
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//! @brief Get value of IPU_IC_CONF_CSI_MEM_WR_EN from a register value.
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#define BG_IPU_IC_CONF_CSI_MEM_WR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CONF_CSI_MEM_WR_EN) >> BP_IPU_IC_CONF_CSI_MEM_WR_EN)
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//! @brief Format value for bitfield IPU_IC_CONF_CSI_MEM_WR_EN.
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#define BF_IPU_IC_CONF_CSI_MEM_WR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CONF_CSI_MEM_WR_EN) & BM_IPU_IC_CONF_CSI_MEM_WR_EN)
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|
|
#ifndef __LANGUAGE_ASM__
|
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//! @brief Set the CSI_MEM_WR_EN field to a new value.
|
|
#define BW_IPU_IC_CONF_CSI_MEM_WR_EN(x, v) (HW_IPU_IC_CONF_WR(x, (HW_IPU_IC_CONF_RD(x) & ~BM_IPU_IC_CONF_CSI_MEM_WR_EN) | BF_IPU_IC_CONF_CSI_MEM_WR_EN(v)))
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#endif
|
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_IC_PRP_ENC_RSC - IC Preprocessing Encoder Resizing Coefficients Register
|
|
//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_PRP_ENC_RSC - IC Preprocessing Encoder Resizing Coefficients Register (RW)
|
|
*
|
|
* Reset value: 0x20002000
|
|
*
|
|
* This register contains the resizing and downsizing parameters for Preprocessing task for
|
|
* encoding.
|
|
*/
|
|
typedef union _hw_ipu_ic_prp_enc_rsc
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_prp_enc_rsc_bitfields
|
|
{
|
|
unsigned PRPENC_RS_R_H : 14; //!< [13:0] Preprocessing task for encoding Resizing horizontal Ratio.
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unsigned PRPENC_DS_R_H : 2; //!< [15:14] Preprocessing task for encoding Downsizing horizontal Ratio.
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unsigned PRPENC_RS_R_V : 14; //!< [29:16] Preprocessing task for encoding Resizing vertical Ratio.
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|
unsigned PRPENC_DS_R_V : 2; //!< [31:30] Preprocessing task for encoding Downsizing vertical Ratio.
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|
} B;
|
|
} hw_ipu_ic_prp_enc_rsc_t;
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|
#endif
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|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_PRP_ENC_RSC register
|
|
*/
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|
//@{
|
|
#define HW_IPU_IC_PRP_ENC_RSC_ADDR(x) (REGS_IPU_BASE(x) + 0x20004)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_PRP_ENC_RSC(x) (*(volatile hw_ipu_ic_prp_enc_rsc_t *) HW_IPU_IC_PRP_ENC_RSC_ADDR(x))
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#define HW_IPU_IC_PRP_ENC_RSC_RD(x) (HW_IPU_IC_PRP_ENC_RSC(x).U)
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|
#define HW_IPU_IC_PRP_ENC_RSC_WR(x, v) (HW_IPU_IC_PRP_ENC_RSC(x).U = (v))
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|
#define HW_IPU_IC_PRP_ENC_RSC_SET(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, HW_IPU_IC_PRP_ENC_RSC_RD(x) | (v)))
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|
#define HW_IPU_IC_PRP_ENC_RSC_CLR(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, HW_IPU_IC_PRP_ENC_RSC_RD(x) & ~(v)))
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|
#define HW_IPU_IC_PRP_ENC_RSC_TOG(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, HW_IPU_IC_PRP_ENC_RSC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_PRP_ENC_RSC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_PRP_ENC_RSC, field PRPENC_RS_R_H[13:0] (RW)
|
|
*
|
|
* Preprocessing task for encoding Resizing horizontal Ratio. This field contains the resizing
|
|
* horizontal coefficient of Preprocessing for Encoding. Resizing Ratio is equal to PRPENC_RS_R_H: M
|
|
* Where M = 2^13; SI - input size; SO - output size PRPENC_RS_R_H = floor(M*(SI-1)/(SO-1));
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H (0) //!< Bit position for IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H.
|
|
#define BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H (0x00003fff) //!< Bit mask for IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H.
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|
|
|
//! @brief Get value of IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H from a register value.
|
|
#define BG_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H) >> BP_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H.
|
|
#define BF_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_RS_R_H field to a new value.
|
|
#define BW_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, (HW_IPU_IC_PRP_ENC_RSC_RD(x) & ~BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H) | BF_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_H(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PRP_ENC_RSC, field PRPENC_DS_R_H[15:14] (RW)
|
|
*
|
|
* Preprocessing task for encoding Downsizing horizontal Ratio. This field contains the downsizing
|
|
* horizontal coefficient of Preprocessing for Encoding. Values:
|
|
*
|
|
* Values:
|
|
* - 00 - 1
|
|
* - 01 - 2
|
|
* - 10 - 4
|
|
* - 11 - RSV
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H (14) //!< Bit position for IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H.
|
|
#define BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H (0x0000c000) //!< Bit mask for IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H.
|
|
|
|
//! @brief Get value of IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H from a register value.
|
|
#define BG_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H) >> BP_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H.
|
|
#define BF_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the PRPENC_DS_R_H field to a new value.
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|
#define BW_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, (HW_IPU_IC_PRP_ENC_RSC_RD(x) & ~BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H) | BF_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_H(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_PRP_ENC_RSC, field PRPENC_RS_R_V[29:16] (RW)
|
|
*
|
|
* Preprocessing task for encoding Resizing vertical Ratio. This field contains the resizing
|
|
* vertical coefficient of Preprocessing for Encoding. Resizing Ratio is equal to PRPENC_RS_R_V: M
|
|
* Where M = 2^13; SI - input size; SO - output size PRPENC_RS_R_V = floor(M*(SI-1)/(SO-1));
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|
*/
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|
//@{
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|
#define BP_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V (16) //!< Bit position for IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V.
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#define BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V (0x3fff0000) //!< Bit mask for IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V.
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//! @brief Get value of IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V from a register value.
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#define BG_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V) >> BP_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V)
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//! @brief Format value for bitfield IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V.
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#define BF_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the PRPENC_RS_R_V field to a new value.
|
|
#define BW_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, (HW_IPU_IC_PRP_ENC_RSC_RD(x) & ~BM_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V) | BF_IPU_IC_PRP_ENC_RSC_PRPENC_RS_R_V(v)))
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#endif
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//@}
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/*! @name Register IPU_IC_PRP_ENC_RSC, field PRPENC_DS_R_V[31:30] (RW)
|
|
*
|
|
* Preprocessing task for encoding Downsizing vertical Ratio. This field contains the downsizing
|
|
* vertical coefficient of Preprocessing for Encoding.
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|
*/
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|
//@{
|
|
#define BP_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V (30) //!< Bit position for IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V.
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#define BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V (0xc0000000) //!< Bit mask for IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V.
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//! @brief Get value of IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V from a register value.
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#define BG_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V) >> BP_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V)
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//! @brief Format value for bitfield IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V.
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#define BF_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V) & BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPENC_DS_R_V field to a new value.
|
|
#define BW_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V(x, v) (HW_IPU_IC_PRP_ENC_RSC_WR(x, (HW_IPU_IC_PRP_ENC_RSC_RD(x) & ~BM_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V) | BF_IPU_IC_PRP_ENC_RSC_PRPENC_DS_R_V(v)))
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#endif
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|
//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_IC_PRP_VF_RSC - IC Preprocessing View-Finder Resizing Coefficients Register
|
|
//-------------------------------------------------------------------------------------------
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_PRP_VF_RSC - IC Preprocessing View-Finder Resizing Coefficients Register (RW)
|
|
*
|
|
* Reset value: 0x20002000
|
|
*
|
|
* This register contains the resizing and downsizing parameters for preprocessing task for display.
|
|
*/
|
|
typedef union _hw_ipu_ic_prp_vf_rsc
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_prp_vf_rsc_bitfields
|
|
{
|
|
unsigned PRPVF_RS_R_H : 14; //!< [13:0] Preprocessing task for view-finding resizing horizontal ratio.
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|
unsigned PRPVF_DS_R_H : 2; //!< [15:14] Preprocessing task for encoding Downsizing horizontal Ratio.
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|
unsigned PRPVF_RS_R_V : 14; //!< [29:16] Preprocessing task for encoding Resizing vertical Ratio.
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|
unsigned PRPVF_DS_R_V : 2; //!< [31:30] Preprocessing task for encoding Downsizing vertical Ratio.
|
|
} B;
|
|
} hw_ipu_ic_prp_vf_rsc_t;
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|
#endif
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|
|
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/*!
|
|
* @name Constants and macros for entire IPU_IC_PRP_VF_RSC register
|
|
*/
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|
//@{
|
|
#define HW_IPU_IC_PRP_VF_RSC_ADDR(x) (REGS_IPU_BASE(x) + 0x20008)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_PRP_VF_RSC(x) (*(volatile hw_ipu_ic_prp_vf_rsc_t *) HW_IPU_IC_PRP_VF_RSC_ADDR(x))
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#define HW_IPU_IC_PRP_VF_RSC_RD(x) (HW_IPU_IC_PRP_VF_RSC(x).U)
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#define HW_IPU_IC_PRP_VF_RSC_WR(x, v) (HW_IPU_IC_PRP_VF_RSC(x).U = (v))
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#define HW_IPU_IC_PRP_VF_RSC_SET(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, HW_IPU_IC_PRP_VF_RSC_RD(x) | (v)))
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#define HW_IPU_IC_PRP_VF_RSC_CLR(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, HW_IPU_IC_PRP_VF_RSC_RD(x) & ~(v)))
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|
#define HW_IPU_IC_PRP_VF_RSC_TOG(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, HW_IPU_IC_PRP_VF_RSC_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_IC_PRP_VF_RSC bitfields
|
|
*/
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|
|
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/*! @name Register IPU_IC_PRP_VF_RSC, field PRPVF_RS_R_H[13:0] (RW)
|
|
*
|
|
* Preprocessing task for view-finding resizing horizontal ratio. This field contains the resizing
|
|
* horizontal coefficient of preprocessing Task For View-finder. Resizing Ratio is equal to
|
|
* PRPVF_RS_R_H: M Where M = 2^13; SI - input size; SO - output size PRPVF_RS_R_H =
|
|
* floor(M*(SI-1)/(SO-1));
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H (0) //!< Bit position for IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H.
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|
#define BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H (0x00003fff) //!< Bit mask for IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H.
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|
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|
//! @brief Get value of IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H from a register value.
|
|
#define BG_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H) >> BP_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H)
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|
|
//! @brief Format value for bitfield IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H.
|
|
#define BF_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H) & BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_RS_R_H field to a new value.
|
|
#define BW_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, (HW_IPU_IC_PRP_VF_RSC_RD(x) & ~BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H) | BF_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_H(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PRP_VF_RSC, field PRPVF_DS_R_H[15:14] (RW)
|
|
*
|
|
* Preprocessing task for encoding Downsizing horizontal Ratio. This field contains the downsizing
|
|
* horizontal coefficient of Preprocessing for View-Finder. Values:
|
|
*
|
|
* Values:
|
|
* - 00 - 1
|
|
* - 01 - 2
|
|
* - 10 - 4
|
|
* - 11 - RSV
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H (14) //!< Bit position for IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H.
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|
#define BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H (0x0000c000) //!< Bit mask for IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H.
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|
|
|
//! @brief Get value of IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H from a register value.
|
|
#define BG_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H) >> BP_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H.
|
|
#define BF_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H) & BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_DS_R_H field to a new value.
|
|
#define BW_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, (HW_IPU_IC_PRP_VF_RSC_RD(x) & ~BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H) | BF_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_H(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PRP_VF_RSC, field PRPVF_RS_R_V[29:16] (RW)
|
|
*
|
|
* Preprocessing task for encoding Resizing vertical Ratio. This field contains the resizing
|
|
* vertical coefficient of Preprocessing for View-Finder. Resizing Ratio is equal to PRPVF_RS_R_V: M
|
|
* Where M = 2^13; SI - input size; SO - output size PRPVF_RS_R_V = floor(M*(SI-1)/(SO-1));
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V (16) //!< Bit position for IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V.
|
|
#define BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V (0x3fff0000) //!< Bit mask for IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V.
|
|
|
|
//! @brief Get value of IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V from a register value.
|
|
#define BG_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V) >> BP_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V.
|
|
#define BF_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V) & BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_RS_R_V field to a new value.
|
|
#define BW_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, (HW_IPU_IC_PRP_VF_RSC_RD(x) & ~BM_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V) | BF_IPU_IC_PRP_VF_RSC_PRPVF_RS_R_V(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PRP_VF_RSC, field PRPVF_DS_R_V[31:30] (RW)
|
|
*
|
|
* Preprocessing task for encoding Downsizing vertical Ratio. This field contains the downsizing
|
|
* vertical coefficient of Preprocessing for View-Finder.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V (30) //!< Bit position for IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V.
|
|
#define BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V (0xc0000000) //!< Bit mask for IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V.
|
|
|
|
//! @brief Get value of IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V from a register value.
|
|
#define BG_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V) >> BP_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V.
|
|
#define BF_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V) & BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PRPVF_DS_R_V field to a new value.
|
|
#define BW_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V(x, v) (HW_IPU_IC_PRP_VF_RSC_WR(x, (HW_IPU_IC_PRP_VF_RSC_RD(x) & ~BM_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V) | BF_IPU_IC_PRP_VF_RSC_PRPVF_DS_R_V(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_PP_RSC - IC Postprocessing Encoder Resizing Coefficients Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_PP_RSC - IC Postprocessing Encoder Resizing Coefficients Register (RW)
|
|
*
|
|
* Reset value: 0x20002000
|
|
*
|
|
* This register contains the resizing and downsizing parameters for Post-Processing task for
|
|
* display.
|
|
*/
|
|
typedef union _hw_ipu_ic_pp_rsc
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_pp_rsc_bitfields
|
|
{
|
|
unsigned PP_RS_R_H : 14; //!< [13:0] Post-Processing task Resizing horizontal Ratio.
|
|
unsigned PP_DS_R_H : 2; //!< [15:14] Post-Processing task Downsizing horizontal Ratio.
|
|
unsigned PP_RS_R_V : 14; //!< [29:16] Post-Processing task Resizing vertical Ratio.
|
|
unsigned PP_DS_R_V : 2; //!< [31:30] Post-Processing task Downsizing vertical Ratio.
|
|
} B;
|
|
} hw_ipu_ic_pp_rsc_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_PP_RSC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_PP_RSC_ADDR(x) (REGS_IPU_BASE(x) + 0x2000c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_PP_RSC(x) (*(volatile hw_ipu_ic_pp_rsc_t *) HW_IPU_IC_PP_RSC_ADDR(x))
|
|
#define HW_IPU_IC_PP_RSC_RD(x) (HW_IPU_IC_PP_RSC(x).U)
|
|
#define HW_IPU_IC_PP_RSC_WR(x, v) (HW_IPU_IC_PP_RSC(x).U = (v))
|
|
#define HW_IPU_IC_PP_RSC_SET(x, v) (HW_IPU_IC_PP_RSC_WR(x, HW_IPU_IC_PP_RSC_RD(x) | (v)))
|
|
#define HW_IPU_IC_PP_RSC_CLR(x, v) (HW_IPU_IC_PP_RSC_WR(x, HW_IPU_IC_PP_RSC_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_PP_RSC_TOG(x, v) (HW_IPU_IC_PP_RSC_WR(x, HW_IPU_IC_PP_RSC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_PP_RSC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_PP_RSC, field PP_RS_R_H[13:0] (RW)
|
|
*
|
|
* Post-Processing task Resizing horizontal Ratio. This field contains the resizing horizontal
|
|
* coefficient of Post-Processing. Resizing Ratio is equal to PP_RS_R_H: M Where M = 2^13; SI -
|
|
* input size; SO - output size PP_RS_R_H = floor(M*(SI-1)/(SO-1));
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PP_RSC_PP_RS_R_H (0) //!< Bit position for IPU_IC_PP_RSC_PP_RS_R_H.
|
|
#define BM_IPU_IC_PP_RSC_PP_RS_R_H (0x00003fff) //!< Bit mask for IPU_IC_PP_RSC_PP_RS_R_H.
|
|
|
|
//! @brief Get value of IPU_IC_PP_RSC_PP_RS_R_H from a register value.
|
|
#define BG_IPU_IC_PP_RSC_PP_RS_R_H(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PP_RSC_PP_RS_R_H) >> BP_IPU_IC_PP_RSC_PP_RS_R_H)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PP_RSC_PP_RS_R_H.
|
|
#define BF_IPU_IC_PP_RSC_PP_RS_R_H(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PP_RSC_PP_RS_R_H) & BM_IPU_IC_PP_RSC_PP_RS_R_H)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_RS_R_H field to a new value.
|
|
#define BW_IPU_IC_PP_RSC_PP_RS_R_H(x, v) (HW_IPU_IC_PP_RSC_WR(x, (HW_IPU_IC_PP_RSC_RD(x) & ~BM_IPU_IC_PP_RSC_PP_RS_R_H) | BF_IPU_IC_PP_RSC_PP_RS_R_H(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PP_RSC, field PP_DS_R_H[15:14] (RW)
|
|
*
|
|
* Post-Processing task Downsizing horizontal Ratio. This field contains the downsizing horizontal
|
|
* coefficient of Post-Processing.
|
|
*
|
|
* Values:
|
|
* - 00 - 1
|
|
* - 01 - 2
|
|
* - 10 - 4
|
|
* - 11 - RSV
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PP_RSC_PP_DS_R_H (14) //!< Bit position for IPU_IC_PP_RSC_PP_DS_R_H.
|
|
#define BM_IPU_IC_PP_RSC_PP_DS_R_H (0x0000c000) //!< Bit mask for IPU_IC_PP_RSC_PP_DS_R_H.
|
|
|
|
//! @brief Get value of IPU_IC_PP_RSC_PP_DS_R_H from a register value.
|
|
#define BG_IPU_IC_PP_RSC_PP_DS_R_H(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PP_RSC_PP_DS_R_H) >> BP_IPU_IC_PP_RSC_PP_DS_R_H)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PP_RSC_PP_DS_R_H.
|
|
#define BF_IPU_IC_PP_RSC_PP_DS_R_H(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PP_RSC_PP_DS_R_H) & BM_IPU_IC_PP_RSC_PP_DS_R_H)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_DS_R_H field to a new value.
|
|
#define BW_IPU_IC_PP_RSC_PP_DS_R_H(x, v) (HW_IPU_IC_PP_RSC_WR(x, (HW_IPU_IC_PP_RSC_RD(x) & ~BM_IPU_IC_PP_RSC_PP_DS_R_H) | BF_IPU_IC_PP_RSC_PP_DS_R_H(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PP_RSC, field PP_RS_R_V[29:16] (RW)
|
|
*
|
|
* Post-Processing task Resizing vertical Ratio. This field contains the resizing vertical
|
|
* coefficient of Post-Processing. Resizing Ratio is equal to PP_RS_R_V: M Where M = 2^13; SI -
|
|
* input size; SO - output size PP_RS_R_V = floor(M*(SI-1)/(SO-1));
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PP_RSC_PP_RS_R_V (16) //!< Bit position for IPU_IC_PP_RSC_PP_RS_R_V.
|
|
#define BM_IPU_IC_PP_RSC_PP_RS_R_V (0x3fff0000) //!< Bit mask for IPU_IC_PP_RSC_PP_RS_R_V.
|
|
|
|
//! @brief Get value of IPU_IC_PP_RSC_PP_RS_R_V from a register value.
|
|
#define BG_IPU_IC_PP_RSC_PP_RS_R_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PP_RSC_PP_RS_R_V) >> BP_IPU_IC_PP_RSC_PP_RS_R_V)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PP_RSC_PP_RS_R_V.
|
|
#define BF_IPU_IC_PP_RSC_PP_RS_R_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PP_RSC_PP_RS_R_V) & BM_IPU_IC_PP_RSC_PP_RS_R_V)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_RS_R_V field to a new value.
|
|
#define BW_IPU_IC_PP_RSC_PP_RS_R_V(x, v) (HW_IPU_IC_PP_RSC_WR(x, (HW_IPU_IC_PP_RSC_RD(x) & ~BM_IPU_IC_PP_RSC_PP_RS_R_V) | BF_IPU_IC_PP_RSC_PP_RS_R_V(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_PP_RSC, field PP_DS_R_V[31:30] (RW)
|
|
*
|
|
* Post-Processing task Downsizing vertical Ratio. This field contains the downsizing vertical
|
|
* coefficient of Post-Processing.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_PP_RSC_PP_DS_R_V (30) //!< Bit position for IPU_IC_PP_RSC_PP_DS_R_V.
|
|
#define BM_IPU_IC_PP_RSC_PP_DS_R_V (0xc0000000) //!< Bit mask for IPU_IC_PP_RSC_PP_DS_R_V.
|
|
|
|
//! @brief Get value of IPU_IC_PP_RSC_PP_DS_R_V from a register value.
|
|
#define BG_IPU_IC_PP_RSC_PP_DS_R_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_PP_RSC_PP_DS_R_V) >> BP_IPU_IC_PP_RSC_PP_DS_R_V)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_PP_RSC_PP_DS_R_V.
|
|
#define BF_IPU_IC_PP_RSC_PP_DS_R_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_PP_RSC_PP_DS_R_V) & BM_IPU_IC_PP_RSC_PP_DS_R_V)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PP_DS_R_V field to a new value.
|
|
#define BW_IPU_IC_PP_RSC_PP_DS_R_V(x, v) (HW_IPU_IC_PP_RSC_WR(x, (HW_IPU_IC_PP_RSC_RD(x) & ~BM_IPU_IC_PP_RSC_PP_DS_R_V) | BF_IPU_IC_PP_RSC_PP_DS_R_V(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_CMBP_1 - IC Combining Parameters Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_CMBP_1 - IC Combining Parameters Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_ic_cmbp_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_cmbp_1_bitfields
|
|
{
|
|
unsigned IC_PRPVF_ALPHA_V : 8; //!< [7:0] Preprocessing task for viewfinder Global Alpha.
|
|
unsigned IC_PP_ALPHA_V : 8; //!< [15:8] Post-Processing task Global Alpha.
|
|
unsigned RESERVED0 : 16; //!< [31:16] Reserved.
|
|
} B;
|
|
} hw_ipu_ic_cmbp_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_CMBP_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_CMBP_1_ADDR(x) (REGS_IPU_BASE(x) + 0x20010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_CMBP_1(x) (*(volatile hw_ipu_ic_cmbp_1_t *) HW_IPU_IC_CMBP_1_ADDR(x))
|
|
#define HW_IPU_IC_CMBP_1_RD(x) (HW_IPU_IC_CMBP_1(x).U)
|
|
#define HW_IPU_IC_CMBP_1_WR(x, v) (HW_IPU_IC_CMBP_1(x).U = (v))
|
|
#define HW_IPU_IC_CMBP_1_SET(x, v) (HW_IPU_IC_CMBP_1_WR(x, HW_IPU_IC_CMBP_1_RD(x) | (v)))
|
|
#define HW_IPU_IC_CMBP_1_CLR(x, v) (HW_IPU_IC_CMBP_1_WR(x, HW_IPU_IC_CMBP_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_CMBP_1_TOG(x, v) (HW_IPU_IC_CMBP_1_WR(x, HW_IPU_IC_CMBP_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_CMBP_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_CMBP_1, field IC_PRPVF_ALPHA_V[7:0] (RW)
|
|
*
|
|
* Preprocessing task for viewfinder Global Alpha. This field contains the Global Alpha value of
|
|
* Preprocessing for viewfinder.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V (0) //!< Bit position for IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V.
|
|
#define BM_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V (0x000000ff) //!< Bit mask for IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V.
|
|
|
|
//! @brief Get value of IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V from a register value.
|
|
#define BG_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V) >> BP_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V.
|
|
#define BF_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V) & BM_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_PRPVF_ALPHA_V field to a new value.
|
|
#define BW_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V(x, v) (HW_IPU_IC_CMBP_1_WR(x, (HW_IPU_IC_CMBP_1_RD(x) & ~BM_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V) | BF_IPU_IC_CMBP_1_IC_PRPVF_ALPHA_V(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CMBP_1, field IC_PP_ALPHA_V[15:8] (RW)
|
|
*
|
|
* Post-Processing task Global Alpha. This field contains the Global Alpha value of Post-Processing.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CMBP_1_IC_PP_ALPHA_V (8) //!< Bit position for IPU_IC_CMBP_1_IC_PP_ALPHA_V.
|
|
#define BM_IPU_IC_CMBP_1_IC_PP_ALPHA_V (0x0000ff00) //!< Bit mask for IPU_IC_CMBP_1_IC_PP_ALPHA_V.
|
|
|
|
//! @brief Get value of IPU_IC_CMBP_1_IC_PP_ALPHA_V from a register value.
|
|
#define BG_IPU_IC_CMBP_1_IC_PP_ALPHA_V(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CMBP_1_IC_PP_ALPHA_V) >> BP_IPU_IC_CMBP_1_IC_PP_ALPHA_V)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CMBP_1_IC_PP_ALPHA_V.
|
|
#define BF_IPU_IC_CMBP_1_IC_PP_ALPHA_V(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CMBP_1_IC_PP_ALPHA_V) & BM_IPU_IC_CMBP_1_IC_PP_ALPHA_V)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_PP_ALPHA_V field to a new value.
|
|
#define BW_IPU_IC_CMBP_1_IC_PP_ALPHA_V(x, v) (HW_IPU_IC_CMBP_1_WR(x, (HW_IPU_IC_CMBP_1_RD(x) & ~BM_IPU_IC_CMBP_1_IC_PP_ALPHA_V) | BF_IPU_IC_CMBP_1_IC_PP_ALPHA_V(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_CMBP_2 - IC Combining Parameters Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_CMBP_2 - IC Combining Parameters Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_ic_cmbp_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_cmbp_2_bitfields
|
|
{
|
|
unsigned IC_KEY_COLOR_B : 8; //!< [7:0] Key Color Blue.
|
|
unsigned IC_KEY_COLOR_G : 8; //!< [15:8] Key Color Green.
|
|
unsigned IC_KEY_COLOR_R : 8; //!< [23:16] Key Color Red.
|
|
unsigned RESERVED0 : 8; //!< [31:24] Reserved.
|
|
} B;
|
|
} hw_ipu_ic_cmbp_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_CMBP_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_CMBP_2_ADDR(x) (REGS_IPU_BASE(x) + 0x20014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_CMBP_2(x) (*(volatile hw_ipu_ic_cmbp_2_t *) HW_IPU_IC_CMBP_2_ADDR(x))
|
|
#define HW_IPU_IC_CMBP_2_RD(x) (HW_IPU_IC_CMBP_2(x).U)
|
|
#define HW_IPU_IC_CMBP_2_WR(x, v) (HW_IPU_IC_CMBP_2(x).U = (v))
|
|
#define HW_IPU_IC_CMBP_2_SET(x, v) (HW_IPU_IC_CMBP_2_WR(x, HW_IPU_IC_CMBP_2_RD(x) | (v)))
|
|
#define HW_IPU_IC_CMBP_2_CLR(x, v) (HW_IPU_IC_CMBP_2_WR(x, HW_IPU_IC_CMBP_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_CMBP_2_TOG(x, v) (HW_IPU_IC_CMBP_2_WR(x, HW_IPU_IC_CMBP_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_CMBP_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_CMBP_2, field IC_KEY_COLOR_B[7:0] (RW)
|
|
*
|
|
* Key Color Blue.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CMBP_2_IC_KEY_COLOR_B (0) //!< Bit position for IPU_IC_CMBP_2_IC_KEY_COLOR_B.
|
|
#define BM_IPU_IC_CMBP_2_IC_KEY_COLOR_B (0x000000ff) //!< Bit mask for IPU_IC_CMBP_2_IC_KEY_COLOR_B.
|
|
|
|
//! @brief Get value of IPU_IC_CMBP_2_IC_KEY_COLOR_B from a register value.
|
|
#define BG_IPU_IC_CMBP_2_IC_KEY_COLOR_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CMBP_2_IC_KEY_COLOR_B) >> BP_IPU_IC_CMBP_2_IC_KEY_COLOR_B)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CMBP_2_IC_KEY_COLOR_B.
|
|
#define BF_IPU_IC_CMBP_2_IC_KEY_COLOR_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CMBP_2_IC_KEY_COLOR_B) & BM_IPU_IC_CMBP_2_IC_KEY_COLOR_B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_KEY_COLOR_B field to a new value.
|
|
#define BW_IPU_IC_CMBP_2_IC_KEY_COLOR_B(x, v) (HW_IPU_IC_CMBP_2_WR(x, (HW_IPU_IC_CMBP_2_RD(x) & ~BM_IPU_IC_CMBP_2_IC_KEY_COLOR_B) | BF_IPU_IC_CMBP_2_IC_KEY_COLOR_B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CMBP_2, field IC_KEY_COLOR_G[15:8] (RW)
|
|
*
|
|
* Key Color Green.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CMBP_2_IC_KEY_COLOR_G (8) //!< Bit position for IPU_IC_CMBP_2_IC_KEY_COLOR_G.
|
|
#define BM_IPU_IC_CMBP_2_IC_KEY_COLOR_G (0x0000ff00) //!< Bit mask for IPU_IC_CMBP_2_IC_KEY_COLOR_G.
|
|
|
|
//! @brief Get value of IPU_IC_CMBP_2_IC_KEY_COLOR_G from a register value.
|
|
#define BG_IPU_IC_CMBP_2_IC_KEY_COLOR_G(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CMBP_2_IC_KEY_COLOR_G) >> BP_IPU_IC_CMBP_2_IC_KEY_COLOR_G)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CMBP_2_IC_KEY_COLOR_G.
|
|
#define BF_IPU_IC_CMBP_2_IC_KEY_COLOR_G(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CMBP_2_IC_KEY_COLOR_G) & BM_IPU_IC_CMBP_2_IC_KEY_COLOR_G)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_KEY_COLOR_G field to a new value.
|
|
#define BW_IPU_IC_CMBP_2_IC_KEY_COLOR_G(x, v) (HW_IPU_IC_CMBP_2_WR(x, (HW_IPU_IC_CMBP_2_RD(x) & ~BM_IPU_IC_CMBP_2_IC_KEY_COLOR_G) | BF_IPU_IC_CMBP_2_IC_KEY_COLOR_G(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_CMBP_2, field IC_KEY_COLOR_R[23:16] (RW)
|
|
*
|
|
* Key Color Red.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_CMBP_2_IC_KEY_COLOR_R (16) //!< Bit position for IPU_IC_CMBP_2_IC_KEY_COLOR_R.
|
|
#define BM_IPU_IC_CMBP_2_IC_KEY_COLOR_R (0x00ff0000) //!< Bit mask for IPU_IC_CMBP_2_IC_KEY_COLOR_R.
|
|
|
|
//! @brief Get value of IPU_IC_CMBP_2_IC_KEY_COLOR_R from a register value.
|
|
#define BG_IPU_IC_CMBP_2_IC_KEY_COLOR_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_CMBP_2_IC_KEY_COLOR_R) >> BP_IPU_IC_CMBP_2_IC_KEY_COLOR_R)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_CMBP_2_IC_KEY_COLOR_R.
|
|
#define BF_IPU_IC_CMBP_2_IC_KEY_COLOR_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_CMBP_2_IC_KEY_COLOR_R) & BM_IPU_IC_CMBP_2_IC_KEY_COLOR_R)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IC_KEY_COLOR_R field to a new value.
|
|
#define BW_IPU_IC_CMBP_2_IC_KEY_COLOR_R(x, v) (HW_IPU_IC_CMBP_2_WR(x, (HW_IPU_IC_CMBP_2_RD(x) & ~BM_IPU_IC_CMBP_2_IC_KEY_COLOR_R) | BF_IPU_IC_CMBP_2_IC_KEY_COLOR_R(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_IDMAC_1 - IC IDMAC Parameters 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_IDMAC_1 - IC IDMAC Parameters 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_ic_idmac_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_idmac_1_bitfields
|
|
{
|
|
unsigned CB0_BURST_16 : 1; //!< [0] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB0
|
|
unsigned CB1_BURST_16 : 1; //!< [1] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB1
|
|
unsigned CB2_BURST_16 : 1; //!< [2] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB2
|
|
unsigned CB3_BURST_16 : 1; //!< [3] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB3
|
|
unsigned CB4_BURST_16 : 1; //!< [4] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB4
|
|
unsigned CB5_BURST_16 : 1; //!< [5] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB5
|
|
unsigned CB6_BURST_16 : 1; //!< [6] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB6
|
|
unsigned CB7_BURST_16 : 1; //!< [7] This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC for IC's CB7
|
|
unsigned RESERVED0 : 3; //!< [10:8] Reserved
|
|
unsigned T1_ROT : 1; //!< [11] Rotation for Encoding (ENC) task
|
|
unsigned T1_FLIP_LR : 1; //!< [12] LEFT/RIGHT flip for Encoding (ENC) task; this bit affect the flipping done on the rotation unit
|
|
unsigned T1_FLIP_UD : 1; //!< [13] UP/DOWN flip for Encoding (ENC) task
|
|
unsigned T2_ROT : 1; //!< [14] Rotation for View Finder (VF) task
|
|
unsigned T2_FLIP_LR : 1; //!< [15] LEFT/RIGHT flip for View Finder (VF) task; this bit affect the flipping done on the rotation unit
|
|
unsigned T2_FLIP_UD : 1; //!< [16] UP/DOWN flip for View Finder (VF) task
|
|
unsigned T3_ROT : 1; //!< [17] Rotation for Post Processing (PP) task
|
|
unsigned T3_FLIP_LR : 1; //!< [18] LEFT/RIGHT flip for Post Processing (PP) task; this bit affect the flipping done on the rotation unit
|
|
unsigned T3_FLIP_UD : 1; //!< [19] UP/DOWN flip for Post Processing (PP) task
|
|
unsigned T1_FLIP_RS : 1; //!< [20] LEFT/RIGHT flip for Encoding (ENC) task; this bit affect the flipping done on the resizing unit.
|
|
unsigned T2_FLIP_RS : 1; //!< [21] LEFT/RIGHT flip for View Finder (VF) task; this bit affect the flipping done on the resizing unit.
|
|
unsigned T3_FLIP_RS : 1; //!< [22] LEFT/RIGHT flip for Post Processing (PP) task; his bit affect the flipping done on the resizing unit.
|
|
unsigned RESERVED1 : 1; //!< [23] Reserved
|
|
unsigned ALT_CB6_BURST_16 : 1; //!< [24] Reserved
|
|
unsigned ALT_CB7_BURST_16 : 1; //!< [25] Reserved
|
|
unsigned RESERVED2 : 6; //!< [31:26] Reserved
|
|
} B;
|
|
} hw_ipu_ic_idmac_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_IDMAC_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_IDMAC_1_ADDR(x) (REGS_IPU_BASE(x) + 0x20018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_IDMAC_1(x) (*(volatile hw_ipu_ic_idmac_1_t *) HW_IPU_IC_IDMAC_1_ADDR(x))
|
|
#define HW_IPU_IC_IDMAC_1_RD(x) (HW_IPU_IC_IDMAC_1(x).U)
|
|
#define HW_IPU_IC_IDMAC_1_WR(x, v) (HW_IPU_IC_IDMAC_1(x).U = (v))
|
|
#define HW_IPU_IC_IDMAC_1_SET(x, v) (HW_IPU_IC_IDMAC_1_WR(x, HW_IPU_IC_IDMAC_1_RD(x) | (v)))
|
|
#define HW_IPU_IC_IDMAC_1_CLR(x, v) (HW_IPU_IC_IDMAC_1_WR(x, HW_IPU_IC_IDMAC_1_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_IDMAC_1_TOG(x, v) (HW_IPU_IC_IDMAC_1_WR(x, HW_IPU_IC_IDMAC_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_IDMAC_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB0_BURST_16[0] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB0 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB0_BURST_16 (0) //!< Bit position for IPU_IC_IDMAC_1_CB0_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB0_BURST_16 (0x00000001) //!< Bit mask for IPU_IC_IDMAC_1_CB0_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB0_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB0_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB0_BURST_16) >> BP_IPU_IC_IDMAC_1_CB0_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB0_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB0_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB0_BURST_16) & BM_IPU_IC_IDMAC_1_CB0_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB0_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB0_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB0_BURST_16) | BF_IPU_IC_IDMAC_1_CB0_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB1_BURST_16[1] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB1 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB1_BURST_16 (1) //!< Bit position for IPU_IC_IDMAC_1_CB1_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB1_BURST_16 (0x00000002) //!< Bit mask for IPU_IC_IDMAC_1_CB1_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB1_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB1_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB1_BURST_16) >> BP_IPU_IC_IDMAC_1_CB1_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB1_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB1_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB1_BURST_16) & BM_IPU_IC_IDMAC_1_CB1_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB1_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB1_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB1_BURST_16) | BF_IPU_IC_IDMAC_1_CB1_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB2_BURST_16[2] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB2 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB2_BURST_16 (2) //!< Bit position for IPU_IC_IDMAC_1_CB2_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB2_BURST_16 (0x00000004) //!< Bit mask for IPU_IC_IDMAC_1_CB2_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB2_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB2_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB2_BURST_16) >> BP_IPU_IC_IDMAC_1_CB2_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB2_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB2_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB2_BURST_16) & BM_IPU_IC_IDMAC_1_CB2_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB2_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB2_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB2_BURST_16) | BF_IPU_IC_IDMAC_1_CB2_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB3_BURST_16[3] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB3 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB3_BURST_16 (3) //!< Bit position for IPU_IC_IDMAC_1_CB3_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB3_BURST_16 (0x00000008) //!< Bit mask for IPU_IC_IDMAC_1_CB3_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB3_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB3_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB3_BURST_16) >> BP_IPU_IC_IDMAC_1_CB3_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB3_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB3_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB3_BURST_16) & BM_IPU_IC_IDMAC_1_CB3_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB3_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB3_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB3_BURST_16) | BF_IPU_IC_IDMAC_1_CB3_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB4_BURST_16[4] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB4 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB4_BURST_16 (4) //!< Bit position for IPU_IC_IDMAC_1_CB4_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB4_BURST_16 (0x00000010) //!< Bit mask for IPU_IC_IDMAC_1_CB4_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB4_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB4_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB4_BURST_16) >> BP_IPU_IC_IDMAC_1_CB4_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB4_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB4_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB4_BURST_16) & BM_IPU_IC_IDMAC_1_CB4_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB4_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB4_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB4_BURST_16) | BF_IPU_IC_IDMAC_1_CB4_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB5_BURST_16[5] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB5 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB5_BURST_16 (5) //!< Bit position for IPU_IC_IDMAC_1_CB5_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB5_BURST_16 (0x00000020) //!< Bit mask for IPU_IC_IDMAC_1_CB5_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB5_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB5_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB5_BURST_16) >> BP_IPU_IC_IDMAC_1_CB5_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB5_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB5_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB5_BURST_16) & BM_IPU_IC_IDMAC_1_CB5_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB5_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB5_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB5_BURST_16) | BF_IPU_IC_IDMAC_1_CB5_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB6_BURST_16[6] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB6 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB6_BURST_16 (6) //!< Bit position for IPU_IC_IDMAC_1_CB6_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB6_BURST_16 (0x00000040) //!< Bit mask for IPU_IC_IDMAC_1_CB6_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB6_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB6_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB6_BURST_16) >> BP_IPU_IC_IDMAC_1_CB6_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB6_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB6_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB6_BURST_16) & BM_IPU_IC_IDMAC_1_CB6_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB6_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB6_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB6_BURST_16) | BF_IPU_IC_IDMAC_1_CB6_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field CB7_BURST_16[7] (RW)
|
|
*
|
|
* This bit defines the number of active cycles within a burst (burst size) coming from the IDMAC
|
|
* for IC's CB7 For pixel data the number of pixels should match the NPB[6:2] value on the IDMAC's
|
|
* CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 8 pixels; The Matching NPB[6:2] should be 00111
|
|
* - 1 - Burst size is 16 pixels; The Matching NPB[6:2] should be 01111
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_CB7_BURST_16 (7) //!< Bit position for IPU_IC_IDMAC_1_CB7_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_CB7_BURST_16 (0x00000080) //!< Bit mask for IPU_IC_IDMAC_1_CB7_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_CB7_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_CB7_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_CB7_BURST_16) >> BP_IPU_IC_IDMAC_1_CB7_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_CB7_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_CB7_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_CB7_BURST_16) & BM_IPU_IC_IDMAC_1_CB7_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CB7_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_CB7_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_CB7_BURST_16) | BF_IPU_IC_IDMAC_1_CB7_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T1_ROT[11] (RW)
|
|
*
|
|
* Rotation for Encoding (ENC) task The value of this field must be identical to the corresponding
|
|
* channel's ROT parameters in the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no rotation
|
|
* - 1 - 90 degree rotation clockwise
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T1_ROT (11) //!< Bit position for IPU_IC_IDMAC_1_T1_ROT.
|
|
#define BM_IPU_IC_IDMAC_1_T1_ROT (0x00000800) //!< Bit mask for IPU_IC_IDMAC_1_T1_ROT.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T1_ROT from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T1_ROT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T1_ROT) >> BP_IPU_IC_IDMAC_1_T1_ROT)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T1_ROT.
|
|
#define BF_IPU_IC_IDMAC_1_T1_ROT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T1_ROT) & BM_IPU_IC_IDMAC_1_T1_ROT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T1_ROT field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T1_ROT(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T1_ROT) | BF_IPU_IC_IDMAC_1_T1_ROT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T1_FLIP_LR[12] (RW)
|
|
*
|
|
* LEFT/RIGHT flip for Encoding (ENC) task; this bit affect the flipping done on the rotation unit
|
|
* The value of this field must be identical to the corresponding channel's HF parameter in the
|
|
* IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - horizontal flip enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T1_FLIP_LR (12) //!< Bit position for IPU_IC_IDMAC_1_T1_FLIP_LR.
|
|
#define BM_IPU_IC_IDMAC_1_T1_FLIP_LR (0x00001000) //!< Bit mask for IPU_IC_IDMAC_1_T1_FLIP_LR.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T1_FLIP_LR from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T1_FLIP_LR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T1_FLIP_LR) >> BP_IPU_IC_IDMAC_1_T1_FLIP_LR)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T1_FLIP_LR.
|
|
#define BF_IPU_IC_IDMAC_1_T1_FLIP_LR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T1_FLIP_LR) & BM_IPU_IC_IDMAC_1_T1_FLIP_LR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T1_FLIP_LR field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T1_FLIP_LR(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T1_FLIP_LR) | BF_IPU_IC_IDMAC_1_T1_FLIP_LR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T1_FLIP_UD[13] (RW)
|
|
*
|
|
* UP/DOWN flip for Encoding (ENC) task The value of this field must be identical to the
|
|
* corresponding channel's VF parameters in the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - Vertical flip enable
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T1_FLIP_UD (13) //!< Bit position for IPU_IC_IDMAC_1_T1_FLIP_UD.
|
|
#define BM_IPU_IC_IDMAC_1_T1_FLIP_UD (0x00002000) //!< Bit mask for IPU_IC_IDMAC_1_T1_FLIP_UD.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T1_FLIP_UD from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T1_FLIP_UD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T1_FLIP_UD) >> BP_IPU_IC_IDMAC_1_T1_FLIP_UD)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T1_FLIP_UD.
|
|
#define BF_IPU_IC_IDMAC_1_T1_FLIP_UD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T1_FLIP_UD) & BM_IPU_IC_IDMAC_1_T1_FLIP_UD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T1_FLIP_UD field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T1_FLIP_UD(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T1_FLIP_UD) | BF_IPU_IC_IDMAC_1_T1_FLIP_UD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T2_ROT[14] (RW)
|
|
*
|
|
* Rotation for View Finder (VF) task The value of this field must be identical to the corresponding
|
|
* channel's ROT parameters in the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no rotation
|
|
* - 1 - 90 degree rotation clockwise
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T2_ROT (14) //!< Bit position for IPU_IC_IDMAC_1_T2_ROT.
|
|
#define BM_IPU_IC_IDMAC_1_T2_ROT (0x00004000) //!< Bit mask for IPU_IC_IDMAC_1_T2_ROT.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T2_ROT from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T2_ROT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T2_ROT) >> BP_IPU_IC_IDMAC_1_T2_ROT)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T2_ROT.
|
|
#define BF_IPU_IC_IDMAC_1_T2_ROT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T2_ROT) & BM_IPU_IC_IDMAC_1_T2_ROT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T2_ROT field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T2_ROT(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T2_ROT) | BF_IPU_IC_IDMAC_1_T2_ROT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T2_FLIP_LR[15] (RW)
|
|
*
|
|
* LEFT/RIGHT flip for View Finder (VF) task; this bit affect the flipping done on the rotation unit
|
|
* The value of this field must be identical to the corresponding channel's HF parameter in the
|
|
* IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - horizontal flip enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T2_FLIP_LR (15) //!< Bit position for IPU_IC_IDMAC_1_T2_FLIP_LR.
|
|
#define BM_IPU_IC_IDMAC_1_T2_FLIP_LR (0x00008000) //!< Bit mask for IPU_IC_IDMAC_1_T2_FLIP_LR.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T2_FLIP_LR from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T2_FLIP_LR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T2_FLIP_LR) >> BP_IPU_IC_IDMAC_1_T2_FLIP_LR)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T2_FLIP_LR.
|
|
#define BF_IPU_IC_IDMAC_1_T2_FLIP_LR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T2_FLIP_LR) & BM_IPU_IC_IDMAC_1_T2_FLIP_LR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T2_FLIP_LR field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T2_FLIP_LR(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T2_FLIP_LR) | BF_IPU_IC_IDMAC_1_T2_FLIP_LR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T2_FLIP_UD[16] (RW)
|
|
*
|
|
* UP/DOWN flip for View Finder (VF) task The value of this field must be identical to the
|
|
* corresponding channel's VF parameters in the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - Vertical flip enable
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T2_FLIP_UD (16) //!< Bit position for IPU_IC_IDMAC_1_T2_FLIP_UD.
|
|
#define BM_IPU_IC_IDMAC_1_T2_FLIP_UD (0x00010000) //!< Bit mask for IPU_IC_IDMAC_1_T2_FLIP_UD.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T2_FLIP_UD from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T2_FLIP_UD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T2_FLIP_UD) >> BP_IPU_IC_IDMAC_1_T2_FLIP_UD)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T2_FLIP_UD.
|
|
#define BF_IPU_IC_IDMAC_1_T2_FLIP_UD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T2_FLIP_UD) & BM_IPU_IC_IDMAC_1_T2_FLIP_UD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T2_FLIP_UD field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T2_FLIP_UD(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T2_FLIP_UD) | BF_IPU_IC_IDMAC_1_T2_FLIP_UD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T3_ROT[17] (RW)
|
|
*
|
|
* Rotation for Post Processing (PP) task The value of this field must be identical to the
|
|
* corresponding channel's ROT parameters in the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no rotation
|
|
* - 1 - 90 degree rotation clockwise
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T3_ROT (17) //!< Bit position for IPU_IC_IDMAC_1_T3_ROT.
|
|
#define BM_IPU_IC_IDMAC_1_T3_ROT (0x00020000) //!< Bit mask for IPU_IC_IDMAC_1_T3_ROT.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T3_ROT from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T3_ROT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T3_ROT) >> BP_IPU_IC_IDMAC_1_T3_ROT)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T3_ROT.
|
|
#define BF_IPU_IC_IDMAC_1_T3_ROT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T3_ROT) & BM_IPU_IC_IDMAC_1_T3_ROT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T3_ROT field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T3_ROT(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T3_ROT) | BF_IPU_IC_IDMAC_1_T3_ROT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T3_FLIP_LR[18] (RW)
|
|
*
|
|
* LEFT/RIGHT flip for Post Processing (PP) task; this bit affect the flipping done on the rotation
|
|
* unit The value of this field must be identical to the corresponding channel's HF parameter in the
|
|
* IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - horizontal flip enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T3_FLIP_LR (18) //!< Bit position for IPU_IC_IDMAC_1_T3_FLIP_LR.
|
|
#define BM_IPU_IC_IDMAC_1_T3_FLIP_LR (0x00040000) //!< Bit mask for IPU_IC_IDMAC_1_T3_FLIP_LR.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T3_FLIP_LR from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T3_FLIP_LR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T3_FLIP_LR) >> BP_IPU_IC_IDMAC_1_T3_FLIP_LR)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T3_FLIP_LR.
|
|
#define BF_IPU_IC_IDMAC_1_T3_FLIP_LR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T3_FLIP_LR) & BM_IPU_IC_IDMAC_1_T3_FLIP_LR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T3_FLIP_LR field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T3_FLIP_LR(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T3_FLIP_LR) | BF_IPU_IC_IDMAC_1_T3_FLIP_LR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T3_FLIP_UD[19] (RW)
|
|
*
|
|
* UP/DOWN flip for Post Processing (PP) task The value of this field must be identical to the
|
|
* corresponding channel's VF parameters in the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - Vertical flip enable
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T3_FLIP_UD (19) //!< Bit position for IPU_IC_IDMAC_1_T3_FLIP_UD.
|
|
#define BM_IPU_IC_IDMAC_1_T3_FLIP_UD (0x00080000) //!< Bit mask for IPU_IC_IDMAC_1_T3_FLIP_UD.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T3_FLIP_UD from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T3_FLIP_UD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T3_FLIP_UD) >> BP_IPU_IC_IDMAC_1_T3_FLIP_UD)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T3_FLIP_UD.
|
|
#define BF_IPU_IC_IDMAC_1_T3_FLIP_UD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T3_FLIP_UD) & BM_IPU_IC_IDMAC_1_T3_FLIP_UD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T3_FLIP_UD field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T3_FLIP_UD(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T3_FLIP_UD) | BF_IPU_IC_IDMAC_1_T3_FLIP_UD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T1_FLIP_RS[20] (RW)
|
|
*
|
|
* LEFT/RIGHT flip for Encoding (ENC) task; this bit affect the flipping done on the resizing unit.
|
|
* The value of this field must be identical to the corresponding channel's HF parameter in the
|
|
* IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - horizontal flip enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T1_FLIP_RS (20) //!< Bit position for IPU_IC_IDMAC_1_T1_FLIP_RS.
|
|
#define BM_IPU_IC_IDMAC_1_T1_FLIP_RS (0x00100000) //!< Bit mask for IPU_IC_IDMAC_1_T1_FLIP_RS.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T1_FLIP_RS from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T1_FLIP_RS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T1_FLIP_RS) >> BP_IPU_IC_IDMAC_1_T1_FLIP_RS)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T1_FLIP_RS.
|
|
#define BF_IPU_IC_IDMAC_1_T1_FLIP_RS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T1_FLIP_RS) & BM_IPU_IC_IDMAC_1_T1_FLIP_RS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T1_FLIP_RS field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T1_FLIP_RS(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T1_FLIP_RS) | BF_IPU_IC_IDMAC_1_T1_FLIP_RS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T2_FLIP_RS[21] (RW)
|
|
*
|
|
* LEFT/RIGHT flip for View Finder (VF) task; this bit affect the flipping done on the resizing
|
|
* unit. The value of this field must be identical to the corresponding channel's HF parameter in
|
|
* the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - horizontal flip enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T2_FLIP_RS (21) //!< Bit position for IPU_IC_IDMAC_1_T2_FLIP_RS.
|
|
#define BM_IPU_IC_IDMAC_1_T2_FLIP_RS (0x00200000) //!< Bit mask for IPU_IC_IDMAC_1_T2_FLIP_RS.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T2_FLIP_RS from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T2_FLIP_RS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T2_FLIP_RS) >> BP_IPU_IC_IDMAC_1_T2_FLIP_RS)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T2_FLIP_RS.
|
|
#define BF_IPU_IC_IDMAC_1_T2_FLIP_RS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T2_FLIP_RS) & BM_IPU_IC_IDMAC_1_T2_FLIP_RS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T2_FLIP_RS field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T2_FLIP_RS(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T2_FLIP_RS) | BF_IPU_IC_IDMAC_1_T2_FLIP_RS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field T3_FLIP_RS[22] (RW)
|
|
*
|
|
* LEFT/RIGHT flip for Post Processing (PP) task; his bit affect the flipping done on the resizing
|
|
* unit. The value of this field must be identical to the corresponding channel's HF parameter in
|
|
* the IDMAC's CPMEM
|
|
*
|
|
* Values:
|
|
* - 0 - no flip
|
|
* - 1 - horizontal flip enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_T3_FLIP_RS (22) //!< Bit position for IPU_IC_IDMAC_1_T3_FLIP_RS.
|
|
#define BM_IPU_IC_IDMAC_1_T3_FLIP_RS (0x00400000) //!< Bit mask for IPU_IC_IDMAC_1_T3_FLIP_RS.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_T3_FLIP_RS from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_T3_FLIP_RS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_T3_FLIP_RS) >> BP_IPU_IC_IDMAC_1_T3_FLIP_RS)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_T3_FLIP_RS.
|
|
#define BF_IPU_IC_IDMAC_1_T3_FLIP_RS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_T3_FLIP_RS) & BM_IPU_IC_IDMAC_1_T3_FLIP_RS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T3_FLIP_RS field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_T3_FLIP_RS(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_T3_FLIP_RS) | BF_IPU_IC_IDMAC_1_T3_FLIP_RS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field ALT_CB6_BURST_16[24] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_ALT_CB6_BURST_16 (24) //!< Bit position for IPU_IC_IDMAC_1_ALT_CB6_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_ALT_CB6_BURST_16 (0x01000000) //!< Bit mask for IPU_IC_IDMAC_1_ALT_CB6_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_ALT_CB6_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_ALT_CB6_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_ALT_CB6_BURST_16) >> BP_IPU_IC_IDMAC_1_ALT_CB6_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_ALT_CB6_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_ALT_CB6_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_ALT_CB6_BURST_16) & BM_IPU_IC_IDMAC_1_ALT_CB6_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ALT_CB6_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_ALT_CB6_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_ALT_CB6_BURST_16) | BF_IPU_IC_IDMAC_1_ALT_CB6_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_1, field ALT_CB7_BURST_16[25] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_1_ALT_CB7_BURST_16 (25) //!< Bit position for IPU_IC_IDMAC_1_ALT_CB7_BURST_16.
|
|
#define BM_IPU_IC_IDMAC_1_ALT_CB7_BURST_16 (0x02000000) //!< Bit mask for IPU_IC_IDMAC_1_ALT_CB7_BURST_16.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_1_ALT_CB7_BURST_16 from a register value.
|
|
#define BG_IPU_IC_IDMAC_1_ALT_CB7_BURST_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_1_ALT_CB7_BURST_16) >> BP_IPU_IC_IDMAC_1_ALT_CB7_BURST_16)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_1_ALT_CB7_BURST_16.
|
|
#define BF_IPU_IC_IDMAC_1_ALT_CB7_BURST_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_1_ALT_CB7_BURST_16) & BM_IPU_IC_IDMAC_1_ALT_CB7_BURST_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ALT_CB7_BURST_16 field to a new value.
|
|
#define BW_IPU_IC_IDMAC_1_ALT_CB7_BURST_16(x, v) (HW_IPU_IC_IDMAC_1_WR(x, (HW_IPU_IC_IDMAC_1_RD(x) & ~BM_IPU_IC_IDMAC_1_ALT_CB7_BURST_16) | BF_IPU_IC_IDMAC_1_ALT_CB7_BURST_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_IDMAC_2 - IC IDMAC Parameters 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_IDMAC_2 - IC IDMAC Parameters 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_ic_idmac_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_idmac_2_bitfields
|
|
{
|
|
unsigned T1_FR_HEIGHT : 10; //!< [9:0] Frame Height for Encoding (ENC) task
|
|
unsigned T2_FR_HEIGHT : 10; //!< [19:10] Frame Height for View Finder (VF) task
|
|
unsigned T3_FR_HEIGHT : 10; //!< [29:20] Frame Height for Post Processing (PP) task
|
|
unsigned RESERVED0 : 2; //!< [31:30] Reserved
|
|
} B;
|
|
} hw_ipu_ic_idmac_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_IDMAC_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_IDMAC_2_ADDR(x) (REGS_IPU_BASE(x) + 0x2001c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_IDMAC_2(x) (*(volatile hw_ipu_ic_idmac_2_t *) HW_IPU_IC_IDMAC_2_ADDR(x))
|
|
#define HW_IPU_IC_IDMAC_2_RD(x) (HW_IPU_IC_IDMAC_2(x).U)
|
|
#define HW_IPU_IC_IDMAC_2_WR(x, v) (HW_IPU_IC_IDMAC_2(x).U = (v))
|
|
#define HW_IPU_IC_IDMAC_2_SET(x, v) (HW_IPU_IC_IDMAC_2_WR(x, HW_IPU_IC_IDMAC_2_RD(x) | (v)))
|
|
#define HW_IPU_IC_IDMAC_2_CLR(x, v) (HW_IPU_IC_IDMAC_2_WR(x, HW_IPU_IC_IDMAC_2_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_IDMAC_2_TOG(x, v) (HW_IPU_IC_IDMAC_2_WR(x, HW_IPU_IC_IDMAC_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_IDMAC_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_IDMAC_2, field T1_FR_HEIGHT[9:0] (RW)
|
|
*
|
|
* Frame Height for Encoding (ENC) task The value of this field must be identical to corresponding
|
|
* FH channel's parameters in the IDMAC's CPMEM. This parameter refers to the output's size -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_2_T1_FR_HEIGHT (0) //!< Bit position for IPU_IC_IDMAC_2_T1_FR_HEIGHT.
|
|
#define BM_IPU_IC_IDMAC_2_T1_FR_HEIGHT (0x000003ff) //!< Bit mask for IPU_IC_IDMAC_2_T1_FR_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_2_T1_FR_HEIGHT from a register value.
|
|
#define BG_IPU_IC_IDMAC_2_T1_FR_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_2_T1_FR_HEIGHT) >> BP_IPU_IC_IDMAC_2_T1_FR_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_2_T1_FR_HEIGHT.
|
|
#define BF_IPU_IC_IDMAC_2_T1_FR_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_2_T1_FR_HEIGHT) & BM_IPU_IC_IDMAC_2_T1_FR_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T1_FR_HEIGHT field to a new value.
|
|
#define BW_IPU_IC_IDMAC_2_T1_FR_HEIGHT(x, v) (HW_IPU_IC_IDMAC_2_WR(x, (HW_IPU_IC_IDMAC_2_RD(x) & ~BM_IPU_IC_IDMAC_2_T1_FR_HEIGHT) | BF_IPU_IC_IDMAC_2_T1_FR_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_2, field T2_FR_HEIGHT[19:10] (RW)
|
|
*
|
|
* Frame Height for View Finder (VF) task The value of this field must be identical to the
|
|
* corresponding FH channel's parameters in the IDMAC's CPMEM. This parameter refers to the output's
|
|
* size -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_2_T2_FR_HEIGHT (10) //!< Bit position for IPU_IC_IDMAC_2_T2_FR_HEIGHT.
|
|
#define BM_IPU_IC_IDMAC_2_T2_FR_HEIGHT (0x000ffc00) //!< Bit mask for IPU_IC_IDMAC_2_T2_FR_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_2_T2_FR_HEIGHT from a register value.
|
|
#define BG_IPU_IC_IDMAC_2_T2_FR_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_2_T2_FR_HEIGHT) >> BP_IPU_IC_IDMAC_2_T2_FR_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_2_T2_FR_HEIGHT.
|
|
#define BF_IPU_IC_IDMAC_2_T2_FR_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_2_T2_FR_HEIGHT) & BM_IPU_IC_IDMAC_2_T2_FR_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T2_FR_HEIGHT field to a new value.
|
|
#define BW_IPU_IC_IDMAC_2_T2_FR_HEIGHT(x, v) (HW_IPU_IC_IDMAC_2_WR(x, (HW_IPU_IC_IDMAC_2_RD(x) & ~BM_IPU_IC_IDMAC_2_T2_FR_HEIGHT) | BF_IPU_IC_IDMAC_2_T2_FR_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_2, field T3_FR_HEIGHT[29:20] (RW)
|
|
*
|
|
* Frame Height for Post Processing (PP) task The value of this field must be identical to the
|
|
* corresponding FH channel's parameters in the IDMAC's CPMEM. This parameter refers to the output's
|
|
* size -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_2_T3_FR_HEIGHT (20) //!< Bit position for IPU_IC_IDMAC_2_T3_FR_HEIGHT.
|
|
#define BM_IPU_IC_IDMAC_2_T3_FR_HEIGHT (0x3ff00000) //!< Bit mask for IPU_IC_IDMAC_2_T3_FR_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_2_T3_FR_HEIGHT from a register value.
|
|
#define BG_IPU_IC_IDMAC_2_T3_FR_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_2_T3_FR_HEIGHT) >> BP_IPU_IC_IDMAC_2_T3_FR_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_2_T3_FR_HEIGHT.
|
|
#define BF_IPU_IC_IDMAC_2_T3_FR_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_2_T3_FR_HEIGHT) & BM_IPU_IC_IDMAC_2_T3_FR_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T3_FR_HEIGHT field to a new value.
|
|
#define BW_IPU_IC_IDMAC_2_T3_FR_HEIGHT(x, v) (HW_IPU_IC_IDMAC_2_WR(x, (HW_IPU_IC_IDMAC_2_RD(x) & ~BM_IPU_IC_IDMAC_2_T3_FR_HEIGHT) | BF_IPU_IC_IDMAC_2_T3_FR_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_IDMAC_3 - IC IDMAC Parameters 3Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_IDMAC_3 - IC IDMAC Parameters 3Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_ic_idmac_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_idmac_3_bitfields
|
|
{
|
|
unsigned T1_FR_WIDTH : 10; //!< [9:0] Frame Width for Encoding (ENC) task
|
|
unsigned T2_FR_WIDTH : 10; //!< [19:10] Frame Width for View Finder (VF) task
|
|
unsigned T3_FR_WIDTH : 10; //!< [29:20] Frame Width for Post Processing (PP) task
|
|
unsigned RESERVED0 : 2; //!< [31:30] Reserved
|
|
} B;
|
|
} hw_ipu_ic_idmac_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_IDMAC_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_IDMAC_3_ADDR(x) (REGS_IPU_BASE(x) + 0x20020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_IDMAC_3(x) (*(volatile hw_ipu_ic_idmac_3_t *) HW_IPU_IC_IDMAC_3_ADDR(x))
|
|
#define HW_IPU_IC_IDMAC_3_RD(x) (HW_IPU_IC_IDMAC_3(x).U)
|
|
#define HW_IPU_IC_IDMAC_3_WR(x, v) (HW_IPU_IC_IDMAC_3(x).U = (v))
|
|
#define HW_IPU_IC_IDMAC_3_SET(x, v) (HW_IPU_IC_IDMAC_3_WR(x, HW_IPU_IC_IDMAC_3_RD(x) | (v)))
|
|
#define HW_IPU_IC_IDMAC_3_CLR(x, v) (HW_IPU_IC_IDMAC_3_WR(x, HW_IPU_IC_IDMAC_3_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_IDMAC_3_TOG(x, v) (HW_IPU_IC_IDMAC_3_WR(x, HW_IPU_IC_IDMAC_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_IDMAC_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_IDMAC_3, field T1_FR_WIDTH[9:0] (RW)
|
|
*
|
|
* Frame Width for Encoding (ENC) task The value of this field must be identical to corresponding FW
|
|
* channel's parameters in the IDMAC's CPMEM. This parameter refers to the output's size -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_3_T1_FR_WIDTH (0) //!< Bit position for IPU_IC_IDMAC_3_T1_FR_WIDTH.
|
|
#define BM_IPU_IC_IDMAC_3_T1_FR_WIDTH (0x000003ff) //!< Bit mask for IPU_IC_IDMAC_3_T1_FR_WIDTH.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_3_T1_FR_WIDTH from a register value.
|
|
#define BG_IPU_IC_IDMAC_3_T1_FR_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_3_T1_FR_WIDTH) >> BP_IPU_IC_IDMAC_3_T1_FR_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_3_T1_FR_WIDTH.
|
|
#define BF_IPU_IC_IDMAC_3_T1_FR_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_3_T1_FR_WIDTH) & BM_IPU_IC_IDMAC_3_T1_FR_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T1_FR_WIDTH field to a new value.
|
|
#define BW_IPU_IC_IDMAC_3_T1_FR_WIDTH(x, v) (HW_IPU_IC_IDMAC_3_WR(x, (HW_IPU_IC_IDMAC_3_RD(x) & ~BM_IPU_IC_IDMAC_3_T1_FR_WIDTH) | BF_IPU_IC_IDMAC_3_T1_FR_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_3, field T2_FR_WIDTH[19:10] (RW)
|
|
*
|
|
* Frame Width for View Finder (VF) task The value of this field must be identical to the
|
|
* corresponding FW channel's parameters in the IDMAC's CPMEM. This parameter refers to the output's
|
|
* size -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_3_T2_FR_WIDTH (10) //!< Bit position for IPU_IC_IDMAC_3_T2_FR_WIDTH.
|
|
#define BM_IPU_IC_IDMAC_3_T2_FR_WIDTH (0x000ffc00) //!< Bit mask for IPU_IC_IDMAC_3_T2_FR_WIDTH.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_3_T2_FR_WIDTH from a register value.
|
|
#define BG_IPU_IC_IDMAC_3_T2_FR_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_3_T2_FR_WIDTH) >> BP_IPU_IC_IDMAC_3_T2_FR_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_3_T2_FR_WIDTH.
|
|
#define BF_IPU_IC_IDMAC_3_T2_FR_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_3_T2_FR_WIDTH) & BM_IPU_IC_IDMAC_3_T2_FR_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T2_FR_WIDTH field to a new value.
|
|
#define BW_IPU_IC_IDMAC_3_T2_FR_WIDTH(x, v) (HW_IPU_IC_IDMAC_3_WR(x, (HW_IPU_IC_IDMAC_3_RD(x) & ~BM_IPU_IC_IDMAC_3_T2_FR_WIDTH) | BF_IPU_IC_IDMAC_3_T2_FR_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_3, field T3_FR_WIDTH[29:20] (RW)
|
|
*
|
|
* Frame Width for Post Processing (PP) task The value of this field must be identical to the
|
|
* corresponding FW channel's parameters in the IDMAC's CPMEM. This parameter refers to the output's
|
|
* size -1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_3_T3_FR_WIDTH (20) //!< Bit position for IPU_IC_IDMAC_3_T3_FR_WIDTH.
|
|
#define BM_IPU_IC_IDMAC_3_T3_FR_WIDTH (0x3ff00000) //!< Bit mask for IPU_IC_IDMAC_3_T3_FR_WIDTH.
|
|
|
|
//! @brief Get value of IPU_IC_IDMAC_3_T3_FR_WIDTH from a register value.
|
|
#define BG_IPU_IC_IDMAC_3_T3_FR_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_3_T3_FR_WIDTH) >> BP_IPU_IC_IDMAC_3_T3_FR_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_3_T3_FR_WIDTH.
|
|
#define BF_IPU_IC_IDMAC_3_T3_FR_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_3_T3_FR_WIDTH) & BM_IPU_IC_IDMAC_3_T3_FR_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the T3_FR_WIDTH field to a new value.
|
|
#define BW_IPU_IC_IDMAC_3_T3_FR_WIDTH(x, v) (HW_IPU_IC_IDMAC_3_WR(x, (HW_IPU_IC_IDMAC_3_RD(x) & ~BM_IPU_IC_IDMAC_3_T3_FR_WIDTH) | BF_IPU_IC_IDMAC_3_T3_FR_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_IC_IDMAC_4 - IC IDMAC Parameters 4 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_IC_IDMAC_4 - IC IDMAC Parameters 4 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_ic_idmac_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_ic_idmac_4_bitfields
|
|
{
|
|
unsigned MPM_RW_BRDG_MAX_RQ : 4; //!< [3:0] MPM memory Bridge Max Requests between MPM's read and writes
|
|
unsigned MPM_DMFC_BRDG_MAX_RQ : 4; //!< [7:4] MPM memory Bridge Max Requests for the IC DMFC interface
|
|
unsigned IBM_BRDG_MAX_RQ : 4; //!< [11:8] IBM memory Bridge Max Requests
|
|
unsigned RM_BRDG_MAX_RQ : 4; //!< [15:12] RM memory Bridge Max Requests
|
|
unsigned RESERVED0 : 16; //!< [31:16] Reserved
|
|
} B;
|
|
} hw_ipu_ic_idmac_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_IC_IDMAC_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_IC_IDMAC_4_ADDR(x) (REGS_IPU_BASE(x) + 0x20024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_IC_IDMAC_4(x) (*(volatile hw_ipu_ic_idmac_4_t *) HW_IPU_IC_IDMAC_4_ADDR(x))
|
|
#define HW_IPU_IC_IDMAC_4_RD(x) (HW_IPU_IC_IDMAC_4(x).U)
|
|
#define HW_IPU_IC_IDMAC_4_WR(x, v) (HW_IPU_IC_IDMAC_4(x).U = (v))
|
|
#define HW_IPU_IC_IDMAC_4_SET(x, v) (HW_IPU_IC_IDMAC_4_WR(x, HW_IPU_IC_IDMAC_4_RD(x) | (v)))
|
|
#define HW_IPU_IC_IDMAC_4_CLR(x, v) (HW_IPU_IC_IDMAC_4_WR(x, HW_IPU_IC_IDMAC_4_RD(x) & ~(v)))
|
|
#define HW_IPU_IC_IDMAC_4_TOG(x, v) (HW_IPU_IC_IDMAC_4_WR(x, HW_IPU_IC_IDMAC_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_IC_IDMAC_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_IC_IDMAC_4, field MPM_RW_BRDG_MAX_RQ[3:0] (RW)
|
|
*
|
|
* MPM memory Bridge Max Requests between MPM's read and writes
|
|
*
|
|
* Values:
|
|
* - 0000 - Feature is disabled
|
|
* - 0001 - Max request is 1
|
|
* - 1111 - Max request are15
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ (0) //!< Bit position for IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ.
|
|
#define BM_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ (0x0000000f) //!< Bit mask for IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ.
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|
|
|
//! @brief Get value of IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ from a register value.
|
|
#define BG_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ) >> BP_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ)
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|
|
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//! @brief Format value for bitfield IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ.
|
|
#define BF_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ) & BM_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MPM_RW_BRDG_MAX_RQ field to a new value.
|
|
#define BW_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ(x, v) (HW_IPU_IC_IDMAC_4_WR(x, (HW_IPU_IC_IDMAC_4_RD(x) & ~BM_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ) | BF_IPU_IC_IDMAC_4_MPM_RW_BRDG_MAX_RQ(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_IC_IDMAC_4, field MPM_DMFC_BRDG_MAX_RQ[7:4] (RW)
|
|
*
|
|
* MPM memory Bridge Max Requests for the IC DMFC interface
|
|
*
|
|
* Values:
|
|
* - 0000 - Feature is disabled
|
|
* - 0001 - Max request is 1
|
|
* - 1111 - Max request are15
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ (4) //!< Bit position for IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ.
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|
#define BM_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ (0x000000f0) //!< Bit mask for IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ.
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|
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//! @brief Get value of IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ from a register value.
|
|
#define BG_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ) >> BP_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ)
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//! @brief Format value for bitfield IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ.
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|
#define BF_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ) & BM_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the MPM_DMFC_BRDG_MAX_RQ field to a new value.
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|
#define BW_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ(x, v) (HW_IPU_IC_IDMAC_4_WR(x, (HW_IPU_IC_IDMAC_4_RD(x) & ~BM_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ) | BF_IPU_IC_IDMAC_4_MPM_DMFC_BRDG_MAX_RQ(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_IC_IDMAC_4, field IBM_BRDG_MAX_RQ[11:8] (RW)
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|
*
|
|
* IBM memory Bridge Max Requests
|
|
*
|
|
* Values:
|
|
* - 0000 - Feature is disabled
|
|
* - 0001 - Max request is 1
|
|
* - 1111 - Max request are15
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ (8) //!< Bit position for IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ.
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|
#define BM_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ (0x00000f00) //!< Bit mask for IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ.
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|
|
|
//! @brief Get value of IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ from a register value.
|
|
#define BG_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ) >> BP_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ)
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|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ.
|
|
#define BF_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ) & BM_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the IBM_BRDG_MAX_RQ field to a new value.
|
|
#define BW_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ(x, v) (HW_IPU_IC_IDMAC_4_WR(x, (HW_IPU_IC_IDMAC_4_RD(x) & ~BM_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ) | BF_IPU_IC_IDMAC_4_IBM_BRDG_MAX_RQ(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_IC_IDMAC_4, field RM_BRDG_MAX_RQ[15:12] (RW)
|
|
*
|
|
* RM memory Bridge Max Requests
|
|
*
|
|
* Values:
|
|
* - 0000 - Feature is disabled
|
|
* - 0001 - Max request is 1
|
|
* - 1111 - Max request are15
|
|
*/
|
|
//@{
|
|
#define BP_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ (12) //!< Bit position for IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ.
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|
#define BM_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ (0x0000f000) //!< Bit mask for IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ.
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|
|
|
//! @brief Get value of IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ from a register value.
|
|
#define BG_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ) >> BP_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ)
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|
|
|
//! @brief Format value for bitfield IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ.
|
|
#define BF_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ) & BM_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RM_BRDG_MAX_RQ field to a new value.
|
|
#define BW_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ(x, v) (HW_IPU_IC_IDMAC_4_WR(x, (HW_IPU_IC_IDMAC_4_RD(x) & ~BM_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ) | BF_IPU_IC_IDMAC_4_RM_BRDG_MAX_RQ(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_SENS_CONF - CSI0 Sensor Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_SENS_CONF - CSI0 Sensor Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_sens_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_sens_conf_bitfields
|
|
{
|
|
unsigned CSI0_VSYNC_POL : 1; //!< [0] Invert IPP_IND_SENSB_VSYNC input.
|
|
unsigned CSI0_HSYNC_POL : 1; //!< [1] Invert IPP_IND_SENSB_HSYNC input.
|
|
unsigned CSI0_DATA_POL : 1; //!< [2] Invert data input.
|
|
unsigned CSI0_SENS_PIX_CLK_POL : 1; //!< [3] Invert Pixel clock input.
|
|
unsigned CSI0_SENS_PRTCL : 3; //!< [6:4] Sensor Protocol.
|
|
unsigned CSI0_PACK_TIGHT : 1; //!< [7] CSI0 Pack Tight
|
|
unsigned CSI0_SENS_DATA_FORMAT : 3; //!< [10:8] Data format from the sensor.
|
|
unsigned CSI0_DATA_WIDTH : 4; //!< [14:11] Data width.
|
|
unsigned CSI0_EXT_VSYNC : 1; //!< [15] External VSYNC enable.
|
|
unsigned CSI0_DIV_RATIO : 8; //!< [23:16] DIV Ratio Clock division ratio minus 1.
|
|
unsigned CSI0_DATA_DEST : 3; //!< [26:24] These bits enable the destination of the data coming from the CSI.
|
|
unsigned CSI0_JPEG8_EN : 1; //!< [27] JPEG8 enable bit
|
|
unsigned CSI0_JPEG_MODE : 1; //!< [28] JPEG Mode - this bit defines the mode of the control signals when working in JPEG mode
|
|
unsigned CSI0_FORCE_EOF : 1; //!< [29] Force End of frame
|
|
unsigned RESERVED0 : 1; //!< [30] Reserved, should be cleared.
|
|
unsigned CSI0_DATA_EN_POL : 1; //!< [31] Invert IPP_IND_SENSB_DATA_EN input.
|
|
} B;
|
|
} hw_ipu_csi0_sens_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_SENS_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_SENS_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x30000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_SENS_CONF(x) (*(volatile hw_ipu_csi0_sens_conf_t *) HW_IPU_CSI0_SENS_CONF_ADDR(x))
|
|
#define HW_IPU_CSI0_SENS_CONF_RD(x) (HW_IPU_CSI0_SENS_CONF(x).U)
|
|
#define HW_IPU_CSI0_SENS_CONF_WR(x, v) (HW_IPU_CSI0_SENS_CONF(x).U = (v))
|
|
#define HW_IPU_CSI0_SENS_CONF_SET(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, HW_IPU_CSI0_SENS_CONF_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_SENS_CONF_CLR(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, HW_IPU_CSI0_SENS_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_SENS_CONF_TOG(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, HW_IPU_CSI0_SENS_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_SENS_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_VSYNC_POL[0] (RW)
|
|
*
|
|
* Invert IPP_IND_SENSB_VSYNC input. This bit selects the polarity of IPP_IND_SENSB_VSYNC signal.
|
|
*
|
|
* Values:
|
|
* - 0 - IPP_IND_SENSB_VSYNC is not inverted before applied to internal circuitry.
|
|
* - 1 - IPP_IND_SENSB_VSYNC is inverted before applied to internal circuitry.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL (0) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL (0x00000001) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL) >> BP_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL) & BM_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_VSYNC_POL field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL) | BF_IPU_CSI0_SENS_CONF_CSI0_VSYNC_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_HSYNC_POL[1] (RW)
|
|
*
|
|
* Invert IPP_IND_SENSB_HSYNC input. This bit selects the polarity of IPP_IND_SENSB_HSYNC signal.
|
|
*
|
|
* Values:
|
|
* - 0 - IPP_IND_SENSB_HSYNC is directly applied to internal circuitry.
|
|
* - 1 - IPP_IND_SENSB_HSYNC is inverted before applied to internal circuitry.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL (1) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL (0x00000002) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL) >> BP_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL) & BM_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_HSYNC_POL field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL) | BF_IPU_CSI0_SENS_CONF_CSI0_HSYNC_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_DATA_POL[2] (RW)
|
|
*
|
|
* Invert data input. This bit selects the polarity of data input.
|
|
*
|
|
* Values:
|
|
* - 0 - data lines are directly applied to internal circuitry.
|
|
* - 1 - data lines are inverted before applied to internal circuitry.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_DATA_POL (2) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_DATA_POL.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_DATA_POL (0x00000004) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_DATA_POL.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_DATA_POL from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_DATA_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_POL) >> BP_IPU_CSI0_SENS_CONF_CSI0_DATA_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_DATA_POL.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_DATA_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_DATA_POL) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DATA_POL field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_DATA_POL(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_DATA_POL) | BF_IPU_CSI0_SENS_CONF_CSI0_DATA_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_SENS_PIX_CLK_POL[3] (RW)
|
|
*
|
|
* Invert Pixel clock input. This bit selects the polarity of pixel clock.
|
|
*
|
|
* Values:
|
|
* - 0 - pixel clock is directly applied to internal circuitry.
|
|
* - 1 - pixel clock is inverted before applied to internal circuitry.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL (3) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL (0x00000008) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL) >> BP_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL) & BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SENS_PIX_CLK_POL field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL) | BF_IPU_CSI0_SENS_CONF_CSI0_SENS_PIX_CLK_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_SENS_PRTCL[6:4] (RW)
|
|
*
|
|
* Sensor Protocol. This bit defines the Sensor timing/data mode protocol. Values:
|
|
*
|
|
* Values:
|
|
* - 000 - Gated clock mode
|
|
* - 001 - Non-gated clock mode
|
|
* - 010 - CCIR progressive mode (BT.656)
|
|
* - 011 - CCIR interlaced mode (BT.656)
|
|
* - 100 - CCIR progressive (BT.1120 DDR mode: data arrives on every edge of the clock)
|
|
* - 101 - CCIR progressive (BT.1120 SDR mode: data arrives only on the positive edge of the clock)
|
|
* - 110 - CCIR interlaced mode (BT.1120 DDR mode: data arrives on every edge of the clock)
|
|
* - 111 - CCIR interlaced mode (BT.1120 SDR mode: data arrives only on the positive edge of the clock)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL (4) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL (0x00000070) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL) >> BP_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL) & BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SENS_PRTCL field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL) | BF_IPU_CSI0_SENS_CONF_CSI0_SENS_PRTCL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_PACK_TIGHT[7] (RW)
|
|
*
|
|
* CSI0 Pack Tight When the data format is YUV or RGB and the component's width is 9-16 bits, it can
|
|
* be sent to the memory in 2 different ways.
|
|
*
|
|
* Values:
|
|
* - 0 - Each component is written as a 16 bit word where the MSB is written to bit #15, color extension is
|
|
* done for the remaining least significant bits.
|
|
* - 1 - Three 10 bits components are packed into a 32 bit word. Color extension/reduction is performed
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT (7) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT (0x00000080) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT) >> BP_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT) & BM_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_PACK_TIGHT field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT) | BF_IPU_CSI0_SENS_CONF_CSI0_PACK_TIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_SENS_DATA_FORMAT[10:8] (RW)
|
|
*
|
|
* Data format from the sensor. This field defines the data format for the input of the CSI sensor.
|
|
* Values:
|
|
*
|
|
* Values:
|
|
* - 000 - full RGB or YUV444
|
|
* - 001 - YUV422 (YUYV...)
|
|
* - 010 - YUV422 (UYVY...)
|
|
* - 011 - Bayer or Generic data
|
|
* - 100 - RGB565
|
|
* - 101 - RGB555
|
|
* - 110 - RGB444
|
|
* - 111 - JPEG
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT (8) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT (0x00000700) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT) >> BP_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT) & BM_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SENS_DATA_FORMAT field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT) | BF_IPU_CSI0_SENS_CONF_CSI0_SENS_DATA_FORMAT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_DATA_WIDTH[14:11] (RW)
|
|
*
|
|
* Data width. This field defines the number of bits per color. Values:
|
|
*
|
|
* Values:
|
|
* - 0000 - 4 bits per color
|
|
* - 0000 - Reserved
|
|
* - 0001 - 8 bits per color
|
|
* - 0010 - 9 bits per color
|
|
* - 0010 - Reserved
|
|
* - 0011 - 10 bits per color
|
|
* - 0100 - 11 bits per color
|
|
* - 0100 - Reserved
|
|
* - 0101 - 12 bits per color
|
|
* - 0101 - Reserved
|
|
* - 0110 - 13 bits per color
|
|
* - 0110 - Reserved
|
|
* - 0111 - 14 bits per color
|
|
* - 0111 - Reserved
|
|
* - 1000 - 15 bits per color
|
|
* - 1000 - Reserved
|
|
* - 1001 - 16 bits per color
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH (11) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH (0x00007800) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH) >> BP_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DATA_WIDTH field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH) | BF_IPU_CSI0_SENS_CONF_CSI0_DATA_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_EXT_VSYNC[15] (RW)
|
|
*
|
|
* External VSYNC enable. This bits select between external and internal VSYNC.
|
|
*
|
|
* Values:
|
|
* - 0 - Internal VSYNC mode.
|
|
* - 1 - External VSYNC mode.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC (15) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC (0x00008000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC) >> BP_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC) & BM_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_EXT_VSYNC field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC) | BF_IPU_CSI0_SENS_CONF_CSI0_EXT_VSYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_DIV_RATIO[23:16] (RW)
|
|
*
|
|
* DIV Ratio Clock division ratio minus 1. This field defines the division ratio of HSP_CLK into
|
|
* SENSB_MCLK: SENSB_MCLK rate = HSP_CLK rate /(DIV_RATIO+1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO (16) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO (0x00ff0000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO) >> BP_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO) & BM_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DIV_RATIO field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO) | BF_IPU_CSI0_SENS_CONF_CSI0_DIV_RATIO(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_DATA_DEST[26:24] (RW)
|
|
*
|
|
* These bits enable the destination of the data coming from the CSI. CSI0_DATA_DEST[0] - Reserved
|
|
* CSI0_DATA_DEST[1] - destination is IC CSI0_DATA_DEST[2] - destination is IDMAC via SMFC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST (24) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_DATA_DEST.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST (0x07000000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_DATA_DEST.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_DATA_DEST from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST) >> BP_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_DATA_DEST.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DATA_DEST field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST) | BF_IPU_CSI0_SENS_CONF_CSI0_DATA_DEST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_JPEG8_EN[27] (RW)
|
|
*
|
|
* JPEG8 enable bit
|
|
*
|
|
* Values:
|
|
* - 0 - JPEG8 is disabled
|
|
* - 1 - JPEG8 detection is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN (27) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN (0x08000000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN) >> BP_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN) & BM_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_JPEG8_EN field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN) | BF_IPU_CSI0_SENS_CONF_CSI0_JPEG8_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_JPEG_MODE[28] (RW)
|
|
*
|
|
* JPEG Mode - this bit defines the mode of the control signals when working in JPEG mode
|
|
*
|
|
* Values:
|
|
* - 0 - The frame starts withe the assertion of VSYNC. The frame ends on the next VSYNC or by setting the
|
|
* CSI0_FORCE_EOF bit.
|
|
* - 1 - The data is valid as long as HSYNC and VSYNC signals are active; HSYNC is valid for single frame
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE (28) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE (0x10000000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE) >> BP_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE) & BM_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_JPEG_MODE field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE) | BF_IPU_CSI0_SENS_CONF_CSI0_JPEG_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_FORCE_EOF[29] (RW)
|
|
*
|
|
* Force End of frame This is a self clear bit allowing the user to force an End-of-frame event;
|
|
* This bit can be used in cases where the frame sent by the sensor was not completed.
|
|
*
|
|
* Values:
|
|
* - 0 - no action
|
|
* - 1 - force end of frame
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF (29) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF (0x20000000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF) >> BP_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF) & BM_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_FORCE_EOF field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF) | BF_IPU_CSI0_SENS_CONF_CSI0_FORCE_EOF(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_CONF, field CSI0_DATA_EN_POL[31] (RW)
|
|
*
|
|
* Invert IPP_IND_SENSB_DATA_EN input. This bit selects the polarity of IPP_IND_SENSB_DATA_EN
|
|
* signal.
|
|
*
|
|
* Values:
|
|
* - 0 - IPP_IND_SENSB_DATA_EN is directly applied to internal circuitry.
|
|
* - 1 - IPP_IND_SENSB_DATA_EN is inverted before applied to internal circuitry.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL (31) //!< Bit position for IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL.
|
|
#define BM_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL (0x80000000) //!< Bit mask for IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL from a register value.
|
|
#define BG_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL) >> BP_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL.
|
|
#define BF_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL) & BM_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DATA_EN_POL field to a new value.
|
|
#define BW_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL(x, v) (HW_IPU_CSI0_SENS_CONF_WR(x, (HW_IPU_CSI0_SENS_CONF_RD(x) & ~BM_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL) | BF_IPU_CSI0_SENS_CONF_CSI0_DATA_EN_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_SENS_FRM_SIZE - CSI0 Sense Frame Size Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_SENS_FRM_SIZE - CSI0 Sense Frame Size Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_sens_frm_size
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_sens_frm_size_bitfields
|
|
{
|
|
unsigned CSI0_SENS_FRM_WIDTH : 13; //!< [12:0] Sensor frame width minus 1.
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved, should be cleared.
|
|
unsigned CSI0_SENS_FRM_HEIGHT : 12; //!< [27:16] Sensor frame height minus 1.
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi0_sens_frm_size_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_SENS_FRM_SIZE register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE_ADDR(x) (REGS_IPU_BASE(x) + 0x30004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE(x) (*(volatile hw_ipu_csi0_sens_frm_size_t *) HW_IPU_CSI0_SENS_FRM_SIZE_ADDR(x))
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE_RD(x) (HW_IPU_CSI0_SENS_FRM_SIZE(x).U)
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE_WR(x, v) (HW_IPU_CSI0_SENS_FRM_SIZE(x).U = (v))
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE_SET(x, v) (HW_IPU_CSI0_SENS_FRM_SIZE_WR(x, HW_IPU_CSI0_SENS_FRM_SIZE_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE_CLR(x, v) (HW_IPU_CSI0_SENS_FRM_SIZE_WR(x, HW_IPU_CSI0_SENS_FRM_SIZE_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_SENS_FRM_SIZE_TOG(x, v) (HW_IPU_CSI0_SENS_FRM_SIZE_WR(x, HW_IPU_CSI0_SENS_FRM_SIZE_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_SENS_FRM_SIZE bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_SENS_FRM_SIZE, field CSI0_SENS_FRM_WIDTH[12:0] (RW)
|
|
*
|
|
* Sensor frame width minus 1. This field defines the sensor frame column number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH (0) //!< Bit position for IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH.
|
|
#define BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH (0x00001fff) //!< Bit mask for IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH from a register value.
|
|
#define BG_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH) >> BP_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH.
|
|
#define BF_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH) & BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SENS_FRM_WIDTH field to a new value.
|
|
#define BW_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH(x, v) (HW_IPU_CSI0_SENS_FRM_SIZE_WR(x, (HW_IPU_CSI0_SENS_FRM_SIZE_RD(x) & ~BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH) | BF_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SENS_FRM_SIZE, field CSI0_SENS_FRM_HEIGHT[27:16] (RW)
|
|
*
|
|
* Sensor frame height minus 1. This field defines the sensor frame rows number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT (16) //!< Bit position for IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT.
|
|
#define BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT (0x0fff0000) //!< Bit mask for IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT from a register value.
|
|
#define BG_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT) >> BP_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT.
|
|
#define BF_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT) & BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SENS_FRM_HEIGHT field to a new value.
|
|
#define BW_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT(x, v) (HW_IPU_CSI0_SENS_FRM_SIZE_WR(x, (HW_IPU_CSI0_SENS_FRM_SIZE_RD(x) & ~BM_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT) | BF_IPU_CSI0_SENS_FRM_SIZE_CSI0_SENS_FRM_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_ACT_FRM_SIZE - CSI0 Actual Frame Size Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_ACT_FRM_SIZE - CSI0 Actual Frame Size Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_act_frm_size
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_act_frm_size_bitfields
|
|
{
|
|
unsigned CSI0_ACT_FRM_WIDTH : 13; //!< [12:0] Actual frame width minus 1.
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved, should be cleared.
|
|
unsigned CSI0_ACT_FRM_HEIGHT : 12; //!< [27:16] Actual frame height minus 1.
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi0_act_frm_size_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_ACT_FRM_SIZE register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE_ADDR(x) (REGS_IPU_BASE(x) + 0x30008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE(x) (*(volatile hw_ipu_csi0_act_frm_size_t *) HW_IPU_CSI0_ACT_FRM_SIZE_ADDR(x))
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE_RD(x) (HW_IPU_CSI0_ACT_FRM_SIZE(x).U)
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE_WR(x, v) (HW_IPU_CSI0_ACT_FRM_SIZE(x).U = (v))
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE_SET(x, v) (HW_IPU_CSI0_ACT_FRM_SIZE_WR(x, HW_IPU_CSI0_ACT_FRM_SIZE_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE_CLR(x, v) (HW_IPU_CSI0_ACT_FRM_SIZE_WR(x, HW_IPU_CSI0_ACT_FRM_SIZE_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_ACT_FRM_SIZE_TOG(x, v) (HW_IPU_CSI0_ACT_FRM_SIZE_WR(x, HW_IPU_CSI0_ACT_FRM_SIZE_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_ACT_FRM_SIZE bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_ACT_FRM_SIZE, field CSI0_ACT_FRM_WIDTH[12:0] (RW)
|
|
*
|
|
* Actual frame width minus 1. This field defines the CSI output frame columns number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH (0) //!< Bit position for IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH.
|
|
#define BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH (0x00001fff) //!< Bit mask for IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH.
|
|
|
|
//! @brief Get value of IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH from a register value.
|
|
#define BG_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH) >> BP_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH.
|
|
#define BF_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH) & BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_ACT_FRM_WIDTH field to a new value.
|
|
#define BW_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH(x, v) (HW_IPU_CSI0_ACT_FRM_SIZE_WR(x, (HW_IPU_CSI0_ACT_FRM_SIZE_RD(x) & ~BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH) | BF_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_ACT_FRM_SIZE, field CSI0_ACT_FRM_HEIGHT[27:16] (RW)
|
|
*
|
|
* Actual frame height minus 1. This field defines the CSI output frame rows number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT (16) //!< Bit position for IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT.
|
|
#define BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT (0x0fff0000) //!< Bit mask for IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT from a register value.
|
|
#define BG_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT) >> BP_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT.
|
|
#define BF_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT) & BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_ACT_FRM_HEIGHT field to a new value.
|
|
#define BW_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT(x, v) (HW_IPU_CSI0_ACT_FRM_SIZE_WR(x, (HW_IPU_CSI0_ACT_FRM_SIZE_RD(x) & ~BM_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT) | BF_IPU_CSI0_ACT_FRM_SIZE_CSI0_ACT_FRM_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_OUT_FRM_CTRL - CSI0 Output Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_OUT_FRM_CTRL - CSI0 Output Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_out_frm_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_out_frm_ctrl_bitfields
|
|
{
|
|
unsigned CSI0_VSC : 12; //!< [11:0] Vertical skip.
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved, should be cleared.
|
|
unsigned CSI0_HSC : 13; //!< [28:16] Horizontal skip.
|
|
unsigned RESERVED1 : 1; //!< [29] Reserved, should be cleared.
|
|
unsigned CSI0_VERT_DWNS : 1; //!< [30] Enable vertical downsizing (decimation) by 2.
|
|
unsigned CSI0_HORZ_DWNS : 1; //!< [31] Enable horizontal downsizing (decimation) by 2.
|
|
} B;
|
|
} hw_ipu_csi0_out_frm_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_OUT_FRM_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x3000c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL(x) (*(volatile hw_ipu_csi0_out_frm_ctrl_t *) HW_IPU_CSI0_OUT_FRM_CTRL_ADDR(x))
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) (HW_IPU_CSI0_OUT_FRM_CTRL(x).U)
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL(x).U = (v))
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL_SET(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL_CLR(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_OUT_FRM_CTRL_TOG(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_OUT_FRM_CTRL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_OUT_FRM_CTRL, field CSI0_VSC[11:0] (RW)
|
|
*
|
|
* Vertical skip. This field defines the number of rows to skip.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC (0) //!< Bit position for IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC.
|
|
#define BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC (0x00000fff) //!< Bit mask for IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC.
|
|
|
|
//! @brief Get value of IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC from a register value.
|
|
#define BG_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC) >> BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC.
|
|
#define BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_VSC field to a new value.
|
|
#define BW_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC) | BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_VSC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_OUT_FRM_CTRL, field CSI0_HSC[28:16] (RW)
|
|
*
|
|
* Horizontal skip. This field defines the number of columns to skip. In Interlaced mode this number
|
|
* refers to the number of lines per field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC (16) //!< Bit position for IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC.
|
|
#define BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC (0x1fff0000) //!< Bit mask for IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC.
|
|
|
|
//! @brief Get value of IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC from a register value.
|
|
#define BG_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC) >> BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC.
|
|
#define BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_HSC field to a new value.
|
|
#define BW_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC) | BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_HSC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_OUT_FRM_CTRL, field CSI0_VERT_DWNS[30] (RW)
|
|
*
|
|
* Enable vertical downsizing (decimation) by 2.
|
|
*
|
|
* Values:
|
|
* - 0 - Downsizing disabled
|
|
* - 1 - Downsizing enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS (30) //!< Bit position for IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS.
|
|
#define BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS (0x40000000) //!< Bit mask for IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS.
|
|
|
|
//! @brief Get value of IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS from a register value.
|
|
#define BG_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS) >> BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS.
|
|
#define BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_VERT_DWNS field to a new value.
|
|
#define BW_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS) | BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_VERT_DWNS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_OUT_FRM_CTRL, field CSI0_HORZ_DWNS[31] (RW)
|
|
*
|
|
* Enable horizontal downsizing (decimation) by 2.
|
|
*
|
|
* Values:
|
|
* - 0 - Downsizing disabled 1 Downsizing enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS (31) //!< Bit position for IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS.
|
|
#define BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS (0x80000000) //!< Bit mask for IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS.
|
|
|
|
//! @brief Get value of IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS from a register value.
|
|
#define BG_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS) >> BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS.
|
|
#define BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS) & BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_HORZ_DWNS field to a new value.
|
|
#define BW_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS(x, v) (HW_IPU_CSI0_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI0_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS) | BF_IPU_CSI0_OUT_FRM_CTRL_CSI0_HORZ_DWNS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_TST_CTRL - CSIO Test Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_TST_CTRL - CSIO Test Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_tst_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_tst_ctrl_bitfields
|
|
{
|
|
unsigned PG_R_VALUE : 8; //!< [7:0] Pattern generator R value.
|
|
unsigned PG_G_VALUE : 8; //!< [15:8] Pattern generator G value.
|
|
unsigned PG_B_VALUE : 8; //!< [23:16] Pattern generator B value.
|
|
unsigned TEST_GEN_MODE : 1; //!< [24] Test generator mode.
|
|
unsigned RESERVED0 : 7; //!< [31:25] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi0_tst_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_TST_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_TST_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x30010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_TST_CTRL(x) (*(volatile hw_ipu_csi0_tst_ctrl_t *) HW_IPU_CSI0_TST_CTRL_ADDR(x))
|
|
#define HW_IPU_CSI0_TST_CTRL_RD(x) (HW_IPU_CSI0_TST_CTRL(x).U)
|
|
#define HW_IPU_CSI0_TST_CTRL_WR(x, v) (HW_IPU_CSI0_TST_CTRL(x).U = (v))
|
|
#define HW_IPU_CSI0_TST_CTRL_SET(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, HW_IPU_CSI0_TST_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_TST_CTRL_CLR(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, HW_IPU_CSI0_TST_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_TST_CTRL_TOG(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, HW_IPU_CSI0_TST_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_TST_CTRL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_TST_CTRL, field PG_R_VALUE[7:0] (RW)
|
|
*
|
|
* Pattern generator R value. This field selects the R value for the generated pattern of even
|
|
* pixel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_TST_CTRL_PG_R_VALUE (0) //!< Bit position for IPU_CSI0_TST_CTRL_PG_R_VALUE.
|
|
#define BM_IPU_CSI0_TST_CTRL_PG_R_VALUE (0x000000ff) //!< Bit mask for IPU_CSI0_TST_CTRL_PG_R_VALUE.
|
|
|
|
//! @brief Get value of IPU_CSI0_TST_CTRL_PG_R_VALUE from a register value.
|
|
#define BG_IPU_CSI0_TST_CTRL_PG_R_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_TST_CTRL_PG_R_VALUE) >> BP_IPU_CSI0_TST_CTRL_PG_R_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_TST_CTRL_PG_R_VALUE.
|
|
#define BF_IPU_CSI0_TST_CTRL_PG_R_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_TST_CTRL_PG_R_VALUE) & BM_IPU_CSI0_TST_CTRL_PG_R_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PG_R_VALUE field to a new value.
|
|
#define BW_IPU_CSI0_TST_CTRL_PG_R_VALUE(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, (HW_IPU_CSI0_TST_CTRL_RD(x) & ~BM_IPU_CSI0_TST_CTRL_PG_R_VALUE) | BF_IPU_CSI0_TST_CTRL_PG_R_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_TST_CTRL, field PG_G_VALUE[15:8] (RW)
|
|
*
|
|
* Pattern generator G value. This field selects the G value for the generated pattern of even
|
|
* pixel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_TST_CTRL_PG_G_VALUE (8) //!< Bit position for IPU_CSI0_TST_CTRL_PG_G_VALUE.
|
|
#define BM_IPU_CSI0_TST_CTRL_PG_G_VALUE (0x0000ff00) //!< Bit mask for IPU_CSI0_TST_CTRL_PG_G_VALUE.
|
|
|
|
//! @brief Get value of IPU_CSI0_TST_CTRL_PG_G_VALUE from a register value.
|
|
#define BG_IPU_CSI0_TST_CTRL_PG_G_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_TST_CTRL_PG_G_VALUE) >> BP_IPU_CSI0_TST_CTRL_PG_G_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_TST_CTRL_PG_G_VALUE.
|
|
#define BF_IPU_CSI0_TST_CTRL_PG_G_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_TST_CTRL_PG_G_VALUE) & BM_IPU_CSI0_TST_CTRL_PG_G_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PG_G_VALUE field to a new value.
|
|
#define BW_IPU_CSI0_TST_CTRL_PG_G_VALUE(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, (HW_IPU_CSI0_TST_CTRL_RD(x) & ~BM_IPU_CSI0_TST_CTRL_PG_G_VALUE) | BF_IPU_CSI0_TST_CTRL_PG_G_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_TST_CTRL, field PG_B_VALUE[23:16] (RW)
|
|
*
|
|
* Pattern generator B value. This field selects the B value for the generated pattern of even
|
|
* pixel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_TST_CTRL_PG_B_VALUE (16) //!< Bit position for IPU_CSI0_TST_CTRL_PG_B_VALUE.
|
|
#define BM_IPU_CSI0_TST_CTRL_PG_B_VALUE (0x00ff0000) //!< Bit mask for IPU_CSI0_TST_CTRL_PG_B_VALUE.
|
|
|
|
//! @brief Get value of IPU_CSI0_TST_CTRL_PG_B_VALUE from a register value.
|
|
#define BG_IPU_CSI0_TST_CTRL_PG_B_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_TST_CTRL_PG_B_VALUE) >> BP_IPU_CSI0_TST_CTRL_PG_B_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_TST_CTRL_PG_B_VALUE.
|
|
#define BF_IPU_CSI0_TST_CTRL_PG_B_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_TST_CTRL_PG_B_VALUE) & BM_IPU_CSI0_TST_CTRL_PG_B_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PG_B_VALUE field to a new value.
|
|
#define BW_IPU_CSI0_TST_CTRL_PG_B_VALUE(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, (HW_IPU_CSI0_TST_CTRL_RD(x) & ~BM_IPU_CSI0_TST_CTRL_PG_B_VALUE) | BF_IPU_CSI0_TST_CTRL_PG_B_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_TST_CTRL, field TEST_GEN_MODE[24] (RW)
|
|
*
|
|
* Test generator mode. This bit activates the signal generation.
|
|
*
|
|
* Values:
|
|
* - 0 - Test signal generator is inactive.
|
|
* - 1 - Test signal generator is active.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_TST_CTRL_TEST_GEN_MODE (24) //!< Bit position for IPU_CSI0_TST_CTRL_TEST_GEN_MODE.
|
|
#define BM_IPU_CSI0_TST_CTRL_TEST_GEN_MODE (0x01000000) //!< Bit mask for IPU_CSI0_TST_CTRL_TEST_GEN_MODE.
|
|
|
|
//! @brief Get value of IPU_CSI0_TST_CTRL_TEST_GEN_MODE from a register value.
|
|
#define BG_IPU_CSI0_TST_CTRL_TEST_GEN_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_TST_CTRL_TEST_GEN_MODE) >> BP_IPU_CSI0_TST_CTRL_TEST_GEN_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_TST_CTRL_TEST_GEN_MODE.
|
|
#define BF_IPU_CSI0_TST_CTRL_TEST_GEN_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_TST_CTRL_TEST_GEN_MODE) & BM_IPU_CSI0_TST_CTRL_TEST_GEN_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the TEST_GEN_MODE field to a new value.
|
|
#define BW_IPU_CSI0_TST_CTRL_TEST_GEN_MODE(x, v) (HW_IPU_CSI0_TST_CTRL_WR(x, (HW_IPU_CSI0_TST_CTRL_RD(x) & ~BM_IPU_CSI0_TST_CTRL_TEST_GEN_MODE) | BF_IPU_CSI0_TST_CTRL_TEST_GEN_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_CCIR_CODE_1 - CSIO CCIR Code Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_CCIR_CODE_1 - CSIO CCIR Code Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_ccir_code_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_ccir_code_1_bitfields
|
|
{
|
|
unsigned CSI0_END_FLD0_BLNK_1ST : 3; //!< [2:0] End of field 0 first blanking line command (interlaces mode).
|
|
unsigned CSI0_STRT_FLD0_BLNK_1ST : 3; //!< [5:3] Start of field 0 first blanking line command (interlaces mode).
|
|
unsigned CSI0_END_FLD0_BLNK_2ND : 3; //!< [8:6] End of field 0 second blanking line command (interlaces mode).
|
|
unsigned CSI0_STRT_FLD0_BLNK_2ND : 3; //!< [11:9] Start of field 0 second blanking line command (interlaces mode).
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved, should be cleared.
|
|
unsigned CSI0_END_FLD0_ACTV : 3; //!< [18:16] End of field 0 active line command (interlaces mode).
|
|
unsigned CSI0_STRT_FLD0_ACTV : 3; //!< [21:19] Start of field 0 active line command (interlaces mode).
|
|
unsigned RESERVED1 : 2; //!< [23:22] Reserved, should be cleared.
|
|
unsigned CSI0_CCIR_ERR_DET_EN : 1; //!< [24] Enable error detection and correction for CCIR interlaced mode with protection bit.
|
|
unsigned RESERVED2 : 7; //!< [31:25] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi0_ccir_code_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_CCIR_CODE_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_CCIR_CODE_1_ADDR(x) (REGS_IPU_BASE(x) + 0x30014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_CCIR_CODE_1(x) (*(volatile hw_ipu_csi0_ccir_code_1_t *) HW_IPU_CSI0_CCIR_CODE_1_ADDR(x))
|
|
#define HW_IPU_CSI0_CCIR_CODE_1_RD(x) (HW_IPU_CSI0_CCIR_CODE_1(x).U)
|
|
#define HW_IPU_CSI0_CCIR_CODE_1_WR(x, v) (HW_IPU_CSI0_CCIR_CODE_1(x).U = (v))
|
|
#define HW_IPU_CSI0_CCIR_CODE_1_SET(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, HW_IPU_CSI0_CCIR_CODE_1_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_CCIR_CODE_1_CLR(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_CCIR_CODE_1_TOG(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, HW_IPU_CSI0_CCIR_CODE_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_CCIR_CODE_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_END_FLD0_BLNK_1ST[2:0] (RW)
|
|
*
|
|
* End of field 0 first blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST (0) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST.
|
|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST (0x00000007) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_END_FLD0_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_STRT_FLD0_BLNK_1ST[5:3] (RW)
|
|
*
|
|
* Start of field 0 first blanking line command (interlaces mode). (In progressive mode this field
|
|
* indicates start of blanking line command).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST (3) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST.
|
|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST (0x00000038) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_STRT_FLD0_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_END_FLD0_BLNK_2ND[8:6] (RW)
|
|
*
|
|
* End of field 0 second blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND (6) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND.
|
|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND (0x000001c0) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_END_FLD0_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_BLNK_2ND(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_STRT_FLD0_BLNK_2ND[11:9] (RW)
|
|
*
|
|
* Start of field 0 second blanking line command (interlaces mode). (In progressive mode this field
|
|
* is ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND (9) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND.
|
|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND (0x00000e00) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND.
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|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND)
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|
|
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//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_STRT_FLD0_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_END_FLD0_ACTV[18:16] (RW)
|
|
*
|
|
* End of field 0 active line command (interlaces mode). (In progressive mode, end of active line
|
|
* command mode).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV (16) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV.
|
|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV (0x00070000) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV.
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|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV)
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|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_END_FLD0_ACTV field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_END_FLD0_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_STRT_FLD0_ACTV[21:19] (RW)
|
|
*
|
|
* Start of field 0 active line command (interlaces mode). (In progressive mode, start of active
|
|
* line command mode).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV (19) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV.
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|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV (0x00380000) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV.
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|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_STRT_FLD0_ACTV field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_STRT_FLD0_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_1, field CSI0_CCIR_ERR_DET_EN[24] (RW)
|
|
*
|
|
* Enable error detection and correction for CCIR interlaced mode with protection bit.
|
|
*
|
|
* Values:
|
|
* - 0 - Error detection and correction is disabled.
|
|
* - 1 - Error detection and correction is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN (24) //!< Bit position for IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN.
|
|
#define BM_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN (0x01000000) //!< Bit mask for IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN) >> BP_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN.
|
|
#define BF_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN) & BM_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CCIR_ERR_DET_EN field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN(x, v) (HW_IPU_CSI0_CCIR_CODE_1_WR(x, (HW_IPU_CSI0_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN) | BF_IPU_CSI0_CCIR_CODE_1_CSI0_CCIR_ERR_DET_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_CCIR_CODE_2 - CSIO CCIR Code Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_CCIR_CODE_2 - CSIO CCIR Code Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_ccir_code_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_ccir_code_2_bitfields
|
|
{
|
|
unsigned CSI0_END_FLD1_BLNK_1ST : 3; //!< [2:0] End of field 1 first blanking line command (interlaces mode).
|
|
unsigned CSI0_STRT_FLD1_BLNK_1ST : 3; //!< [5:3] Start of field 1 first blanking line command (interlaces mode).
|
|
unsigned CSI0_END_FLD1_BLNK_2ND : 3; //!< [8:6] End of field 1 second blanking line command (interlaces mode).
|
|
unsigned CSI0_STRT_FLD1_BLNK_2ND : 3; //!< [11:9] Start of field 1 second blanking line command (interlaces mode).
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved, should be cleared.
|
|
unsigned CSI0_END_FLD1_ACTV : 3; //!< [18:16] End of field 1 active line command (interlaces mode).
|
|
unsigned CSI0_STRT_FLD1_ACTV : 3; //!< [21:19] Start of field 1 active line command (interlaces mode).
|
|
unsigned RESERVED1 : 10; //!< [31:22] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi0_ccir_code_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_CCIR_CODE_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_CCIR_CODE_2_ADDR(x) (REGS_IPU_BASE(x) + 0x30018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_CCIR_CODE_2(x) (*(volatile hw_ipu_csi0_ccir_code_2_t *) HW_IPU_CSI0_CCIR_CODE_2_ADDR(x))
|
|
#define HW_IPU_CSI0_CCIR_CODE_2_RD(x) (HW_IPU_CSI0_CCIR_CODE_2(x).U)
|
|
#define HW_IPU_CSI0_CCIR_CODE_2_WR(x, v) (HW_IPU_CSI0_CCIR_CODE_2(x).U = (v))
|
|
#define HW_IPU_CSI0_CCIR_CODE_2_SET(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, HW_IPU_CSI0_CCIR_CODE_2_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_CCIR_CODE_2_CLR(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_CCIR_CODE_2_TOG(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, HW_IPU_CSI0_CCIR_CODE_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_CCIR_CODE_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_2, field CSI0_END_FLD1_BLNK_1ST[2:0] (RW)
|
|
*
|
|
* End of field 1 first blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST (0) //!< Bit position for IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST.
|
|
#define BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST (0x00000007) //!< Bit mask for IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST) >> BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST.
|
|
#define BF_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_END_FLD1_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, (HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST) | BF_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_2, field CSI0_STRT_FLD1_BLNK_1ST[5:3] (RW)
|
|
*
|
|
* Start of field 1 first blanking line command (interlaces mode). (In progressive mode this field
|
|
* is ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST (3) //!< Bit position for IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST.
|
|
#define BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST (0x00000038) //!< Bit mask for IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST) >> BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST.
|
|
#define BF_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_STRT_FLD1_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, (HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST) | BF_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_2, field CSI0_END_FLD1_BLNK_2ND[8:6] (RW)
|
|
*
|
|
* End of field 1 second blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND (6) //!< Bit position for IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND.
|
|
#define BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND (0x000001c0) //!< Bit mask for IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND) >> BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND.
|
|
#define BF_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_END_FLD1_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, (HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND) | BF_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_2, field CSI0_STRT_FLD1_BLNK_2ND[11:9] (RW)
|
|
*
|
|
* Start of field 1 second blanking line command (interlaces mode). (In progressive mode this field
|
|
* is ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND (9) //!< Bit position for IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND.
|
|
#define BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND (0x00000e00) //!< Bit mask for IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND) >> BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND.
|
|
#define BF_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_STRT_FLD1_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, (HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND) | BF_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_2, field CSI0_END_FLD1_ACTV[18:16] (RW)
|
|
*
|
|
* End of field 1 active line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV (16) //!< Bit position for IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV.
|
|
#define BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV (0x00070000) //!< Bit mask for IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV.
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|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV) >> BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV)
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|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV.
|
|
#define BF_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_END_FLD1_ACTV field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, (HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV) | BF_IPU_CSI0_CCIR_CODE_2_CSI0_END_FLD1_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_2, field CSI0_STRT_FLD1_ACTV[21:19] (RW)
|
|
*
|
|
* Start of field 1 active line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV (19) //!< Bit position for IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV.
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|
#define BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV (0x00380000) //!< Bit mask for IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV.
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|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV from a register value.
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|
#define BG_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV) >> BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV)
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|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV.
|
|
#define BF_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV) & BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_STRT_FLD1_ACTV field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV(x, v) (HW_IPU_CSI0_CCIR_CODE_2_WR(x, (HW_IPU_CSI0_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV) | BF_IPU_CSI0_CCIR_CODE_2_CSI0_STRT_FLD1_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_CCIR_CODE_3 - CSIO CCIR Code Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_CCIR_CODE_3 - CSIO CCIR Code Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi0_ccir_code_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_ccir_code_3_bitfields
|
|
{
|
|
unsigned CSI0_CCIR_PRECOM : 30; //!< [29:0] CCIR pre command.
|
|
unsigned RESERVED0 : 2; //!< [31:30] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi0_ccir_code_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_CCIR_CODE_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_CCIR_CODE_3_ADDR(x) (REGS_IPU_BASE(x) + 0x3001c)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_CCIR_CODE_3(x) (*(volatile hw_ipu_csi0_ccir_code_3_t *) HW_IPU_CSI0_CCIR_CODE_3_ADDR(x))
|
|
#define HW_IPU_CSI0_CCIR_CODE_3_RD(x) (HW_IPU_CSI0_CCIR_CODE_3(x).U)
|
|
#define HW_IPU_CSI0_CCIR_CODE_3_WR(x, v) (HW_IPU_CSI0_CCIR_CODE_3(x).U = (v))
|
|
#define HW_IPU_CSI0_CCIR_CODE_3_SET(x, v) (HW_IPU_CSI0_CCIR_CODE_3_WR(x, HW_IPU_CSI0_CCIR_CODE_3_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_CCIR_CODE_3_CLR(x, v) (HW_IPU_CSI0_CCIR_CODE_3_WR(x, HW_IPU_CSI0_CCIR_CODE_3_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_CCIR_CODE_3_TOG(x, v) (HW_IPU_CSI0_CCIR_CODE_3_WR(x, HW_IPU_CSI0_CCIR_CODE_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_CCIR_CODE_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_CCIR_CODE_3, field CSI0_CCIR_PRECOM[29:0] (RW)
|
|
*
|
|
* CCIR pre command. This field defines the sequence which comes before the CCIR command. For BT.656
|
|
* the code should be written to bits [23:0] while bits [29:24] are ignored (3X8bit) For BT.1120 the
|
|
* code should be written to bits [29:0] (3X10bit)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM (0) //!< Bit position for IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM.
|
|
#define BM_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM (0x3fffffff) //!< Bit mask for IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM.
|
|
|
|
//! @brief Get value of IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM from a register value.
|
|
#define BG_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM) >> BP_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM.
|
|
#define BF_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM) & BM_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CCIR_PRECOM field to a new value.
|
|
#define BW_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM(x, v) (HW_IPU_CSI0_CCIR_CODE_3_WR(x, (HW_IPU_CSI0_CCIR_CODE_3_RD(x) & ~BM_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM) | BF_IPU_CSI0_CCIR_CODE_3_CSI0_CCIR_PRECOM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_DI - CSI0 Data Identifier Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_DI - CSI0 Data Identifier Register (RW)
|
|
*
|
|
* Reset value: 0xffffffff
|
|
*/
|
|
typedef union _hw_ipu_csi0_di
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_di_bitfields
|
|
{
|
|
unsigned CSI0_MIPI_DI0 : 8; //!< [7:0] CSI0_MIPI_DI0
|
|
unsigned CSI0_MIPI_DI1 : 8; //!< [15:8] CSI0_MIPI_DI1
|
|
unsigned CSI0_MIPI_DI2 : 8; //!< [23:16] CSI0_MIPI_DI2
|
|
unsigned CSI0_MIPI_DI3 : 8; //!< [31:24] CSI0_MIPI_DI3
|
|
} B;
|
|
} hw_ipu_csi0_di_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_DI register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_DI_ADDR(x) (REGS_IPU_BASE(x) + 0x30020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_DI(x) (*(volatile hw_ipu_csi0_di_t *) HW_IPU_CSI0_DI_ADDR(x))
|
|
#define HW_IPU_CSI0_DI_RD(x) (HW_IPU_CSI0_DI(x).U)
|
|
#define HW_IPU_CSI0_DI_WR(x, v) (HW_IPU_CSI0_DI(x).U = (v))
|
|
#define HW_IPU_CSI0_DI_SET(x, v) (HW_IPU_CSI0_DI_WR(x, HW_IPU_CSI0_DI_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_DI_CLR(x, v) (HW_IPU_CSI0_DI_WR(x, HW_IPU_CSI0_DI_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_DI_TOG(x, v) (HW_IPU_CSI0_DI_WR(x, HW_IPU_CSI0_DI_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_DI bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_DI, field CSI0_MIPI_DI0[7:0] (RW)
|
|
*
|
|
* CSI0_MIPI_DI0 This field holds the Data Identifier #0 handled by the CSI; This is the main
|
|
* stream.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_DI_CSI0_MIPI_DI0 (0) //!< Bit position for IPU_CSI0_DI_CSI0_MIPI_DI0.
|
|
#define BM_IPU_CSI0_DI_CSI0_MIPI_DI0 (0x000000ff) //!< Bit mask for IPU_CSI0_DI_CSI0_MIPI_DI0.
|
|
|
|
//! @brief Get value of IPU_CSI0_DI_CSI0_MIPI_DI0 from a register value.
|
|
#define BG_IPU_CSI0_DI_CSI0_MIPI_DI0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_DI_CSI0_MIPI_DI0) >> BP_IPU_CSI0_DI_CSI0_MIPI_DI0)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_DI_CSI0_MIPI_DI0.
|
|
#define BF_IPU_CSI0_DI_CSI0_MIPI_DI0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_DI_CSI0_MIPI_DI0) & BM_IPU_CSI0_DI_CSI0_MIPI_DI0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MIPI_DI0 field to a new value.
|
|
#define BW_IPU_CSI0_DI_CSI0_MIPI_DI0(x, v) (HW_IPU_CSI0_DI_WR(x, (HW_IPU_CSI0_DI_RD(x) & ~BM_IPU_CSI0_DI_CSI0_MIPI_DI0) | BF_IPU_CSI0_DI_CSI0_MIPI_DI0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_DI, field CSI0_MIPI_DI1[15:8] (RW)
|
|
*
|
|
* CSI0_MIPI_DI1 This field holds the Data Identifier #1 handled by the CSI
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_DI_CSI0_MIPI_DI1 (8) //!< Bit position for IPU_CSI0_DI_CSI0_MIPI_DI1.
|
|
#define BM_IPU_CSI0_DI_CSI0_MIPI_DI1 (0x0000ff00) //!< Bit mask for IPU_CSI0_DI_CSI0_MIPI_DI1.
|
|
|
|
//! @brief Get value of IPU_CSI0_DI_CSI0_MIPI_DI1 from a register value.
|
|
#define BG_IPU_CSI0_DI_CSI0_MIPI_DI1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_DI_CSI0_MIPI_DI1) >> BP_IPU_CSI0_DI_CSI0_MIPI_DI1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_DI_CSI0_MIPI_DI1.
|
|
#define BF_IPU_CSI0_DI_CSI0_MIPI_DI1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_DI_CSI0_MIPI_DI1) & BM_IPU_CSI0_DI_CSI0_MIPI_DI1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MIPI_DI1 field to a new value.
|
|
#define BW_IPU_CSI0_DI_CSI0_MIPI_DI1(x, v) (HW_IPU_CSI0_DI_WR(x, (HW_IPU_CSI0_DI_RD(x) & ~BM_IPU_CSI0_DI_CSI0_MIPI_DI1) | BF_IPU_CSI0_DI_CSI0_MIPI_DI1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_DI, field CSI0_MIPI_DI2[23:16] (RW)
|
|
*
|
|
* CSI0_MIPI_DI2 This field holds the Data Identifier #2 handled by the CSI.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_DI_CSI0_MIPI_DI2 (16) //!< Bit position for IPU_CSI0_DI_CSI0_MIPI_DI2.
|
|
#define BM_IPU_CSI0_DI_CSI0_MIPI_DI2 (0x00ff0000) //!< Bit mask for IPU_CSI0_DI_CSI0_MIPI_DI2.
|
|
|
|
//! @brief Get value of IPU_CSI0_DI_CSI0_MIPI_DI2 from a register value.
|
|
#define BG_IPU_CSI0_DI_CSI0_MIPI_DI2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_DI_CSI0_MIPI_DI2) >> BP_IPU_CSI0_DI_CSI0_MIPI_DI2)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_DI_CSI0_MIPI_DI2.
|
|
#define BF_IPU_CSI0_DI_CSI0_MIPI_DI2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_DI_CSI0_MIPI_DI2) & BM_IPU_CSI0_DI_CSI0_MIPI_DI2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MIPI_DI2 field to a new value.
|
|
#define BW_IPU_CSI0_DI_CSI0_MIPI_DI2(x, v) (HW_IPU_CSI0_DI_WR(x, (HW_IPU_CSI0_DI_RD(x) & ~BM_IPU_CSI0_DI_CSI0_MIPI_DI2) | BF_IPU_CSI0_DI_CSI0_MIPI_DI2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_DI, field CSI0_MIPI_DI3[31:24] (RW)
|
|
*
|
|
* CSI0_MIPI_DI3 This field holds the Data Identifier #3 handled by the CSI.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_DI_CSI0_MIPI_DI3 (24) //!< Bit position for IPU_CSI0_DI_CSI0_MIPI_DI3.
|
|
#define BM_IPU_CSI0_DI_CSI0_MIPI_DI3 (0xff000000) //!< Bit mask for IPU_CSI0_DI_CSI0_MIPI_DI3.
|
|
|
|
//! @brief Get value of IPU_CSI0_DI_CSI0_MIPI_DI3 from a register value.
|
|
#define BG_IPU_CSI0_DI_CSI0_MIPI_DI3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_DI_CSI0_MIPI_DI3) >> BP_IPU_CSI0_DI_CSI0_MIPI_DI3)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_DI_CSI0_MIPI_DI3.
|
|
#define BF_IPU_CSI0_DI_CSI0_MIPI_DI3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_DI_CSI0_MIPI_DI3) & BM_IPU_CSI0_DI_CSI0_MIPI_DI3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MIPI_DI3 field to a new value.
|
|
#define BW_IPU_CSI0_DI_CSI0_MIPI_DI3(x, v) (HW_IPU_CSI0_DI_WR(x, (HW_IPU_CSI0_DI_RD(x) & ~BM_IPU_CSI0_DI_CSI0_MIPI_DI3) | BF_IPU_CSI0_DI_CSI0_MIPI_DI3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_SKIP - CSI0 SKIP Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_SKIP - CSI0 SKIP Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register controls the frame skipping supported between CSI0 and the SMFC.
|
|
*/
|
|
typedef union _hw_ipu_csi0_skip
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_skip_bitfields
|
|
{
|
|
unsigned CSI0_MAX_RATIO_SKIP_SMFC : 3; //!< [2:0] CSI0 Maximum Ratio Skip for SMFC
|
|
unsigned CSI0_SKIP_SMFC : 5; //!< [7:3] CSI0 SKIP SMFC
|
|
unsigned CSI0_ID_2_SKIP : 2; //!< [9:8] CSI0 to SMFC Skipping ID.
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved
|
|
unsigned CSI0_MAX_RATIO_SKIP_ISP : 3; //!< [18:16] Reserved
|
|
unsigned CSI0_SKIP_ISP : 5; //!< [23:19] Reserved
|
|
unsigned RESERVED1 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_csi0_skip_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_SKIP register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_SKIP_ADDR(x) (REGS_IPU_BASE(x) + 0x30024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_SKIP(x) (*(volatile hw_ipu_csi0_skip_t *) HW_IPU_CSI0_SKIP_ADDR(x))
|
|
#define HW_IPU_CSI0_SKIP_RD(x) (HW_IPU_CSI0_SKIP(x).U)
|
|
#define HW_IPU_CSI0_SKIP_WR(x, v) (HW_IPU_CSI0_SKIP(x).U = (v))
|
|
#define HW_IPU_CSI0_SKIP_SET(x, v) (HW_IPU_CSI0_SKIP_WR(x, HW_IPU_CSI0_SKIP_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_SKIP_CLR(x, v) (HW_IPU_CSI0_SKIP_WR(x, HW_IPU_CSI0_SKIP_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_SKIP_TOG(x, v) (HW_IPU_CSI0_SKIP_WR(x, HW_IPU_CSI0_SKIP_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_SKIP bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_SKIP, field CSI0_MAX_RATIO_SKIP_SMFC[2:0] (RW)
|
|
*
|
|
* CSI0 Maximum Ratio Skip for SMFC These bits define the number of frames in a skipping set. The
|
|
* skipping number is equal to CSI0_MAX_RATIO_SKIP_SMFC+1; The maximum value of this bits is 5. When
|
|
* set to 0 the skipping is disabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC (0) //!< Bit position for IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC.
|
|
#define BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC (0x00000007) //!< Bit mask for IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC.
|
|
|
|
//! @brief Get value of IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC from a register value.
|
|
#define BG_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC) >> BP_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC)
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//! @brief Format value for bitfield IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC.
|
|
#define BF_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC) & BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MAX_RATIO_SKIP_SMFC field to a new value.
|
|
#define BW_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC(x, v) (HW_IPU_CSI0_SKIP_WR(x, (HW_IPU_CSI0_SKIP_RD(x) & ~BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC) | BF_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_SMFC(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_CSI0_SKIP, field CSI0_SKIP_SMFC[7:3] (RW)
|
|
*
|
|
* CSI0 SKIP SMFC These 5 bits define the skipping pattern of the frames send to the SMFC. Skipping
|
|
* is done for a set of frames. The number of frames in a set is defined at
|
|
* CSI0_MAX_RATIO_SKIP_SMFC. when CSI0_MAX_RATIO_SKIP_SMFC = 1 => CSI0_SKIP_SMFC[0] is used; other
|
|
* bits are ignored when CSI0_MAX_RATIO_SKIP_SMFC = 2 => CSI0_SKIP_SMFC[1:0] are used; other bits
|
|
* are ignored when CSI0_MAX_RATIO_SKIP_SMFC = 3 => CSI0_SKIP_SMFC[2:0] are used; other bits are
|
|
* ignored when CSI0_MAX_RATIO_SKIP_SMFC = 4 => CSI0_SKIP_SMFC[3:0] are used; other bits are ignored
|
|
* when CSI0_MAX_RATIO_SKIP_SMFC = 5 => CSI0_SKIP_SMFC[4:0] are used; Setting bit #n of
|
|
* CSI0_SKIP_SMFC means that the #n frame in the set is skipped. For example: if
|
|
* CSI0_MAX_RATIO_SKIP_SMFC = 4 and CSI0_SKIP_SMFC = 11010 Frames #0 & Frame #2 will not be skipped
|
|
* as bit0 and bit2 are cleared Frames #1 & Frame #3 will be skipped as bit1 and bit3 are set bit #4
|
|
* is ignored as CSI0_MAX_RATIO_SKIP_SMFC is set to 4
|
|
*/
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|
//@{
|
|
#define BP_IPU_CSI0_SKIP_CSI0_SKIP_SMFC (3) //!< Bit position for IPU_CSI0_SKIP_CSI0_SKIP_SMFC.
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#define BM_IPU_CSI0_SKIP_CSI0_SKIP_SMFC (0x000000f8) //!< Bit mask for IPU_CSI0_SKIP_CSI0_SKIP_SMFC.
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//! @brief Get value of IPU_CSI0_SKIP_CSI0_SKIP_SMFC from a register value.
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|
#define BG_IPU_CSI0_SKIP_CSI0_SKIP_SMFC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SKIP_CSI0_SKIP_SMFC) >> BP_IPU_CSI0_SKIP_CSI0_SKIP_SMFC)
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//! @brief Format value for bitfield IPU_CSI0_SKIP_CSI0_SKIP_SMFC.
|
|
#define BF_IPU_CSI0_SKIP_CSI0_SKIP_SMFC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SKIP_CSI0_SKIP_SMFC) & BM_IPU_CSI0_SKIP_CSI0_SKIP_SMFC)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SKIP_SMFC field to a new value.
|
|
#define BW_IPU_CSI0_SKIP_CSI0_SKIP_SMFC(x, v) (HW_IPU_CSI0_SKIP_WR(x, (HW_IPU_CSI0_SKIP_RD(x) & ~BM_IPU_CSI0_SKIP_CSI0_SKIP_SMFC) | BF_IPU_CSI0_SKIP_CSI0_SKIP_SMFC(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_CSI0_SKIP, field CSI0_ID_2_SKIP[9:8] (RW)
|
|
*
|
|
* CSI0 to SMFC Skipping ID. Data from the CSI0 to the SMFC has an ID associated with it. The ID is
|
|
* received from the MIPI interface. The skipping mechanism between the CSI0 and the SMFC can be
|
|
* used for only one ID. There is no skipping for data coming with ID different from the ID
|
|
* programed in this bits
|
|
*
|
|
* Values:
|
|
* - 00 - - Skipping mechanism is activated on frames with ID equal to 00
|
|
* - 01 - - Skipping mechanism is activated on frames with ID equal to 01
|
|
* - 10 - - Skipping mechanism is activated on frames with ID equal to 10
|
|
* - 11 - - Skipping mechanism is activated on frames with ID equal to 11
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SKIP_CSI0_ID_2_SKIP (8) //!< Bit position for IPU_CSI0_SKIP_CSI0_ID_2_SKIP.
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|
#define BM_IPU_CSI0_SKIP_CSI0_ID_2_SKIP (0x00000300) //!< Bit mask for IPU_CSI0_SKIP_CSI0_ID_2_SKIP.
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|
|
|
//! @brief Get value of IPU_CSI0_SKIP_CSI0_ID_2_SKIP from a register value.
|
|
#define BG_IPU_CSI0_SKIP_CSI0_ID_2_SKIP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SKIP_CSI0_ID_2_SKIP) >> BP_IPU_CSI0_SKIP_CSI0_ID_2_SKIP)
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|
|
|
//! @brief Format value for bitfield IPU_CSI0_SKIP_CSI0_ID_2_SKIP.
|
|
#define BF_IPU_CSI0_SKIP_CSI0_ID_2_SKIP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SKIP_CSI0_ID_2_SKIP) & BM_IPU_CSI0_SKIP_CSI0_ID_2_SKIP)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_ID_2_SKIP field to a new value.
|
|
#define BW_IPU_CSI0_SKIP_CSI0_ID_2_SKIP(x, v) (HW_IPU_CSI0_SKIP_WR(x, (HW_IPU_CSI0_SKIP_RD(x) & ~BM_IPU_CSI0_SKIP_CSI0_ID_2_SKIP) | BF_IPU_CSI0_SKIP_CSI0_ID_2_SKIP(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SKIP, field CSI0_MAX_RATIO_SKIP_ISP[18:16] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP (16) //!< Bit position for IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP.
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|
#define BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP (0x00070000) //!< Bit mask for IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP.
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|
|
|
//! @brief Get value of IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP from a register value.
|
|
#define BG_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP) >> BP_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP)
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|
|
|
//! @brief Format value for bitfield IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP.
|
|
#define BF_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP) & BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MAX_RATIO_SKIP_ISP field to a new value.
|
|
#define BW_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP(x, v) (HW_IPU_CSI0_SKIP_WR(x, (HW_IPU_CSI0_SKIP_RD(x) & ~BM_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP) | BF_IPU_CSI0_SKIP_CSI0_MAX_RATIO_SKIP_ISP(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_SKIP, field CSI0_SKIP_ISP[23:19] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_SKIP_CSI0_SKIP_ISP (19) //!< Bit position for IPU_CSI0_SKIP_CSI0_SKIP_ISP.
|
|
#define BM_IPU_CSI0_SKIP_CSI0_SKIP_ISP (0x00f80000) //!< Bit mask for IPU_CSI0_SKIP_CSI0_SKIP_ISP.
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|
|
|
//! @brief Get value of IPU_CSI0_SKIP_CSI0_SKIP_ISP from a register value.
|
|
#define BG_IPU_CSI0_SKIP_CSI0_SKIP_ISP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_SKIP_CSI0_SKIP_ISP) >> BP_IPU_CSI0_SKIP_CSI0_SKIP_ISP)
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|
|
|
//! @brief Format value for bitfield IPU_CSI0_SKIP_CSI0_SKIP_ISP.
|
|
#define BF_IPU_CSI0_SKIP_CSI0_SKIP_ISP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_SKIP_CSI0_SKIP_ISP) & BM_IPU_CSI0_SKIP_CSI0_SKIP_ISP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_SKIP_ISP field to a new value.
|
|
#define BW_IPU_CSI0_SKIP_CSI0_SKIP_ISP(x, v) (HW_IPU_CSI0_SKIP_WR(x, (HW_IPU_CSI0_SKIP_RD(x) & ~BM_IPU_CSI0_SKIP_CSI0_SKIP_ISP) | BF_IPU_CSI0_SKIP_CSI0_SKIP_ISP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSIO_CPD_CTRL - CSI0 Compander Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSIO_CPD_CTRL - CSI0 Compander Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csio_cpd_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_ctrl_bitfields
|
|
{
|
|
unsigned CSI0_GREEN_P_BEGIN : 1; //!< [0] Color of first component in the frame.
|
|
unsigned CSI0_RED_ROW_BEGIN : 1; //!< [1] Color of first row in the frame.
|
|
unsigned CSI0_CPD : 3; //!< [4:2] CSI0_CPD
|
|
unsigned RESERVED0 : 27; //!< [31:5] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csio_cpd_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSIO_CPD_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSIO_CPD_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x30028)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSIO_CPD_CTRL(x) (*(volatile hw_ipu_csio_cpd_ctrl_t *) HW_IPU_CSIO_CPD_CTRL_ADDR(x))
|
|
#define HW_IPU_CSIO_CPD_CTRL_RD(x) (HW_IPU_CSIO_CPD_CTRL(x).U)
|
|
#define HW_IPU_CSIO_CPD_CTRL_WR(x, v) (HW_IPU_CSIO_CPD_CTRL(x).U = (v))
|
|
#define HW_IPU_CSIO_CPD_CTRL_SET(x, v) (HW_IPU_CSIO_CPD_CTRL_WR(x, HW_IPU_CSIO_CPD_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_CSIO_CPD_CTRL_CLR(x, v) (HW_IPU_CSIO_CPD_CTRL_WR(x, HW_IPU_CSIO_CPD_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_CSIO_CPD_CTRL_TOG(x, v) (HW_IPU_CSIO_CPD_CTRL_WR(x, HW_IPU_CSIO_CPD_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSIO_CPD_CTRL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSIO_CPD_CTRL, field CSI0_GREEN_P_BEGIN[0] (RW)
|
|
*
|
|
* Color of first component in the frame. Reserved
|
|
*
|
|
* Values:
|
|
* - 0 - First component in the frame is blue or red, depending from RED_ROW bit.
|
|
* - 1 - First component in the frame is green
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN (0) //!< Bit position for IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN.
|
|
#define BM_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN (0x00000001) //!< Bit mask for IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN from a register value.
|
|
#define BG_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN) >> BP_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN.
|
|
#define BF_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN) & BM_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_GREEN_P_BEGIN field to a new value.
|
|
#define BW_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN(x, v) (HW_IPU_CSIO_CPD_CTRL_WR(x, (HW_IPU_CSIO_CPD_CTRL_RD(x) & ~BM_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN) | BF_IPU_CSIO_CPD_CTRL_CSI0_GREEN_P_BEGIN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_CTRL, field CSI0_RED_ROW_BEGIN[1] (RW)
|
|
*
|
|
* Color of first row in the frame. Reserved
|
|
*
|
|
* Values:
|
|
* - 0 - First row in the frame is GBGB.
|
|
* - 1 - First row in the frame is GRGR.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN (1) //!< Bit position for IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN.
|
|
#define BM_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN (0x00000002) //!< Bit mask for IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN from a register value.
|
|
#define BG_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN) >> BP_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN.
|
|
#define BF_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN) & BM_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_RED_ROW_BEGIN field to a new value.
|
|
#define BW_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN(x, v) (HW_IPU_CSIO_CPD_CTRL_WR(x, (HW_IPU_CSIO_CPD_CTRL_RD(x) & ~BM_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN) | BF_IPU_CSIO_CPD_CTRL_CSI0_RED_ROW_BEGIN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_CTRL, field CSI0_CPD[4:2] (RW)
|
|
*
|
|
* CSI0_CPD These bits enable the compander in the path to different destination. CSI0_CPD[0] -
|
|
* CSI0_CPD[1] - Enable for the compander for data sent to the IC CSI0_CPD[2] - Enable for the
|
|
* compander for data sent to the IDMAC via SMFC If all the 3 bits are zero the compander is
|
|
* disabled Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_CTRL_CSI0_CPD (2) //!< Bit position for IPU_CSIO_CPD_CTRL_CSI0_CPD.
|
|
#define BM_IPU_CSIO_CPD_CTRL_CSI0_CPD (0x0000001c) //!< Bit mask for IPU_CSIO_CPD_CTRL_CSI0_CPD.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_CTRL_CSI0_CPD from a register value.
|
|
#define BG_IPU_CSIO_CPD_CTRL_CSI0_CPD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_CTRL_CSI0_CPD) >> BP_IPU_CSIO_CPD_CTRL_CSI0_CPD)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_CTRL_CSI0_CPD.
|
|
#define BF_IPU_CSIO_CPD_CTRL_CSI0_CPD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_CTRL_CSI0_CPD) & BM_IPU_CSIO_CPD_CTRL_CSI0_CPD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD field to a new value.
|
|
#define BW_IPU_CSIO_CPD_CTRL_CSI0_CPD(x, v) (HW_IPU_CSIO_CPD_CTRL_WR(x, (HW_IPU_CSIO_CPD_CTRL_RD(x) & ~BM_IPU_CSIO_CPD_CTRL_CSI0_CPD) | BF_IPU_CSIO_CPD_CTRL_CSI0_CPD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSIO_CPD_RC_I - CSI0 Red Component Compander Constants Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSIO_CPD_RC_I - CSI0 Red Component Compander Constants Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain CONSTANT <i> parameters used for companding of red component.
|
|
*/
|
|
typedef union _hw_ipu_csio_cpd_rc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_rc_i_bitfields
|
|
{
|
|
unsigned CSI0_CPD_RC_2I : 9; //!< [8:0] CONSTANT <2*i> parameter of Compander, Red component.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned CSI0_CPD_RC_2I_1 : 9; //!< [24:16] CONSTANT <2*i+1> parameter of Compander, Red component.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_csio_cpd_rc_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSIO_CPD_RC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSIO_CPD_RC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3002c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSIO_CPD_RC_I(x) (*(volatile hw_ipu_csio_cpd_rc_i_t *) HW_IPU_CSIO_CPD_RC_I_ADDR(x))
|
|
#define HW_IPU_CSIO_CPD_RC_I_RD(x) (HW_IPU_CSIO_CPD_RC_I(x).U)
|
|
#define HW_IPU_CSIO_CPD_RC_I_WR(x, v) (HW_IPU_CSIO_CPD_RC_I(x).U = (v))
|
|
#define HW_IPU_CSIO_CPD_RC_I_SET(x, v) (HW_IPU_CSIO_CPD_RC_I_WR(x, HW_IPU_CSIO_CPD_RC_I_RD(x) | (v)))
|
|
#define HW_IPU_CSIO_CPD_RC_I_CLR(x, v) (HW_IPU_CSIO_CPD_RC_I_WR(x, HW_IPU_CSIO_CPD_RC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSIO_CPD_RC_I_TOG(x, v) (HW_IPU_CSIO_CPD_RC_I_WR(x, HW_IPU_CSIO_CPD_RC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSIO_CPD_RC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSIO_CPD_RC_I, field CSI0_CPD_RC_2I[8:0] (RW)
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*
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* CONSTANT <2*i> parameter of Compander, Red component. Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I (0) //!< Bit position for IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I.
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#define BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I (0x000001ff) //!< Bit mask for IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I.
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//! @brief Get value of IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I from a register value.
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#define BG_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I) >> BP_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I)
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//! @brief Format value for bitfield IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I.
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#define BF_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I) & BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_RC_2I field to a new value.
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#define BW_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I(x, v) (HW_IPU_CSIO_CPD_RC_I_WR(x, (HW_IPU_CSIO_CPD_RC_I_RD(x) & ~BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I) | BF_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_RC_I, field CSI0_CPD_RC_2I_1[24:16] (RW)
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*
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* CONSTANT <2*i+1> parameter of Compander, Red component. Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1 (16) //!< Bit position for IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1.
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#define BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1.
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//! @brief Get value of IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1 from a register value.
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#define BG_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1) >> BP_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1)
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//! @brief Format value for bitfield IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1.
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#define BF_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1) & BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_RC_2I_1 field to a new value.
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#define BW_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1(x, v) (HW_IPU_CSIO_CPD_RC_I_WR(x, (HW_IPU_CSIO_CPD_RC_I_RD(x) & ~BM_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1) | BF_IPU_CSIO_CPD_RC_I_CSI0_CPD_RC_2I_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CSIO_CPD_RS_I - CSI0 Red Component Compander SLOPE Register <i>
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_CSIO_CPD_RS_I - CSI0 Red Component Compander SLOPE Register <i> (RW)
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*
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* Reset value: 0x00000000
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*
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* These registers contain SLOPE <i> parameters used for companding of red component.
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*/
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typedef union _hw_ipu_csio_cpd_rs_i
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{
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reg32_t U;
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struct _hw_ipu_csio_cpd_rs_i_bitfields
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{
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unsigned CSI0_CPD_RS_4I : 8; //!< [7:0] Reserved
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unsigned CSI0_CPD_RS_4I_1 : 8; //!< [15:8] Reserved
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unsigned CSI0_CPD_RS_4I_2 : 8; //!< [23:16] Reserved
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unsigned CSI0_CPD_RS_4I_3 : 8; //!< [31:24] Reserved
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} B;
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} hw_ipu_csio_cpd_rs_i_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_CSIO_CPD_RS_I register
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*/
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//@{
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#define HW_IPU_CSIO_CPD_RS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3004c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_CSIO_CPD_RS_I(x) (*(volatile hw_ipu_csio_cpd_rs_i_t *) HW_IPU_CSIO_CPD_RS_I_ADDR(x))
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#define HW_IPU_CSIO_CPD_RS_I_RD(x) (HW_IPU_CSIO_CPD_RS_I(x).U)
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#define HW_IPU_CSIO_CPD_RS_I_WR(x, v) (HW_IPU_CSIO_CPD_RS_I(x).U = (v))
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#define HW_IPU_CSIO_CPD_RS_I_SET(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, HW_IPU_CSIO_CPD_RS_I_RD(x) | (v)))
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#define HW_IPU_CSIO_CPD_RS_I_CLR(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, HW_IPU_CSIO_CPD_RS_I_RD(x) & ~(v)))
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#define HW_IPU_CSIO_CPD_RS_I_TOG(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, HW_IPU_CSIO_CPD_RS_I_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_CSIO_CPD_RS_I bitfields
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*/
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/*! @name Register IPU_CSIO_CPD_RS_I, field CSI0_CPD_RS_4I[7:0] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I (0) //!< Bit position for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I.
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#define BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I (0x000000ff) //!< Bit mask for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I.
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//! @brief Get value of IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I from a register value.
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#define BG_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I) >> BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I)
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//! @brief Format value for bitfield IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I.
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#define BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_RS_4I field to a new value.
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#define BW_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, (HW_IPU_CSIO_CPD_RS_I_RD(x) & ~BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I) | BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_RS_I, field CSI0_CPD_RS_4I_1[15:8] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1 (8) //!< Bit position for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1.
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#define BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1.
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//! @brief Get value of IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1 from a register value.
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#define BG_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1) >> BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1)
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//! @brief Format value for bitfield IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1.
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#define BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_RS_4I_1 field to a new value.
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#define BW_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, (HW_IPU_CSIO_CPD_RS_I_RD(x) & ~BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1) | BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_1(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_RS_I, field CSI0_CPD_RS_4I_2[23:16] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2 (16) //!< Bit position for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2.
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#define BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2.
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//! @brief Get value of IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2 from a register value.
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#define BG_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2) >> BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2)
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//! @brief Format value for bitfield IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2.
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|
#define BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_RS_4I_2 field to a new value.
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|
#define BW_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, (HW_IPU_CSIO_CPD_RS_I_RD(x) & ~BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2) | BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_2(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_RS_I, field CSI0_CPD_RS_4I_3[31:24] (RW)
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*
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|
* Reserved
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|
*/
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//@{
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|
#define BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3 (24) //!< Bit position for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3.
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#define BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3 (0xff000000) //!< Bit mask for IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3.
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//! @brief Get value of IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3 from a register value.
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#define BG_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3) >> BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3)
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//! @brief Format value for bitfield IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3.
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#define BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3) & BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_RS_4I_3 field to a new value.
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#define BW_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3(x, v) (HW_IPU_CSIO_CPD_RS_I_WR(x, (HW_IPU_CSIO_CPD_RS_I_RD(x) & ~BM_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3) | BF_IPU_CSIO_CPD_RS_I_CSI0_CPD_RS_4I_3(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CSIO_CPD_GRC_I - CSI0 GR Component Compander Constants Register <i>
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//-------------------------------------------------------------------------------------------
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|
#ifndef __LANGUAGE_ASM__
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|
/*!
|
|
* @brief HW_IPU_CSIO_CPD_GRC_I - CSI0 GR Component Compander Constants Register <i> (RW)
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|
*
|
|
* Reset value: 0x00000000
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|
*
|
|
* These registers contain CONSTANTi parameters used for companding of green components in GRGR
|
|
* rows.
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|
*/
|
|
typedef union _hw_ipu_csio_cpd_grc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_grc_i_bitfields
|
|
{
|
|
unsigned CSI0_CPD_GRC_2I : 9; //!< [8:0] Reserved
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|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
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|
unsigned CSI0_CPD_GRC_2I_1 : 9; //!< [24:16] Reserved
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unsigned RESERVED1 : 7; //!< [31:25] Reserved.
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} B;
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|
} hw_ipu_csio_cpd_grc_i_t;
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#endif
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|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSIO_CPD_GRC_I register
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|
*/
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|
//@{
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|
#define HW_IPU_CSIO_CPD_GRC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3005c)
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|
#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_CSIO_CPD_GRC_I(x) (*(volatile hw_ipu_csio_cpd_grc_i_t *) HW_IPU_CSIO_CPD_GRC_I_ADDR(x))
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#define HW_IPU_CSIO_CPD_GRC_I_RD(x) (HW_IPU_CSIO_CPD_GRC_I(x).U)
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#define HW_IPU_CSIO_CPD_GRC_I_WR(x, v) (HW_IPU_CSIO_CPD_GRC_I(x).U = (v))
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#define HW_IPU_CSIO_CPD_GRC_I_SET(x, v) (HW_IPU_CSIO_CPD_GRC_I_WR(x, HW_IPU_CSIO_CPD_GRC_I_RD(x) | (v)))
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#define HW_IPU_CSIO_CPD_GRC_I_CLR(x, v) (HW_IPU_CSIO_CPD_GRC_I_WR(x, HW_IPU_CSIO_CPD_GRC_I_RD(x) & ~(v)))
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#define HW_IPU_CSIO_CPD_GRC_I_TOG(x, v) (HW_IPU_CSIO_CPD_GRC_I_WR(x, HW_IPU_CSIO_CPD_GRC_I_RD(x) ^ (v)))
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#endif
|
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//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_CSIO_CPD_GRC_I bitfields
|
|
*/
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|
/*! @name Register IPU_CSIO_CPD_GRC_I, field CSI0_CPD_GRC_2I[8:0] (RW)
|
|
*
|
|
* Reserved
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|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I (0) //!< Bit position for IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I.
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|
#define BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I (0x000001ff) //!< Bit mask for IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I.
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|
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|
//! @brief Get value of IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I from a register value.
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|
#define BG_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I) >> BP_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I)
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|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I.
|
|
#define BF_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I) & BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_GRC_2I field to a new value.
|
|
#define BW_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I(x, v) (HW_IPU_CSIO_CPD_GRC_I_WR(x, (HW_IPU_CSIO_CPD_GRC_I_RD(x) & ~BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I) | BF_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_GRC_I, field CSI0_CPD_GRC_2I_1[24:16] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1 (16) //!< Bit position for IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1.
|
|
#define BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1.
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|
|
|
//! @brief Get value of IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1 from a register value.
|
|
#define BG_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1) >> BP_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1.
|
|
#define BF_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1) & BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
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//! @brief Set the CSI0_CPD_GRC_2I_1 field to a new value.
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#define BW_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1(x, v) (HW_IPU_CSIO_CPD_GRC_I_WR(x, (HW_IPU_CSIO_CPD_GRC_I_RD(x) & ~BM_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1) | BF_IPU_CSIO_CPD_GRC_I_CSI0_CPD_GRC_2I_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CSIO_CPD_GRS_I - CSI0 GR Component Compander SLOPE Register <i>
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_CSIO_CPD_GRS_I - CSI0 GR Component Compander SLOPE Register <i> (RW)
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*
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* Reset value: 0x00000000
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*
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* These registers contain SLOPEi parameters used for companding of green components in GRGR rows.
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*/
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typedef union _hw_ipu_csio_cpd_grs_i
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{
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reg32_t U;
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struct _hw_ipu_csio_cpd_grs_i_bitfields
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{
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unsigned CSI0_CPD_GRS_4I : 8; //!< [7:0] Reserved
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unsigned CSI0_CPD_GRS_4I_1 : 8; //!< [15:8] Reserved
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unsigned CSI0_CPD_GRS_4I_2 : 8; //!< [23:16] Reserved
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unsigned CSI0_CPD_GRS_4I_3 : 8; //!< [31:24] Reserved
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} B;
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} hw_ipu_csio_cpd_grs_i_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_CSIO_CPD_GRS_I register
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*/
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//@{
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#define HW_IPU_CSIO_CPD_GRS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3007c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_CSIO_CPD_GRS_I(x) (*(volatile hw_ipu_csio_cpd_grs_i_t *) HW_IPU_CSIO_CPD_GRS_I_ADDR(x))
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#define HW_IPU_CSIO_CPD_GRS_I_RD(x) (HW_IPU_CSIO_CPD_GRS_I(x).U)
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#define HW_IPU_CSIO_CPD_GRS_I_WR(x, v) (HW_IPU_CSIO_CPD_GRS_I(x).U = (v))
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#define HW_IPU_CSIO_CPD_GRS_I_SET(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, HW_IPU_CSIO_CPD_GRS_I_RD(x) | (v)))
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#define HW_IPU_CSIO_CPD_GRS_I_CLR(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, HW_IPU_CSIO_CPD_GRS_I_RD(x) & ~(v)))
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#define HW_IPU_CSIO_CPD_GRS_I_TOG(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, HW_IPU_CSIO_CPD_GRS_I_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_CSIO_CPD_GRS_I bitfields
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*/
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/*! @name Register IPU_CSIO_CPD_GRS_I, field CSI0_CPD_GRS_4I[7:0] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I (0) //!< Bit position for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I.
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#define BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I (0x000000ff) //!< Bit mask for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I.
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//! @brief Get value of IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I from a register value.
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#define BG_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I) >> BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I.
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#define BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_GRS_4I field to a new value.
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#define BW_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, (HW_IPU_CSIO_CPD_GRS_I_RD(x) & ~BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I) | BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_GRS_I, field CSI0_CPD_GRS_4I_1[15:8] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1 (8) //!< Bit position for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1.
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#define BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1.
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//! @brief Get value of IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1 from a register value.
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#define BG_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1) >> BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1.
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#define BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_GRS_4I_1 field to a new value.
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#define BW_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, (HW_IPU_CSIO_CPD_GRS_I_RD(x) & ~BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1) | BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_1(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_GRS_I, field CSI0_CPD_GRS_4I_2[23:16] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2 (16) //!< Bit position for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2.
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#define BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2.
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//! @brief Get value of IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2 from a register value.
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#define BG_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2) >> BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2.
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#define BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_GRS_4I_2 field to a new value.
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#define BW_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, (HW_IPU_CSIO_CPD_GRS_I_RD(x) & ~BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2) | BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_2(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_GRS_I, field CSI0_CPD_GRS_4I_3[31:24] (RW)
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*
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* Reserved
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*/
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//@{
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#define BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3 (24) //!< Bit position for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3.
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#define BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3 (0xff000000) //!< Bit mask for IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3.
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//! @brief Get value of IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3 from a register value.
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#define BG_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3) >> BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3.
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#define BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3) & BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI0_CPD_GRS_4I_3 field to a new value.
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#define BW_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3(x, v) (HW_IPU_CSIO_CPD_GRS_I_WR(x, (HW_IPU_CSIO_CPD_GRS_I_RD(x) & ~BM_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3) | BF_IPU_CSIO_CPD_GRS_I_CSI0_CPD_GRS_4I_3(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CSIO_CPD_GBC_I - CSI0 GB Component Compander Constants Register <i>
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_CSIO_CPD_GBC_I - CSI0 GB Component Compander Constants Register <i> (RW)
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|
*
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* Reset value: 0x00000000
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*
|
|
* These registers contain CONSTANTi parameters used for companding of green components in GBGB
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* rows.
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*/
|
|
typedef union _hw_ipu_csio_cpd_gbc_i
|
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{
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|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_gbc_i_bitfields
|
|
{
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|
unsigned CSI0_CPD_GBC_2I : 9; //!< [8:0] Reserved
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unsigned RESERVED0 : 7; //!< [15:9] Reserved.
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unsigned CSI0_CPD_GBC_2I_1 : 9; //!< [24:16] Reserved
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unsigned RESERVED1 : 7; //!< [31:25] Reserved.
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} B;
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|
} hw_ipu_csio_cpd_gbc_i_t;
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#endif
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/*!
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|
* @name Constants and macros for entire IPU_CSIO_CPD_GBC_I register
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*/
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//@{
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|
#define HW_IPU_CSIO_CPD_GBC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3008c)
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|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSIO_CPD_GBC_I(x) (*(volatile hw_ipu_csio_cpd_gbc_i_t *) HW_IPU_CSIO_CPD_GBC_I_ADDR(x))
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#define HW_IPU_CSIO_CPD_GBC_I_RD(x) (HW_IPU_CSIO_CPD_GBC_I(x).U)
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#define HW_IPU_CSIO_CPD_GBC_I_WR(x, v) (HW_IPU_CSIO_CPD_GBC_I(x).U = (v))
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#define HW_IPU_CSIO_CPD_GBC_I_SET(x, v) (HW_IPU_CSIO_CPD_GBC_I_WR(x, HW_IPU_CSIO_CPD_GBC_I_RD(x) | (v)))
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#define HW_IPU_CSIO_CPD_GBC_I_CLR(x, v) (HW_IPU_CSIO_CPD_GBC_I_WR(x, HW_IPU_CSIO_CPD_GBC_I_RD(x) & ~(v)))
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#define HW_IPU_CSIO_CPD_GBC_I_TOG(x, v) (HW_IPU_CSIO_CPD_GBC_I_WR(x, HW_IPU_CSIO_CPD_GBC_I_RD(x) ^ (v)))
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#endif
|
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//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSIO_CPD_GBC_I bitfields
|
|
*/
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|
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/*! @name Register IPU_CSIO_CPD_GBC_I, field CSI0_CPD_GBC_2I[8:0] (RW)
|
|
*
|
|
* Reserved
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|
*/
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|
//@{
|
|
#define BP_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I (0) //!< Bit position for IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I.
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#define BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I (0x000001ff) //!< Bit mask for IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I.
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//! @brief Get value of IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I from a register value.
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#define BG_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I) >> BP_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I.
|
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#define BF_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I) & BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_GBC_2I field to a new value.
|
|
#define BW_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I(x, v) (HW_IPU_CSIO_CPD_GBC_I_WR(x, (HW_IPU_CSIO_CPD_GBC_I_RD(x) & ~BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I) | BF_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_GBC_I, field CSI0_CPD_GBC_2I_1[24:16] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1 (16) //!< Bit position for IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1.
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#define BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1.
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|
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|
//! @brief Get value of IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1 from a register value.
|
|
#define BG_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1) >> BP_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1)
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|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1.
|
|
#define BF_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1) & BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_GBC_2I_1 field to a new value.
|
|
#define BW_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1(x, v) (HW_IPU_CSIO_CPD_GBC_I_WR(x, (HW_IPU_CSIO_CPD_GBC_I_RD(x) & ~BM_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1) | BF_IPU_CSIO_CPD_GBC_I_CSI0_CPD_GBC_2I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSIO_CPD_GBS_I - CSI0 GB Component Compander SLOPE Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSIO_CPD_GBS_I - CSI0 GB Component Compander SLOPE Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain SLOPEi parameters used for companding of green components in GBGB rows.
|
|
*/
|
|
typedef union _hw_ipu_csio_cpd_gbs_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_gbs_i_bitfields
|
|
{
|
|
unsigned CSI0_CPD_GBS_4I : 8; //!< [7:0] Reserved
|
|
unsigned CSI0_CPD_GBS_4I_1 : 8; //!< [15:8] Reserved
|
|
unsigned CSI0_CPD_GBS_4I_2 : 8; //!< [23:16] Reserved
|
|
unsigned CSI0_CPD_GBS_4I_3 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_csio_cpd_gbs_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSIO_CPD_GBS_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSIO_CPD_GBS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x300ac)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSIO_CPD_GBS_I(x) (*(volatile hw_ipu_csio_cpd_gbs_i_t *) HW_IPU_CSIO_CPD_GBS_I_ADDR(x))
|
|
#define HW_IPU_CSIO_CPD_GBS_I_RD(x) (HW_IPU_CSIO_CPD_GBS_I(x).U)
|
|
#define HW_IPU_CSIO_CPD_GBS_I_WR(x, v) (HW_IPU_CSIO_CPD_GBS_I(x).U = (v))
|
|
#define HW_IPU_CSIO_CPD_GBS_I_SET(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, HW_IPU_CSIO_CPD_GBS_I_RD(x) | (v)))
|
|
#define HW_IPU_CSIO_CPD_GBS_I_CLR(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, HW_IPU_CSIO_CPD_GBS_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSIO_CPD_GBS_I_TOG(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, HW_IPU_CSIO_CPD_GBS_I_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
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/*
|
|
* constants & macros for individual IPU_CSIO_CPD_GBS_I bitfields
|
|
*/
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/*! @name Register IPU_CSIO_CPD_GBS_I, field CSI0_CPD_GBS_4I[7:0] (RW)
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|
*
|
|
* Reserved
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|
*/
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|
//@{
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|
#define BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I (0) //!< Bit position for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I.
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#define BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I (0x000000ff) //!< Bit mask for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I.
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//! @brief Get value of IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I from a register value.
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|
#define BG_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I) >> BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I.
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#define BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the CSI0_CPD_GBS_4I field to a new value.
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|
#define BW_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, (HW_IPU_CSIO_CPD_GBS_I_RD(x) & ~BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I) | BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I(v)))
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#endif
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//@}
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/*! @name Register IPU_CSIO_CPD_GBS_I, field CSI0_CPD_GBS_4I_1[15:8] (RW)
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|
*
|
|
* Reserved
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|
*/
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|
//@{
|
|
#define BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1 (8) //!< Bit position for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1.
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#define BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1.
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//! @brief Get value of IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1 from a register value.
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#define BG_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1) >> BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1.
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#define BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the CSI0_CPD_GBS_4I_1 field to a new value.
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|
#define BW_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, (HW_IPU_CSIO_CPD_GBS_I_RD(x) & ~BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1) | BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_1(v)))
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#endif
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|
//@}
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/*! @name Register IPU_CSIO_CPD_GBS_I, field CSI0_CPD_GBS_4I_2[23:16] (RW)
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|
*
|
|
* Reserved
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|
*/
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|
//@{
|
|
#define BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2 (16) //!< Bit position for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2.
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#define BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2.
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//! @brief Get value of IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2 from a register value.
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|
#define BG_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2) >> BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2)
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//! @brief Format value for bitfield IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2.
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|
#define BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the CSI0_CPD_GBS_4I_2 field to a new value.
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|
#define BW_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, (HW_IPU_CSIO_CPD_GBS_I_RD(x) & ~BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2) | BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_2(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_CSIO_CPD_GBS_I, field CSI0_CPD_GBS_4I_3[31:24] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3 (24) //!< Bit position for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3.
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|
#define BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3 (0xff000000) //!< Bit mask for IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3.
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|
|
//! @brief Get value of IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3 from a register value.
|
|
#define BG_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3) >> BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3)
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|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3.
|
|
#define BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3) & BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_GBS_4I_3 field to a new value.
|
|
#define BW_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3(x, v) (HW_IPU_CSIO_CPD_GBS_I_WR(x, (HW_IPU_CSIO_CPD_GBS_I_RD(x) & ~BM_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3) | BF_IPU_CSIO_CPD_GBS_I_CSI0_CPD_GBS_4I_3(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSIO_CPD_BC_I - CSI0 Blue Component Compander Constants Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSIO_CPD_BC_I - CSI0 Blue Component Compander Constants Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain CONSTANTi parameters used for companding of blue component.
|
|
*/
|
|
typedef union _hw_ipu_csio_cpd_bc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_bc_i_bitfields
|
|
{
|
|
unsigned CSI0_CPD_BC_2I : 9; //!< [8:0] Reserved
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned CSI0_CPD_BC_2I_1 : 9; //!< [24:16] Reserved
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_csio_cpd_bc_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSIO_CPD_BC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSIO_CPD_BC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x300bc)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSIO_CPD_BC_I(x) (*(volatile hw_ipu_csio_cpd_bc_i_t *) HW_IPU_CSIO_CPD_BC_I_ADDR(x))
|
|
#define HW_IPU_CSIO_CPD_BC_I_RD(x) (HW_IPU_CSIO_CPD_BC_I(x).U)
|
|
#define HW_IPU_CSIO_CPD_BC_I_WR(x, v) (HW_IPU_CSIO_CPD_BC_I(x).U = (v))
|
|
#define HW_IPU_CSIO_CPD_BC_I_SET(x, v) (HW_IPU_CSIO_CPD_BC_I_WR(x, HW_IPU_CSIO_CPD_BC_I_RD(x) | (v)))
|
|
#define HW_IPU_CSIO_CPD_BC_I_CLR(x, v) (HW_IPU_CSIO_CPD_BC_I_WR(x, HW_IPU_CSIO_CPD_BC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSIO_CPD_BC_I_TOG(x, v) (HW_IPU_CSIO_CPD_BC_I_WR(x, HW_IPU_CSIO_CPD_BC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSIO_CPD_BC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSIO_CPD_BC_I, field CSI0_CPD_BC_2I[8:0] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I (0) //!< Bit position for IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I.
|
|
#define BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I (0x000001ff) //!< Bit mask for IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I from a register value.
|
|
#define BG_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I) >> BP_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I.
|
|
#define BF_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I) & BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_BC_2I field to a new value.
|
|
#define BW_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I(x, v) (HW_IPU_CSIO_CPD_BC_I_WR(x, (HW_IPU_CSIO_CPD_BC_I_RD(x) & ~BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I) | BF_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_BC_I, field CSI0_CPD_BC_2I_1[24:16] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1 (16) //!< Bit position for IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1.
|
|
#define BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1 from a register value.
|
|
#define BG_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1) >> BP_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1.
|
|
#define BF_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1) & BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_BC_2I_1 field to a new value.
|
|
#define BW_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1(x, v) (HW_IPU_CSIO_CPD_BC_I_WR(x, (HW_IPU_CSIO_CPD_BC_I_RD(x) & ~BM_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1) | BF_IPU_CSIO_CPD_BC_I_CSI0_CPD_BC_2I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSIO_CPD_BS_I - CSI0 Blue Component Compander SLOPE Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSIO_CPD_BS_I - CSI0 Blue Component Compander SLOPE Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain SLOPEi parameters used for companding of red component.
|
|
*/
|
|
typedef union _hw_ipu_csio_cpd_bs_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csio_cpd_bs_i_bitfields
|
|
{
|
|
unsigned CSI0_CPD_BS_4I : 8; //!< [7:0] Reserved
|
|
unsigned CSI0_CPD_BS_4I_1 : 8; //!< [15:8] Reserved
|
|
unsigned CSI0_CPD_BS_4I_2 : 8; //!< [23:16] Reserved
|
|
unsigned CSI0_CPD_BS_4I_3 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_csio_cpd_bs_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSIO_CPD_BS_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSIO_CPD_BS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x300dc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSIO_CPD_BS_I(x) (*(volatile hw_ipu_csio_cpd_bs_i_t *) HW_IPU_CSIO_CPD_BS_I_ADDR(x))
|
|
#define HW_IPU_CSIO_CPD_BS_I_RD(x) (HW_IPU_CSIO_CPD_BS_I(x).U)
|
|
#define HW_IPU_CSIO_CPD_BS_I_WR(x, v) (HW_IPU_CSIO_CPD_BS_I(x).U = (v))
|
|
#define HW_IPU_CSIO_CPD_BS_I_SET(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, HW_IPU_CSIO_CPD_BS_I_RD(x) | (v)))
|
|
#define HW_IPU_CSIO_CPD_BS_I_CLR(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, HW_IPU_CSIO_CPD_BS_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSIO_CPD_BS_I_TOG(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, HW_IPU_CSIO_CPD_BS_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSIO_CPD_BS_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSIO_CPD_BS_I, field CSI0_CPD_BS_4I[7:0] (RW)
|
|
*
|
|
* Reserved l
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I (0) //!< Bit position for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I.
|
|
#define BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I (0x000000ff) //!< Bit mask for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I from a register value.
|
|
#define BG_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I) >> BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I.
|
|
#define BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_BS_4I field to a new value.
|
|
#define BW_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, (HW_IPU_CSIO_CPD_BS_I_RD(x) & ~BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I) | BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_BS_I, field CSI0_CPD_BS_4I_1[15:8] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1 (8) //!< Bit position for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1.
|
|
#define BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1.
|
|
|
|
//! @brief Get value of IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1 from a register value.
|
|
#define BG_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1) >> BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1.
|
|
#define BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_BS_4I_1 field to a new value.
|
|
#define BW_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, (HW_IPU_CSIO_CPD_BS_I_RD(x) & ~BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1) | BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_1(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSIO_CPD_BS_I, field CSI0_CPD_BS_4I_2[23:16] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2 (16) //!< Bit position for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2.
|
|
#define BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2.
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|
|
//! @brief Get value of IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2 from a register value.
|
|
#define BG_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2) >> BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2)
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//! @brief Format value for bitfield IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2.
|
|
#define BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_BS_4I_2 field to a new value.
|
|
#define BW_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, (HW_IPU_CSIO_CPD_BS_I_RD(x) & ~BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2) | BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_2(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_CSIO_CPD_BS_I, field CSI0_CPD_BS_4I_3[31:24] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3 (24) //!< Bit position for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3.
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|
#define BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3 (0xff000000) //!< Bit mask for IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3.
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|
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//! @brief Get value of IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3 from a register value.
|
|
#define BG_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3) >> BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3)
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|
|
//! @brief Format value for bitfield IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3.
|
|
#define BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3) & BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_BS_4I_3 field to a new value.
|
|
#define BW_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3(x, v) (HW_IPU_CSIO_CPD_BS_I_WR(x, (HW_IPU_CSIO_CPD_BS_I_RD(x) & ~BM_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3) | BF_IPU_CSIO_CPD_BS_I_CSI0_CPD_BS_4I_3(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_CPD_OFFSET1 - CSI0 Compander Offset Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_CPD_OFFSET1 - CSI0 Compander Offset Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain Offset parameters used for companding.
|
|
*/
|
|
typedef union _hw_ipu_csi0_cpd_offset1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_cpd_offset1_bitfields
|
|
{
|
|
unsigned CSI0_GR_OFFSET : 10; //!< [9:0] Reserved
|
|
unsigned CSI0_GB_OFFSET : 10; //!< [19:10] Reserved
|
|
unsigned CSI0_CPD_B_OFFSET : 10; //!< [29:20] Reserved
|
|
unsigned RESERVED0 : 2; //!< [31:30] Reserved
|
|
} B;
|
|
} hw_ipu_csi0_cpd_offset1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_CPD_OFFSET1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_CPD_OFFSET1_ADDR(x) (REGS_IPU_BASE(x) + 0x300ec)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_CPD_OFFSET1(x) (*(volatile hw_ipu_csi0_cpd_offset1_t *) HW_IPU_CSI0_CPD_OFFSET1_ADDR(x))
|
|
#define HW_IPU_CSI0_CPD_OFFSET1_RD(x) (HW_IPU_CSI0_CPD_OFFSET1(x).U)
|
|
#define HW_IPU_CSI0_CPD_OFFSET1_WR(x, v) (HW_IPU_CSI0_CPD_OFFSET1(x).U = (v))
|
|
#define HW_IPU_CSI0_CPD_OFFSET1_SET(x, v) (HW_IPU_CSI0_CPD_OFFSET1_WR(x, HW_IPU_CSI0_CPD_OFFSET1_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_CPD_OFFSET1_CLR(x, v) (HW_IPU_CSI0_CPD_OFFSET1_WR(x, HW_IPU_CSI0_CPD_OFFSET1_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_CPD_OFFSET1_TOG(x, v) (HW_IPU_CSI0_CPD_OFFSET1_WR(x, HW_IPU_CSI0_CPD_OFFSET1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_CPD_OFFSET1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_CPD_OFFSET1, field CSI0_GR_OFFSET[9:0] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET (0) //!< Bit position for IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET.
|
|
#define BM_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET (0x000003ff) //!< Bit mask for IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET from a register value.
|
|
#define BG_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET) >> BP_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET.
|
|
#define BF_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET) & BM_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_GR_OFFSET field to a new value.
|
|
#define BW_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET(x, v) (HW_IPU_CSI0_CPD_OFFSET1_WR(x, (HW_IPU_CSI0_CPD_OFFSET1_RD(x) & ~BM_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET) | BF_IPU_CSI0_CPD_OFFSET1_CSI0_GR_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CPD_OFFSET1, field CSI0_GB_OFFSET[19:10] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET (10) //!< Bit position for IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET.
|
|
#define BM_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET (0x000ffc00) //!< Bit mask for IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET.
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|
|
|
//! @brief Get value of IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET from a register value.
|
|
#define BG_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET) >> BP_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET.
|
|
#define BF_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET) & BM_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_GB_OFFSET field to a new value.
|
|
#define BW_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET(x, v) (HW_IPU_CSI0_CPD_OFFSET1_WR(x, (HW_IPU_CSI0_CPD_OFFSET1_RD(x) & ~BM_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET) | BF_IPU_CSI0_CPD_OFFSET1_CSI0_GB_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI0_CPD_OFFSET1, field CSI0_CPD_B_OFFSET[29:20] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET (20) //!< Bit position for IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET.
|
|
#define BM_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET (0x3ff00000) //!< Bit mask for IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET from a register value.
|
|
#define BG_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET) >> BP_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET.
|
|
#define BF_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET) & BM_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_B_OFFSET field to a new value.
|
|
#define BW_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET(x, v) (HW_IPU_CSI0_CPD_OFFSET1_WR(x, (HW_IPU_CSI0_CPD_OFFSET1_RD(x) & ~BM_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET) | BF_IPU_CSI0_CPD_OFFSET1_CSI0_CPD_B_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI0_CPD_OFFSET2 - CSI0 Compander Offset Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI0_CPD_OFFSET2 - CSI0 Compander Offset Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register contain Offset parameters used for companding.
|
|
*/
|
|
typedef union _hw_ipu_csi0_cpd_offset2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi0_cpd_offset2_bitfields
|
|
{
|
|
unsigned CSI0_CPD_R_OFFSET : 10; //!< [9:0] CSI0 Red component offset
|
|
unsigned RESERVED0 : 22; //!< [31:10] Reserved
|
|
} B;
|
|
} hw_ipu_csi0_cpd_offset2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI0_CPD_OFFSET2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI0_CPD_OFFSET2_ADDR(x) (REGS_IPU_BASE(x) + 0x300f0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI0_CPD_OFFSET2(x) (*(volatile hw_ipu_csi0_cpd_offset2_t *) HW_IPU_CSI0_CPD_OFFSET2_ADDR(x))
|
|
#define HW_IPU_CSI0_CPD_OFFSET2_RD(x) (HW_IPU_CSI0_CPD_OFFSET2(x).U)
|
|
#define HW_IPU_CSI0_CPD_OFFSET2_WR(x, v) (HW_IPU_CSI0_CPD_OFFSET2(x).U = (v))
|
|
#define HW_IPU_CSI0_CPD_OFFSET2_SET(x, v) (HW_IPU_CSI0_CPD_OFFSET2_WR(x, HW_IPU_CSI0_CPD_OFFSET2_RD(x) | (v)))
|
|
#define HW_IPU_CSI0_CPD_OFFSET2_CLR(x, v) (HW_IPU_CSI0_CPD_OFFSET2_WR(x, HW_IPU_CSI0_CPD_OFFSET2_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI0_CPD_OFFSET2_TOG(x, v) (HW_IPU_CSI0_CPD_OFFSET2_WR(x, HW_IPU_CSI0_CPD_OFFSET2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI0_CPD_OFFSET2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI0_CPD_OFFSET2, field CSI0_CPD_R_OFFSET[9:0] (RW)
|
|
*
|
|
* CSI0 Red component offset The value is between -512 to 511. The value is added to the red
|
|
* component before companding. Clipping: If the result of the red components value + the offset is
|
|
* smaller than 0, the result is zero If the result of the red components value + the offset is
|
|
* greater than 1023, the result is 1023 Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET (0) //!< Bit position for IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET.
|
|
#define BM_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET (0x000003ff) //!< Bit mask for IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET from a register value.
|
|
#define BG_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET) >> BP_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET.
|
|
#define BF_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET) & BM_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_CPD_R_OFFSET field to a new value.
|
|
#define BW_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET(x, v) (HW_IPU_CSI0_CPD_OFFSET2_WR(x, (HW_IPU_CSI0_CPD_OFFSET2_RD(x) & ~BM_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET) | BF_IPU_CSI0_CPD_OFFSET2_CSI0_CPD_R_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_SENS_CONF - CSI1 Sensor Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_SENS_CONF - CSI1 Sensor Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_sens_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_sens_conf_bitfields
|
|
{
|
|
unsigned CSI1_VSYNC_POL : 1; //!< [0] Invert IPP_IND_SENSB_VSYNC input.
|
|
unsigned CSI1_HSYNC_POL : 1; //!< [1] Invert IPP_IND_SENSB_HSYNC input.
|
|
unsigned CSI1_DATA_POL : 1; //!< [2] Invert data input.
|
|
unsigned CSI1_SENS_PIX_CLK_POL : 1; //!< [3] Invert Pixel clock input.
|
|
unsigned CSI1_SENS_PRTCL : 3; //!< [6:4] Sensor Protocol.
|
|
unsigned CSI1_PACK_TIGHT : 1; //!< [7] CSI1 Pack Tight
|
|
unsigned CSI1_SENS_DATA_FORMAT : 3; //!< [10:8] Data format from the sensor.
|
|
unsigned CSI1_DATA_WIDTH : 4; //!< [14:11] Data width.
|
|
unsigned CSI1_EXT_VSYNC : 1; //!< [15] External VSYNC enable.
|
|
unsigned CSI1_DIV_RATIO : 8; //!< [23:16] DIV Ratio Clock division ratio minus 1.
|
|
unsigned CSI1_DATA_DEST : 3; //!< [26:24] These bits enable the destination of the data coming from the CSI.
|
|
unsigned CSI1_JPEG8_EN : 1; //!< [27] JPEG8 enable bit
|
|
unsigned CSI1_JPEG_MODE : 1; //!< [28] JPEG Mode - this bit defines the mode of the control signals when working in JPEG mode
|
|
unsigned CSI1_FORCE_EOF : 1; //!< [29] Force End of frame
|
|
unsigned RESERVED0 : 1; //!< [30] Reserved, should be cleared.
|
|
unsigned CSI0_DATA_EN_POL : 1; //!< [31] Invert IPP_IND_SENSB_DATA_EN input.
|
|
} B;
|
|
} hw_ipu_csi1_sens_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_SENS_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_SENS_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x38000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_SENS_CONF(x) (*(volatile hw_ipu_csi1_sens_conf_t *) HW_IPU_CSI1_SENS_CONF_ADDR(x))
|
|
#define HW_IPU_CSI1_SENS_CONF_RD(x) (HW_IPU_CSI1_SENS_CONF(x).U)
|
|
#define HW_IPU_CSI1_SENS_CONF_WR(x, v) (HW_IPU_CSI1_SENS_CONF(x).U = (v))
|
|
#define HW_IPU_CSI1_SENS_CONF_SET(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, HW_IPU_CSI1_SENS_CONF_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_SENS_CONF_CLR(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, HW_IPU_CSI1_SENS_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_SENS_CONF_TOG(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, HW_IPU_CSI1_SENS_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_SENS_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_VSYNC_POL[0] (RW)
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*
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* Invert IPP_IND_SENSB_VSYNC input. This bit selects the polarity of IPP_IND_SENSB_VSYNC signal.
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*
|
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* Values:
|
|
* - 0 - IPP_IND_SENSB_VSYNC is not inverted before applied to internal circuitry.
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* - 1 - IPP_IND_SENSB_VSYNC is inverted before applied to internal circuitry.
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*/
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//@{
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#define BP_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL (0) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL.
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#define BM_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL (0x00000001) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL.
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//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL from a register value.
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#define BG_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL) >> BP_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL)
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL.
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#define BF_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL) & BM_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI1_VSYNC_POL field to a new value.
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#define BW_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL) | BF_IPU_CSI1_SENS_CONF_CSI1_VSYNC_POL(v)))
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#endif
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//@}
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_HSYNC_POL[1] (RW)
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*
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* Invert IPP_IND_SENSB_HSYNC input. This bit selects the polarity of IPP_IND_SENSB_HSYNC signal.
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*
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* Values:
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* - 0 - IPP_IND_SENSB_HSYNC is directly applied to internal circuitry.
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* - 1 - IPP_IND_SENSB_HSYNC is inverted before applied to internal circuitry.
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*/
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//@{
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#define BP_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL (1) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL.
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#define BM_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL (0x00000002) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL.
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//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL from a register value.
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#define BG_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL) >> BP_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL)
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL.
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#define BF_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL) & BM_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI1_HSYNC_POL field to a new value.
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#define BW_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL) | BF_IPU_CSI1_SENS_CONF_CSI1_HSYNC_POL(v)))
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#endif
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//@}
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_DATA_POL[2] (RW)
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*
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* Invert data input. This bit selects the polarity of data input.
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*
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|
* Values:
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|
* - 0 - data lines are directly applied to internal circuitry.
|
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* - 1 - data lines are inverted before applied to internal circuitry.
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*/
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//@{
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#define BP_IPU_CSI1_SENS_CONF_CSI1_DATA_POL (2) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_DATA_POL.
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#define BM_IPU_CSI1_SENS_CONF_CSI1_DATA_POL (0x00000004) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_DATA_POL.
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//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_DATA_POL from a register value.
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#define BG_IPU_CSI1_SENS_CONF_CSI1_DATA_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_DATA_POL) >> BP_IPU_CSI1_SENS_CONF_CSI1_DATA_POL)
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_DATA_POL.
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#define BF_IPU_CSI1_SENS_CONF_CSI1_DATA_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_DATA_POL) & BM_IPU_CSI1_SENS_CONF_CSI1_DATA_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI1_DATA_POL field to a new value.
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|
#define BW_IPU_CSI1_SENS_CONF_CSI1_DATA_POL(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_DATA_POL) | BF_IPU_CSI1_SENS_CONF_CSI1_DATA_POL(v)))
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#endif
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|
//@}
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|
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_SENS_PIX_CLK_POL[3] (RW)
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*
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* Invert Pixel clock input. This bit selects the polarity of pixel clock.
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|
*
|
|
* Values:
|
|
* - 0 - pixel clock is directly applied to internal circuitry.
|
|
* - 1 - pixel clock is inverted before applied to internal circuitry.
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|
*/
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|
//@{
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|
#define BP_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL (3) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL.
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#define BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL (0x00000008) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL.
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//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL from a register value.
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|
#define BG_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL) >> BP_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL)
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL.
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|
#define BF_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL) & BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SENS_PIX_CLK_POL field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL) | BF_IPU_CSI1_SENS_CONF_CSI1_SENS_PIX_CLK_POL(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_SENS_PRTCL[6:4] (RW)
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|
*
|
|
* Sensor Protocol. This bit defines the Sensor timing/data mode protocol. Values:
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|
*
|
|
* Values:
|
|
* - 000 - Gated clock mode
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|
* - 001 - Non-gated clock mode
|
|
* - 010 - CCIR progressive mode (BT.656)
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|
* - 011 - CCIR interlaced mode (BT.656)
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|
* - 100 - CCIR progressive (BT.1120 DDR mode: data arrives on every edge of the clock)
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|
* - 101 - CCIR progressive (BT.1120 SDR mode: data arrives only on the positive edge of the clock)
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|
* - 110 - CCIR interlaced mode (BT.1120 DDR mode: data arrives on every edge of the clock)
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|
* - 111 - CCIR interlaced mode (BT.1120 SDR mode: data arrives only on the positive edge of the clock)
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|
*/
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|
//@{
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|
#define BP_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL (4) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL.
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|
#define BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL (0x00000070) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL.
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|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL from a register value.
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|
#define BG_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL) >> BP_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL.
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|
#define BF_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL) & BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SENS_PRTCL field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL) | BF_IPU_CSI1_SENS_CONF_CSI1_SENS_PRTCL(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_PACK_TIGHT[7] (RW)
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|
*
|
|
* CSI1 Pack Tight When the data format is YUV or RGB and the component's width is 9-16 bits, it can
|
|
* be sent to the memory in 2 different ways
|
|
*
|
|
* Values:
|
|
* - 0 - Each component is written as a 16 bit word where the MSB is written to bit #15, color extension is
|
|
* done for the remaining least significant bits.
|
|
* - 1 - Three 10 bits components are packed into a 32 bit word. Color extension/reduction is performed
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|
*/
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|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT (7) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT.
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|
#define BM_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT (0x00000080) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT.
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|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT) >> BP_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT) & BM_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_PACK_TIGHT field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT) | BF_IPU_CSI1_SENS_CONF_CSI1_PACK_TIGHT(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_SENS_DATA_FORMAT[10:8] (RW)
|
|
*
|
|
* Data format from the sensor. This field defines the data format for the input of the CSI sensor.
|
|
* Values:
|
|
*
|
|
* Values:
|
|
* - 000 - full RGB or YUV444
|
|
* - 001 - YUV422 (YUYV...)
|
|
* - 010 - YUV422 (UYVY...)
|
|
* - 011 - Bayer or Generic data
|
|
* - 100 - RGB565
|
|
* - 101 - RGB555
|
|
* - 110 - RGB444
|
|
* - 111 - JPEG
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT (8) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT.
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|
#define BM_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT (0x00000700) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT.
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|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT) >> BP_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT) & BM_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SENS_DATA_FORMAT field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT) | BF_IPU_CSI1_SENS_CONF_CSI1_SENS_DATA_FORMAT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_DATA_WIDTH[14:11] (RW)
|
|
*
|
|
* Data width. This fields defines the number of bits per color. Values:
|
|
*
|
|
* Values:
|
|
* - 0000 - 4 bits per color
|
|
* - 0000 - Reserved
|
|
* - 0001 - 8 bits per color
|
|
* - 0010 - 9 bits per color
|
|
* - 0010 - Reserved
|
|
* - 0011 - 10 bits per color
|
|
* - 0100 - 11 bits per color
|
|
* - 0100 - Reserved
|
|
* - 0101 - 12 bits per color
|
|
* - 0101 - Reserved
|
|
* - 0110 - 13 bits per color
|
|
* - 0110 - Reserved
|
|
* - 0111 - 14 bits per color
|
|
* - 0111 - Reserved
|
|
* - 1000 - 15 bits per color
|
|
* - 1000 - Reserved
|
|
* - 1001 - 16 bits per color
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH (11) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH.
|
|
#define BM_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH (0x00007800) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH.
|
|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH) >> BP_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH) & BM_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_DATA_WIDTH field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH) | BF_IPU_CSI1_SENS_CONF_CSI1_DATA_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_EXT_VSYNC[15] (RW)
|
|
*
|
|
* External VSYNC enable. This bits select between external and internal VSYNC.
|
|
*
|
|
* Values:
|
|
* - 0 - Internal VSYNC mode.
|
|
* - 1 - External VSYNC mode.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC (15) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC.
|
|
#define BM_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC (0x00008000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC.
|
|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC) >> BP_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC) & BM_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_EXT_VSYNC field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC) | BF_IPU_CSI1_SENS_CONF_CSI1_EXT_VSYNC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_DIV_RATIO[23:16] (RW)
|
|
*
|
|
* DIV Ratio Clock division ratio minus 1. This field defines the division ratio of HSP_CLK into
|
|
* SENSB_MCLK: SENSB_MCLK rate = HSP_CLK rate /(DIV_RATIO+1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO (16) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO.
|
|
#define BM_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO (0x00ff0000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO.
|
|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO) >> BP_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO) & BM_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_DIV_RATIO field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO) | BF_IPU_CSI1_SENS_CONF_CSI1_DIV_RATIO(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_DATA_DEST[26:24] (RW)
|
|
*
|
|
* These bits enable the destination of the data coming from the CSI. CSI1_DATA_DEST[0] - Reserved
|
|
* CSI1_DATA_DEST[1] - destination is IC CSI1_DATA_DEST[2] - destination is IDMAC via SMFC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST (24) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_DATA_DEST.
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#define BM_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST (0x07000000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_DATA_DEST.
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//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_DATA_DEST from a register value.
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|
#define BG_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST) >> BP_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST)
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_DATA_DEST.
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|
#define BF_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST) & BM_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_DATA_DEST field to a new value.
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|
#define BW_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST) | BF_IPU_CSI1_SENS_CONF_CSI1_DATA_DEST(v)))
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#endif
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|
//@}
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_JPEG8_EN[27] (RW)
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|
*
|
|
* JPEG8 enable bit
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|
*
|
|
* Values:
|
|
* - 0 - JPEG8 is disabled
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|
* - 1 - JPEG8 detection is enabled
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|
*/
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|
//@{
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|
#define BP_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN (27) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN.
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#define BM_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN (0x08000000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN.
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//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN from a register value.
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|
#define BG_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN) >> BP_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN)
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN) & BM_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_JPEG8_EN field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN) | BF_IPU_CSI1_SENS_CONF_CSI1_JPEG8_EN(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_JPEG_MODE[28] (RW)
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|
*
|
|
* JPEG Mode - this bit defines the mode of the control signals when working in JPEG mode
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|
*
|
|
* Values:
|
|
* - 0 - The frame starts withe the assertion of VSYNC. The frame ends on the next VSYNC or by setting the
|
|
* CSI0_FORCE_EOF bit
|
|
* - 1 - The data is valid as long as HSYNC and VSYNC signals are active; HSYNC is valid for single frame
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE (28) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE.
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|
#define BM_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE (0x10000000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE.
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|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE) >> BP_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE)
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|
|
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//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE) & BM_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_JPEG_MODE field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE) | BF_IPU_CSI1_SENS_CONF_CSI1_JPEG_MODE(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI1_FORCE_EOF[29] (RW)
|
|
*
|
|
* Force End of frame This is a self clear bit allowing the user to force an End-of-frame event;
|
|
* This bit can be used in cases where the frame sent by the sensor was not completed.
|
|
*
|
|
* Values:
|
|
* - 0 - no action
|
|
* - 1 - force end of frame
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF (29) //!< Bit position for IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF.
|
|
#define BM_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF (0x20000000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF.
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|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF) >> BP_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF) & BM_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_FORCE_EOF field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF) | BF_IPU_CSI1_SENS_CONF_CSI1_FORCE_EOF(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_CONF, field CSI0_DATA_EN_POL[31] (RW)
|
|
*
|
|
* Invert IPP_IND_SENSB_DATA_EN input. This bit selects the polarity of IPP_IND_SENSB_DATA_EN
|
|
* signal.
|
|
*
|
|
* Values:
|
|
* - 0 - IPP_IND_SENSB_DATA_EN is directly applied to internal circuitry.
|
|
* - 1 - IPP_IND_SENSB_DATA_EN is inverted before applied to internal circuitry.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL (31) //!< Bit position for IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL.
|
|
#define BM_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL (0x80000000) //!< Bit mask for IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL.
|
|
|
|
//! @brief Get value of IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL from a register value.
|
|
#define BG_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL) >> BP_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL.
|
|
#define BF_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL) & BM_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_DATA_EN_POL field to a new value.
|
|
#define BW_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL(x, v) (HW_IPU_CSI1_SENS_CONF_WR(x, (HW_IPU_CSI1_SENS_CONF_RD(x) & ~BM_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL) | BF_IPU_CSI1_SENS_CONF_CSI0_DATA_EN_POL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_SENS_FRM_SIZE - CSI1 Sense Frame Size Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_SENS_FRM_SIZE - CSI1 Sense Frame Size Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_sens_frm_size
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_sens_frm_size_bitfields
|
|
{
|
|
unsigned CSI1_SENS_FRM_WIDTH : 13; //!< [12:0] Sensor frame width minus 1.
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved, should be cleared.
|
|
unsigned CSI1_SENS_FRM_HEIGHT : 12; //!< [27:16] Sensor frame height minus 1.
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi1_sens_frm_size_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_SENS_FRM_SIZE register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE_ADDR(x) (REGS_IPU_BASE(x) + 0x38004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE(x) (*(volatile hw_ipu_csi1_sens_frm_size_t *) HW_IPU_CSI1_SENS_FRM_SIZE_ADDR(x))
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE_RD(x) (HW_IPU_CSI1_SENS_FRM_SIZE(x).U)
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE_WR(x, v) (HW_IPU_CSI1_SENS_FRM_SIZE(x).U = (v))
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE_SET(x, v) (HW_IPU_CSI1_SENS_FRM_SIZE_WR(x, HW_IPU_CSI1_SENS_FRM_SIZE_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE_CLR(x, v) (HW_IPU_CSI1_SENS_FRM_SIZE_WR(x, HW_IPU_CSI1_SENS_FRM_SIZE_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_SENS_FRM_SIZE_TOG(x, v) (HW_IPU_CSI1_SENS_FRM_SIZE_WR(x, HW_IPU_CSI1_SENS_FRM_SIZE_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_SENS_FRM_SIZE bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_SENS_FRM_SIZE, field CSI1_SENS_FRM_WIDTH[12:0] (RW)
|
|
*
|
|
* Sensor frame width minus 1. This field defines the sensor frame column number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH (0) //!< Bit position for IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH.
|
|
#define BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH (0x00001fff) //!< Bit mask for IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH.
|
|
|
|
//! @brief Get value of IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH from a register value.
|
|
#define BG_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH) >> BP_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH.
|
|
#define BF_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH) & BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SENS_FRM_WIDTH field to a new value.
|
|
#define BW_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH(x, v) (HW_IPU_CSI1_SENS_FRM_SIZE_WR(x, (HW_IPU_CSI1_SENS_FRM_SIZE_RD(x) & ~BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH) | BF_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SENS_FRM_SIZE, field CSI1_SENS_FRM_HEIGHT[27:16] (RW)
|
|
*
|
|
* Sensor frame height minus 1. This field defines the sensor frame rows number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT (16) //!< Bit position for IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT.
|
|
#define BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT (0x0fff0000) //!< Bit mask for IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT from a register value.
|
|
#define BG_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT) >> BP_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT.
|
|
#define BF_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT) & BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SENS_FRM_HEIGHT field to a new value.
|
|
#define BW_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT(x, v) (HW_IPU_CSI1_SENS_FRM_SIZE_WR(x, (HW_IPU_CSI1_SENS_FRM_SIZE_RD(x) & ~BM_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT) | BF_IPU_CSI1_SENS_FRM_SIZE_CSI1_SENS_FRM_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_ACT_FRM_SIZE - CSI1 Actual Frame Size Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_ACT_FRM_SIZE - CSI1 Actual Frame Size Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_act_frm_size
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_act_frm_size_bitfields
|
|
{
|
|
unsigned CSI1_ACT_FRM_WIDTH : 13; //!< [12:0] Actual frame width minus 1.
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved, should be cleared.
|
|
unsigned CSI1_ACT_FRM_HEIGHT : 12; //!< [27:16] Actual frame height minus 1.
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi1_act_frm_size_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_ACT_FRM_SIZE register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE_ADDR(x) (REGS_IPU_BASE(x) + 0x38008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE(x) (*(volatile hw_ipu_csi1_act_frm_size_t *) HW_IPU_CSI1_ACT_FRM_SIZE_ADDR(x))
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE_RD(x) (HW_IPU_CSI1_ACT_FRM_SIZE(x).U)
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE_WR(x, v) (HW_IPU_CSI1_ACT_FRM_SIZE(x).U = (v))
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE_SET(x, v) (HW_IPU_CSI1_ACT_FRM_SIZE_WR(x, HW_IPU_CSI1_ACT_FRM_SIZE_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE_CLR(x, v) (HW_IPU_CSI1_ACT_FRM_SIZE_WR(x, HW_IPU_CSI1_ACT_FRM_SIZE_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_ACT_FRM_SIZE_TOG(x, v) (HW_IPU_CSI1_ACT_FRM_SIZE_WR(x, HW_IPU_CSI1_ACT_FRM_SIZE_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_ACT_FRM_SIZE bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_ACT_FRM_SIZE, field CSI1_ACT_FRM_WIDTH[12:0] (RW)
|
|
*
|
|
* Actual frame width minus 1. This field defines the CSI output frame columns number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH (0) //!< Bit position for IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH.
|
|
#define BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH (0x00001fff) //!< Bit mask for IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH.
|
|
|
|
//! @brief Get value of IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH from a register value.
|
|
#define BG_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH) >> BP_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH.
|
|
#define BF_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH) & BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_ACT_FRM_WIDTH field to a new value.
|
|
#define BW_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH(x, v) (HW_IPU_CSI1_ACT_FRM_SIZE_WR(x, (HW_IPU_CSI1_ACT_FRM_SIZE_RD(x) & ~BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH) | BF_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_WIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_ACT_FRM_SIZE, field CSI1_ACT_FRM_HEIGHT[27:16] (RW)
|
|
*
|
|
* Actual frame height minus 1. This field defines the CSI output frame rows number minus 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT (16) //!< Bit position for IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT.
|
|
#define BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT (0x0fff0000) //!< Bit mask for IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT from a register value.
|
|
#define BG_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT) >> BP_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT.
|
|
#define BF_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT) & BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_ACT_FRM_HEIGHT field to a new value.
|
|
#define BW_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT(x, v) (HW_IPU_CSI1_ACT_FRM_SIZE_WR(x, (HW_IPU_CSI1_ACT_FRM_SIZE_RD(x) & ~BM_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT) | BF_IPU_CSI1_ACT_FRM_SIZE_CSI1_ACT_FRM_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_OUT_FRM_CTRL - CSI1 Output Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_OUT_FRM_CTRL - CSI1 Output Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_out_frm_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_out_frm_ctrl_bitfields
|
|
{
|
|
unsigned CSI1_VSC : 12; //!< [11:0] Vertical skip.
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved, should be cleared.
|
|
unsigned CSI1_HSC : 13; //!< [28:16] Horizontal skip.
|
|
unsigned RESERVED1 : 1; //!< [29] Reserved
|
|
unsigned CSI1_VERT_DWNS : 1; //!< [30] Enable vertical downsizing (decimation) by 2.
|
|
unsigned CSI1_HORZ_DWNS : 1; //!< [31] Enable horizontal downsizing (decimation) by 2.
|
|
} B;
|
|
} hw_ipu_csi1_out_frm_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_OUT_FRM_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x3800c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL(x) (*(volatile hw_ipu_csi1_out_frm_ctrl_t *) HW_IPU_CSI1_OUT_FRM_CTRL_ADDR(x))
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) (HW_IPU_CSI1_OUT_FRM_CTRL(x).U)
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL(x).U = (v))
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL_SET(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL_CLR(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_OUT_FRM_CTRL_TOG(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_OUT_FRM_CTRL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_OUT_FRM_CTRL, field CSI1_VSC[11:0] (RW)
|
|
*
|
|
* Vertical skip. This field defines the number of rows to skip.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC (0) //!< Bit position for IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC.
|
|
#define BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC (0x00000fff) //!< Bit mask for IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC.
|
|
|
|
//! @brief Get value of IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC from a register value.
|
|
#define BG_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC) >> BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC.
|
|
#define BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_VSC field to a new value.
|
|
#define BW_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC) | BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_VSC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_OUT_FRM_CTRL, field CSI1_HSC[28:16] (RW)
|
|
*
|
|
* Horizontal skip. This field defines the number of columns to skip. In Interlaced mode this number
|
|
* refers to the number of lines per field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC (16) //!< Bit position for IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC.
|
|
#define BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC (0x1fff0000) //!< Bit mask for IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC.
|
|
|
|
//! @brief Get value of IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC from a register value.
|
|
#define BG_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC) >> BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC.
|
|
#define BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_HSC field to a new value.
|
|
#define BW_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC) | BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_HSC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_OUT_FRM_CTRL, field CSI1_VERT_DWNS[30] (RW)
|
|
*
|
|
* Enable vertical downsizing (decimation) by 2.
|
|
*
|
|
* Values:
|
|
* - 0 - Downsizing disabled
|
|
* - 1 - Downsizing enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS (30) //!< Bit position for IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS.
|
|
#define BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS (0x40000000) //!< Bit mask for IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS.
|
|
|
|
//! @brief Get value of IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS from a register value.
|
|
#define BG_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS) >> BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS.
|
|
#define BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_VERT_DWNS field to a new value.
|
|
#define BW_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS) | BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_VERT_DWNS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_OUT_FRM_CTRL, field CSI1_HORZ_DWNS[31] (RW)
|
|
*
|
|
* Enable horizontal downsizing (decimation) by 2.
|
|
*
|
|
* Values:
|
|
* - 0 - Downsizing disabled 1 Downsizing enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS (31) //!< Bit position for IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS.
|
|
#define BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS (0x80000000) //!< Bit mask for IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS.
|
|
|
|
//! @brief Get value of IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS from a register value.
|
|
#define BG_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS) >> BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS.
|
|
#define BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS) & BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_HORZ_DWNS field to a new value.
|
|
#define BW_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS(x, v) (HW_IPU_CSI1_OUT_FRM_CTRL_WR(x, (HW_IPU_CSI1_OUT_FRM_CTRL_RD(x) & ~BM_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS) | BF_IPU_CSI1_OUT_FRM_CTRL_CSI1_HORZ_DWNS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_TST_CTRL - CSI1 Test Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_TST_CTRL - CSI1 Test Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_tst_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_tst_ctrl_bitfields
|
|
{
|
|
unsigned PG_R_VALUE : 8; //!< [7:0] Pattern generator R value.
|
|
unsigned PG_G_VALUE : 8; //!< [15:8] Pattern generator G value.
|
|
unsigned PG_B_VALUE : 8; //!< [23:16] Pattern generator B value.
|
|
unsigned TEST_GEN_MODE : 1; //!< [24] Test generator mode.
|
|
unsigned RESERVED0 : 7; //!< [31:25] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi1_tst_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_TST_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_TST_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x38010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_TST_CTRL(x) (*(volatile hw_ipu_csi1_tst_ctrl_t *) HW_IPU_CSI1_TST_CTRL_ADDR(x))
|
|
#define HW_IPU_CSI1_TST_CTRL_RD(x) (HW_IPU_CSI1_TST_CTRL(x).U)
|
|
#define HW_IPU_CSI1_TST_CTRL_WR(x, v) (HW_IPU_CSI1_TST_CTRL(x).U = (v))
|
|
#define HW_IPU_CSI1_TST_CTRL_SET(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, HW_IPU_CSI1_TST_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_TST_CTRL_CLR(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, HW_IPU_CSI1_TST_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_TST_CTRL_TOG(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, HW_IPU_CSI1_TST_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_TST_CTRL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_TST_CTRL, field PG_R_VALUE[7:0] (RW)
|
|
*
|
|
* Pattern generator R value. This field selects the R value for the generated pattern of even
|
|
* pixel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_TST_CTRL_PG_R_VALUE (0) //!< Bit position for IPU_CSI1_TST_CTRL_PG_R_VALUE.
|
|
#define BM_IPU_CSI1_TST_CTRL_PG_R_VALUE (0x000000ff) //!< Bit mask for IPU_CSI1_TST_CTRL_PG_R_VALUE.
|
|
|
|
//! @brief Get value of IPU_CSI1_TST_CTRL_PG_R_VALUE from a register value.
|
|
#define BG_IPU_CSI1_TST_CTRL_PG_R_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_TST_CTRL_PG_R_VALUE) >> BP_IPU_CSI1_TST_CTRL_PG_R_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_TST_CTRL_PG_R_VALUE.
|
|
#define BF_IPU_CSI1_TST_CTRL_PG_R_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_TST_CTRL_PG_R_VALUE) & BM_IPU_CSI1_TST_CTRL_PG_R_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PG_R_VALUE field to a new value.
|
|
#define BW_IPU_CSI1_TST_CTRL_PG_R_VALUE(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, (HW_IPU_CSI1_TST_CTRL_RD(x) & ~BM_IPU_CSI1_TST_CTRL_PG_R_VALUE) | BF_IPU_CSI1_TST_CTRL_PG_R_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_TST_CTRL, field PG_G_VALUE[15:8] (RW)
|
|
*
|
|
* Pattern generator G value. This field selects the G value for the generated pattern of even
|
|
* pixel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_TST_CTRL_PG_G_VALUE (8) //!< Bit position for IPU_CSI1_TST_CTRL_PG_G_VALUE.
|
|
#define BM_IPU_CSI1_TST_CTRL_PG_G_VALUE (0x0000ff00) //!< Bit mask for IPU_CSI1_TST_CTRL_PG_G_VALUE.
|
|
|
|
//! @brief Get value of IPU_CSI1_TST_CTRL_PG_G_VALUE from a register value.
|
|
#define BG_IPU_CSI1_TST_CTRL_PG_G_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_TST_CTRL_PG_G_VALUE) >> BP_IPU_CSI1_TST_CTRL_PG_G_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_TST_CTRL_PG_G_VALUE.
|
|
#define BF_IPU_CSI1_TST_CTRL_PG_G_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_TST_CTRL_PG_G_VALUE) & BM_IPU_CSI1_TST_CTRL_PG_G_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PG_G_VALUE field to a new value.
|
|
#define BW_IPU_CSI1_TST_CTRL_PG_G_VALUE(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, (HW_IPU_CSI1_TST_CTRL_RD(x) & ~BM_IPU_CSI1_TST_CTRL_PG_G_VALUE) | BF_IPU_CSI1_TST_CTRL_PG_G_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_TST_CTRL, field PG_B_VALUE[23:16] (RW)
|
|
*
|
|
* Pattern generator B value. This field selects the B value for the generated pattern of even
|
|
* pixel.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_TST_CTRL_PG_B_VALUE (16) //!< Bit position for IPU_CSI1_TST_CTRL_PG_B_VALUE.
|
|
#define BM_IPU_CSI1_TST_CTRL_PG_B_VALUE (0x00ff0000) //!< Bit mask for IPU_CSI1_TST_CTRL_PG_B_VALUE.
|
|
|
|
//! @brief Get value of IPU_CSI1_TST_CTRL_PG_B_VALUE from a register value.
|
|
#define BG_IPU_CSI1_TST_CTRL_PG_B_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_TST_CTRL_PG_B_VALUE) >> BP_IPU_CSI1_TST_CTRL_PG_B_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_TST_CTRL_PG_B_VALUE.
|
|
#define BF_IPU_CSI1_TST_CTRL_PG_B_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_TST_CTRL_PG_B_VALUE) & BM_IPU_CSI1_TST_CTRL_PG_B_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PG_B_VALUE field to a new value.
|
|
#define BW_IPU_CSI1_TST_CTRL_PG_B_VALUE(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, (HW_IPU_CSI1_TST_CTRL_RD(x) & ~BM_IPU_CSI1_TST_CTRL_PG_B_VALUE) | BF_IPU_CSI1_TST_CTRL_PG_B_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_TST_CTRL, field TEST_GEN_MODE[24] (RW)
|
|
*
|
|
* Test generator mode. This bit activates the signal generation.
|
|
*
|
|
* Values:
|
|
* - 0 - Test signal generator is inactive.
|
|
* - 1 - Test signal generator is active.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_TST_CTRL_TEST_GEN_MODE (24) //!< Bit position for IPU_CSI1_TST_CTRL_TEST_GEN_MODE.
|
|
#define BM_IPU_CSI1_TST_CTRL_TEST_GEN_MODE (0x01000000) //!< Bit mask for IPU_CSI1_TST_CTRL_TEST_GEN_MODE.
|
|
|
|
//! @brief Get value of IPU_CSI1_TST_CTRL_TEST_GEN_MODE from a register value.
|
|
#define BG_IPU_CSI1_TST_CTRL_TEST_GEN_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_TST_CTRL_TEST_GEN_MODE) >> BP_IPU_CSI1_TST_CTRL_TEST_GEN_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_TST_CTRL_TEST_GEN_MODE.
|
|
#define BF_IPU_CSI1_TST_CTRL_TEST_GEN_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_TST_CTRL_TEST_GEN_MODE) & BM_IPU_CSI1_TST_CTRL_TEST_GEN_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the TEST_GEN_MODE field to a new value.
|
|
#define BW_IPU_CSI1_TST_CTRL_TEST_GEN_MODE(x, v) (HW_IPU_CSI1_TST_CTRL_WR(x, (HW_IPU_CSI1_TST_CTRL_RD(x) & ~BM_IPU_CSI1_TST_CTRL_TEST_GEN_MODE) | BF_IPU_CSI1_TST_CTRL_TEST_GEN_MODE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CCIR_CODE_1 - CSI1 CCIR Code Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CCIR_CODE_1 - CSI1 CCIR Code Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_ccir_code_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_ccir_code_1_bitfields
|
|
{
|
|
unsigned CSI1_END_FLD0_BLNK_1ST : 3; //!< [2:0] End of field 0 first blanking line command (interlaces mode).
|
|
unsigned CSI1_STRT_FLD0_BLNK_1ST : 3; //!< [5:3] Start of field 0 first blanking line command (interlaces mode).
|
|
unsigned CSI1_END_FLD0_BLNK_2ND : 3; //!< [8:6] End of field 0 second blanking line command (interlaces mode).
|
|
unsigned CSI1_STRT_FLD0_BLNK_2ND : 3; //!< [11:9] Start of field 0 second blanking line command (interlaces mode).
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved, should be cleared.
|
|
unsigned CSI1_END_FLD0_ACTV : 3; //!< [18:16] End of field 0 active line command (interlaces mode).
|
|
unsigned CSI1_STRT_FLD0_ACTV : 3; //!< [21:19] Start of field 0 active line command (interlaces mode).
|
|
unsigned RESERVED1 : 2; //!< [23:22] Reserved, should be cleared.
|
|
unsigned CSI1_CCIR_ERR_DET_EN : 1; //!< [24] Enable error detection and correction for CCIR interlaced mode with protection bit.
|
|
unsigned RESERVED2 : 7; //!< [31:25] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi1_ccir_code_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CCIR_CODE_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CCIR_CODE_1_ADDR(x) (REGS_IPU_BASE(x) + 0x38014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CCIR_CODE_1(x) (*(volatile hw_ipu_csi1_ccir_code_1_t *) HW_IPU_CSI1_CCIR_CODE_1_ADDR(x))
|
|
#define HW_IPU_CSI1_CCIR_CODE_1_RD(x) (HW_IPU_CSI1_CCIR_CODE_1(x).U)
|
|
#define HW_IPU_CSI1_CCIR_CODE_1_WR(x, v) (HW_IPU_CSI1_CCIR_CODE_1(x).U = (v))
|
|
#define HW_IPU_CSI1_CCIR_CODE_1_SET(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, HW_IPU_CSI1_CCIR_CODE_1_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CCIR_CODE_1_CLR(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CCIR_CODE_1_TOG(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, HW_IPU_CSI1_CCIR_CODE_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CCIR_CODE_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_END_FLD0_BLNK_1ST[2:0] (RW)
|
|
*
|
|
* End of field 0 first blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST (0) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST (0x00000007) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_END_FLD0_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_STRT_FLD0_BLNK_1ST[5:3] (RW)
|
|
*
|
|
* Start of field 0 first blanking line command (interlaces mode). (In progressive mode this field
|
|
* indicates start of blanking line command).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST (3) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST (0x00000038) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_STRT_FLD0_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_END_FLD0_BLNK_2ND[8:6] (RW)
|
|
*
|
|
* End of field 0 second blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND (6) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND (0x000001c0) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_END_FLD0_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_STRT_FLD0_BLNK_2ND[11:9] (RW)
|
|
*
|
|
* Start of field 0 second blanking line command (interlaces mode). (In progressive mode this field
|
|
* is ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND (9) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND (0x00000e00) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_STRT_FLD0_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_END_FLD0_ACTV[18:16] (RW)
|
|
*
|
|
* End of field 0 active line command (interlaces mode). (In progressive mode, end of active line
|
|
* command mode).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV (16) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV (0x00070000) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_END_FLD0_ACTV field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_END_FLD0_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_STRT_FLD0_ACTV[21:19] (RW)
|
|
*
|
|
* Start of field 0 active line command (interlaces mode). (In progressive mode, start of active
|
|
* line command mode).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV (19) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV (0x00380000) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_STRT_FLD0_ACTV field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_STRT_FLD0_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_1, field CSI1_CCIR_ERR_DET_EN[24] (RW)
|
|
*
|
|
* Enable error detection and correction for CCIR interlaced mode with protection bit.
|
|
*
|
|
* Values:
|
|
* - 0 - Error detection and correction is disabled.
|
|
* - 1 - Error detection and correction is enabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN (24) //!< Bit position for IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN.
|
|
#define BM_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN (0x01000000) //!< Bit mask for IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN) >> BP_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN.
|
|
#define BF_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN) & BM_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CCIR_ERR_DET_EN field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN(x, v) (HW_IPU_CSI1_CCIR_CODE_1_WR(x, (HW_IPU_CSI1_CCIR_CODE_1_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN) | BF_IPU_CSI1_CCIR_CODE_1_CSI1_CCIR_ERR_DET_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CCIR_CODE_2 - CSI1 CCIR Code Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CCIR_CODE_2 - CSI1 CCIR Code Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_ccir_code_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_ccir_code_2_bitfields
|
|
{
|
|
unsigned CSI1_END_FLD1_BLNK_1ST : 3; //!< [2:0] End of field 1 first blanking line command (interlaces mode).
|
|
unsigned CSI1_STRT_FLD1_BLNK_1ST : 3; //!< [5:3] Start of field 1 first blanking line command (interlaces mode).
|
|
unsigned CSI1_END_FLD1_BLNK_2ND : 3; //!< [8:6] End of field 1 second blanking line command (interlaces mode).
|
|
unsigned CSI1_STRT_FLD1_BLNK_2ND : 3; //!< [11:9] Start of field 1 second blanking line command (interlaces mode).
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved, should be cleared.
|
|
unsigned CSI1_END_FLD1_ACTV : 3; //!< [18:16] End of field 1 active line command (interlaces mode).
|
|
unsigned CSI1_STRT_FLD1_ACTV : 3; //!< [21:19] Start of field 1 active line command (interlaces mode).
|
|
unsigned RESERVED1 : 10; //!< [31:22] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi1_ccir_code_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CCIR_CODE_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CCIR_CODE_2_ADDR(x) (REGS_IPU_BASE(x) + 0x38018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CCIR_CODE_2(x) (*(volatile hw_ipu_csi1_ccir_code_2_t *) HW_IPU_CSI1_CCIR_CODE_2_ADDR(x))
|
|
#define HW_IPU_CSI1_CCIR_CODE_2_RD(x) (HW_IPU_CSI1_CCIR_CODE_2(x).U)
|
|
#define HW_IPU_CSI1_CCIR_CODE_2_WR(x, v) (HW_IPU_CSI1_CCIR_CODE_2(x).U = (v))
|
|
#define HW_IPU_CSI1_CCIR_CODE_2_SET(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, HW_IPU_CSI1_CCIR_CODE_2_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CCIR_CODE_2_CLR(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CCIR_CODE_2_TOG(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, HW_IPU_CSI1_CCIR_CODE_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CCIR_CODE_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_2, field CSI1_END_FLD1_BLNK_1ST[2:0] (RW)
|
|
*
|
|
* End of field 1 first blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST (0) //!< Bit position for IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST.
|
|
#define BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST (0x00000007) //!< Bit mask for IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST) >> BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST.
|
|
#define BF_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_END_FLD1_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, (HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST) | BF_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_2, field CSI1_STRT_FLD1_BLNK_1ST[5:3] (RW)
|
|
*
|
|
* Start of field 1 first blanking line command (interlaces mode). (In progressive mode this field
|
|
* is ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST (3) //!< Bit position for IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST.
|
|
#define BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST (0x00000038) //!< Bit mask for IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST) >> BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST.
|
|
#define BF_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_STRT_FLD1_BLNK_1ST field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, (HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST) | BF_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_1ST(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_2, field CSI1_END_FLD1_BLNK_2ND[8:6] (RW)
|
|
*
|
|
* End of field 1 second blanking line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND (6) //!< Bit position for IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND.
|
|
#define BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND (0x000001c0) //!< Bit mask for IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND) >> BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND.
|
|
#define BF_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_END_FLD1_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, (HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND) | BF_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_2, field CSI1_STRT_FLD1_BLNK_2ND[11:9] (RW)
|
|
*
|
|
* Start of field 1 second blanking line command (interlaces mode). (In progressive mode this field
|
|
* is ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND (9) //!< Bit position for IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND.
|
|
#define BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND (0x00000e00) //!< Bit mask for IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND) >> BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND.
|
|
#define BF_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_STRT_FLD1_BLNK_2ND field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, (HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND) | BF_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_BLNK_2ND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_2, field CSI1_END_FLD1_ACTV[18:16] (RW)
|
|
*
|
|
* End of field 1 active line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV (16) //!< Bit position for IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV.
|
|
#define BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV (0x00070000) //!< Bit mask for IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV) >> BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV.
|
|
#define BF_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_END_FLD1_ACTV field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, (HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV) | BF_IPU_CSI1_CCIR_CODE_2_CSI1_END_FLD1_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_2, field CSI1_STRT_FLD1_ACTV[21:19] (RW)
|
|
*
|
|
* Start of field 1 active line command (interlaces mode). (In progressive mode this field is
|
|
* ignored).
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV (19) //!< Bit position for IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV.
|
|
#define BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV (0x00380000) //!< Bit mask for IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV) >> BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV.
|
|
#define BF_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV) & BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_STRT_FLD1_ACTV field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV(x, v) (HW_IPU_CSI1_CCIR_CODE_2_WR(x, (HW_IPU_CSI1_CCIR_CODE_2_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV) | BF_IPU_CSI1_CCIR_CODE_2_CSI1_STRT_FLD1_ACTV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CCIR_CODE_3 - CSI1 CCIR Code Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CCIR_CODE_3 - CSI1 CCIR Code Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_ccir_code_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_ccir_code_3_bitfields
|
|
{
|
|
unsigned CSI1_CCIR_PRECOM : 30; //!< [29:0] CCIR pre command.
|
|
unsigned RESERVED0 : 2; //!< [31:30] Reserved, should be cleared.
|
|
} B;
|
|
} hw_ipu_csi1_ccir_code_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CCIR_CODE_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CCIR_CODE_3_ADDR(x) (REGS_IPU_BASE(x) + 0x3801c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CCIR_CODE_3(x) (*(volatile hw_ipu_csi1_ccir_code_3_t *) HW_IPU_CSI1_CCIR_CODE_3_ADDR(x))
|
|
#define HW_IPU_CSI1_CCIR_CODE_3_RD(x) (HW_IPU_CSI1_CCIR_CODE_3(x).U)
|
|
#define HW_IPU_CSI1_CCIR_CODE_3_WR(x, v) (HW_IPU_CSI1_CCIR_CODE_3(x).U = (v))
|
|
#define HW_IPU_CSI1_CCIR_CODE_3_SET(x, v) (HW_IPU_CSI1_CCIR_CODE_3_WR(x, HW_IPU_CSI1_CCIR_CODE_3_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CCIR_CODE_3_CLR(x, v) (HW_IPU_CSI1_CCIR_CODE_3_WR(x, HW_IPU_CSI1_CCIR_CODE_3_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CCIR_CODE_3_TOG(x, v) (HW_IPU_CSI1_CCIR_CODE_3_WR(x, HW_IPU_CSI1_CCIR_CODE_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CCIR_CODE_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CCIR_CODE_3, field CSI1_CCIR_PRECOM[29:0] (RW)
|
|
*
|
|
* CCIR pre command. This field defines the sequence which comes before the CCIR command. For BT.656
|
|
* the code should be written to bits [23:0] while bits [29:24] are ignored (3X8bit) For BT.1120 the
|
|
* code should be written to bits [29:0] (3X10bit)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM (0) //!< Bit position for IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM.
|
|
#define BM_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM (0x3fffffff) //!< Bit mask for IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM.
|
|
|
|
//! @brief Get value of IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM from a register value.
|
|
#define BG_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM) >> BP_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM.
|
|
#define BF_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM) & BM_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CCIR_PRECOM field to a new value.
|
|
#define BW_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM(x, v) (HW_IPU_CSI1_CCIR_CODE_3_WR(x, (HW_IPU_CSI1_CCIR_CODE_3_RD(x) & ~BM_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM) | BF_IPU_CSI1_CCIR_CODE_3_CSI1_CCIR_PRECOM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_DI - CSI1 Data Identifier Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_DI - CSI1 Data Identifier Register (RW)
|
|
*
|
|
* Reset value: 0xffffffff
|
|
*/
|
|
typedef union _hw_ipu_csi1_di
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_di_bitfields
|
|
{
|
|
unsigned CSI1_MIPI_DI0 : 8; //!< [7:0] CSI1_MIPI_DI0
|
|
unsigned CSI0_MIPI_DI1 : 8; //!< [15:8] CSI1_MIPI_DI1
|
|
unsigned CSI1_MIPI_DI2 : 8; //!< [23:16] CSI1_MIPI_DI2
|
|
unsigned CSI1_MIPI_DI3 : 8; //!< [31:24] CSI1_MIPI_DI3
|
|
} B;
|
|
} hw_ipu_csi1_di_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_DI register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_DI_ADDR(x) (REGS_IPU_BASE(x) + 0x38020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_DI(x) (*(volatile hw_ipu_csi1_di_t *) HW_IPU_CSI1_DI_ADDR(x))
|
|
#define HW_IPU_CSI1_DI_RD(x) (HW_IPU_CSI1_DI(x).U)
|
|
#define HW_IPU_CSI1_DI_WR(x, v) (HW_IPU_CSI1_DI(x).U = (v))
|
|
#define HW_IPU_CSI1_DI_SET(x, v) (HW_IPU_CSI1_DI_WR(x, HW_IPU_CSI1_DI_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_DI_CLR(x, v) (HW_IPU_CSI1_DI_WR(x, HW_IPU_CSI1_DI_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_DI_TOG(x, v) (HW_IPU_CSI1_DI_WR(x, HW_IPU_CSI1_DI_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_DI bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_DI, field CSI1_MIPI_DI0[7:0] (RW)
|
|
*
|
|
* CSI1_MIPI_DI0 This field holds the Data Identifier #0 handled by the CSI; This is the main
|
|
* stream.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_DI_CSI1_MIPI_DI0 (0) //!< Bit position for IPU_CSI1_DI_CSI1_MIPI_DI0.
|
|
#define BM_IPU_CSI1_DI_CSI1_MIPI_DI0 (0x000000ff) //!< Bit mask for IPU_CSI1_DI_CSI1_MIPI_DI0.
|
|
|
|
//! @brief Get value of IPU_CSI1_DI_CSI1_MIPI_DI0 from a register value.
|
|
#define BG_IPU_CSI1_DI_CSI1_MIPI_DI0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_DI_CSI1_MIPI_DI0) >> BP_IPU_CSI1_DI_CSI1_MIPI_DI0)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_DI_CSI1_MIPI_DI0.
|
|
#define BF_IPU_CSI1_DI_CSI1_MIPI_DI0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_DI_CSI1_MIPI_DI0) & BM_IPU_CSI1_DI_CSI1_MIPI_DI0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_MIPI_DI0 field to a new value.
|
|
#define BW_IPU_CSI1_DI_CSI1_MIPI_DI0(x, v) (HW_IPU_CSI1_DI_WR(x, (HW_IPU_CSI1_DI_RD(x) & ~BM_IPU_CSI1_DI_CSI1_MIPI_DI0) | BF_IPU_CSI1_DI_CSI1_MIPI_DI0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_DI, field CSI0_MIPI_DI1[15:8] (RW)
|
|
*
|
|
* CSI1_MIPI_DI1 This field holds the Data Identifier #1 handled by the CSI
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_DI_CSI0_MIPI_DI1 (8) //!< Bit position for IPU_CSI1_DI_CSI0_MIPI_DI1.
|
|
#define BM_IPU_CSI1_DI_CSI0_MIPI_DI1 (0x0000ff00) //!< Bit mask for IPU_CSI1_DI_CSI0_MIPI_DI1.
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|
|
|
//! @brief Get value of IPU_CSI1_DI_CSI0_MIPI_DI1 from a register value.
|
|
#define BG_IPU_CSI1_DI_CSI0_MIPI_DI1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_DI_CSI0_MIPI_DI1) >> BP_IPU_CSI1_DI_CSI0_MIPI_DI1)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_DI_CSI0_MIPI_DI1.
|
|
#define BF_IPU_CSI1_DI_CSI0_MIPI_DI1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_DI_CSI0_MIPI_DI1) & BM_IPU_CSI1_DI_CSI0_MIPI_DI1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI0_MIPI_DI1 field to a new value.
|
|
#define BW_IPU_CSI1_DI_CSI0_MIPI_DI1(x, v) (HW_IPU_CSI1_DI_WR(x, (HW_IPU_CSI1_DI_RD(x) & ~BM_IPU_CSI1_DI_CSI0_MIPI_DI1) | BF_IPU_CSI1_DI_CSI0_MIPI_DI1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_DI, field CSI1_MIPI_DI2[23:16] (RW)
|
|
*
|
|
* CSI1_MIPI_DI2 This field holds the Data Identifier #2 handled by the CSI.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_DI_CSI1_MIPI_DI2 (16) //!< Bit position for IPU_CSI1_DI_CSI1_MIPI_DI2.
|
|
#define BM_IPU_CSI1_DI_CSI1_MIPI_DI2 (0x00ff0000) //!< Bit mask for IPU_CSI1_DI_CSI1_MIPI_DI2.
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|
|
|
//! @brief Get value of IPU_CSI1_DI_CSI1_MIPI_DI2 from a register value.
|
|
#define BG_IPU_CSI1_DI_CSI1_MIPI_DI2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_DI_CSI1_MIPI_DI2) >> BP_IPU_CSI1_DI_CSI1_MIPI_DI2)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_DI_CSI1_MIPI_DI2.
|
|
#define BF_IPU_CSI1_DI_CSI1_MIPI_DI2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_DI_CSI1_MIPI_DI2) & BM_IPU_CSI1_DI_CSI1_MIPI_DI2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_MIPI_DI2 field to a new value.
|
|
#define BW_IPU_CSI1_DI_CSI1_MIPI_DI2(x, v) (HW_IPU_CSI1_DI_WR(x, (HW_IPU_CSI1_DI_RD(x) & ~BM_IPU_CSI1_DI_CSI1_MIPI_DI2) | BF_IPU_CSI1_DI_CSI1_MIPI_DI2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_DI, field CSI1_MIPI_DI3[31:24] (RW)
|
|
*
|
|
* CSI1_MIPI_DI3 This field holds the Data Identifier #3 handled by the CSI.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_DI_CSI1_MIPI_DI3 (24) //!< Bit position for IPU_CSI1_DI_CSI1_MIPI_DI3.
|
|
#define BM_IPU_CSI1_DI_CSI1_MIPI_DI3 (0xff000000) //!< Bit mask for IPU_CSI1_DI_CSI1_MIPI_DI3.
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|
|
|
//! @brief Get value of IPU_CSI1_DI_CSI1_MIPI_DI3 from a register value.
|
|
#define BG_IPU_CSI1_DI_CSI1_MIPI_DI3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_DI_CSI1_MIPI_DI3) >> BP_IPU_CSI1_DI_CSI1_MIPI_DI3)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_DI_CSI1_MIPI_DI3.
|
|
#define BF_IPU_CSI1_DI_CSI1_MIPI_DI3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_DI_CSI1_MIPI_DI3) & BM_IPU_CSI1_DI_CSI1_MIPI_DI3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_MIPI_DI3 field to a new value.
|
|
#define BW_IPU_CSI1_DI_CSI1_MIPI_DI3(x, v) (HW_IPU_CSI1_DI_WR(x, (HW_IPU_CSI1_DI_RD(x) & ~BM_IPU_CSI1_DI_CSI1_MIPI_DI3) | BF_IPU_CSI1_DI_CSI1_MIPI_DI3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_SKIP - CSI1 SKIP Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_SKIP - CSI1 SKIP Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register control the frame skipping supported between CSI1 and the SMFC.
|
|
*/
|
|
typedef union _hw_ipu_csi1_skip
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_skip_bitfields
|
|
{
|
|
unsigned CSI1_MAX_RATIO_SKIP_SMFC : 3; //!< [2:0] CSI1 Maximum Ratio Skip for SMFC
|
|
unsigned CSI1_SKIP_SMFC : 5; //!< [7:3] CSI1 SKIP SMFC
|
|
unsigned CSI1_ID_2_SKIP : 2; //!< [9:8] CSI1 to SMFC Skipping ID.
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved
|
|
unsigned CSI1_MAX_RATIO_SKIP_ISP : 3; //!< [18:16]
|
|
unsigned CSI1_SKIP_ISP : 5; //!< [23:19] Reserved
|
|
unsigned RESERVED1 : 8; //!< [31:24] Reserved
|
|
} B;
|
|
} hw_ipu_csi1_skip_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_SKIP register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_SKIP_ADDR(x) (REGS_IPU_BASE(x) + 0x38024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_SKIP(x) (*(volatile hw_ipu_csi1_skip_t *) HW_IPU_CSI1_SKIP_ADDR(x))
|
|
#define HW_IPU_CSI1_SKIP_RD(x) (HW_IPU_CSI1_SKIP(x).U)
|
|
#define HW_IPU_CSI1_SKIP_WR(x, v) (HW_IPU_CSI1_SKIP(x).U = (v))
|
|
#define HW_IPU_CSI1_SKIP_SET(x, v) (HW_IPU_CSI1_SKIP_WR(x, HW_IPU_CSI1_SKIP_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_SKIP_CLR(x, v) (HW_IPU_CSI1_SKIP_WR(x, HW_IPU_CSI1_SKIP_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_SKIP_TOG(x, v) (HW_IPU_CSI1_SKIP_WR(x, HW_IPU_CSI1_SKIP_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_SKIP bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_SKIP, field CSI1_MAX_RATIO_SKIP_SMFC[2:0] (RW)
|
|
*
|
|
* CSI1 Maximum Ratio Skip for SMFC These bits define the number of frames in a skipping set. These
|
|
* bits define the number of frames in a skipping set. The skipping number is equal to
|
|
* CSI1_MAX_RATIO_SKIP_SMFC+1; The maximum value of this bits is 5. When set to 0 the skipping is
|
|
* disabled.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC (0) //!< Bit position for IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC.
|
|
#define BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC (0x00000007) //!< Bit mask for IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC.
|
|
|
|
//! @brief Get value of IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC from a register value.
|
|
#define BG_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC) >> BP_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC.
|
|
#define BF_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC) & BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_MAX_RATIO_SKIP_SMFC field to a new value.
|
|
#define BW_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC(x, v) (HW_IPU_CSI1_SKIP_WR(x, (HW_IPU_CSI1_SKIP_RD(x) & ~BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC) | BF_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_SMFC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SKIP, field CSI1_SKIP_SMFC[7:3] (RW)
|
|
*
|
|
* CSI1 SKIP SMFC These 5 bits define the skipping pattern of the frames send to the SMFC. Skipping
|
|
* is done for a set of frames. The number of frames in a set is defined at
|
|
* CSI1_MAX_RATIO_SKIP_SMFC. when CSI1_MAX_RATIO_SKIP_SMFC = 1 => CSI1_SKIP_SMFC[0] is used; other
|
|
* bits are ignored when CSI1_MAX_RATIO_SKIP_SMFC = 2 => CSI1_SKIP_SMFC[1:0] are used; other bits
|
|
* are ignored when CSI1_MAX_RATIO_SKIP_SMFC = 3 => CSI1_SKIP_SMFC[2:0] are used; other bits are
|
|
* ignored when CSI1_MAX_RATIO_SKIP_SMFC = 4 => CSI1_SKIP_SMFC[3:0] are used; other bits are ignored
|
|
* when CSI1_MAX_RATIO_SKIP_SMFC = 5 => CSI1_SKIP_SMFC[4:0] are used; Setting bit #n of
|
|
* CSI1_SKIP_SMFC means that the #n frame in the set is skipped. For example: if
|
|
* CSI1_MAX_RATIO_SKIP_SMFC = 4 and CSI1_SKIP_SMFC = 11010 Frames #0 & Frame #2 will not be skipped
|
|
* as bit0 and bit2 are cleared Frames #1 & Frame #3 will be skipped as bit1 and bit3 are set bit #4
|
|
* is ignored as CSI1_MAX_RATIO_SKIP_SMFC is set to 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SKIP_CSI1_SKIP_SMFC (3) //!< Bit position for IPU_CSI1_SKIP_CSI1_SKIP_SMFC.
|
|
#define BM_IPU_CSI1_SKIP_CSI1_SKIP_SMFC (0x000000f8) //!< Bit mask for IPU_CSI1_SKIP_CSI1_SKIP_SMFC.
|
|
|
|
//! @brief Get value of IPU_CSI1_SKIP_CSI1_SKIP_SMFC from a register value.
|
|
#define BG_IPU_CSI1_SKIP_CSI1_SKIP_SMFC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SKIP_CSI1_SKIP_SMFC) >> BP_IPU_CSI1_SKIP_CSI1_SKIP_SMFC)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SKIP_CSI1_SKIP_SMFC.
|
|
#define BF_IPU_CSI1_SKIP_CSI1_SKIP_SMFC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SKIP_CSI1_SKIP_SMFC) & BM_IPU_CSI1_SKIP_CSI1_SKIP_SMFC)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SKIP_SMFC field to a new value.
|
|
#define BW_IPU_CSI1_SKIP_CSI1_SKIP_SMFC(x, v) (HW_IPU_CSI1_SKIP_WR(x, (HW_IPU_CSI1_SKIP_RD(x) & ~BM_IPU_CSI1_SKIP_CSI1_SKIP_SMFC) | BF_IPU_CSI1_SKIP_CSI1_SKIP_SMFC(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SKIP, field CSI1_ID_2_SKIP[9:8] (RW)
|
|
*
|
|
* CSI1 to SMFC Skipping ID. Data from the CSI1 to the SMFC has an ID associated with it. The ID is
|
|
* received from the MIPI interface. The skipping mechanism between the CSI1 and the SMFC can be
|
|
* used for only one ID. There is no skipping for data coming with ID different from the ID
|
|
* programed in this bits
|
|
*
|
|
* Values:
|
|
* - 00 - - Skipping mechanism is activated on frames with ID equal to 00
|
|
* - 01 - - Skipping mechanism is activated on frames with ID equal to 01
|
|
* - 10 - - Skipping mechanism is activated on frames with ID equal to 10
|
|
* - 11 - - Skipping mechanism is activated on frames with ID equal to 11
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SKIP_CSI1_ID_2_SKIP (8) //!< Bit position for IPU_CSI1_SKIP_CSI1_ID_2_SKIP.
|
|
#define BM_IPU_CSI1_SKIP_CSI1_ID_2_SKIP (0x00000300) //!< Bit mask for IPU_CSI1_SKIP_CSI1_ID_2_SKIP.
|
|
|
|
//! @brief Get value of IPU_CSI1_SKIP_CSI1_ID_2_SKIP from a register value.
|
|
#define BG_IPU_CSI1_SKIP_CSI1_ID_2_SKIP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SKIP_CSI1_ID_2_SKIP) >> BP_IPU_CSI1_SKIP_CSI1_ID_2_SKIP)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SKIP_CSI1_ID_2_SKIP.
|
|
#define BF_IPU_CSI1_SKIP_CSI1_ID_2_SKIP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SKIP_CSI1_ID_2_SKIP) & BM_IPU_CSI1_SKIP_CSI1_ID_2_SKIP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_ID_2_SKIP field to a new value.
|
|
#define BW_IPU_CSI1_SKIP_CSI1_ID_2_SKIP(x, v) (HW_IPU_CSI1_SKIP_WR(x, (HW_IPU_CSI1_SKIP_RD(x) & ~BM_IPU_CSI1_SKIP_CSI1_ID_2_SKIP) | BF_IPU_CSI1_SKIP_CSI1_ID_2_SKIP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SKIP, field CSI1_MAX_RATIO_SKIP_ISP[18:16] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP (16) //!< Bit position for IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP.
|
|
#define BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP (0x00070000) //!< Bit mask for IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP.
|
|
|
|
//! @brief Get value of IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP from a register value.
|
|
#define BG_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP) >> BP_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP.
|
|
#define BF_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP) & BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_MAX_RATIO_SKIP_ISP field to a new value.
|
|
#define BW_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP(x, v) (HW_IPU_CSI1_SKIP_WR(x, (HW_IPU_CSI1_SKIP_RD(x) & ~BM_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP) | BF_IPU_CSI1_SKIP_CSI1_MAX_RATIO_SKIP_ISP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_SKIP, field CSI1_SKIP_ISP[23:19] (RW)
|
|
*
|
|
* Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_SKIP_CSI1_SKIP_ISP (19) //!< Bit position for IPU_CSI1_SKIP_CSI1_SKIP_ISP.
|
|
#define BM_IPU_CSI1_SKIP_CSI1_SKIP_ISP (0x00f80000) //!< Bit mask for IPU_CSI1_SKIP_CSI1_SKIP_ISP.
|
|
|
|
//! @brief Get value of IPU_CSI1_SKIP_CSI1_SKIP_ISP from a register value.
|
|
#define BG_IPU_CSI1_SKIP_CSI1_SKIP_ISP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_SKIP_CSI1_SKIP_ISP) >> BP_IPU_CSI1_SKIP_CSI1_SKIP_ISP)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_SKIP_CSI1_SKIP_ISP.
|
|
#define BF_IPU_CSI1_SKIP_CSI1_SKIP_ISP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_SKIP_CSI1_SKIP_ISP) & BM_IPU_CSI1_SKIP_CSI1_SKIP_ISP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_SKIP_ISP field to a new value.
|
|
#define BW_IPU_CSI1_SKIP_CSI1_SKIP_ISP(x, v) (HW_IPU_CSI1_SKIP_WR(x, (HW_IPU_CSI1_SKIP_RD(x) & ~BM_IPU_CSI1_SKIP_CSI1_SKIP_ISP) | BF_IPU_CSI1_SKIP_CSI1_SKIP_ISP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_CTRL - CSI1 Compander Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_CTRL - CSI1 Compander Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_ctrl_bitfields
|
|
{
|
|
unsigned RESERVED2 : 32; //!< [31:0] Reserved.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x38028)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_CTRL(x) (*(volatile hw_ipu_csi1_cpd_ctrl_t *) HW_IPU_CSI1_CPD_CTRL_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_CTRL_RD(x) (HW_IPU_CSI1_CPD_CTRL(x).U)
|
|
#define HW_IPU_CSI1_CPD_CTRL_WR(x, v) (HW_IPU_CSI1_CPD_CTRL(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_CTRL_SET(x, v) (HW_IPU_CSI1_CPD_CTRL_WR(x, HW_IPU_CSI1_CPD_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_CTRL_CLR(x, v) (HW_IPU_CSI1_CPD_CTRL_WR(x, HW_IPU_CSI1_CPD_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_CTRL_TOG(x, v) (HW_IPU_CSI1_CPD_CTRL_WR(x, HW_IPU_CSI1_CPD_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_CTRL bitfields
|
|
*/
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_RC_I - CSI1 Red Component Compander Constants Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_RC_I - CSI1 Red Component Compander Constants Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain CONSTANT <i> parameters used for companding of red component.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_rc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_rc_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_RC_2I : 9; //!< [8:0] CONSTANT <2*i> parameter of Compander, Red component.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned CSI1_CPD_RC_2I_1 : 9; //!< [24:16] CONSTANT <2*i+1> parameter of Compander, Red component.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_rc_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_RC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_RC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3802c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_RC_I(x) (*(volatile hw_ipu_csi1_cpd_rc_i_t *) HW_IPU_CSI1_CPD_RC_I_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_RC_I_RD(x) (HW_IPU_CSI1_CPD_RC_I(x).U)
|
|
#define HW_IPU_CSI1_CPD_RC_I_WR(x, v) (HW_IPU_CSI1_CPD_RC_I(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_RC_I_SET(x, v) (HW_IPU_CSI1_CPD_RC_I_WR(x, HW_IPU_CSI1_CPD_RC_I_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_RC_I_CLR(x, v) (HW_IPU_CSI1_CPD_RC_I_WR(x, HW_IPU_CSI1_CPD_RC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_RC_I_TOG(x, v) (HW_IPU_CSI1_CPD_RC_I_WR(x, HW_IPU_CSI1_CPD_RC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_RC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_RC_I, field CSI1_CPD_RC_2I[8:0] (RW)
|
|
*
|
|
* CONSTANT <2*i> parameter of Compander, Red component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I (0) //!< Bit position for IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I.
|
|
#define BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I (0x000001ff) //!< Bit mask for IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I from a register value.
|
|
#define BG_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I) >> BP_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I.
|
|
#define BF_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I) & BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_RC_2I field to a new value.
|
|
#define BW_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I(x, v) (HW_IPU_CSI1_CPD_RC_I_WR(x, (HW_IPU_CSI1_CPD_RC_I_RD(x) & ~BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I) | BF_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_RC_I, field CSI1_CPD_RC_2I_1[24:16] (RW)
|
|
*
|
|
* CONSTANT <2*i+1> parameter of Compander, Red component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1 (16) //!< Bit position for IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1.
|
|
#define BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1 from a register value.
|
|
#define BG_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1) >> BP_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1.
|
|
#define BF_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1) & BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_RC_2I_1 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1(x, v) (HW_IPU_CSI1_CPD_RC_I_WR(x, (HW_IPU_CSI1_CPD_RC_I_RD(x) & ~BM_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1) | BF_IPU_CSI1_CPD_RC_I_CSI1_CPD_RC_2I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_RS_I - CSI1 Red Component Compander SLOPE Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_RS_I - CSI1 Red Component Compander SLOPE Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain SLOPE <i> parameters used for companding of red component.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_rs_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_rs_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_RS_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Compander, Red component.
|
|
unsigned CSI1_CPD_RS_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Compander, Red component.
|
|
unsigned CSI1_CPD_RS_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Compander, Red component.
|
|
unsigned CSI1_CPD_RS_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Compander, Red component.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_rs_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_RS_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_RS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3804c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_RS_I(x) (*(volatile hw_ipu_csi1_cpd_rs_i_t *) HW_IPU_CSI1_CPD_RS_I_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_RS_I_RD(x) (HW_IPU_CSI1_CPD_RS_I(x).U)
|
|
#define HW_IPU_CSI1_CPD_RS_I_WR(x, v) (HW_IPU_CSI1_CPD_RS_I(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_RS_I_SET(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, HW_IPU_CSI1_CPD_RS_I_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_RS_I_CLR(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, HW_IPU_CSI1_CPD_RS_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_RS_I_TOG(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, HW_IPU_CSI1_CPD_RS_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_RS_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_RS_I, field CSI1_CPD_RS_4I[7:0] (RW)
|
|
*
|
|
* SLOPE<4*i> parameter of Compander, Red component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I (0) //!< Bit position for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I.
|
|
#define BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I (0x000000ff) //!< Bit mask for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I from a register value.
|
|
#define BG_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I) >> BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I.
|
|
#define BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_RS_4I field to a new value.
|
|
#define BW_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, (HW_IPU_CSI1_CPD_RS_I_RD(x) & ~BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I) | BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_RS_I, field CSI1_CPD_RS_4I_1[15:8] (RW)
|
|
*
|
|
* SLOPE<4*i+1> parameter of Compander, Red component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1 (8) //!< Bit position for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1.
|
|
#define BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1 from a register value.
|
|
#define BG_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1) >> BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1.
|
|
#define BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_RS_4I_1 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, (HW_IPU_CSI1_CPD_RS_I_RD(x) & ~BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1) | BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_RS_I, field CSI1_CPD_RS_4I_2[23:16] (RW)
|
|
*
|
|
* SLOPE<4*i+2> parameter of Compander, Red component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2 (16) //!< Bit position for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2.
|
|
#define BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2 from a register value.
|
|
#define BG_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2) >> BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2.
|
|
#define BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_RS_4I_2 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, (HW_IPU_CSI1_CPD_RS_I_RD(x) & ~BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2) | BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_RS_I, field CSI1_CPD_RS_4I_3[31:24] (RW)
|
|
*
|
|
* SLOPE<4*i+3> parameter of Compander, Red component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3 (24) //!< Bit position for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3.
|
|
#define BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3 (0xff000000) //!< Bit mask for IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3 from a register value.
|
|
#define BG_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3) >> BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3.
|
|
#define BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3) & BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_RS_4I_3 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3(x, v) (HW_IPU_CSI1_CPD_RS_I_WR(x, (HW_IPU_CSI1_CPD_RS_I_RD(x) & ~BM_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3) | BF_IPU_CSI1_CPD_RS_I_CSI1_CPD_RS_4I_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_GRC_I - CSI1 GR Component Compander Constants Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_GRC_I - CSI1 GR Component Compander Constants Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain CONSTANTi parameters used for companding of green components in GRGR
|
|
* rows.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_grc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_grc_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_GRC_2I : 9; //!< [8:0] CONSTANT<2*i> parameter of Compander, GR component.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned CSI1_CPD_GRC_2I_1 : 9; //!< [24:16] CONST<2*i+1> parameter of Compander, GR component.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_grc_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_GRC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_GRC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3805c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_GRC_I(x) (*(volatile hw_ipu_csi1_cpd_grc_i_t *) HW_IPU_CSI1_CPD_GRC_I_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_GRC_I_RD(x) (HW_IPU_CSI1_CPD_GRC_I(x).U)
|
|
#define HW_IPU_CSI1_CPD_GRC_I_WR(x, v) (HW_IPU_CSI1_CPD_GRC_I(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_GRC_I_SET(x, v) (HW_IPU_CSI1_CPD_GRC_I_WR(x, HW_IPU_CSI1_CPD_GRC_I_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_GRC_I_CLR(x, v) (HW_IPU_CSI1_CPD_GRC_I_WR(x, HW_IPU_CSI1_CPD_GRC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_GRC_I_TOG(x, v) (HW_IPU_CSI1_CPD_GRC_I_WR(x, HW_IPU_CSI1_CPD_GRC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_GRC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GRC_I, field CSI1_CPD_GRC_2I[8:0] (RW)
|
|
*
|
|
* CONSTANT<2*i> parameter of Compander, GR component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GRC should be equal to CSI1_CPD_GBC Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I (0) //!< Bit position for IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I.
|
|
#define BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I (0x000001ff) //!< Bit mask for IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I.
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|
|
|
//! @brief Get value of IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I from a register value.
|
|
#define BG_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I) >> BP_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I)
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|
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|
//! @brief Format value for bitfield IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I.
|
|
#define BF_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I) & BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GRC_2I field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I(x, v) (HW_IPU_CSI1_CPD_GRC_I_WR(x, (HW_IPU_CSI1_CPD_GRC_I_RD(x) & ~BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I) | BF_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GRC_I, field CSI1_CPD_GRC_2I_1[24:16] (RW)
|
|
*
|
|
* CONST<2*i+1> parameter of Compander, GR component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GRC should be equal to CSI1_CPD_GBC Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1 (16) //!< Bit position for IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1.
|
|
#define BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1.
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|
|
|
//! @brief Get value of IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1 from a register value.
|
|
#define BG_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1) >> BP_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1.
|
|
#define BF_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1) & BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GRC_2I_1 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1(x, v) (HW_IPU_CSI1_CPD_GRC_I_WR(x, (HW_IPU_CSI1_CPD_GRC_I_RD(x) & ~BM_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1) | BF_IPU_CSI1_CPD_GRC_I_CSI1_CPD_GRC_2I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_GRS_I - CSI1 GR Component Compander SLOPE Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_GRS_I - CSI1 GR Component Compander SLOPE Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain SLOPEi parameters used for companding of green components in GRGR rows.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_grs_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_grs_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_GRS_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Compander, GR component.
|
|
unsigned CSI1_CPD_GRS_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Compander, GR component.
|
|
unsigned CSI1_CPD_GRS_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Compander, GR component.
|
|
unsigned CSI1_CPD_GRS_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Compander, GR component.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_grs_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_GRS_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_GRS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3807c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_GRS_I(x) (*(volatile hw_ipu_csi1_cpd_grs_i_t *) HW_IPU_CSI1_CPD_GRS_I_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_GRS_I_RD(x) (HW_IPU_CSI1_CPD_GRS_I(x).U)
|
|
#define HW_IPU_CSI1_CPD_GRS_I_WR(x, v) (HW_IPU_CSI1_CPD_GRS_I(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_GRS_I_SET(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, HW_IPU_CSI1_CPD_GRS_I_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_GRS_I_CLR(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, HW_IPU_CSI1_CPD_GRS_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_GRS_I_TOG(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, HW_IPU_CSI1_CPD_GRS_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_GRS_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GRS_I, field CSI1_CPD_GRS_4I[7:0] (RW)
|
|
*
|
|
* SLOPE<4*i> parameter of Compander, GR component. If the input format is RGB/YUV then CSI1_CPD_GRS
|
|
* should be equal to CSI1_CPD_GBS Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I (0) //!< Bit position for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I.
|
|
#define BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I (0x000000ff) //!< Bit mask for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I from a register value.
|
|
#define BG_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I) >> BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I.
|
|
#define BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GRS_4I field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, (HW_IPU_CSI1_CPD_GRS_I_RD(x) & ~BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I) | BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GRS_I, field CSI1_CPD_GRS_4I_1[15:8] (RW)
|
|
*
|
|
* SLOPE<4*i+1> parameter of Compander, GR component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GRS should be equal to CSI1_CPD_GBS Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1 (8) //!< Bit position for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1.
|
|
#define BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1 from a register value.
|
|
#define BG_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1) >> BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1.
|
|
#define BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GRS_4I_1 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, (HW_IPU_CSI1_CPD_GRS_I_RD(x) & ~BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1) | BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GRS_I, field CSI1_CPD_GRS_4I_2[23:16] (RW)
|
|
*
|
|
* SLOPE<4*i+2> parameter of Compander, GR component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GRS should be equal to CSI1_CPD_GBS Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2 (16) //!< Bit position for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2.
|
|
#define BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2 from a register value.
|
|
#define BG_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2) >> BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2.
|
|
#define BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GRS_4I_2 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, (HW_IPU_CSI1_CPD_GRS_I_RD(x) & ~BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2) | BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GRS_I, field CSI1_CPD_GRS_4I_3[31:24] (RW)
|
|
*
|
|
* SLOPE<4*i+3> parameter of Compander, GR component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GRS should be equal to CSI1_CPD_GBS Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3 (24) //!< Bit position for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3.
|
|
#define BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3 (0xff000000) //!< Bit mask for IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3 from a register value.
|
|
#define BG_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3) >> BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3.
|
|
#define BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3) & BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GRS_4I_3 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3(x, v) (HW_IPU_CSI1_CPD_GRS_I_WR(x, (HW_IPU_CSI1_CPD_GRS_I_RD(x) & ~BM_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3) | BF_IPU_CSI1_CPD_GRS_I_CSI1_CPD_GRS_4I_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_GBC_I - CSI1 GB Component Compander Constants Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_GBC_I - CSI1 GB Component Compander Constants Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain CONSTANTi parameters used for companding of green components in GBGB
|
|
* rows.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_gbc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_gbc_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_GBC_2I : 9; //!< [8:0] CONSTANTi parameter of Compander, GB component.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned CSI1_CPD_GBC_2I_1 : 9; //!< [24:16] CONSTi+1 parameter of Compander, GB component.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_gbc_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_GBC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_GBC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x3808c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_GBC_I(x) (*(volatile hw_ipu_csi1_cpd_gbc_i_t *) HW_IPU_CSI1_CPD_GBC_I_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_GBC_I_RD(x) (HW_IPU_CSI1_CPD_GBC_I(x).U)
|
|
#define HW_IPU_CSI1_CPD_GBC_I_WR(x, v) (HW_IPU_CSI1_CPD_GBC_I(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_GBC_I_SET(x, v) (HW_IPU_CSI1_CPD_GBC_I_WR(x, HW_IPU_CSI1_CPD_GBC_I_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_GBC_I_CLR(x, v) (HW_IPU_CSI1_CPD_GBC_I_WR(x, HW_IPU_CSI1_CPD_GBC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_GBC_I_TOG(x, v) (HW_IPU_CSI1_CPD_GBC_I_WR(x, HW_IPU_CSI1_CPD_GBC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_GBC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GBC_I, field CSI1_CPD_GBC_2I[8:0] (RW)
|
|
*
|
|
* CONSTANTi parameter of Compander, GB component. If the input format is RGB/YUV then CSI1_CPD_GBC
|
|
* should be equal to CSI1_CPD_GRC Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I (0) //!< Bit position for IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I.
|
|
#define BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I (0x000001ff) //!< Bit mask for IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I from a register value.
|
|
#define BG_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I) >> BP_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I)
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//! @brief Format value for bitfield IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I.
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#define BF_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I) & BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI1_CPD_GBC_2I field to a new value.
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#define BW_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I(x, v) (HW_IPU_CSI1_CPD_GBC_I_WR(x, (HW_IPU_CSI1_CPD_GBC_I_RD(x) & ~BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I) | BF_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I(v)))
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#endif
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//@}
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/*! @name Register IPU_CSI1_CPD_GBC_I, field CSI1_CPD_GBC_2I_1[24:16] (RW)
|
|
*
|
|
* CONSTi+1 parameter of Compander, GB component. If the input format is RGB/YUV then CSI1_CPD_GBC
|
|
* should be equal to CSI1_CPD_GRC Reserved
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|
*/
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|
//@{
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|
#define BP_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1 (16) //!< Bit position for IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1.
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#define BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1.
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//! @brief Get value of IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1 from a register value.
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#define BG_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1) >> BP_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1)
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//! @brief Format value for bitfield IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1.
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#define BF_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1) & BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CSI1_CPD_GBC_2I_1 field to a new value.
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#define BW_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1(x, v) (HW_IPU_CSI1_CPD_GBC_I_WR(x, (HW_IPU_CSI1_CPD_GBC_I_RD(x) & ~BM_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1) | BF_IPU_CSI1_CPD_GBC_I_CSI1_CPD_GBC_2I_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CSI1_CPD_GBS_I - CSI1 GB Component Compander SLOPE Register <i>
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_CSI1_CPD_GBS_I - CSI1 GB Component Compander SLOPE Register <i> (RW)
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*
|
|
* Reset value: 0x00000000
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*
|
|
* These registers contain SLOPEi parameters used for companding of green components in GBGB rows.
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*/
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typedef union _hw_ipu_csi1_cpd_gbs_i
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{
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reg32_t U;
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struct _hw_ipu_csi1_cpd_gbs_i_bitfields
|
|
{
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unsigned CSI1_CPD_GBS_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Compander, GB component.
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unsigned CSI1_CPD_GBS_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Compander, GB component.
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unsigned CSI1_CPD_GBS_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Compander, GB component.
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unsigned CSI1_CPD_GBS_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Compander, GB component.
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} B;
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} hw_ipu_csi1_cpd_gbs_i_t;
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#endif
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/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_GBS_I register
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*/
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//@{
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|
#define HW_IPU_CSI1_CPD_GBS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x380ac)
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#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_CSI1_CPD_GBS_I(x) (*(volatile hw_ipu_csi1_cpd_gbs_i_t *) HW_IPU_CSI1_CPD_GBS_I_ADDR(x))
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#define HW_IPU_CSI1_CPD_GBS_I_RD(x) (HW_IPU_CSI1_CPD_GBS_I(x).U)
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#define HW_IPU_CSI1_CPD_GBS_I_WR(x, v) (HW_IPU_CSI1_CPD_GBS_I(x).U = (v))
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#define HW_IPU_CSI1_CPD_GBS_I_SET(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, HW_IPU_CSI1_CPD_GBS_I_RD(x) | (v)))
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#define HW_IPU_CSI1_CPD_GBS_I_CLR(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, HW_IPU_CSI1_CPD_GBS_I_RD(x) & ~(v)))
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#define HW_IPU_CSI1_CPD_GBS_I_TOG(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, HW_IPU_CSI1_CPD_GBS_I_RD(x) ^ (v)))
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#endif
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//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_GBS_I bitfields
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|
*/
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/*! @name Register IPU_CSI1_CPD_GBS_I, field CSI1_CPD_GBS_4I[7:0] (RW)
|
|
*
|
|
* SLOPE<4*i> parameter of Compander, GB component. If the input format is RGB/YUV then CSI1_CPD_GBS
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|
* should be equal to CSI1_CPD_GRS Reserved
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|
*/
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|
//@{
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|
#define BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I (0) //!< Bit position for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I.
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#define BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I (0x000000ff) //!< Bit mask for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I.
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//! @brief Get value of IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I from a register value.
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|
#define BG_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I) >> BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I)
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//! @brief Format value for bitfield IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I.
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|
#define BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GBS_4I field to a new value.
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|
#define BW_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, (HW_IPU_CSI1_CPD_GBS_I_RD(x) & ~BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I) | BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_CSI1_CPD_GBS_I, field CSI1_CPD_GBS_4I_1[15:8] (RW)
|
|
*
|
|
* SLOPE<4*i+1> parameter of Compander, GB component. If the input format is RGB/YUV then
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|
* CSI1_CPD_GBS should be equal to CSI1_CPD_GRS Reserved
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|
*/
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|
//@{
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|
#define BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1 (8) //!< Bit position for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1.
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#define BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1.
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//! @brief Get value of IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1 from a register value.
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#define BG_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1) >> BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1)
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//! @brief Format value for bitfield IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1.
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#define BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the CSI1_CPD_GBS_4I_1 field to a new value.
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|
#define BW_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, (HW_IPU_CSI1_CPD_GBS_I_RD(x) & ~BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1) | BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_1(v)))
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|
#endif
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|
//@}
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|
/*! @name Register IPU_CSI1_CPD_GBS_I, field CSI1_CPD_GBS_4I_2[23:16] (RW)
|
|
*
|
|
* SLOPE<4*i+2> parameter of Compander, GB component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GBS should be equal to CSI1_CPD_GRS Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2 (16) //!< Bit position for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2.
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|
#define BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2.
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|
|
|
//! @brief Get value of IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2 from a register value.
|
|
#define BG_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2) >> BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2)
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|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2.
|
|
#define BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GBS_4I_2 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, (HW_IPU_CSI1_CPD_GBS_I_RD(x) & ~BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2) | BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_2(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_GBS_I, field CSI1_CPD_GBS_4I_3[31:24] (RW)
|
|
*
|
|
* SLOPE<4*i+3> parameter of Compander, GB component. If the input format is RGB/YUV then
|
|
* CSI1_CPD_GBS should be equal to CSI1_CPD_GRS Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3 (24) //!< Bit position for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3.
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|
#define BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3 (0xff000000) //!< Bit mask for IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3.
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|
|
|
//! @brief Get value of IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3 from a register value.
|
|
#define BG_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3) >> BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3.
|
|
#define BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3) & BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GBS_4I_3 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3(x, v) (HW_IPU_CSI1_CPD_GBS_I_WR(x, (HW_IPU_CSI1_CPD_GBS_I_RD(x) & ~BM_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3) | BF_IPU_CSI1_CPD_GBS_I_CSI1_CPD_GBS_4I_3(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_BC_I - CSI1 Blue Component Compander Constants Register <i>
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_BC_I - CSI1 Blue Component Compander Constants Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contend CONSTANTi parameters used for companding of blue component.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_bc_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_bc_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_BC_2I : 9; //!< [8:0] CONSTANT<2*i> parameter of Compander, Blue component.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned CSI1_CPD_BC_2I_1 : 9; //!< [24:16] CONSTANT<2*i+1> parameter of Compander, Blue component.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_csi1_cpd_bc_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_BC_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_BC_I_ADDR(x) (REGS_IPU_BASE(x) + 0x380bc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_BC_I(x) (*(volatile hw_ipu_csi1_cpd_bc_i_t *) HW_IPU_CSI1_CPD_BC_I_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_BC_I_RD(x) (HW_IPU_CSI1_CPD_BC_I(x).U)
|
|
#define HW_IPU_CSI1_CPD_BC_I_WR(x, v) (HW_IPU_CSI1_CPD_BC_I(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_BC_I_SET(x, v) (HW_IPU_CSI1_CPD_BC_I_WR(x, HW_IPU_CSI1_CPD_BC_I_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_BC_I_CLR(x, v) (HW_IPU_CSI1_CPD_BC_I_WR(x, HW_IPU_CSI1_CPD_BC_I_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_BC_I_TOG(x, v) (HW_IPU_CSI1_CPD_BC_I_WR(x, HW_IPU_CSI1_CPD_BC_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_BC_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_BC_I, field CSI1_CPD_BC_2I[8:0] (RW)
|
|
*
|
|
* CONSTANT<2*i> parameter of Compander, Blue component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I (0) //!< Bit position for IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I.
|
|
#define BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I (0x000001ff) //!< Bit mask for IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I from a register value.
|
|
#define BG_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I) >> BP_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I.
|
|
#define BF_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I) & BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_BC_2I field to a new value.
|
|
#define BW_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I(x, v) (HW_IPU_CSI1_CPD_BC_I_WR(x, (HW_IPU_CSI1_CPD_BC_I_RD(x) & ~BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I) | BF_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_BC_I, field CSI1_CPD_BC_2I_1[24:16] (RW)
|
|
*
|
|
* CONSTANT<2*i+1> parameter of Compander, Blue component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1 (16) //!< Bit position for IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1.
|
|
#define BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1 (0x01ff0000) //!< Bit mask for IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1 from a register value.
|
|
#define BG_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1) >> BP_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1)
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//! @brief Format value for bitfield IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1.
|
|
#define BF_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1) & BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_BC_2I_1 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1(x, v) (HW_IPU_CSI1_CPD_BC_I_WR(x, (HW_IPU_CSI1_CPD_BC_I_RD(x) & ~BM_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1) | BF_IPU_CSI1_CPD_BC_I_CSI1_CPD_BC_2I_1(v)))
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#endif
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//@}
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|
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//-------------------------------------------------------------------------------------------
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// HW_IPU_CSI1_CPD_BS_I - CSI1 Blue Component Compander SLOPE Register <i>
|
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//-------------------------------------------------------------------------------------------
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|
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|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_BS_I - CSI1 Blue Component Compander SLOPE Register <i> (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This registers contain SLOPEi parameters used for companding of red component.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_bs_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_bs_i_bitfields
|
|
{
|
|
unsigned CSI1_CPD_BS_4I : 8; //!< [7:0] SLOPE<4*i> parameter of Compander, Blue component.
|
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unsigned CSI1_CPD_BS_4I_1 : 8; //!< [15:8] SLOPE<4*i+1> parameter of Compander, Blue component.
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unsigned CSI1_CPD_BS_4I_2 : 8; //!< [23:16] SLOPE<4*i+2> parameter of Compander, Blue component.
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unsigned CSI1_CPD_BS_4I_3 : 8; //!< [31:24] SLOPE<4*i+3> parameter of Compander, Blue component.
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|
} B;
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|
} hw_ipu_csi1_cpd_bs_i_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_BS_I register
|
|
*/
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|
//@{
|
|
#define HW_IPU_CSI1_CPD_BS_I_ADDR(x) (REGS_IPU_BASE(x) + 0x380dc)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_CSI1_CPD_BS_I(x) (*(volatile hw_ipu_csi1_cpd_bs_i_t *) HW_IPU_CSI1_CPD_BS_I_ADDR(x))
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#define HW_IPU_CSI1_CPD_BS_I_RD(x) (HW_IPU_CSI1_CPD_BS_I(x).U)
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#define HW_IPU_CSI1_CPD_BS_I_WR(x, v) (HW_IPU_CSI1_CPD_BS_I(x).U = (v))
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#define HW_IPU_CSI1_CPD_BS_I_SET(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, HW_IPU_CSI1_CPD_BS_I_RD(x) | (v)))
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#define HW_IPU_CSI1_CPD_BS_I_CLR(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, HW_IPU_CSI1_CPD_BS_I_RD(x) & ~(v)))
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#define HW_IPU_CSI1_CPD_BS_I_TOG(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, HW_IPU_CSI1_CPD_BS_I_RD(x) ^ (v)))
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#endif
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|
//@}
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|
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/*
|
|
* constants & macros for individual IPU_CSI1_CPD_BS_I bitfields
|
|
*/
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/*! @name Register IPU_CSI1_CPD_BS_I, field CSI1_CPD_BS_4I[7:0] (RW)
|
|
*
|
|
* SLOPE<4*i> parameter of Compander, Blue component. Reserved
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|
*/
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|
//@{
|
|
#define BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I (0) //!< Bit position for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I.
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|
#define BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I (0x000000ff) //!< Bit mask for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I.
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//! @brief Get value of IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I from a register value.
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|
#define BG_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I) >> BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I)
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//! @brief Format value for bitfield IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I.
|
|
#define BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_BS_4I field to a new value.
|
|
#define BW_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, (HW_IPU_CSI1_CPD_BS_I_RD(x) & ~BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I) | BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_CSI1_CPD_BS_I, field CSI1_CPD_BS_4I_1[15:8] (RW)
|
|
*
|
|
* SLOPE<4*i+1> parameter of Compander, Blue component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1 (8) //!< Bit position for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1.
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|
#define BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1 (0x0000ff00) //!< Bit mask for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1.
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//! @brief Get value of IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1 from a register value.
|
|
#define BG_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1) >> BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1)
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|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1.
|
|
#define BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_BS_4I_1 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, (HW_IPU_CSI1_CPD_BS_I_RD(x) & ~BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1) | BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_1(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_CSI1_CPD_BS_I, field CSI1_CPD_BS_4I_2[23:16] (RW)
|
|
*
|
|
* SLOPE<4*i+2> parameter of Compander, Blue component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2 (16) //!< Bit position for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2.
|
|
#define BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2 (0x00ff0000) //!< Bit mask for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2.
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|
|
|
//! @brief Get value of IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2 from a register value.
|
|
#define BG_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2) >> BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2)
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|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2.
|
|
#define BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_BS_4I_2 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, (HW_IPU_CSI1_CPD_BS_I_RD(x) & ~BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2) | BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_2(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_BS_I, field CSI1_CPD_BS_4I_3[31:24] (RW)
|
|
*
|
|
* SLOPE<4*i+3> parameter of Compander, Blue component. Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3 (24) //!< Bit position for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3.
|
|
#define BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3 (0xff000000) //!< Bit mask for IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3.
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|
|
|
//! @brief Get value of IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3 from a register value.
|
|
#define BG_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3) >> BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3.
|
|
#define BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3) & BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_BS_4I_3 field to a new value.
|
|
#define BW_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3(x, v) (HW_IPU_CSI1_CPD_BS_I_WR(x, (HW_IPU_CSI1_CPD_BS_I_RD(x) & ~BM_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3) | BF_IPU_CSI1_CPD_BS_I_CSI1_CPD_BS_4I_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_OFFSET1 - CSI1 Compander Offset Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_OFFSET1 - CSI1 Compander Offset Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain Offset parameters used for companding.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_offset1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_offset1_bitfields
|
|
{
|
|
unsigned CSI1_CPD_GR_OFFSET : 10; //!< [9:0] CSI1 Green Red component offset
|
|
unsigned CSI1_CPD_GB_OFFSET : 10; //!< [19:10] CSI1 Green Blue component offset
|
|
unsigned CSI1_CPD_B_OFFSET : 10; //!< [29:20] CSI1 Blue component offset
|
|
unsigned RESERVED0 : 2; //!< [31:30] Reserved
|
|
} B;
|
|
} hw_ipu_csi1_cpd_offset1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_OFFSET1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_OFFSET1_ADDR(x) (REGS_IPU_BASE(x) + 0x380ec)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_OFFSET1(x) (*(volatile hw_ipu_csi1_cpd_offset1_t *) HW_IPU_CSI1_CPD_OFFSET1_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_OFFSET1_RD(x) (HW_IPU_CSI1_CPD_OFFSET1(x).U)
|
|
#define HW_IPU_CSI1_CPD_OFFSET1_WR(x, v) (HW_IPU_CSI1_CPD_OFFSET1(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_OFFSET1_SET(x, v) (HW_IPU_CSI1_CPD_OFFSET1_WR(x, HW_IPU_CSI1_CPD_OFFSET1_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_OFFSET1_CLR(x, v) (HW_IPU_CSI1_CPD_OFFSET1_WR(x, HW_IPU_CSI1_CPD_OFFSET1_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_OFFSET1_TOG(x, v) (HW_IPU_CSI1_CPD_OFFSET1_WR(x, HW_IPU_CSI1_CPD_OFFSET1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_OFFSET1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_OFFSET1, field CSI1_CPD_GR_OFFSET[9:0] (RW)
|
|
*
|
|
* CSI1 Green Red component offset The value is between -512 to 511. The value is added to the
|
|
* green-red component before companding. Clipping: If the result of the green-red components value
|
|
* + the offset is smaller than 0, the result is zero If the result of the green-red components
|
|
* value + the offset is greater than 1023, the result is 1023 Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET (0) //!< Bit position for IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET.
|
|
#define BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET (0x000003ff) //!< Bit mask for IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET from a register value.
|
|
#define BG_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET) >> BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET.
|
|
#define BF_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET) & BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GR_OFFSET field to a new value.
|
|
#define BW_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET(x, v) (HW_IPU_CSI1_CPD_OFFSET1_WR(x, (HW_IPU_CSI1_CPD_OFFSET1_RD(x) & ~BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET) | BF_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GR_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_OFFSET1, field CSI1_CPD_GB_OFFSET[19:10] (RW)
|
|
*
|
|
* CSI1 Green Blue component offset The value is between -512 to 511. The value is added to the blue
|
|
* component before companding. Clipping: If the result of the green-blue components value + the
|
|
* offset is smaller than 0, the result is zero If the result of the green-blue components value +
|
|
* the offset is greater than 1023, the result is 1023 If the input format is RGB/YUV then
|
|
* CSI1_GB_OFFSET must be equal to CSI1_GR_OFFSET Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET (10) //!< Bit position for IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET.
|
|
#define BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET (0x000ffc00) //!< Bit mask for IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET from a register value.
|
|
#define BG_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET) >> BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET.
|
|
#define BF_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET) & BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_GB_OFFSET field to a new value.
|
|
#define BW_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET(x, v) (HW_IPU_CSI1_CPD_OFFSET1_WR(x, (HW_IPU_CSI1_CPD_OFFSET1_RD(x) & ~BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET) | BF_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_GB_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_CSI1_CPD_OFFSET1, field CSI1_CPD_B_OFFSET[29:20] (RW)
|
|
*
|
|
* CSI1 Blue component offset The value is between -512 to 511. The value is added to the blue
|
|
* component before companding. Clipping: If the result of the blue components value + the offset is
|
|
* smaller than 0, the result is zero If the result of the blue components value + the offset is
|
|
* greater than 1023, the result is 1023 Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET (20) //!< Bit position for IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET.
|
|
#define BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET (0x3ff00000) //!< Bit mask for IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET from a register value.
|
|
#define BG_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET) >> BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET.
|
|
#define BF_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET) & BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_B_OFFSET field to a new value.
|
|
#define BW_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET(x, v) (HW_IPU_CSI1_CPD_OFFSET1_WR(x, (HW_IPU_CSI1_CPD_OFFSET1_RD(x) & ~BM_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET) | BF_IPU_CSI1_CPD_OFFSET1_CSI1_CPD_B_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_CSI1_CPD_OFFSET2 - CSI1 Compander Offset Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_CSI1_CPD_OFFSET2 - CSI1 Compander Offset Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* These registers contain Offset parameters used for companding.
|
|
*/
|
|
typedef union _hw_ipu_csi1_cpd_offset2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_csi1_cpd_offset2_bitfields
|
|
{
|
|
unsigned CSI1_CPD_R_OFFSET : 10; //!< [9:0] CSI1 Red component offset
|
|
unsigned RESERVED0 : 22; //!< [31:10] Reserved
|
|
} B;
|
|
} hw_ipu_csi1_cpd_offset2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_CSI1_CPD_OFFSET2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_CSI1_CPD_OFFSET2_ADDR(x) (REGS_IPU_BASE(x) + 0x380f0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_CSI1_CPD_OFFSET2(x) (*(volatile hw_ipu_csi1_cpd_offset2_t *) HW_IPU_CSI1_CPD_OFFSET2_ADDR(x))
|
|
#define HW_IPU_CSI1_CPD_OFFSET2_RD(x) (HW_IPU_CSI1_CPD_OFFSET2(x).U)
|
|
#define HW_IPU_CSI1_CPD_OFFSET2_WR(x, v) (HW_IPU_CSI1_CPD_OFFSET2(x).U = (v))
|
|
#define HW_IPU_CSI1_CPD_OFFSET2_SET(x, v) (HW_IPU_CSI1_CPD_OFFSET2_WR(x, HW_IPU_CSI1_CPD_OFFSET2_RD(x) | (v)))
|
|
#define HW_IPU_CSI1_CPD_OFFSET2_CLR(x, v) (HW_IPU_CSI1_CPD_OFFSET2_WR(x, HW_IPU_CSI1_CPD_OFFSET2_RD(x) & ~(v)))
|
|
#define HW_IPU_CSI1_CPD_OFFSET2_TOG(x, v) (HW_IPU_CSI1_CPD_OFFSET2_WR(x, HW_IPU_CSI1_CPD_OFFSET2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_CSI1_CPD_OFFSET2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_CSI1_CPD_OFFSET2, field CSI1_CPD_R_OFFSET[9:0] (RW)
|
|
*
|
|
* CSI1 Red component offset The value is between -512 to 511. The value is added to the red
|
|
* component before companding. Clipping: If the result of the red components value + the offset is
|
|
* smaller than 0, the result is zero If the result of the red components value + the offset is
|
|
* greater than 1023, the result is 1023 Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET (0) //!< Bit position for IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET.
|
|
#define BM_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET (0x000003ff) //!< Bit mask for IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET.
|
|
|
|
//! @brief Get value of IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET from a register value.
|
|
#define BG_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET) >> BP_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET.
|
|
#define BF_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET) & BM_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CSI1_CPD_R_OFFSET field to a new value.
|
|
#define BW_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET(x, v) (HW_IPU_CSI1_CPD_OFFSET2_WR(x, (HW_IPU_CSI1_CPD_OFFSET2_RD(x) & ~BM_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET) | BF_IPU_CSI1_CPD_OFFSET2_CSI1_CPD_R_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_GENERAL - DI0 General Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_GENERAL - DI0 General Register (RW)
|
|
*
|
|
* Reset value: 0x00200000
|
|
*/
|
|
typedef union _hw_ipu_di0_general
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_general_bitfields
|
|
{
|
|
unsigned DI0_POLARITY_I_1 : 8; //!< [7:0] DI0 output pin's polarity
|
|
unsigned DI0_POLARITY_CS0 : 1; //!< [8] DI0 Chip Select's 0 polarity
|
|
unsigned DI0_POLARITY_CS1 : 1; //!< [9] DI0 Chip Select's 1 polarity
|
|
unsigned DI0_ERM_VSYNC_SEL : 1; //!< [10] DI0 error recovery block's VSYNC source select
|
|
unsigned DI0_ERR_TREATMENT : 1; //!< [11] In case of synchronous flow error there are 2 ways to handle the display
|
|
unsigned DI0_SYNC_COUNT_SEL : 4; //!< [15:12] For synchronous flow error: selects synchronous flow synchronization counter in DI:
|
|
unsigned RESERVED0 : 1; //!< [16] Reserved
|
|
unsigned DI0_POLARITY_DISP_CLK : 1; //!< [17] DI0 Output Clock's polarity
|
|
unsigned DI0_WATCHDOG_MODE : 2; //!< [19:18] DI0 watchdog mode
|
|
unsigned DI0_CLK_EXT : 1; //!< [20] DI0 External Clock.
|
|
unsigned DI0_VSYNC_EXT : 1; //!< [21] DI0 External VSYNC.
|
|
unsigned DI0_MASK_SEL : 1; //!< [22] DI0 Mask select.
|
|
unsigned DI0_DISP_CLOCK_INIT : 1; //!< [23] Display clock's initial mode
|
|
unsigned DI0_CLOCK_STOP_MODE : 4; //!< [27:24] DI clock stop mode
|
|
unsigned DI0_DISP_Y_SEL : 3; //!< [30:28] DI0 Display Vertical coordinate (Y) select.
|
|
unsigned DI0_PIN8_PIN15_SEL : 1; //!< [31] This bit routes PIN8 over PIN15
|
|
} B;
|
|
} hw_ipu_di0_general_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_GENERAL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_GENERAL_ADDR(x) (REGS_IPU_BASE(x) + 0x40000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_GENERAL(x) (*(volatile hw_ipu_di0_general_t *) HW_IPU_DI0_GENERAL_ADDR(x))
|
|
#define HW_IPU_DI0_GENERAL_RD(x) (HW_IPU_DI0_GENERAL(x).U)
|
|
#define HW_IPU_DI0_GENERAL_WR(x, v) (HW_IPU_DI0_GENERAL(x).U = (v))
|
|
#define HW_IPU_DI0_GENERAL_SET(x, v) (HW_IPU_DI0_GENERAL_WR(x, HW_IPU_DI0_GENERAL_RD(x) | (v)))
|
|
#define HW_IPU_DI0_GENERAL_CLR(x, v) (HW_IPU_DI0_GENERAL_WR(x, HW_IPU_DI0_GENERAL_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_GENERAL_TOG(x, v) (HW_IPU_DI0_GENERAL_WR(x, HW_IPU_DI0_GENERAL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_GENERAL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_POLARITY_I_1[7:0] (RW)
|
|
*
|
|
* DI0 output pin's polarity This bits define the polarity of each of the DI's outputs.
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_POLARITY_I_1 (0) //!< Bit position for IPU_DI0_GENERAL_DI0_POLARITY_I_1.
|
|
#define BM_IPU_DI0_GENERAL_DI0_POLARITY_I_1 (0x000000ff) //!< Bit mask for IPU_DI0_GENERAL_DI0_POLARITY_I_1.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_POLARITY_I_1 from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_POLARITY_I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_POLARITY_I_1) >> BP_IPU_DI0_GENERAL_DI0_POLARITY_I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_POLARITY_I_1.
|
|
#define BF_IPU_DI0_GENERAL_DI0_POLARITY_I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_POLARITY_I_1) & BM_IPU_DI0_GENERAL_DI0_POLARITY_I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_POLARITY_I_1 field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_POLARITY_I_1(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_POLARITY_I_1) | BF_IPU_DI0_GENERAL_DI0_POLARITY_I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_POLARITY_CS0[8] (RW)
|
|
*
|
|
* DI0 Chip Select's 0 polarity This bits define the polarity of the DI's CS0.
|
|
*
|
|
* Values:
|
|
* - 0 - The CS0 is active low
|
|
* - 1 - The CS0 is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_POLARITY_CS0 (8) //!< Bit position for IPU_DI0_GENERAL_DI0_POLARITY_CS0.
|
|
#define BM_IPU_DI0_GENERAL_DI0_POLARITY_CS0 (0x00000100) //!< Bit mask for IPU_DI0_GENERAL_DI0_POLARITY_CS0.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_POLARITY_CS0 from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_POLARITY_CS0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_POLARITY_CS0) >> BP_IPU_DI0_GENERAL_DI0_POLARITY_CS0)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_POLARITY_CS0.
|
|
#define BF_IPU_DI0_GENERAL_DI0_POLARITY_CS0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_POLARITY_CS0) & BM_IPU_DI0_GENERAL_DI0_POLARITY_CS0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_POLARITY_CS0 field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_POLARITY_CS0(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_POLARITY_CS0) | BF_IPU_DI0_GENERAL_DI0_POLARITY_CS0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_POLARITY_CS1[9] (RW)
|
|
*
|
|
* DI0 Chip Select's 1 polarity This bits define the polarity of the DI's CS1.
|
|
*
|
|
* Values:
|
|
* - 0 - The CS1 is active low
|
|
* - 1 - The CS1 is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_POLARITY_CS1 (9) //!< Bit position for IPU_DI0_GENERAL_DI0_POLARITY_CS1.
|
|
#define BM_IPU_DI0_GENERAL_DI0_POLARITY_CS1 (0x00000200) //!< Bit mask for IPU_DI0_GENERAL_DI0_POLARITY_CS1.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_POLARITY_CS1 from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_POLARITY_CS1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_POLARITY_CS1) >> BP_IPU_DI0_GENERAL_DI0_POLARITY_CS1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_POLARITY_CS1.
|
|
#define BF_IPU_DI0_GENERAL_DI0_POLARITY_CS1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_POLARITY_CS1) & BM_IPU_DI0_GENERAL_DI0_POLARITY_CS1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_POLARITY_CS1 field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_POLARITY_CS1(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_POLARITY_CS1) | BF_IPU_DI0_GENERAL_DI0_POLARITY_CS1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_ERM_VSYNC_SEL[10] (RW)
|
|
*
|
|
* DI0 error recovery block's VSYNC source select The error recovery block detect a case where the
|
|
* DI's VSYNC is asserted before the EOF. This bit selects the source of the VSYNC signal monitored
|
|
* by this mechanism.
|
|
*
|
|
* Values:
|
|
* - 0 - vsync_pre - an internal VSYNC signal asserted 2 lines before the DI's VSYNC
|
|
* - 1 - vsync_post - an internal VSYNC signal asserted 2 lines after the DI's VSYNC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL (10) //!< Bit position for IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL.
|
|
#define BM_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL (0x00000400) //!< Bit mask for IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL) >> BP_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL.
|
|
#define BF_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL) & BM_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_ERM_VSYNC_SEL field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL) | BF_IPU_DI0_GENERAL_DI0_ERM_VSYNC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_ERR_TREATMENT[11] (RW)
|
|
*
|
|
* In case of synchronous flow error there are 2 ways to handle the display
|
|
*
|
|
* Values:
|
|
* - 0 - Drive the last component
|
|
* - 1 - to wait (stop clock)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_ERR_TREATMENT (11) //!< Bit position for IPU_DI0_GENERAL_DI0_ERR_TREATMENT.
|
|
#define BM_IPU_DI0_GENERAL_DI0_ERR_TREATMENT (0x00000800) //!< Bit mask for IPU_DI0_GENERAL_DI0_ERR_TREATMENT.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_ERR_TREATMENT from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_ERR_TREATMENT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_ERR_TREATMENT) >> BP_IPU_DI0_GENERAL_DI0_ERR_TREATMENT)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_ERR_TREATMENT.
|
|
#define BF_IPU_DI0_GENERAL_DI0_ERR_TREATMENT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_ERR_TREATMENT) & BM_IPU_DI0_GENERAL_DI0_ERR_TREATMENT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_ERR_TREATMENT field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_ERR_TREATMENT(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_ERR_TREATMENT) | BF_IPU_DI0_GENERAL_DI0_ERR_TREATMENT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_SYNC_COUNT_SEL[15:12] (RW)
|
|
*
|
|
* For synchronous flow error: selects synchronous flow synchronization counter in DI:
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL (12) //!< Bit position for IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL.
|
|
#define BM_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL (0x0000f000) //!< Bit mask for IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL) >> BP_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL.
|
|
#define BF_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL) & BM_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SYNC_COUNT_SEL field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL) | BF_IPU_DI0_GENERAL_DI0_SYNC_COUNT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_POLARITY_DISP_CLK[17] (RW)
|
|
*
|
|
* DI0 Output Clock's polarity This bits define the polarity of the DI0's clock.
|
|
*
|
|
* Values:
|
|
* - 0 - The output clock is active low
|
|
* - 1 - The output clock is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK (17) //!< Bit position for IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK.
|
|
#define BM_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK (0x00020000) //!< Bit mask for IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK.
|
|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK) >> BP_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK.
|
|
#define BF_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK) & BM_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_POLARITY_DISP_CLK field to a new value.
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#define BW_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK) | BF_IPU_DI0_GENERAL_DI0_POLARITY_DISP_CLK(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_GENERAL, field DI0_WATCHDOG_MODE[19:18] (RW)
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*
|
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* DI0 watchdog mode In case of a display error where the DI clock is stopped (defined at
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* di0_err_treatment). An internal watchdog counts DI clocks. If this timer reached its pre defined
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* value the DI will skip the current frame and restart on the frame. This 2 bits define the number
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* of DI clock cycles that the timer counts.
|
|
*
|
|
* Values:
|
|
* - 00 - The timer counts 4 DI cycles
|
|
* - 01 - The timer counts 16 DI cycles
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* - 10 - The timer counts 64 DI cycles
|
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* - 11 - The timer counts 128 DI cycles
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*/
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//@{
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#define BP_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE (18) //!< Bit position for IPU_DI0_GENERAL_DI0_WATCHDOG_MODE.
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#define BM_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE (0x000c0000) //!< Bit mask for IPU_DI0_GENERAL_DI0_WATCHDOG_MODE.
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//! @brief Get value of IPU_DI0_GENERAL_DI0_WATCHDOG_MODE from a register value.
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#define BG_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE) >> BP_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE)
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//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_WATCHDOG_MODE.
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#define BF_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE) & BM_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_WATCHDOG_MODE field to a new value.
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|
#define BW_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE) | BF_IPU_DI0_GENERAL_DI0_WATCHDOG_MODE(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_GENERAL, field DI0_CLK_EXT[20] (RW)
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*
|
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* DI0 External Clock. This bit selects the source of the DI0's clock
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|
*
|
|
* Values:
|
|
* - 0 - The clock is internally generated by the IPU
|
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* - 1 - The source of the clock is external to the IPU
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*/
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//@{
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#define BP_IPU_DI0_GENERAL_DI0_CLK_EXT (20) //!< Bit position for IPU_DI0_GENERAL_DI0_CLK_EXT.
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#define BM_IPU_DI0_GENERAL_DI0_CLK_EXT (0x00100000) //!< Bit mask for IPU_DI0_GENERAL_DI0_CLK_EXT.
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//! @brief Get value of IPU_DI0_GENERAL_DI0_CLK_EXT from a register value.
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#define BG_IPU_DI0_GENERAL_DI0_CLK_EXT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_CLK_EXT) >> BP_IPU_DI0_GENERAL_DI0_CLK_EXT)
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//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_CLK_EXT.
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#define BF_IPU_DI0_GENERAL_DI0_CLK_EXT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_CLK_EXT) & BM_IPU_DI0_GENERAL_DI0_CLK_EXT)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CLK_EXT field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_CLK_EXT(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_CLK_EXT) | BF_IPU_DI0_GENERAL_DI0_CLK_EXT(v)))
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#endif
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|
//@}
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/*! @name Register IPU_DI0_GENERAL, field DI0_VSYNC_EXT[21] (RW)
|
|
*
|
|
* DI0 External VSYNC. This bit selects the source of the VSYNC signal
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|
*
|
|
* Values:
|
|
* - 0 - Internally generated by the IPU
|
|
* - 1 - External to the IPU
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|
*/
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|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_VSYNC_EXT (21) //!< Bit position for IPU_DI0_GENERAL_DI0_VSYNC_EXT.
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#define BM_IPU_DI0_GENERAL_DI0_VSYNC_EXT (0x00200000) //!< Bit mask for IPU_DI0_GENERAL_DI0_VSYNC_EXT.
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//! @brief Get value of IPU_DI0_GENERAL_DI0_VSYNC_EXT from a register value.
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|
#define BG_IPU_DI0_GENERAL_DI0_VSYNC_EXT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_VSYNC_EXT) >> BP_IPU_DI0_GENERAL_DI0_VSYNC_EXT)
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//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_VSYNC_EXT.
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|
#define BF_IPU_DI0_GENERAL_DI0_VSYNC_EXT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_VSYNC_EXT) & BM_IPU_DI0_GENERAL_DI0_VSYNC_EXT)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_VSYNC_EXT field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_VSYNC_EXT(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_VSYNC_EXT) | BF_IPU_DI0_GENERAL_DI0_VSYNC_EXT(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DI0_GENERAL, field DI0_MASK_SEL[22] (RW)
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|
*
|
|
* DI0 Mask select. IPP_PIN_2 output of the DI that functions as MASK signal can come from 2
|
|
* sources: counter #2 or extracted from the MASK data coming from the memory.
|
|
*
|
|
* Values:
|
|
* - 0 - IPP_PIN_2 is coming from counter #2
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|
* - 1 - IPP_PIN_2 is coming from extracted MASK data coming from the memory
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_GENERAL_DI0_MASK_SEL (22) //!< Bit position for IPU_DI0_GENERAL_DI0_MASK_SEL.
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#define BM_IPU_DI0_GENERAL_DI0_MASK_SEL (0x00400000) //!< Bit mask for IPU_DI0_GENERAL_DI0_MASK_SEL.
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//! @brief Get value of IPU_DI0_GENERAL_DI0_MASK_SEL from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_MASK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_MASK_SEL) >> BP_IPU_DI0_GENERAL_DI0_MASK_SEL)
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//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_MASK_SEL.
|
|
#define BF_IPU_DI0_GENERAL_DI0_MASK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_MASK_SEL) & BM_IPU_DI0_GENERAL_DI0_MASK_SEL)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_MASK_SEL field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_MASK_SEL(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_MASK_SEL) | BF_IPU_DI0_GENERAL_DI0_MASK_SEL(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DI0_GENERAL, field DI0_DISP_CLOCK_INIT[23] (RW)
|
|
*
|
|
* Display clock's initial mode For synchronization error conditions the display clock can be
|
|
* stopped on the next VSYNC
|
|
*
|
|
* Values:
|
|
* - 0 - The display's clock is stopped after the next VSYNC (indicating new frame)
|
|
* - 1 - The display's clock is running after the next VSYNC (indicating new frame)
|
|
*/
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|
//@{
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|
#define BP_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT (23) //!< Bit position for IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT.
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|
#define BM_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT (0x00800000) //!< Bit mask for IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT.
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//! @brief Get value of IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT) >> BP_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT)
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|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT.
|
|
#define BF_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT) & BM_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DISP_CLOCK_INIT field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT) | BF_IPU_DI0_GENERAL_DI0_DISP_CLOCK_INIT(v)))
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|
#endif
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|
//@}
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|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_CLOCK_STOP_MODE[27:24] (RW)
|
|
*
|
|
* DI clock stop mode When performing a clock change. The DI stops the clock to the display. These
|
|
* field defines when the clock will be stopped. Stopping at EOL/EOF is supported for the case where
|
|
* the data is coming from the IDMAC (DMA access). In case that only direct accesses is performed,
|
|
* the user should set this field to 0000 0001-1001 stop at the next event of one of the counters
|
|
* (counter #1 to counter #9)
|
|
*
|
|
* Values:
|
|
* - 0000 - stop at the next edge of the display clock
|
|
* - 1100 - stop at EOL (end of a line), but if stop request is during blanking interval, stop now
|
|
* - 1101 - stop at EOF (end of a frame), but if stop request is during blanking interval, stop now
|
|
* - 1110 - stop at EOL (end of a line), but if stop request is during blanking interval, stop at the end of the
|
|
* next line
|
|
* - 1111 - stop at EOF (end of a frame), but if stop request is during blanking interval, stop at the end of
|
|
* the next frame
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE (24) //!< Bit position for IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE.
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|
#define BM_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE (0x0f000000) //!< Bit mask for IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE.
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|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE) >> BP_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE)
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|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE.
|
|
#define BF_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE) & BM_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CLOCK_STOP_MODE field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE) | BF_IPU_DI0_GENERAL_DI0_CLOCK_STOP_MODE(v)))
|
|
#endif
|
|
//@}
|
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|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_DISP_Y_SEL[30:28] (RW)
|
|
*
|
|
* DI0 Display Vertical coordinate (Y) select. This field defines which one of the 8 counters will
|
|
* be used as a display's line counter.
|
|
*
|
|
* Values:
|
|
* - 000 - counter #1 is selected
|
|
* - 111 - counter #8 is selected
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_DISP_Y_SEL (28) //!< Bit position for IPU_DI0_GENERAL_DI0_DISP_Y_SEL.
|
|
#define BM_IPU_DI0_GENERAL_DI0_DISP_Y_SEL (0x70000000) //!< Bit mask for IPU_DI0_GENERAL_DI0_DISP_Y_SEL.
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|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_DISP_Y_SEL from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_DISP_Y_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_DISP_Y_SEL) >> BP_IPU_DI0_GENERAL_DI0_DISP_Y_SEL)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_DISP_Y_SEL.
|
|
#define BF_IPU_DI0_GENERAL_DI0_DISP_Y_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_DISP_Y_SEL) & BM_IPU_DI0_GENERAL_DI0_DISP_Y_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DISP_Y_SEL field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_DISP_Y_SEL(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_DISP_Y_SEL) | BF_IPU_DI0_GENERAL_DI0_DISP_Y_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_GENERAL, field DI0_PIN8_PIN15_SEL[31] (RW)
|
|
*
|
|
* This bit routes PIN8 over PIN15
|
|
*
|
|
* Values:
|
|
* - 0 - PIN15 is routed to PIN15, PIN8 is routed to PIN8
|
|
* - 1 - PIN8 is routed to PIN15, PIN8 is also routed to PIN8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL (31) //!< Bit position for IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL.
|
|
#define BM_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL (0x80000000) //!< Bit mask for IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL.
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|
|
|
//! @brief Get value of IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL from a register value.
|
|
#define BG_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL) >> BP_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL.
|
|
#define BF_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL) & BM_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PIN8_PIN15_SEL field to a new value.
|
|
#define BW_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL(x, v) (HW_IPU_DI0_GENERAL_WR(x, (HW_IPU_DI0_GENERAL_RD(x) & ~BM_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL) | BF_IPU_DI0_GENERAL_DI0_PIN8_PIN15_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_BS_CLKGEN0 - DI0 Base Sync Clock Gen 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_BS_CLKGEN0 - DI0 Base Sync Clock Gen 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_bs_clkgen0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_bs_clkgen0_bitfields
|
|
{
|
|
unsigned DI0_DISP_CLK_PERIOD : 12; //!< [11:0] DI0 Display Clock Period
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved.
|
|
unsigned DI0_DISP_CLK_OFFSET : 9; //!< [24:16] DI0 Display Clock Offset
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_bs_clkgen0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_BS_CLKGEN0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_BS_CLKGEN0_ADDR(x) (REGS_IPU_BASE(x) + 0x40004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_BS_CLKGEN0(x) (*(volatile hw_ipu_di0_bs_clkgen0_t *) HW_IPU_DI0_BS_CLKGEN0_ADDR(x))
|
|
#define HW_IPU_DI0_BS_CLKGEN0_RD(x) (HW_IPU_DI0_BS_CLKGEN0(x).U)
|
|
#define HW_IPU_DI0_BS_CLKGEN0_WR(x, v) (HW_IPU_DI0_BS_CLKGEN0(x).U = (v))
|
|
#define HW_IPU_DI0_BS_CLKGEN0_SET(x, v) (HW_IPU_DI0_BS_CLKGEN0_WR(x, HW_IPU_DI0_BS_CLKGEN0_RD(x) | (v)))
|
|
#define HW_IPU_DI0_BS_CLKGEN0_CLR(x, v) (HW_IPU_DI0_BS_CLKGEN0_WR(x, HW_IPU_DI0_BS_CLKGEN0_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_BS_CLKGEN0_TOG(x, v) (HW_IPU_DI0_BS_CLKGEN0_WR(x, HW_IPU_DI0_BS_CLKGEN0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_BS_CLKGEN0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_BS_CLKGEN0, field DI0_DISP_CLK_PERIOD[11:0] (RW)
|
|
*
|
|
* DI0 Display Clock Period This field defines the Display interface clock period for display write
|
|
* access. This parameter contains an integer part (bits 11:4) and a fractional part (bits 3:0). It
|
|
* defines a fractional division ratio of the HSP_CLK clock for generation of the display's
|
|
* interface clock.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD (0) //!< Bit position for IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD.
|
|
#define BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD (0x00000fff) //!< Bit mask for IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD.
|
|
|
|
//! @brief Get value of IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD from a register value.
|
|
#define BG_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD) >> BP_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD.
|
|
#define BF_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD) & BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DISP_CLK_PERIOD field to a new value.
|
|
#define BW_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD(x, v) (HW_IPU_DI0_BS_CLKGEN0_WR(x, (HW_IPU_DI0_BS_CLKGEN0_RD(x) & ~BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD) | BF_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_PERIOD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_BS_CLKGEN0, field DI0_DISP_CLK_OFFSET[24:16] (RW)
|
|
*
|
|
* DI0 Display Clock Offset The DI has the ability to delay the display's clock This field defines
|
|
* the amount of IPU's clock cycles added as delay on this clock.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET (16) //!< Bit position for IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET.
|
|
#define BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET (0x01ff0000) //!< Bit mask for IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET.
|
|
|
|
//! @brief Get value of IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET from a register value.
|
|
#define BG_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET) >> BP_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET.
|
|
#define BF_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET) & BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DISP_CLK_OFFSET field to a new value.
|
|
#define BW_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET(x, v) (HW_IPU_DI0_BS_CLKGEN0_WR(x, (HW_IPU_DI0_BS_CLKGEN0_RD(x) & ~BM_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET) | BF_IPU_DI0_BS_CLKGEN0_DI0_DISP_CLK_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_BS_CLKGEN1 - DI0 Base Sync Clock Gen 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_BS_CLKGEN1 - DI0 Base Sync Clock Gen 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_bs_clkgen1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_bs_clkgen1_bitfields
|
|
{
|
|
unsigned DI0_DISP_CLK_UP : 9; //!< [8:0] DI0 display clock rising edge position
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI0_DISP_CLK_DOWN : 9; //!< [24:16] DI0 display clock falling edge position
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_bs_clkgen1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_BS_CLKGEN1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_BS_CLKGEN1_ADDR(x) (REGS_IPU_BASE(x) + 0x40008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_BS_CLKGEN1(x) (*(volatile hw_ipu_di0_bs_clkgen1_t *) HW_IPU_DI0_BS_CLKGEN1_ADDR(x))
|
|
#define HW_IPU_DI0_BS_CLKGEN1_RD(x) (HW_IPU_DI0_BS_CLKGEN1(x).U)
|
|
#define HW_IPU_DI0_BS_CLKGEN1_WR(x, v) (HW_IPU_DI0_BS_CLKGEN1(x).U = (v))
|
|
#define HW_IPU_DI0_BS_CLKGEN1_SET(x, v) (HW_IPU_DI0_BS_CLKGEN1_WR(x, HW_IPU_DI0_BS_CLKGEN1_RD(x) | (v)))
|
|
#define HW_IPU_DI0_BS_CLKGEN1_CLR(x, v) (HW_IPU_DI0_BS_CLKGEN1_WR(x, HW_IPU_DI0_BS_CLKGEN1_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_BS_CLKGEN1_TOG(x, v) (HW_IPU_DI0_BS_CLKGEN1_WR(x, HW_IPU_DI0_BS_CLKGEN1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_BS_CLKGEN1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_BS_CLKGEN1, field DI0_DISP_CLK_UP[8:0] (RW)
|
|
*
|
|
* DI0 display clock rising edge position This parameter contains an integer part (bits 8:1) and a
|
|
* fractional part (bit 0). The position value is a time interval between display's access start
|
|
* point and display's interface clock rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP (0) //!< Bit position for IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP.
|
|
#define BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP (0x000001ff) //!< Bit mask for IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP.
|
|
|
|
//! @brief Get value of IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP from a register value.
|
|
#define BG_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP) >> BP_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP.
|
|
#define BF_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP) & BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DISP_CLK_UP field to a new value.
|
|
#define BW_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP(x, v) (HW_IPU_DI0_BS_CLKGEN1_WR(x, (HW_IPU_DI0_BS_CLKGEN1_RD(x) & ~BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP) | BF_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_UP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_BS_CLKGEN1, field DI0_DISP_CLK_DOWN[24:16] (RW)
|
|
*
|
|
* DI0 display clock falling edge position This parameter contains an integer part (bits 24:17) and
|
|
* a fractional part (bit 16). The position value is a time interval between display's access start
|
|
* point and display's interface clock falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN (16) //!< Bit position for IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN.
|
|
#define BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN (0x01ff0000) //!< Bit mask for IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN.
|
|
|
|
//! @brief Get value of IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN from a register value.
|
|
#define BG_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN) >> BP_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN.
|
|
#define BF_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN) & BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DISP_CLK_DOWN field to a new value.
|
|
#define BW_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN(x, v) (HW_IPU_DI0_BS_CLKGEN1_WR(x, (HW_IPU_DI0_BS_CLKGEN1_RD(x) & ~BM_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN) | BF_IPU_DI0_BS_CLKGEN1_DI0_DISP_CLK_DOWN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_1 - DI0 Sync Wave Gen 1 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_1 - DI0 Sync Wave Gen 1 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_1_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_1 : 3; //!< [2:0] DI0 counter #1 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_1 : 12; //!< [14:3] DI0 counter #1 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI0_RUN_RESOLUTION_1 : 3; //!< [18:16] DI0 counter #1 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_1 : 12; //!< [30:19] DI0 counter #1 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_1_ADDR(x) (REGS_IPU_BASE(x) + 0x4000c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_1(x) (*(volatile hw_ipu_di0_sw_gen0_1_t *) HW_IPU_DI0_SW_GEN0_1_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_1_RD(x) (HW_IPU_DI0_SW_GEN0_1(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_1_WR(x, v) (HW_IPU_DI0_SW_GEN0_1(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_1_SET(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, HW_IPU_DI0_SW_GEN0_1_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_1_CLR(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, HW_IPU_DI0_SW_GEN0_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_1_TOG(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, HW_IPU_DI0_SW_GEN0_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_1, field DI0_OFFSET_RESOLUTION_1[2:0] (RW)
|
|
*
|
|
* DI0 counter #1 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock
|
|
* - 010 - NA
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSIs according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1 (0) //!< Bit position for IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1.
|
|
#define BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1) >> BP_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1.
|
|
#define BF_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1) & BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, (HW_IPU_DI0_SW_GEN0_1_RD(x) & ~BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1) | BF_IPU_DI0_SW_GEN0_1_DI0_OFFSET_RESOLUTION_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_1, field DI0_OFFSET_VALUE_1[14:3] (RW)
|
|
*
|
|
* DI0 counter #1 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1 (3) //!< Bit position for IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1.
|
|
#define BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1) >> BP_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1.
|
|
#define BF_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1) & BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, (HW_IPU_DI0_SW_GEN0_1_RD(x) & ~BM_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1) | BF_IPU_DI0_SW_GEN0_1_DI0_OFFSET_VALUE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_1, field DI0_RUN_RESOLUTION_1[18:16] (RW)
|
|
*
|
|
* DI0 counter #1 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - NA
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSIs according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1 (16) //!< Bit position for IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1.
|
|
#define BM_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1) >> BP_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1.
|
|
#define BF_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1) & BM_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, (HW_IPU_DI0_SW_GEN0_1_RD(x) & ~BM_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1) | BF_IPU_DI0_SW_GEN0_1_DI0_RUN_RESOLUTION_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_1, field DI0_RUN_VALUE_M1_1[30:19] (RW)
|
|
*
|
|
* DI0 counter #1 pre defined value This fields defines the counter #1 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_1 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1 (19) //!< Bit position for IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1.
|
|
#define BM_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1) >> BP_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1.
|
|
#define BF_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1) & BM_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1(x, v) (HW_IPU_DI0_SW_GEN0_1_WR(x, (HW_IPU_DI0_SW_GEN0_1_RD(x) & ~BM_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1) | BF_IPU_DI0_SW_GEN0_1_DI0_RUN_VALUE_M1_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_2 - DI0 Sync Wave Gen 2 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_2 - DI0 Sync Wave Gen 2 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_2_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_2 : 3; //!< [2:0] DI0 counter #2 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_2 : 12; //!< [14:3] DI0 counter #2 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_2 : 3; //!< [18:16] DI0 counter #2 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_2 : 12; //!< [30:19] DI0 counter #2 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_2_ADDR(x) (REGS_IPU_BASE(x) + 0x40010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_2(x) (*(volatile hw_ipu_di0_sw_gen0_2_t *) HW_IPU_DI0_SW_GEN0_2_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_2_RD(x) (HW_IPU_DI0_SW_GEN0_2(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_2_WR(x, v) (HW_IPU_DI0_SW_GEN0_2(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_2_SET(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, HW_IPU_DI0_SW_GEN0_2_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_2_CLR(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, HW_IPU_DI0_SW_GEN0_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_2_TOG(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, HW_IPU_DI0_SW_GEN0_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_2, field DI0_OFFSET_RESOLUTION_2[2:0] (RW)
|
|
*
|
|
* DI0 counter #2 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSIs according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2 (0) //!< Bit position for IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2.
|
|
#define BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2) >> BP_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2.
|
|
#define BF_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2) & BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, (HW_IPU_DI0_SW_GEN0_2_RD(x) & ~BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2) | BF_IPU_DI0_SW_GEN0_2_DI0_OFFSET_RESOLUTION_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_2, field DI0_OFFSET_VALUE_2[14:3] (RW)
|
|
*
|
|
* DI0 counter #2 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2 (3) //!< Bit position for IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2.
|
|
#define BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2) >> BP_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2.
|
|
#define BF_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2) & BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, (HW_IPU_DI0_SW_GEN0_2_RD(x) & ~BM_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2) | BF_IPU_DI0_SW_GEN0_2_DI0_OFFSET_VALUE_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_2, field DI0_RUN_RESOLUTION_2[18:16] (RW)
|
|
*
|
|
* DI0 counter #2 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2 (16) //!< Bit position for IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2.
|
|
#define BM_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2) >> BP_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2.
|
|
#define BF_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2) & BM_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, (HW_IPU_DI0_SW_GEN0_2_RD(x) & ~BM_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2) | BF_IPU_DI0_SW_GEN0_2_DI0_RUN_RESOLUTION_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_2, field DI0_RUN_VALUE_M1_2[30:19] (RW)
|
|
*
|
|
* DI0 counter #2 pre defined value This fields defines the counter #2 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_2 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2 (19) //!< Bit position for IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2.
|
|
#define BM_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2) >> BP_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2.
|
|
#define BF_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2) & BM_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2(x, v) (HW_IPU_DI0_SW_GEN0_2_WR(x, (HW_IPU_DI0_SW_GEN0_2_RD(x) & ~BM_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2) | BF_IPU_DI0_SW_GEN0_2_DI0_RUN_VALUE_M1_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_3 - DI0 Sync Wave Gen 3 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_3 - DI0 Sync Wave Gen 3 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_3_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_3 : 3; //!< [2:0] DI0 counter #3 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_3 : 12; //!< [14:3] DI0 counter #3 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_3 : 3; //!< [18:16] DI0 counter #3 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_3 : 12; //!< [30:19] DI0 counter #3 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_3_ADDR(x) (REGS_IPU_BASE(x) + 0x40014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_3(x) (*(volatile hw_ipu_di0_sw_gen0_3_t *) HW_IPU_DI0_SW_GEN0_3_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_3_RD(x) (HW_IPU_DI0_SW_GEN0_3(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_3_WR(x, v) (HW_IPU_DI0_SW_GEN0_3(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_3_SET(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, HW_IPU_DI0_SW_GEN0_3_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_3_CLR(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, HW_IPU_DI0_SW_GEN0_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_3_TOG(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, HW_IPU_DI0_SW_GEN0_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_3, field DI0_OFFSET_RESOLUTION_3[2:0] (RW)
|
|
*
|
|
* DI0 counter #3 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3 (0) //!< Bit position for IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3.
|
|
#define BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3) >> BP_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3.
|
|
#define BF_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3) & BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, (HW_IPU_DI0_SW_GEN0_3_RD(x) & ~BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3) | BF_IPU_DI0_SW_GEN0_3_DI0_OFFSET_RESOLUTION_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_3, field DI0_OFFSET_VALUE_3[14:3] (RW)
|
|
*
|
|
* DI0 counter #3 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3 (3) //!< Bit position for IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3.
|
|
#define BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3) >> BP_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3.
|
|
#define BF_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3) & BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, (HW_IPU_DI0_SW_GEN0_3_RD(x) & ~BM_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3) | BF_IPU_DI0_SW_GEN0_3_DI0_OFFSET_VALUE_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_3, field DI0_RUN_RESOLUTION_3[18:16] (RW)
|
|
*
|
|
* DI0 counter #3 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3 (16) //!< Bit position for IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3.
|
|
#define BM_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3) >> BP_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3.
|
|
#define BF_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3) & BM_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, (HW_IPU_DI0_SW_GEN0_3_RD(x) & ~BM_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3) | BF_IPU_DI0_SW_GEN0_3_DI0_RUN_RESOLUTION_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_3, field DI0_RUN_VALUE_M1_3[30:19] (RW)
|
|
*
|
|
* DI0 counter #3 pre defined value This fields defines the counter #3 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_3 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3 (19) //!< Bit position for IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3.
|
|
#define BM_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3) >> BP_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3.
|
|
#define BF_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3) & BM_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3(x, v) (HW_IPU_DI0_SW_GEN0_3_WR(x, (HW_IPU_DI0_SW_GEN0_3_RD(x) & ~BM_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3) | BF_IPU_DI0_SW_GEN0_3_DI0_RUN_VALUE_M1_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_4 - DI0 Sync Wave Gen 4 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_4 - DI0 Sync Wave Gen 4 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_4_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_4 : 3; //!< [2:0] DI0 counter #4 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_4 : 12; //!< [14:3] DI0 counter #4 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_4 : 3; //!< [18:16] DI0 counter #4 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_4 : 12; //!< [30:19] DI0 counter #4 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_4_ADDR(x) (REGS_IPU_BASE(x) + 0x40018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_4(x) (*(volatile hw_ipu_di0_sw_gen0_4_t *) HW_IPU_DI0_SW_GEN0_4_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_4_RD(x) (HW_IPU_DI0_SW_GEN0_4(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_4_WR(x, v) (HW_IPU_DI0_SW_GEN0_4(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_4_SET(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, HW_IPU_DI0_SW_GEN0_4_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_4_CLR(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, HW_IPU_DI0_SW_GEN0_4_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_4_TOG(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, HW_IPU_DI0_SW_GEN0_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_4, field DI0_OFFSET_RESOLUTION_4[2:0] (RW)
|
|
*
|
|
* DI0 counter #4 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4 (0) //!< Bit position for IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4.
|
|
#define BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4) >> BP_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4.
|
|
#define BF_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4) & BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_4 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, (HW_IPU_DI0_SW_GEN0_4_RD(x) & ~BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4) | BF_IPU_DI0_SW_GEN0_4_DI0_OFFSET_RESOLUTION_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_4, field DI0_OFFSET_VALUE_4[14:3] (RW)
|
|
*
|
|
* DI0 counter #4 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4 (3) //!< Bit position for IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4.
|
|
#define BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4) >> BP_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4.
|
|
#define BF_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4) & BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_4 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, (HW_IPU_DI0_SW_GEN0_4_RD(x) & ~BM_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4) | BF_IPU_DI0_SW_GEN0_4_DI0_OFFSET_VALUE_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_4, field DI0_RUN_RESOLUTION_4[18:16] (RW)
|
|
*
|
|
* DI0 counter #4 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4 (16) //!< Bit position for IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4.
|
|
#define BM_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4) >> BP_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4.
|
|
#define BF_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4) & BM_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_4 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, (HW_IPU_DI0_SW_GEN0_4_RD(x) & ~BM_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4) | BF_IPU_DI0_SW_GEN0_4_DI0_RUN_RESOLUTION_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_4, field DI0_RUN_VALUE_M1_4[30:19] (RW)
|
|
*
|
|
* DI0 counter #4 pre defined value This fields defines the counter #4 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_4 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4 (19) //!< Bit position for IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4.
|
|
#define BM_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4) >> BP_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4.
|
|
#define BF_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4) & BM_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_4 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4(x, v) (HW_IPU_DI0_SW_GEN0_4_WR(x, (HW_IPU_DI0_SW_GEN0_4_RD(x) & ~BM_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4) | BF_IPU_DI0_SW_GEN0_4_DI0_RUN_VALUE_M1_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_5 - DI0 Sync Wave Gen 5 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_5 - DI0 Sync Wave Gen 5 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_5_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_5 : 3; //!< [2:0] DI0 counter #5 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_5 : 12; //!< [14:3] DI0 counter #5 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_5 : 3; //!< [18:16] DI0 counter #5 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_5 : 12; //!< [30:19] DI0 counter #5 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_5_ADDR(x) (REGS_IPU_BASE(x) + 0x4001c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_5(x) (*(volatile hw_ipu_di0_sw_gen0_5_t *) HW_IPU_DI0_SW_GEN0_5_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_5_RD(x) (HW_IPU_DI0_SW_GEN0_5(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_5_WR(x, v) (HW_IPU_DI0_SW_GEN0_5(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_5_SET(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, HW_IPU_DI0_SW_GEN0_5_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_5_CLR(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, HW_IPU_DI0_SW_GEN0_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_5_TOG(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, HW_IPU_DI0_SW_GEN0_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_5, field DI0_OFFSET_RESOLUTION_5[2:0] (RW)
|
|
*
|
|
* DI0 counter #5 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - -The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5 (0) //!< Bit position for IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5.
|
|
#define BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5) >> BP_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5.
|
|
#define BF_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5) & BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, (HW_IPU_DI0_SW_GEN0_5_RD(x) & ~BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5) | BF_IPU_DI0_SW_GEN0_5_DI0_OFFSET_RESOLUTION_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_5, field DI0_OFFSET_VALUE_5[14:3] (RW)
|
|
*
|
|
* DI0 counter #5 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5 (3) //!< Bit position for IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5.
|
|
#define BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5) >> BP_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5.
|
|
#define BF_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5) & BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, (HW_IPU_DI0_SW_GEN0_5_RD(x) & ~BM_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5) | BF_IPU_DI0_SW_GEN0_5_DI0_OFFSET_VALUE_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_5, field DI0_RUN_RESOLUTION_5[18:16] (RW)
|
|
*
|
|
* DI0 counter #5 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5 (16) //!< Bit position for IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5.
|
|
#define BM_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5) >> BP_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5.
|
|
#define BF_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5) & BM_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, (HW_IPU_DI0_SW_GEN0_5_RD(x) & ~BM_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5) | BF_IPU_DI0_SW_GEN0_5_DI0_RUN_RESOLUTION_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_5, field DI0_RUN_VALUE_M1_5[30:19] (RW)
|
|
*
|
|
* DI0 counter #5 pre defined value This fields defines the counter #5 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_5 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5 (19) //!< Bit position for IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5.
|
|
#define BM_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5) >> BP_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5.
|
|
#define BF_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5) & BM_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5(x, v) (HW_IPU_DI0_SW_GEN0_5_WR(x, (HW_IPU_DI0_SW_GEN0_5_RD(x) & ~BM_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5) | BF_IPU_DI0_SW_GEN0_5_DI0_RUN_VALUE_M1_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_6 - DI0 Sync Wave Gen 6 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_6 - DI0 Sync Wave Gen 6 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_6_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_6 : 3; //!< [2:0] DI0 counter #6 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_6 : 12; //!< [14:3] DI0 counter #6 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_6 : 3; //!< [18:16] DI0 counter #6 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_6 : 12; //!< [30:19] DI0 counter #6 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_6_ADDR(x) (REGS_IPU_BASE(x) + 0x40020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_6(x) (*(volatile hw_ipu_di0_sw_gen0_6_t *) HW_IPU_DI0_SW_GEN0_6_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_6_RD(x) (HW_IPU_DI0_SW_GEN0_6(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_6_WR(x, v) (HW_IPU_DI0_SW_GEN0_6(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_6_SET(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, HW_IPU_DI0_SW_GEN0_6_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_6_CLR(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, HW_IPU_DI0_SW_GEN0_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_6_TOG(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, HW_IPU_DI0_SW_GEN0_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_6, field DI0_OFFSET_RESOLUTION_6[2:0] (RW)
|
|
*
|
|
* DI0 counter #6 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6 (0) //!< Bit position for IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6.
|
|
#define BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6) >> BP_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6.
|
|
#define BF_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6) & BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, (HW_IPU_DI0_SW_GEN0_6_RD(x) & ~BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6) | BF_IPU_DI0_SW_GEN0_6_DI0_OFFSET_RESOLUTION_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_6, field DI0_OFFSET_VALUE_6[14:3] (RW)
|
|
*
|
|
* DI0 counter #6 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6 (3) //!< Bit position for IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6.
|
|
#define BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6) >> BP_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6.
|
|
#define BF_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6) & BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, (HW_IPU_DI0_SW_GEN0_6_RD(x) & ~BM_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6) | BF_IPU_DI0_SW_GEN0_6_DI0_OFFSET_VALUE_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_6, field DI0_RUN_RESOLUTION_6[18:16] (RW)
|
|
*
|
|
* DI0 counter #6 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6 (16) //!< Bit position for IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6.
|
|
#define BM_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6) >> BP_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6.
|
|
#define BF_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6) & BM_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, (HW_IPU_DI0_SW_GEN0_6_RD(x) & ~BM_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6) | BF_IPU_DI0_SW_GEN0_6_DI0_RUN_RESOLUTION_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_6, field DI0_RUN_VALUE_M1_6[30:19] (RW)
|
|
*
|
|
* DI0 counter #6 pre defined value This fields defines the counter #6 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_6 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6 (19) //!< Bit position for IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6.
|
|
#define BM_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6) >> BP_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6.
|
|
#define BF_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6) & BM_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6(x, v) (HW_IPU_DI0_SW_GEN0_6_WR(x, (HW_IPU_DI0_SW_GEN0_6_RD(x) & ~BM_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6) | BF_IPU_DI0_SW_GEN0_6_DI0_RUN_VALUE_M1_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_7 - DI0 Sync Wave Gen 7 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_7 - DI0 Sync Wave Gen 7 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_7_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_1 : 3; //!< [2:0] DI0 counter #7 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_7 : 12; //!< [14:3] DI0 counter #7 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_7 : 3; //!< [18:16] DI0 counter #1 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_7 : 12; //!< [30:19] DI0 counter #7 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_7_ADDR(x) (REGS_IPU_BASE(x) + 0x40024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_7(x) (*(volatile hw_ipu_di0_sw_gen0_7_t *) HW_IPU_DI0_SW_GEN0_7_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_7_RD(x) (HW_IPU_DI0_SW_GEN0_7(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_7_WR(x, v) (HW_IPU_DI0_SW_GEN0_7(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_7_SET(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, HW_IPU_DI0_SW_GEN0_7_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN0_7_CLR(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, HW_IPU_DI0_SW_GEN0_7_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN0_7_TOG(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, HW_IPU_DI0_SW_GEN0_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_7, field DI0_OFFSET_RESOLUTION_1[2:0] (RW)
|
|
*
|
|
* DI0 counter #7 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1 (0) //!< Bit position for IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1.
|
|
#define BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1) >> BP_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1.
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#define BF_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1) & BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_OFFSET_RESOLUTION_1 field to a new value.
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#define BW_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, (HW_IPU_DI0_SW_GEN0_7_RD(x) & ~BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1) | BF_IPU_DI0_SW_GEN0_7_DI0_OFFSET_RESOLUTION_1(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_DI0_SW_GEN0_7, field DI0_OFFSET_VALUE_7[14:3] (RW)
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|
*
|
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* DI0 counter #7 offset value The counter can start counting after a pre defined delay This field
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|
* defines the amount of cycles that the counter will be delayed by
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|
*/
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//@{
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#define BP_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7 (3) //!< Bit position for IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7.
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#define BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7.
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//! @brief Get value of IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7 from a register value.
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#define BG_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7) >> BP_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7.
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#define BF_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7) & BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_OFFSET_VALUE_7 field to a new value.
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#define BW_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, (HW_IPU_DI0_SW_GEN0_7_RD(x) & ~BM_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7) | BF_IPU_DI0_SW_GEN0_7_DI0_OFFSET_VALUE_7(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN0_7, field DI0_RUN_RESOLUTION_7[18:16] (RW)
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*
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* DI0 counter #1 Run Resolution This field defines the trigger causing the counter to increment.
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*
|
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* Values:
|
|
* - 000 - Counter is disabled
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* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
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* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
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* - 100 - The Counter is triggered by counter #3
|
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* - 101 - The Counter is triggered by counter #4
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* - 110 - The Counter is triggered by counter #5
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* - 111 - Counter is always on.
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|
*/
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//@{
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|
#define BP_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7 (16) //!< Bit position for IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7.
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#define BM_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7.
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//! @brief Get value of IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7 from a register value.
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#define BG_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7) >> BP_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7.
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|
#define BF_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7) & BM_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_7 field to a new value.
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|
#define BW_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, (HW_IPU_DI0_SW_GEN0_7_RD(x) & ~BM_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7) | BF_IPU_DI0_SW_GEN0_7_DI0_RUN_RESOLUTION_7(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_DI0_SW_GEN0_7, field DI0_RUN_VALUE_M1_7[30:19] (RW)
|
|
*
|
|
* DI0 counter #7 pre defined value This fields defines the counter #7 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_7 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
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|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7 (19) //!< Bit position for IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7.
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|
#define BM_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7 from a register value.
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|
#define BG_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7) >> BP_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7)
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|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7.
|
|
#define BF_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7) & BM_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7(x, v) (HW_IPU_DI0_SW_GEN0_7_WR(x, (HW_IPU_DI0_SW_GEN0_7_RD(x) & ~BM_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7) | BF_IPU_DI0_SW_GEN0_7_DI0_RUN_VALUE_M1_7(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_8 - DI0 Sync Wave Gen 8 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_8 - DI0 Sync Wave Gen 8 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_8_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_8 : 3; //!< [2:0] DI0 counter #8 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_8 : 12; //!< [14:3] DI0 counter #8 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_8 : 3; //!< [18:16] DI0 counter #8 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_8 : 12; //!< [30:19] DI0 counter #8 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_8_ADDR(x) (REGS_IPU_BASE(x) + 0x40028)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN0_8(x) (*(volatile hw_ipu_di0_sw_gen0_8_t *) HW_IPU_DI0_SW_GEN0_8_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN0_8_RD(x) (HW_IPU_DI0_SW_GEN0_8(x).U)
|
|
#define HW_IPU_DI0_SW_GEN0_8_WR(x, v) (HW_IPU_DI0_SW_GEN0_8(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN0_8_SET(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, HW_IPU_DI0_SW_GEN0_8_RD(x) | (v)))
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|
#define HW_IPU_DI0_SW_GEN0_8_CLR(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, HW_IPU_DI0_SW_GEN0_8_RD(x) & ~(v)))
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|
#define HW_IPU_DI0_SW_GEN0_8_TOG(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, HW_IPU_DI0_SW_GEN0_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN0_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_8, field DI0_OFFSET_RESOLUTION_8[2:0] (RW)
|
|
*
|
|
* DI0 counter #8 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8 (0) //!< Bit position for IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8.
|
|
#define BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8) >> BP_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8.
|
|
#define BF_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8) & BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_RESOLUTION_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, (HW_IPU_DI0_SW_GEN0_8_RD(x) & ~BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8) | BF_IPU_DI0_SW_GEN0_8_DI0_OFFSET_RESOLUTION_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_8, field DI0_OFFSET_VALUE_8[14:3] (RW)
|
|
*
|
|
* DI0 counter #8 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8 (3) //!< Bit position for IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8.
|
|
#define BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8) >> BP_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8.
|
|
#define BF_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8) & BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_OFFSET_VALUE_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, (HW_IPU_DI0_SW_GEN0_8_RD(x) & ~BM_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8) | BF_IPU_DI0_SW_GEN0_8_DI0_OFFSET_VALUE_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_8, field DI0_RUN_RESOLUTION_8[18:16] (RW)
|
|
*
|
|
* DI0 counter #8 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8 (16) //!< Bit position for IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8.
|
|
#define BM_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8) >> BP_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8.
|
|
#define BF_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8) & BM_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_RESOLUTION_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, (HW_IPU_DI0_SW_GEN0_8_RD(x) & ~BM_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8) | BF_IPU_DI0_SW_GEN0_8_DI0_RUN_RESOLUTION_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN0_8, field DI0_RUN_VALUE_M1_8[30:19] (RW)
|
|
*
|
|
* DI0 counter #8 pre defined value This fields defines the counter #8 pre defines value. When the
|
|
* counter is auto reload mode (di0_cnt_auto_reload_8 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di0_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8 (19) //!< Bit position for IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8.
|
|
#define BM_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8) >> BP_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8.
|
|
#define BF_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8) & BM_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_RUN_VALUE_M1_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8(x, v) (HW_IPU_DI0_SW_GEN0_8_WR(x, (HW_IPU_DI0_SW_GEN0_8_RD(x) & ~BM_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8) | BF_IPU_DI0_SW_GEN0_8_DI0_RUN_VALUE_M1_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN0_9 - DI0 Sync Wave Gen 9 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN0_9 - DI0 Sync Wave Gen 9 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen0_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen0_9_bitfields
|
|
{
|
|
unsigned DI0_OFFSET_RESOLUTION_9 : 3; //!< [2:0] DI0 counter #9 offset Resolution
|
|
unsigned DI0_OFFSET_VALUE_9 : 12; //!< [14:3] DI0 counter #9 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned DI0_RUN_RESOLUTION_9 : 3; //!< [18:16] DI0 counter #9 Run Resolution
|
|
unsigned DI0_RUN_VALUE_M1_9 : 12; //!< [30:19] DI0 counter #9 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen0_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN0_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN0_9_ADDR(x) (REGS_IPU_BASE(x) + 0x4002c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_SW_GEN0_9(x) (*(volatile hw_ipu_di0_sw_gen0_9_t *) HW_IPU_DI0_SW_GEN0_9_ADDR(x))
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#define HW_IPU_DI0_SW_GEN0_9_RD(x) (HW_IPU_DI0_SW_GEN0_9(x).U)
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#define HW_IPU_DI0_SW_GEN0_9_WR(x, v) (HW_IPU_DI0_SW_GEN0_9(x).U = (v))
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#define HW_IPU_DI0_SW_GEN0_9_SET(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, HW_IPU_DI0_SW_GEN0_9_RD(x) | (v)))
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#define HW_IPU_DI0_SW_GEN0_9_CLR(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, HW_IPU_DI0_SW_GEN0_9_RD(x) & ~(v)))
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#define HW_IPU_DI0_SW_GEN0_9_TOG(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, HW_IPU_DI0_SW_GEN0_9_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DI0_SW_GEN0_9 bitfields
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*/
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/*! @name Register IPU_DI0_SW_GEN0_9, field DI0_OFFSET_RESOLUTION_9[2:0] (RW)
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*
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* DI0 counter #9 offset Resolution This field defines the trigger causing the offset counter to
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* increment
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*
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* Values:
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* - 000 - Counter is disabled
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* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
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* - 010 - The Counter is triggered by counter #1
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* - 011 - The Counter is triggered by counter #2
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* - 100 - The Counter is triggered by counter #3
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* - 101 - The Counter is triggered by counter #4
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* - 110 - The Counter is triggered by counter #5
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* - 111 - Counter is always on.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9 (0) //!< Bit position for IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9.
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#define BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9 (0x00000007) //!< Bit mask for IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9.
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//! @brief Get value of IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9 from a register value.
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#define BG_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9) >> BP_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9.
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#define BF_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9) & BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_OFFSET_RESOLUTION_9 field to a new value.
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#define BW_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, (HW_IPU_DI0_SW_GEN0_9_RD(x) & ~BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9) | BF_IPU_DI0_SW_GEN0_9_DI0_OFFSET_RESOLUTION_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN0_9, field DI0_OFFSET_VALUE_9[14:3] (RW)
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*
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* DI0 counter #9 offset value The counter can start counting after a pre defined delay This field
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* defines the amount of cycles that the counter will be delayed by
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9 (3) //!< Bit position for IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9.
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#define BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9 (0x00007ff8) //!< Bit mask for IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9.
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//! @brief Get value of IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9 from a register value.
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#define BG_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9) >> BP_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9.
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#define BF_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9) & BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_OFFSET_VALUE_9 field to a new value.
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#define BW_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, (HW_IPU_DI0_SW_GEN0_9_RD(x) & ~BM_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9) | BF_IPU_DI0_SW_GEN0_9_DI0_OFFSET_VALUE_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN0_9, field DI0_RUN_RESOLUTION_9[18:16] (RW)
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*
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* DI0 counter #9 Run Resolution This field defines the trigger causing the counter to increment.
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*
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* Values:
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* - 000 - Counter is disabled
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* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
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* - 010 - The Counter is triggered by counter #1
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* - 011 - The Counter is triggered by counter #2
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* - 100 - The Counter is triggered by counter #3
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* - 101 - The Counter is triggered by counter #4
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* - 110 - The Counter is triggered by counter #5
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* - 111 - Counter is always on.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9 (16) //!< Bit position for IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9.
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#define BM_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9 (0x00070000) //!< Bit mask for IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9.
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//! @brief Get value of IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9 from a register value.
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#define BG_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9) >> BP_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9.
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#define BF_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9) & BM_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_RUN_RESOLUTION_9 field to a new value.
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#define BW_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, (HW_IPU_DI0_SW_GEN0_9_RD(x) & ~BM_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9) | BF_IPU_DI0_SW_GEN0_9_DI0_RUN_RESOLUTION_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN0_9, field DI0_RUN_VALUE_M1_9[30:19] (RW)
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*
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* DI0 counter #9 pre defined value This fields defines the counter #9 pre defines value. When the
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* counter is auto reload mode (di0_cnt_auto_reload_9 bit is set), the counter automatically
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* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
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* di0_step_repeat field.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9 (19) //!< Bit position for IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9.
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#define BM_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9 (0x7ff80000) //!< Bit mask for IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9.
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//! @brief Get value of IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9 from a register value.
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#define BG_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9) >> BP_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9.
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#define BF_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9) & BM_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_RUN_VALUE_M1_9 field to a new value.
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#define BW_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9(x, v) (HW_IPU_DI0_SW_GEN0_9_WR(x, (HW_IPU_DI0_SW_GEN0_9_RD(x) & ~BM_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9) | BF_IPU_DI0_SW_GEN0_9_DI0_RUN_VALUE_M1_9(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_SW_GEN1_1 - DI0 Sync Wave Gen 1 Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI0_SW_GEN1_1 - DI0 Sync Wave Gen 1 Register 1 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di0_sw_gen1_1
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{
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reg32_t U;
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struct _hw_ipu_di0_sw_gen1_1_bitfields
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{
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unsigned DI0_CNT_UP_1 : 9; //!< [8:0] Counter rising edge position
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unsigned DI0_CNT_POLARITY_CLR_SEL_1 : 3; //!< [11:9] DI0 counter's polarity Clear select
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unsigned DI0_CNT_POLARITY_TRIGGER_SEL_1 : 3; //!< [14:12] DI0 Counter's toggling trigger select
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unsigned RESERVED0 : 1; //!< [15] Reserved
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unsigned DI0_CNT_DOWN_1 : 9; //!< [24:16] Counter falling edge position
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unsigned DI0_CNT_CLR_SEL_1 : 3; //!< [27:25] Counter Clear select
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unsigned DI0_CNT_AUTO_RELOAD_1 : 1; //!< [28] Counter auto reload mode
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unsigned DI0_CNT_POLARITY_GEN_EN_1 : 2; //!< [30:29] DI0 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_di0_sw_gen1_1_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DI0_SW_GEN1_1 register
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*/
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//@{
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#define HW_IPU_DI0_SW_GEN1_1_ADDR(x) (REGS_IPU_BASE(x) + 0x40030)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_SW_GEN1_1(x) (*(volatile hw_ipu_di0_sw_gen1_1_t *) HW_IPU_DI0_SW_GEN1_1_ADDR(x))
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#define HW_IPU_DI0_SW_GEN1_1_RD(x) (HW_IPU_DI0_SW_GEN1_1(x).U)
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#define HW_IPU_DI0_SW_GEN1_1_WR(x, v) (HW_IPU_DI0_SW_GEN1_1(x).U = (v))
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#define HW_IPU_DI0_SW_GEN1_1_SET(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, HW_IPU_DI0_SW_GEN1_1_RD(x) | (v)))
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#define HW_IPU_DI0_SW_GEN1_1_CLR(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, HW_IPU_DI0_SW_GEN1_1_RD(x) & ~(v)))
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#define HW_IPU_DI0_SW_GEN1_1_TOG(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, HW_IPU_DI0_SW_GEN1_1_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
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* constants & macros for individual IPU_DI0_SW_GEN1_1 bitfields
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*/
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/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_UP_1[8:0] (RW)
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*
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* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
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* point and the waveform's rising edge.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1 (0) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1.
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#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1.
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//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1 from a register value.
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#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1.
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#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_UP_1 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_UP_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_POLARITY_CLR_SEL_1[11:9] (RW)
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*
|
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* DI0 counter's polarity Clear select This field selects the input to the counter telling the
|
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* counter wether to invert the output
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*
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|
* Values:
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|
* - 000 - Output is always inverted
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* - 001 - Output is kept the same (no inversion)
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* - 010 - Reserved
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* - 011 - Reserved
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* - 100 - Reserved
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* - 101 - Reserved
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* - 110 - Reserved
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* - 111 - Reserved
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1 (9) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1.
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#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1.
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//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1 from a register value.
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#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1.
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#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_1 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_CLR_SEL_1(v)))
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#endif
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|
//@}
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/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_POLARITY_TRIGGER_SEL_1[14:12] (RW)
|
|
*
|
|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
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|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
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|
*/
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|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1 (12) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1.
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#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1.
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|
//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1 from a register value.
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|
#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1)
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|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1.
|
|
#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_TRIGGER_SEL_1(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_DOWN_1[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1 (16) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1.
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#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1.
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//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1 from a register value.
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|
#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1.
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|
#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_DOWN_1 field to a new value.
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|
#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_DOWN_1(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_CLR_SEL_1[27:25] (RW)
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*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
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|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
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* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1 (25) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1.
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#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1.
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//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1 from a register value.
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#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1.
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#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_CLR_SEL_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_CLR_SEL_1(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_AUTO_RELOAD_1[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_1 field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1 (28) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1.
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|
#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1.
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//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1)
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|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1.
|
|
#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_AUTO_RELOAD_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_AUTO_RELOAD_1(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_1, field DI0_CNT_POLARITY_GEN_EN_1[30:29] (RW)
|
|
*
|
|
* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1 (29) //!< Bit position for IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1.
|
|
#define BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1) >> BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1.
|
|
#define BF_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1) & BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_GEN_EN_1 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1(x, v) (HW_IPU_DI0_SW_GEN1_1_WR(x, (HW_IPU_DI0_SW_GEN1_1_RD(x) & ~BM_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1) | BF_IPU_DI0_SW_GEN1_1_DI0_CNT_POLARITY_GEN_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN1_2 - DI0 Sync Wave Gen 2 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN1_2 - DI0 Sync Wave Gen 2 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen1_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen1_2_bitfields
|
|
{
|
|
unsigned DI0_CNT_UP_2 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI0_CNT_POLARITY_CLR_SEL_2 : 3; //!< [11:9] DI0 counter's polarity Clear select
|
|
unsigned DI0_CNT_POLARITY_TRIGGER_SEL_2 : 3; //!< [14:12] DI0 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI0_CNT_DOWN_2 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI0_CNT_CLR_SEL_2 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI0_CNT_AUTO_RELOAD_2 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI0_CNT_POLARITY_GEN_EN_2 : 2; //!< [30:29] DI0 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen1_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN1_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN1_2_ADDR(x) (REGS_IPU_BASE(x) + 0x40034)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN1_2(x) (*(volatile hw_ipu_di0_sw_gen1_2_t *) HW_IPU_DI0_SW_GEN1_2_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN1_2_RD(x) (HW_IPU_DI0_SW_GEN1_2(x).U)
|
|
#define HW_IPU_DI0_SW_GEN1_2_WR(x, v) (HW_IPU_DI0_SW_GEN1_2(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN1_2_SET(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, HW_IPU_DI0_SW_GEN1_2_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN1_2_CLR(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, HW_IPU_DI0_SW_GEN1_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN1_2_TOG(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, HW_IPU_DI0_SW_GEN1_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN1_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_UP_2[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2 (0) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2.
|
|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_UP_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_UP_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_POLARITY_CLR_SEL_2[11:9] (RW)
|
|
*
|
|
* DI0 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2 (9) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2.
|
|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_CLR_SEL_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_POLARITY_TRIGGER_SEL_2[14:12] (RW)
|
|
*
|
|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2 (12) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2.
|
|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_TRIGGER_SEL_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_DOWN_2[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2 (16) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2.
|
|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_DOWN_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_DOWN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_CLR_SEL_2[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2 (25) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2.
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|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2.
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|
|
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//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2)
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|
|
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_CLR_SEL_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_CLR_SEL_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_AUTO_RELOAD_2[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2 (28) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2.
|
|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_AUTO_RELOAD_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_AUTO_RELOAD_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_2, field DI0_CNT_POLARITY_GEN_EN_2[30:29] (RW)
|
|
*
|
|
* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2 (29) //!< Bit position for IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2.
|
|
#define BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2) >> BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2.
|
|
#define BF_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2) & BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_GEN_EN_2 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2(x, v) (HW_IPU_DI0_SW_GEN1_2_WR(x, (HW_IPU_DI0_SW_GEN1_2_RD(x) & ~BM_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2) | BF_IPU_DI0_SW_GEN1_2_DI0_CNT_POLARITY_GEN_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN1_3 - DI0 Sync Wave Gen 3 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN1_3 - DI0 Sync Wave Gen 3 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen1_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen1_3_bitfields
|
|
{
|
|
unsigned DI0_CNT_UP_3 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI0_CNT_POLARITY_CLR_SEL_3 : 3; //!< [11:9] DI0 counter's polarity Clear select
|
|
unsigned DI0_CNT_POLARITY_TRIGGER_SEL_3 : 3; //!< [14:12] DI0 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI0_CNT_DOWN_3 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI0_CNT_CLR_SEL_3 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI0_CNT_AUTO_RELOAD_3 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI0_CNT_POLARITY_GEN_EN_3 : 2; //!< [30:29] DI0 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen1_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN1_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN1_3_ADDR(x) (REGS_IPU_BASE(x) + 0x40038)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN1_3(x) (*(volatile hw_ipu_di0_sw_gen1_3_t *) HW_IPU_DI0_SW_GEN1_3_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN1_3_RD(x) (HW_IPU_DI0_SW_GEN1_3(x).U)
|
|
#define HW_IPU_DI0_SW_GEN1_3_WR(x, v) (HW_IPU_DI0_SW_GEN1_3(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN1_3_SET(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, HW_IPU_DI0_SW_GEN1_3_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN1_3_CLR(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, HW_IPU_DI0_SW_GEN1_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN1_3_TOG(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, HW_IPU_DI0_SW_GEN1_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN1_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_UP_3[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3 (0) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3.
|
|
#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3.
|
|
#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_UP_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_UP_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_POLARITY_CLR_SEL_3[11:9] (RW)
|
|
*
|
|
* DI0 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Reserved
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3 (9) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3.
|
|
#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3.
|
|
#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_CLR_SEL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_POLARITY_TRIGGER_SEL_3[14:12] (RW)
|
|
*
|
|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3 (12) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3.
|
|
#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3.
|
|
#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_TRIGGER_SEL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_DOWN_3[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3 (16) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3.
|
|
#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3.
|
|
#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_DOWN_3 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_DOWN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_CLR_SEL_3[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3 (25) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3.
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#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3.
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//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3 from a register value.
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#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3.
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#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_CLR_SEL_3 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_CLR_SEL_3(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_AUTO_RELOAD_3[28] (RW)
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*
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* Counter auto reload mode
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*
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* Values:
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* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
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* defined on the di0_step_repeat_<i> field
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* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
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* field
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3 (28) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3.
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#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3.
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//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3 from a register value.
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#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3.
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#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_AUTO_RELOAD_3 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_AUTO_RELOAD_3(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_3, field DI0_CNT_POLARITY_GEN_EN_3[30:29] (RW)
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*
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* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
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*
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* Values:
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* - 00 - Dynamic polarity change is disabled
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* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
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* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
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* multiple of 2.
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* - 10 - Dynamic polarity change is enabled
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* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3 (29) //!< Bit position for IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3.
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#define BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3.
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//! @brief Get value of IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3 from a register value.
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#define BG_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3) >> BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3.
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#define BF_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3) & BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_GEN_EN_3 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3(x, v) (HW_IPU_DI0_SW_GEN1_3_WR(x, (HW_IPU_DI0_SW_GEN1_3_RD(x) & ~BM_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3) | BF_IPU_DI0_SW_GEN1_3_DI0_CNT_POLARITY_GEN_EN_3(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_SW_GEN1_4 - DI0 Sync Wave Gen 4 Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI0_SW_GEN1_4 - DI0 Sync Wave Gen 4 Register 1 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di0_sw_gen1_4
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{
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reg32_t U;
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struct _hw_ipu_di0_sw_gen1_4_bitfields
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{
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unsigned DI0_CNT_UP_4 : 9; //!< [8:0] Counter rising edge position
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unsigned DI0_CNT_POLARITY_CLR_SEL_4 : 3; //!< [11:9] DI0 counter's polarity Clear select
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unsigned DI0_CNT_POLARITY_TRIGGER_SEL_4 : 3; //!< [14:12] DI0 Counter's toggling trigger select
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unsigned RESERVED0 : 1; //!< [15] Reserved
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unsigned DI0_CNT_DOWN_4 : 9; //!< [24:16] Counter falling edge position
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unsigned DI0_CNT_CLR_SEL_4 : 3; //!< [27:25] Counter Clear select
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unsigned DI0_CNT_AUTO_RELOAD_4 : 1; //!< [28] Counter auto reload mode
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unsigned DI0_CNT_POLARITY_GEN_EN_4 : 2; //!< [30:29] DI0 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_di0_sw_gen1_4_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DI0_SW_GEN1_4 register
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*/
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//@{
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#define HW_IPU_DI0_SW_GEN1_4_ADDR(x) (REGS_IPU_BASE(x) + 0x4003c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_SW_GEN1_4(x) (*(volatile hw_ipu_di0_sw_gen1_4_t *) HW_IPU_DI0_SW_GEN1_4_ADDR(x))
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#define HW_IPU_DI0_SW_GEN1_4_RD(x) (HW_IPU_DI0_SW_GEN1_4(x).U)
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#define HW_IPU_DI0_SW_GEN1_4_WR(x, v) (HW_IPU_DI0_SW_GEN1_4(x).U = (v))
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#define HW_IPU_DI0_SW_GEN1_4_SET(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, HW_IPU_DI0_SW_GEN1_4_RD(x) | (v)))
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#define HW_IPU_DI0_SW_GEN1_4_CLR(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, HW_IPU_DI0_SW_GEN1_4_RD(x) & ~(v)))
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#define HW_IPU_DI0_SW_GEN1_4_TOG(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, HW_IPU_DI0_SW_GEN1_4_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DI0_SW_GEN1_4 bitfields
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*/
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/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_UP_4[8:0] (RW)
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*
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* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
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* point and the waveform's rising edge.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4 (0) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4.
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#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4.
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//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4 from a register value.
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#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4.
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#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_UP_4 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_UP_4(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_POLARITY_CLR_SEL_4[11:9] (RW)
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*
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* DI0 counter's polarity Clear select This field selects the input to the counter telling the
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* counter wether to invert the output
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*
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|
* Values:
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|
* - 000 - Output is always inverted
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* - 001 - Output is kept the same (no inversion)
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* - 010 - Output is inverted if the output of counter #1 is set
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* - 011 - Output is inverted if the output of counter #2 is set
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* - 100 - Output is inverted if the output of counter #3 is set
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* - 101 - Reserved
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* - 110 - Reserved
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* - 111 - Reserved
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4 (9) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4.
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#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4.
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//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4 from a register value.
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#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4.
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#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_4 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_CLR_SEL_4(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_POLARITY_TRIGGER_SEL_4[14:12] (RW)
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*
|
|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
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* to toggle
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|
*
|
|
* Values:
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|
* - 000 - Counter is disabled
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* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
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|
* - 010 - The Counter is triggered by counter #1
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|
* - 011 - The Counter is triggered by counter #2
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|
* - 100 - The Counter is triggered by counter #3
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|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
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* - 110 - External VSYNC
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|
* - 111 - Counter is always on.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4 (12) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4.
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#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4.
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//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4 from a register value.
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#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4.
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#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_4 field to a new value.
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|
#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_TRIGGER_SEL_4(v)))
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#endif
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|
//@}
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/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_DOWN_4[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
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|
//@{
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|
#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4 (16) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4.
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|
#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4 from a register value.
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|
#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4.
|
|
#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_DOWN_4 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_DOWN_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_CLR_SEL_4[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4 (25) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4.
|
|
#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4.
|
|
#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4)
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|
|
|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_CLR_SEL_4 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_CLR_SEL_4(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_AUTO_RELOAD_4[28] (RW)
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*
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* Counter auto reload mode
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|
*
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* Values:
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|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
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|
* defined on the di0_step_repeat_<i> field
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* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
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* field
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4 (28) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4.
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#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4.
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//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4 from a register value.
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#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4.
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#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_AUTO_RELOAD_4 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_AUTO_RELOAD_4(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_4, field DI0_CNT_POLARITY_GEN_EN_4[30:29] (RW)
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*
|
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* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
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*
|
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* Values:
|
|
* - 00 - Dynamic polarity change is disabled
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* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
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* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
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* multiple of 2.
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* - 10 - Dynamic polarity change is enabled
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* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4 (29) //!< Bit position for IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4.
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#define BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4.
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//! @brief Get value of IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4 from a register value.
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#define BG_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4) >> BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4.
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#define BF_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4) & BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_GEN_EN_4 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4(x, v) (HW_IPU_DI0_SW_GEN1_4_WR(x, (HW_IPU_DI0_SW_GEN1_4_RD(x) & ~BM_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4) | BF_IPU_DI0_SW_GEN1_4_DI0_CNT_POLARITY_GEN_EN_4(v)))
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#endif
|
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//@}
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN1_5 - DI0 Sync Wave Gen 5 Register 1
|
|
//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN1_5 - DI0 Sync Wave Gen 5 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen1_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen1_5_bitfields
|
|
{
|
|
unsigned DI0_CNT_UP_5 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI0_CNT_POLARITY_CLR_SEL_5 : 3; //!< [11:9] DI0 counter's polarity Clear select
|
|
unsigned DI0_CNT_POLARITY_TRIGGER_SEL_5 : 3; //!< [14:12] DI0 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI0_CNT_DOWN_5 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI0_CNT_CLR_SEL_5 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI0_CNT_AUTO_RELOAD_5 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI0_CNT_POLARITY_GEN_EN_5 : 2; //!< [30:29] DI0 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen1_5_t;
|
|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN1_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN1_5_ADDR(x) (REGS_IPU_BASE(x) + 0x40040)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN1_5(x) (*(volatile hw_ipu_di0_sw_gen1_5_t *) HW_IPU_DI0_SW_GEN1_5_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN1_5_RD(x) (HW_IPU_DI0_SW_GEN1_5(x).U)
|
|
#define HW_IPU_DI0_SW_GEN1_5_WR(x, v) (HW_IPU_DI0_SW_GEN1_5(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN1_5_SET(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, HW_IPU_DI0_SW_GEN1_5_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN1_5_CLR(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, HW_IPU_DI0_SW_GEN1_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN1_5_TOG(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, HW_IPU_DI0_SW_GEN1_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN1_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_UP_5[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5 (0) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5.
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|
#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5.
|
|
#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_UP_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_UP_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_POLARITY_CLR_SEL_5[11:9] (RW)
|
|
*
|
|
* DI0 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Output is inverted if the output of counter #4 is set
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5 (9) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5.
|
|
#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5.
|
|
#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_CLR_SEL_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_POLARITY_TRIGGER_SEL_5[14:12] (RW)
|
|
*
|
|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5 (12) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5.
|
|
#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5.
|
|
#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_TRIGGER_SEL_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_DOWN_5[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5 (16) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5.
|
|
#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5.
|
|
#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_DOWN_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_DOWN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_CLR_SEL_5[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5 (25) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5.
|
|
#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5.
|
|
#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_CLR_SEL_5 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_CLR_SEL_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_AUTO_RELOAD_5[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5 (28) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5.
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|
#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5.
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//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5 from a register value.
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#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5.
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#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_AUTO_RELOAD_5 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_AUTO_RELOAD_5(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_5, field DI0_CNT_POLARITY_GEN_EN_5[30:29] (RW)
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*
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* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
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*
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* Values:
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* - 00 - Dynamic polarity change is disabled
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* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
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* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
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* multiple of 2.
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* - 10 - Dynamic polarity change is enabled
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* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5 (29) //!< Bit position for IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5.
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#define BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5.
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//! @brief Get value of IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5 from a register value.
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#define BG_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5) >> BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5.
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#define BF_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5) & BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_GEN_EN_5 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5(x, v) (HW_IPU_DI0_SW_GEN1_5_WR(x, (HW_IPU_DI0_SW_GEN1_5_RD(x) & ~BM_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5) | BF_IPU_DI0_SW_GEN1_5_DI0_CNT_POLARITY_GEN_EN_5(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_SW_GEN1_6 - DI0 Sync Wave Gen 6 Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI0_SW_GEN1_6 - DI0 Sync Wave Gen 6 Register 1 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di0_sw_gen1_6
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{
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reg32_t U;
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struct _hw_ipu_di0_sw_gen1_6_bitfields
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{
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unsigned DI0_CNT_UP_6 : 9; //!< [8:0] Counter rising edge position
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unsigned DI0_CNT_POLARITY_CLR_SEL_6 : 3; //!< [11:9] DI0 counter's polarity Clear select
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unsigned DI0_CNT_POLARITY_TRIGGER_SEL_6 : 3; //!< [14:12] DI0 Counter's toggling trigger select
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unsigned RESERVED0 : 1; //!< [15] Reserved
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unsigned DI0_CNT_DOWN_6 : 9; //!< [24:16] Counter falling edge position
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unsigned DI0_CNT_CLR_SEL_6 : 3; //!< [27:25] Counter Clear select
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unsigned DI0_CNT_AUTO_RELOAD_6 : 1; //!< [28] Counter auto reload mode
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unsigned DI0_CNT_POLARITY_GEN_EN_6 : 2; //!< [30:29] DI0 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_di0_sw_gen1_6_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DI0_SW_GEN1_6 register
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*/
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//@{
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#define HW_IPU_DI0_SW_GEN1_6_ADDR(x) (REGS_IPU_BASE(x) + 0x40044)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_SW_GEN1_6(x) (*(volatile hw_ipu_di0_sw_gen1_6_t *) HW_IPU_DI0_SW_GEN1_6_ADDR(x))
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#define HW_IPU_DI0_SW_GEN1_6_RD(x) (HW_IPU_DI0_SW_GEN1_6(x).U)
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#define HW_IPU_DI0_SW_GEN1_6_WR(x, v) (HW_IPU_DI0_SW_GEN1_6(x).U = (v))
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#define HW_IPU_DI0_SW_GEN1_6_SET(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, HW_IPU_DI0_SW_GEN1_6_RD(x) | (v)))
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#define HW_IPU_DI0_SW_GEN1_6_CLR(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, HW_IPU_DI0_SW_GEN1_6_RD(x) & ~(v)))
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#define HW_IPU_DI0_SW_GEN1_6_TOG(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, HW_IPU_DI0_SW_GEN1_6_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DI0_SW_GEN1_6 bitfields
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*/
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/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_UP_6[8:0] (RW)
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*
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* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
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* point and the waveform's rising edge.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6 (0) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6.
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#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6.
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//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6 from a register value.
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#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6.
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#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_UP_6 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_UP_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_POLARITY_CLR_SEL_6[11:9] (RW)
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*
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* DI0 counter's polarity Clear select This field selects the input to the counter telling the
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|
* counter wether to invert the output
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*
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|
* Values:
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|
* - 000 - Output is always inverted
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* - 001 - Output is kept the same (no inversion)
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* - 010 - Output is inverted if the output of counter #1 is set
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* - 011 - Output is inverted if the output of counter #2 is set
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* - 100 - Output is inverted if the output of counter #3 is set
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* - 101 - Output is inverted if the output of counter #4 is set
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* - 110 - Output is inverted if the output of counter #5 is set
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* - 111 - Reserved
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6 (9) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6.
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#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6.
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//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6 from a register value.
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#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6.
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#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6)
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|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_6 field to a new value.
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|
#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_CLR_SEL_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_POLARITY_TRIGGER_SEL_6[14:12] (RW)
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|
*
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|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
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|
*
|
|
* Values:
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|
* - 000 - Counter is disabled
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|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
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|
* - 010 - The Counter is triggered by counter #1
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|
* - 011 - The Counter is triggered by counter #2
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* - 100 - The Counter is triggered by counter #3
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|
* - 101 - The Counter is triggered by counter #4
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* - 110 - The Counter is triggered by counter #5
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* - 111 - Counter is always on.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6 (12) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6.
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#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6.
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//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6 from a register value.
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#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6.
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#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_6 field to a new value.
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|
#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_TRIGGER_SEL_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_DOWN_6[24:16] (RW)
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|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
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|
//@{
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|
#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6 (16) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6.
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|
#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6.
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//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6 from a register value.
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|
#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6)
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|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6.
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|
#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_DOWN_6 field to a new value.
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|
#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_DOWN_6(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_CLR_SEL_6[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6 (25) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6.
|
|
#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6.
|
|
#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_CLR_SEL_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_CLR_SEL_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_AUTO_RELOAD_6[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6 (28) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6.
|
|
#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6.
|
|
#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_AUTO_RELOAD_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_AUTO_RELOAD_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_6, field DI0_CNT_POLARITY_GEN_EN_6[30:29] (RW)
|
|
*
|
|
* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6 (29) //!< Bit position for IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6.
|
|
#define BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6) >> BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6.
|
|
#define BF_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6) & BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_GEN_EN_6 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6(x, v) (HW_IPU_DI0_SW_GEN1_6_WR(x, (HW_IPU_DI0_SW_GEN1_6_RD(x) & ~BM_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6) | BF_IPU_DI0_SW_GEN1_6_DI0_CNT_POLARITY_GEN_EN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SW_GEN1_7 - DI0 Sync Wave Gen 7 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN1_7 - DI0 Sync Wave Gen 7 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sw_gen1_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sw_gen1_7_bitfields
|
|
{
|
|
unsigned DI0_CNT_UP_7 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI0_CNT_POLARITY_CLR_SEL_7 : 3; //!< [11:9] DI0 counter's polarity Clear select
|
|
unsigned DI0_CNT_POLARITY_TRIGGER_SEL_7 : 3; //!< [14:12] DI0 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI0_CNT_DOWN_7 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI0_CNT_CLR_SEL_7 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI0_CNT_AUTO_RELOAD_7 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI0_CNT_POLARITY_GEN_EN_7 : 2; //!< [30:29] DI0 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_sw_gen1_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN1_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SW_GEN1_7_ADDR(x) (REGS_IPU_BASE(x) + 0x40048)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SW_GEN1_7(x) (*(volatile hw_ipu_di0_sw_gen1_7_t *) HW_IPU_DI0_SW_GEN1_7_ADDR(x))
|
|
#define HW_IPU_DI0_SW_GEN1_7_RD(x) (HW_IPU_DI0_SW_GEN1_7(x).U)
|
|
#define HW_IPU_DI0_SW_GEN1_7_WR(x, v) (HW_IPU_DI0_SW_GEN1_7(x).U = (v))
|
|
#define HW_IPU_DI0_SW_GEN1_7_SET(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, HW_IPU_DI0_SW_GEN1_7_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SW_GEN1_7_CLR(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, HW_IPU_DI0_SW_GEN1_7_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SW_GEN1_7_TOG(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, HW_IPU_DI0_SW_GEN1_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN1_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_UP_7[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7 (0) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7.
|
|
#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7.
|
|
#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_UP_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_UP_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_POLARITY_CLR_SEL_7[11:9] (RW)
|
|
*
|
|
* DI0 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Output is inverted if the output of counter #4 is set
|
|
* - 110 - Output is inverted if the output of counter #5 is set
|
|
* - 111 - Output is inverted if the output of counter #6 is set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7 (9) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7.
|
|
#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7.
|
|
#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_CLR_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_POLARITY_TRIGGER_SEL_7[14:12] (RW)
|
|
*
|
|
* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7 (12) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7.
|
|
#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7.
|
|
#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_TRIGGER_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_DOWN_7[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7 (16) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7.
|
|
#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7.
|
|
#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_DOWN_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_DOWN_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_CLR_SEL_7[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7 (25) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7.
|
|
#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7.
|
|
#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_CLR_SEL_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_CLR_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_AUTO_RELOAD_7[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7 (28) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7.
|
|
#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7.
|
|
#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_AUTO_RELOAD_7 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_AUTO_RELOAD_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_7, field DI0_CNT_POLARITY_GEN_EN_7[30:29] (RW)
|
|
*
|
|
* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7 (29) //!< Bit position for IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7.
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#define BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7.
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//! @brief Get value of IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7 from a register value.
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#define BG_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7) >> BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7.
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#define BF_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7) & BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_GEN_EN_7 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7(x, v) (HW_IPU_DI0_SW_GEN1_7_WR(x, (HW_IPU_DI0_SW_GEN1_7_RD(x) & ~BM_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7) | BF_IPU_DI0_SW_GEN1_7_DI0_CNT_POLARITY_GEN_EN_7(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_SW_GEN1_8 - DI0 Sync Wave Gen 8 Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI0_SW_GEN1_8 - DI0 Sync Wave Gen 8 Register 1 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di0_sw_gen1_8
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{
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reg32_t U;
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struct _hw_ipu_di0_sw_gen1_8_bitfields
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{
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unsigned DI0_CNT_UP_8 : 9; //!< [8:0] Counter rising edge position
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unsigned DI0_CNT_POLARITY_CLR_SEL_8 : 3; //!< [11:9] DI0 counter's polarity Clear select
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unsigned DI0_CNT_POLARITY_TRIGGER_SEL_8 : 3; //!< [14:12] DI0 Counter's toggling trigger select
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unsigned RESERVED0 : 1; //!< [15] Reserved
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unsigned DI0_CNT_DOWN_8 : 9; //!< [24:16] Counter falling edge position
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unsigned DI0_CNT_CLR_SEL_8 : 3; //!< [27:25] Counter Clear select
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unsigned DI0_CNT_AUTO_RELOAD_8 : 1; //!< [28] Counter auto reload mode
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unsigned DI0_CNT_POLARITY_GEN_EN_8 : 2; //!< [30:29] DI0 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_di0_sw_gen1_8_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DI0_SW_GEN1_8 register
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*/
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//@{
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#define HW_IPU_DI0_SW_GEN1_8_ADDR(x) (REGS_IPU_BASE(x) + 0x4004c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_SW_GEN1_8(x) (*(volatile hw_ipu_di0_sw_gen1_8_t *) HW_IPU_DI0_SW_GEN1_8_ADDR(x))
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#define HW_IPU_DI0_SW_GEN1_8_RD(x) (HW_IPU_DI0_SW_GEN1_8(x).U)
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#define HW_IPU_DI0_SW_GEN1_8_WR(x, v) (HW_IPU_DI0_SW_GEN1_8(x).U = (v))
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#define HW_IPU_DI0_SW_GEN1_8_SET(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, HW_IPU_DI0_SW_GEN1_8_RD(x) | (v)))
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#define HW_IPU_DI0_SW_GEN1_8_CLR(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, HW_IPU_DI0_SW_GEN1_8_RD(x) & ~(v)))
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#define HW_IPU_DI0_SW_GEN1_8_TOG(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, HW_IPU_DI0_SW_GEN1_8_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DI0_SW_GEN1_8 bitfields
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*/
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/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_UP_8[8:0] (RW)
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*
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* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
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* point and the waveform's rising edge.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8 (0) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8.
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#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8.
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//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8 from a register value.
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#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8.
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#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_UP_8 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_UP_8(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_POLARITY_CLR_SEL_8[11:9] (RW)
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*
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* DI0 counter's polarity Clear select This field selects the input to the counter telling the
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* counter wether to invert the output
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*
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* Values:
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* - 000 - Output is always inverted
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* - 001 - Output is kept the same (no inversion)
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* - 010 - Output is inverted if the output of counter #1 is set
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* - 011 - Output is inverted if the output of counter #2 is set
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* - 100 - Output is inverted if the output of counter #3 is set
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* - 101 - Output is inverted if the output of counter #4 is set
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* - 110 - Output is inverted if the output of counter #5 is set
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* - 111 - Output is inverted if the output of counter #6 is set
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8 (9) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8.
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#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8 (0x00000e00) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8.
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//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8 from a register value.
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#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8.
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#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_CLR_SEL_8 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_CLR_SEL_8(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_POLARITY_TRIGGER_SEL_8[14:12] (RW)
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*
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* DI0 Counter's toggling trigger select This field selects the counter's trigger causing the output
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* to toggle
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*
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* Values:
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* - 000 - Counter is disabled
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* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
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* - 010 - The Counter is triggered by counter #1
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* - 011 - The Counter is triggered by counter #2
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* - 100 - The Counter is triggered by counter #3
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* - 101 - The Counter is triggered by counter #4
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* - 110 - The Counter is triggered by counter #5
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* - 111 - Counter is always on.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8 (12) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8.
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#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8 (0x00007000) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8.
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//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8 from a register value.
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#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8.
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#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_CNT_POLARITY_TRIGGER_SEL_8 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_TRIGGER_SEL_8(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_DOWN_8[24:16] (RW)
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*
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* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
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* point and the waveform's falling edge.
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*/
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//@{
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#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8 (16) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8.
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#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8.
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//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8 from a register value.
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#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8.
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#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_DOWN_8 field to a new value.
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#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_DOWN_8(v)))
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#endif
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|
//@}
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/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_CLR_SEL_8[27:25] (RW)
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|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
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|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
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|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
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|
*/
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|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8 (25) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8.
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#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8.
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//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8 from a register value.
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|
#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8)
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8.
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|
#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CNT_CLR_SEL_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_CLR_SEL_8(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_AUTO_RELOAD_8[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8 (28) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8.
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|
#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8.
|
|
#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_AUTO_RELOAD_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_AUTO_RELOAD_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_8, field DI0_CNT_POLARITY_GEN_EN_8[30:29] (RW)
|
|
*
|
|
* DI0 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8 (29) //!< Bit position for IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8.
|
|
#define BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8 (0x60000000) //!< Bit mask for IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8) >> BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8.
|
|
#define BF_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8) & BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8)
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|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_POLARITY_GEN_EN_8 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8(x, v) (HW_IPU_DI0_SW_GEN1_8_WR(x, (HW_IPU_DI0_SW_GEN1_8_RD(x) & ~BM_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8) | BF_IPU_DI0_SW_GEN1_8_DI0_CNT_POLARITY_GEN_EN_8(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_SW_GEN1_9 - DI0 Sync Wave Gen 9 Register 1
|
|
//-------------------------------------------------------------------------------------------
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|
|
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#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SW_GEN1_9 - DI0 Sync Wave Gen 9 Register 1 (RW)
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|
*
|
|
* Reset value: 0x00000000
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|
*/
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|
typedef union _hw_ipu_di0_sw_gen1_9
|
|
{
|
|
reg32_t U;
|
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struct _hw_ipu_di0_sw_gen1_9_bitfields
|
|
{
|
|
unsigned DI0_CNT_UP_9 : 9; //!< [8:0] Counter rising edge position
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unsigned RESERVED0 : 6; //!< [14:9] Reserved
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|
unsigned DI0_TAG_SEL_9 : 1; //!< [15] Counter #9 can send a synchronous tag when counter #9 reach its predefined value or when it's triggering counter reaches its pre defined value.
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unsigned DI0_CNT_DOWN_9 : 9; //!< [24:16] Counter falling edge position
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unsigned DI0_CNT_CLR_SEL_9 : 3; //!< [27:25] Counter Clear select
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unsigned DI0_CNT_AUTO_RELOAD_9 : 1; //!< [28] Counter auto reload mode
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unsigned DI0_GENTIME_SEL_9 : 3; //!< [31:29] Counter #9 main waveform select
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} B;
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} hw_ipu_di0_sw_gen1_9_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DI0_SW_GEN1_9 register
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|
*/
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//@{
|
|
#define HW_IPU_DI0_SW_GEN1_9_ADDR(x) (REGS_IPU_BASE(x) + 0x40050)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_SW_GEN1_9(x) (*(volatile hw_ipu_di0_sw_gen1_9_t *) HW_IPU_DI0_SW_GEN1_9_ADDR(x))
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#define HW_IPU_DI0_SW_GEN1_9_RD(x) (HW_IPU_DI0_SW_GEN1_9(x).U)
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#define HW_IPU_DI0_SW_GEN1_9_WR(x, v) (HW_IPU_DI0_SW_GEN1_9(x).U = (v))
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#define HW_IPU_DI0_SW_GEN1_9_SET(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, HW_IPU_DI0_SW_GEN1_9_RD(x) | (v)))
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#define HW_IPU_DI0_SW_GEN1_9_CLR(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, HW_IPU_DI0_SW_GEN1_9_RD(x) & ~(v)))
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#define HW_IPU_DI0_SW_GEN1_9_TOG(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, HW_IPU_DI0_SW_GEN1_9_RD(x) ^ (v)))
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#endif
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//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SW_GEN1_9 bitfields
|
|
*/
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/*! @name Register IPU_DI0_SW_GEN1_9, field DI0_CNT_UP_9[8:0] (RW)
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|
*
|
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* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
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|
* point and the waveform's rising edge.
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9 (0) //!< Bit position for IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9.
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#define BM_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9 (0x000001ff) //!< Bit mask for IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9.
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|
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//! @brief Get value of IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9) >> BP_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9)
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|
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//! @brief Format value for bitfield IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9.
|
|
#define BF_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_UP_9 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, (HW_IPU_DI0_SW_GEN1_9_RD(x) & ~BM_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9) | BF_IPU_DI0_SW_GEN1_9_DI0_CNT_UP_9(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DI0_SW_GEN1_9, field DI0_TAG_SEL_9[15] (RW)
|
|
*
|
|
* Counter #9 can send a synchronous tag when counter #9 reach its predefined value or when it's
|
|
* triggering counter reaches its pre defined value.
|
|
*
|
|
* Values:
|
|
* - 0 - Tag's source is the triggering counter.
|
|
* - 1 - tag source is counter #9
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9 (15) //!< Bit position for IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9.
|
|
#define BM_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9 (0x00008000) //!< Bit mask for IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9) >> BP_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9.
|
|
#define BF_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9) & BM_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_TAG_SEL_9 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, (HW_IPU_DI0_SW_GEN1_9_RD(x) & ~BM_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9) | BF_IPU_DI0_SW_GEN1_9_DI0_TAG_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_9, field DI0_CNT_DOWN_9[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9 (16) //!< Bit position for IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9.
|
|
#define BM_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9 (0x01ff0000) //!< Bit mask for IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9.
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|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9) >> BP_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9.
|
|
#define BF_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_DOWN_9 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, (HW_IPU_DI0_SW_GEN1_9_RD(x) & ~BM_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9) | BF_IPU_DI0_SW_GEN1_9_DI0_CNT_DOWN_9(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_9, field DI0_CNT_CLR_SEL_9[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9 (25) //!< Bit position for IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9.
|
|
#define BM_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9 (0x0e000000) //!< Bit mask for IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9) >> BP_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9.
|
|
#define BF_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_CLR_SEL_9 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, (HW_IPU_DI0_SW_GEN1_9_RD(x) & ~BM_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9) | BF_IPU_DI0_SW_GEN1_9_DI0_CNT_CLR_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_9, field DI0_CNT_AUTO_RELOAD_9[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di0_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9 (28) //!< Bit position for IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9.
|
|
#define BM_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9 (0x10000000) //!< Bit mask for IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9) >> BP_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9.
|
|
#define BF_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9) & BM_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CNT_AUTO_RELOAD_9 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, (HW_IPU_DI0_SW_GEN1_9_RD(x) & ~BM_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9) | BF_IPU_DI0_SW_GEN1_9_DI0_CNT_AUTO_RELOAD_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SW_GEN1_9, field DI0_GENTIME_SEL_9[31:29] (RW)
|
|
*
|
|
* Counter #9 main waveform select This field defines the counter that counter #9's auxiliary
|
|
* waveform will be attached too.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter #9's waveform is attached to counter #1's waveform
|
|
* - 001 - Counter #9's waveform is attached to counter #2's waveform
|
|
* - 010 - Counter #9's waveform is attached to counter #3's waveform
|
|
* - 011 - Counter #9's waveform is attached to counter #4's waveform
|
|
* - 100 - Counter #9's waveform is attached to counter #5's waveform
|
|
* - 101 - Counter #9's waveform is attached to counter #6's waveform
|
|
* - 110 - Counter #9's waveform is attached to counter #7's waveform
|
|
* - 111 - Counter #9's waveform is attached to counter #8's waveform
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9 (29) //!< Bit position for IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9.
|
|
#define BM_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9 (0xe0000000) //!< Bit mask for IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9.
|
|
|
|
//! @brief Get value of IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9 from a register value.
|
|
#define BG_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9) >> BP_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9.
|
|
#define BF_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9) & BM_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_GENTIME_SEL_9 field to a new value.
|
|
#define BW_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9(x, v) (HW_IPU_DI0_SW_GEN1_9_WR(x, (HW_IPU_DI0_SW_GEN1_9_RD(x) & ~BM_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9) | BF_IPU_DI0_SW_GEN1_9_DI0_GENTIME_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SYNC_AS_GEN - DI0 Sync Assistance Gen Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SYNC_AS_GEN - DI0 Sync Assistance Gen Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_sync_as_gen
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_sync_as_gen_bitfields
|
|
{
|
|
unsigned DI0_SYNC_START : 12; //!< [11:0] DI0 Sync start
|
|
unsigned RESERVED0 : 1; //!< [12] Reserved.
|
|
unsigned DI0_VSYNC_SEL : 3; //!< [15:13] VSYNC select
|
|
unsigned RESERVED1 : 12; //!< [27:16] Reserved
|
|
unsigned DI0_SYNC_START_EN : 1; //!< [28] di0_sync_start_en
|
|
unsigned RESERVED2 : 3; //!< [31:29] Reserved
|
|
} B;
|
|
} hw_ipu_di0_sync_as_gen_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SYNC_AS_GEN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SYNC_AS_GEN_ADDR(x) (REGS_IPU_BASE(x) + 0x40054)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SYNC_AS_GEN(x) (*(volatile hw_ipu_di0_sync_as_gen_t *) HW_IPU_DI0_SYNC_AS_GEN_ADDR(x))
|
|
#define HW_IPU_DI0_SYNC_AS_GEN_RD(x) (HW_IPU_DI0_SYNC_AS_GEN(x).U)
|
|
#define HW_IPU_DI0_SYNC_AS_GEN_WR(x, v) (HW_IPU_DI0_SYNC_AS_GEN(x).U = (v))
|
|
#define HW_IPU_DI0_SYNC_AS_GEN_SET(x, v) (HW_IPU_DI0_SYNC_AS_GEN_WR(x, HW_IPU_DI0_SYNC_AS_GEN_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SYNC_AS_GEN_CLR(x, v) (HW_IPU_DI0_SYNC_AS_GEN_WR(x, HW_IPU_DI0_SYNC_AS_GEN_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SYNC_AS_GEN_TOG(x, v) (HW_IPU_DI0_SYNC_AS_GEN_WR(x, HW_IPU_DI0_SYNC_AS_GEN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SYNC_AS_GEN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SYNC_AS_GEN, field DI0_SYNC_START[11:0] (RW)
|
|
*
|
|
* DI0 Sync start This field defines the number of low (including blanking rows) on the which the
|
|
* DI0 starts preparing the data for the next frame.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START (0) //!< Bit position for IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START.
|
|
#define BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START (0x00000fff) //!< Bit mask for IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START.
|
|
|
|
//! @brief Get value of IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START from a register value.
|
|
#define BG_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START) >> BP_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START.
|
|
#define BF_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START) & BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_SYNC_START field to a new value.
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|
#define BW_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START(x, v) (HW_IPU_DI0_SYNC_AS_GEN_WR(x, (HW_IPU_DI0_SYNC_AS_GEN_RD(x) & ~BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START) | BF_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SYNC_AS_GEN, field DI0_VSYNC_SEL[15:13] (RW)
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*
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|
* VSYNC select This field defines which of the counters functions as VSYNC signal
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|
*
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|
* Values:
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|
* - 000 - VSYNC is coming from counter #1
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* - 001 - VSYNC is coming from counter #2
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|
* - 111 - VSYNC is coming from counter #8
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|
*/
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|
//@{
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#define BP_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL (13) //!< Bit position for IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL.
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#define BM_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL (0x0000e000) //!< Bit mask for IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL.
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//! @brief Get value of IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL from a register value.
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#define BG_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL) >> BP_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL)
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//! @brief Format value for bitfield IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL.
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#define BF_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL) & BM_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_VSYNC_SEL field to a new value.
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#define BW_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL(x, v) (HW_IPU_DI0_SYNC_AS_GEN_WR(x, (HW_IPU_DI0_SYNC_AS_GEN_RD(x) & ~BM_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL) | BF_IPU_DI0_SYNC_AS_GEN_DI0_VSYNC_SEL(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SYNC_AS_GEN, field DI0_SYNC_START_EN[28] (RW)
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*
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* di0_sync_start_en
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*/
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//@{
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#define BP_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN (28) //!< Bit position for IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN.
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#define BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN (0x10000000) //!< Bit mask for IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN.
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//! @brief Get value of IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN from a register value.
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#define BG_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN) >> BP_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN)
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//! @brief Format value for bitfield IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN.
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|
#define BF_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN) & BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SYNC_START_EN field to a new value.
|
|
#define BW_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN(x, v) (HW_IPU_DI0_SYNC_AS_GEN_WR(x, (HW_IPU_DI0_SYNC_AS_GEN_RD(x) & ~BM_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN) | BF_IPU_DI0_SYNC_AS_GEN_DI0_SYNC_START_EN(v)))
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#endif
|
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//@}
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//-------------------------------------------------------------------------------------------
|
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// HW_IPU_DI0_DW_GEN_I - DI0 Data Wave Gen <i> Register
|
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//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_DW_GEN_I - DI0 Data Wave Gen <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The DI0_DW_GEN_<i> register holds pointers for the waveform generators. These registers have
|
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* different bit arrangements for parallel and serial display. When using a parallel display VDI
|
|
* Plane Size Register 4 is applicable. When using a serial interface VDI Plane Size Register 4 is
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|
* applicable. Register Field Descriptions for Serial Display Field Description 31-24
|
|
* di0_serial_period_<i> DI0 Serial Period <i> This field defines the period of the time base serial
|
|
* display clock. The units are the internal DI clock 23-16 di0_start_period_<i> DI0 start period
|
|
* This field defines the amount of cycles between the point where the access is ready to be
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|
* launched to the actual point where the time base serial display clock restarts. The units are the
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|
* internal DI clock 15-14 di0_cst_<i> DI0 Chip Select pointer for waveform <i> This field points to
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|
* a register that defines the waveform of the CS pin. For serial displays the down value as defined
|
|
* on DI0_DW_SET*_<i> is measured from the assertion of the last serial display time base clock. 00
|
|
* The waveform is defined according to the settings on DI0_DW_SET0_<i> 01 The waveform is defined
|
|
* according to the settings on DI0_DW_SET1_<i> 10 The waveform is defined according to the settings
|
|
* on DI0_DW_SET2_<i> 11 The waveform is defined according to the settings on DI0_DW_SET3_<i> 13-9
|
|
* Reserved 8-4 di0_serial_valid_bits<i> DI0 Serial valid bits. This field defines the amount of
|
|
* valid bits to be transmitted within the 32 bits internal word aligned to bit[0]. The actual
|
|
* amount of valid bits is di0_serial_valid_bits_<i> + 1 3-2 di0_serial_rs_<i> DI0 Serial RS This
|
|
* field points to a register that defines the waveform of the RS pin. For serial displays the down
|
|
* value as defined on DI0_DW_SET*_<i> is measured from the assertion of the last serial display
|
|
* time base clock. 00 The waveform is defined according to the settings on DI0_DW_SET0_<i> 01 The
|
|
* waveform is defined according to the settings on DI0_DW_SET1_<i> 10 The waveform is defined
|
|
* according to the settings on DI0_DW_SET2_<i> 11 The waveform is defined according to the settings
|
|
* on DI0_DW_SET3_<i> 1-0 di0_serial_clk_<i> DI0 serial clock<i> This field points to a register
|
|
* that defines the waveform of the Serial clock pin. 00 The waveform is defined according to the
|
|
* settings on DI0_DW_SET0_<i> 01 The waveform is defined according to the settings on
|
|
* DI0_DW_SET1_<i> 10 The waveform is defined according to the settings on DI0_DW_SET2_<i> 11 The
|
|
* waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
typedef union _hw_ipu_di0_dw_gen_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_dw_gen_i_bitfields
|
|
{
|
|
unsigned DI0_PT_0_I : 2; //!< [1:0] DI0 PIN_11 pointer for waveform <i>
|
|
unsigned DI0_PT_1_I : 2; //!< [3:2] DI0 PIN_12 pointer for waveform <i>
|
|
unsigned DI0_PT_2_I : 2; //!< [5:4] DI0 PIN_13 pointer for waveform <i>
|
|
unsigned DI0_PT_3_I : 2; //!< [7:6] DI0 PIN_14 pointer for waveform <i>
|
|
unsigned DI0_PT_4_I : 2; //!< [9:8] DI0 PIN_15 pointer for waveform <i>
|
|
unsigned DI0_PT_5_I : 2; //!< [11:10] DI0 PIN_16 pointer for waveform <i>
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|
unsigned DI0_PT_6_I : 2; //!< [13:12] DI0 PIN_17 pointer for waveform <i>
|
|
unsigned DI0_CST_I : 2; //!< [15:14] DI0 Chip Select pointer for waveform <i>
|
|
unsigned DI0_COMPONNENT_SIZE_I : 8; //!< [23:16] DI0 component Size
|
|
unsigned DI0_ACCESS_SIZE_I : 8; //!< [31:24] DI0 Access Size <i>
|
|
} B;
|
|
} hw_ipu_di0_dw_gen_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_DW_GEN_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_DW_GEN_I_ADDR(x) (REGS_IPU_BASE(x) + 0x40058)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_DW_GEN_I(x) (*(volatile hw_ipu_di0_dw_gen_i_t *) HW_IPU_DI0_DW_GEN_I_ADDR(x))
|
|
#define HW_IPU_DI0_DW_GEN_I_RD(x) (HW_IPU_DI0_DW_GEN_I(x).U)
|
|
#define HW_IPU_DI0_DW_GEN_I_WR(x, v) (HW_IPU_DI0_DW_GEN_I(x).U = (v))
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|
#define HW_IPU_DI0_DW_GEN_I_SET(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, HW_IPU_DI0_DW_GEN_I_RD(x) | (v)))
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|
#define HW_IPU_DI0_DW_GEN_I_CLR(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, HW_IPU_DI0_DW_GEN_I_RD(x) & ~(v)))
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|
#define HW_IPU_DI0_DW_GEN_I_TOG(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, HW_IPU_DI0_DW_GEN_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_DW_GEN_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_0_I[1:0] (RW)
|
|
*
|
|
* DI0 PIN_11 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_11 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_0_I (0) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_0_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_0_I (0x00000003) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_0_I.
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|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_0_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_0_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_0_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_0_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_0_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_0_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_0_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_0_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_0_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_0_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_0_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_0_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_1_I[3:2] (RW)
|
|
*
|
|
* DI0 PIN_12 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_12 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_1_I (2) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_1_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_1_I (0x0000000c) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_1_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_1_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_1_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_1_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_1_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_1_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_1_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_1_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_1_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_1_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_1_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_1_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_1_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_2_I[5:4] (RW)
|
|
*
|
|
* DI0 PIN_13 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_13 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_2_I (4) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_2_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_2_I (0x00000030) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_2_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_2_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_2_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_2_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_2_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_2_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_2_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_2_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_2_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_2_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_2_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_2_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_2_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_3_I[7:6] (RW)
|
|
*
|
|
* DI0 PIN_14 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_14 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_3_I (6) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_3_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_3_I (0x000000c0) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_3_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_3_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_3_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_3_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_3_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_3_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_3_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_3_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_3_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_3_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_3_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_3_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_3_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_4_I[9:8] (RW)
|
|
*
|
|
* DI0 PIN_15 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_15 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_4_I (8) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_4_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_4_I (0x00000300) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_4_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_4_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_4_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_4_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_4_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_4_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_4_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_4_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_4_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_4_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_4_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_4_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_4_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_5_I[11:10] (RW)
|
|
*
|
|
* DI0 PIN_16 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_16 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_5_I (10) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_5_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_5_I (0x00000c00) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_5_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_5_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_5_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_5_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_5_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_5_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_5_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_5_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_5_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_5_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_5_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_5_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_5_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_PT_6_I[13:12] (RW)
|
|
*
|
|
* DI0 PIN_17 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_17 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_PT_6_I (12) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_PT_6_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_PT_6_I (0x00003000) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_PT_6_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_PT_6_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_PT_6_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_PT_6_I) >> BP_IPU_DI0_DW_GEN_I_DI0_PT_6_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_PT_6_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_PT_6_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_PT_6_I) & BM_IPU_DI0_DW_GEN_I_DI0_PT_6_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PT_6_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_PT_6_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_PT_6_I) | BF_IPU_DI0_DW_GEN_I_DI0_PT_6_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_CST_I[15:14] (RW)
|
|
*
|
|
* DI0 Chip Select pointer for waveform <i> This field points to a register that defines the
|
|
* waveform of the CS pin. The CS is automatically mapped to a specific display
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI0_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI0_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI0_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI0_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_CST_I (14) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_CST_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_CST_I (0x0000c000) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_CST_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_CST_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_CST_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_CST_I) >> BP_IPU_DI0_DW_GEN_I_DI0_CST_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_CST_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_CST_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_CST_I) & BM_IPU_DI0_DW_GEN_I_DI0_CST_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CST_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_CST_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_CST_I) | BF_IPU_DI0_DW_GEN_I_DI0_CST_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_COMPONNENT_SIZE_I[23:16] (RW)
|
|
*
|
|
* DI0 component Size This field defines the amount of IPU cycles between any 2 components
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I (16) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I (0x00ff0000) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I) >> BP_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I) & BM_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_COMPONNENT_SIZE_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I) | BF_IPU_DI0_DW_GEN_I_DI0_COMPONNENT_SIZE_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_GEN_I, field DI0_ACCESS_SIZE_I[31:24] (RW)
|
|
*
|
|
* DI0 Access Size <i> This field defines the amount of IPU cycles between any 2 accesses (an access
|
|
* may be a pixel or generic data that may have more one component)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I (24) //!< Bit position for IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I.
|
|
#define BM_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I (0xff000000) //!< Bit mask for IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I from a register value.
|
|
#define BG_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I) >> BP_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I.
|
|
#define BF_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I) & BM_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_ACCESS_SIZE_I field to a new value.
|
|
#define BW_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I(x, v) (HW_IPU_DI0_DW_GEN_I_WR(x, (HW_IPU_DI0_DW_GEN_I_RD(x) & ~BM_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I) | BF_IPU_DI0_DW_GEN_I_DI0_ACCESS_SIZE_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_DW_SET0_I - DI0 Data Wave Set 0 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_DW_SET0_I - DI0 Data Wave Set 0 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_dw_set0_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_dw_set0_i_bitfields
|
|
{
|
|
unsigned DI0_DATA_CNT_UP0_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI0_DATA_CNT_DOWN0_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_dw_set0_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_DW_SET0_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_DW_SET0_I_ADDR(x) (REGS_IPU_BASE(x) + 0x40088)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_DW_SET0_I(x) (*(volatile hw_ipu_di0_dw_set0_i_t *) HW_IPU_DI0_DW_SET0_I_ADDR(x))
|
|
#define HW_IPU_DI0_DW_SET0_I_RD(x) (HW_IPU_DI0_DW_SET0_I(x).U)
|
|
#define HW_IPU_DI0_DW_SET0_I_WR(x, v) (HW_IPU_DI0_DW_SET0_I(x).U = (v))
|
|
#define HW_IPU_DI0_DW_SET0_I_SET(x, v) (HW_IPU_DI0_DW_SET0_I_WR(x, HW_IPU_DI0_DW_SET0_I_RD(x) | (v)))
|
|
#define HW_IPU_DI0_DW_SET0_I_CLR(x, v) (HW_IPU_DI0_DW_SET0_I_WR(x, HW_IPU_DI0_DW_SET0_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_DW_SET0_I_TOG(x, v) (HW_IPU_DI0_DW_SET0_I_WR(x, HW_IPU_DI0_DW_SET0_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_DW_SET0_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_DW_SET0_I, field DI0_DATA_CNT_UP0_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a point according to the corresponding di0_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I (0) //!< Bit position for IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I.
|
|
#define BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I (0x000001ff) //!< Bit mask for IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I from a register value.
|
|
#define BG_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I) >> BP_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I.
|
|
#define BF_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I) & BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DATA_CNT_UP0_I field to a new value.
|
|
#define BW_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I(x, v) (HW_IPU_DI0_DW_SET0_I_WR(x, (HW_IPU_DI0_DW_SET0_I_RD(x) & ~BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I) | BF_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_UP0_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_SET0_I, field DI0_DATA_CNT_DOWN0_I[24:16] (RW)
|
|
*
|
|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a point according to the corresponding di0_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I (16) //!< Bit position for IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I.
|
|
#define BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I (0x01ff0000) //!< Bit mask for IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I.
|
|
|
|
//! @brief Get value of IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I from a register value.
|
|
#define BG_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I) >> BP_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I.
|
|
#define BF_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I) & BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DATA_CNT_DOWN0_I field to a new value.
|
|
#define BW_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I(x, v) (HW_IPU_DI0_DW_SET0_I_WR(x, (HW_IPU_DI0_DW_SET0_I_RD(x) & ~BM_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I) | BF_IPU_DI0_DW_SET0_I_DI0_DATA_CNT_DOWN0_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_DW_SET1_I - DI0 Data Wave Set 1 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_DW_SET1_I - DI0 Data Wave Set 1 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_dw_set1_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_dw_set1_i_bitfields
|
|
{
|
|
unsigned DI0_DATA_CNT_UP1_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI0_DATA_CNT_DOWN1_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_dw_set1_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_DW_SET1_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_DW_SET1_I_ADDR(x) (REGS_IPU_BASE(x) + 0x400b8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_DW_SET1_I(x) (*(volatile hw_ipu_di0_dw_set1_i_t *) HW_IPU_DI0_DW_SET1_I_ADDR(x))
|
|
#define HW_IPU_DI0_DW_SET1_I_RD(x) (HW_IPU_DI0_DW_SET1_I(x).U)
|
|
#define HW_IPU_DI0_DW_SET1_I_WR(x, v) (HW_IPU_DI0_DW_SET1_I(x).U = (v))
|
|
#define HW_IPU_DI0_DW_SET1_I_SET(x, v) (HW_IPU_DI0_DW_SET1_I_WR(x, HW_IPU_DI0_DW_SET1_I_RD(x) | (v)))
|
|
#define HW_IPU_DI0_DW_SET1_I_CLR(x, v) (HW_IPU_DI0_DW_SET1_I_WR(x, HW_IPU_DI0_DW_SET1_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_DW_SET1_I_TOG(x, v) (HW_IPU_DI0_DW_SET1_I_WR(x, HW_IPU_DI0_DW_SET1_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_DW_SET1_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_DW_SET1_I, field DI0_DATA_CNT_UP1_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di0_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I (0) //!< Bit position for IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I.
|
|
#define BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I (0x000001ff) //!< Bit mask for IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I.
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//! @brief Get value of IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I from a register value.
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#define BG_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I) >> BP_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I)
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//! @brief Format value for bitfield IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I.
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#define BF_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I) & BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_DATA_CNT_UP1_I field to a new value.
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#define BW_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I(x, v) (HW_IPU_DI0_DW_SET1_I_WR(x, (HW_IPU_DI0_DW_SET1_I_RD(x) & ~BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I) | BF_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_UP1_I(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_DW_SET1_I, field DI0_DATA_CNT_DOWN1_I[24:16] (RW)
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*
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* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
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* Waveform is mapped to a pint according to the corresponding di0_pt_*_<i>
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*/
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//@{
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#define BP_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I (16) //!< Bit position for IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I.
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#define BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I (0x01ff0000) //!< Bit mask for IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I.
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//! @brief Get value of IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I from a register value.
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#define BG_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I) >> BP_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I)
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//! @brief Format value for bitfield IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I.
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#define BF_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I) & BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_DATA_CNT_DOWN1_I field to a new value.
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#define BW_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I(x, v) (HW_IPU_DI0_DW_SET1_I_WR(x, (HW_IPU_DI0_DW_SET1_I_RD(x) & ~BM_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I) | BF_IPU_DI0_DW_SET1_I_DI0_DATA_CNT_DOWN1_I(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_DW_SET2_I - DI0 Data Wave Set 2 <i> Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI0_DW_SET2_I - DI0 Data Wave Set 2 <i> Register (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di0_dw_set2_i
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{
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reg32_t U;
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struct _hw_ipu_di0_dw_set2_i_bitfields
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{
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unsigned DI0_DATA_CNT_UP2_I : 9; //!< [8:0] Waveform's rising edge position.
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unsigned RESERVED0 : 7; //!< [15:9] Reserved.
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unsigned DI0_DATA_CNT_DOWN2_I : 9; //!< [24:16] Waveform's falling edge position.
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unsigned RESERVED1 : 7; //!< [31:25] Reserved.
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} B;
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} hw_ipu_di0_dw_set2_i_t;
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#endif
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/*!
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|
* @name Constants and macros for entire IPU_DI0_DW_SET2_I register
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*/
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//@{
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#define HW_IPU_DI0_DW_SET2_I_ADDR(x) (REGS_IPU_BASE(x) + 0x400e8)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_DW_SET2_I(x) (*(volatile hw_ipu_di0_dw_set2_i_t *) HW_IPU_DI0_DW_SET2_I_ADDR(x))
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#define HW_IPU_DI0_DW_SET2_I_RD(x) (HW_IPU_DI0_DW_SET2_I(x).U)
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#define HW_IPU_DI0_DW_SET2_I_WR(x, v) (HW_IPU_DI0_DW_SET2_I(x).U = (v))
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#define HW_IPU_DI0_DW_SET2_I_SET(x, v) (HW_IPU_DI0_DW_SET2_I_WR(x, HW_IPU_DI0_DW_SET2_I_RD(x) | (v)))
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#define HW_IPU_DI0_DW_SET2_I_CLR(x, v) (HW_IPU_DI0_DW_SET2_I_WR(x, HW_IPU_DI0_DW_SET2_I_RD(x) & ~(v)))
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#define HW_IPU_DI0_DW_SET2_I_TOG(x, v) (HW_IPU_DI0_DW_SET2_I_WR(x, HW_IPU_DI0_DW_SET2_I_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DI0_DW_SET2_I bitfields
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*/
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/*! @name Register IPU_DI0_DW_SET2_I, field DI0_DATA_CNT_UP2_I[8:0] (RW)
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*
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* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
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* Waveform is mapped to a pint according to the corresponding di0_pt_*_<i>
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|
*/
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//@{
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#define BP_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I (0) //!< Bit position for IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I.
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#define BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I (0x000001ff) //!< Bit mask for IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I.
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//! @brief Get value of IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I from a register value.
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#define BG_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I) >> BP_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I)
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//! @brief Format value for bitfield IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I.
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#define BF_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I) & BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_DATA_CNT_UP2_I field to a new value.
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#define BW_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I(x, v) (HW_IPU_DI0_DW_SET2_I_WR(x, (HW_IPU_DI0_DW_SET2_I_RD(x) & ~BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I) | BF_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_UP2_I(v)))
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|
#endif
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//@}
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/*! @name Register IPU_DI0_DW_SET2_I, field DI0_DATA_CNT_DOWN2_I[24:16] (RW)
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|
*
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|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di0_pt_*_<i>
|
|
*/
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|
//@{
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|
#define BP_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I (16) //!< Bit position for IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I.
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#define BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I (0x01ff0000) //!< Bit mask for IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I.
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//! @brief Get value of IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I from a register value.
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#define BG_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I) >> BP_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I)
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//! @brief Format value for bitfield IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I.
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#define BF_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I) & BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I)
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|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_DATA_CNT_DOWN2_I field to a new value.
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#define BW_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I(x, v) (HW_IPU_DI0_DW_SET2_I_WR(x, (HW_IPU_DI0_DW_SET2_I_RD(x) & ~BM_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I) | BF_IPU_DI0_DW_SET2_I_DI0_DATA_CNT_DOWN2_I(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_DW_SET3_I - DI0 Data Wave Set 3 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_DW_SET3_I - DI0 Data Wave Set 3 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_dw_set3_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_dw_set3_i_bitfields
|
|
{
|
|
unsigned DI0_DATA_CNT_UP3_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI0_DATA_CNT_DOWN3_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_dw_set3_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_DW_SET3_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_DW_SET3_I_ADDR(x) (REGS_IPU_BASE(x) + 0x40118)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_DW_SET3_I(x) (*(volatile hw_ipu_di0_dw_set3_i_t *) HW_IPU_DI0_DW_SET3_I_ADDR(x))
|
|
#define HW_IPU_DI0_DW_SET3_I_RD(x) (HW_IPU_DI0_DW_SET3_I(x).U)
|
|
#define HW_IPU_DI0_DW_SET3_I_WR(x, v) (HW_IPU_DI0_DW_SET3_I(x).U = (v))
|
|
#define HW_IPU_DI0_DW_SET3_I_SET(x, v) (HW_IPU_DI0_DW_SET3_I_WR(x, HW_IPU_DI0_DW_SET3_I_RD(x) | (v)))
|
|
#define HW_IPU_DI0_DW_SET3_I_CLR(x, v) (HW_IPU_DI0_DW_SET3_I_WR(x, HW_IPU_DI0_DW_SET3_I_RD(x) & ~(v)))
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|
#define HW_IPU_DI0_DW_SET3_I_TOG(x, v) (HW_IPU_DI0_DW_SET3_I_WR(x, HW_IPU_DI0_DW_SET3_I_RD(x) ^ (v)))
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|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_DW_SET3_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_DW_SET3_I, field DI0_DATA_CNT_UP3_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di0_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I (0) //!< Bit position for IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I.
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|
#define BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I (0x000001ff) //!< Bit mask for IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I.
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|
|
|
//! @brief Get value of IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I from a register value.
|
|
#define BG_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I) >> BP_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I)
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|
|
//! @brief Format value for bitfield IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I.
|
|
#define BF_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I) & BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DATA_CNT_UP3_I field to a new value.
|
|
#define BW_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I(x, v) (HW_IPU_DI0_DW_SET3_I_WR(x, (HW_IPU_DI0_DW_SET3_I_RD(x) & ~BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I) | BF_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_UP3_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_DW_SET3_I, field DI0_DATA_CNT_DOWN3_I[24:16] (RW)
|
|
*
|
|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di0_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I (16) //!< Bit position for IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I.
|
|
#define BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I (0x01ff0000) //!< Bit mask for IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I.
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|
|
|
//! @brief Get value of IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I from a register value.
|
|
#define BG_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I) >> BP_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I.
|
|
#define BF_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I) & BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DATA_CNT_DOWN3_I field to a new value.
|
|
#define BW_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I(x, v) (HW_IPU_DI0_DW_SET3_I_WR(x, (HW_IPU_DI0_DW_SET3_I_RD(x) & ~BM_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I) | BF_IPU_DI0_DW_SET3_I_DI0_DATA_CNT_DOWN3_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_STP_REP_I - DI0 Step Repeat <i> Registers
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_STP_REP_I - DI0 Step Repeat <i> Registers (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_stp_rep_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_stp_rep_i_bitfields
|
|
{
|
|
unsigned DI0_STEP_REPEAT_2I_MINUS_1 : 12; //!< [11:0] Step Repeat <i>
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved
|
|
unsigned DI0_STEP_REPEAT_2I : 12; //!< [27:16] Step Repeat <i>
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved
|
|
} B;
|
|
} hw_ipu_di0_stp_rep_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_STP_REP_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_STP_REP_I_ADDR(x) (REGS_IPU_BASE(x) + 0x40148)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_STP_REP_I(x) (*(volatile hw_ipu_di0_stp_rep_i_t *) HW_IPU_DI0_STP_REP_I_ADDR(x))
|
|
#define HW_IPU_DI0_STP_REP_I_RD(x) (HW_IPU_DI0_STP_REP_I(x).U)
|
|
#define HW_IPU_DI0_STP_REP_I_WR(x, v) (HW_IPU_DI0_STP_REP_I(x).U = (v))
|
|
#define HW_IPU_DI0_STP_REP_I_SET(x, v) (HW_IPU_DI0_STP_REP_I_WR(x, HW_IPU_DI0_STP_REP_I_RD(x) | (v)))
|
|
#define HW_IPU_DI0_STP_REP_I_CLR(x, v) (HW_IPU_DI0_STP_REP_I_WR(x, HW_IPU_DI0_STP_REP_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_STP_REP_I_TOG(x, v) (HW_IPU_DI0_STP_REP_I_WR(x, HW_IPU_DI0_STP_REP_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_STP_REP_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_STP_REP_I, field DI0_STEP_REPEAT_2I_MINUS_1[11:0] (RW)
|
|
*
|
|
* Step Repeat <i> This fields defines the amount of repetitions that will be performed by the
|
|
* counter <i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1 (0) //!< Bit position for IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1.
|
|
#define BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1 (0x00000fff) //!< Bit mask for IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1.
|
|
|
|
//! @brief Get value of IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1 from a register value.
|
|
#define BG_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1) >> BP_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1)
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//! @brief Format value for bitfield IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1.
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#define BF_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1) & BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_STEP_REPEAT_2I_MINUS_1 field to a new value.
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#define BW_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1(x, v) (HW_IPU_DI0_STP_REP_I_WR(x, (HW_IPU_DI0_STP_REP_I_RD(x) & ~BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1) | BF_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I_MINUS_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_STP_REP_I, field DI0_STEP_REPEAT_2I[27:16] (RW)
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*
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* Step Repeat <i> This fields defines the amount of repetitions that will be performed by the
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* counter <i>
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*/
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//@{
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#define BP_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I (16) //!< Bit position for IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I.
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#define BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I (0x0fff0000) //!< Bit mask for IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I.
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//! @brief Get value of IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I from a register value.
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#define BG_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I) >> BP_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I)
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//! @brief Format value for bitfield IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I.
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#define BF_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I) & BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_STEP_REPEAT_2I field to a new value.
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#define BW_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I(x, v) (HW_IPU_DI0_STP_REP_I_WR(x, (HW_IPU_DI0_STP_REP_I_RD(x) & ~BM_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I) | BF_IPU_DI0_STP_REP_I_DI0_STEP_REPEAT_2I(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI0_STP_REP_9 - DI0 Step Repeat 9 Registers
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI0_STP_REP_9 - DI0 Step Repeat 9 Registers (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di0_stp_rep_9
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{
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reg32_t U;
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struct _hw_ipu_di0_stp_rep_9_bitfields
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{
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unsigned DI0_STEP_REPEAT_9 : 12; //!< [11:0] Step Repeat 9
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unsigned RESERVED0 : 20; //!< [31:12] Reserved
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} B;
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} hw_ipu_di0_stp_rep_9_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DI0_STP_REP_9 register
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*/
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//@{
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#define HW_IPU_DI0_STP_REP_9_ADDR(x) (REGS_IPU_BASE(x) + 0x40158)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI0_STP_REP_9(x) (*(volatile hw_ipu_di0_stp_rep_9_t *) HW_IPU_DI0_STP_REP_9_ADDR(x))
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#define HW_IPU_DI0_STP_REP_9_RD(x) (HW_IPU_DI0_STP_REP_9(x).U)
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#define HW_IPU_DI0_STP_REP_9_WR(x, v) (HW_IPU_DI0_STP_REP_9(x).U = (v))
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#define HW_IPU_DI0_STP_REP_9_SET(x, v) (HW_IPU_DI0_STP_REP_9_WR(x, HW_IPU_DI0_STP_REP_9_RD(x) | (v)))
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#define HW_IPU_DI0_STP_REP_9_CLR(x, v) (HW_IPU_DI0_STP_REP_9_WR(x, HW_IPU_DI0_STP_REP_9_RD(x) & ~(v)))
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#define HW_IPU_DI0_STP_REP_9_TOG(x, v) (HW_IPU_DI0_STP_REP_9_WR(x, HW_IPU_DI0_STP_REP_9_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
|
|
* constants & macros for individual IPU_DI0_STP_REP_9 bitfields
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|
*/
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/*! @name Register IPU_DI0_STP_REP_9, field DI0_STEP_REPEAT_9[11:0] (RW)
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*
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|
* Step Repeat 9 This fields defines the amount of repetitions that will be performed by the counter
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|
* 9
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9 (0) //!< Bit position for IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9.
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#define BM_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9 (0x00000fff) //!< Bit mask for IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9.
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//! @brief Get value of IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9 from a register value.
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|
#define BG_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9) >> BP_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9)
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//! @brief Format value for bitfield IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9.
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|
#define BF_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9) & BM_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_STEP_REPEAT_9 field to a new value.
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|
#define BW_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9(x, v) (HW_IPU_DI0_STP_REP_9_WR(x, (HW_IPU_DI0_STP_REP_9_RD(x) & ~BM_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9) | BF_IPU_DI0_STP_REP_9_DI0_STEP_REPEAT_9(v)))
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#endif
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|
//@}
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|
//-------------------------------------------------------------------------------------------
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|
// HW_IPU_DI0_SER_CONF - DI0 Serial Display Control Register
|
|
//-------------------------------------------------------------------------------------------
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|
|
|
#ifndef __LANGUAGE_ASM__
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|
/*!
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|
* @brief HW_IPU_DI0_SER_CONF - DI0 Serial Display Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
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|
*/
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|
typedef union _hw_ipu_di0_ser_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_ser_conf_bitfields
|
|
{
|
|
unsigned DI0_WAIT4SERIAL : 1; //!< [0] Wait for Serial
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|
unsigned DI0_SERIAL_CS_POLARITY : 1; //!< [1] Serial Chip Select Polarity
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|
unsigned DI0_SERIAL_RS_POLARITY : 1; //!< [2] Serial RS Polarity
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|
unsigned DI0_SERIAL_DATA_POLARITY : 1; //!< [3] Serial Data Polarity
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|
unsigned DI0_SER_CLK_POLARITY : 1; //!< [4] Serial Clock Polarity
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|
unsigned DI0_LLA_SER_ACCESS : 1; //!< [5] Direct Low Level Access to Serial display
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|
unsigned RESERVED0 : 2; //!< [7:6] Reserved
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|
unsigned DI0_SERIAL_LATCH : 8; //!< [15:8] DI0 Serial Latch
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|
unsigned DI0_SERIAL_LLA_PNTR_RS_W_0 : 4; //!< [19:16] RS 0 waveform pointer for write low level access
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|
unsigned DI0_SERIAL_LLA_PNTR_RS_W_1 : 4; //!< [23:20] RS 1 waveform pointer for write low level access
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unsigned DI0_SERIAL_LLA_PNTR_RS_R_0 : 4; //!< [27:24] RS 2 waveform pointer for read low level access
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unsigned DI0_SERIAL_LLA_PNTR_RS_R_1 : 4; //!< [31:28] RS 3 waveform pointer for read low level access
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|
} B;
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|
} hw_ipu_di0_ser_conf_t;
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|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SER_CONF register
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|
*/
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|
//@{
|
|
#define HW_IPU_DI0_SER_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x4015c)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SER_CONF(x) (*(volatile hw_ipu_di0_ser_conf_t *) HW_IPU_DI0_SER_CONF_ADDR(x))
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|
#define HW_IPU_DI0_SER_CONF_RD(x) (HW_IPU_DI0_SER_CONF(x).U)
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|
#define HW_IPU_DI0_SER_CONF_WR(x, v) (HW_IPU_DI0_SER_CONF(x).U = (v))
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|
#define HW_IPU_DI0_SER_CONF_SET(x, v) (HW_IPU_DI0_SER_CONF_WR(x, HW_IPU_DI0_SER_CONF_RD(x) | (v)))
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|
#define HW_IPU_DI0_SER_CONF_CLR(x, v) (HW_IPU_DI0_SER_CONF_WR(x, HW_IPU_DI0_SER_CONF_RD(x) & ~(v)))
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|
#define HW_IPU_DI0_SER_CONF_TOG(x, v) (HW_IPU_DI0_SER_CONF_WR(x, HW_IPU_DI0_SER_CONF_RD(x) ^ (v)))
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|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SER_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_WAIT4SERIAL[0] (RW)
|
|
*
|
|
* Wait for Serial When the parallel display share pins with the serial port. Accessing the parallel
|
|
* port is not allowed till the serial port completes its access.
|
|
*
|
|
* Values:
|
|
* - 0 - The parallel port should not wait to the serial port as the pins are not shared
|
|
* - 1 - The parallel port should wait to the serial port as the pins are shared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL (0) //!< Bit position for IPU_DI0_SER_CONF_DI0_WAIT4SERIAL.
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|
#define BM_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL (0x00000001) //!< Bit mask for IPU_DI0_SER_CONF_DI0_WAIT4SERIAL.
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|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_WAIT4SERIAL from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL) >> BP_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_WAIT4SERIAL.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL) & BM_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_WAIT4SERIAL field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL) | BF_IPU_DI0_SER_CONF_DI0_WAIT4SERIAL(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_CS_POLARITY[1] (RW)
|
|
*
|
|
* Serial Chip Select Polarity The output polarity of the SER_CS pin
|
|
*
|
|
* Values:
|
|
* - 0 - The CS is not inverted
|
|
* - 1 - The CS is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY (1) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY.
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|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY (0x00000002) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY.
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|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_CS_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_CS_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_RS_POLARITY[2] (RW)
|
|
*
|
|
* Serial RS Polarity The output polarity of the SER_RS pin
|
|
*
|
|
* Values:
|
|
* - 0 - The RS is not inverted
|
|
* - 1 - The RS is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY (2) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY (0x00000004) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY.
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|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_RS_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_RS_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_DATA_POLARITY[3] (RW)
|
|
*
|
|
* Serial Data Polarity The output polarity of the SER_DATA pin
|
|
*
|
|
* Values:
|
|
* - 0 - The data is not inverted
|
|
* - 1 - The data is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY (3) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY (0x00000008) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SER_CLK_POLARITY[4] (RW)
|
|
*
|
|
* Serial Clock Polarity The output polarity of the SER_CLK pin
|
|
*
|
|
* Values:
|
|
* - 0 - The clock is not inverted
|
|
* - 1 - The clock is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY (4) //!< Bit position for IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY (0x00000010) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY) >> BP_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY) & BM_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SER_CLK_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY) | BF_IPU_DI0_SER_CONF_DI0_SER_CLK_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_LLA_SER_ACCESS[5] (RW)
|
|
*
|
|
* Direct Low Level Access to Serial display
|
|
*
|
|
* Values:
|
|
* - 0 - ARM platform access to the serial display port is not done directly, hence other source are allowed
|
|
* to access the serial port. The arbitration is done automatically
|
|
* - 1 - ARM platform access is performed via a direct path to the serial display in LLA mode, in this mode
|
|
* only the ARM platform in LLA mode can access the serial port
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS (5) //!< Bit position for IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS (0x00000020) //!< Bit mask for IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS) >> BP_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS) & BM_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_LLA_SER_ACCESS field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS) | BF_IPU_DI0_SER_CONF_DI0_LLA_SER_ACCESS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_LATCH[15:8] (RW)
|
|
*
|
|
* DI0 Serial Latch This field defines how many cycles to insert between serial read accesses start
|
|
* to data sampling in the
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH (8) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_LATCH.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH (0x0000ff00) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_LATCH.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_LATCH from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_LATCH.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_LATCH field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_LATCH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_LLA_PNTR_RS_W_0[19:16] (RW)
|
|
*
|
|
* RS 0 waveform pointer for write low level access This pointer defines which waveform set will be
|
|
* chosen when the low level write access is targeted to RS group 0.
|
|
*
|
|
* Values:
|
|
* - 0000 - Waveform set #1
|
|
* - 0001 - Waveform set #2
|
|
* - 1011 - Waveform set #12
|
|
* - 1100 - Reserved
|
|
* - 1100 - Reserved
|
|
* - 1101 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0 (16) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0 (0x000f0000) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0 from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_LLA_PNTR_RS_W_0 field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_LLA_PNTR_RS_W_1[23:20] (RW)
|
|
*
|
|
* RS 1 waveform pointer for write low level access This pointer defines which waveform set will be
|
|
* chosen when the low level write access is targeted to RS group 1.
|
|
*
|
|
* Values:
|
|
* - 0000 - Waveform set #1
|
|
* - 0001 - Waveform set #2
|
|
* - 1011 - Waveform set #12
|
|
* - 1100 - Reserved
|
|
* - 1100 - Reserved
|
|
* - 1101 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1 (20) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1 (0x00f00000) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1 from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_LLA_PNTR_RS_W_1 field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_W_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_LLA_PNTR_RS_R_0[27:24] (RW)
|
|
*
|
|
* RS 2 waveform pointer for read low level access This pointer defines which waveform set will be
|
|
* chosen when the read low level access is targeted to RS group 0.
|
|
*
|
|
* Values:
|
|
* - 0000 - Waveform set #1
|
|
* - 0001 - Waveform set #2
|
|
* - 1011 - Waveform set #12
|
|
* - 1100 - Reserved
|
|
* - 1100 - Reserved
|
|
* - 1101 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0 (24) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0 (0x0f000000) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0 from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_LLA_PNTR_RS_R_0 field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SER_CONF, field DI0_SERIAL_LLA_PNTR_RS_R_1[31:28] (RW)
|
|
*
|
|
* RS 3 waveform pointer for read low level access This pointer defines which waveform set will be
|
|
* chosen when the read low level access is targeted to RS group 1.
|
|
*
|
|
* Values:
|
|
* - 0000 - Waveform set #1
|
|
* - 0001 - Waveform set #2
|
|
* - 1011 - Waveform set #12
|
|
* - 1100 - Reserved
|
|
* - 1100 - Reserved
|
|
* - 1101 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1 (28) //!< Bit position for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1.
|
|
#define BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1 (0xf0000000) //!< Bit mask for IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1.
|
|
|
|
//! @brief Get value of IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1 from a register value.
|
|
#define BG_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1) >> BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1.
|
|
#define BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1) & BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SERIAL_LLA_PNTR_RS_R_1 field to a new value.
|
|
#define BW_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1(x, v) (HW_IPU_DI0_SER_CONF_WR(x, (HW_IPU_DI0_SER_CONF_RD(x) & ~BM_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1) | BF_IPU_DI0_SER_CONF_DI0_SERIAL_LLA_PNTR_RS_R_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SSC - DI0 Special Signals Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SSC - DI0 Special Signals Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_ssc
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_ssc_bitfields
|
|
{
|
|
unsigned DI0_BYTE_EN_PNTR : 3; //!< [2:0] Byte Enable Pointer
|
|
unsigned DI0_BYTE_EN_RD_IN : 1; //!< [3] Byte Enable Read In
|
|
unsigned RESERVED0 : 1; //!< [4] Reserved
|
|
unsigned DI0_WAIT_ON : 1; //!< [5] Wait On
|
|
unsigned RESERVED1 : 10; //!< [15:6] Reserved.
|
|
unsigned DI0_CS_ERM : 1; //!< [16] DI0 GLUELOGIC error recovery mode.
|
|
unsigned DI0_PIN11_ERM : 1; //!< [17] DI0 PIN11 error recovery mode.
|
|
unsigned DI0_PIN12_ERM : 1; //!< [18] DI0 PIN12 error recovery mode.
|
|
unsigned DI0_PIN13_ERM : 1; //!< [19] DI0 PIN13 error recovery mode.
|
|
unsigned DI0_PIN14_ERM : 1; //!< [20] DI0 PIN14 error recovery mode.
|
|
unsigned DI0_PIN15_ERM : 1; //!< [21] DI0 PIN15 error recovery mode.
|
|
unsigned DI0_PIN16_ERM : 1; //!< [22] DI0 PIN16 error recovery mode.
|
|
unsigned DI0_PIN17_ERM : 1; //!< [23] DI0 PIN17 error recovery mode.
|
|
unsigned RESERVED2 : 8; //!< [31:24] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_ssc_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SSC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SSC_ADDR(x) (REGS_IPU_BASE(x) + 0x40160)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SSC(x) (*(volatile hw_ipu_di0_ssc_t *) HW_IPU_DI0_SSC_ADDR(x))
|
|
#define HW_IPU_DI0_SSC_RD(x) (HW_IPU_DI0_SSC(x).U)
|
|
#define HW_IPU_DI0_SSC_WR(x, v) (HW_IPU_DI0_SSC(x).U = (v))
|
|
#define HW_IPU_DI0_SSC_SET(x, v) (HW_IPU_DI0_SSC_WR(x, HW_IPU_DI0_SSC_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SSC_CLR(x, v) (HW_IPU_DI0_SSC_WR(x, HW_IPU_DI0_SSC_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SSC_TOG(x, v) (HW_IPU_DI0_SSC_WR(x, HW_IPU_DI0_SSC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SSC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SSC, field DI0_BYTE_EN_PNTR[2:0] (RW)
|
|
*
|
|
* Byte Enable Pointer This pointer selects the pin asserted along with the byte enables signals
|
|
*
|
|
* Values:
|
|
* - 000 - wave form of byte enable as pin_11
|
|
* - 001 - wave form of byte enable as pin_12
|
|
* - 111 - wave form of byte enable as suitable CS pin
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SSC_DI0_BYTE_EN_PNTR (0) //!< Bit position for IPU_DI0_SSC_DI0_BYTE_EN_PNTR.
|
|
#define BM_IPU_DI0_SSC_DI0_BYTE_EN_PNTR (0x00000007) //!< Bit mask for IPU_DI0_SSC_DI0_BYTE_EN_PNTR.
|
|
|
|
//! @brief Get value of IPU_DI0_SSC_DI0_BYTE_EN_PNTR from a register value.
|
|
#define BG_IPU_DI0_SSC_DI0_BYTE_EN_PNTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_BYTE_EN_PNTR) >> BP_IPU_DI0_SSC_DI0_BYTE_EN_PNTR)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_BYTE_EN_PNTR.
|
|
#define BF_IPU_DI0_SSC_DI0_BYTE_EN_PNTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_BYTE_EN_PNTR) & BM_IPU_DI0_SSC_DI0_BYTE_EN_PNTR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_BYTE_EN_PNTR field to a new value.
|
|
#define BW_IPU_DI0_SSC_DI0_BYTE_EN_PNTR(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_BYTE_EN_PNTR) | BF_IPU_DI0_SSC_DI0_BYTE_EN_PNTR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SSC, field DI0_BYTE_EN_RD_IN[3] (RW)
|
|
*
|
|
* Byte Enable Read In This bit selects the source of the byte enable pins
|
|
*
|
|
* Values:
|
|
* - 0 - The byte enable signals are routed via bits [17:16] of the display's data for both read and write
|
|
* - 1 - The write byte enable signals are routed via bits [17:16] of the display's data, The read byte
|
|
* enable signals are routed via bits [19:18 of the display's data
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN (3) //!< Bit position for IPU_DI0_SSC_DI0_BYTE_EN_RD_IN.
|
|
#define BM_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN (0x00000008) //!< Bit mask for IPU_DI0_SSC_DI0_BYTE_EN_RD_IN.
|
|
|
|
//! @brief Get value of IPU_DI0_SSC_DI0_BYTE_EN_RD_IN from a register value.
|
|
#define BG_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN) >> BP_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_BYTE_EN_RD_IN.
|
|
#define BF_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN) & BM_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN)
|
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_BYTE_EN_RD_IN field to a new value.
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#define BW_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN) | BF_IPU_DI0_SSC_DI0_BYTE_EN_RD_IN(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SSC, field DI0_WAIT_ON[5] (RW)
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*
|
|
* Wait On This field defines the DC's response to WAIT signal
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|
*
|
|
* Values:
|
|
* - 0 - The DC continues the flow regardless the WAIT signal
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|
* - 1 - The DC holds the flow as long as WAIT is asserted
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|
*/
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//@{
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|
#define BP_IPU_DI0_SSC_DI0_WAIT_ON (5) //!< Bit position for IPU_DI0_SSC_DI0_WAIT_ON.
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#define BM_IPU_DI0_SSC_DI0_WAIT_ON (0x00000020) //!< Bit mask for IPU_DI0_SSC_DI0_WAIT_ON.
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//! @brief Get value of IPU_DI0_SSC_DI0_WAIT_ON from a register value.
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#define BG_IPU_DI0_SSC_DI0_WAIT_ON(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_WAIT_ON) >> BP_IPU_DI0_SSC_DI0_WAIT_ON)
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//! @brief Format value for bitfield IPU_DI0_SSC_DI0_WAIT_ON.
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#define BF_IPU_DI0_SSC_DI0_WAIT_ON(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_WAIT_ON) & BM_IPU_DI0_SSC_DI0_WAIT_ON)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI0_WAIT_ON field to a new value.
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#define BW_IPU_DI0_SSC_DI0_WAIT_ON(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_WAIT_ON) | BF_IPU_DI0_SSC_DI0_WAIT_ON(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SSC, field DI0_CS_ERM[16] (RW)
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*
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* DI0 GLUELOGIC error recovery mode. This bit defines the error recovery mode of the GLUELOGIC.
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*
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* Values:
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|
* - 0 - Nothing is done to the GLUELOGIC following a display error detection
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* - 1 - The GLUELOGIC is release in case of a synchronous display error. The release will be done on the
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* next VSYNC
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*/
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//@{
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#define BP_IPU_DI0_SSC_DI0_CS_ERM (16) //!< Bit position for IPU_DI0_SSC_DI0_CS_ERM.
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#define BM_IPU_DI0_SSC_DI0_CS_ERM (0x00010000) //!< Bit mask for IPU_DI0_SSC_DI0_CS_ERM.
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//! @brief Get value of IPU_DI0_SSC_DI0_CS_ERM from a register value.
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#define BG_IPU_DI0_SSC_DI0_CS_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_CS_ERM) >> BP_IPU_DI0_SSC_DI0_CS_ERM)
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//! @brief Format value for bitfield IPU_DI0_SSC_DI0_CS_ERM.
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#define BF_IPU_DI0_SSC_DI0_CS_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_CS_ERM) & BM_IPU_DI0_SSC_DI0_CS_ERM)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_CS_ERM field to a new value.
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|
#define BW_IPU_DI0_SSC_DI0_CS_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_CS_ERM) | BF_IPU_DI0_SSC_DI0_CS_ERM(v)))
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#endif
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//@}
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/*! @name Register IPU_DI0_SSC, field DI0_PIN11_ERM[17] (RW)
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|
*
|
|
* DI0 PIN11 error recovery mode. This bit defines the error recovery mode of the PIN11 pin.
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|
*
|
|
* Values:
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|
* - 0 - Nothing is done to the PIN11 pin following a display error detection
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* - 1 - The PIN11 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_SSC_DI0_PIN11_ERM (17) //!< Bit position for IPU_DI0_SSC_DI0_PIN11_ERM.
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#define BM_IPU_DI0_SSC_DI0_PIN11_ERM (0x00020000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN11_ERM.
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//! @brief Get value of IPU_DI0_SSC_DI0_PIN11_ERM from a register value.
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#define BG_IPU_DI0_SSC_DI0_PIN11_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN11_ERM) >> BP_IPU_DI0_SSC_DI0_PIN11_ERM)
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//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN11_ERM.
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|
#define BF_IPU_DI0_SSC_DI0_PIN11_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN11_ERM) & BM_IPU_DI0_SSC_DI0_PIN11_ERM)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_PIN11_ERM field to a new value.
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|
#define BW_IPU_DI0_SSC_DI0_PIN11_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN11_ERM) | BF_IPU_DI0_SSC_DI0_PIN11_ERM(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DI0_SSC, field DI0_PIN12_ERM[18] (RW)
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|
*
|
|
* DI0 PIN12 error recovery mode. This bit defines the error recovery mode of the PIN12 pin.
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|
*
|
|
* Values:
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|
* - 0 - Nothing is done to the PIN12 pin following a display error detection
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|
* - 1 - The PIN12 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_SSC_DI0_PIN12_ERM (18) //!< Bit position for IPU_DI0_SSC_DI0_PIN12_ERM.
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#define BM_IPU_DI0_SSC_DI0_PIN12_ERM (0x00040000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN12_ERM.
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//! @brief Get value of IPU_DI0_SSC_DI0_PIN12_ERM from a register value.
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|
#define BG_IPU_DI0_SSC_DI0_PIN12_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN12_ERM) >> BP_IPU_DI0_SSC_DI0_PIN12_ERM)
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|
|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN12_ERM.
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|
#define BF_IPU_DI0_SSC_DI0_PIN12_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN12_ERM) & BM_IPU_DI0_SSC_DI0_PIN12_ERM)
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|
|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_PIN12_ERM field to a new value.
|
|
#define BW_IPU_DI0_SSC_DI0_PIN12_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN12_ERM) | BF_IPU_DI0_SSC_DI0_PIN12_ERM(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DI0_SSC, field DI0_PIN13_ERM[19] (RW)
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|
*
|
|
* DI0 PIN13 error recovery mode. This bit defines the error recovery mode of the PIN13 pin.
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|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN13 pin following a display error detection
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|
* - 1 - The PIN13 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_SSC_DI0_PIN13_ERM (19) //!< Bit position for IPU_DI0_SSC_DI0_PIN13_ERM.
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|
#define BM_IPU_DI0_SSC_DI0_PIN13_ERM (0x00080000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN13_ERM.
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|
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|
//! @brief Get value of IPU_DI0_SSC_DI0_PIN13_ERM from a register value.
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|
#define BG_IPU_DI0_SSC_DI0_PIN13_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN13_ERM) >> BP_IPU_DI0_SSC_DI0_PIN13_ERM)
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|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN13_ERM.
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|
#define BF_IPU_DI0_SSC_DI0_PIN13_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN13_ERM) & BM_IPU_DI0_SSC_DI0_PIN13_ERM)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI0_PIN13_ERM field to a new value.
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|
#define BW_IPU_DI0_SSC_DI0_PIN13_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN13_ERM) | BF_IPU_DI0_SSC_DI0_PIN13_ERM(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DI0_SSC, field DI0_PIN14_ERM[20] (RW)
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|
*
|
|
* DI0 PIN14 error recovery mode. This bit defines the error recovery mode of the PIN14 pin.
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|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN14 pin following a display error detection
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|
* - 1 - The PIN14 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC
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|
*/
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|
//@{
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|
#define BP_IPU_DI0_SSC_DI0_PIN14_ERM (20) //!< Bit position for IPU_DI0_SSC_DI0_PIN14_ERM.
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|
#define BM_IPU_DI0_SSC_DI0_PIN14_ERM (0x00100000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN14_ERM.
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|
//! @brief Get value of IPU_DI0_SSC_DI0_PIN14_ERM from a register value.
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|
#define BG_IPU_DI0_SSC_DI0_PIN14_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN14_ERM) >> BP_IPU_DI0_SSC_DI0_PIN14_ERM)
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|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN14_ERM.
|
|
#define BF_IPU_DI0_SSC_DI0_PIN14_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN14_ERM) & BM_IPU_DI0_SSC_DI0_PIN14_ERM)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PIN14_ERM field to a new value.
|
|
#define BW_IPU_DI0_SSC_DI0_PIN14_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN14_ERM) | BF_IPU_DI0_SSC_DI0_PIN14_ERM(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DI0_SSC, field DI0_PIN15_ERM[21] (RW)
|
|
*
|
|
* DI0 PIN15 error recovery mode. This bit defines the error recovery mode of the PIN15 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN15 pin following a display error detection
|
|
* - 1 - The PIN15 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SSC_DI0_PIN15_ERM (21) //!< Bit position for IPU_DI0_SSC_DI0_PIN15_ERM.
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|
#define BM_IPU_DI0_SSC_DI0_PIN15_ERM (0x00200000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN15_ERM.
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|
|
//! @brief Get value of IPU_DI0_SSC_DI0_PIN15_ERM from a register value.
|
|
#define BG_IPU_DI0_SSC_DI0_PIN15_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN15_ERM) >> BP_IPU_DI0_SSC_DI0_PIN15_ERM)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN15_ERM.
|
|
#define BF_IPU_DI0_SSC_DI0_PIN15_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN15_ERM) & BM_IPU_DI0_SSC_DI0_PIN15_ERM)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PIN15_ERM field to a new value.
|
|
#define BW_IPU_DI0_SSC_DI0_PIN15_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN15_ERM) | BF_IPU_DI0_SSC_DI0_PIN15_ERM(v)))
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|
#endif
|
|
//@}
|
|
|
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/*! @name Register IPU_DI0_SSC, field DI0_PIN16_ERM[22] (RW)
|
|
*
|
|
* DI0 PIN16 error recovery mode. This bit defines the error recovery mode of the PIN16 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN16 pin following a display error detection
|
|
* - 1 - The PIN16 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SSC_DI0_PIN16_ERM (22) //!< Bit position for IPU_DI0_SSC_DI0_PIN16_ERM.
|
|
#define BM_IPU_DI0_SSC_DI0_PIN16_ERM (0x00400000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN16_ERM.
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|
|
|
//! @brief Get value of IPU_DI0_SSC_DI0_PIN16_ERM from a register value.
|
|
#define BG_IPU_DI0_SSC_DI0_PIN16_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN16_ERM) >> BP_IPU_DI0_SSC_DI0_PIN16_ERM)
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|
|
|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN16_ERM.
|
|
#define BF_IPU_DI0_SSC_DI0_PIN16_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN16_ERM) & BM_IPU_DI0_SSC_DI0_PIN16_ERM)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PIN16_ERM field to a new value.
|
|
#define BW_IPU_DI0_SSC_DI0_PIN16_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN16_ERM) | BF_IPU_DI0_SSC_DI0_PIN16_ERM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_SSC, field DI0_PIN17_ERM[23] (RW)
|
|
*
|
|
* DI0 PIN17 error recovery mode. This bit defines the error recovery mode of the PIN17 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN17 pin following a display error detection
|
|
* - 1 - The PIN17 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SSC_DI0_PIN17_ERM (23) //!< Bit position for IPU_DI0_SSC_DI0_PIN17_ERM.
|
|
#define BM_IPU_DI0_SSC_DI0_PIN17_ERM (0x00800000) //!< Bit mask for IPU_DI0_SSC_DI0_PIN17_ERM.
|
|
|
|
//! @brief Get value of IPU_DI0_SSC_DI0_PIN17_ERM from a register value.
|
|
#define BG_IPU_DI0_SSC_DI0_PIN17_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SSC_DI0_PIN17_ERM) >> BP_IPU_DI0_SSC_DI0_PIN17_ERM)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SSC_DI0_PIN17_ERM.
|
|
#define BF_IPU_DI0_SSC_DI0_PIN17_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SSC_DI0_PIN17_ERM) & BM_IPU_DI0_SSC_DI0_PIN17_ERM)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_PIN17_ERM field to a new value.
|
|
#define BW_IPU_DI0_SSC_DI0_PIN17_ERM(x, v) (HW_IPU_DI0_SSC_WR(x, (HW_IPU_DI0_SSC_RD(x) & ~BM_IPU_DI0_SSC_DI0_PIN17_ERM) | BF_IPU_DI0_SSC_DI0_PIN17_ERM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_POL - DI0 Polarity Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_POL - DI0 Polarity Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_pol
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_pol_bitfields
|
|
{
|
|
unsigned DI0_DRDY_POLARITY : 7; //!< [6:0] DI0 output dynamic pin's polarity for synchronous access
|
|
unsigned DI0_DRDY_DATA_POLARITY : 1; //!< [7] Data Polarity associated with DRDY
|
|
unsigned DI0_CS0_POLARITY : 7; //!< [14:8] DI0 output pin's polarity for CS1
|
|
unsigned DI0_CS0_DATA_POLARITY : 1; //!< [15] Data Polarity associated with CS0
|
|
unsigned DI0_CS1_POLARITY : 7; //!< [22:16] DI0 output pin's polarity for CS1
|
|
unsigned DI0_CS1_DATA_POLARITY : 1; //!< [23] Data Polarity associated with CS1
|
|
unsigned DI0_CS0_BYTE_EN_POLARITY : 1; //!< [24] Byte Enable associated with CS0 polarity
|
|
unsigned DI0_CS1_BYTE_EN_POLARITY : 1; //!< [25] Byte Enable associated with CS1 polarity
|
|
unsigned DI0_WAIT_POLARITY : 1; //!< [26] WAIT polarity
|
|
unsigned RESERVED0 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_pol_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_POL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_POL_ADDR(x) (REGS_IPU_BASE(x) + 0x40164)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_POL(x) (*(volatile hw_ipu_di0_pol_t *) HW_IPU_DI0_POL_ADDR(x))
|
|
#define HW_IPU_DI0_POL_RD(x) (HW_IPU_DI0_POL(x).U)
|
|
#define HW_IPU_DI0_POL_WR(x, v) (HW_IPU_DI0_POL(x).U = (v))
|
|
#define HW_IPU_DI0_POL_SET(x, v) (HW_IPU_DI0_POL_WR(x, HW_IPU_DI0_POL_RD(x) | (v)))
|
|
#define HW_IPU_DI0_POL_CLR(x, v) (HW_IPU_DI0_POL_WR(x, HW_IPU_DI0_POL_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_POL_TOG(x, v) (HW_IPU_DI0_POL_WR(x, HW_IPU_DI0_POL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_POL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_DRDY_POLARITY[6:0] (RW)
|
|
*
|
|
* DI0 output dynamic pin's polarity for synchronous access This bits define the polarity of each of
|
|
* the DI's outputs when synchronous display access is asserted The pins' default polarity is the
|
|
* same as defined in the di0_drdy_polarity bits
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_DRDY_POLARITY (0) //!< Bit position for IPU_DI0_POL_DI0_DRDY_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_DRDY_POLARITY (0x0000007f) //!< Bit mask for IPU_DI0_POL_DI0_DRDY_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_DRDY_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_DRDY_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_DRDY_POLARITY) >> BP_IPU_DI0_POL_DI0_DRDY_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_DRDY_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_DRDY_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_DRDY_POLARITY) & BM_IPU_DI0_POL_DI0_DRDY_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DRDY_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_DRDY_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_DRDY_POLARITY) | BF_IPU_DI0_POL_DI0_DRDY_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_DRDY_DATA_POLARITY[7] (RW)
|
|
*
|
|
* Data Polarity associated with DRDY
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY (7) //!< Bit position for IPU_DI0_POL_DI0_DRDY_DATA_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY (0x00000080) //!< Bit mask for IPU_DI0_POL_DI0_DRDY_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_DRDY_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY) >> BP_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_DRDY_DATA_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY) & BM_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_DRDY_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY) | BF_IPU_DI0_POL_DI0_DRDY_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_CS0_POLARITY[14:8] (RW)
|
|
*
|
|
* DI0 output pin's polarity for CS1 This bits define the polarity of each of the DI's outputs when
|
|
* CS1 is asserted
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_CS0_POLARITY (8) //!< Bit position for IPU_DI0_POL_DI0_CS0_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_CS0_POLARITY (0x00007f00) //!< Bit mask for IPU_DI0_POL_DI0_CS0_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_CS0_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_CS0_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_CS0_POLARITY) >> BP_IPU_DI0_POL_DI0_CS0_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_CS0_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_CS0_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_CS0_POLARITY) & BM_IPU_DI0_POL_DI0_CS0_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CS0_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_CS0_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_CS0_POLARITY) | BF_IPU_DI0_POL_DI0_CS0_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_CS0_DATA_POLARITY[15] (RW)
|
|
*
|
|
* Data Polarity associated with CS0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_CS0_DATA_POLARITY (15) //!< Bit position for IPU_DI0_POL_DI0_CS0_DATA_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_CS0_DATA_POLARITY (0x00008000) //!< Bit mask for IPU_DI0_POL_DI0_CS0_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_CS0_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_CS0_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_CS0_DATA_POLARITY) >> BP_IPU_DI0_POL_DI0_CS0_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_CS0_DATA_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_CS0_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_CS0_DATA_POLARITY) & BM_IPU_DI0_POL_DI0_CS0_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CS0_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_CS0_DATA_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_CS0_DATA_POLARITY) | BF_IPU_DI0_POL_DI0_CS0_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_CS1_POLARITY[22:16] (RW)
|
|
*
|
|
* DI0 output pin's polarity for CS1 This bits define the polarity of each of the DI's outputs when
|
|
* CS1 is asserted
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_CS1_POLARITY (16) //!< Bit position for IPU_DI0_POL_DI0_CS1_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_CS1_POLARITY (0x007f0000) //!< Bit mask for IPU_DI0_POL_DI0_CS1_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_CS1_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_CS1_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_CS1_POLARITY) >> BP_IPU_DI0_POL_DI0_CS1_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_CS1_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_CS1_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_CS1_POLARITY) & BM_IPU_DI0_POL_DI0_CS1_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CS1_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_CS1_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_CS1_POLARITY) | BF_IPU_DI0_POL_DI0_CS1_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_CS1_DATA_POLARITY[23] (RW)
|
|
*
|
|
* Data Polarity associated with CS1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_CS1_DATA_POLARITY (23) //!< Bit position for IPU_DI0_POL_DI0_CS1_DATA_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_CS1_DATA_POLARITY (0x00800000) //!< Bit mask for IPU_DI0_POL_DI0_CS1_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_CS1_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_CS1_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_CS1_DATA_POLARITY) >> BP_IPU_DI0_POL_DI0_CS1_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_CS1_DATA_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_CS1_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_CS1_DATA_POLARITY) & BM_IPU_DI0_POL_DI0_CS1_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CS1_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_CS1_DATA_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_CS1_DATA_POLARITY) | BF_IPU_DI0_POL_DI0_CS1_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_CS0_BYTE_EN_POLARITY[24] (RW)
|
|
*
|
|
* Byte Enable associated with CS0 polarity This bit defines the polarity of the byte enable signals
|
|
* to the display
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY (24) //!< Bit position for IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY (0x01000000) //!< Bit mask for IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY) >> BP_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY) & BM_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CS0_BYTE_EN_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY) | BF_IPU_DI0_POL_DI0_CS0_BYTE_EN_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_CS1_BYTE_EN_POLARITY[25] (RW)
|
|
*
|
|
* Byte Enable associated with CS1 polarity This bit defines the polarity of the byte enable signals
|
|
* to the display
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY (25) //!< Bit position for IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY (0x02000000) //!< Bit mask for IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY) >> BP_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY) & BM_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_CS1_BYTE_EN_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY) | BF_IPU_DI0_POL_DI0_CS1_BYTE_EN_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_POL, field DI0_WAIT_POLARITY[26] (RW)
|
|
*
|
|
* WAIT polarity This bit defines the polarity of the wait signal input coming from the displa1
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_POL_DI0_WAIT_POLARITY (26) //!< Bit position for IPU_DI0_POL_DI0_WAIT_POLARITY.
|
|
#define BM_IPU_DI0_POL_DI0_WAIT_POLARITY (0x04000000) //!< Bit mask for IPU_DI0_POL_DI0_WAIT_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI0_POL_DI0_WAIT_POLARITY from a register value.
|
|
#define BG_IPU_DI0_POL_DI0_WAIT_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_POL_DI0_WAIT_POLARITY) >> BP_IPU_DI0_POL_DI0_WAIT_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_POL_DI0_WAIT_POLARITY.
|
|
#define BF_IPU_DI0_POL_DI0_WAIT_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_POL_DI0_WAIT_POLARITY) & BM_IPU_DI0_POL_DI0_WAIT_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_WAIT_POLARITY field to a new value.
|
|
#define BW_IPU_DI0_POL_DI0_WAIT_POLARITY(x, v) (HW_IPU_DI0_POL_WR(x, (HW_IPU_DI0_POL_RD(x) & ~BM_IPU_DI0_POL_DI0_WAIT_POLARITY) | BF_IPU_DI0_POL_DI0_WAIT_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_AW0 - DI0 Active Window 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_AW0 - DI0 Active Window 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_aw0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_aw0_bitfields
|
|
{
|
|
unsigned DI0_AW_HSTART : 12; //!< [11:0] This field defines the horizontal start of the active window
|
|
unsigned DI0_AW_HCOUNT_SEL : 4; //!< [15:12] GM: This field selects the counter that counts the horizontal position of the display's active window
|
|
unsigned DI0_AW_HEND : 12; //!< [27:16] This field defines the horizontal end of the active window
|
|
unsigned DI0_AW_TRIG_SEL : 4; //!< [31:28] This field selects the trigger for sending data during the display's active window
|
|
} B;
|
|
} hw_ipu_di0_aw0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_AW0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_AW0_ADDR(x) (REGS_IPU_BASE(x) + 0x40168)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_AW0(x) (*(volatile hw_ipu_di0_aw0_t *) HW_IPU_DI0_AW0_ADDR(x))
|
|
#define HW_IPU_DI0_AW0_RD(x) (HW_IPU_DI0_AW0(x).U)
|
|
#define HW_IPU_DI0_AW0_WR(x, v) (HW_IPU_DI0_AW0(x).U = (v))
|
|
#define HW_IPU_DI0_AW0_SET(x, v) (HW_IPU_DI0_AW0_WR(x, HW_IPU_DI0_AW0_RD(x) | (v)))
|
|
#define HW_IPU_DI0_AW0_CLR(x, v) (HW_IPU_DI0_AW0_WR(x, HW_IPU_DI0_AW0_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_AW0_TOG(x, v) (HW_IPU_DI0_AW0_WR(x, HW_IPU_DI0_AW0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_AW0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_AW0, field DI0_AW_HSTART[11:0] (RW)
|
|
*
|
|
* This field defines the horizontal start of the active window DI0_AW_HSTART < DI0_AW_HEND
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW0_DI0_AW_HSTART (0) //!< Bit position for IPU_DI0_AW0_DI0_AW_HSTART.
|
|
#define BM_IPU_DI0_AW0_DI0_AW_HSTART (0x00000fff) //!< Bit mask for IPU_DI0_AW0_DI0_AW_HSTART.
|
|
|
|
//! @brief Get value of IPU_DI0_AW0_DI0_AW_HSTART from a register value.
|
|
#define BG_IPU_DI0_AW0_DI0_AW_HSTART(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW0_DI0_AW_HSTART) >> BP_IPU_DI0_AW0_DI0_AW_HSTART)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW0_DI0_AW_HSTART.
|
|
#define BF_IPU_DI0_AW0_DI0_AW_HSTART(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW0_DI0_AW_HSTART) & BM_IPU_DI0_AW0_DI0_AW_HSTART)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_HSTART field to a new value.
|
|
#define BW_IPU_DI0_AW0_DI0_AW_HSTART(x, v) (HW_IPU_DI0_AW0_WR(x, (HW_IPU_DI0_AW0_RD(x) & ~BM_IPU_DI0_AW0_DI0_AW_HSTART) | BF_IPU_DI0_AW0_DI0_AW_HSTART(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_AW0, field DI0_AW_HCOUNT_SEL[15:12] (RW)
|
|
*
|
|
* GM: This field selects the counter that counts the horizontal position of the display's active
|
|
* window
|
|
*
|
|
* Values:
|
|
* - 0000 - disabled
|
|
* - 0001 - reserved
|
|
* - 0010 - The counter is counter #1
|
|
* - 0011 - The counter is counter #2
|
|
* - 0100 - The counter is counter #3
|
|
* - 0101 - The counter is counter #4
|
|
* - 0110 - The counter is counter #5
|
|
* - 1001 - The counter is counter #8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL (12) //!< Bit position for IPU_DI0_AW0_DI0_AW_HCOUNT_SEL.
|
|
#define BM_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL (0x0000f000) //!< Bit mask for IPU_DI0_AW0_DI0_AW_HCOUNT_SEL.
|
|
|
|
//! @brief Get value of IPU_DI0_AW0_DI0_AW_HCOUNT_SEL from a register value.
|
|
#define BG_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL) >> BP_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW0_DI0_AW_HCOUNT_SEL.
|
|
#define BF_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL) & BM_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_HCOUNT_SEL field to a new value.
|
|
#define BW_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL(x, v) (HW_IPU_DI0_AW0_WR(x, (HW_IPU_DI0_AW0_RD(x) & ~BM_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL) | BF_IPU_DI0_AW0_DI0_AW_HCOUNT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_AW0, field DI0_AW_HEND[27:16] (RW)
|
|
*
|
|
* This field defines the horizontal end of the active window
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW0_DI0_AW_HEND (16) //!< Bit position for IPU_DI0_AW0_DI0_AW_HEND.
|
|
#define BM_IPU_DI0_AW0_DI0_AW_HEND (0x0fff0000) //!< Bit mask for IPU_DI0_AW0_DI0_AW_HEND.
|
|
|
|
//! @brief Get value of IPU_DI0_AW0_DI0_AW_HEND from a register value.
|
|
#define BG_IPU_DI0_AW0_DI0_AW_HEND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW0_DI0_AW_HEND) >> BP_IPU_DI0_AW0_DI0_AW_HEND)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW0_DI0_AW_HEND.
|
|
#define BF_IPU_DI0_AW0_DI0_AW_HEND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW0_DI0_AW_HEND) & BM_IPU_DI0_AW0_DI0_AW_HEND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_HEND field to a new value.
|
|
#define BW_IPU_DI0_AW0_DI0_AW_HEND(x, v) (HW_IPU_DI0_AW0_WR(x, (HW_IPU_DI0_AW0_RD(x) & ~BM_IPU_DI0_AW0_DI0_AW_HEND) | BF_IPU_DI0_AW0_DI0_AW_HEND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_AW0, field DI0_AW_TRIG_SEL[31:28] (RW)
|
|
*
|
|
* This field selects the trigger for sending data during the display's active window
|
|
*
|
|
* Values:
|
|
* - 000 - disabled
|
|
* - 001 - The trigger is the same trigger that triggers the displays clock.
|
|
* - 010 - The trigger is counter #1
|
|
* - 011 - The trigger is counter #2
|
|
* - 100 - The trigger is counter #3
|
|
* - 101 - The trigger is counter #4
|
|
* - 110 - The trigger is counter #5
|
|
* - 111 - The trigger is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW0_DI0_AW_TRIG_SEL (28) //!< Bit position for IPU_DI0_AW0_DI0_AW_TRIG_SEL.
|
|
#define BM_IPU_DI0_AW0_DI0_AW_TRIG_SEL (0xf0000000) //!< Bit mask for IPU_DI0_AW0_DI0_AW_TRIG_SEL.
|
|
|
|
//! @brief Get value of IPU_DI0_AW0_DI0_AW_TRIG_SEL from a register value.
|
|
#define BG_IPU_DI0_AW0_DI0_AW_TRIG_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW0_DI0_AW_TRIG_SEL) >> BP_IPU_DI0_AW0_DI0_AW_TRIG_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW0_DI0_AW_TRIG_SEL.
|
|
#define BF_IPU_DI0_AW0_DI0_AW_TRIG_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW0_DI0_AW_TRIG_SEL) & BM_IPU_DI0_AW0_DI0_AW_TRIG_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_TRIG_SEL field to a new value.
|
|
#define BW_IPU_DI0_AW0_DI0_AW_TRIG_SEL(x, v) (HW_IPU_DI0_AW0_WR(x, (HW_IPU_DI0_AW0_RD(x) & ~BM_IPU_DI0_AW0_DI0_AW_TRIG_SEL) | BF_IPU_DI0_AW0_DI0_AW_TRIG_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_AW1 - DI0 Active Window 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_AW1 - DI0 Active Window 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_aw1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_aw1_bitfields
|
|
{
|
|
unsigned DI0_AW_VSTART : 12; //!< [11:0] This field defines the vertical start of the active window
|
|
unsigned DI0_AW_VCOUNT_SEL : 4; //!< [15:12] This field selects the counter that counts the vertical position of the display's active window
|
|
unsigned DI0_AW_VEND : 12; //!< [27:16] This field defines the vertical end of the active window
|
|
unsigned RESERVED0 : 4; //!< [31:28] Reserved
|
|
} B;
|
|
} hw_ipu_di0_aw1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_AW1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_AW1_ADDR(x) (REGS_IPU_BASE(x) + 0x4016c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_AW1(x) (*(volatile hw_ipu_di0_aw1_t *) HW_IPU_DI0_AW1_ADDR(x))
|
|
#define HW_IPU_DI0_AW1_RD(x) (HW_IPU_DI0_AW1(x).U)
|
|
#define HW_IPU_DI0_AW1_WR(x, v) (HW_IPU_DI0_AW1(x).U = (v))
|
|
#define HW_IPU_DI0_AW1_SET(x, v) (HW_IPU_DI0_AW1_WR(x, HW_IPU_DI0_AW1_RD(x) | (v)))
|
|
#define HW_IPU_DI0_AW1_CLR(x, v) (HW_IPU_DI0_AW1_WR(x, HW_IPU_DI0_AW1_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_AW1_TOG(x, v) (HW_IPU_DI0_AW1_WR(x, HW_IPU_DI0_AW1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_AW1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_AW1, field DI0_AW_VSTART[11:0] (RW)
|
|
*
|
|
* This field defines the vertical start of the active window DI0_AW_VSTART < DI0_AW_VEND
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW1_DI0_AW_VSTART (0) //!< Bit position for IPU_DI0_AW1_DI0_AW_VSTART.
|
|
#define BM_IPU_DI0_AW1_DI0_AW_VSTART (0x00000fff) //!< Bit mask for IPU_DI0_AW1_DI0_AW_VSTART.
|
|
|
|
//! @brief Get value of IPU_DI0_AW1_DI0_AW_VSTART from a register value.
|
|
#define BG_IPU_DI0_AW1_DI0_AW_VSTART(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW1_DI0_AW_VSTART) >> BP_IPU_DI0_AW1_DI0_AW_VSTART)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW1_DI0_AW_VSTART.
|
|
#define BF_IPU_DI0_AW1_DI0_AW_VSTART(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW1_DI0_AW_VSTART) & BM_IPU_DI0_AW1_DI0_AW_VSTART)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_VSTART field to a new value.
|
|
#define BW_IPU_DI0_AW1_DI0_AW_VSTART(x, v) (HW_IPU_DI0_AW1_WR(x, (HW_IPU_DI0_AW1_RD(x) & ~BM_IPU_DI0_AW1_DI0_AW_VSTART) | BF_IPU_DI0_AW1_DI0_AW_VSTART(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_AW1, field DI0_AW_VCOUNT_SEL[15:12] (RW)
|
|
*
|
|
* This field selects the counter that counts the vertical position of the display's active window
|
|
*
|
|
* Values:
|
|
* - 0000 - disabled
|
|
* - 0001 - reserved
|
|
* - 0010 - The counter is counter #1
|
|
* - 0011 - The counter is counter #2
|
|
* - 0100 - The counter is counter #3
|
|
* - 0101 - The counter is counter #4
|
|
* - 0110 - The counter is counter #5
|
|
* - 1001 - The counter is counter #8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL (12) //!< Bit position for IPU_DI0_AW1_DI0_AW_VCOUNT_SEL.
|
|
#define BM_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL (0x0000f000) //!< Bit mask for IPU_DI0_AW1_DI0_AW_VCOUNT_SEL.
|
|
|
|
//! @brief Get value of IPU_DI0_AW1_DI0_AW_VCOUNT_SEL from a register value.
|
|
#define BG_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL) >> BP_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW1_DI0_AW_VCOUNT_SEL.
|
|
#define BF_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL) & BM_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_VCOUNT_SEL field to a new value.
|
|
#define BW_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL(x, v) (HW_IPU_DI0_AW1_WR(x, (HW_IPU_DI0_AW1_RD(x) & ~BM_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL) | BF_IPU_DI0_AW1_DI0_AW_VCOUNT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_AW1, field DI0_AW_VEND[27:16] (RW)
|
|
*
|
|
* This field defines the vertical end of the active window
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_AW1_DI0_AW_VEND (16) //!< Bit position for IPU_DI0_AW1_DI0_AW_VEND.
|
|
#define BM_IPU_DI0_AW1_DI0_AW_VEND (0x0fff0000) //!< Bit mask for IPU_DI0_AW1_DI0_AW_VEND.
|
|
|
|
//! @brief Get value of IPU_DI0_AW1_DI0_AW_VEND from a register value.
|
|
#define BG_IPU_DI0_AW1_DI0_AW_VEND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_AW1_DI0_AW_VEND) >> BP_IPU_DI0_AW1_DI0_AW_VEND)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_AW1_DI0_AW_VEND.
|
|
#define BF_IPU_DI0_AW1_DI0_AW_VEND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_AW1_DI0_AW_VEND) & BM_IPU_DI0_AW1_DI0_AW_VEND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_AW_VEND field to a new value.
|
|
#define BW_IPU_DI0_AW1_DI0_AW_VEND(x, v) (HW_IPU_DI0_AW1_WR(x, (HW_IPU_DI0_AW1_RD(x) & ~BM_IPU_DI0_AW1_DI0_AW_VEND) | BF_IPU_DI0_AW1_DI0_AW_VEND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_SCR_CONF - DI0 Screen Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_SCR_CONF - DI0 Screen Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di0_scr_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_scr_conf_bitfields
|
|
{
|
|
unsigned DI0_SCREEN_HEIGHT : 12; //!< [11:0] This field defines the number of display rows (Number_of_ROWS = DI0_SCREEN_HEIGHT+1)
|
|
unsigned RESERVED0 : 20; //!< [31:12] Reserved.
|
|
} B;
|
|
} hw_ipu_di0_scr_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_SCR_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_SCR_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x40170)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_SCR_CONF(x) (*(volatile hw_ipu_di0_scr_conf_t *) HW_IPU_DI0_SCR_CONF_ADDR(x))
|
|
#define HW_IPU_DI0_SCR_CONF_RD(x) (HW_IPU_DI0_SCR_CONF(x).U)
|
|
#define HW_IPU_DI0_SCR_CONF_WR(x, v) (HW_IPU_DI0_SCR_CONF(x).U = (v))
|
|
#define HW_IPU_DI0_SCR_CONF_SET(x, v) (HW_IPU_DI0_SCR_CONF_WR(x, HW_IPU_DI0_SCR_CONF_RD(x) | (v)))
|
|
#define HW_IPU_DI0_SCR_CONF_CLR(x, v) (HW_IPU_DI0_SCR_CONF_WR(x, HW_IPU_DI0_SCR_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_DI0_SCR_CONF_TOG(x, v) (HW_IPU_DI0_SCR_CONF_WR(x, HW_IPU_DI0_SCR_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_SCR_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_SCR_CONF, field DI0_SCREEN_HEIGHT[11:0] (RW)
|
|
*
|
|
* This field defines the number of display rows (Number_of_ROWS = DI0_SCREEN_HEIGHT+1) This field
|
|
* is used for VSYNC calculation and for anti-tearing
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT (0) //!< Bit position for IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT.
|
|
#define BM_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT (0x00000fff) //!< Bit mask for IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT from a register value.
|
|
#define BG_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT) >> BP_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT.
|
|
#define BF_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT) & BM_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI0_SCREEN_HEIGHT field to a new value.
|
|
#define BW_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT(x, v) (HW_IPU_DI0_SCR_CONF_WR(x, (HW_IPU_DI0_SCR_CONF_RD(x) & ~BM_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT) | BF_IPU_DI0_SCR_CONF_DI0_SCREEN_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI0_STAT - DI0 Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI0_STAT - DI0 Status Register (RO)
|
|
*
|
|
* Reset value: 0x00000005
|
|
*/
|
|
typedef union _hw_ipu_di0_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di0_stat_bitfields
|
|
{
|
|
unsigned DI0_READ_FIFO_EMPTY : 1; //!< [0] This bit indicates an empty state of the DI0 FIFO when performing a read.
|
|
unsigned DI0_READ_FIFO_FULL : 1; //!< [1] This bit indicates a full state of the DI0 FIFO when performing a read.
|
|
unsigned DI0_READ_CNTR_EMPTY : 1; //!< [2] This bit indicates an empty state of the DI0 FIFO.
|
|
unsigned DI0_CNTR_FIFO_FULL : 1; //!< [3] This bit indicates a full state of the DI0 FIFO.
|
|
unsigned RESERVED0 : 28; //!< [31:4] Reserved
|
|
} B;
|
|
} hw_ipu_di0_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI0_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI0_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x40174)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI0_STAT(x) (*(volatile hw_ipu_di0_stat_t *) HW_IPU_DI0_STAT_ADDR(x))
|
|
#define HW_IPU_DI0_STAT_RD(x) (HW_IPU_DI0_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI0_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI0_STAT, field DI0_READ_FIFO_EMPTY[0] (RO)
|
|
*
|
|
* This bit indicates an empty state of the DI0 FIFO when performing a read. This FIFO is part of
|
|
* the DI0 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_STAT_DI0_READ_FIFO_EMPTY (0) //!< Bit position for IPU_DI0_STAT_DI0_READ_FIFO_EMPTY.
|
|
#define BM_IPU_DI0_STAT_DI0_READ_FIFO_EMPTY (0x00000001) //!< Bit mask for IPU_DI0_STAT_DI0_READ_FIFO_EMPTY.
|
|
|
|
//! @brief Get value of IPU_DI0_STAT_DI0_READ_FIFO_EMPTY from a register value.
|
|
#define BG_IPU_DI0_STAT_DI0_READ_FIFO_EMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STAT_DI0_READ_FIFO_EMPTY) >> BP_IPU_DI0_STAT_DI0_READ_FIFO_EMPTY)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_STAT, field DI0_READ_FIFO_FULL[1] (RO)
|
|
*
|
|
* This bit indicates a full state of the DI0 FIFO when performing a read. This FIFO is part of the
|
|
* DI0 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_STAT_DI0_READ_FIFO_FULL (1) //!< Bit position for IPU_DI0_STAT_DI0_READ_FIFO_FULL.
|
|
#define BM_IPU_DI0_STAT_DI0_READ_FIFO_FULL (0x00000002) //!< Bit mask for IPU_DI0_STAT_DI0_READ_FIFO_FULL.
|
|
|
|
//! @brief Get value of IPU_DI0_STAT_DI0_READ_FIFO_FULL from a register value.
|
|
#define BG_IPU_DI0_STAT_DI0_READ_FIFO_FULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STAT_DI0_READ_FIFO_FULL) >> BP_IPU_DI0_STAT_DI0_READ_FIFO_FULL)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_STAT, field DI0_READ_CNTR_EMPTY[2] (RO)
|
|
*
|
|
* This bit indicates an empty state of the DI0 FIFO. This FIFO is part of the DI0 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_STAT_DI0_READ_CNTR_EMPTY (2) //!< Bit position for IPU_DI0_STAT_DI0_READ_CNTR_EMPTY.
|
|
#define BM_IPU_DI0_STAT_DI0_READ_CNTR_EMPTY (0x00000004) //!< Bit mask for IPU_DI0_STAT_DI0_READ_CNTR_EMPTY.
|
|
|
|
//! @brief Get value of IPU_DI0_STAT_DI0_READ_CNTR_EMPTY from a register value.
|
|
#define BG_IPU_DI0_STAT_DI0_READ_CNTR_EMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STAT_DI0_READ_CNTR_EMPTY) >> BP_IPU_DI0_STAT_DI0_READ_CNTR_EMPTY)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI0_STAT, field DI0_CNTR_FIFO_FULL[3] (RO)
|
|
*
|
|
* This bit indicates a full state of the DI0 FIFO. This FIFO is part of the DI0 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI0_STAT_DI0_CNTR_FIFO_FULL (3) //!< Bit position for IPU_DI0_STAT_DI0_CNTR_FIFO_FULL.
|
|
#define BM_IPU_DI0_STAT_DI0_CNTR_FIFO_FULL (0x00000008) //!< Bit mask for IPU_DI0_STAT_DI0_CNTR_FIFO_FULL.
|
|
|
|
//! @brief Get value of IPU_DI0_STAT_DI0_CNTR_FIFO_FULL from a register value.
|
|
#define BG_IPU_DI0_STAT_DI0_CNTR_FIFO_FULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI0_STAT_DI0_CNTR_FIFO_FULL) >> BP_IPU_DI0_STAT_DI0_CNTR_FIFO_FULL)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_GENERAL - DI1General Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_GENERAL - DI1General Register (RW)
|
|
*
|
|
* Reset value: 0x00200000
|
|
*/
|
|
typedef union _hw_ipu_di1_general
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_general_bitfields
|
|
{
|
|
unsigned DI1_POLARITY_I_1 : 8; //!< [7:0] DI1 output pin's polarity
|
|
unsigned DI1_POLARITY_CS0 : 1; //!< [8] DI1 Chip Select's 0 polarity
|
|
unsigned DI1_POLARITY_CS1 : 1; //!< [9] DI1 Chip Select's 1 polarity
|
|
unsigned DI1_ERM_VSYNC_SEL : 1; //!< [10] DI1 error recovery module's VSYNC source select
|
|
unsigned DI1_ERR_TREATMENT : 1; //!< [11] In case of synchronous flow error there are 2 ways to handle the display
|
|
unsigned DI1_SYNC_COUNT_SEL : 4; //!< [15:12] For synchronous flow error: selects synchronous flow synchronization counter in DI:
|
|
unsigned RESERVED0 : 1; //!< [16] Reserved
|
|
unsigned DI1_POLARITY_DISP_CLK : 1; //!< [17] DI1 Output Clock's polarity
|
|
unsigned DI1_WATCHDOG_MODE : 2; //!< [19:18] DI1 watchdog mode
|
|
unsigned DI1_CLK_EXT : 1; //!< [20] DI1 External Clock.
|
|
unsigned DI1_VSYNC_EXT : 1; //!< [21] DI1 External VSYNC.
|
|
unsigned DI1_MASK_SEL : 1; //!< [22] DI1 Mask select.
|
|
unsigned DI1_DISP_CLOCK_INIT : 1; //!< [23] Display clock's initial mode
|
|
unsigned DI1_CLOCK_STOP_MODE : 4; //!< [27:24] DI clock stop mode
|
|
unsigned DI1_DISP_Y_SEL : 3; //!< [30:28] DI1 Display Vertical coordinate (Y) select.
|
|
unsigned DI1_PIN8_PIN15_SEL : 1; //!< [31] This bit routes PIN8 over PIN15
|
|
} B;
|
|
} hw_ipu_di1_general_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_GENERAL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_GENERAL_ADDR(x) (REGS_IPU_BASE(x) + 0x48000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_GENERAL(x) (*(volatile hw_ipu_di1_general_t *) HW_IPU_DI1_GENERAL_ADDR(x))
|
|
#define HW_IPU_DI1_GENERAL_RD(x) (HW_IPU_DI1_GENERAL(x).U)
|
|
#define HW_IPU_DI1_GENERAL_WR(x, v) (HW_IPU_DI1_GENERAL(x).U = (v))
|
|
#define HW_IPU_DI1_GENERAL_SET(x, v) (HW_IPU_DI1_GENERAL_WR(x, HW_IPU_DI1_GENERAL_RD(x) | (v)))
|
|
#define HW_IPU_DI1_GENERAL_CLR(x, v) (HW_IPU_DI1_GENERAL_WR(x, HW_IPU_DI1_GENERAL_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_GENERAL_TOG(x, v) (HW_IPU_DI1_GENERAL_WR(x, HW_IPU_DI1_GENERAL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_GENERAL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_POLARITY_I_1[7:0] (RW)
|
|
*
|
|
* DI1 output pin's polarity This bits define the polarity of each of the DI's outputs.
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_POLARITY_I_1 (0) //!< Bit position for IPU_DI1_GENERAL_DI1_POLARITY_I_1.
|
|
#define BM_IPU_DI1_GENERAL_DI1_POLARITY_I_1 (0x000000ff) //!< Bit mask for IPU_DI1_GENERAL_DI1_POLARITY_I_1.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_POLARITY_I_1 from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_POLARITY_I_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_POLARITY_I_1) >> BP_IPU_DI1_GENERAL_DI1_POLARITY_I_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_POLARITY_I_1.
|
|
#define BF_IPU_DI1_GENERAL_DI1_POLARITY_I_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_POLARITY_I_1) & BM_IPU_DI1_GENERAL_DI1_POLARITY_I_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_POLARITY_I_1 field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_POLARITY_I_1(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_POLARITY_I_1) | BF_IPU_DI1_GENERAL_DI1_POLARITY_I_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_POLARITY_CS0[8] (RW)
|
|
*
|
|
* DI1 Chip Select's 0 polarity This bits define the polarity of the DI's CS0.
|
|
*
|
|
* Values:
|
|
* - 0 - The CS0 is active low
|
|
* - 1 - The CS0 is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_POLARITY_CS0 (8) //!< Bit position for IPU_DI1_GENERAL_DI1_POLARITY_CS0.
|
|
#define BM_IPU_DI1_GENERAL_DI1_POLARITY_CS0 (0x00000100) //!< Bit mask for IPU_DI1_GENERAL_DI1_POLARITY_CS0.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_POLARITY_CS0 from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_POLARITY_CS0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_POLARITY_CS0) >> BP_IPU_DI1_GENERAL_DI1_POLARITY_CS0)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_POLARITY_CS0.
|
|
#define BF_IPU_DI1_GENERAL_DI1_POLARITY_CS0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_POLARITY_CS0) & BM_IPU_DI1_GENERAL_DI1_POLARITY_CS0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_POLARITY_CS0 field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_POLARITY_CS0(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_POLARITY_CS0) | BF_IPU_DI1_GENERAL_DI1_POLARITY_CS0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_POLARITY_CS1[9] (RW)
|
|
*
|
|
* DI1 Chip Select's 1 polarity This bits define the polarity of the DI's CS1.
|
|
*
|
|
* Values:
|
|
* - 0 - The CS1 is active low
|
|
* - 1 - The CS1 is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_POLARITY_CS1 (9) //!< Bit position for IPU_DI1_GENERAL_DI1_POLARITY_CS1.
|
|
#define BM_IPU_DI1_GENERAL_DI1_POLARITY_CS1 (0x00000200) //!< Bit mask for IPU_DI1_GENERAL_DI1_POLARITY_CS1.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_POLARITY_CS1 from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_POLARITY_CS1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_POLARITY_CS1) >> BP_IPU_DI1_GENERAL_DI1_POLARITY_CS1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_POLARITY_CS1.
|
|
#define BF_IPU_DI1_GENERAL_DI1_POLARITY_CS1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_POLARITY_CS1) & BM_IPU_DI1_GENERAL_DI1_POLARITY_CS1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_POLARITY_CS1 field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_POLARITY_CS1(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_POLARITY_CS1) | BF_IPU_DI1_GENERAL_DI1_POLARITY_CS1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_ERM_VSYNC_SEL[10] (RW)
|
|
*
|
|
* DI1 error recovery module's VSYNC source select The error recovery block detect a case where the
|
|
* DI's VSYNC is asserted before the EOF. This bit selects the source of the VSYNC signal monitored
|
|
* by this mechanism.
|
|
*
|
|
* Values:
|
|
* - 0 - vsync_pre - an internal VSYNC signal asserted 2 lines before the DI's VSYNC
|
|
* - 1 - vsync_post - an internal VSYNC signal asserted 2 lines after the DI's VSYNC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL (10) //!< Bit position for IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL.
|
|
#define BM_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL (0x00000400) //!< Bit mask for IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL) >> BP_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL.
|
|
#define BF_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL) & BM_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_ERM_VSYNC_SEL field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL) | BF_IPU_DI1_GENERAL_DI1_ERM_VSYNC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_ERR_TREATMENT[11] (RW)
|
|
*
|
|
* In case of synchronous flow error there are 2 ways to handle the display
|
|
*
|
|
* Values:
|
|
* - 0 - Drive the last component
|
|
* - 1 - to wait (i.e. stop clock)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_ERR_TREATMENT (11) //!< Bit position for IPU_DI1_GENERAL_DI1_ERR_TREATMENT.
|
|
#define BM_IPU_DI1_GENERAL_DI1_ERR_TREATMENT (0x00000800) //!< Bit mask for IPU_DI1_GENERAL_DI1_ERR_TREATMENT.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_ERR_TREATMENT from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_ERR_TREATMENT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_ERR_TREATMENT) >> BP_IPU_DI1_GENERAL_DI1_ERR_TREATMENT)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_ERR_TREATMENT.
|
|
#define BF_IPU_DI1_GENERAL_DI1_ERR_TREATMENT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_ERR_TREATMENT) & BM_IPU_DI1_GENERAL_DI1_ERR_TREATMENT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_ERR_TREATMENT field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_ERR_TREATMENT(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_ERR_TREATMENT) | BF_IPU_DI1_GENERAL_DI1_ERR_TREATMENT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_SYNC_COUNT_SEL[15:12] (RW)
|
|
*
|
|
* For synchronous flow error: selects synchronous flow synchronization counter in DI:
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL (12) //!< Bit position for IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL.
|
|
#define BM_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL (0x0000f000) //!< Bit mask for IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL) >> BP_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL.
|
|
#define BF_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL) & BM_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SYNC_COUNT_SEL field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL) | BF_IPU_DI1_GENERAL_DI1_SYNC_COUNT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_POLARITY_DISP_CLK[17] (RW)
|
|
*
|
|
* DI1 Output Clock's polarity This bits define the polarity of the DI's clock.
|
|
*
|
|
* Values:
|
|
* - 0 - The output clock is active low
|
|
* - 1 - The output clock is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK (17) //!< Bit position for IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK.
|
|
#define BM_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK (0x00020000) //!< Bit mask for IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK) >> BP_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK.
|
|
#define BF_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK) & BM_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_POLARITY_DISP_CLK field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK) | BF_IPU_DI1_GENERAL_DI1_POLARITY_DISP_CLK(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_WATCHDOG_MODE[19:18] (RW)
|
|
*
|
|
* DI1 watchdog mode In case of a display error where the DI clock is stopped (defined at
|
|
* di0_err_treatment). An internal watchdog counts DI clocks. If this timer reached its pre defined
|
|
* value the DI will skip the current frame and restart on the frame. This 2 bits define the number
|
|
* of DI clock cycles that the timer counts.
|
|
*
|
|
* Values:
|
|
* - 00 - The timer counts 4 DI cycles
|
|
* - 01 - The timer counts 16 DI cycles
|
|
* - 10 - The timer counts 64 DI cycles
|
|
* - 11 - The timer counts 128 DI cycles
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE (18) //!< Bit position for IPU_DI1_GENERAL_DI1_WATCHDOG_MODE.
|
|
#define BM_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE (0x000c0000) //!< Bit mask for IPU_DI1_GENERAL_DI1_WATCHDOG_MODE.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_WATCHDOG_MODE from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE) >> BP_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_WATCHDOG_MODE.
|
|
#define BF_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE) & BM_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_WATCHDOG_MODE field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE) | BF_IPU_DI1_GENERAL_DI1_WATCHDOG_MODE(v)))
|
|
#endif
|
|
//@}
|
|
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/*! @name Register IPU_DI1_GENERAL, field DI1_CLK_EXT[20] (RW)
|
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*
|
|
* DI1 External Clock. This bit selects the source of the DI's clock
|
|
*
|
|
* Values:
|
|
* - 0 - The clock is internally generated by the IPU
|
|
* - 1 - The source of the clock is external to the IPU
|
|
*/
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|
//@{
|
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#define BP_IPU_DI1_GENERAL_DI1_CLK_EXT (20) //!< Bit position for IPU_DI1_GENERAL_DI1_CLK_EXT.
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#define BM_IPU_DI1_GENERAL_DI1_CLK_EXT (0x00100000) //!< Bit mask for IPU_DI1_GENERAL_DI1_CLK_EXT.
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//! @brief Get value of IPU_DI1_GENERAL_DI1_CLK_EXT from a register value.
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|
#define BG_IPU_DI1_GENERAL_DI1_CLK_EXT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_CLK_EXT) >> BP_IPU_DI1_GENERAL_DI1_CLK_EXT)
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//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_CLK_EXT.
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|
#define BF_IPU_DI1_GENERAL_DI1_CLK_EXT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_CLK_EXT) & BM_IPU_DI1_GENERAL_DI1_CLK_EXT)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CLK_EXT field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_CLK_EXT(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_CLK_EXT) | BF_IPU_DI1_GENERAL_DI1_CLK_EXT(v)))
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#endif
|
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//@}
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/*! @name Register IPU_DI1_GENERAL, field DI1_VSYNC_EXT[21] (RW)
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*
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|
* DI1 External VSYNC. This bit selects the source of the VSYNC signal
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*
|
|
* Values:
|
|
* - 0 - Internally generated by the IPU
|
|
* - 1 - External to the IPU
|
|
*/
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|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_VSYNC_EXT (21) //!< Bit position for IPU_DI1_GENERAL_DI1_VSYNC_EXT.
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#define BM_IPU_DI1_GENERAL_DI1_VSYNC_EXT (0x00200000) //!< Bit mask for IPU_DI1_GENERAL_DI1_VSYNC_EXT.
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//! @brief Get value of IPU_DI1_GENERAL_DI1_VSYNC_EXT from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_VSYNC_EXT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_VSYNC_EXT) >> BP_IPU_DI1_GENERAL_DI1_VSYNC_EXT)
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//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_VSYNC_EXT.
|
|
#define BF_IPU_DI1_GENERAL_DI1_VSYNC_EXT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_VSYNC_EXT) & BM_IPU_DI1_GENERAL_DI1_VSYNC_EXT)
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|
|
#ifndef __LANGUAGE_ASM__
|
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//! @brief Set the DI1_VSYNC_EXT field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_VSYNC_EXT(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_VSYNC_EXT) | BF_IPU_DI1_GENERAL_DI1_VSYNC_EXT(v)))
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#endif
|
|
//@}
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/*! @name Register IPU_DI1_GENERAL, field DI1_MASK_SEL[22] (RW)
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|
*
|
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* DI1 Mask select. IPP_PIN_2 output of the DI that functions as MASK signal can come from 2
|
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* sources: counter #2 or extracted from the MASK data coming from the memory.
|
|
*
|
|
* Values:
|
|
* - 0 - IPP_PIN_2 is coming from counter #2
|
|
* - 1 - IPP_PIN_2 is coming from extracted MASK data coming from the memory
|
|
*/
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|
//@{
|
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#define BP_IPU_DI1_GENERAL_DI1_MASK_SEL (22) //!< Bit position for IPU_DI1_GENERAL_DI1_MASK_SEL.
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#define BM_IPU_DI1_GENERAL_DI1_MASK_SEL (0x00400000) //!< Bit mask for IPU_DI1_GENERAL_DI1_MASK_SEL.
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//! @brief Get value of IPU_DI1_GENERAL_DI1_MASK_SEL from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_MASK_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_MASK_SEL) >> BP_IPU_DI1_GENERAL_DI1_MASK_SEL)
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//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_MASK_SEL.
|
|
#define BF_IPU_DI1_GENERAL_DI1_MASK_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_MASK_SEL) & BM_IPU_DI1_GENERAL_DI1_MASK_SEL)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_MASK_SEL field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_MASK_SEL(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_MASK_SEL) | BF_IPU_DI1_GENERAL_DI1_MASK_SEL(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DI1_GENERAL, field DI1_DISP_CLOCK_INIT[23] (RW)
|
|
*
|
|
* Display clock's initial mode For synchronization error conditions the display clock can be
|
|
* stopped on the next VSYNC
|
|
*
|
|
* Values:
|
|
* - 0 - The display's clock is stopped after the next VSYNC (indicating new frame)
|
|
* - 1 - The display's clock is running after the next VSYNC (indicating new frame)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT (23) //!< Bit position for IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT.
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#define BM_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT (0x00800000) //!< Bit mask for IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT.
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//! @brief Get value of IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT) >> BP_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT)
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//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT.
|
|
#define BF_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT) & BM_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLOCK_INIT field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT) | BF_IPU_DI1_GENERAL_DI1_DISP_CLOCK_INIT(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DI1_GENERAL, field DI1_CLOCK_STOP_MODE[27:24] (RW)
|
|
*
|
|
* DI clock stop mode When performing a clock change. The DI stops the clock to the display. These
|
|
* field defines when the clock will be stopped Stopping at EOL/EOF is supported for the case where
|
|
* the data is coming from the IDMAC (DMA access). In case that only direct accesses is performed,
|
|
* the user should set this field to 0000 0001-1001 stop at the next event of one of the counters
|
|
* (counter #1 to counter #9)
|
|
*
|
|
* Values:
|
|
* - 0000 - stop at the next edge of the display clock
|
|
* - 1100 - stop at EOL (end of a line), but if stop request is during blanking interval, stop now
|
|
* - 1101 - stop at EOF (end of a frame), but if stop request is during blanking interval, stop now
|
|
* - 1110 - stop at EOL (end of a line), but if stop request is during blanking interval, stop at the end of the
|
|
* next line
|
|
* - 1111 - stop at EOF (end of a frame), but if stop request is during blanking interval, stop at the end of
|
|
* the next frame
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE (24) //!< Bit position for IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE.
|
|
#define BM_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE (0x0f000000) //!< Bit mask for IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE.
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|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE) >> BP_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE.
|
|
#define BF_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE) & BM_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CLOCK_STOP_MODE field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE) | BF_IPU_DI1_GENERAL_DI1_CLOCK_STOP_MODE(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_DISP_Y_SEL[30:28] (RW)
|
|
*
|
|
* DI1 Display Vertical coordinate (Y) select. This field defines which one of the 8 counters will
|
|
* be used as a display's line counter.
|
|
*
|
|
* Values:
|
|
* - 000 - counter #1 is selected
|
|
* - 111 - counter #8 is selected
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_DISP_Y_SEL (28) //!< Bit position for IPU_DI1_GENERAL_DI1_DISP_Y_SEL.
|
|
#define BM_IPU_DI1_GENERAL_DI1_DISP_Y_SEL (0x70000000) //!< Bit mask for IPU_DI1_GENERAL_DI1_DISP_Y_SEL.
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|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_DISP_Y_SEL from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_DISP_Y_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_DISP_Y_SEL) >> BP_IPU_DI1_GENERAL_DI1_DISP_Y_SEL)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_DISP_Y_SEL.
|
|
#define BF_IPU_DI1_GENERAL_DI1_DISP_Y_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_DISP_Y_SEL) & BM_IPU_DI1_GENERAL_DI1_DISP_Y_SEL)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_Y_SEL field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_DISP_Y_SEL(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_DISP_Y_SEL) | BF_IPU_DI1_GENERAL_DI1_DISP_Y_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_GENERAL, field DI1_PIN8_PIN15_SEL[31] (RW)
|
|
*
|
|
* This bit routes PIN8 over PIN15
|
|
*
|
|
* Values:
|
|
* - 0 - PIN15 is routed to PIN15, PIN8 is routed to PIN8
|
|
* - 1 - PIN8 is routed to PIN15, PIN8 is also routed to PIN8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL (31) //!< Bit position for IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL.
|
|
#define BM_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL (0x80000000) //!< Bit mask for IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL from a register value.
|
|
#define BG_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL) >> BP_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL.
|
|
#define BF_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL) & BM_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN8_PIN15_SEL field to a new value.
|
|
#define BW_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL(x, v) (HW_IPU_DI1_GENERAL_WR(x, (HW_IPU_DI1_GENERAL_RD(x) & ~BM_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL) | BF_IPU_DI1_GENERAL_DI1_PIN8_PIN15_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_BS_CLKGEN0 - DI1 Base Sync Clock Gen 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_BS_CLKGEN0 - DI1 Base Sync Clock Gen 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_bs_clkgen0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_bs_clkgen0_bitfields
|
|
{
|
|
unsigned DI1_DISP_CLK_PERIOD : 12; //!< [11:0] DI1 Display Clock Period
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved.
|
|
unsigned DI1_DISP_CLK_OFFSET : 9; //!< [24:16] DI1 Display Clock Offset
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_bs_clkgen0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_BS_CLKGEN0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_BS_CLKGEN0_ADDR(x) (REGS_IPU_BASE(x) + 0x48004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_BS_CLKGEN0(x) (*(volatile hw_ipu_di1_bs_clkgen0_t *) HW_IPU_DI1_BS_CLKGEN0_ADDR(x))
|
|
#define HW_IPU_DI1_BS_CLKGEN0_RD(x) (HW_IPU_DI1_BS_CLKGEN0(x).U)
|
|
#define HW_IPU_DI1_BS_CLKGEN0_WR(x, v) (HW_IPU_DI1_BS_CLKGEN0(x).U = (v))
|
|
#define HW_IPU_DI1_BS_CLKGEN0_SET(x, v) (HW_IPU_DI1_BS_CLKGEN0_WR(x, HW_IPU_DI1_BS_CLKGEN0_RD(x) | (v)))
|
|
#define HW_IPU_DI1_BS_CLKGEN0_CLR(x, v) (HW_IPU_DI1_BS_CLKGEN0_WR(x, HW_IPU_DI1_BS_CLKGEN0_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_BS_CLKGEN0_TOG(x, v) (HW_IPU_DI1_BS_CLKGEN0_WR(x, HW_IPU_DI1_BS_CLKGEN0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_BS_CLKGEN0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_BS_CLKGEN0, field DI1_DISP_CLK_PERIOD[11:0] (RW)
|
|
*
|
|
* DI1 Display Clock Period This field defines the Display interface clock period for display write
|
|
* access. This parameter contains an integer part (bits 11:4) and a fractional part (bits 3:0). It
|
|
* defines a fractional division ratio of the HSP_CLK clock for generation of the display's
|
|
* interface clock.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD (0) //!< Bit position for IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD.
|
|
#define BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD (0x00000fff) //!< Bit mask for IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD.
|
|
|
|
//! @brief Get value of IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD from a register value.
|
|
#define BG_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD) >> BP_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD.
|
|
#define BF_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD) & BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLK_PERIOD field to a new value.
|
|
#define BW_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD(x, v) (HW_IPU_DI1_BS_CLKGEN0_WR(x, (HW_IPU_DI1_BS_CLKGEN0_RD(x) & ~BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD) | BF_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_PERIOD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_BS_CLKGEN0, field DI1_DISP_CLK_OFFSET[24:16] (RW)
|
|
*
|
|
* DI1 Display Clock Offset The DI has the ability to delay the display's clock This field defines
|
|
* the amount of IPU's clock cycles added as delay on this clock.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET (16) //!< Bit position for IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET.
|
|
#define BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET (0x01ff0000) //!< Bit mask for IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET.
|
|
|
|
//! @brief Get value of IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET from a register value.
|
|
#define BG_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET) >> BP_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET.
|
|
#define BF_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET) & BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLK_OFFSET field to a new value.
|
|
#define BW_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET(x, v) (HW_IPU_DI1_BS_CLKGEN0_WR(x, (HW_IPU_DI1_BS_CLKGEN0_RD(x) & ~BM_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET) | BF_IPU_DI1_BS_CLKGEN0_DI1_DISP_CLK_OFFSET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_BS_CLKGEN1 - DI1 Base Sync Clock Gen 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_BS_CLKGEN1 - DI1 Base Sync Clock Gen 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_bs_clkgen1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_bs_clkgen1_bitfields
|
|
{
|
|
unsigned DI1_DISP_CLK_UP : 9; //!< [8:0] DI1 display clock rising edge position
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI1_DISP_CLK_DOWN : 9; //!< [24:16] DI1 display clock falling edge position
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_bs_clkgen1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_BS_CLKGEN1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_BS_CLKGEN1_ADDR(x) (REGS_IPU_BASE(x) + 0x48008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_BS_CLKGEN1(x) (*(volatile hw_ipu_di1_bs_clkgen1_t *) HW_IPU_DI1_BS_CLKGEN1_ADDR(x))
|
|
#define HW_IPU_DI1_BS_CLKGEN1_RD(x) (HW_IPU_DI1_BS_CLKGEN1(x).U)
|
|
#define HW_IPU_DI1_BS_CLKGEN1_WR(x, v) (HW_IPU_DI1_BS_CLKGEN1(x).U = (v))
|
|
#define HW_IPU_DI1_BS_CLKGEN1_SET(x, v) (HW_IPU_DI1_BS_CLKGEN1_WR(x, HW_IPU_DI1_BS_CLKGEN1_RD(x) | (v)))
|
|
#define HW_IPU_DI1_BS_CLKGEN1_CLR(x, v) (HW_IPU_DI1_BS_CLKGEN1_WR(x, HW_IPU_DI1_BS_CLKGEN1_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_BS_CLKGEN1_TOG(x, v) (HW_IPU_DI1_BS_CLKGEN1_WR(x, HW_IPU_DI1_BS_CLKGEN1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_BS_CLKGEN1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_BS_CLKGEN1, field DI1_DISP_CLK_UP[8:0] (RW)
|
|
*
|
|
* DI1 display clock rising edge position This parameter contains an integer part (bits 8:1) and a
|
|
* fractional part (bit 0). The position value is a time interval between display's access start
|
|
* point and display 's interface clock rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP (0) //!< Bit position for IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP.
|
|
#define BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP (0x000001ff) //!< Bit mask for IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP.
|
|
|
|
//! @brief Get value of IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP from a register value.
|
|
#define BG_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP) >> BP_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP.
|
|
#define BF_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP) & BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLK_UP field to a new value.
|
|
#define BW_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP(x, v) (HW_IPU_DI1_BS_CLKGEN1_WR(x, (HW_IPU_DI1_BS_CLKGEN1_RD(x) & ~BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP) | BF_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_UP(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_BS_CLKGEN1, field DI1_DISP_CLK_DOWN[24:16] (RW)
|
|
*
|
|
* DI1 display clock falling edge position This parameter contains an integer part (bits 24:17) and
|
|
* a fractional part (bit 16). The position value is a time interval between display's access start
|
|
* point and display 's interface clock falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN (16) //!< Bit position for IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN.
|
|
#define BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN (0x01ff0000) //!< Bit mask for IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN.
|
|
|
|
//! @brief Get value of IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN from a register value.
|
|
#define BG_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN) >> BP_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN.
|
|
#define BF_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN) & BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DISP_CLK_DOWN field to a new value.
|
|
#define BW_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN(x, v) (HW_IPU_DI1_BS_CLKGEN1_WR(x, (HW_IPU_DI1_BS_CLKGEN1_RD(x) & ~BM_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN) | BF_IPU_DI1_BS_CLKGEN1_DI1_DISP_CLK_DOWN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_1 - DI1 Sync Wave Gen 1 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_1 - DI1 Sync Wave Gen 1 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_1_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_1 : 3; //!< [2:0] DI1 counter #1 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_1 : 12; //!< [14:3] DI1 counter #1 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_1 : 3; //!< [18:16] DI1 counter #1 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_1 : 12; //!< [30:19] DI1 counter #1 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_1_ADDR(x) (REGS_IPU_BASE(x) + 0x4800c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_1(x) (*(volatile hw_ipu_di1_sw_gen0_1_t *) HW_IPU_DI1_SW_GEN0_1_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_1_RD(x) (HW_IPU_DI1_SW_GEN0_1(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_1_WR(x, v) (HW_IPU_DI1_SW_GEN0_1(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_1_SET(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, HW_IPU_DI1_SW_GEN0_1_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_1_CLR(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, HW_IPU_DI1_SW_GEN0_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_1_TOG(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, HW_IPU_DI1_SW_GEN0_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_1, field DI1_OFFSET_RESOLUTION_1[2:0] (RW)
|
|
*
|
|
* DI1 counter #1 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - NA
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1 (0) //!< Bit position for IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1.
|
|
#define BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1) >> BP_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1.
|
|
#define BF_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1) & BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, (HW_IPU_DI1_SW_GEN0_1_RD(x) & ~BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1) | BF_IPU_DI1_SW_GEN0_1_DI1_OFFSET_RESOLUTION_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_1, field DI1_OFFSET_VALUE_1[14:3] (RW)
|
|
*
|
|
* DI1 counter #1 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1 (3) //!< Bit position for IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1.
|
|
#define BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1) >> BP_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1.
|
|
#define BF_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1) & BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, (HW_IPU_DI1_SW_GEN0_1_RD(x) & ~BM_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1) | BF_IPU_DI1_SW_GEN0_1_DI1_OFFSET_VALUE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_1, field DI1_RUN_RESOLUTION_1[18:16] (RW)
|
|
*
|
|
* DI1 counter #1 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - NA
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1 (16) //!< Bit position for IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1.
|
|
#define BM_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1) >> BP_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1.
|
|
#define BF_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1) & BM_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, (HW_IPU_DI1_SW_GEN0_1_RD(x) & ~BM_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1) | BF_IPU_DI1_SW_GEN0_1_DI1_RUN_RESOLUTION_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_1, field DI1_RUN_VALUE_M1_1[30:19] (RW)
|
|
*
|
|
* DI1 counter #1 pre defined value This fields defines the counter #1 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_1 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1 (19) //!< Bit position for IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1.
|
|
#define BM_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1) >> BP_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1.
|
|
#define BF_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1) & BM_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1(x, v) (HW_IPU_DI1_SW_GEN0_1_WR(x, (HW_IPU_DI1_SW_GEN0_1_RD(x) & ~BM_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1) | BF_IPU_DI1_SW_GEN0_1_DI1_RUN_VALUE_M1_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_2 - DI1 Sync Wave Gen 2 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_2 - DI1 Sync Wave Gen 2 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_2_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_2 : 3; //!< [2:0] DI1 counter #2 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_2 : 12; //!< [14:3] DI1 counter #2 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_2 : 3; //!< [18:16] DI1 counter #2 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_2 : 12; //!< [30:19] DI1 counter #2 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_2_ADDR(x) (REGS_IPU_BASE(x) + 0x48010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_2(x) (*(volatile hw_ipu_di1_sw_gen0_2_t *) HW_IPU_DI1_SW_GEN0_2_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_2_RD(x) (HW_IPU_DI1_SW_GEN0_2(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_2_WR(x, v) (HW_IPU_DI1_SW_GEN0_2(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_2_SET(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, HW_IPU_DI1_SW_GEN0_2_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_2_CLR(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, HW_IPU_DI1_SW_GEN0_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_2_TOG(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, HW_IPU_DI1_SW_GEN0_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_2, field DI1_OFFSET_RESOLUTION_2[2:0] (RW)
|
|
*
|
|
* DI1 counter #2 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2 (0) //!< Bit position for IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2.
|
|
#define BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2) >> BP_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2)
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|
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//! @brief Format value for bitfield IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2.
|
|
#define BF_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2) & BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, (HW_IPU_DI1_SW_GEN0_2_RD(x) & ~BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2) | BF_IPU_DI1_SW_GEN0_2_DI1_OFFSET_RESOLUTION_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_2, field DI1_OFFSET_VALUE_2[14:3] (RW)
|
|
*
|
|
* DI1 counter #2 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2 (3) //!< Bit position for IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2.
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|
#define BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2.
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|
|
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//! @brief Get value of IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2) >> BP_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2)
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|
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//! @brief Format value for bitfield IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2.
|
|
#define BF_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2) & BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, (HW_IPU_DI1_SW_GEN0_2_RD(x) & ~BM_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2) | BF_IPU_DI1_SW_GEN0_2_DI1_OFFSET_VALUE_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_2, field DI1_RUN_RESOLUTION_2[18:16] (RW)
|
|
*
|
|
* DI1 counter #2 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - NA
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2 (16) //!< Bit position for IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2.
|
|
#define BM_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2) >> BP_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2.
|
|
#define BF_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2) & BM_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, (HW_IPU_DI1_SW_GEN0_2_RD(x) & ~BM_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2) | BF_IPU_DI1_SW_GEN0_2_DI1_RUN_RESOLUTION_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_2, field DI1_RUN_VALUE_M1_2[30:19] (RW)
|
|
*
|
|
* DI1 counter #2 pre defined value This fields defines the counter #2 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_2 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2 (19) //!< Bit position for IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2.
|
|
#define BM_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2) >> BP_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2.
|
|
#define BF_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2) & BM_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2(x, v) (HW_IPU_DI1_SW_GEN0_2_WR(x, (HW_IPU_DI1_SW_GEN0_2_RD(x) & ~BM_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2) | BF_IPU_DI1_SW_GEN0_2_DI1_RUN_VALUE_M1_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_3 - DI1 Sync Wave Gen 3 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_3 - DI1 Sync Wave Gen 3 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_3_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_3 : 3; //!< [2:0] DI1 counter #3 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_3 : 12; //!< [14:3] DI1 counter #3 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_3 : 3; //!< [18:16] DI1 counter #3 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_3 : 12; //!< [30:19] DI1 counter #3 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_3_ADDR(x) (REGS_IPU_BASE(x) + 0x48014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_3(x) (*(volatile hw_ipu_di1_sw_gen0_3_t *) HW_IPU_DI1_SW_GEN0_3_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_3_RD(x) (HW_IPU_DI1_SW_GEN0_3(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_3_WR(x, v) (HW_IPU_DI1_SW_GEN0_3(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_3_SET(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, HW_IPU_DI1_SW_GEN0_3_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_3_CLR(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, HW_IPU_DI1_SW_GEN0_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_3_TOG(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, HW_IPU_DI1_SW_GEN0_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_3, field DI1_OFFSET_RESOLUTION_3[2:0] (RW)
|
|
*
|
|
* DI1 counter #3 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3 (0) //!< Bit position for IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3.
|
|
#define BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3) >> BP_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3.
|
|
#define BF_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3) & BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, (HW_IPU_DI1_SW_GEN0_3_RD(x) & ~BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3) | BF_IPU_DI1_SW_GEN0_3_DI1_OFFSET_RESOLUTION_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_3, field DI1_OFFSET_VALUE_3[14:3] (RW)
|
|
*
|
|
* DI1 counter #3 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3 (3) //!< Bit position for IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3.
|
|
#define BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3) >> BP_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3.
|
|
#define BF_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3) & BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, (HW_IPU_DI1_SW_GEN0_3_RD(x) & ~BM_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3) | BF_IPU_DI1_SW_GEN0_3_DI1_OFFSET_VALUE_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_3, field DI1_RUN_RESOLUTION_3[18:16] (RW)
|
|
*
|
|
* DI1 counter #3 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - NA
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3 (16) //!< Bit position for IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3.
|
|
#define BM_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3) >> BP_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3.
|
|
#define BF_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3) & BM_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, (HW_IPU_DI1_SW_GEN0_3_RD(x) & ~BM_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3) | BF_IPU_DI1_SW_GEN0_3_DI1_RUN_RESOLUTION_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_3, field DI1_RUN_VALUE_M1_3[30:19] (RW)
|
|
*
|
|
* DI1 counter #3 pre defined value This fields defines the counter #3 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_3 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3 (19) //!< Bit position for IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3.
|
|
#define BM_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3) >> BP_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3.
|
|
#define BF_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3) & BM_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3(x, v) (HW_IPU_DI1_SW_GEN0_3_WR(x, (HW_IPU_DI1_SW_GEN0_3_RD(x) & ~BM_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3) | BF_IPU_DI1_SW_GEN0_3_DI1_RUN_VALUE_M1_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_4 - DI1 Sync Wave Gen 4 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_4 - DI1 Sync Wave Gen 4 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_4_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_4 : 3; //!< [2:0] DI1 counter #4 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_4 : 12; //!< [14:3] DI1 counter #4 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_4 : 3; //!< [18:16] DI1 counter #4 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_4 : 12; //!< [30:19] DI1 counter #4 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_4_ADDR(x) (REGS_IPU_BASE(x) + 0x48018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_4(x) (*(volatile hw_ipu_di1_sw_gen0_4_t *) HW_IPU_DI1_SW_GEN0_4_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_4_RD(x) (HW_IPU_DI1_SW_GEN0_4(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_4_WR(x, v) (HW_IPU_DI1_SW_GEN0_4(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_4_SET(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, HW_IPU_DI1_SW_GEN0_4_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_4_CLR(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, HW_IPU_DI1_SW_GEN0_4_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_4_TOG(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, HW_IPU_DI1_SW_GEN0_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_4, field DI1_OFFSET_RESOLUTION_4[2:0] (RW)
|
|
*
|
|
* DI1 counter #4 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4 (0) //!< Bit position for IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4.
|
|
#define BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4) >> BP_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4.
|
|
#define BF_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4) & BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, (HW_IPU_DI1_SW_GEN0_4_RD(x) & ~BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4) | BF_IPU_DI1_SW_GEN0_4_DI1_OFFSET_RESOLUTION_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_4, field DI1_OFFSET_VALUE_4[14:3] (RW)
|
|
*
|
|
* DI1 counter #4 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4 (3) //!< Bit position for IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4.
|
|
#define BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4) >> BP_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4.
|
|
#define BF_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4) & BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, (HW_IPU_DI1_SW_GEN0_4_RD(x) & ~BM_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4) | BF_IPU_DI1_SW_GEN0_4_DI1_OFFSET_VALUE_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_4, field DI1_RUN_RESOLUTION_4[18:16] (RW)
|
|
*
|
|
* DI1 counter #4 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4 (16) //!< Bit position for IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4.
|
|
#define BM_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4) >> BP_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4.
|
|
#define BF_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4) & BM_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, (HW_IPU_DI1_SW_GEN0_4_RD(x) & ~BM_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4) | BF_IPU_DI1_SW_GEN0_4_DI1_RUN_RESOLUTION_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_4, field DI1_RUN_VALUE_M1_4[30:19] (RW)
|
|
*
|
|
* DI1 counter #4 pre defined value This fields defines the counter #4 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_4 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4 (19) //!< Bit position for IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4.
|
|
#define BM_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4) >> BP_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4.
|
|
#define BF_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4) & BM_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4(x, v) (HW_IPU_DI1_SW_GEN0_4_WR(x, (HW_IPU_DI1_SW_GEN0_4_RD(x) & ~BM_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4) | BF_IPU_DI1_SW_GEN0_4_DI1_RUN_VALUE_M1_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_5 - DI1 Sync Wave Gen 5 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_5 - DI1 Sync Wave Gen 5 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_5_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_5 : 3; //!< [2:0] DI1 counter #5 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_5 : 12; //!< [14:3] DI1 counter #5 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_5 : 3; //!< [18:16] DI1 counter #5 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_5 : 12; //!< [30:19] DI1 counter #5 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_5_ADDR(x) (REGS_IPU_BASE(x) + 0x4801c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_5(x) (*(volatile hw_ipu_di1_sw_gen0_5_t *) HW_IPU_DI1_SW_GEN0_5_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_5_RD(x) (HW_IPU_DI1_SW_GEN0_5(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_5_WR(x, v) (HW_IPU_DI1_SW_GEN0_5(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_5_SET(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, HW_IPU_DI1_SW_GEN0_5_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_5_CLR(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, HW_IPU_DI1_SW_GEN0_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_5_TOG(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, HW_IPU_DI1_SW_GEN0_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_5, field DI1_OFFSET_RESOLUTION_5[2:0] (RW)
|
|
*
|
|
* DI1 counter #5 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - -The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5 (0) //!< Bit position for IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5.
|
|
#define BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5) >> BP_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5.
|
|
#define BF_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5) & BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, (HW_IPU_DI1_SW_GEN0_5_RD(x) & ~BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5) | BF_IPU_DI1_SW_GEN0_5_DI1_OFFSET_RESOLUTION_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_5, field DI1_OFFSET_VALUE_5[14:3] (RW)
|
|
*
|
|
* DI1 counter #5 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5 (3) //!< Bit position for IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5.
|
|
#define BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5) >> BP_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5.
|
|
#define BF_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5) & BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, (HW_IPU_DI1_SW_GEN0_5_RD(x) & ~BM_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5) | BF_IPU_DI1_SW_GEN0_5_DI1_OFFSET_VALUE_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_5, field DI1_RUN_RESOLUTION_5[18:16] (RW)
|
|
*
|
|
* DI1 counter #5 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5 (16) //!< Bit position for IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5.
|
|
#define BM_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5) >> BP_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5.
|
|
#define BF_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5) & BM_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, (HW_IPU_DI1_SW_GEN0_5_RD(x) & ~BM_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5) | BF_IPU_DI1_SW_GEN0_5_DI1_RUN_RESOLUTION_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_5, field DI1_RUN_VALUE_M1_5[30:19] (RW)
|
|
*
|
|
* DI1 counter #5 pre defined value This fields defines the counter #5 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_5 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5 (19) //!< Bit position for IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5.
|
|
#define BM_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5) >> BP_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5.
|
|
#define BF_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5) & BM_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5(x, v) (HW_IPU_DI1_SW_GEN0_5_WR(x, (HW_IPU_DI1_SW_GEN0_5_RD(x) & ~BM_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5) | BF_IPU_DI1_SW_GEN0_5_DI1_RUN_VALUE_M1_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_6 - DI1 Sync Wave Gen 6 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_6 - DI1 Sync Wave Gen 6 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_6_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_6 : 3; //!< [2:0] DI1 counter #6 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_6 : 12; //!< [14:3] DI1 counter #6 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_6 : 3; //!< [18:16] DI1 counter #6 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_6 : 12; //!< [30:19] DI1 counter #6 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_6_ADDR(x) (REGS_IPU_BASE(x) + 0x48020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_6(x) (*(volatile hw_ipu_di1_sw_gen0_6_t *) HW_IPU_DI1_SW_GEN0_6_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_6_RD(x) (HW_IPU_DI1_SW_GEN0_6(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_6_WR(x, v) (HW_IPU_DI1_SW_GEN0_6(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_6_SET(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, HW_IPU_DI1_SW_GEN0_6_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_6_CLR(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, HW_IPU_DI1_SW_GEN0_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_6_TOG(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, HW_IPU_DI1_SW_GEN0_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_6, field DI1_OFFSET_RESOLUTION_6[2:0] (RW)
|
|
*
|
|
* DI1 counter #6 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6 (0) //!< Bit position for IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6.
|
|
#define BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6) >> BP_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6.
|
|
#define BF_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6) & BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, (HW_IPU_DI1_SW_GEN0_6_RD(x) & ~BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6) | BF_IPU_DI1_SW_GEN0_6_DI1_OFFSET_RESOLUTION_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_6, field DI1_OFFSET_VALUE_6[14:3] (RW)
|
|
*
|
|
* DI1 counter #6 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6 (3) //!< Bit position for IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6.
|
|
#define BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6) >> BP_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6.
|
|
#define BF_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6) & BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, (HW_IPU_DI1_SW_GEN0_6_RD(x) & ~BM_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6) | BF_IPU_DI1_SW_GEN0_6_DI1_OFFSET_VALUE_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_6, field DI1_RUN_RESOLUTION_6[18:16] (RW)
|
|
*
|
|
* DI1 counter #6 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6 (16) //!< Bit position for IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6.
|
|
#define BM_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6) >> BP_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6.
|
|
#define BF_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6) & BM_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, (HW_IPU_DI1_SW_GEN0_6_RD(x) & ~BM_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6) | BF_IPU_DI1_SW_GEN0_6_DI1_RUN_RESOLUTION_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_6, field DI1_RUN_VALUE_M1_6[30:19] (RW)
|
|
*
|
|
* DI1 counter #6 pre defined value This fields defines the counter #6 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_6 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6 (19) //!< Bit position for IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6.
|
|
#define BM_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6) >> BP_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6.
|
|
#define BF_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6) & BM_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6(x, v) (HW_IPU_DI1_SW_GEN0_6_WR(x, (HW_IPU_DI1_SW_GEN0_6_RD(x) & ~BM_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6) | BF_IPU_DI1_SW_GEN0_6_DI1_RUN_VALUE_M1_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_7 - DI1 Sync Wave Gen 7 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_7 - DI1 Sync Wave Gen 7 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_7_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_1 : 3; //!< [2:0] DI1 counter #7 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_7 : 12; //!< [14:3] DI1 counter #7 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_7 : 3; //!< [18:16] DI1 counter #1 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_7 : 12; //!< [30:19] DI1 counter #7 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_7_ADDR(x) (REGS_IPU_BASE(x) + 0x48024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_7(x) (*(volatile hw_ipu_di1_sw_gen0_7_t *) HW_IPU_DI1_SW_GEN0_7_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_7_RD(x) (HW_IPU_DI1_SW_GEN0_7(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_7_WR(x, v) (HW_IPU_DI1_SW_GEN0_7(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_7_SET(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, HW_IPU_DI1_SW_GEN0_7_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_7_CLR(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, HW_IPU_DI1_SW_GEN0_7_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_7_TOG(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, HW_IPU_DI1_SW_GEN0_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_7, field DI1_OFFSET_RESOLUTION_1[2:0] (RW)
|
|
*
|
|
* DI1 counter #7 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1 (0) //!< Bit position for IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1.
|
|
#define BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1) >> BP_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1.
|
|
#define BF_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1) & BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, (HW_IPU_DI1_SW_GEN0_7_RD(x) & ~BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1) | BF_IPU_DI1_SW_GEN0_7_DI1_OFFSET_RESOLUTION_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_7, field DI1_OFFSET_VALUE_7[14:3] (RW)
|
|
*
|
|
* DI1 counter #7 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7 (3) //!< Bit position for IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7.
|
|
#define BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7) >> BP_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7.
|
|
#define BF_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7) & BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, (HW_IPU_DI1_SW_GEN0_7_RD(x) & ~BM_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7) | BF_IPU_DI1_SW_GEN0_7_DI1_OFFSET_VALUE_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_7, field DI1_RUN_RESOLUTION_7[18:16] (RW)
|
|
*
|
|
* DI1 counter #1 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7 (16) //!< Bit position for IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7.
|
|
#define BM_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7) >> BP_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7.
|
|
#define BF_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7) & BM_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, (HW_IPU_DI1_SW_GEN0_7_RD(x) & ~BM_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7) | BF_IPU_DI1_SW_GEN0_7_DI1_RUN_RESOLUTION_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_7, field DI1_RUN_VALUE_M1_7[30:19] (RW)
|
|
*
|
|
* DI1 counter #7 pre defined value This fields defines the counter #7 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_7 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7 (19) //!< Bit position for IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7.
|
|
#define BM_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7) >> BP_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7.
|
|
#define BF_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7) & BM_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7(x, v) (HW_IPU_DI1_SW_GEN0_7_WR(x, (HW_IPU_DI1_SW_GEN0_7_RD(x) & ~BM_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7) | BF_IPU_DI1_SW_GEN0_7_DI1_RUN_VALUE_M1_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_8 - DI1 Sync Wave Gen 8 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_8 - DI1 Sync Wave Gen 8 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_8_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_8 : 3; //!< [2:0] DI1 counter #8 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_8 : 12; //!< [14:3] DI1 counter #8 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_8 : 3; //!< [18:16] DI1 counter #8 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_8 : 12; //!< [30:19] DI1 counter #8 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_8_ADDR(x) (REGS_IPU_BASE(x) + 0x48028)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_8(x) (*(volatile hw_ipu_di1_sw_gen0_8_t *) HW_IPU_DI1_SW_GEN0_8_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_8_RD(x) (HW_IPU_DI1_SW_GEN0_8(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_8_WR(x, v) (HW_IPU_DI1_SW_GEN0_8(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_8_SET(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, HW_IPU_DI1_SW_GEN0_8_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_8_CLR(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, HW_IPU_DI1_SW_GEN0_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_8_TOG(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, HW_IPU_DI1_SW_GEN0_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_8, field DI1_OFFSET_RESOLUTION_8[2:0] (RW)
|
|
*
|
|
* DI1 counter #8 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8 (0) //!< Bit position for IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8.
|
|
#define BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8) >> BP_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8.
|
|
#define BF_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8) & BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_RESOLUTION_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, (HW_IPU_DI1_SW_GEN0_8_RD(x) & ~BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8) | BF_IPU_DI1_SW_GEN0_8_DI1_OFFSET_RESOLUTION_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_8, field DI1_OFFSET_VALUE_8[14:3] (RW)
|
|
*
|
|
* DI1 counter #8 offset value The counter can start counting after a pre defined delay This field
|
|
* defines the amount of cycles that the counter will be delayed by
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8 (3) //!< Bit position for IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8.
|
|
#define BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8) >> BP_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8.
|
|
#define BF_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8) & BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_OFFSET_VALUE_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, (HW_IPU_DI1_SW_GEN0_8_RD(x) & ~BM_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8) | BF_IPU_DI1_SW_GEN0_8_DI1_OFFSET_VALUE_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_8, field DI1_RUN_RESOLUTION_8[18:16] (RW)
|
|
*
|
|
* DI1 counter #8 Run Resolution This field defines the trigger causing the counter to increment.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8 (16) //!< Bit position for IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8.
|
|
#define BM_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8) >> BP_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8.
|
|
#define BF_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8) & BM_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_RESOLUTION_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, (HW_IPU_DI1_SW_GEN0_8_RD(x) & ~BM_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8) | BF_IPU_DI1_SW_GEN0_8_DI1_RUN_RESOLUTION_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_8, field DI1_RUN_VALUE_M1_8[30:19] (RW)
|
|
*
|
|
* DI1 counter #8 pre defined value This fields defines the counter #8 pre defines value. When the
|
|
* counter is auto reload mode (di1_cnt_auto_reload_8 bit is set), the counter automatically
|
|
* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
|
|
* di1_step_repeat field.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8 (19) //!< Bit position for IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8.
|
|
#define BM_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8) >> BP_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8.
|
|
#define BF_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8) & BM_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_RUN_VALUE_M1_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8(x, v) (HW_IPU_DI1_SW_GEN0_8_WR(x, (HW_IPU_DI1_SW_GEN0_8_RD(x) & ~BM_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8) | BF_IPU_DI1_SW_GEN0_8_DI1_RUN_VALUE_M1_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN0_9 - DI1Sync Wave Gen 9 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN0_9 - DI1Sync Wave Gen 9 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen0_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen0_9_bitfields
|
|
{
|
|
unsigned DI1_OFFSET_RESOLUTION_9 : 3; //!< [2:0] DI1 counter #9 offset Resolution
|
|
unsigned DI1_OFFSET_VALUE_9 : 12; //!< [14:3] DI1 counter #9 offset value
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_RUN_RESOLUTION_9 : 3; //!< [18:16] DI1 counter #9 Run Resolution
|
|
unsigned DI1_RUN_VALUE_M1_9 : 12; //!< [30:19] DI1 counter #9 pre defined value
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen0_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN0_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN0_9_ADDR(x) (REGS_IPU_BASE(x) + 0x4802c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN0_9(x) (*(volatile hw_ipu_di1_sw_gen0_9_t *) HW_IPU_DI1_SW_GEN0_9_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN0_9_RD(x) (HW_IPU_DI1_SW_GEN0_9(x).U)
|
|
#define HW_IPU_DI1_SW_GEN0_9_WR(x, v) (HW_IPU_DI1_SW_GEN0_9(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN0_9_SET(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, HW_IPU_DI1_SW_GEN0_9_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN0_9_CLR(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, HW_IPU_DI1_SW_GEN0_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN0_9_TOG(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, HW_IPU_DI1_SW_GEN0_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN0_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN0_9, field DI1_OFFSET_RESOLUTION_9[2:0] (RW)
|
|
*
|
|
* DI1 counter #9 offset Resolution This field defines the trigger causing the offset counter to
|
|
* increment
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9 (0) //!< Bit position for IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9.
|
|
#define BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9 (0x00000007) //!< Bit mask for IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9) >> BP_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9.
|
|
#define BF_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9) & BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_OFFSET_RESOLUTION_9 field to a new value.
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#define BW_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, (HW_IPU_DI1_SW_GEN0_9_RD(x) & ~BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9) | BF_IPU_DI1_SW_GEN0_9_DI1_OFFSET_RESOLUTION_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SW_GEN0_9, field DI1_OFFSET_VALUE_9[14:3] (RW)
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*
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* DI1 counter #9 offset value The counter can start counting after a pre defined delay This field
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* defines the amount of cycles that the counter will be delayed by
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*/
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//@{
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#define BP_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9 (3) //!< Bit position for IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9.
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#define BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9 (0x00007ff8) //!< Bit mask for IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9.
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//! @brief Get value of IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9 from a register value.
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#define BG_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9) >> BP_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9.
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#define BF_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9) & BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_OFFSET_VALUE_9 field to a new value.
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#define BW_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, (HW_IPU_DI1_SW_GEN0_9_RD(x) & ~BM_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9) | BF_IPU_DI1_SW_GEN0_9_DI1_OFFSET_VALUE_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SW_GEN0_9, field DI1_RUN_RESOLUTION_9[18:16] (RW)
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*
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* DI1 counter #9 Run Resolution This field defines the trigger causing the counter to increment.
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*
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* Values:
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* - 000 - Counter is disabled
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* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
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* - 010 - The Counter is triggered by counter #1
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* - 011 - The Counter is triggered by counter #2
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* - 100 - The Counter is triggered by counter #3
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* - 101 - The Counter is triggered by counter #4
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* - 110 - The Counter is triggered by counter #5
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* - 111 - Counter is always on.
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*/
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//@{
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#define BP_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9 (16) //!< Bit position for IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9.
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#define BM_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9 (0x00070000) //!< Bit mask for IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9.
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//! @brief Get value of IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9 from a register value.
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#define BG_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9) >> BP_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9.
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#define BF_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9) & BM_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_RUN_RESOLUTION_9 field to a new value.
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|
#define BW_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, (HW_IPU_DI1_SW_GEN0_9_RD(x) & ~BM_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9) | BF_IPU_DI1_SW_GEN0_9_DI1_RUN_RESOLUTION_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SW_GEN0_9, field DI1_RUN_VALUE_M1_9[30:19] (RW)
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*
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|
* DI1 counter #9 pre defined value This fields defines the counter #9 pre defines value. When the
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|
* counter is auto reload mode (di1_cnt_auto_reload_9 bit is set), the counter automatically
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* restarts. otherwise the counter restarts for the amount of time defined on the corresponding
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|
* di1_step_repeat field.
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|
*/
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//@{
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#define BP_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9 (19) //!< Bit position for IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9.
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#define BM_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9 (0x7ff80000) //!< Bit mask for IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9.
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//! @brief Get value of IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9 from a register value.
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|
#define BG_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9) >> BP_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9.
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|
#define BF_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9) & BM_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI1_RUN_VALUE_M1_9 field to a new value.
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|
#define BW_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9(x, v) (HW_IPU_DI1_SW_GEN0_9_WR(x, (HW_IPU_DI1_SW_GEN0_9_RD(x) & ~BM_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9) | BF_IPU_DI1_SW_GEN0_9_DI1_RUN_VALUE_M1_9(v)))
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|
#endif
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|
//@}
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_1 - DI1 Sync Wave Gen 1 Register 1
|
|
//-------------------------------------------------------------------------------------------
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|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_1 - DI1 Sync Wave Gen 1 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_1_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_1 : 9; //!< [8:0] Counter rising edge position
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|
unsigned DI1_CNT_POLARITY_CLR_SEL_1 : 3; //!< [11:9] DI1 counter's polarity Clear select
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|
unsigned DI1_CNT_POLARITY_TRIGGER_SEL_1 : 3; //!< [14:12] DI1 Counter's toggling trigger select
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|
unsigned RESERVED0 : 1; //!< [15] Reserved
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|
unsigned DI1_CNT_DOWN_1 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI1_CNT_CLR_SEL_1 : 3; //!< [27:25] Counter Clear select
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|
unsigned DI1_CNT_AUTO_RELOAD_1 : 1; //!< [28] Counter auto reload mode
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|
unsigned DI1_CNT_POLARITY_GEN_EN_1 : 2; //!< [30:29] DI1 Counter polarity generator enable
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|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_1_t;
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|
#endif
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|
|
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/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_1 register
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|
*/
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|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_1_ADDR(x) (REGS_IPU_BASE(x) + 0x48030)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN1_1(x) (*(volatile hw_ipu_di1_sw_gen1_1_t *) HW_IPU_DI1_SW_GEN1_1_ADDR(x))
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#define HW_IPU_DI1_SW_GEN1_1_RD(x) (HW_IPU_DI1_SW_GEN1_1(x).U)
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|
#define HW_IPU_DI1_SW_GEN1_1_WR(x, v) (HW_IPU_DI1_SW_GEN1_1(x).U = (v))
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|
#define HW_IPU_DI1_SW_GEN1_1_SET(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, HW_IPU_DI1_SW_GEN1_1_RD(x) | (v)))
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|
#define HW_IPU_DI1_SW_GEN1_1_CLR(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, HW_IPU_DI1_SW_GEN1_1_RD(x) & ~(v)))
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|
#define HW_IPU_DI1_SW_GEN1_1_TOG(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, HW_IPU_DI1_SW_GEN1_1_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_1 bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_UP_1[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1 (0) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1.
|
|
#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1)
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|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1.
|
|
#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_UP_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_POLARITY_CLR_SEL_1[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1 (9) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1.
|
|
#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1.
|
|
#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_CLR_SEL_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_POLARITY_TRIGGER_SEL_1[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1 (12) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1.
|
|
#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1.
|
|
#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_TRIGGER_SEL_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_DOWN_1[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1 (16) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1.
|
|
#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1.
|
|
#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_1 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_DOWN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_CLR_SEL_1[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - Reserved
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1 (25) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1.
|
|
#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1.
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#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_CNT_CLR_SEL_1 field to a new value.
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#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_CLR_SEL_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_AUTO_RELOAD_1[28] (RW)
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*
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* Counter auto reload mode
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*
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* Values:
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* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
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* defined on the di1_step_repeat_1 field
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* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
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* field
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*/
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//@{
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#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1 (28) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1.
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#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1.
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//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1 from a register value.
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#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1.
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#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_CNT_AUTO_RELOAD_1 field to a new value.
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#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_AUTO_RELOAD_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SW_GEN1_1, field DI1_CNT_POLARITY_GEN_EN_1[30:29] (RW)
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*
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* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
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*
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* Values:
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* - 00 - Dynamic polarity change is disabled
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* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
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* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
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* multiple of 2.
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* - 10 - Dynamic polarity change is enabled
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* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
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*/
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//@{
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#define BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1 (29) //!< Bit position for IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1.
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#define BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1.
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//! @brief Get value of IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1 from a register value.
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#define BG_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1) >> BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1.
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#define BF_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1) & BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_CNT_POLARITY_GEN_EN_1 field to a new value.
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#define BW_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1(x, v) (HW_IPU_DI1_SW_GEN1_1_WR(x, (HW_IPU_DI1_SW_GEN1_1_RD(x) & ~BM_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1) | BF_IPU_DI1_SW_GEN1_1_DI1_CNT_POLARITY_GEN_EN_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI1_SW_GEN1_2 - DI1 Sync Wave Gen 2 Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI1_SW_GEN1_2 - DI1 Sync Wave Gen 2 Register 1 (RW)
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*
|
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di1_sw_gen1_2
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{
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reg32_t U;
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struct _hw_ipu_di1_sw_gen1_2_bitfields
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{
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unsigned DI1_CNT_UP_2 : 9; //!< [8:0] Counter rising edge position
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unsigned DI1_CNT_POLARITY_CLR_SEL_2 : 3; //!< [11:9] DI1 counter's polarity Clear select
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unsigned DI1_CNT_POLARITY_TRIGGER_SEL_2 : 3; //!< [14:12] DI1 Counter's toggling trigger select
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unsigned RESERVED0 : 1; //!< [15] Reserved
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unsigned DI1_CNT_DOWN_2 : 9; //!< [24:16] Counter falling edge position
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unsigned DI1_CNT_CLR_SEL_2 : 3; //!< [27:25] Counter Clear select
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unsigned DI1_CNT_AUTO_RELOAD_2 : 1; //!< [28] Counter auto reload mode
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unsigned DI1_CNT_POLARITY_GEN_EN_2 : 2; //!< [30:29] DI1 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_di1_sw_gen1_2_t;
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#endif
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/*!
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|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_2 register
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*/
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//@{
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#define HW_IPU_DI1_SW_GEN1_2_ADDR(x) (REGS_IPU_BASE(x) + 0x48034)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI1_SW_GEN1_2(x) (*(volatile hw_ipu_di1_sw_gen1_2_t *) HW_IPU_DI1_SW_GEN1_2_ADDR(x))
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#define HW_IPU_DI1_SW_GEN1_2_RD(x) (HW_IPU_DI1_SW_GEN1_2(x).U)
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#define HW_IPU_DI1_SW_GEN1_2_WR(x, v) (HW_IPU_DI1_SW_GEN1_2(x).U = (v))
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#define HW_IPU_DI1_SW_GEN1_2_SET(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, HW_IPU_DI1_SW_GEN1_2_RD(x) | (v)))
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#define HW_IPU_DI1_SW_GEN1_2_CLR(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, HW_IPU_DI1_SW_GEN1_2_RD(x) & ~(v)))
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#define HW_IPU_DI1_SW_GEN1_2_TOG(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, HW_IPU_DI1_SW_GEN1_2_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
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|
* constants & macros for individual IPU_DI1_SW_GEN1_2 bitfields
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|
*/
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/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_UP_2[8:0] (RW)
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|
*
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|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
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|
*/
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//@{
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#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2 (0) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2.
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#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2.
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//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2 from a register value.
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#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2.
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#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI1_CNT_UP_2 field to a new value.
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|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_UP_2(v)))
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#endif
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|
//@}
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/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_POLARITY_CLR_SEL_2[11:9] (RW)
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|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
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|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Reserved
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|
* - 011 - Reserved
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|
* - 100 - Reserved
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|
* - 101 - Reserved
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|
* - 110 - Reserved
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|
* - 111 - Reserved
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|
*/
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|
//@{
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|
#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2 (9) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2.
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|
#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2.
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//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2 from a register value.
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#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2.
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#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_2 field to a new value.
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|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_CLR_SEL_2(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_POLARITY_TRIGGER_SEL_2[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
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|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2 (12) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2.
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|
#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2.
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//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2)
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|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2.
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|
#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_TRIGGER_SEL_2(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_DOWN_2[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2 (16) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2.
|
|
#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2.
|
|
#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_DOWN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_CLR_SEL_2[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - Reserved
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2 (25) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2.
|
|
#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2.
|
|
#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_CLR_SEL_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_AUTO_RELOAD_2[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2 (28) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2.
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|
#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2 from a register value.
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|
#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2.
|
|
#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_AUTO_RELOAD_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_2, field DI1_CNT_POLARITY_GEN_EN_2[30:29] (RW)
|
|
*
|
|
* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2 (29) //!< Bit position for IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2.
|
|
#define BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2) >> BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2.
|
|
#define BF_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2) & BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_GEN_EN_2 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2(x, v) (HW_IPU_DI1_SW_GEN1_2_WR(x, (HW_IPU_DI1_SW_GEN1_2_RD(x) & ~BM_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2) | BF_IPU_DI1_SW_GEN1_2_DI1_CNT_POLARITY_GEN_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_3 - DI1 Sync Wave Gen 3 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_3 - DI1 Sync Wave Gen 3 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_3_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_3 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI1_CNT_POLARITY_CLR_SEL_3 : 3; //!< [11:9] DI1 counter's polarity Clear select
|
|
unsigned DI1_CNT_POLARITY_TRIGGER_SEL_3 : 3; //!< [14:12] DI1 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_CNT_DOWN_3 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI1_CNT_CLR_SEL_3 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI1_CNT_AUTO_RELOAD_3 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI1_CNT_POLARITY_GEN_EN_3 : 2; //!< [30:29] DI1 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_3_ADDR(x) (REGS_IPU_BASE(x) + 0x48038)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN1_3(x) (*(volatile hw_ipu_di1_sw_gen1_3_t *) HW_IPU_DI1_SW_GEN1_3_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN1_3_RD(x) (HW_IPU_DI1_SW_GEN1_3(x).U)
|
|
#define HW_IPU_DI1_SW_GEN1_3_WR(x, v) (HW_IPU_DI1_SW_GEN1_3(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN1_3_SET(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, HW_IPU_DI1_SW_GEN1_3_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN1_3_CLR(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, HW_IPU_DI1_SW_GEN1_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN1_3_TOG(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, HW_IPU_DI1_SW_GEN1_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_UP_3[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3 (0) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3.
|
|
#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3.
|
|
#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_UP_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_POLARITY_CLR_SEL_3[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Reserved
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3 (9) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3.
|
|
#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3.
|
|
#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_CLR_SEL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_POLARITY_TRIGGER_SEL_3[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3 (12) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3.
|
|
#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3.
|
|
#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_TRIGGER_SEL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_DOWN_3[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3 (16) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3.
|
|
#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3.
|
|
#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_DOWN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_CLR_SEL_3[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - Reserved
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3 (25) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3.
|
|
#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3.
|
|
#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_3 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_CLR_SEL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_AUTO_RELOAD_3[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3 (28) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3.
|
|
#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3.
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#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_CNT_AUTO_RELOAD_3 field to a new value.
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#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_AUTO_RELOAD_3(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SW_GEN1_3, field DI1_CNT_POLARITY_GEN_EN_3[30:29] (RW)
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*
|
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* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
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*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
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|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
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|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
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|
* multiple of 2.
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* - 10 - Dynamic polarity change is enabled
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* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
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|
*/
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//@{
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|
#define BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3 (29) //!< Bit position for IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3.
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#define BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3.
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//! @brief Get value of IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3 from a register value.
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#define BG_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3) >> BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3.
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#define BF_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3) & BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_CNT_POLARITY_GEN_EN_3 field to a new value.
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#define BW_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3(x, v) (HW_IPU_DI1_SW_GEN1_3_WR(x, (HW_IPU_DI1_SW_GEN1_3_RD(x) & ~BM_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3) | BF_IPU_DI1_SW_GEN1_3_DI1_CNT_POLARITY_GEN_EN_3(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI1_SW_GEN1_4 - DI1 Sync Wave Gen 4 Register 1
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI1_SW_GEN1_4 - DI1 Sync Wave Gen 4 Register 1 (RW)
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*
|
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* Reset value: 0x00000000
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|
*/
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typedef union _hw_ipu_di1_sw_gen1_4
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{
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reg32_t U;
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struct _hw_ipu_di1_sw_gen1_4_bitfields
|
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{
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unsigned DI1_CNT_UP_4 : 9; //!< [8:0] Counter rising edge position
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unsigned DI1_CNT_POLARITY_CLR_SEL_4 : 3; //!< [11:9] DI1 counter's polarity Clear select
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unsigned DI1_CNT_POLARITY_TRIGGER_SEL_4 : 3; //!< [14:12] DI1 Counter's toggling trigger select
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unsigned RESERVED0 : 1; //!< [15] Reserved
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unsigned DI1_CNT_DOWN_4 : 9; //!< [24:16] Counter falling edge position
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unsigned DI1_CNT_CLR_SEL_4 : 3; //!< [27:25] Counter Clear select
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unsigned DI1_CNT_AUTO_RELOAD_4 : 1; //!< [28] Counter auto reload mode
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unsigned DI1_CNT_POLARITY_GEN_EN_4 : 2; //!< [30:29] DI1 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_4_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_4 register
|
|
*/
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|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_4_ADDR(x) (REGS_IPU_BASE(x) + 0x4803c)
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|
|
#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_DI1_SW_GEN1_4(x) (*(volatile hw_ipu_di1_sw_gen1_4_t *) HW_IPU_DI1_SW_GEN1_4_ADDR(x))
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#define HW_IPU_DI1_SW_GEN1_4_RD(x) (HW_IPU_DI1_SW_GEN1_4(x).U)
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#define HW_IPU_DI1_SW_GEN1_4_WR(x, v) (HW_IPU_DI1_SW_GEN1_4(x).U = (v))
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|
#define HW_IPU_DI1_SW_GEN1_4_SET(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, HW_IPU_DI1_SW_GEN1_4_RD(x) | (v)))
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#define HW_IPU_DI1_SW_GEN1_4_CLR(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, HW_IPU_DI1_SW_GEN1_4_RD(x) & ~(v)))
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|
#define HW_IPU_DI1_SW_GEN1_4_TOG(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, HW_IPU_DI1_SW_GEN1_4_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_4 bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_UP_4[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
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|
*/
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|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4 (0) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4.
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|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4.
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|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4)
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|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_UP_4(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_POLARITY_CLR_SEL_4[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4 (9) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4.
|
|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_CLR_SEL_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_POLARITY_TRIGGER_SEL_4[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - - Counter is disabled
|
|
* - 001 - - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - - The Counter is triggered by counter #1
|
|
* - 011 - - The Counter is triggered by counter #2
|
|
* - 100 - - The Counter is triggered by counter #3
|
|
* - 101 - - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST
|
|
* bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4 (12) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4.
|
|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_TRIGGER_SEL_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_DOWN_4[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4 (16) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4.
|
|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_DOWN_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_CLR_SEL_4[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit.
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4 (25) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4.
|
|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_CLR_SEL_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_AUTO_RELOAD_4[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4 (28) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4.
|
|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_AUTO_RELOAD_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_4, field DI1_CNT_POLARITY_GEN_EN_4[30:29] (RW)
|
|
*
|
|
* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4 (29) //!< Bit position for IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4.
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|
#define BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4.
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|
|
//! @brief Get value of IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4) >> BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4.
|
|
#define BF_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4) & BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_GEN_EN_4 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4(x, v) (HW_IPU_DI1_SW_GEN1_4_WR(x, (HW_IPU_DI1_SW_GEN1_4_RD(x) & ~BM_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4) | BF_IPU_DI1_SW_GEN1_4_DI1_CNT_POLARITY_GEN_EN_4(v)))
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#endif
|
|
//@}
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|
|
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_5 - DI1 Sync Wave Gen 5 Register 1
|
|
//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_5 - DI1 Sync Wave Gen 5 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_5_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_5 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI1_CNT_POLARITY_CLR_SEL_5 : 3; //!< [11:9] DI1 counter's polarity Clear select
|
|
unsigned DI1_CNT_POLARITY_TRIGGER_SEL_5 : 3; //!< [14:12] DI1 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_CNT_DOWN_5 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI1_CNT_CLR_SEL_5 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI1_CNT_AUTO_RELOAD_5 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI1_CNT_POLARITY_GEN_EN_5 : 2; //!< [30:29] DI1 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_5_ADDR(x) (REGS_IPU_BASE(x) + 0x48040)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN1_5(x) (*(volatile hw_ipu_di1_sw_gen1_5_t *) HW_IPU_DI1_SW_GEN1_5_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN1_5_RD(x) (HW_IPU_DI1_SW_GEN1_5(x).U)
|
|
#define HW_IPU_DI1_SW_GEN1_5_WR(x, v) (HW_IPU_DI1_SW_GEN1_5(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN1_5_SET(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, HW_IPU_DI1_SW_GEN1_5_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN1_5_CLR(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, HW_IPU_DI1_SW_GEN1_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN1_5_TOG(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, HW_IPU_DI1_SW_GEN1_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_UP_5[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5 (0) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_UP_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_POLARITY_CLR_SEL_5[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Output is inverted if the output of counter #4 is set
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5 (9) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_CLR_SEL_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_POLARITY_TRIGGER_SEL_5[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5 (12) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_TRIGGER_SEL_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_DOWN_5[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5 (16) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_DOWN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_CLR_SEL_5[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - External VSYNC
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5 (25) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_CLR_SEL_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_AUTO_RELOAD_5[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5 (28) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_AUTO_RELOAD_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_5, field DI1_CNT_POLARITY_GEN_EN_5[30:29] (RW)
|
|
*
|
|
* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5 (29) //!< Bit position for IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5.
|
|
#define BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5) >> BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5)
|
|
|
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5.
|
|
#define BF_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5) & BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_GEN_EN_5 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5(x, v) (HW_IPU_DI1_SW_GEN1_5_WR(x, (HW_IPU_DI1_SW_GEN1_5_RD(x) & ~BM_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5) | BF_IPU_DI1_SW_GEN1_5_DI1_CNT_POLARITY_GEN_EN_5(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_6 - DI1 Sync Wave Gen 6 Register 1
|
|
//-------------------------------------------------------------------------------------------
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|
|
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#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_6 - DI1 Sync Wave Gen 6 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_6_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_6 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI1_CNT_POLARITY_CLR_SEL_6 : 3; //!< [11:9] DI1 counter's polarity Clear select
|
|
unsigned DI1_CNT_POLARITY_TRIGGER_SEL_6 : 3; //!< [14:12] DI1 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_CNT_DOWN_6 : 9; //!< [24:16] Counter falling edge position
|
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unsigned DI1_CNT_CLR_SEL_6 : 3; //!< [27:25] Counter Clear select
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|
unsigned DI1_CNT_AUTO_RELOAD_6 : 1; //!< [28] Counter auto reload mode
|
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unsigned DI1_CNT_POLARITY_GEN_EN_6 : 2; //!< [30:29] DI1 Counter polarity generator enable
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unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_6_t;
|
|
#endif
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|
|
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/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_6_ADDR(x) (REGS_IPU_BASE(x) + 0x48044)
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|
|
#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_DI1_SW_GEN1_6(x) (*(volatile hw_ipu_di1_sw_gen1_6_t *) HW_IPU_DI1_SW_GEN1_6_ADDR(x))
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#define HW_IPU_DI1_SW_GEN1_6_RD(x) (HW_IPU_DI1_SW_GEN1_6(x).U)
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#define HW_IPU_DI1_SW_GEN1_6_WR(x, v) (HW_IPU_DI1_SW_GEN1_6(x).U = (v))
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|
#define HW_IPU_DI1_SW_GEN1_6_SET(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, HW_IPU_DI1_SW_GEN1_6_RD(x) | (v)))
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|
#define HW_IPU_DI1_SW_GEN1_6_CLR(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, HW_IPU_DI1_SW_GEN1_6_RD(x) & ~(v)))
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|
#define HW_IPU_DI1_SW_GEN1_6_TOG(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, HW_IPU_DI1_SW_GEN1_6_RD(x) ^ (v)))
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#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_6 bitfields
|
|
*/
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|
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/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_UP_6[8:0] (RW)
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|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
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|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
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|
*/
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|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6 (0) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6.
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|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6)
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//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_UP_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_POLARITY_CLR_SEL_6[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Output is inverted if the output of counter #4 is set
|
|
* - 110 - Output is inverted if the output of counter #5 is set
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6 (9) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_CLR_SEL_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_POLARITY_TRIGGER_SEL_6[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6 (12) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_TRIGGER_SEL_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_DOWN_6[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6 (16) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_DOWN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_CLR_SEL_6[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6 (25) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_CLR_SEL_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_AUTO_RELOAD_6[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6 (28) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_AUTO_RELOAD_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_6, field DI1_CNT_POLARITY_GEN_EN_6[30:29] (RW)
|
|
*
|
|
* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6 (29) //!< Bit position for IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6.
|
|
#define BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6) >> BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6.
|
|
#define BF_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6) & BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_GEN_EN_6 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6(x, v) (HW_IPU_DI1_SW_GEN1_6_WR(x, (HW_IPU_DI1_SW_GEN1_6_RD(x) & ~BM_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6) | BF_IPU_DI1_SW_GEN1_6_DI1_CNT_POLARITY_GEN_EN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_7 - DI1Sync Wave Gen 7 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_7 - DI1Sync Wave Gen 7 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_7_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_7 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI1_CNT_POLARITY_CLR_SEL_7 : 3; //!< [11:9] DI1 counter's polarity Clear select
|
|
unsigned DI1_CNT_POLARITY_TRIGGER_SEL_7 : 3; //!< [14:12] DI1 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_CNT_DOWN_7 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI1_CNT_CLR_SEL_7 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI1_CNT_AUTO_RELOAD_7 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI1_CNT_POLARITY_GEN_EN_7 : 2; //!< [30:29] DI1 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_7_ADDR(x) (REGS_IPU_BASE(x) + 0x48048)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN1_7(x) (*(volatile hw_ipu_di1_sw_gen1_7_t *) HW_IPU_DI1_SW_GEN1_7_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN1_7_RD(x) (HW_IPU_DI1_SW_GEN1_7(x).U)
|
|
#define HW_IPU_DI1_SW_GEN1_7_WR(x, v) (HW_IPU_DI1_SW_GEN1_7(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN1_7_SET(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, HW_IPU_DI1_SW_GEN1_7_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN1_7_CLR(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, HW_IPU_DI1_SW_GEN1_7_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN1_7_TOG(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, HW_IPU_DI1_SW_GEN1_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_UP_7[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7 (0) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_UP_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_POLARITY_CLR_SEL_7[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Output is inverted if the output of counter #4 is set
|
|
* - 110 - Output is inverted if the output of counter #5 is set
|
|
* - 111 - Output is inverted if the output of counter #6 is set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7 (9) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_CLR_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_POLARITY_TRIGGER_SEL_7[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7 (12) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_TRIGGER_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_DOWN_7[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7 (16) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_DOWN_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_CLR_SEL_7[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7 (25) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_CLR_SEL_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_AUTO_RELOAD_7[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7 (28) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_AUTO_RELOAD_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_7, field DI1_CNT_POLARITY_GEN_EN_7[30:29] (RW)
|
|
*
|
|
* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7 (29) //!< Bit position for IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7.
|
|
#define BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7) >> BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7.
|
|
#define BF_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7) & BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_GEN_EN_7 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7(x, v) (HW_IPU_DI1_SW_GEN1_7_WR(x, (HW_IPU_DI1_SW_GEN1_7_RD(x) & ~BM_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7) | BF_IPU_DI1_SW_GEN1_7_DI1_CNT_POLARITY_GEN_EN_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_8 - DI1 Sync Wave Gen 8 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_8 - DI1 Sync Wave Gen 8 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_8_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_8 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned DI1_CNT_POLARITY_CLR_SEL_8 : 3; //!< [11:9] DI1 counter's polarity Clear select
|
|
unsigned DI1_CNT_POLARITY_TRIGGER_SEL_8 : 3; //!< [14:12] DI1 Counter's toggling trigger select
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved
|
|
unsigned DI1_CNT_DOWN_8 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI1_CNT_CLR_SEL_8 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI1_CNT_AUTO_RELOAD_8 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI1_CNT_POLARITY_GEN_EN_8 : 2; //!< [30:29] DI1 Counter polarity generator enable
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_8_ADDR(x) (REGS_IPU_BASE(x) + 0x4804c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN1_8(x) (*(volatile hw_ipu_di1_sw_gen1_8_t *) HW_IPU_DI1_SW_GEN1_8_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN1_8_RD(x) (HW_IPU_DI1_SW_GEN1_8(x).U)
|
|
#define HW_IPU_DI1_SW_GEN1_8_WR(x, v) (HW_IPU_DI1_SW_GEN1_8(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN1_8_SET(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, HW_IPU_DI1_SW_GEN1_8_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN1_8_CLR(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, HW_IPU_DI1_SW_GEN1_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN1_8_TOG(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, HW_IPU_DI1_SW_GEN1_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_UP_8[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8 (0) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_UP_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_POLARITY_CLR_SEL_8[11:9] (RW)
|
|
*
|
|
* DI1 counter's polarity Clear select This field selects the input to the counter telling the
|
|
* counter wether to invert the output
|
|
*
|
|
* Values:
|
|
* - 000 - Output is always inverted
|
|
* - 001 - Output is kept the same (no inversion)
|
|
* - 010 - Output is inverted if the output of counter #1 is set
|
|
* - 011 - Output is inverted if the output of counter #2 is set
|
|
* - 100 - Output is inverted if the output of counter #3 is set
|
|
* - 101 - Output is inverted if the output of counter #4 is set
|
|
* - 110 - Output is inverted if the output of counter #5 is set
|
|
* - 111 - Output is inverted if the output of counter #6 is set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8 (9) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8 (0x00000e00) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_CLR_SEL_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_CLR_SEL_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_POLARITY_TRIGGER_SEL_8[14:12] (RW)
|
|
*
|
|
* DI1 Counter's toggling trigger select This field selects the counter's trigger causing the output
|
|
* to toggle
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8 (12) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8 (0x00007000) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_TRIGGER_SEL_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_TRIGGER_SEL_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_DOWN_8[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8 (16) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_DOWN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_CLR_SEL_8[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8 (25) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_CLR_SEL_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_AUTO_RELOAD_8[28] (RW)
|
|
*
|
|
* Counter auto reload mode 1 The counter will automatically be reloaded forever, ignoring the value
|
|
* of the di1_step_repeat_<i> field 0 The counter will not be automatically reloaded, It will be
|
|
* reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8 (28) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_AUTO_RELOAD_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_8, field DI1_CNT_POLARITY_GEN_EN_8[30:29] (RW)
|
|
*
|
|
* DI1 Counter polarity generator enable The counter's output polarity can be changed on the fly.
|
|
*
|
|
* Values:
|
|
* - 00 - Dynamic polarity change is disabled
|
|
* - 01 - The counters UP and DOWN value are calculated according to the trigger selected by
|
|
* cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a
|
|
* multiple of 2.
|
|
* - 10 - Dynamic polarity change is enabled
|
|
* - 11 - Outputs polarity is dynamically changed every time the counter reaches its pre defined value
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8 (29) //!< Bit position for IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8.
|
|
#define BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8 (0x60000000) //!< Bit mask for IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8) >> BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8.
|
|
#define BF_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8) & BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_POLARITY_GEN_EN_8 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8(x, v) (HW_IPU_DI1_SW_GEN1_8_WR(x, (HW_IPU_DI1_SW_GEN1_8_RD(x) & ~BM_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8) | BF_IPU_DI1_SW_GEN1_8_DI1_CNT_POLARITY_GEN_EN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SW_GEN1_9 - DI1 Sync Wave Gen 9 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SW_GEN1_9 - DI1 Sync Wave Gen 9 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sw_gen1_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sw_gen1_9_bitfields
|
|
{
|
|
unsigned DI1_CNT_UP_9 : 9; //!< [8:0] Counter rising edge position
|
|
unsigned RESERVED0 : 6; //!< [14:9] Reserved
|
|
unsigned DI1_TAG_SEL_9 : 1; //!< [15] Counter #9 can send a synchronous tag when counter #9 reach its predefined value or when it's triggering counter reaches its pre defined value.
|
|
unsigned DI1_CNT_DOWN_9 : 9; //!< [24:16] Counter falling edge position
|
|
unsigned DI1_CNT_CLR_SEL_9 : 3; //!< [27:25] Counter Clear select
|
|
unsigned DI1_CNT_AUTO_RELOAD_9 : 1; //!< [28] Counter auto reload mode
|
|
unsigned DI1_GENTIME_SEL_9 : 3; //!< [31:29] Counter #9 main waveform select
|
|
} B;
|
|
} hw_ipu_di1_sw_gen1_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SW_GEN1_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SW_GEN1_9_ADDR(x) (REGS_IPU_BASE(x) + 0x48050)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SW_GEN1_9(x) (*(volatile hw_ipu_di1_sw_gen1_9_t *) HW_IPU_DI1_SW_GEN1_9_ADDR(x))
|
|
#define HW_IPU_DI1_SW_GEN1_9_RD(x) (HW_IPU_DI1_SW_GEN1_9(x).U)
|
|
#define HW_IPU_DI1_SW_GEN1_9_WR(x, v) (HW_IPU_DI1_SW_GEN1_9(x).U = (v))
|
|
#define HW_IPU_DI1_SW_GEN1_9_SET(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, HW_IPU_DI1_SW_GEN1_9_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SW_GEN1_9_CLR(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, HW_IPU_DI1_SW_GEN1_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SW_GEN1_9_TOG(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, HW_IPU_DI1_SW_GEN1_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SW_GEN1_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_9, field DI1_CNT_UP_9[8:0] (RW)
|
|
*
|
|
* Counter rising edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's rising edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9 (0) //!< Bit position for IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9.
|
|
#define BM_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9 (0x000001ff) //!< Bit mask for IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9) >> BP_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9.
|
|
#define BF_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_UP_9 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, (HW_IPU_DI1_SW_GEN1_9_RD(x) & ~BM_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9) | BF_IPU_DI1_SW_GEN1_9_DI1_CNT_UP_9(v)))
|
|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DI1_SW_GEN1_9, field DI1_TAG_SEL_9[15] (RW)
|
|
*
|
|
* Counter #9 can send a synchronous tag when counter #9 reach its predefined value or when it's
|
|
* triggering counter reaches its pre defined value.
|
|
*
|
|
* Values:
|
|
* - 0 - Tag's source is the triggering counter.
|
|
* - 1 - tag source is counter #9
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9 (15) //!< Bit position for IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9.
|
|
#define BM_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9 (0x00008000) //!< Bit mask for IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9) >> BP_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9.
|
|
#define BF_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9) & BM_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_TAG_SEL_9 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, (HW_IPU_DI1_SW_GEN1_9_RD(x) & ~BM_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9) | BF_IPU_DI1_SW_GEN1_9_DI1_TAG_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_9, field DI1_CNT_DOWN_9[24:16] (RW)
|
|
*
|
|
* Counter falling edge position This parameter contains an integer part (bits 24:17) and a
|
|
* fractional part (bit 16). The position value is the amount of cycles between the trigger's start
|
|
* point and the waveform's falling edge.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9 (16) //!< Bit position for IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9.
|
|
#define BM_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9 (0x01ff0000) //!< Bit mask for IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9.
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|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9) >> BP_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9.
|
|
#define BF_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_DOWN_9 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, (HW_IPU_DI1_SW_GEN1_9_RD(x) & ~BM_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9) | BF_IPU_DI1_SW_GEN1_9_DI1_CNT_DOWN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_9, field DI1_CNT_CLR_SEL_9[27:25] (RW)
|
|
*
|
|
* Counter Clear select This field defines the source of the signals that clears the counter.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter is disabled
|
|
* - 001 - The counter is triggered by the same trigger that triggers the displays clock.
|
|
* - 010 - The Counter is triggered by counter #1
|
|
* - 011 - The Counter is triggered by counter #2
|
|
* - 100 - The Counter is triggered by counter #3
|
|
* - 101 - The Counter is triggered by counter #4
|
|
* - 110 - The Counter is triggered by counter #5
|
|
* - 111 - Counter is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9 (25) //!< Bit position for IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9.
|
|
#define BM_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9 (0x0e000000) //!< Bit mask for IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9) >> BP_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9.
|
|
#define BF_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_CLR_SEL_9 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, (HW_IPU_DI1_SW_GEN1_9_RD(x) & ~BM_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9) | BF_IPU_DI1_SW_GEN1_9_DI1_CNT_CLR_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_9, field DI1_CNT_AUTO_RELOAD_9[28] (RW)
|
|
*
|
|
* Counter auto reload mode
|
|
*
|
|
* Values:
|
|
* - 0 - The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times
|
|
* defined on the di1_step_repeat_<i> field
|
|
* - 1 - The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i>
|
|
* field
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9 (28) //!< Bit position for IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9.
|
|
#define BM_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9 (0x10000000) //!< Bit mask for IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9) >> BP_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9.
|
|
#define BF_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9) & BM_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CNT_AUTO_RELOAD_9 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, (HW_IPU_DI1_SW_GEN1_9_RD(x) & ~BM_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9) | BF_IPU_DI1_SW_GEN1_9_DI1_CNT_AUTO_RELOAD_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SW_GEN1_9, field DI1_GENTIME_SEL_9[31:29] (RW)
|
|
*
|
|
* Counter #9 main waveform select This field defines the counter that counter #9's auxiliary
|
|
* waveform will be attached too.
|
|
*
|
|
* Values:
|
|
* - 000 - Counter #9's waveform is attached to counter #1's waveform
|
|
* - 001 - Counter #9's waveform is attached to counter #2's waveform
|
|
* - 010 - Counter #9's waveform is attached to counter #3's waveform
|
|
* - 011 - Counter #9's waveform is attached to counter #4's waveform
|
|
* - 100 - Counter #9's waveform is attached to counter #5's waveform
|
|
* - 101 - Counter #9's waveform is attached to counter #6's waveform
|
|
* - 110 - Counter #9's waveform is attached to counter #7's waveform
|
|
* - 111 - Counter #9's waveform is attached to counter #8's waveform
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9 (29) //!< Bit position for IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9.
|
|
#define BM_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9 (0xe0000000) //!< Bit mask for IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9.
|
|
|
|
//! @brief Get value of IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9 from a register value.
|
|
#define BG_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9) >> BP_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9.
|
|
#define BF_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9) & BM_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_GENTIME_SEL_9 field to a new value.
|
|
#define BW_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9(x, v) (HW_IPU_DI1_SW_GEN1_9_WR(x, (HW_IPU_DI1_SW_GEN1_9_RD(x) & ~BM_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9) | BF_IPU_DI1_SW_GEN1_9_DI1_GENTIME_SEL_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SYNC_AS_GEN - DI1 Sync Assistance Gen Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SYNC_AS_GEN - DI1 Sync Assistance Gen Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_sync_as_gen
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_sync_as_gen_bitfields
|
|
{
|
|
unsigned DI1_SYNC_START : 12; //!< [11:0] DI1 Sync start
|
|
unsigned RESERVED0 : 1; //!< [12] Reserved.
|
|
unsigned DI1_VSYNC_SEL : 3; //!< [15:13] VSYNC select
|
|
unsigned RESERVED1 : 12; //!< [27:16] Reserved.
|
|
unsigned DI1_SYNC_START_EN : 1; //!< [28] di1_sync_start_en
|
|
unsigned RESERVED2 : 3; //!< [31:29] Reserve
|
|
} B;
|
|
} hw_ipu_di1_sync_as_gen_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SYNC_AS_GEN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SYNC_AS_GEN_ADDR(x) (REGS_IPU_BASE(x) + 0x48054)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SYNC_AS_GEN(x) (*(volatile hw_ipu_di1_sync_as_gen_t *) HW_IPU_DI1_SYNC_AS_GEN_ADDR(x))
|
|
#define HW_IPU_DI1_SYNC_AS_GEN_RD(x) (HW_IPU_DI1_SYNC_AS_GEN(x).U)
|
|
#define HW_IPU_DI1_SYNC_AS_GEN_WR(x, v) (HW_IPU_DI1_SYNC_AS_GEN(x).U = (v))
|
|
#define HW_IPU_DI1_SYNC_AS_GEN_SET(x, v) (HW_IPU_DI1_SYNC_AS_GEN_WR(x, HW_IPU_DI1_SYNC_AS_GEN_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SYNC_AS_GEN_CLR(x, v) (HW_IPU_DI1_SYNC_AS_GEN_WR(x, HW_IPU_DI1_SYNC_AS_GEN_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SYNC_AS_GEN_TOG(x, v) (HW_IPU_DI1_SYNC_AS_GEN_WR(x, HW_IPU_DI1_SYNC_AS_GEN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SYNC_AS_GEN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SYNC_AS_GEN, field DI1_SYNC_START[11:0] (RW)
|
|
*
|
|
* DI1 Sync start This field defines the number of low (including blanking rows) on the which the
|
|
* DI1 starts preparing the data for the next frame.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START (0) //!< Bit position for IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START.
|
|
#define BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START (0x00000fff) //!< Bit mask for IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START.
|
|
|
|
//! @brief Get value of IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START from a register value.
|
|
#define BG_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START) >> BP_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START.
|
|
#define BF_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START) & BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SYNC_START field to a new value.
|
|
#define BW_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START(x, v) (HW_IPU_DI1_SYNC_AS_GEN_WR(x, (HW_IPU_DI1_SYNC_AS_GEN_RD(x) & ~BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START) | BF_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SYNC_AS_GEN, field DI1_VSYNC_SEL[15:13] (RW)
|
|
*
|
|
* VSYNC select This field defines which of the counters functions as VSYNC signal
|
|
*
|
|
* Values:
|
|
* - 000 - VSYNC is coming from counter #1
|
|
* - 001 - VSYNC is coming from counter #2
|
|
* - 111 - VSYNC is coming from counter #8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL (13) //!< Bit position for IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL.
|
|
#define BM_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL (0x0000e000) //!< Bit mask for IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL from a register value.
|
|
#define BG_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL) >> BP_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL.
|
|
#define BF_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL) & BM_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_VSYNC_SEL field to a new value.
|
|
#define BW_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL(x, v) (HW_IPU_DI1_SYNC_AS_GEN_WR(x, (HW_IPU_DI1_SYNC_AS_GEN_RD(x) & ~BM_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL) | BF_IPU_DI1_SYNC_AS_GEN_DI1_VSYNC_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SYNC_AS_GEN, field DI1_SYNC_START_EN[28] (RW)
|
|
*
|
|
* di1_sync_start_en
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN (28) //!< Bit position for IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN.
|
|
#define BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN (0x10000000) //!< Bit mask for IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN.
|
|
|
|
//! @brief Get value of IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN from a register value.
|
|
#define BG_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN) >> BP_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN)
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//! @brief Format value for bitfield IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN.
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#define BF_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN) & BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SYNC_START_EN field to a new value.
|
|
#define BW_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN(x, v) (HW_IPU_DI1_SYNC_AS_GEN_WR(x, (HW_IPU_DI1_SYNC_AS_GEN_RD(x) & ~BM_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN) | BF_IPU_DI1_SYNC_AS_GEN_DI1_SYNC_START_EN(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI1_DW_GEN_I - DI1 Data Wave Gen <i> Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
|
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/*!
|
|
* @brief HW_IPU_DI1_DW_GEN_I - DI1 Data Wave Gen <i> Register (RW)
|
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*
|
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* Reset value: 0x00000000
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*
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* The DI1_DW_GEN_<i> register holds pointers for the waveform generators. These registers have
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* different bit arrangements for parallel and serial display. When using a parallel display VDI
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* Plane Size Register 4 is applicable. When using a serial interface VDI Plane Size Register 4 is
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* applicable. Register Field Descriptions for Serial display Field Description 31-24
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* di1_serial_period_<i> DI1 Serial Period <i> This field defines the period of the time base serial
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* display clock. The units are the internal DI clock 23-16 di1_start_period_<i> DI1 start period
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* This field defines the amount of cycles between the point where the access is ready to be
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* launched to the actual point where the time base serial display clock restarts. The units are the
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* internal DI clock. 15-14 di1_cst_<i> DI1 Chip Select pointer for waveform <i> This field points
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* to a register that defines the waveform of the CS pin. For serial displays the down value as
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* defined on DI1_DW_SET*_<i> is measured from the assertion of the last serial display time base
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* clock. 00 The waveform is defined according to the settings on DI1_DW_SET0_<i> 01 The waveform is
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* defined according to the settings on DI1_DW_SET1_<i> 10 The waveform is defined according to the
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* settings on DI1_DW_SET2_<i> 11 The waveform is defined according to the settings on
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* DI1_DW_SET3_<i> 13-9 Reserved 8-4 di1_serial_valid_bits_<i> DI1 Serial valid bits. This field
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* defines the amount of valid bits to be transmitted within the 32 bits internal word aligned to
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* bit[0]. The actual amount of valid bits is di1_serial_valid_bits_<i> + 1 3-2 di1_serial_rs_<i>
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* DI1 Serial RS This field points to a register that defines the waveform of the RS pin. For serial
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* displays the down value as defined on DI1_DW_SET*_<i> is measured from the assertion of the last
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* serial display time base clock. 00 The waveform is defined according to the settings on
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* DI1_DW_SET0_<i> 01 The waveform is defined according to the settings on DI1_DW_SET1_<i> 10 The
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* waveform is defined according to the settings on DI1_DW_SET2_<i> 11 The waveform is defined
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* according to the settings on DI1_DW_SET3_<i> 1-0 di1_serial_clk_<i> DI1 serial clock<i> This
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* field points to a register that defines the waveform of the Serial clock pin. 00 The waveform is
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* defined according to the settings on DI1_DW_SET0_<i> 01 The waveform is defined according to the
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* settings on DI1_DW_SET1_<i> 10 The waveform is defined according to the settings on
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* DI1_DW_SET2_<i> 11 The waveform is defined according to the settings on DI1_DW_SET3_<i>
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*/
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typedef union _hw_ipu_di1_dw_gen_i
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{
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reg32_t U;
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struct _hw_ipu_di1_dw_gen_i_bitfields
|
|
{
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unsigned DI1_PT_0_I : 2; //!< [1:0] DI1 PIN_11 pointer for waveform <i>
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unsigned DI1_PT_1_I : 2; //!< [3:2] DI1 PIN_12 pointer for waveform <i>
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unsigned DI1_PT_2_I : 2; //!< [5:4] DI1 PIN_13 pointer for waveform <i>
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unsigned DI1_PT_3_I : 2; //!< [7:6] DI1 PIN_14 pointer for waveform <i>
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unsigned DI1_PT_4_I : 2; //!< [9:8] DI1 PIN_15 pointer for waveform <i>
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unsigned DI1_PT_5_I : 2; //!< [11:10] DI1 PIN_16 pointer for waveform <i>
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unsigned DI1_PT_6_I : 2; //!< [13:12] DI1 PIN_17 pointer for waveform <i>
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unsigned DI1_CST_I : 2; //!< [15:14] DI1 Chip Select pointer for waveform <i>
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unsigned DI1_COMPONNENT_SIZE_I : 8; //!< [23:16] DI1 component Size
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unsigned DI1_ACCESS_SIZE_I : 8; //!< [31:24] DI1 Access Size <i>
|
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} B;
|
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} hw_ipu_di1_dw_gen_i_t;
|
|
#endif
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|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_DW_GEN_I register
|
|
*/
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//@{
|
|
#define HW_IPU_DI1_DW_GEN_I_ADDR(x) (REGS_IPU_BASE(x) + 0x48058)
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|
|
#ifndef __LANGUAGE_ASM__
|
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#define HW_IPU_DI1_DW_GEN_I(x) (*(volatile hw_ipu_di1_dw_gen_i_t *) HW_IPU_DI1_DW_GEN_I_ADDR(x))
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#define HW_IPU_DI1_DW_GEN_I_RD(x) (HW_IPU_DI1_DW_GEN_I(x).U)
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#define HW_IPU_DI1_DW_GEN_I_WR(x, v) (HW_IPU_DI1_DW_GEN_I(x).U = (v))
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#define HW_IPU_DI1_DW_GEN_I_SET(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, HW_IPU_DI1_DW_GEN_I_RD(x) | (v)))
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|
#define HW_IPU_DI1_DW_GEN_I_CLR(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, HW_IPU_DI1_DW_GEN_I_RD(x) & ~(v)))
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#define HW_IPU_DI1_DW_GEN_I_TOG(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, HW_IPU_DI1_DW_GEN_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
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|
|
/*
|
|
* constants & macros for individual IPU_DI1_DW_GEN_I bitfields
|
|
*/
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|
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/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_0_I[1:0] (RW)
|
|
*
|
|
* DI1 PIN_11 pointer for waveform <i> This field points to a register that defines the waveform of
|
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* the PIN_11 pin.
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|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
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|
* - 11 - - The waveform is defined according to the settings on DI1_DW_SET3_<i>
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|
*/
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|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_0_I (0) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_0_I.
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#define BM_IPU_DI1_DW_GEN_I_DI1_PT_0_I (0x00000003) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_0_I.
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|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_0_I from a register value.
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|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_0_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_0_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_0_I)
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|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_0_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_0_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_0_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_0_I)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_0_I field to a new value.
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|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_0_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_0_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_0_I(v)))
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|
#endif
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//@}
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/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_1_I[3:2] (RW)
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*
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|
* DI1 PIN_12 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_12 pin.
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|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
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|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
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* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
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* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
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|
*/
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|
//@{
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|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_1_I (2) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_1_I.
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#define BM_IPU_DI1_DW_GEN_I_DI1_PT_1_I (0x0000000c) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_1_I.
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//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_1_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_1_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_1_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_1_I)
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|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_1_I.
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|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_1_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_1_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_1_I)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_1_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_1_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_1_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_1_I(v)))
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#endif
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|
//@}
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|
/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_2_I[5:4] (RW)
|
|
*
|
|
* DI1 PIN_13 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_13 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_2_I (4) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_2_I.
|
|
#define BM_IPU_DI1_DW_GEN_I_DI1_PT_2_I (0x00000030) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_2_I.
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|
|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_2_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_2_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_2_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_2_I)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_2_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_2_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_2_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_2_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_2_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_2_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_2_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_2_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_3_I[7:6] (RW)
|
|
*
|
|
* DI1 PIN_14 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_14 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_3_I (6) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_3_I.
|
|
#define BM_IPU_DI1_DW_GEN_I_DI1_PT_3_I (0x000000c0) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_3_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_3_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_3_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_3_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_3_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_3_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_3_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_3_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_3_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_3_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_3_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_3_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_3_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_4_I[9:8] (RW)
|
|
*
|
|
* DI1 PIN_15 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_15 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_4_I (8) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_4_I.
|
|
#define BM_IPU_DI1_DW_GEN_I_DI1_PT_4_I (0x00000300) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_4_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_4_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_4_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_4_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_4_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_4_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_4_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_4_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_4_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_4_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_4_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_4_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_4_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_5_I[11:10] (RW)
|
|
*
|
|
* DI1 PIN_16 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_16 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_5_I (10) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_5_I.
|
|
#define BM_IPU_DI1_DW_GEN_I_DI1_PT_5_I (0x00000c00) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_5_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_5_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_5_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_5_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_5_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_5_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_5_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_5_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_5_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_5_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_5_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_5_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_5_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_GEN_I, field DI1_PT_6_I[13:12] (RW)
|
|
*
|
|
* DI1 PIN_17 pointer for waveform <i> This field points to a register that defines the waveform of
|
|
* the PIN_17 pin.
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_PT_6_I (12) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_PT_6_I.
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#define BM_IPU_DI1_DW_GEN_I_DI1_PT_6_I (0x00003000) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_PT_6_I.
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|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_PT_6_I from a register value.
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|
#define BG_IPU_DI1_DW_GEN_I_DI1_PT_6_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_PT_6_I) >> BP_IPU_DI1_DW_GEN_I_DI1_PT_6_I)
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//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_PT_6_I.
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|
#define BF_IPU_DI1_DW_GEN_I_DI1_PT_6_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_PT_6_I) & BM_IPU_DI1_DW_GEN_I_DI1_PT_6_I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PT_6_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_PT_6_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_PT_6_I) | BF_IPU_DI1_DW_GEN_I_DI1_PT_6_I(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_DI1_DW_GEN_I, field DI1_CST_I[15:14] (RW)
|
|
*
|
|
* DI1 Chip Select pointer for waveform <i> This field points to a register that defines the
|
|
* waveform of the CS pin. The CS is automatically mapped to a specific display
|
|
*
|
|
* Values:
|
|
* - 00 - The waveform is defined according to the settings on DI1_DW_SET0_<i>
|
|
* - 01 - The waveform is defined according to the settings on DI1_DW_SET1_<i>
|
|
* - 10 - The waveform is defined according to the settings on DI1_DW_SET2_<i>
|
|
* - 11 - The waveform is defined according to the settings on DI1_DW_SET3_<i>
|
|
*/
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|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_CST_I (14) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_CST_I.
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#define BM_IPU_DI1_DW_GEN_I_DI1_CST_I (0x0000c000) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_CST_I.
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|
|
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//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_CST_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_CST_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_CST_I) >> BP_IPU_DI1_DW_GEN_I_DI1_CST_I)
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//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_CST_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_CST_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_CST_I) & BM_IPU_DI1_DW_GEN_I_DI1_CST_I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CST_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_CST_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_CST_I) | BF_IPU_DI1_DW_GEN_I_DI1_CST_I(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DI1_DW_GEN_I, field DI1_COMPONNENT_SIZE_I[23:16] (RW)
|
|
*
|
|
* DI1 component Size This field defines the amount of IPU cycles between any 2 components
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I (16) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I.
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|
#define BM_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I (0x00ff0000) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I.
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|
|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I) >> BP_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I) & BM_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_COMPONNENT_SIZE_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I) | BF_IPU_DI1_DW_GEN_I_DI1_COMPONNENT_SIZE_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_GEN_I, field DI1_ACCESS_SIZE_I[31:24] (RW)
|
|
*
|
|
* DI1 Access Size <i> This field defines the amount of IPU cycles between any 2 accesses (an access
|
|
* may be a pixel or generic data that may have more one component)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I (24) //!< Bit position for IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I.
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|
#define BM_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I (0xff000000) //!< Bit mask for IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I.
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|
|
|
//! @brief Get value of IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I from a register value.
|
|
#define BG_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I) >> BP_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I.
|
|
#define BF_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I) & BM_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_ACCESS_SIZE_I field to a new value.
|
|
#define BW_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I(x, v) (HW_IPU_DI1_DW_GEN_I_WR(x, (HW_IPU_DI1_DW_GEN_I_RD(x) & ~BM_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I) | BF_IPU_DI1_DW_GEN_I_DI1_ACCESS_SIZE_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_DW_SET0_I - DI1 Data Wave Set 0 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_DW_SET0_I - DI1 Data Wave Set 0 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_dw_set0_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_dw_set0_i_bitfields
|
|
{
|
|
unsigned DI1_DATA_CNT_UP0_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI1_DATA_CNT_DOWN0_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_dw_set0_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_DW_SET0_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_DW_SET0_I_ADDR(x) (REGS_IPU_BASE(x) + 0x48088)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_DW_SET0_I(x) (*(volatile hw_ipu_di1_dw_set0_i_t *) HW_IPU_DI1_DW_SET0_I_ADDR(x))
|
|
#define HW_IPU_DI1_DW_SET0_I_RD(x) (HW_IPU_DI1_DW_SET0_I(x).U)
|
|
#define HW_IPU_DI1_DW_SET0_I_WR(x, v) (HW_IPU_DI1_DW_SET0_I(x).U = (v))
|
|
#define HW_IPU_DI1_DW_SET0_I_SET(x, v) (HW_IPU_DI1_DW_SET0_I_WR(x, HW_IPU_DI1_DW_SET0_I_RD(x) | (v)))
|
|
#define HW_IPU_DI1_DW_SET0_I_CLR(x, v) (HW_IPU_DI1_DW_SET0_I_WR(x, HW_IPU_DI1_DW_SET0_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_DW_SET0_I_TOG(x, v) (HW_IPU_DI1_DW_SET0_I_WR(x, HW_IPU_DI1_DW_SET0_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_DW_SET0_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_DW_SET0_I, field DI1_DATA_CNT_UP0_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I (0) //!< Bit position for IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I.
|
|
#define BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I (0x000001ff) //!< Bit mask for IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I) >> BP_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I.
|
|
#define BF_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I) & BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_UP0_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I(x, v) (HW_IPU_DI1_DW_SET0_I_WR(x, (HW_IPU_DI1_DW_SET0_I_RD(x) & ~BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I) | BF_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_UP0_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_SET0_I, field DI1_DATA_CNT_DOWN0_I[24:16] (RW)
|
|
*
|
|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I (16) //!< Bit position for IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I.
|
|
#define BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I (0x01ff0000) //!< Bit mask for IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I) >> BP_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I.
|
|
#define BF_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I) & BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_DOWN0_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I(x, v) (HW_IPU_DI1_DW_SET0_I_WR(x, (HW_IPU_DI1_DW_SET0_I_RD(x) & ~BM_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I) | BF_IPU_DI1_DW_SET0_I_DI1_DATA_CNT_DOWN0_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_DW_SET1_I - DI1 Data Wave Set 1 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_DW_SET1_I - DI1 Data Wave Set 1 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_dw_set1_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_dw_set1_i_bitfields
|
|
{
|
|
unsigned DI1_DATA_CNT_UP1_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI1_DATA_CNT_DOWN1_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_dw_set1_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_DW_SET1_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_DW_SET1_I_ADDR(x) (REGS_IPU_BASE(x) + 0x480b8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_DW_SET1_I(x) (*(volatile hw_ipu_di1_dw_set1_i_t *) HW_IPU_DI1_DW_SET1_I_ADDR(x))
|
|
#define HW_IPU_DI1_DW_SET1_I_RD(x) (HW_IPU_DI1_DW_SET1_I(x).U)
|
|
#define HW_IPU_DI1_DW_SET1_I_WR(x, v) (HW_IPU_DI1_DW_SET1_I(x).U = (v))
|
|
#define HW_IPU_DI1_DW_SET1_I_SET(x, v) (HW_IPU_DI1_DW_SET1_I_WR(x, HW_IPU_DI1_DW_SET1_I_RD(x) | (v)))
|
|
#define HW_IPU_DI1_DW_SET1_I_CLR(x, v) (HW_IPU_DI1_DW_SET1_I_WR(x, HW_IPU_DI1_DW_SET1_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_DW_SET1_I_TOG(x, v) (HW_IPU_DI1_DW_SET1_I_WR(x, HW_IPU_DI1_DW_SET1_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_DW_SET1_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_DW_SET1_I, field DI1_DATA_CNT_UP1_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I (0) //!< Bit position for IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I.
|
|
#define BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I (0x000001ff) //!< Bit mask for IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I) >> BP_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I.
|
|
#define BF_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I) & BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_UP1_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I(x, v) (HW_IPU_DI1_DW_SET1_I_WR(x, (HW_IPU_DI1_DW_SET1_I_RD(x) & ~BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I) | BF_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_UP1_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_SET1_I, field DI1_DATA_CNT_DOWN1_I[24:16] (RW)
|
|
*
|
|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I (16) //!< Bit position for IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I.
|
|
#define BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I (0x01ff0000) //!< Bit mask for IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I) >> BP_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I.
|
|
#define BF_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I) & BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_DOWN1_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I(x, v) (HW_IPU_DI1_DW_SET1_I_WR(x, (HW_IPU_DI1_DW_SET1_I_RD(x) & ~BM_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I) | BF_IPU_DI1_DW_SET1_I_DI1_DATA_CNT_DOWN1_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_DW_SET2_I - DI1 Data Wave Set 2 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_DW_SET2_I - DI1 Data Wave Set 2 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_dw_set2_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_dw_set2_i_bitfields
|
|
{
|
|
unsigned DI1_DATA_CNT_UP2_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI1_DATA_CNT_DOWN2_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_dw_set2_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_DW_SET2_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_DW_SET2_I_ADDR(x) (REGS_IPU_BASE(x) + 0x480e8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_DW_SET2_I(x) (*(volatile hw_ipu_di1_dw_set2_i_t *) HW_IPU_DI1_DW_SET2_I_ADDR(x))
|
|
#define HW_IPU_DI1_DW_SET2_I_RD(x) (HW_IPU_DI1_DW_SET2_I(x).U)
|
|
#define HW_IPU_DI1_DW_SET2_I_WR(x, v) (HW_IPU_DI1_DW_SET2_I(x).U = (v))
|
|
#define HW_IPU_DI1_DW_SET2_I_SET(x, v) (HW_IPU_DI1_DW_SET2_I_WR(x, HW_IPU_DI1_DW_SET2_I_RD(x) | (v)))
|
|
#define HW_IPU_DI1_DW_SET2_I_CLR(x, v) (HW_IPU_DI1_DW_SET2_I_WR(x, HW_IPU_DI1_DW_SET2_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_DW_SET2_I_TOG(x, v) (HW_IPU_DI1_DW_SET2_I_WR(x, HW_IPU_DI1_DW_SET2_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_DW_SET2_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_DW_SET2_I, field DI1_DATA_CNT_UP2_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I (0) //!< Bit position for IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I.
|
|
#define BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I (0x000001ff) //!< Bit mask for IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I) >> BP_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I.
|
|
#define BF_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I) & BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_UP2_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I(x, v) (HW_IPU_DI1_DW_SET2_I_WR(x, (HW_IPU_DI1_DW_SET2_I_RD(x) & ~BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I) | BF_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_UP2_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_SET2_I, field DI1_DATA_CNT_DOWN2_I[24:16] (RW)
|
|
*
|
|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I (16) //!< Bit position for IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I.
|
|
#define BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I (0x01ff0000) //!< Bit mask for IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I) >> BP_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I.
|
|
#define BF_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I) & BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_DOWN2_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I(x, v) (HW_IPU_DI1_DW_SET2_I_WR(x, (HW_IPU_DI1_DW_SET2_I_RD(x) & ~BM_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I) | BF_IPU_DI1_DW_SET2_I_DI1_DATA_CNT_DOWN2_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_DW_SET3_I - DI1 Data Wave Set 3 <i> Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_DW_SET3_I - DI1 Data Wave Set 3 <i> Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_dw_set3_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_dw_set3_i_bitfields
|
|
{
|
|
unsigned DI1_DATA_CNT_UP3_I : 9; //!< [8:0] Waveform's rising edge position.
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned DI1_DATA_CNT_DOWN3_I : 9; //!< [24:16] Waveform's falling edge position.
|
|
unsigned RESERVED1 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_dw_set3_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_DW_SET3_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_DW_SET3_I_ADDR(x) (REGS_IPU_BASE(x) + 0x48118)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_DW_SET3_I(x) (*(volatile hw_ipu_di1_dw_set3_i_t *) HW_IPU_DI1_DW_SET3_I_ADDR(x))
|
|
#define HW_IPU_DI1_DW_SET3_I_RD(x) (HW_IPU_DI1_DW_SET3_I(x).U)
|
|
#define HW_IPU_DI1_DW_SET3_I_WR(x, v) (HW_IPU_DI1_DW_SET3_I(x).U = (v))
|
|
#define HW_IPU_DI1_DW_SET3_I_SET(x, v) (HW_IPU_DI1_DW_SET3_I_WR(x, HW_IPU_DI1_DW_SET3_I_RD(x) | (v)))
|
|
#define HW_IPU_DI1_DW_SET3_I_CLR(x, v) (HW_IPU_DI1_DW_SET3_I_WR(x, HW_IPU_DI1_DW_SET3_I_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_DW_SET3_I_TOG(x, v) (HW_IPU_DI1_DW_SET3_I_WR(x, HW_IPU_DI1_DW_SET3_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_DW_SET3_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_DW_SET3_I, field DI1_DATA_CNT_UP3_I[8:0] (RW)
|
|
*
|
|
* Waveform's rising edge position. This field defines the Waveform's rising edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I (0) //!< Bit position for IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I.
|
|
#define BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I (0x000001ff) //!< Bit mask for IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I) >> BP_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I.
|
|
#define BF_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I) & BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_UP3_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I(x, v) (HW_IPU_DI1_DW_SET3_I_WR(x, (HW_IPU_DI1_DW_SET3_I_RD(x) & ~BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I) | BF_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_UP3_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_DW_SET3_I, field DI1_DATA_CNT_DOWN3_I[24:16] (RW)
|
|
*
|
|
* Waveform's falling edge position. This field defines the Waveform's falling edge position. The
|
|
* Waveform is mapped to a pint according to the corresponding di1_pt_*_<i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I (16) //!< Bit position for IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I.
|
|
#define BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I (0x01ff0000) //!< Bit mask for IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I.
|
|
|
|
//! @brief Get value of IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I from a register value.
|
|
#define BG_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I) >> BP_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I.
|
|
#define BF_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I) & BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DATA_CNT_DOWN3_I field to a new value.
|
|
#define BW_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I(x, v) (HW_IPU_DI1_DW_SET3_I_WR(x, (HW_IPU_DI1_DW_SET3_I_RD(x) & ~BM_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I) | BF_IPU_DI1_DW_SET3_I_DI1_DATA_CNT_DOWN3_I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_D1_STP_REP_I - DI1 Step Repeat <i> Registers
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_D1_STP_REP_I - DI1 Step Repeat <i> Registers (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_d1_stp_rep_i
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_d1_stp_rep_i_bitfields
|
|
{
|
|
unsigned DI1_STEP_REPEAT_2I_MINUS_1 : 12; //!< [11:0] Step Repeat <i>
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved
|
|
unsigned DI1_STEP_REPEAT_2I : 12; //!< [27:16] Step Repeat <i>
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved
|
|
} B;
|
|
} hw_ipu_d1_stp_rep_i_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_D1_STP_REP_I register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_D1_STP_REP_I_ADDR(x) (REGS_IPU_BASE(x) + 0x48148)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_D1_STP_REP_I(x) (*(volatile hw_ipu_d1_stp_rep_i_t *) HW_IPU_D1_STP_REP_I_ADDR(x))
|
|
#define HW_IPU_D1_STP_REP_I_RD(x) (HW_IPU_D1_STP_REP_I(x).U)
|
|
#define HW_IPU_D1_STP_REP_I_WR(x, v) (HW_IPU_D1_STP_REP_I(x).U = (v))
|
|
#define HW_IPU_D1_STP_REP_I_SET(x, v) (HW_IPU_D1_STP_REP_I_WR(x, HW_IPU_D1_STP_REP_I_RD(x) | (v)))
|
|
#define HW_IPU_D1_STP_REP_I_CLR(x, v) (HW_IPU_D1_STP_REP_I_WR(x, HW_IPU_D1_STP_REP_I_RD(x) & ~(v)))
|
|
#define HW_IPU_D1_STP_REP_I_TOG(x, v) (HW_IPU_D1_STP_REP_I_WR(x, HW_IPU_D1_STP_REP_I_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_D1_STP_REP_I bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_D1_STP_REP_I, field DI1_STEP_REPEAT_2I_MINUS_1[11:0] (RW)
|
|
*
|
|
* Step Repeat <i> This fields defines the amount of repetitions that will be performed by the
|
|
* counter <i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1 (0) //!< Bit position for IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1.
|
|
#define BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1 (0x00000fff) //!< Bit mask for IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1.
|
|
|
|
//! @brief Get value of IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1 from a register value.
|
|
#define BG_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1) >> BP_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1)
|
|
|
|
//! @brief Format value for bitfield IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1.
|
|
#define BF_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1) & BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_STEP_REPEAT_2I_MINUS_1 field to a new value.
|
|
#define BW_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1(x, v) (HW_IPU_D1_STP_REP_I_WR(x, (HW_IPU_D1_STP_REP_I_RD(x) & ~BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1) | BF_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I_MINUS_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_D1_STP_REP_I, field DI1_STEP_REPEAT_2I[27:16] (RW)
|
|
*
|
|
* Step Repeat <i> This fields defines the amount of repetitions that will be performed by the
|
|
* counter <i>
|
|
*/
|
|
//@{
|
|
#define BP_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I (16) //!< Bit position for IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I.
|
|
#define BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I (0x0fff0000) //!< Bit mask for IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I.
|
|
|
|
//! @brief Get value of IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I from a register value.
|
|
#define BG_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I) >> BP_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I)
|
|
|
|
//! @brief Format value for bitfield IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I.
|
|
#define BF_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I) & BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_STEP_REPEAT_2I field to a new value.
|
|
#define BW_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I(x, v) (HW_IPU_D1_STP_REP_I_WR(x, (HW_IPU_D1_STP_REP_I_RD(x) & ~BM_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I) | BF_IPU_D1_STP_REP_I_DI1_STEP_REPEAT_2I(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_STP_REP_9 - DI1Step Repeat 9 Registers
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_STP_REP_9 - DI1Step Repeat 9 Registers (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_stp_rep_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_stp_rep_9_bitfields
|
|
{
|
|
unsigned DI1_STEP_REPEAT_9 : 12; //!< [11:0] Step Repeat 9
|
|
unsigned RESERVED0 : 20; //!< [31:12] Reserved
|
|
} B;
|
|
} hw_ipu_di1_stp_rep_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_STP_REP_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_STP_REP_9_ADDR(x) (REGS_IPU_BASE(x) + 0x48158)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_STP_REP_9(x) (*(volatile hw_ipu_di1_stp_rep_9_t *) HW_IPU_DI1_STP_REP_9_ADDR(x))
|
|
#define HW_IPU_DI1_STP_REP_9_RD(x) (HW_IPU_DI1_STP_REP_9(x).U)
|
|
#define HW_IPU_DI1_STP_REP_9_WR(x, v) (HW_IPU_DI1_STP_REP_9(x).U = (v))
|
|
#define HW_IPU_DI1_STP_REP_9_SET(x, v) (HW_IPU_DI1_STP_REP_9_WR(x, HW_IPU_DI1_STP_REP_9_RD(x) | (v)))
|
|
#define HW_IPU_DI1_STP_REP_9_CLR(x, v) (HW_IPU_DI1_STP_REP_9_WR(x, HW_IPU_DI1_STP_REP_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_STP_REP_9_TOG(x, v) (HW_IPU_DI1_STP_REP_9_WR(x, HW_IPU_DI1_STP_REP_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_STP_REP_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_STP_REP_9, field DI1_STEP_REPEAT_9[11:0] (RW)
|
|
*
|
|
* Step Repeat 9 This fields defines the amount of repetitions that will be performed by the counter
|
|
* 9.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9 (0) //!< Bit position for IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9.
|
|
#define BM_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9 (0x00000fff) //!< Bit mask for IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9.
|
|
|
|
//! @brief Get value of IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9 from a register value.
|
|
#define BG_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9) >> BP_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9.
|
|
#define BF_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9) & BM_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_STEP_REPEAT_9 field to a new value.
|
|
#define BW_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9(x, v) (HW_IPU_DI1_STP_REP_9_WR(x, (HW_IPU_DI1_STP_REP_9_RD(x) & ~BM_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9) | BF_IPU_DI1_STP_REP_9_DI1_STEP_REPEAT_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SER_CONF - DI1 Serial Display Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SER_CONF - DI1 Serial Display Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_ser_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_ser_conf_bitfields
|
|
{
|
|
unsigned DI1_WAIT4SERIAL : 1; //!< [0] Wait for Serial
|
|
unsigned DI1_SERIAL_CS_POLARITY : 1; //!< [1] Serial Chip Select Polarity
|
|
unsigned DI1_SERIAL_RS_POLARITY : 1; //!< [2] Serial RS Polarity
|
|
unsigned DI1_SERIAL_DATA_POLARITY : 1; //!< [3] Serial Data Polarity
|
|
unsigned DI1_SER_CLK_POLARITY : 1; //!< [4] Serial Clock Polarity
|
|
unsigned DI1_LLA_SER_ACCESS : 1; //!< [5] Direct Low Level Access to Serial display
|
|
unsigned RESERVED0 : 2; //!< [7:6] Reserved
|
|
unsigned DI1_SERIAL_LATCH : 8; //!< [15:8] DI1 Serial Latch
|
|
unsigned DI1_SERIAL_LLA_PNTR_RS_W_0 : 4; //!< [19:16] RS 0 waveform pointer for write low level access
|
|
unsigned DI1_SERIAL_LLA_PNTR_RS_W_1 : 4; //!< [23:20] RS 1 waveform pointer for write low level access
|
|
unsigned DI1_SERIAL_LLA_PNTR_RS_R_0 : 4; //!< [27:24] RS 2 waveform pointer for low level access
|
|
unsigned DI1_SERIAL_LLA_PNTR_RS_R_1 : 4; //!< [31:28] RS 3 waveform pointer for read low level access
|
|
} B;
|
|
} hw_ipu_di1_ser_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SER_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SER_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x4815c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SER_CONF(x) (*(volatile hw_ipu_di1_ser_conf_t *) HW_IPU_DI1_SER_CONF_ADDR(x))
|
|
#define HW_IPU_DI1_SER_CONF_RD(x) (HW_IPU_DI1_SER_CONF(x).U)
|
|
#define HW_IPU_DI1_SER_CONF_WR(x, v) (HW_IPU_DI1_SER_CONF(x).U = (v))
|
|
#define HW_IPU_DI1_SER_CONF_SET(x, v) (HW_IPU_DI1_SER_CONF_WR(x, HW_IPU_DI1_SER_CONF_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SER_CONF_CLR(x, v) (HW_IPU_DI1_SER_CONF_WR(x, HW_IPU_DI1_SER_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SER_CONF_TOG(x, v) (HW_IPU_DI1_SER_CONF_WR(x, HW_IPU_DI1_SER_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SER_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_WAIT4SERIAL[0] (RW)
|
|
*
|
|
* Wait for Serial When the parallel display share pins with the serial port. Accessing the parallel
|
|
* port is not allowed till the serial port completes its access.
|
|
*
|
|
* Values:
|
|
* - 0 - The parallel port should not wait to the serial port as the pins are not shared
|
|
* - 1 - The parallel port should wait to the serial port as the pins are shared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL (0) //!< Bit position for IPU_DI1_SER_CONF_DI1_WAIT4SERIAL.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL (0x00000001) //!< Bit mask for IPU_DI1_SER_CONF_DI1_WAIT4SERIAL.
|
|
|
|
//! @brief Get value of IPU_DI1_SER_CONF_DI1_WAIT4SERIAL from a register value.
|
|
#define BG_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL) >> BP_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_WAIT4SERIAL.
|
|
#define BF_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL) & BM_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_WAIT4SERIAL field to a new value.
|
|
#define BW_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL) | BF_IPU_DI1_SER_CONF_DI1_WAIT4SERIAL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_CS_POLARITY[1] (RW)
|
|
*
|
|
* Serial Chip Select Polarity The output polarity of the SER_CS pin
|
|
*
|
|
* Values:
|
|
* - 0 - The CS is not inverted
|
|
* - 1 - The CS is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY (1) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY (0x00000002) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY from a register value.
|
|
#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY.
|
|
#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SERIAL_CS_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_CS_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_RS_POLARITY[2] (RW)
|
|
*
|
|
* Serial RS Polarity The output polarity of the SER_RS pin
|
|
*
|
|
* Values:
|
|
* - 0 - The RS is not inverted
|
|
* - 1 - The RS is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY (2) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY (0x00000004) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY from a register value.
|
|
#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY.
|
|
#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SERIAL_RS_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_RS_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_DATA_POLARITY[3] (RW)
|
|
*
|
|
* Serial Data Polarity The output polarity of the SER_DATA pin
|
|
*
|
|
* Values:
|
|
* - 0 - The data is not inverted
|
|
* - 1 - The data is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY (3) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY (0x00000008) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY.
|
|
#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SERIAL_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_SER_CLK_POLARITY[4] (RW)
|
|
*
|
|
* Serial Clock Polarity The output polarity of the SER_CLK pin
|
|
*
|
|
* Values:
|
|
* - 0 - The clock is not inverted
|
|
* - 1 - The clock is inverted
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY (4) //!< Bit position for IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY (0x00000010) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY from a register value.
|
|
#define BG_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY) >> BP_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY.
|
|
#define BF_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY) & BM_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SER_CLK_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY) | BF_IPU_DI1_SER_CONF_DI1_SER_CLK_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_LLA_SER_ACCESS[5] (RW)
|
|
*
|
|
* Direct Low Level Access to Serial display
|
|
*
|
|
* Values:
|
|
* - 0 - ARM platform access to the serial display port is not done directly, hence other source are allowed
|
|
* to access the serial port. The arbitration is done automatically
|
|
* - 1 - ARM platform access is performed via a direct path to the serial display in LLA mode, in this mode
|
|
* only the ARM platform in LLA mode can access the serial port
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS (5) //!< Bit position for IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS (0x00000020) //!< Bit mask for IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS.
|
|
|
|
//! @brief Get value of IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS from a register value.
|
|
#define BG_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS) >> BP_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS.
|
|
#define BF_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS) & BM_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_LLA_SER_ACCESS field to a new value.
|
|
#define BW_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS) | BF_IPU_DI1_SER_CONF_DI1_LLA_SER_ACCESS(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_LATCH[15:8] (RW)
|
|
*
|
|
* DI1 Serial Latch This field defines how many cycles to insert between serial read accesses start
|
|
* to data sampling in the
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH (8) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_LATCH.
|
|
#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH (0x0000ff00) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_LATCH.
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//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_LATCH from a register value.
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#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH)
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//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_LATCH.
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#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_SERIAL_LATCH field to a new value.
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#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_LATCH(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_LLA_PNTR_RS_W_0[19:16] (RW)
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*
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* RS 0 waveform pointer for write low level access This pointer defines which waveform set will be
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* chosen when the write low level access is targeted to RS group 0.
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*
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* Values:
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* - 0000 - Waveform set #1
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* - 0001 - Waveform set #2
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* - 1011 - Waveform set #12
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* - 1100 - Reserved
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* - 1100 - Reserved
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* - 1101 - Reserved
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*/
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//@{
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#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0 (16) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0.
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#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0 (0x000f0000) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0.
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//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0 from a register value.
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#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0)
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//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0.
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#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_SERIAL_LLA_PNTR_RS_W_0 field to a new value.
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#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_0(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_LLA_PNTR_RS_W_1[23:20] (RW)
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*
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* RS 1 waveform pointer for write low level access This pointer defines which waveform set will be
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* chosen when the write low level access is targeted to RS group 1.
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*
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* Values:
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* - 0000 - Waveform set #1
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* - 0001 - Waveform set #2
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* - 1011 - Waveform set #12
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* - 1100 - Reserved
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* - 1100 - Reserved
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* - 1101 - Reserved
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*/
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//@{
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#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1 (20) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1.
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#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1 (0x00f00000) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1.
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//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1 from a register value.
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#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1)
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//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1.
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#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_SERIAL_LLA_PNTR_RS_W_1 field to a new value.
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#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_W_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_LLA_PNTR_RS_R_0[27:24] (RW)
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*
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* RS 2 waveform pointer for low level access This pointer defines which waveform set will be chosen
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* when the read low level access is targeted to RS group 0.
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*
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* Values:
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* - 0000 - Waveform set #1
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* - 0001 - Waveform set #2
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* - 1011 - Waveform set #12
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* - 1100 - Reserved
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* - 1100 - Reserved
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* - 1101 - Reserved
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*/
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//@{
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#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0 (24) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0.
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#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0 (0x0f000000) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0.
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//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0 from a register value.
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#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0)
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//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0.
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#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_SERIAL_LLA_PNTR_RS_R_0 field to a new value.
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#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_0(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SER_CONF, field DI1_SERIAL_LLA_PNTR_RS_R_1[31:28] (RW)
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*
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* RS 3 waveform pointer for read low level access This pointer defines which waveform set will be
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* chosen when the read low level access is targeted to RS group 1.
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*
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|
* Values:
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|
* - 0000 - Waveform set #1
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* - 0001 - Waveform set #2
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* - 1011 - Waveform set #12
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* - 1100 - Reserved
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* - 1100 - Reserved
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* - 1101 - Reserved
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*/
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//@{
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#define BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1 (28) //!< Bit position for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1.
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#define BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1 (0xf0000000) //!< Bit mask for IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1.
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//! @brief Get value of IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1 from a register value.
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#define BG_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1) >> BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1)
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//! @brief Format value for bitfield IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1.
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#define BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1) & BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI1_SERIAL_LLA_PNTR_RS_R_1 field to a new value.
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#define BW_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1(x, v) (HW_IPU_DI1_SER_CONF_WR(x, (HW_IPU_DI1_SER_CONF_RD(x) & ~BM_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1) | BF_IPU_DI1_SER_CONF_DI1_SERIAL_LLA_PNTR_RS_R_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DI1_SSC - DI1 Special Signals Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DI1_SSC - DI1 Special Signals Control Register (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_di1_ssc
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{
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reg32_t U;
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struct _hw_ipu_di1_ssc_bitfields
|
|
{
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unsigned DI1_BYTE_EN_PNTR : 3; //!< [2:0] Byte Enable Pointer
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unsigned DI1_BYTE_EN_RD_IN : 1; //!< [3] Byte Enable Read In
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unsigned DI1_BYTE_EN_POLARITY : 1; //!< [4] Byte Enable polarity
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unsigned DI1_WAIT_ON : 1; //!< [5] Wait On
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unsigned RESERVED0 : 10; //!< [15:6] Reserved.
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unsigned DI1_CS_ERM : 1; //!< [16] DI1 GLUELOGIC error recovery mode.
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unsigned DI1_PIN11_ERM : 1; //!< [17] DI1 PIN11 error recovery mode.
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unsigned DI1_PIN12_ERM : 1; //!< [18] DI1 PIN12 error recovery mode.
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unsigned DI1_PIN13_ERM : 1; //!< [19] DI1 PIN13 error recovery mode.
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unsigned DI1_PIN14_ERM : 1; //!< [20] DI1 PIN14 error recovery mode.
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unsigned DI1_PIN15_ERM : 1; //!< [21] DI1 PIN15 error recovery mode.
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unsigned DI1_PIN16_ERM : 1; //!< [22] DI1 PIN16 error recovery mode.
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unsigned DI1_PIN17_ERM : 1; //!< [23] DI1 PIN17 error recovery mode.
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unsigned RESERVED1 : 8; //!< [31:24] Reserved.
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} B;
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} hw_ipu_di1_ssc_t;
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#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DI1_SSC register
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|
*/
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//@{
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|
#define HW_IPU_DI1_SSC_ADDR(x) (REGS_IPU_BASE(x) + 0x48160)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DI1_SSC(x) (*(volatile hw_ipu_di1_ssc_t *) HW_IPU_DI1_SSC_ADDR(x))
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#define HW_IPU_DI1_SSC_RD(x) (HW_IPU_DI1_SSC(x).U)
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#define HW_IPU_DI1_SSC_WR(x, v) (HW_IPU_DI1_SSC(x).U = (v))
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#define HW_IPU_DI1_SSC_SET(x, v) (HW_IPU_DI1_SSC_WR(x, HW_IPU_DI1_SSC_RD(x) | (v)))
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#define HW_IPU_DI1_SSC_CLR(x, v) (HW_IPU_DI1_SSC_WR(x, HW_IPU_DI1_SSC_RD(x) & ~(v)))
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#define HW_IPU_DI1_SSC_TOG(x, v) (HW_IPU_DI1_SSC_WR(x, HW_IPU_DI1_SSC_RD(x) ^ (v)))
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#endif
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//@}
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|
|
/*
|
|
* constants & macros for individual IPU_DI1_SSC bitfields
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|
*/
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|
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/*! @name Register IPU_DI1_SSC, field DI1_BYTE_EN_PNTR[2:0] (RW)
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*
|
|
* Byte Enable Pointer This pointer selects the pin asserted along with the byte enables signals
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|
*
|
|
* Values:
|
|
* - 000 - wave form of byte enable as pin_11
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|
* - 001 - wave form of byte enable as pin_12
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|
* - 111 - wave form of byte enable as suitable CS pin
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*/
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//@{
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#define BP_IPU_DI1_SSC_DI1_BYTE_EN_PNTR (0) //!< Bit position for IPU_DI1_SSC_DI1_BYTE_EN_PNTR.
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#define BM_IPU_DI1_SSC_DI1_BYTE_EN_PNTR (0x00000007) //!< Bit mask for IPU_DI1_SSC_DI1_BYTE_EN_PNTR.
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//! @brief Get value of IPU_DI1_SSC_DI1_BYTE_EN_PNTR from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_BYTE_EN_PNTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_BYTE_EN_PNTR) >> BP_IPU_DI1_SSC_DI1_BYTE_EN_PNTR)
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//! @brief Format value for bitfield IPU_DI1_SSC_DI1_BYTE_EN_PNTR.
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|
#define BF_IPU_DI1_SSC_DI1_BYTE_EN_PNTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_BYTE_EN_PNTR) & BM_IPU_DI1_SSC_DI1_BYTE_EN_PNTR)
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|
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI1_BYTE_EN_PNTR field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_BYTE_EN_PNTR(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_BYTE_EN_PNTR) | BF_IPU_DI1_SSC_DI1_BYTE_EN_PNTR(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SSC, field DI1_BYTE_EN_RD_IN[3] (RW)
|
|
*
|
|
* Byte Enable Read In This bit selects the source of the byte enable pins
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|
*
|
|
* Values:
|
|
* - 0 - The byte enable signals are routed via bits [17:16] of the display's data for both read and write
|
|
* - 1 - The write byte enable signals are routed via bits [17:16] of the display's data, The read byte
|
|
* enable signals are routed via bits [19:18 of the display's data
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|
*/
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|
//@{
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|
#define BP_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN (3) //!< Bit position for IPU_DI1_SSC_DI1_BYTE_EN_RD_IN.
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#define BM_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN (0x00000008) //!< Bit mask for IPU_DI1_SSC_DI1_BYTE_EN_RD_IN.
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//! @brief Get value of IPU_DI1_SSC_DI1_BYTE_EN_RD_IN from a register value.
|
|
#define BG_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN) >> BP_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN)
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|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_BYTE_EN_RD_IN.
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|
#define BF_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN) & BM_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_BYTE_EN_RD_IN field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN) | BF_IPU_DI1_SSC_DI1_BYTE_EN_RD_IN(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SSC, field DI1_BYTE_EN_POLARITY[4] (RW)
|
|
*
|
|
* Byte Enable polarity This bit defines the polarity of the byte enable signals to the display.
|
|
*
|
|
* Values:
|
|
* - 0 - active low.
|
|
* - 1 - active high.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY (4) //!< Bit position for IPU_DI1_SSC_DI1_BYTE_EN_POLARITY.
|
|
#define BM_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY (0x00000010) //!< Bit mask for IPU_DI1_SSC_DI1_BYTE_EN_POLARITY.
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|
|
|
//! @brief Get value of IPU_DI1_SSC_DI1_BYTE_EN_POLARITY from a register value.
|
|
#define BG_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY) >> BP_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_BYTE_EN_POLARITY.
|
|
#define BF_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY) & BM_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_BYTE_EN_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY) | BF_IPU_DI1_SSC_DI1_BYTE_EN_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SSC, field DI1_WAIT_ON[5] (RW)
|
|
*
|
|
* Wait On This field defines the DC's response to WAIT signal
|
|
*
|
|
* Values:
|
|
* - 0 - The DC continues the flow regardless the WAIT signal.
|
|
* - 1 - The DC holds the flow as long as WAIT is asserted.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SSC_DI1_WAIT_ON (5) //!< Bit position for IPU_DI1_SSC_DI1_WAIT_ON.
|
|
#define BM_IPU_DI1_SSC_DI1_WAIT_ON (0x00000020) //!< Bit mask for IPU_DI1_SSC_DI1_WAIT_ON.
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//! @brief Get value of IPU_DI1_SSC_DI1_WAIT_ON from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_WAIT_ON(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_WAIT_ON) >> BP_IPU_DI1_SSC_DI1_WAIT_ON)
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//! @brief Format value for bitfield IPU_DI1_SSC_DI1_WAIT_ON.
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|
#define BF_IPU_DI1_SSC_DI1_WAIT_ON(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_WAIT_ON) & BM_IPU_DI1_SSC_DI1_WAIT_ON)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_WAIT_ON field to a new value.
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|
#define BW_IPU_DI1_SSC_DI1_WAIT_ON(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_WAIT_ON) | BF_IPU_DI1_SSC_DI1_WAIT_ON(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SSC, field DI1_CS_ERM[16] (RW)
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*
|
|
* DI1 GLUELOGIC error recovery mode. This bit defines the error recovery mode of the GLUELOGIC.
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|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the GLUELOGIC following a display error detection.
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|
* - 1 - The GLUELOGIC is release in case of a synchronous display error. The release will be done on the
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* next VSYNC.
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|
*/
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//@{
|
|
#define BP_IPU_DI1_SSC_DI1_CS_ERM (16) //!< Bit position for IPU_DI1_SSC_DI1_CS_ERM.
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#define BM_IPU_DI1_SSC_DI1_CS_ERM (0x00010000) //!< Bit mask for IPU_DI1_SSC_DI1_CS_ERM.
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//! @brief Get value of IPU_DI1_SSC_DI1_CS_ERM from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_CS_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_CS_ERM) >> BP_IPU_DI1_SSC_DI1_CS_ERM)
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//! @brief Format value for bitfield IPU_DI1_SSC_DI1_CS_ERM.
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#define BF_IPU_DI1_SSC_DI1_CS_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_CS_ERM) & BM_IPU_DI1_SSC_DI1_CS_ERM)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DI1_CS_ERM field to a new value.
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|
#define BW_IPU_DI1_SSC_DI1_CS_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_CS_ERM) | BF_IPU_DI1_SSC_DI1_CS_ERM(v)))
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#endif
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//@}
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/*! @name Register IPU_DI1_SSC, field DI1_PIN11_ERM[17] (RW)
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*
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|
* DI1 PIN11 error recovery mode. This bit defines the error recovery mode of the PIN11 pin.
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*
|
|
* Values:
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|
* - 0 - Nothing is done to the PIN11 pin following a display error detection.
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* - 1 - The PIN11 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC.
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|
*/
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//@{
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|
#define BP_IPU_DI1_SSC_DI1_PIN11_ERM (17) //!< Bit position for IPU_DI1_SSC_DI1_PIN11_ERM.
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#define BM_IPU_DI1_SSC_DI1_PIN11_ERM (0x00020000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN11_ERM.
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//! @brief Get value of IPU_DI1_SSC_DI1_PIN11_ERM from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_PIN11_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN11_ERM) >> BP_IPU_DI1_SSC_DI1_PIN11_ERM)
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//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN11_ERM.
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|
#define BF_IPU_DI1_SSC_DI1_PIN11_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN11_ERM) & BM_IPU_DI1_SSC_DI1_PIN11_ERM)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN11_ERM field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_PIN11_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN11_ERM) | BF_IPU_DI1_SSC_DI1_PIN11_ERM(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DI1_SSC, field DI1_PIN12_ERM[18] (RW)
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|
*
|
|
* DI1 PIN12 error recovery mode. This bit defines the error recovery mode of the PIN12 pin.
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|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN12 pin following a display error detection.
|
|
* - 1 - The PIN12 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC.
|
|
*/
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|
//@{
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|
#define BP_IPU_DI1_SSC_DI1_PIN12_ERM (18) //!< Bit position for IPU_DI1_SSC_DI1_PIN12_ERM.
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#define BM_IPU_DI1_SSC_DI1_PIN12_ERM (0x00040000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN12_ERM.
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//! @brief Get value of IPU_DI1_SSC_DI1_PIN12_ERM from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_PIN12_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN12_ERM) >> BP_IPU_DI1_SSC_DI1_PIN12_ERM)
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|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN12_ERM.
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|
#define BF_IPU_DI1_SSC_DI1_PIN12_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN12_ERM) & BM_IPU_DI1_SSC_DI1_PIN12_ERM)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN12_ERM field to a new value.
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|
#define BW_IPU_DI1_SSC_DI1_PIN12_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN12_ERM) | BF_IPU_DI1_SSC_DI1_PIN12_ERM(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DI1_SSC, field DI1_PIN13_ERM[19] (RW)
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|
*
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|
* DI1 PIN13 error recovery mode. This bit defines the error recovery mode of the PIN13 pin.
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|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN13 pin following a display error detection.
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|
* - 1 - The PIN13 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC.
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|
*/
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|
//@{
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|
#define BP_IPU_DI1_SSC_DI1_PIN13_ERM (19) //!< Bit position for IPU_DI1_SSC_DI1_PIN13_ERM.
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|
#define BM_IPU_DI1_SSC_DI1_PIN13_ERM (0x00080000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN13_ERM.
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|
|
//! @brief Get value of IPU_DI1_SSC_DI1_PIN13_ERM from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_PIN13_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN13_ERM) >> BP_IPU_DI1_SSC_DI1_PIN13_ERM)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN13_ERM.
|
|
#define BF_IPU_DI1_SSC_DI1_PIN13_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN13_ERM) & BM_IPU_DI1_SSC_DI1_PIN13_ERM)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN13_ERM field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_PIN13_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN13_ERM) | BF_IPU_DI1_SSC_DI1_PIN13_ERM(v)))
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|
#endif
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|
//@}
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|
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/*! @name Register IPU_DI1_SSC, field DI1_PIN14_ERM[20] (RW)
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|
*
|
|
* DI1 PIN14 error recovery mode. This bit defines the error recovery mode of the PIN14 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN14 pin following a display error detection.
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|
* - 1 - The PIN14 pin is cleared in case of a synchronous display error. The clear will be done on the next
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|
* VSYNC.
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|
*/
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|
//@{
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|
#define BP_IPU_DI1_SSC_DI1_PIN14_ERM (20) //!< Bit position for IPU_DI1_SSC_DI1_PIN14_ERM.
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|
#define BM_IPU_DI1_SSC_DI1_PIN14_ERM (0x00100000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN14_ERM.
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|
|
//! @brief Get value of IPU_DI1_SSC_DI1_PIN14_ERM from a register value.
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|
#define BG_IPU_DI1_SSC_DI1_PIN14_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN14_ERM) >> BP_IPU_DI1_SSC_DI1_PIN14_ERM)
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|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN14_ERM.
|
|
#define BF_IPU_DI1_SSC_DI1_PIN14_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN14_ERM) & BM_IPU_DI1_SSC_DI1_PIN14_ERM)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN14_ERM field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_PIN14_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN14_ERM) | BF_IPU_DI1_SSC_DI1_PIN14_ERM(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DI1_SSC, field DI1_PIN15_ERM[21] (RW)
|
|
*
|
|
* DI1 PIN15 error recovery mode. This bit defines the error recovery mode of the PIN15 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN15 pin following a display error detection.
|
|
* - 1 - The PIN15 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SSC_DI1_PIN15_ERM (21) //!< Bit position for IPU_DI1_SSC_DI1_PIN15_ERM.
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|
#define BM_IPU_DI1_SSC_DI1_PIN15_ERM (0x00200000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN15_ERM.
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|
|
|
//! @brief Get value of IPU_DI1_SSC_DI1_PIN15_ERM from a register value.
|
|
#define BG_IPU_DI1_SSC_DI1_PIN15_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN15_ERM) >> BP_IPU_DI1_SSC_DI1_PIN15_ERM)
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|
|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN15_ERM.
|
|
#define BF_IPU_DI1_SSC_DI1_PIN15_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN15_ERM) & BM_IPU_DI1_SSC_DI1_PIN15_ERM)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN15_ERM field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_PIN15_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN15_ERM) | BF_IPU_DI1_SSC_DI1_PIN15_ERM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SSC, field DI1_PIN16_ERM[22] (RW)
|
|
*
|
|
* DI1 PIN16 error recovery mode. This bit defines the error recovery mode of the PIN16 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN16 pin following a display error detection.
|
|
* - 1 - The PIN16 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SSC_DI1_PIN16_ERM (22) //!< Bit position for IPU_DI1_SSC_DI1_PIN16_ERM.
|
|
#define BM_IPU_DI1_SSC_DI1_PIN16_ERM (0x00400000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN16_ERM.
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|
|
|
//! @brief Get value of IPU_DI1_SSC_DI1_PIN16_ERM from a register value.
|
|
#define BG_IPU_DI1_SSC_DI1_PIN16_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN16_ERM) >> BP_IPU_DI1_SSC_DI1_PIN16_ERM)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN16_ERM.
|
|
#define BF_IPU_DI1_SSC_DI1_PIN16_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN16_ERM) & BM_IPU_DI1_SSC_DI1_PIN16_ERM)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN16_ERM field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_PIN16_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN16_ERM) | BF_IPU_DI1_SSC_DI1_PIN16_ERM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_SSC, field DI1_PIN17_ERM[23] (RW)
|
|
*
|
|
* DI1 PIN17 error recovery mode. This bit defines the error recovery mode of the PIN17 pin.
|
|
*
|
|
* Values:
|
|
* - 0 - Nothing is done to the PIN17 pin following a display error detection.
|
|
* - 1 - The PIN17 pin is cleared in case of a synchronous display error. The clear will be done on the next
|
|
* VSYNC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SSC_DI1_PIN17_ERM (23) //!< Bit position for IPU_DI1_SSC_DI1_PIN17_ERM.
|
|
#define BM_IPU_DI1_SSC_DI1_PIN17_ERM (0x00800000) //!< Bit mask for IPU_DI1_SSC_DI1_PIN17_ERM.
|
|
|
|
//! @brief Get value of IPU_DI1_SSC_DI1_PIN17_ERM from a register value.
|
|
#define BG_IPU_DI1_SSC_DI1_PIN17_ERM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SSC_DI1_PIN17_ERM) >> BP_IPU_DI1_SSC_DI1_PIN17_ERM)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SSC_DI1_PIN17_ERM.
|
|
#define BF_IPU_DI1_SSC_DI1_PIN17_ERM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SSC_DI1_PIN17_ERM) & BM_IPU_DI1_SSC_DI1_PIN17_ERM)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_PIN17_ERM field to a new value.
|
|
#define BW_IPU_DI1_SSC_DI1_PIN17_ERM(x, v) (HW_IPU_DI1_SSC_WR(x, (HW_IPU_DI1_SSC_RD(x) & ~BM_IPU_DI1_SSC_DI1_PIN17_ERM) | BF_IPU_DI1_SSC_DI1_PIN17_ERM(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_POL - DI1 Polarity Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_POL - DI1 Polarity Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_pol
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_pol_bitfields
|
|
{
|
|
unsigned DI1_DRDY_POLARITY : 7; //!< [6:0] DI1 output dynamic pin's polarity for synchronous access
|
|
unsigned DI1_DRDY_DATA_POLARITY : 1; //!< [7] Data Polarity associated with DRDY
|
|
unsigned DI1_CS0_POLARITY : 7; //!< [14:8] DI1 output pin's polarity for CS1
|
|
unsigned DI1_CS0_DATA_POLARITY : 1; //!< [15] Data Polarity associated with CS0
|
|
unsigned DI1_CS1_POLARITY : 7; //!< [22:16] DI1 output pin's polarity for CS1
|
|
unsigned DI1_CS1_DATA_POLARITY : 1; //!< [23] Data Polarity associated with CS1
|
|
unsigned DI1_CS0_BYTE_EN_POLARITY : 1; //!< [24] Byte Enable associated with CS0 polarity
|
|
unsigned DI1_CS1_BYTE_EN_POLARITY : 1; //!< [25] Byte Enable associated with CS1 polarity
|
|
unsigned DI1_WAIT_POLARITY : 1; //!< [26] WAIT polarity
|
|
unsigned RESERVED0 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_pol_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_POL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_POL_ADDR(x) (REGS_IPU_BASE(x) + 0x48164)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_POL(x) (*(volatile hw_ipu_di1_pol_t *) HW_IPU_DI1_POL_ADDR(x))
|
|
#define HW_IPU_DI1_POL_RD(x) (HW_IPU_DI1_POL(x).U)
|
|
#define HW_IPU_DI1_POL_WR(x, v) (HW_IPU_DI1_POL(x).U = (v))
|
|
#define HW_IPU_DI1_POL_SET(x, v) (HW_IPU_DI1_POL_WR(x, HW_IPU_DI1_POL_RD(x) | (v)))
|
|
#define HW_IPU_DI1_POL_CLR(x, v) (HW_IPU_DI1_POL_WR(x, HW_IPU_DI1_POL_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_POL_TOG(x, v) (HW_IPU_DI1_POL_WR(x, HW_IPU_DI1_POL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_POL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_DRDY_POLARITY[6:0] (RW)
|
|
*
|
|
* DI1 output dynamic pin's polarity for synchronous access This bits define the polarity of each of
|
|
* the DI's outputs when synchronous display access is asserted The pins' default polarity is the
|
|
* same as defined in the di0_drdy_polarity bits
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_DRDY_POLARITY (0) //!< Bit position for IPU_DI1_POL_DI1_DRDY_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_DRDY_POLARITY (0x0000007f) //!< Bit mask for IPU_DI1_POL_DI1_DRDY_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_DRDY_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_DRDY_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_DRDY_POLARITY) >> BP_IPU_DI1_POL_DI1_DRDY_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_DRDY_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_DRDY_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_DRDY_POLARITY) & BM_IPU_DI1_POL_DI1_DRDY_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DRDY_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_DRDY_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_DRDY_POLARITY) | BF_IPU_DI1_POL_DI1_DRDY_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_DRDY_DATA_POLARITY[7] (RW)
|
|
*
|
|
* Data Polarity associated with DRDY
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY (7) //!< Bit position for IPU_DI1_POL_DI1_DRDY_DATA_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY (0x00000080) //!< Bit mask for IPU_DI1_POL_DI1_DRDY_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_DRDY_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY) >> BP_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_DRDY_DATA_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY) & BM_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_DRDY_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY) | BF_IPU_DI1_POL_DI1_DRDY_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_CS0_POLARITY[14:8] (RW)
|
|
*
|
|
* DI1 output pin's polarity for CS1 This bits define the polarity of each of the DI's outputs when
|
|
* CS1 is asserted
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_CS0_POLARITY (8) //!< Bit position for IPU_DI1_POL_DI1_CS0_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_CS0_POLARITY (0x00007f00) //!< Bit mask for IPU_DI1_POL_DI1_CS0_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_CS0_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_CS0_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_CS0_POLARITY) >> BP_IPU_DI1_POL_DI1_CS0_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_CS0_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_CS0_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_CS0_POLARITY) & BM_IPU_DI1_POL_DI1_CS0_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CS0_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_CS0_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_CS0_POLARITY) | BF_IPU_DI1_POL_DI1_CS0_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_CS0_DATA_POLARITY[15] (RW)
|
|
*
|
|
* Data Polarity associated with CS0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_CS0_DATA_POLARITY (15) //!< Bit position for IPU_DI1_POL_DI1_CS0_DATA_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_CS0_DATA_POLARITY (0x00008000) //!< Bit mask for IPU_DI1_POL_DI1_CS0_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_CS0_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_CS0_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_CS0_DATA_POLARITY) >> BP_IPU_DI1_POL_DI1_CS0_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_CS0_DATA_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_CS0_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_CS0_DATA_POLARITY) & BM_IPU_DI1_POL_DI1_CS0_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CS0_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_CS0_DATA_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_CS0_DATA_POLARITY) | BF_IPU_DI1_POL_DI1_CS0_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_CS1_POLARITY[22:16] (RW)
|
|
*
|
|
* DI1 output pin's polarity for CS1 This bits define the polarity of each of the DI's outputs when
|
|
* CS1 is asserted
|
|
*
|
|
* Values:
|
|
* - 0 - The output pin is active low
|
|
* - 1 - The output pin is active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_CS1_POLARITY (16) //!< Bit position for IPU_DI1_POL_DI1_CS1_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_CS1_POLARITY (0x007f0000) //!< Bit mask for IPU_DI1_POL_DI1_CS1_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_CS1_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_CS1_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_CS1_POLARITY) >> BP_IPU_DI1_POL_DI1_CS1_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_CS1_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_CS1_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_CS1_POLARITY) & BM_IPU_DI1_POL_DI1_CS1_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CS1_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_CS1_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_CS1_POLARITY) | BF_IPU_DI1_POL_DI1_CS1_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_CS1_DATA_POLARITY[23] (RW)
|
|
*
|
|
* Data Polarity associated with CS1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_CS1_DATA_POLARITY (23) //!< Bit position for IPU_DI1_POL_DI1_CS1_DATA_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_CS1_DATA_POLARITY (0x00800000) //!< Bit mask for IPU_DI1_POL_DI1_CS1_DATA_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_CS1_DATA_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_CS1_DATA_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_CS1_DATA_POLARITY) >> BP_IPU_DI1_POL_DI1_CS1_DATA_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_CS1_DATA_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_CS1_DATA_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_CS1_DATA_POLARITY) & BM_IPU_DI1_POL_DI1_CS1_DATA_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CS1_DATA_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_CS1_DATA_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_CS1_DATA_POLARITY) | BF_IPU_DI1_POL_DI1_CS1_DATA_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_CS0_BYTE_EN_POLARITY[24] (RW)
|
|
*
|
|
* Byte Enable associated with CS0 polarity This bit defines the polarity of the byte enable signals
|
|
* to the display
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY (24) //!< Bit position for IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY (0x01000000) //!< Bit mask for IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY) >> BP_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY) & BM_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CS0_BYTE_EN_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY) | BF_IPU_DI1_POL_DI1_CS0_BYTE_EN_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_CS1_BYTE_EN_POLARITY[25] (RW)
|
|
*
|
|
* Byte Enable associated with CS1 polarity This bit defines the polarity of the byte enable signals
|
|
* to the display
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY (25) //!< Bit position for IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY (0x02000000) //!< Bit mask for IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY) >> BP_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY) & BM_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_CS1_BYTE_EN_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY) | BF_IPU_DI1_POL_DI1_CS1_BYTE_EN_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_POL, field DI1_WAIT_POLARITY[26] (RW)
|
|
*
|
|
* WAIT polarity This bit defines the polarity of the wait signal input coming from the displa1
|
|
*
|
|
* Values:
|
|
* - 0 - active low
|
|
* - 1 - active high
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_POL_DI1_WAIT_POLARITY (26) //!< Bit position for IPU_DI1_POL_DI1_WAIT_POLARITY.
|
|
#define BM_IPU_DI1_POL_DI1_WAIT_POLARITY (0x04000000) //!< Bit mask for IPU_DI1_POL_DI1_WAIT_POLARITY.
|
|
|
|
//! @brief Get value of IPU_DI1_POL_DI1_WAIT_POLARITY from a register value.
|
|
#define BG_IPU_DI1_POL_DI1_WAIT_POLARITY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_POL_DI1_WAIT_POLARITY) >> BP_IPU_DI1_POL_DI1_WAIT_POLARITY)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_POL_DI1_WAIT_POLARITY.
|
|
#define BF_IPU_DI1_POL_DI1_WAIT_POLARITY(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_POL_DI1_WAIT_POLARITY) & BM_IPU_DI1_POL_DI1_WAIT_POLARITY)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_WAIT_POLARITY field to a new value.
|
|
#define BW_IPU_DI1_POL_DI1_WAIT_POLARITY(x, v) (HW_IPU_DI1_POL_WR(x, (HW_IPU_DI1_POL_RD(x) & ~BM_IPU_DI1_POL_DI1_WAIT_POLARITY) | BF_IPU_DI1_POL_DI1_WAIT_POLARITY(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_AW0 - DI1Active Window 0 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_AW0 - DI1Active Window 0 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_aw0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_aw0_bitfields
|
|
{
|
|
unsigned DI1_AW_HSTART : 12; //!< [11:0] This field defines the horizontal start of the active window
|
|
unsigned DI1_AW_HCOUNT_SEL : 4; //!< [15:12] This field selects the counter that counts the horizontal position of the display's active window
|
|
unsigned DI1_AW_HEND : 12; //!< [27:16] This field defines the horizontal end of the active window
|
|
unsigned DI1_AW_TRIG_SEL : 4; //!< [31:28] This field selects the trigger for sending data during the display's active window
|
|
} B;
|
|
} hw_ipu_di1_aw0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_AW0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_AW0_ADDR(x) (REGS_IPU_BASE(x) + 0x48168)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_AW0(x) (*(volatile hw_ipu_di1_aw0_t *) HW_IPU_DI1_AW0_ADDR(x))
|
|
#define HW_IPU_DI1_AW0_RD(x) (HW_IPU_DI1_AW0(x).U)
|
|
#define HW_IPU_DI1_AW0_WR(x, v) (HW_IPU_DI1_AW0(x).U = (v))
|
|
#define HW_IPU_DI1_AW0_SET(x, v) (HW_IPU_DI1_AW0_WR(x, HW_IPU_DI1_AW0_RD(x) | (v)))
|
|
#define HW_IPU_DI1_AW0_CLR(x, v) (HW_IPU_DI1_AW0_WR(x, HW_IPU_DI1_AW0_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_AW0_TOG(x, v) (HW_IPU_DI1_AW0_WR(x, HW_IPU_DI1_AW0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_AW0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_AW0, field DI1_AW_HSTART[11:0] (RW)
|
|
*
|
|
* This field defines the horizontal start of the active window DI1_AW_HSTART < DI1_AW_HEND
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW0_DI1_AW_HSTART (0) //!< Bit position for IPU_DI1_AW0_DI1_AW_HSTART.
|
|
#define BM_IPU_DI1_AW0_DI1_AW_HSTART (0x00000fff) //!< Bit mask for IPU_DI1_AW0_DI1_AW_HSTART.
|
|
|
|
//! @brief Get value of IPU_DI1_AW0_DI1_AW_HSTART from a register value.
|
|
#define BG_IPU_DI1_AW0_DI1_AW_HSTART(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW0_DI1_AW_HSTART) >> BP_IPU_DI1_AW0_DI1_AW_HSTART)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW0_DI1_AW_HSTART.
|
|
#define BF_IPU_DI1_AW0_DI1_AW_HSTART(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW0_DI1_AW_HSTART) & BM_IPU_DI1_AW0_DI1_AW_HSTART)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_HSTART field to a new value.
|
|
#define BW_IPU_DI1_AW0_DI1_AW_HSTART(x, v) (HW_IPU_DI1_AW0_WR(x, (HW_IPU_DI1_AW0_RD(x) & ~BM_IPU_DI1_AW0_DI1_AW_HSTART) | BF_IPU_DI1_AW0_DI1_AW_HSTART(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_AW0, field DI1_AW_HCOUNT_SEL[15:12] (RW)
|
|
*
|
|
* This field selects the counter that counts the horizontal position of the display's active window
|
|
*
|
|
* Values:
|
|
* - 0000 - disabled
|
|
* - 0001 - reserved
|
|
* - 0010 - The counter is counter #1
|
|
* - 0011 - The counter is counter #2
|
|
* - 0100 - The counter is counter #3
|
|
* - 0101 - The counter is counter #4
|
|
* - 0110 - The counter is counter #5
|
|
* - 1001 - The counter is counter #8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL (12) //!< Bit position for IPU_DI1_AW0_DI1_AW_HCOUNT_SEL.
|
|
#define BM_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL (0x0000f000) //!< Bit mask for IPU_DI1_AW0_DI1_AW_HCOUNT_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_AW0_DI1_AW_HCOUNT_SEL from a register value.
|
|
#define BG_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL) >> BP_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW0_DI1_AW_HCOUNT_SEL.
|
|
#define BF_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL) & BM_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_HCOUNT_SEL field to a new value.
|
|
#define BW_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL(x, v) (HW_IPU_DI1_AW0_WR(x, (HW_IPU_DI1_AW0_RD(x) & ~BM_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL) | BF_IPU_DI1_AW0_DI1_AW_HCOUNT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_AW0, field DI1_AW_HEND[27:16] (RW)
|
|
*
|
|
* This field defines the horizontal end of the active window
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW0_DI1_AW_HEND (16) //!< Bit position for IPU_DI1_AW0_DI1_AW_HEND.
|
|
#define BM_IPU_DI1_AW0_DI1_AW_HEND (0x0fff0000) //!< Bit mask for IPU_DI1_AW0_DI1_AW_HEND.
|
|
|
|
//! @brief Get value of IPU_DI1_AW0_DI1_AW_HEND from a register value.
|
|
#define BG_IPU_DI1_AW0_DI1_AW_HEND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW0_DI1_AW_HEND) >> BP_IPU_DI1_AW0_DI1_AW_HEND)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW0_DI1_AW_HEND.
|
|
#define BF_IPU_DI1_AW0_DI1_AW_HEND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW0_DI1_AW_HEND) & BM_IPU_DI1_AW0_DI1_AW_HEND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_HEND field to a new value.
|
|
#define BW_IPU_DI1_AW0_DI1_AW_HEND(x, v) (HW_IPU_DI1_AW0_WR(x, (HW_IPU_DI1_AW0_RD(x) & ~BM_IPU_DI1_AW0_DI1_AW_HEND) | BF_IPU_DI1_AW0_DI1_AW_HEND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_AW0, field DI1_AW_TRIG_SEL[31:28] (RW)
|
|
*
|
|
* This field selects the trigger for sending data during the display's active window
|
|
*
|
|
* Values:
|
|
* - 000 - disabled
|
|
* - 001 - The trigger is the same trigger that triggers the displays clock.
|
|
* - 010 - The trigger is counter #1
|
|
* - 011 - The trigger is counter #2
|
|
* - 100 - The trigger is counter #3
|
|
* - 101 - The trigger is counter #4
|
|
* - 110 - The trigger is counter #5
|
|
* - 111 - The trigger is always on.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW0_DI1_AW_TRIG_SEL (28) //!< Bit position for IPU_DI1_AW0_DI1_AW_TRIG_SEL.
|
|
#define BM_IPU_DI1_AW0_DI1_AW_TRIG_SEL (0xf0000000) //!< Bit mask for IPU_DI1_AW0_DI1_AW_TRIG_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_AW0_DI1_AW_TRIG_SEL from a register value.
|
|
#define BG_IPU_DI1_AW0_DI1_AW_TRIG_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW0_DI1_AW_TRIG_SEL) >> BP_IPU_DI1_AW0_DI1_AW_TRIG_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW0_DI1_AW_TRIG_SEL.
|
|
#define BF_IPU_DI1_AW0_DI1_AW_TRIG_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW0_DI1_AW_TRIG_SEL) & BM_IPU_DI1_AW0_DI1_AW_TRIG_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_TRIG_SEL field to a new value.
|
|
#define BW_IPU_DI1_AW0_DI1_AW_TRIG_SEL(x, v) (HW_IPU_DI1_AW0_WR(x, (HW_IPU_DI1_AW0_RD(x) & ~BM_IPU_DI1_AW0_DI1_AW_TRIG_SEL) | BF_IPU_DI1_AW0_DI1_AW_TRIG_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_AW1 - DI1 Active Window 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_AW1 - DI1 Active Window 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_aw1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_aw1_bitfields
|
|
{
|
|
unsigned DI1_AW_VSTART : 12; //!< [11:0] This field defines the vertical start of the active window
|
|
unsigned DI1_AW_VCOUNT_SEL : 4; //!< [15:12] This field selects the counter that counts the vertical position of the display's active window
|
|
unsigned DI1_AW_VEND : 12; //!< [27:16] This field defines the vertical end of the active window
|
|
unsigned RESERVED0 : 4; //!< [31:28] Reserved
|
|
} B;
|
|
} hw_ipu_di1_aw1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_AW1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_AW1_ADDR(x) (REGS_IPU_BASE(x) + 0x4816c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_AW1(x) (*(volatile hw_ipu_di1_aw1_t *) HW_IPU_DI1_AW1_ADDR(x))
|
|
#define HW_IPU_DI1_AW1_RD(x) (HW_IPU_DI1_AW1(x).U)
|
|
#define HW_IPU_DI1_AW1_WR(x, v) (HW_IPU_DI1_AW1(x).U = (v))
|
|
#define HW_IPU_DI1_AW1_SET(x, v) (HW_IPU_DI1_AW1_WR(x, HW_IPU_DI1_AW1_RD(x) | (v)))
|
|
#define HW_IPU_DI1_AW1_CLR(x, v) (HW_IPU_DI1_AW1_WR(x, HW_IPU_DI1_AW1_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_AW1_TOG(x, v) (HW_IPU_DI1_AW1_WR(x, HW_IPU_DI1_AW1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_AW1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_AW1, field DI1_AW_VSTART[11:0] (RW)
|
|
*
|
|
* This field defines the vertical start of the active window DI1_AW_VSTART < DI1_AW_VEND
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW1_DI1_AW_VSTART (0) //!< Bit position for IPU_DI1_AW1_DI1_AW_VSTART.
|
|
#define BM_IPU_DI1_AW1_DI1_AW_VSTART (0x00000fff) //!< Bit mask for IPU_DI1_AW1_DI1_AW_VSTART.
|
|
|
|
//! @brief Get value of IPU_DI1_AW1_DI1_AW_VSTART from a register value.
|
|
#define BG_IPU_DI1_AW1_DI1_AW_VSTART(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW1_DI1_AW_VSTART) >> BP_IPU_DI1_AW1_DI1_AW_VSTART)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW1_DI1_AW_VSTART.
|
|
#define BF_IPU_DI1_AW1_DI1_AW_VSTART(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW1_DI1_AW_VSTART) & BM_IPU_DI1_AW1_DI1_AW_VSTART)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_VSTART field to a new value.
|
|
#define BW_IPU_DI1_AW1_DI1_AW_VSTART(x, v) (HW_IPU_DI1_AW1_WR(x, (HW_IPU_DI1_AW1_RD(x) & ~BM_IPU_DI1_AW1_DI1_AW_VSTART) | BF_IPU_DI1_AW1_DI1_AW_VSTART(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_AW1, field DI1_AW_VCOUNT_SEL[15:12] (RW)
|
|
*
|
|
* This field selects the counter that counts the vertical position of the display's active window
|
|
*
|
|
* Values:
|
|
* - 0000 - disabled
|
|
* - 0001 - reserved
|
|
* - 0010 - The counter is counter #1
|
|
* - 0011 - The counter is counter #2
|
|
* - 0100 - The counter is counter #3
|
|
* - 0101 - The counter is counter #4
|
|
* - 0110 - The counter is counter #5
|
|
* - 1001 - The counter is counter #8
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL (12) //!< Bit position for IPU_DI1_AW1_DI1_AW_VCOUNT_SEL.
|
|
#define BM_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL (0x0000f000) //!< Bit mask for IPU_DI1_AW1_DI1_AW_VCOUNT_SEL.
|
|
|
|
//! @brief Get value of IPU_DI1_AW1_DI1_AW_VCOUNT_SEL from a register value.
|
|
#define BG_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL) >> BP_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW1_DI1_AW_VCOUNT_SEL.
|
|
#define BF_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL) & BM_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_VCOUNT_SEL field to a new value.
|
|
#define BW_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL(x, v) (HW_IPU_DI1_AW1_WR(x, (HW_IPU_DI1_AW1_RD(x) & ~BM_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL) | BF_IPU_DI1_AW1_DI1_AW_VCOUNT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_AW1, field DI1_AW_VEND[27:16] (RW)
|
|
*
|
|
* This field defines the vertical end of the active window
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_AW1_DI1_AW_VEND (16) //!< Bit position for IPU_DI1_AW1_DI1_AW_VEND.
|
|
#define BM_IPU_DI1_AW1_DI1_AW_VEND (0x0fff0000) //!< Bit mask for IPU_DI1_AW1_DI1_AW_VEND.
|
|
|
|
//! @brief Get value of IPU_DI1_AW1_DI1_AW_VEND from a register value.
|
|
#define BG_IPU_DI1_AW1_DI1_AW_VEND(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_AW1_DI1_AW_VEND) >> BP_IPU_DI1_AW1_DI1_AW_VEND)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_AW1_DI1_AW_VEND.
|
|
#define BF_IPU_DI1_AW1_DI1_AW_VEND(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_AW1_DI1_AW_VEND) & BM_IPU_DI1_AW1_DI1_AW_VEND)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_AW_VEND field to a new value.
|
|
#define BW_IPU_DI1_AW1_DI1_AW_VEND(x, v) (HW_IPU_DI1_AW1_WR(x, (HW_IPU_DI1_AW1_RD(x) & ~BM_IPU_DI1_AW1_DI1_AW_VEND) | BF_IPU_DI1_AW1_DI1_AW_VEND(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_SCR_CONF - DI1 Screen Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_SCR_CONF - DI1 Screen Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_di1_scr_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_scr_conf_bitfields
|
|
{
|
|
unsigned DI1_SCREEN_HEIGHT : 12; //!< [11:0] This field defines the number of display rows (Number_of_ROWS = DI1_SCREEN_HEIGHT+1)
|
|
unsigned RESERVED0 : 20; //!< [31:12] Reserved.
|
|
} B;
|
|
} hw_ipu_di1_scr_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_SCR_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_SCR_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x48170)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_SCR_CONF(x) (*(volatile hw_ipu_di1_scr_conf_t *) HW_IPU_DI1_SCR_CONF_ADDR(x))
|
|
#define HW_IPU_DI1_SCR_CONF_RD(x) (HW_IPU_DI1_SCR_CONF(x).U)
|
|
#define HW_IPU_DI1_SCR_CONF_WR(x, v) (HW_IPU_DI1_SCR_CONF(x).U = (v))
|
|
#define HW_IPU_DI1_SCR_CONF_SET(x, v) (HW_IPU_DI1_SCR_CONF_WR(x, HW_IPU_DI1_SCR_CONF_RD(x) | (v)))
|
|
#define HW_IPU_DI1_SCR_CONF_CLR(x, v) (HW_IPU_DI1_SCR_CONF_WR(x, HW_IPU_DI1_SCR_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_DI1_SCR_CONF_TOG(x, v) (HW_IPU_DI1_SCR_CONF_WR(x, HW_IPU_DI1_SCR_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_SCR_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_SCR_CONF, field DI1_SCREEN_HEIGHT[11:0] (RW)
|
|
*
|
|
* This field defines the number of display rows (Number_of_ROWS = DI1_SCREEN_HEIGHT+1) This field
|
|
* is used for VSYNC calculation and for anti-tearing
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT (0) //!< Bit position for IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT.
|
|
#define BM_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT (0x00000fff) //!< Bit mask for IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT.
|
|
|
|
//! @brief Get value of IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT from a register value.
|
|
#define BG_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT) >> BP_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT.
|
|
#define BF_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT) & BM_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI1_SCREEN_HEIGHT field to a new value.
|
|
#define BW_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT(x, v) (HW_IPU_DI1_SCR_CONF_WR(x, (HW_IPU_DI1_SCR_CONF_RD(x) & ~BM_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT) | BF_IPU_DI1_SCR_CONF_DI1_SCREEN_HEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DI1_STAT - DI1 Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DI1_STAT - DI1 Status Register (RO)
|
|
*
|
|
* Reset value: 0x00000005
|
|
*/
|
|
typedef union _hw_ipu_di1_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_di1_stat_bitfields
|
|
{
|
|
unsigned DI1_READ_FIFO_EMPTY : 1; //!< [0] This bit indicates an empty state of the DI1 FIFO when performing a read.
|
|
unsigned DI1_READ_FIFO_FULL : 1; //!< [1] This bit indicates a full state of the DI1 FIFO when performing a read.
|
|
unsigned DI1_CNTR_FIFO_EMPTY : 1; //!< [2] This bit indicates an empty state of the DI1 FIFO.
|
|
unsigned DI1_CNTR_FIFO_FULL : 1; //!< [3] This bit indicates a full state of the DI1 FIFO.
|
|
unsigned RESERVED0 : 28; //!< [31:4] Reserved
|
|
} B;
|
|
} hw_ipu_di1_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DI1_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DI1_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x48174)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DI1_STAT(x) (*(volatile hw_ipu_di1_stat_t *) HW_IPU_DI1_STAT_ADDR(x))
|
|
#define HW_IPU_DI1_STAT_RD(x) (HW_IPU_DI1_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DI1_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DI1_STAT, field DI1_READ_FIFO_EMPTY[0] (RO)
|
|
*
|
|
* This bit indicates an empty state of the DI1 FIFO when performing a read. This FIFO is part of
|
|
* the DI1 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_STAT_DI1_READ_FIFO_EMPTY (0) //!< Bit position for IPU_DI1_STAT_DI1_READ_FIFO_EMPTY.
|
|
#define BM_IPU_DI1_STAT_DI1_READ_FIFO_EMPTY (0x00000001) //!< Bit mask for IPU_DI1_STAT_DI1_READ_FIFO_EMPTY.
|
|
|
|
//! @brief Get value of IPU_DI1_STAT_DI1_READ_FIFO_EMPTY from a register value.
|
|
#define BG_IPU_DI1_STAT_DI1_READ_FIFO_EMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_STAT_DI1_READ_FIFO_EMPTY) >> BP_IPU_DI1_STAT_DI1_READ_FIFO_EMPTY)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_STAT, field DI1_READ_FIFO_FULL[1] (RO)
|
|
*
|
|
* This bit indicates a full state of the DI1 FIFO when performing a read. This FIFO is part of the
|
|
* DI1 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_STAT_DI1_READ_FIFO_FULL (1) //!< Bit position for IPU_DI1_STAT_DI1_READ_FIFO_FULL.
|
|
#define BM_IPU_DI1_STAT_DI1_READ_FIFO_FULL (0x00000002) //!< Bit mask for IPU_DI1_STAT_DI1_READ_FIFO_FULL.
|
|
|
|
//! @brief Get value of IPU_DI1_STAT_DI1_READ_FIFO_FULL from a register value.
|
|
#define BG_IPU_DI1_STAT_DI1_READ_FIFO_FULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_STAT_DI1_READ_FIFO_FULL) >> BP_IPU_DI1_STAT_DI1_READ_FIFO_FULL)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_STAT, field DI1_CNTR_FIFO_EMPTY[2] (RO)
|
|
*
|
|
* This bit indicates an empty state of the DI1 FIFO. This FIFO is part of the DI1 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY (2) //!< Bit position for IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY.
|
|
#define BM_IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY (0x00000004) //!< Bit mask for IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY.
|
|
|
|
//! @brief Get value of IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY from a register value.
|
|
#define BG_IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY) >> BP_IPU_DI1_STAT_DI1_CNTR_FIFO_EMPTY)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DI1_STAT, field DI1_CNTR_FIFO_FULL[3] (RO)
|
|
*
|
|
* This bit indicates a full state of the DI1 FIFO. This FIFO is part of the DI1 synchronizer.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DI1_STAT_DI1_CNTR_FIFO_FULL (3) //!< Bit position for IPU_DI1_STAT_DI1_CNTR_FIFO_FULL.
|
|
#define BM_IPU_DI1_STAT_DI1_CNTR_FIFO_FULL (0x00000008) //!< Bit mask for IPU_DI1_STAT_DI1_CNTR_FIFO_FULL.
|
|
|
|
//! @brief Get value of IPU_DI1_STAT_DI1_CNTR_FIFO_FULL from a register value.
|
|
#define BG_IPU_DI1_STAT_DI1_CNTR_FIFO_FULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DI1_STAT_DI1_CNTR_FIFO_FULL) >> BP_IPU_DI1_STAT_DI1_CNTR_FIFO_FULL)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SMFC_MAP - SMFC Mapping Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SMFC_MAP - SMFC Mapping Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The purpose of this register is to map CSI frames to IDMAC channels.
|
|
*/
|
|
typedef union _hw_ipu_smfc_map
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_smfc_map_bitfields
|
|
{
|
|
unsigned MAP_CH0 : 3; //!< [2:0] DMASMFC channel 0 mapping bits.
|
|
unsigned MAP_CH1 : 3; //!< [5:3] DMASMFC channel 1 mapping bits.
|
|
unsigned MAP_CH2 : 3; //!< [8:6] DMASMFC channel 2 mapping bits.
|
|
unsigned MAP_CH3 : 3; //!< [11:9] DMASMFC channel 3mapping bits.
|
|
unsigned RESERVED0 : 20; //!< [31:12] Reserved.
|
|
} B;
|
|
} hw_ipu_smfc_map_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SMFC_MAP register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SMFC_MAP_ADDR(x) (REGS_IPU_BASE(x) + 0x50000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SMFC_MAP(x) (*(volatile hw_ipu_smfc_map_t *) HW_IPU_SMFC_MAP_ADDR(x))
|
|
#define HW_IPU_SMFC_MAP_RD(x) (HW_IPU_SMFC_MAP(x).U)
|
|
#define HW_IPU_SMFC_MAP_WR(x, v) (HW_IPU_SMFC_MAP(x).U = (v))
|
|
#define HW_IPU_SMFC_MAP_SET(x, v) (HW_IPU_SMFC_MAP_WR(x, HW_IPU_SMFC_MAP_RD(x) | (v)))
|
|
#define HW_IPU_SMFC_MAP_CLR(x, v) (HW_IPU_SMFC_MAP_WR(x, HW_IPU_SMFC_MAP_RD(x) & ~(v)))
|
|
#define HW_IPU_SMFC_MAP_TOG(x, v) (HW_IPU_SMFC_MAP_WR(x, HW_IPU_SMFC_MAP_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SMFC_MAP bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SMFC_MAP, field MAP_CH0[2:0] (RW)
|
|
*
|
|
* DMASMFC channel 0 mapping bits.
|
|
*
|
|
* Values:
|
|
* - 000 - CSI0, ID=0 mapped to DMASMFC channel 0.
|
|
* - 001 - CSI0, ID=1 mapped to DMASMFC channel 0.
|
|
* - 010 - CSI0, ID=2 mapped to DMASMFC channel 0.
|
|
* - 011 - CSI0, ID=3 mapped to DMASMFC channel 0.
|
|
* - 100 - CSI1, ID=0 mapped to DMASMFC channel 0.
|
|
* - 101 - CSI1, ID=1 mapped to DMASMFC channel 0.
|
|
* - 110 - CSI1, ID=2 mapped to DMASMFC channel 0.
|
|
* - 111 - CSI1, ID=3 mapped to DMASMFC channel 0.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_MAP_MAP_CH0 (0) //!< Bit position for IPU_SMFC_MAP_MAP_CH0.
|
|
#define BM_IPU_SMFC_MAP_MAP_CH0 (0x00000007) //!< Bit mask for IPU_SMFC_MAP_MAP_CH0.
|
|
|
|
//! @brief Get value of IPU_SMFC_MAP_MAP_CH0 from a register value.
|
|
#define BG_IPU_SMFC_MAP_MAP_CH0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_MAP_MAP_CH0) >> BP_IPU_SMFC_MAP_MAP_CH0)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_MAP_MAP_CH0.
|
|
#define BF_IPU_SMFC_MAP_MAP_CH0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_MAP_MAP_CH0) & BM_IPU_SMFC_MAP_MAP_CH0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAP_CH0 field to a new value.
|
|
#define BW_IPU_SMFC_MAP_MAP_CH0(x, v) (HW_IPU_SMFC_MAP_WR(x, (HW_IPU_SMFC_MAP_RD(x) & ~BM_IPU_SMFC_MAP_MAP_CH0) | BF_IPU_SMFC_MAP_MAP_CH0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_MAP, field MAP_CH1[5:3] (RW)
|
|
*
|
|
* DMASMFC channel 1 mapping bits.
|
|
*
|
|
* Values:
|
|
* - 000 - CSI0, ID=0 mapped to DMASMFC channel 1.
|
|
* - 001 - CSI0, ID=1 mapped to DMASMFC channel 1.
|
|
* - 010 - CSI0, ID=2 mapped to DMASMFC channel 1.
|
|
* - 011 - CSI0, ID=3 mapped to DMASMFC channel 1.
|
|
* - 100 - CSI1, ID=0 mapped to DMASMFC channel 1.
|
|
* - 101 - CSI1, ID=1 mapped to DMASMFC channel 1.
|
|
* - 110 - CSI1, ID=2 mapped to DMASMFC channel 1.
|
|
* - 111 - CSI1, ID=3 mapped to DMASMFC channel 1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_MAP_MAP_CH1 (3) //!< Bit position for IPU_SMFC_MAP_MAP_CH1.
|
|
#define BM_IPU_SMFC_MAP_MAP_CH1 (0x00000038) //!< Bit mask for IPU_SMFC_MAP_MAP_CH1.
|
|
|
|
//! @brief Get value of IPU_SMFC_MAP_MAP_CH1 from a register value.
|
|
#define BG_IPU_SMFC_MAP_MAP_CH1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_MAP_MAP_CH1) >> BP_IPU_SMFC_MAP_MAP_CH1)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_MAP_MAP_CH1.
|
|
#define BF_IPU_SMFC_MAP_MAP_CH1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_MAP_MAP_CH1) & BM_IPU_SMFC_MAP_MAP_CH1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAP_CH1 field to a new value.
|
|
#define BW_IPU_SMFC_MAP_MAP_CH1(x, v) (HW_IPU_SMFC_MAP_WR(x, (HW_IPU_SMFC_MAP_RD(x) & ~BM_IPU_SMFC_MAP_MAP_CH1) | BF_IPU_SMFC_MAP_MAP_CH1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_MAP, field MAP_CH2[8:6] (RW)
|
|
*
|
|
* DMASMFC channel 2 mapping bits.
|
|
*
|
|
* Values:
|
|
* - 000 - CSI0, ID=0 mapped to DMASMFC channel 2.
|
|
* - 001 - CSI0, ID=1 mapped to DMASMFC channel 2.
|
|
* - 010 - CSI0, ID=2 mapped to DMASMFC channel 2.
|
|
* - 011 - CSI0, ID=3 mapped to DMASMFC channel 2.
|
|
* - 100 - CSI1, ID=0 mapped to DMASMFC channel 2.
|
|
* - 101 - CSI1, ID=1 mapped to DMASMFC channel 2.
|
|
* - 110 - CSI1, ID=2 mapped to DMASMFC channel 2.
|
|
* - 111 - CSI1, ID=3 mapped to DMASMFC channel 2.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_MAP_MAP_CH2 (6) //!< Bit position for IPU_SMFC_MAP_MAP_CH2.
|
|
#define BM_IPU_SMFC_MAP_MAP_CH2 (0x000001c0) //!< Bit mask for IPU_SMFC_MAP_MAP_CH2.
|
|
|
|
//! @brief Get value of IPU_SMFC_MAP_MAP_CH2 from a register value.
|
|
#define BG_IPU_SMFC_MAP_MAP_CH2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_MAP_MAP_CH2) >> BP_IPU_SMFC_MAP_MAP_CH2)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_MAP_MAP_CH2.
|
|
#define BF_IPU_SMFC_MAP_MAP_CH2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_MAP_MAP_CH2) & BM_IPU_SMFC_MAP_MAP_CH2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAP_CH2 field to a new value.
|
|
#define BW_IPU_SMFC_MAP_MAP_CH2(x, v) (HW_IPU_SMFC_MAP_WR(x, (HW_IPU_SMFC_MAP_RD(x) & ~BM_IPU_SMFC_MAP_MAP_CH2) | BF_IPU_SMFC_MAP_MAP_CH2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_MAP, field MAP_CH3[11:9] (RW)
|
|
*
|
|
* DMASMFC channel 3mapping bits.
|
|
*
|
|
* Values:
|
|
* - 000 - CSI0, ID=0 mapped to DMASMFC channel 3.
|
|
* - 001 - CSI0, ID=1 mapped to DMASMFC channel 3.
|
|
* - 010 - CSI0, ID=2 mapped to DMASMFC channel 3.
|
|
* - 011 - CSI0, ID=3 mapped to DMASMFC channel 3.
|
|
* - 100 - CSI1, ID=0 mapped to DMASMFC channel 3.
|
|
* - 101 - CSI1, ID=1 mapped to DMASMFC channel 3.
|
|
* - 110 - CSI1, ID=2 mapped to DMASMFC channel 3.
|
|
* - 111 - CSI1, ID=3 mapped to DMASMFC channel 3.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_MAP_MAP_CH3 (9) //!< Bit position for IPU_SMFC_MAP_MAP_CH3.
|
|
#define BM_IPU_SMFC_MAP_MAP_CH3 (0x00000e00) //!< Bit mask for IPU_SMFC_MAP_MAP_CH3.
|
|
|
|
//! @brief Get value of IPU_SMFC_MAP_MAP_CH3 from a register value.
|
|
#define BG_IPU_SMFC_MAP_MAP_CH3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_MAP_MAP_CH3) >> BP_IPU_SMFC_MAP_MAP_CH3)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_MAP_MAP_CH3.
|
|
#define BF_IPU_SMFC_MAP_MAP_CH3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_MAP_MAP_CH3) & BM_IPU_SMFC_MAP_MAP_CH3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAP_CH3 field to a new value.
|
|
#define BW_IPU_SMFC_MAP_MAP_CH3(x, v) (HW_IPU_SMFC_MAP_WR(x, (HW_IPU_SMFC_MAP_RD(x) & ~BM_IPU_SMFC_MAP_MAP_CH3) | BF_IPU_SMFC_MAP_MAP_CH3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SMFC_WMC - SMFC Watermark Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SMFC_WMC - SMFC Watermark Control Register (RW)
|
|
*
|
|
* Reset value: 0x000009a6
|
|
*
|
|
* The purpose of this register is to control watermarks levels of DMA channels. The bit setting
|
|
* given relative to FIFO size and not in number of words since FIFO size depend from number of
|
|
* enabled DMA channels.
|
|
*/
|
|
typedef union _hw_ipu_smfc_wmc
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_smfc_wmc_bitfields
|
|
{
|
|
unsigned WM0_SET : 3; //!< [2:0] Watermark "set" level of DMASMFC channel 0.
|
|
unsigned WM0_CLR : 3; //!< [5:3] Watermark "clear" level of DMASMFC channel 0.
|
|
unsigned WM1_SET : 3; //!< [8:6] Watermark "set" level of DMASMFC channel 1.
|
|
unsigned WM1_CLR : 3; //!< [11:9] Watermark "clear" level of DMASMFC channel 1.
|
|
unsigned RESERVED0 : 4; //!< [15:12] Reserved.
|
|
unsigned WM2_SET : 3; //!< [18:16] Watermark "set" level of DMASMFC channel 2.
|
|
unsigned WM2_CLR : 3; //!< [21:19] Watermark "clear" level of DMASMFC channel 2.
|
|
unsigned WM3_SET : 3; //!< [24:22] Watermark "set" level of DMASMFC channel 3
|
|
unsigned WM3_CLR : 3; //!< [27:25] Watermark "clear" level of DMASMFC channel 3.
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved.
|
|
} B;
|
|
} hw_ipu_smfc_wmc_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SMFC_WMC register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SMFC_WMC_ADDR(x) (REGS_IPU_BASE(x) + 0x50004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SMFC_WMC(x) (*(volatile hw_ipu_smfc_wmc_t *) HW_IPU_SMFC_WMC_ADDR(x))
|
|
#define HW_IPU_SMFC_WMC_RD(x) (HW_IPU_SMFC_WMC(x).U)
|
|
#define HW_IPU_SMFC_WMC_WR(x, v) (HW_IPU_SMFC_WMC(x).U = (v))
|
|
#define HW_IPU_SMFC_WMC_SET(x, v) (HW_IPU_SMFC_WMC_WR(x, HW_IPU_SMFC_WMC_RD(x) | (v)))
|
|
#define HW_IPU_SMFC_WMC_CLR(x, v) (HW_IPU_SMFC_WMC_WR(x, HW_IPU_SMFC_WMC_RD(x) & ~(v)))
|
|
#define HW_IPU_SMFC_WMC_TOG(x, v) (HW_IPU_SMFC_WMC_WR(x, HW_IPU_SMFC_WMC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SMFC_WMC bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM0_SET[2:0] (RW)
|
|
*
|
|
* Watermark "set" level of DMASMFC channel 0.
|
|
*
|
|
* Values:
|
|
* - 000 - set watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - set watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - set watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - set watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM0_SET (0) //!< Bit position for IPU_SMFC_WMC_WM0_SET.
|
|
#define BM_IPU_SMFC_WMC_WM0_SET (0x00000007) //!< Bit mask for IPU_SMFC_WMC_WM0_SET.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM0_SET from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM0_SET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM0_SET) >> BP_IPU_SMFC_WMC_WM0_SET)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM0_SET.
|
|
#define BF_IPU_SMFC_WMC_WM0_SET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM0_SET) & BM_IPU_SMFC_WMC_WM0_SET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM0_SET field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM0_SET(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM0_SET) | BF_IPU_SMFC_WMC_WM0_SET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM0_CLR[5:3] (RW)
|
|
*
|
|
* Watermark "clear" level of DMASMFC channel 0.
|
|
*
|
|
* Values:
|
|
* - 000 - clear watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - clear watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - clear watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - clear watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM0_CLR (3) //!< Bit position for IPU_SMFC_WMC_WM0_CLR.
|
|
#define BM_IPU_SMFC_WMC_WM0_CLR (0x00000038) //!< Bit mask for IPU_SMFC_WMC_WM0_CLR.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM0_CLR from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM0_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM0_CLR) >> BP_IPU_SMFC_WMC_WM0_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM0_CLR.
|
|
#define BF_IPU_SMFC_WMC_WM0_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM0_CLR) & BM_IPU_SMFC_WMC_WM0_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM0_CLR field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM0_CLR(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM0_CLR) | BF_IPU_SMFC_WMC_WM0_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM1_SET[8:6] (RW)
|
|
*
|
|
* Watermark "set" level of DMASMFC channel 1.
|
|
*
|
|
* Values:
|
|
* - 000 - set watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - set watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - set watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - set watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM1_SET (6) //!< Bit position for IPU_SMFC_WMC_WM1_SET.
|
|
#define BM_IPU_SMFC_WMC_WM1_SET (0x000001c0) //!< Bit mask for IPU_SMFC_WMC_WM1_SET.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM1_SET from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM1_SET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM1_SET) >> BP_IPU_SMFC_WMC_WM1_SET)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM1_SET.
|
|
#define BF_IPU_SMFC_WMC_WM1_SET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM1_SET) & BM_IPU_SMFC_WMC_WM1_SET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM1_SET field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM1_SET(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM1_SET) | BF_IPU_SMFC_WMC_WM1_SET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM1_CLR[11:9] (RW)
|
|
*
|
|
* Watermark "clear" level of DMASMFC channel 1.
|
|
*
|
|
* Values:
|
|
* - 000 - clear watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - clear watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - clear watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - clear watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM1_CLR (9) //!< Bit position for IPU_SMFC_WMC_WM1_CLR.
|
|
#define BM_IPU_SMFC_WMC_WM1_CLR (0x00000e00) //!< Bit mask for IPU_SMFC_WMC_WM1_CLR.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM1_CLR from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM1_CLR) >> BP_IPU_SMFC_WMC_WM1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM1_CLR.
|
|
#define BF_IPU_SMFC_WMC_WM1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM1_CLR) & BM_IPU_SMFC_WMC_WM1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM1_CLR field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM1_CLR(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM1_CLR) | BF_IPU_SMFC_WMC_WM1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM2_SET[18:16] (RW)
|
|
*
|
|
* Watermark "set" level of DMASMFC channel 2.
|
|
*
|
|
* Values:
|
|
* - 000 - set watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - set watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - set watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - set watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM2_SET (16) //!< Bit position for IPU_SMFC_WMC_WM2_SET.
|
|
#define BM_IPU_SMFC_WMC_WM2_SET (0x00070000) //!< Bit mask for IPU_SMFC_WMC_WM2_SET.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM2_SET from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM2_SET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM2_SET) >> BP_IPU_SMFC_WMC_WM2_SET)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM2_SET.
|
|
#define BF_IPU_SMFC_WMC_WM2_SET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM2_SET) & BM_IPU_SMFC_WMC_WM2_SET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM2_SET field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM2_SET(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM2_SET) | BF_IPU_SMFC_WMC_WM2_SET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM2_CLR[21:19] (RW)
|
|
*
|
|
* Watermark "clear" level of DMASMFC channel 2.
|
|
*
|
|
* Values:
|
|
* - 000 - clear watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - clear watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - clear watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - clear watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM2_CLR (19) //!< Bit position for IPU_SMFC_WMC_WM2_CLR.
|
|
#define BM_IPU_SMFC_WMC_WM2_CLR (0x00380000) //!< Bit mask for IPU_SMFC_WMC_WM2_CLR.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM2_CLR from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM2_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM2_CLR) >> BP_IPU_SMFC_WMC_WM2_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM2_CLR.
|
|
#define BF_IPU_SMFC_WMC_WM2_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM2_CLR) & BM_IPU_SMFC_WMC_WM2_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM2_CLR field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM2_CLR(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM2_CLR) | BF_IPU_SMFC_WMC_WM2_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM3_SET[24:22] (RW)
|
|
*
|
|
* Watermark "set" level of DMASMFC channel 3
|
|
*
|
|
* Values:
|
|
* - 000 - set watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - set watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - set watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - set watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM3_SET (22) //!< Bit position for IPU_SMFC_WMC_WM3_SET.
|
|
#define BM_IPU_SMFC_WMC_WM3_SET (0x01c00000) //!< Bit mask for IPU_SMFC_WMC_WM3_SET.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM3_SET from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM3_SET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM3_SET) >> BP_IPU_SMFC_WMC_WM3_SET)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM3_SET.
|
|
#define BF_IPU_SMFC_WMC_WM3_SET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM3_SET) & BM_IPU_SMFC_WMC_WM3_SET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM3_SET field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM3_SET(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM3_SET) | BF_IPU_SMFC_WMC_WM3_SET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_WMC, field WM3_CLR[27:25] (RW)
|
|
*
|
|
* Watermark "clear" level of DMASMFC channel 3.
|
|
*
|
|
* Values:
|
|
* - 000 - clear watermark level when FIFO is full on 1/8 of their size.
|
|
* - 001 - clear watermark level when FIFO is full on 2/8 of their size.
|
|
* - 110 - clear watermark level when FIFO is full on 7/8 of their size.
|
|
* - 111 - clear watermark level when FIFO is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_WMC_WM3_CLR (25) //!< Bit position for IPU_SMFC_WMC_WM3_CLR.
|
|
#define BM_IPU_SMFC_WMC_WM3_CLR (0x0e000000) //!< Bit mask for IPU_SMFC_WMC_WM3_CLR.
|
|
|
|
//! @brief Get value of IPU_SMFC_WMC_WM3_CLR from a register value.
|
|
#define BG_IPU_SMFC_WMC_WM3_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_WMC_WM3_CLR) >> BP_IPU_SMFC_WMC_WM3_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_WMC_WM3_CLR.
|
|
#define BF_IPU_SMFC_WMC_WM3_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_WMC_WM3_CLR) & BM_IPU_SMFC_WMC_WM3_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WM3_CLR field to a new value.
|
|
#define BW_IPU_SMFC_WMC_WM3_CLR(x, v) (HW_IPU_SMFC_WMC_WR(x, (HW_IPU_SMFC_WMC_RD(x) & ~BM_IPU_SMFC_WMC_WM3_CLR) | BF_IPU_SMFC_WMC_WM3_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_SMFC_BS - SMFC Burst Size Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_SMFC_BS - SMFC Burst Size Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* This register holds the burst size value for each DMASMFC channel. The burst size is the number
|
|
* of IDMAC's active accesses that will done for each IDMAC's burst. This number is a function of
|
|
* PFS, BPP & NPB parameters in the IDMAC's CPMEM. These are the parameters corresponding to the
|
|
* IDMAC's channel used. The table below describes what should be the burst size according to PFS,
|
|
* BPP & NPB settings SMFC Burst Size BPP PFS BURST_SIZE 8 6 NPB[6:4] 16 6 NPB[6:4] All other All
|
|
* other NPB[6:2]
|
|
*/
|
|
typedef union _hw_ipu_smfc_bs
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_smfc_bs_bitfields
|
|
{
|
|
unsigned BURST0_SIZE : 4; //!< [3:0] Burst Size of SMFCDMA channel 0.
|
|
unsigned BURST1_SIZE : 4; //!< [7:4] Burst Size of SMFCDMA channel 1.
|
|
unsigned BURST2_SIZE : 4; //!< [11:8] Burst Size of SMFCDMA channel 2.
|
|
unsigned BURST3_SIZE : 4; //!< [15:12] Burst Size of SMFCDMA channel 3.
|
|
unsigned RESERVED0 : 16; //!< [31:16] Reserved.
|
|
} B;
|
|
} hw_ipu_smfc_bs_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_SMFC_BS register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_SMFC_BS_ADDR(x) (REGS_IPU_BASE(x) + 0x50008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_SMFC_BS(x) (*(volatile hw_ipu_smfc_bs_t *) HW_IPU_SMFC_BS_ADDR(x))
|
|
#define HW_IPU_SMFC_BS_RD(x) (HW_IPU_SMFC_BS(x).U)
|
|
#define HW_IPU_SMFC_BS_WR(x, v) (HW_IPU_SMFC_BS(x).U = (v))
|
|
#define HW_IPU_SMFC_BS_SET(x, v) (HW_IPU_SMFC_BS_WR(x, HW_IPU_SMFC_BS_RD(x) | (v)))
|
|
#define HW_IPU_SMFC_BS_CLR(x, v) (HW_IPU_SMFC_BS_WR(x, HW_IPU_SMFC_BS_RD(x) & ~(v)))
|
|
#define HW_IPU_SMFC_BS_TOG(x, v) (HW_IPU_SMFC_BS_WR(x, HW_IPU_SMFC_BS_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_SMFC_BS bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_SMFC_BS, field BURST0_SIZE[3:0] (RW)
|
|
*
|
|
* Burst Size of SMFCDMA channel 0. The value programed here should be BURST_SIZE-1 (for example:
|
|
* for a burst size of 1, write 0 to these bits)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_BS_BURST0_SIZE (0) //!< Bit position for IPU_SMFC_BS_BURST0_SIZE.
|
|
#define BM_IPU_SMFC_BS_BURST0_SIZE (0x0000000f) //!< Bit mask for IPU_SMFC_BS_BURST0_SIZE.
|
|
|
|
//! @brief Get value of IPU_SMFC_BS_BURST0_SIZE from a register value.
|
|
#define BG_IPU_SMFC_BS_BURST0_SIZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_BS_BURST0_SIZE) >> BP_IPU_SMFC_BS_BURST0_SIZE)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_BS_BURST0_SIZE.
|
|
#define BF_IPU_SMFC_BS_BURST0_SIZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_BS_BURST0_SIZE) & BM_IPU_SMFC_BS_BURST0_SIZE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BURST0_SIZE field to a new value.
|
|
#define BW_IPU_SMFC_BS_BURST0_SIZE(x, v) (HW_IPU_SMFC_BS_WR(x, (HW_IPU_SMFC_BS_RD(x) & ~BM_IPU_SMFC_BS_BURST0_SIZE) | BF_IPU_SMFC_BS_BURST0_SIZE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_BS, field BURST1_SIZE[7:4] (RW)
|
|
*
|
|
* Burst Size of SMFCDMA channel 1. The value programed here should be BURST_SIZE-1 (for example:
|
|
* for a burst size of 1, write 0 to these bits)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_BS_BURST1_SIZE (4) //!< Bit position for IPU_SMFC_BS_BURST1_SIZE.
|
|
#define BM_IPU_SMFC_BS_BURST1_SIZE (0x000000f0) //!< Bit mask for IPU_SMFC_BS_BURST1_SIZE.
|
|
|
|
//! @brief Get value of IPU_SMFC_BS_BURST1_SIZE from a register value.
|
|
#define BG_IPU_SMFC_BS_BURST1_SIZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_BS_BURST1_SIZE) >> BP_IPU_SMFC_BS_BURST1_SIZE)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_BS_BURST1_SIZE.
|
|
#define BF_IPU_SMFC_BS_BURST1_SIZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_BS_BURST1_SIZE) & BM_IPU_SMFC_BS_BURST1_SIZE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BURST1_SIZE field to a new value.
|
|
#define BW_IPU_SMFC_BS_BURST1_SIZE(x, v) (HW_IPU_SMFC_BS_WR(x, (HW_IPU_SMFC_BS_RD(x) & ~BM_IPU_SMFC_BS_BURST1_SIZE) | BF_IPU_SMFC_BS_BURST1_SIZE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_BS, field BURST2_SIZE[11:8] (RW)
|
|
*
|
|
* Burst Size of SMFCDMA channel 2. The value programed here should be BURST_SIZE-1 (for example:
|
|
* for a burst size of 1, write 0 to these bits)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_BS_BURST2_SIZE (8) //!< Bit position for IPU_SMFC_BS_BURST2_SIZE.
|
|
#define BM_IPU_SMFC_BS_BURST2_SIZE (0x00000f00) //!< Bit mask for IPU_SMFC_BS_BURST2_SIZE.
|
|
|
|
//! @brief Get value of IPU_SMFC_BS_BURST2_SIZE from a register value.
|
|
#define BG_IPU_SMFC_BS_BURST2_SIZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_BS_BURST2_SIZE) >> BP_IPU_SMFC_BS_BURST2_SIZE)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_BS_BURST2_SIZE.
|
|
#define BF_IPU_SMFC_BS_BURST2_SIZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_BS_BURST2_SIZE) & BM_IPU_SMFC_BS_BURST2_SIZE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BURST2_SIZE field to a new value.
|
|
#define BW_IPU_SMFC_BS_BURST2_SIZE(x, v) (HW_IPU_SMFC_BS_WR(x, (HW_IPU_SMFC_BS_RD(x) & ~BM_IPU_SMFC_BS_BURST2_SIZE) | BF_IPU_SMFC_BS_BURST2_SIZE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_SMFC_BS, field BURST3_SIZE[15:12] (RW)
|
|
*
|
|
* Burst Size of SMFCDMA channel 3. The value programed here should be BURST_SIZE-1 (for example:
|
|
* for a burst size of 1, write 0 to these bits)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_SMFC_BS_BURST3_SIZE (12) //!< Bit position for IPU_SMFC_BS_BURST3_SIZE.
|
|
#define BM_IPU_SMFC_BS_BURST3_SIZE (0x0000f000) //!< Bit mask for IPU_SMFC_BS_BURST3_SIZE.
|
|
|
|
//! @brief Get value of IPU_SMFC_BS_BURST3_SIZE from a register value.
|
|
#define BG_IPU_SMFC_BS_BURST3_SIZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_SMFC_BS_BURST3_SIZE) >> BP_IPU_SMFC_BS_BURST3_SIZE)
|
|
|
|
//! @brief Format value for bitfield IPU_SMFC_BS_BURST3_SIZE.
|
|
#define BF_IPU_SMFC_BS_BURST3_SIZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_SMFC_BS_BURST3_SIZE) & BM_IPU_SMFC_BS_BURST3_SIZE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the BURST3_SIZE field to a new value.
|
|
#define BW_IPU_SMFC_BS_BURST3_SIZE(x, v) (HW_IPU_SMFC_BS_WR(x, (HW_IPU_SMFC_BS_RD(x) & ~BM_IPU_SMFC_BS_BURST3_SIZE) | BF_IPU_SMFC_BS_BURST3_SIZE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_READ_CH_CONF - DC Read Channel Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_READ_CH_CONF - DC Read Channel Configuration Register (RW)
|
|
*
|
|
* Reset value: 0xffff0000
|
|
*/
|
|
typedef union _hw_ipu_dc_read_ch_conf
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_read_ch_conf_bitfields
|
|
{
|
|
unsigned RD_CHANNEL_EN : 1; //!< [0] This bit enables the read channel.
|
|
unsigned PROG_DI_ID_0 : 1; //!< [1] This bit select the DI which a read transaction can be performed through
|
|
unsigned PROG_DISP_ID_0 : 2; //!< [3:2] The field defines which one of the 4 displays can be read.
|
|
unsigned W_SIZE_0 : 2; //!< [5:4] Word Size
|
|
unsigned CHAN_MASK_DEFAULT_0 : 1; //!< [6] Event mask bit for the read channel
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved
|
|
unsigned CS_ID_0 : 1; //!< [8] This bit maps an asynchronous display to a chip select
|
|
unsigned CS_ID_1 : 1; //!< [9] This bit maps an asynchronous display to a chip select
|
|
unsigned CS_ID_2 : 1; //!< [10] This bit maps an asynchronous display to a chip select
|
|
unsigned CS_ID_3 : 1; //!< [11] This bit maps an asynchronous display to a chip select
|
|
unsigned RESERVED1 : 4; //!< [15:12] Reserved
|
|
unsigned TIME_OUT_VALUE : 16; //!< [31:16] Time out value.
|
|
} B;
|
|
} hw_ipu_dc_read_ch_conf_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_READ_CH_CONF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_READ_CH_CONF_ADDR(x) (REGS_IPU_BASE(x) + 0x58000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_READ_CH_CONF(x) (*(volatile hw_ipu_dc_read_ch_conf_t *) HW_IPU_DC_READ_CH_CONF_ADDR(x))
|
|
#define HW_IPU_DC_READ_CH_CONF_RD(x) (HW_IPU_DC_READ_CH_CONF(x).U)
|
|
#define HW_IPU_DC_READ_CH_CONF_WR(x, v) (HW_IPU_DC_READ_CH_CONF(x).U = (v))
|
|
#define HW_IPU_DC_READ_CH_CONF_SET(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, HW_IPU_DC_READ_CH_CONF_RD(x) | (v)))
|
|
#define HW_IPU_DC_READ_CH_CONF_CLR(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, HW_IPU_DC_READ_CH_CONF_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_READ_CH_CONF_TOG(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, HW_IPU_DC_READ_CH_CONF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_READ_CH_CONF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field RD_CHANNEL_EN[0] (RW)
|
|
*
|
|
* This bit enables the read channel.
|
|
*
|
|
* Values:
|
|
* - 0 - The Read channel is disabled
|
|
* - 1 - The Read channel is enabled
|
|
*/
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|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN (0) //!< Bit position for IPU_DC_READ_CH_CONF_RD_CHANNEL_EN.
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#define BM_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN (0x00000001) //!< Bit mask for IPU_DC_READ_CH_CONF_RD_CHANNEL_EN.
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//! @brief Get value of IPU_DC_READ_CH_CONF_RD_CHANNEL_EN from a register value.
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|
#define BG_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN) >> BP_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN)
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//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_RD_CHANNEL_EN.
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|
#define BF_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN) & BM_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the RD_CHANNEL_EN field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN) | BF_IPU_DC_READ_CH_CONF_RD_CHANNEL_EN(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_DC_READ_CH_CONF, field PROG_DI_ID_0[1] (RW)
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*
|
|
* This bit select the DI which a read transaction can be performed through
|
|
*
|
|
* Values:
|
|
* - 0 - DI #0
|
|
* - 1 - DI #1
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|
*/
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|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_PROG_DI_ID_0 (1) //!< Bit position for IPU_DC_READ_CH_CONF_PROG_DI_ID_0.
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#define BM_IPU_DC_READ_CH_CONF_PROG_DI_ID_0 (0x00000002) //!< Bit mask for IPU_DC_READ_CH_CONF_PROG_DI_ID_0.
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//! @brief Get value of IPU_DC_READ_CH_CONF_PROG_DI_ID_0 from a register value.
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#define BG_IPU_DC_READ_CH_CONF_PROG_DI_ID_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_PROG_DI_ID_0) >> BP_IPU_DC_READ_CH_CONF_PROG_DI_ID_0)
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//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_PROG_DI_ID_0.
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|
#define BF_IPU_DC_READ_CH_CONF_PROG_DI_ID_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_PROG_DI_ID_0) & BM_IPU_DC_READ_CH_CONF_PROG_DI_ID_0)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DI_ID_0 field to a new value.
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|
#define BW_IPU_DC_READ_CH_CONF_PROG_DI_ID_0(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_PROG_DI_ID_0) | BF_IPU_DC_READ_CH_CONF_PROG_DI_ID_0(v)))
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#endif
|
|
//@}
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|
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/*! @name Register IPU_DC_READ_CH_CONF, field PROG_DISP_ID_0[3:2] (RW)
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|
*
|
|
* The field defines which one of the 4 displays can be read.
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|
*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
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|
* - 10 - display #2
|
|
* - 11 - display #3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0 (2) //!< Bit position for IPU_DC_READ_CH_CONF_PROG_DISP_ID_0.
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#define BM_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0 (0x0000000c) //!< Bit mask for IPU_DC_READ_CH_CONF_PROG_DISP_ID_0.
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|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_PROG_DISP_ID_0 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0) >> BP_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0)
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|
|
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//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_PROG_DISP_ID_0.
|
|
#define BF_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0) & BM_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DISP_ID_0 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0) | BF_IPU_DC_READ_CH_CONF_PROG_DISP_ID_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field W_SIZE_0[5:4] (RW)
|
|
*
|
|
* Word Size The data coming from the IDMAC is 32bit wide. This field defines the size of the word
|
|
* used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_W_SIZE_0 (4) //!< Bit position for IPU_DC_READ_CH_CONF_W_SIZE_0.
|
|
#define BM_IPU_DC_READ_CH_CONF_W_SIZE_0 (0x00000030) //!< Bit mask for IPU_DC_READ_CH_CONF_W_SIZE_0.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_W_SIZE_0 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_W_SIZE_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_W_SIZE_0) >> BP_IPU_DC_READ_CH_CONF_W_SIZE_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_W_SIZE_0.
|
|
#define BF_IPU_DC_READ_CH_CONF_W_SIZE_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_W_SIZE_0) & BM_IPU_DC_READ_CH_CONF_W_SIZE_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_0 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_W_SIZE_0(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_W_SIZE_0) | BF_IPU_DC_READ_CH_CONF_W_SIZE_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field CHAN_MASK_DEFAULT_0[6] (RW)
|
|
*
|
|
* Event mask bit for the read channel When more then one event is used during a flow (EOF, EOL, NL,
|
|
* NF, EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
|
|
* event
|
|
*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
|
* - 1 - All the events are used - no mask
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0 (6) //!< Bit position for IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0.
|
|
#define BM_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0 (0x00000040) //!< Bit mask for IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0) >> BP_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0.
|
|
#define BF_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0) & BM_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CHAN_MASK_DEFAULT_0 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0) | BF_IPU_DC_READ_CH_CONF_CHAN_MASK_DEFAULT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field CS_ID_0[8] (RW)
|
|
*
|
|
* This bit maps an asynchronous display to a chip select
|
|
*
|
|
* Values:
|
|
* - 0 - display #0 is connected to CS0
|
|
* - 1 - display #0 is connected to CS1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_CS_ID_0 (8) //!< Bit position for IPU_DC_READ_CH_CONF_CS_ID_0.
|
|
#define BM_IPU_DC_READ_CH_CONF_CS_ID_0 (0x00000100) //!< Bit mask for IPU_DC_READ_CH_CONF_CS_ID_0.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_CS_ID_0 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_CS_ID_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_CS_ID_0) >> BP_IPU_DC_READ_CH_CONF_CS_ID_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_CS_ID_0.
|
|
#define BF_IPU_DC_READ_CH_CONF_CS_ID_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_CS_ID_0) & BM_IPU_DC_READ_CH_CONF_CS_ID_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CS_ID_0 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_CS_ID_0(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_CS_ID_0) | BF_IPU_DC_READ_CH_CONF_CS_ID_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field CS_ID_1[9] (RW)
|
|
*
|
|
* This bit maps an asynchronous display to a chip select
|
|
*
|
|
* Values:
|
|
* - 0 - display #1 is connected to CS0
|
|
* - 1 - display #1 is connected to CS1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_CS_ID_1 (9) //!< Bit position for IPU_DC_READ_CH_CONF_CS_ID_1.
|
|
#define BM_IPU_DC_READ_CH_CONF_CS_ID_1 (0x00000200) //!< Bit mask for IPU_DC_READ_CH_CONF_CS_ID_1.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_CS_ID_1 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_CS_ID_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_CS_ID_1) >> BP_IPU_DC_READ_CH_CONF_CS_ID_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_CS_ID_1.
|
|
#define BF_IPU_DC_READ_CH_CONF_CS_ID_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_CS_ID_1) & BM_IPU_DC_READ_CH_CONF_CS_ID_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CS_ID_1 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_CS_ID_1(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_CS_ID_1) | BF_IPU_DC_READ_CH_CONF_CS_ID_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field CS_ID_2[10] (RW)
|
|
*
|
|
* This bit maps an asynchronous display to a chip select
|
|
*
|
|
* Values:
|
|
* - 0 - display #2 is connected to CS0
|
|
* - 1 - display #2 is connected to CS1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_CS_ID_2 (10) //!< Bit position for IPU_DC_READ_CH_CONF_CS_ID_2.
|
|
#define BM_IPU_DC_READ_CH_CONF_CS_ID_2 (0x00000400) //!< Bit mask for IPU_DC_READ_CH_CONF_CS_ID_2.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_CS_ID_2 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_CS_ID_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_CS_ID_2) >> BP_IPU_DC_READ_CH_CONF_CS_ID_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_CS_ID_2.
|
|
#define BF_IPU_DC_READ_CH_CONF_CS_ID_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_CS_ID_2) & BM_IPU_DC_READ_CH_CONF_CS_ID_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CS_ID_2 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_CS_ID_2(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_CS_ID_2) | BF_IPU_DC_READ_CH_CONF_CS_ID_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field CS_ID_3[11] (RW)
|
|
*
|
|
* This bit maps an asynchronous display to a chip select
|
|
*
|
|
* Values:
|
|
* - 0 - display #3 is connected to CS0
|
|
* - 1 - display #3 is connected to CS1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_CS_ID_3 (11) //!< Bit position for IPU_DC_READ_CH_CONF_CS_ID_3.
|
|
#define BM_IPU_DC_READ_CH_CONF_CS_ID_3 (0x00000800) //!< Bit mask for IPU_DC_READ_CH_CONF_CS_ID_3.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_CS_ID_3 from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_CS_ID_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_CS_ID_3) >> BP_IPU_DC_READ_CH_CONF_CS_ID_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_CS_ID_3.
|
|
#define BF_IPU_DC_READ_CH_CONF_CS_ID_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_CS_ID_3) & BM_IPU_DC_READ_CH_CONF_CS_ID_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CS_ID_3 field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_CS_ID_3(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_CS_ID_3) | BF_IPU_DC_READ_CH_CONF_CS_ID_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_READ_CH_CONF, field TIME_OUT_VALUE[31:16] (RW)
|
|
*
|
|
* Time out value. In case of a error during read accesses to the display, where no response from
|
|
* the display was received. A time-out counter will terminate the current access and perform the
|
|
* next commend defined in the microcode. This field defines the amount of the hsp_clk cycles
|
|
* counted before the time-out event is issued. This event is tied to the interrupt controller and
|
|
* can generate an error interrupt.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE (16) //!< Bit position for IPU_DC_READ_CH_CONF_TIME_OUT_VALUE.
|
|
#define BM_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE (0xffff0000) //!< Bit mask for IPU_DC_READ_CH_CONF_TIME_OUT_VALUE.
|
|
|
|
//! @brief Get value of IPU_DC_READ_CH_CONF_TIME_OUT_VALUE from a register value.
|
|
#define BG_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE) >> BP_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_READ_CH_CONF_TIME_OUT_VALUE.
|
|
#define BF_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE) & BM_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the TIME_OUT_VALUE field to a new value.
|
|
#define BW_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE(x, v) (HW_IPU_DC_READ_CH_CONF_WR(x, (HW_IPU_DC_READ_CH_CONF_RD(x) & ~BM_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE) | BF_IPU_DC_READ_CH_CONF_TIME_OUT_VALUE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_READ_SH_ADDR - DC Read Channel Start Address Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_READ_SH_ADDR - DC Read Channel Start Address Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_read_sh_addr
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_read_sh_addr_bitfields
|
|
{
|
|
unsigned ST_ADDR_0 : 29; //!< [28:0] This field defines the start address within the display's memory space where the read transactions will be done from.
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_read_sh_addr_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_READ_SH_ADDR register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_READ_SH_ADDR_ADDR(x) (REGS_IPU_BASE(x) + 0x58004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_READ_SH_ADDR(x) (*(volatile hw_ipu_dc_read_sh_addr_t *) HW_IPU_DC_READ_SH_ADDR_ADDR(x))
|
|
#define HW_IPU_DC_READ_SH_ADDR_RD(x) (HW_IPU_DC_READ_SH_ADDR(x).U)
|
|
#define HW_IPU_DC_READ_SH_ADDR_WR(x, v) (HW_IPU_DC_READ_SH_ADDR(x).U = (v))
|
|
#define HW_IPU_DC_READ_SH_ADDR_SET(x, v) (HW_IPU_DC_READ_SH_ADDR_WR(x, HW_IPU_DC_READ_SH_ADDR_RD(x) | (v)))
|
|
#define HW_IPU_DC_READ_SH_ADDR_CLR(x, v) (HW_IPU_DC_READ_SH_ADDR_WR(x, HW_IPU_DC_READ_SH_ADDR_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_READ_SH_ADDR_TOG(x, v) (HW_IPU_DC_READ_SH_ADDR_WR(x, HW_IPU_DC_READ_SH_ADDR_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_READ_SH_ADDR bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_READ_SH_ADDR, field ST_ADDR_0[28:0] (RW)
|
|
*
|
|
* This field defines the start address within the display's memory space where the read
|
|
* transactions will be done from.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_READ_SH_ADDR_ST_ADDR_0 (0) //!< Bit position for IPU_DC_READ_SH_ADDR_ST_ADDR_0.
|
|
#define BM_IPU_DC_READ_SH_ADDR_ST_ADDR_0 (0x1fffffff) //!< Bit mask for IPU_DC_READ_SH_ADDR_ST_ADDR_0.
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|
|
|
//! @brief Get value of IPU_DC_READ_SH_ADDR_ST_ADDR_0 from a register value.
|
|
#define BG_IPU_DC_READ_SH_ADDR_ST_ADDR_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_READ_SH_ADDR_ST_ADDR_0) >> BP_IPU_DC_READ_SH_ADDR_ST_ADDR_0)
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|
|
|
//! @brief Format value for bitfield IPU_DC_READ_SH_ADDR_ST_ADDR_0.
|
|
#define BF_IPU_DC_READ_SH_ADDR_ST_ADDR_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_READ_SH_ADDR_ST_ADDR_0) & BM_IPU_DC_READ_SH_ADDR_ST_ADDR_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ST_ADDR_0 field to a new value.
|
|
#define BW_IPU_DC_READ_SH_ADDR_ST_ADDR_0(x, v) (HW_IPU_DC_READ_SH_ADDR_WR(x, (HW_IPU_DC_READ_SH_ADDR_RD(x) & ~BM_IPU_DC_READ_SH_ADDR_ST_ADDR_0) | BF_IPU_DC_READ_SH_ADDR_ST_ADDR_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL0_CH_0 - DC Routine Link Register 0 Channel 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL0_CH_0 - DC Routine Link Register 0 Channel 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl0_ch_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl0_ch_0_bitfields
|
|
{
|
|
unsigned COD_NF_PRIORITY_CHAN_0 : 4; //!< [3:0] This field defines the priority of the new frame (NF) event
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NF_START_CHAN_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new Frame event (NF) resides
|
|
unsigned COD_NL_PRIORITY_CHAN_0 : 4; //!< [19:16] This field defines the priority of the new line (NL) event
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NL_START_CHAN_0 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new line event (NL) resides
|
|
} B;
|
|
} hw_ipu_dc_rl0_ch_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL0_CH_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL0_CH_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL0_CH_0(x) (*(volatile hw_ipu_dc_rl0_ch_0_t *) HW_IPU_DC_RL0_CH_0_ADDR(x))
|
|
#define HW_IPU_DC_RL0_CH_0_RD(x) (HW_IPU_DC_RL0_CH_0(x).U)
|
|
#define HW_IPU_DC_RL0_CH_0_WR(x, v) (HW_IPU_DC_RL0_CH_0(x).U = (v))
|
|
#define HW_IPU_DC_RL0_CH_0_SET(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, HW_IPU_DC_RL0_CH_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL0_CH_0_CLR(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, HW_IPU_DC_RL0_CH_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL0_CH_0_TOG(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, HW_IPU_DC_RL0_CH_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL0_CH_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_0, field COD_NF_PRIORITY_CHAN_0[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new frame (NF) event The priority between the events
|
|
* should be set to a unique value. i.e. two events must not have the same priority (except 0000 -
|
|
* disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0 (0) //!< Bit position for IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0 (0x0000000f) //!< Bit mask for IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0) >> BP_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0) & BM_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, (HW_IPU_DC_RL0_CH_0_RD(x) & ~BM_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0) | BF_IPU_DC_RL0_CH_0_COD_NF_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_0, field COD_NF_START_CHAN_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new Frame event (NF) resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0 (8) //!< Bit position for IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0.
|
|
#define BM_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0) >> BP_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0.
|
|
#define BF_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0) & BM_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, (HW_IPU_DC_RL0_CH_0_RD(x) & ~BM_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0) | BF_IPU_DC_RL0_CH_0_COD_NF_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_0, field COD_NL_PRIORITY_CHAN_0[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line (NL) event The priority between the events should
|
|
* be set to a unique value. i.e. two events must not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0 (16) //!< Bit position for IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0 (0x000f0000) //!< Bit mask for IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0) >> BP_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0) & BM_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, (HW_IPU_DC_RL0_CH_0_RD(x) & ~BM_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0) | BF_IPU_DC_RL0_CH_0_COD_NL_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_0, field COD_NL_START_CHAN_0[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new line event (NL) resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0 (24) //!< Bit position for IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0.
|
|
#define BM_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0 (0xff000000) //!< Bit mask for IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0) >> BP_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0.
|
|
#define BF_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0) & BM_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0(x, v) (HW_IPU_DC_RL0_CH_0_WR(x, (HW_IPU_DC_RL0_CH_0_RD(x) & ~BM_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0) | BF_IPU_DC_RL0_CH_0_COD_NL_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL1_CH_0 - DC Routine Link Register 1 Channel 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_0 - DC Routine Link Register 1 Channel 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl1_ch_0_bitfields
|
|
{
|
|
unsigned COD_EOF_PRIORITY_CHAN_0 : 4; //!< [3:0] This field defines the priority of the end-of-frame event (EOF) event
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOF_START_CHAN_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end-of-frame event (EOF) resides
|
|
unsigned COD_NFIELD_PRIORITY_CHAN_0 : 4; //!< [19:16] This field defines the priority of the new field event
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NFIELD_START_CHAN_0 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new field event resides
|
|
} B;
|
|
} hw_ipu_dc_rl1_ch_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL1_CH_0_ADDR(x) (REGS_IPU_BASE(x) + 0x5800c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL1_CH_0(x) (*(volatile hw_ipu_dc_rl1_ch_0_t *) HW_IPU_DC_RL1_CH_0_ADDR(x))
|
|
#define HW_IPU_DC_RL1_CH_0_RD(x) (HW_IPU_DC_RL1_CH_0(x).U)
|
|
#define HW_IPU_DC_RL1_CH_0_WR(x, v) (HW_IPU_DC_RL1_CH_0(x).U = (v))
|
|
#define HW_IPU_DC_RL1_CH_0_SET(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, HW_IPU_DC_RL1_CH_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL1_CH_0_CLR(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, HW_IPU_DC_RL1_CH_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL1_CH_0_TOG(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, HW_IPU_DC_RL1_CH_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL1_CH_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_0, field COD_EOF_PRIORITY_CHAN_0[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the end-of-frame event (EOF) event The priority between the
|
|
* events should be set to a unique value. i.e. two events must not have the same priority (except
|
|
* 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0 (0) //!< Bit position for IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0) >> BP_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0) & BM_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, (HW_IPU_DC_RL1_CH_0_RD(x) & ~BM_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0) | BF_IPU_DC_RL1_CH_0_COD_EOF_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_0, field COD_EOF_START_CHAN_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end-of-frame event (EOF) resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0 (8) //!< Bit position for IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0.
|
|
#define BM_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0) >> BP_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0.
|
|
#define BF_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0) & BM_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, (HW_IPU_DC_RL1_CH_0_RD(x) & ~BM_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0) | BF_IPU_DC_RL1_CH_0_COD_EOF_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_0, field COD_NFIELD_PRIORITY_CHAN_0[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new field event The priority between the events should be
|
|
* set to a unique value. i.e. two events must not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0 (16) //!< Bit position for IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0 (0x000f0000) //!< Bit mask for IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0) >> BP_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0) & BM_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, (HW_IPU_DC_RL1_CH_0_RD(x) & ~BM_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0) | BF_IPU_DC_RL1_CH_0_COD_NFIELD_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_0, field COD_NFIELD_START_CHAN_0[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new field event resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0 (24) //!< Bit position for IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0.
|
|
#define BM_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0) >> BP_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0.
|
|
#define BF_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0) & BM_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0(x, v) (HW_IPU_DC_RL1_CH_0_WR(x, (HW_IPU_DC_RL1_CH_0_RD(x) & ~BM_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0) | BF_IPU_DC_RL1_CH_0_COD_NFIELD_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_0 - DC Routine Link Register2 Channel 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_0 - DC Routine Link Register2 Channel 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_0_bitfields
|
|
{
|
|
unsigned COD_EOL_PRIORITY_CHAN_0 : 4; //!< [3:0] This field defines the priority of the end-of-line event (EOL) event
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOL_START_CHAN_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end-of-line event (EOL) resides
|
|
unsigned COD_EOFIELD_PRIORITY_CHAN_0 : 4; //!< [19:16] This field defines the priority of the end-of-field event
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_EOFIELD_START_CHAN_0 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the end-of-field event resides
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_0(x) (*(volatile hw_ipu_dc_rl2_ch_0_t *) HW_IPU_DC_RL2_CH_0_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_0_RD(x) (HW_IPU_DC_RL2_CH_0(x).U)
|
|
#define HW_IPU_DC_RL2_CH_0_WR(x, v) (HW_IPU_DC_RL2_CH_0(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_0_SET(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, HW_IPU_DC_RL2_CH_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_0_CLR(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, HW_IPU_DC_RL2_CH_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_0_TOG(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, HW_IPU_DC_RL2_CH_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_0, field COD_EOL_PRIORITY_CHAN_0[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the end-of-line event (EOL) event The priority between the
|
|
* events should be set to a unique value. i.e. two events must not have the same priority (except
|
|
* 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0 (0) //!< Bit position for IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0) >> BP_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0) & BM_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, (HW_IPU_DC_RL2_CH_0_RD(x) & ~BM_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0) | BF_IPU_DC_RL2_CH_0_COD_EOL_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_0, field COD_EOL_START_CHAN_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end-of-line event (EOL) resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0 (8) //!< Bit position for IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0.
|
|
#define BM_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0) >> BP_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0.
|
|
#define BF_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0) & BM_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, (HW_IPU_DC_RL2_CH_0_RD(x) & ~BM_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0) | BF_IPU_DC_RL2_CH_0_COD_EOL_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_0, field COD_EOFIELD_PRIORITY_CHAN_0[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the end-of-field event The priority between the events should
|
|
* be set to a unique value. i.e. two events must not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0 (16) //!< Bit position for IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0 (0x000f0000) //!< Bit mask for IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0) >> BP_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0) & BM_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, (HW_IPU_DC_RL2_CH_0_RD(x) & ~BM_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0) | BF_IPU_DC_RL2_CH_0_COD_EOFIELD_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_0, field COD_EOFIELD_START_CHAN_0[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end-of-field event resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0 (24) //!< Bit position for IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0.
|
|
#define BM_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0) >> BP_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0.
|
|
#define BF_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0) & BM_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0(x, v) (HW_IPU_DC_RL2_CH_0_WR(x, (HW_IPU_DC_RL2_CH_0_RD(x) & ~BM_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0) | BF_IPU_DC_RL2_CH_0_COD_EOFIELD_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL3_CH_0 - DC Routine Link Registe3 Channel 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL3_CH_0 - DC Routine Link Registe3 Channel 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl3_ch_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl3_ch_0_bitfields
|
|
{
|
|
unsigned COD_NEW_ADDR_PRIORITY_CHAN_0 : 4; //!< [3:0] This field defines the priority of the new address event
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides
|
|
unsigned COD_NEW_CHAN_PRIORITY_CHAN_0 : 4; //!< [19:16] This field defines the priority of the new channel event
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_0 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides
|
|
} B;
|
|
} hw_ipu_dc_rl3_ch_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL3_CH_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL3_CH_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL3_CH_0(x) (*(volatile hw_ipu_dc_rl3_ch_0_t *) HW_IPU_DC_RL3_CH_0_ADDR(x))
|
|
#define HW_IPU_DC_RL3_CH_0_RD(x) (HW_IPU_DC_RL3_CH_0(x).U)
|
|
#define HW_IPU_DC_RL3_CH_0_WR(x, v) (HW_IPU_DC_RL3_CH_0(x).U = (v))
|
|
#define HW_IPU_DC_RL3_CH_0_SET(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, HW_IPU_DC_RL3_CH_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL3_CH_0_CLR(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, HW_IPU_DC_RL3_CH_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL3_CH_0_TOG(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, HW_IPU_DC_RL3_CH_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL3_CH_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_0, field COD_NEW_ADDR_PRIORITY_CHAN_0[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new address event The priority between the events should
|
|
* be set to a unique value. i.e. two events must not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0 (0) //!< Bit position for IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0) >> BP_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0) & BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_0 field to a new value.
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#define BW_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, (HW_IPU_DC_RL3_CH_0_RD(x) & ~BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0) | BF_IPU_DC_RL3_CH_0_COD_NEW_ADDR_PRIORITY_CHAN_0(v)))
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#endif
|
|
//@}
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|
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/*! @name Register IPU_DC_RL3_CH_0, field COD_NEW_ADDR_START_CHAN_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides
|
|
*/
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|
//@{
|
|
#define BP_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0 (8) //!< Bit position for IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0.
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#define BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0.
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//! @brief Get value of IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0 from a register value.
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|
#define BG_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0) >> BP_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0.
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#define BF_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0) & BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_ADDR_START_CHAN_0 field to a new value.
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#define BW_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, (HW_IPU_DC_RL3_CH_0_RD(x) & ~BM_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0) | BF_IPU_DC_RL3_CH_0_COD_NEW_ADDR_START_CHAN_0(v)))
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#endif
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//@}
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|
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/*! @name Register IPU_DC_RL3_CH_0, field COD_NEW_CHAN_PRIORITY_CHAN_0[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new channel event The priority between the events should
|
|
* be set to a unique value. i.e. two events must not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
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|
*/
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|
//@{
|
|
#define BP_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0 (16) //!< Bit position for IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0.
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#define BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0 (0x000f0000) //!< Bit mask for IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0.
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//! @brief Get value of IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0 from a register value.
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|
#define BG_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0) >> BP_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0.
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|
#define BF_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0) & BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_0 field to a new value.
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|
#define BW_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, (HW_IPU_DC_RL3_CH_0_RD(x) & ~BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0) | BF_IPU_DC_RL3_CH_0_COD_NEW_CHAN_PRIORITY_CHAN_0(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DC_RL3_CH_0, field COD_NEW_CHAN_START_CHAN_0[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides
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|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0 (24) //!< Bit position for IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0.
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#define BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0.
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//! @brief Get value of IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0 from a register value.
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|
#define BG_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0) >> BP_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0)
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|
//! @brief Format value for bitfield IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0.
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|
#define BF_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0) & BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0(x, v) (HW_IPU_DC_RL3_CH_0_WR(x, (HW_IPU_DC_RL3_CH_0_RD(x) & ~BM_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0) | BF_IPU_DC_RL3_CH_0_COD_NEW_CHAN_START_CHAN_0(v)))
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|
#endif
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|
//@}
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|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL4_CH_0 - DC Routine Link Register 4 Channel 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL4_CH_0 - DC Routine Link Register 4 Channel 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl4_ch_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl4_ch_0_bitfields
|
|
{
|
|
unsigned COD_NEW_DATA_PRIORITY_CHAN_0 : 4; //!< [3:0] This field defines the priority of the new data event
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides
|
|
unsigned RESERVED1 : 16; //!< [31:16] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_rl4_ch_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL4_CH_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL4_CH_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58018)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL4_CH_0(x) (*(volatile hw_ipu_dc_rl4_ch_0_t *) HW_IPU_DC_RL4_CH_0_ADDR(x))
|
|
#define HW_IPU_DC_RL4_CH_0_RD(x) (HW_IPU_DC_RL4_CH_0(x).U)
|
|
#define HW_IPU_DC_RL4_CH_0_WR(x, v) (HW_IPU_DC_RL4_CH_0(x).U = (v))
|
|
#define HW_IPU_DC_RL4_CH_0_SET(x, v) (HW_IPU_DC_RL4_CH_0_WR(x, HW_IPU_DC_RL4_CH_0_RD(x) | (v)))
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|
#define HW_IPU_DC_RL4_CH_0_CLR(x, v) (HW_IPU_DC_RL4_CH_0_WR(x, HW_IPU_DC_RL4_CH_0_RD(x) & ~(v)))
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|
#define HW_IPU_DC_RL4_CH_0_TOG(x, v) (HW_IPU_DC_RL4_CH_0_WR(x, HW_IPU_DC_RL4_CH_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_0, field COD_NEW_DATA_PRIORITY_CHAN_0[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new data event The priority between the events should be
|
|
* set to a unique value. i.e. two events must not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0 (0) //!< Bit position for IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0.
|
|
#define BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0 (0x0000000f) //!< Bit mask for IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0.
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|
|
|
//! @brief Get value of IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0) >> BP_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0.
|
|
#define BF_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0) & BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0(x, v) (HW_IPU_DC_RL4_CH_0_WR(x, (HW_IPU_DC_RL4_CH_0_RD(x) & ~BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0) | BF_IPU_DC_RL4_CH_0_COD_NEW_DATA_PRIORITY_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_0, field COD_NEW_DATA_START_CHAN_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0 (8) //!< Bit position for IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0.
|
|
#define BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0) >> BP_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0.
|
|
#define BF_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0) & BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_0 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0(x, v) (HW_IPU_DC_RL4_CH_0_WR(x, (HW_IPU_DC_RL4_CH_0_RD(x) & ~BM_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0) | BF_IPU_DC_RL4_CH_0_COD_NEW_DATA_START_CHAN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF_1 - DC Write Channel 1 Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF_1 - DC Write Channel 1 Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf_1_bitfields
|
|
{
|
|
unsigned W_SIZE_1 : 2; //!< [1:0] Word Size associated with channel #1
|
|
unsigned PROG_DI_ID_1 : 1; //!< [2] This bit select the DI which a transaction associated with channel #1 can be performed to
|
|
unsigned PROG_DISP_ID_1 : 2; //!< [4:3] The field defines which one of the 4 displays is associated with channel #1.
|
|
unsigned PROG_CHAN_TYP_1 : 3; //!< [7:5] This field define the mode of operation of channel #1
|
|
unsigned CHAN_MASK_DEFAULT_1 : 1; //!< [8] Event mask bit for channel #1
|
|
unsigned FIELD_MODE_1 : 1; //!< [9] Field mode bit for channel #1
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved.
|
|
unsigned PROG_START_TIME_1 : 11; //!< [26:16] This field defines the delay between display 's vertical synchronization pulse and the start time point of DC's channel 1 window.
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF_1_ADDR(x) (REGS_IPU_BASE(x) + 0x5801c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF_1(x) (*(volatile hw_ipu_dc_wr_ch_conf_1_t *) HW_IPU_DC_WR_CH_CONF_1_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF_1_RD(x) (HW_IPU_DC_WR_CH_CONF_1(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF_1_WR(x, v) (HW_IPU_DC_WR_CH_CONF_1(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF_1_SET(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, HW_IPU_DC_WR_CH_CONF_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_1_CLR(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_1_TOG(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, HW_IPU_DC_WR_CH_CONF_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_1, field W_SIZE_1[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #1 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_1_W_SIZE_1 (0) //!< Bit position for IPU_DC_WR_CH_CONF_1_W_SIZE_1.
|
|
#define BM_IPU_DC_WR_CH_CONF_1_W_SIZE_1 (0x00000003) //!< Bit mask for IPU_DC_WR_CH_CONF_1_W_SIZE_1.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_1_W_SIZE_1 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_1_W_SIZE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_W_SIZE_1) >> BP_IPU_DC_WR_CH_CONF_1_W_SIZE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_W_SIZE_1.
|
|
#define BF_IPU_DC_WR_CH_CONF_1_W_SIZE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_W_SIZE_1) & BM_IPU_DC_WR_CH_CONF_1_W_SIZE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_1 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_1_W_SIZE_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_W_SIZE_1) | BF_IPU_DC_WR_CH_CONF_1_W_SIZE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_1, field PROG_DI_ID_1[2] (RW)
|
|
*
|
|
* This bit select the DI which a transaction associated with channel #1 can be performed to
|
|
*
|
|
* Values:
|
|
* - 0 - DI #0
|
|
* - 1 - DI #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1 (2) //!< Bit position for IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1.
|
|
#define BM_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1 (0x00000004) //!< Bit mask for IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1) >> BP_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1.
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#define BF_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1) & BM_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PROG_DI_ID_1 field to a new value.
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#define BW_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1) | BF_IPU_DC_WR_CH_CONF_1_PROG_DI_ID_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_WR_CH_CONF_1, field PROG_DISP_ID_1[4:3] (RW)
|
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*
|
|
* The field defines which one of the 4 displays is associated with channel #1.
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*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
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* - 10 - display #2
|
|
* - 11 - display #3
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|
*/
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|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1 (3) //!< Bit position for IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1.
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#define BM_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1 (0x00000018) //!< Bit mask for IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1.
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//! @brief Get value of IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1) >> BP_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1.
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#define BF_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1) & BM_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PROG_DISP_ID_1 field to a new value.
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#define BW_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1) | BF_IPU_DC_WR_CH_CONF_1_PROG_DISP_ID_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_WR_CH_CONF_1, field PROG_CHAN_TYP_1[7:5] (RW)
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*
|
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* This field define the mode of operation of channel #1
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*
|
|
* Values:
|
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* - 000 - Disable
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* - 001 - Reserved
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* - 010 - Reserved
|
|
* - 100 - Normal mode without anti-tearing. For sync display this is the only mode allowed
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* - 101 - Normal mode with anti-tearing
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* - 110 - Reserved
|
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* - 111 - Additional command channel is added to the flow handled by DC channel #1
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*/
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//@{
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#define BP_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1 (5) //!< Bit position for IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1.
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#define BM_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1 (0x000000e0) //!< Bit mask for IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1.
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//! @brief Get value of IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1) >> BP_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1.
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#define BF_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1) & BM_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PROG_CHAN_TYP_1 field to a new value.
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|
#define BW_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1) | BF_IPU_DC_WR_CH_CONF_1_PROG_CHAN_TYP_1(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_WR_CH_CONF_1, field CHAN_MASK_DEFAULT_1[8] (RW)
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*
|
|
* Event mask bit for channel #1 When more then one event is used during a flow (EOF, EOL, NL, NF,
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|
* EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
|
|
* event
|
|
*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
|
* - 1 - All the events are used - no mask
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|
*/
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//@{
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|
#define BP_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1 (8) //!< Bit position for IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1.
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#define BM_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1 (0x00000100) //!< Bit mask for IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1.
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//! @brief Get value of IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1 from a register value.
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|
#define BG_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1) >> BP_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1.
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|
#define BF_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1) & BM_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1)
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|
|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the CHAN_MASK_DEFAULT_1 field to a new value.
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|
#define BW_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1) | BF_IPU_DC_WR_CH_CONF_1_CHAN_MASK_DEFAULT_1(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DC_WR_CH_CONF_1, field FIELD_MODE_1[9] (RW)
|
|
*
|
|
* Field mode bit for channel #1 This bit defines if the channel works in field mode or frame mode;
|
|
* This bit is relevant if the flow is sync flow
|
|
*
|
|
* Values:
|
|
* - 0 - Frame mode
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|
* - 1 - Field mode
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|
*/
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|
//@{
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|
#define BP_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1 (9) //!< Bit position for IPU_DC_WR_CH_CONF_1_FIELD_MODE_1.
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|
#define BM_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1 (0x00000200) //!< Bit mask for IPU_DC_WR_CH_CONF_1_FIELD_MODE_1.
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|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_1_FIELD_MODE_1 from a register value.
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|
#define BG_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1) >> BP_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1)
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|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_FIELD_MODE_1.
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|
#define BF_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1) & BM_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the FIELD_MODE_1 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1) | BF_IPU_DC_WR_CH_CONF_1_FIELD_MODE_1(v)))
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|
#endif
|
|
//@}
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/*! @name Register IPU_DC_WR_CH_CONF_1, field PROG_START_TIME_1[26:16] (RW)
|
|
*
|
|
* This field defines the delay between display 's vertical synchronization pulse and the start time
|
|
* point of DC's channel 1 window. The delay is defined in pairs of rows. It is used for tearing
|
|
* elimination
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|
*/
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|
//@{
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|
#define BP_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1 (16) //!< Bit position for IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1.
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|
#define BM_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1 (0x07ff0000) //!< Bit mask for IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1.
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|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1) >> BP_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1)
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|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1.
|
|
#define BF_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1) & BM_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_START_TIME_1 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1(x, v) (HW_IPU_DC_WR_CH_CONF_1_WR(x, (HW_IPU_DC_WR_CH_CONF_1_RD(x) & ~BM_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1) | BF_IPU_DC_WR_CH_CONF_1_PROG_START_TIME_1(v)))
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|
#endif
|
|
//@}
|
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|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_ADDR_1 - DC Write Channel 1 Address Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_ADDR_1 - DC Write Channel 1 Address Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_addr_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_addr_1_bitfields
|
|
{
|
|
unsigned ST_ADDR_1 : 29; //!< [28:0] This field defines the start address within the display's memory space where the write transactions will be done to for channel #1.
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_addr_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_ADDR_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_ADDR_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58020)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_ADDR_1(x) (*(volatile hw_ipu_dc_wr_ch_addr_1_t *) HW_IPU_DC_WR_CH_ADDR_1_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_ADDR_1_RD(x) (HW_IPU_DC_WR_CH_ADDR_1(x).U)
|
|
#define HW_IPU_DC_WR_CH_ADDR_1_WR(x, v) (HW_IPU_DC_WR_CH_ADDR_1(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_ADDR_1_SET(x, v) (HW_IPU_DC_WR_CH_ADDR_1_WR(x, HW_IPU_DC_WR_CH_ADDR_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_ADDR_1_CLR(x, v) (HW_IPU_DC_WR_CH_ADDR_1_WR(x, HW_IPU_DC_WR_CH_ADDR_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_ADDR_1_TOG(x, v) (HW_IPU_DC_WR_CH_ADDR_1_WR(x, HW_IPU_DC_WR_CH_ADDR_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_ADDR_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_ADDR_1, field ST_ADDR_1[28:0] (RW)
|
|
*
|
|
* This field defines the start address within the display's memory space where the write
|
|
* transactions will be done to for channel #1.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1 (0) //!< Bit position for IPU_DC_WR_CH_ADDR_1_ST_ADDR_1.
|
|
#define BM_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1 (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_ADDR_1_ST_ADDR_1.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_ADDR_1_ST_ADDR_1 from a register value.
|
|
#define BG_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1) >> BP_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_ADDR_1_ST_ADDR_1.
|
|
#define BF_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1) & BM_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ST_ADDR_1 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1(x, v) (HW_IPU_DC_WR_CH_ADDR_1_WR(x, (HW_IPU_DC_WR_CH_ADDR_1_RD(x) & ~BM_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1) | BF_IPU_DC_WR_CH_ADDR_1_ST_ADDR_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL0_CH_1 - DC Routine Link Register 0 Channel 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL0_CH_1 - DC Routine Link Register 0 Channel 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl0_ch_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl0_ch_1_bitfields
|
|
{
|
|
unsigned COD_NF_PRIORITY_CHAN_1 : 4; //!< [3:0] This field defines the priority of the new frame event (associated with channel #1)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NF_START_CHAN_1 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new frame event resides (associated with channel #1)
|
|
unsigned COD_NL_PRIORITY_CHAN_1 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #1)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NL_START_CHAN_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new line event resides (associated with channel #1)
|
|
} B;
|
|
} hw_ipu_dc_rl0_ch_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL0_CH_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL0_CH_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL0_CH_1(x) (*(volatile hw_ipu_dc_rl0_ch_1_t *) HW_IPU_DC_RL0_CH_1_ADDR(x))
|
|
#define HW_IPU_DC_RL0_CH_1_RD(x) (HW_IPU_DC_RL0_CH_1(x).U)
|
|
#define HW_IPU_DC_RL0_CH_1_WR(x, v) (HW_IPU_DC_RL0_CH_1(x).U = (v))
|
|
#define HW_IPU_DC_RL0_CH_1_SET(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, HW_IPU_DC_RL0_CH_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL0_CH_1_CLR(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, HW_IPU_DC_RL0_CH_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL0_CH_1_TOG(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, HW_IPU_DC_RL0_CH_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL0_CH_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_1, field COD_NF_PRIORITY_CHAN_1[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new frame event (associated with channel #1) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1 (0) //!< Bit position for IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1 (0x0000000f) //!< Bit mask for IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1) >> BP_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1) & BM_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, (HW_IPU_DC_RL0_CH_1_RD(x) & ~BM_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1) | BF_IPU_DC_RL0_CH_1_COD_NF_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_1, field COD_NF_START_CHAN_1[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new frame event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1 (8) //!< Bit position for IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1.
|
|
#define BM_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1 (0x0000ff00) //!< Bit mask for IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1) >> BP_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1.
|
|
#define BF_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1) & BM_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, (HW_IPU_DC_RL0_CH_1_RD(x) & ~BM_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1) | BF_IPU_DC_RL0_CH_1_COD_NF_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_1, field COD_NL_PRIORITY_CHAN_1[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #1) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1 (16) //!< Bit position for IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1 (0x000f0000) //!< Bit mask for IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1) >> BP_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1) & BM_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, (HW_IPU_DC_RL0_CH_1_RD(x) & ~BM_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1) | BF_IPU_DC_RL0_CH_1_COD_NL_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_1, field COD_NL_START_CHAN_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new line event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1 (24) //!< Bit position for IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1.
|
|
#define BM_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1 (0xff000000) //!< Bit mask for IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1) >> BP_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1.
|
|
#define BF_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1) & BM_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1(x, v) (HW_IPU_DC_RL0_CH_1_WR(x, (HW_IPU_DC_RL0_CH_1_RD(x) & ~BM_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1) | BF_IPU_DC_RL0_CH_1_COD_NL_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL1_CH_1 - DC Routine Link Register 1 Channel 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_1 - DC Routine Link Register 1 Channel 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl1_ch_1_bitfields
|
|
{
|
|
unsigned COD_EOF_PRIORITY_CHAN_1 : 4; //!< [3:0] This field defines the priority of the end of frame event (associated with channel #1)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOF_START_CHAN_1 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of frame event resides (associated with channel #1)
|
|
unsigned COD_NFIELD_PRIORITY_CHAN_1 : 4; //!< [19:16] This field defines the priority of the new field event (associated with channel #1)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NFIELD_START_CHAN_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new field event resides (associated with channel #1)
|
|
} B;
|
|
} hw_ipu_dc_rl1_ch_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL1_CH_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58028)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL1_CH_1(x) (*(volatile hw_ipu_dc_rl1_ch_1_t *) HW_IPU_DC_RL1_CH_1_ADDR(x))
|
|
#define HW_IPU_DC_RL1_CH_1_RD(x) (HW_IPU_DC_RL1_CH_1(x).U)
|
|
#define HW_IPU_DC_RL1_CH_1_WR(x, v) (HW_IPU_DC_RL1_CH_1(x).U = (v))
|
|
#define HW_IPU_DC_RL1_CH_1_SET(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, HW_IPU_DC_RL1_CH_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL1_CH_1_CLR(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, HW_IPU_DC_RL1_CH_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL1_CH_1_TOG(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, HW_IPU_DC_RL1_CH_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL1_CH_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_1, field COD_EOF_PRIORITY_CHAN_1[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the end of frame event (associated with channel #1) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1 (0) //!< Bit position for IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1) >> BP_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1) & BM_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, (HW_IPU_DC_RL1_CH_1_RD(x) & ~BM_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1) | BF_IPU_DC_RL1_CH_1_COD_EOF_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_1, field COD_EOF_START_CHAN_1[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of frame event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1 (8) //!< Bit position for IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1.
|
|
#define BM_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1) >> BP_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1.
|
|
#define BF_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1) & BM_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, (HW_IPU_DC_RL1_CH_1_RD(x) & ~BM_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1) | BF_IPU_DC_RL1_CH_1_COD_EOF_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_1, field COD_NFIELD_PRIORITY_CHAN_1[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #1) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1 (16) //!< Bit position for IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1 (0x000f0000) //!< Bit mask for IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1) >> BP_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1) & BM_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, (HW_IPU_DC_RL1_CH_1_RD(x) & ~BM_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1) | BF_IPU_DC_RL1_CH_1_COD_NFIELD_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_1, field COD_NFIELD_START_CHAN_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new field event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1 (24) //!< Bit position for IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1.
|
|
#define BM_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1) >> BP_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1.
|
|
#define BF_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1) & BM_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1(x, v) (HW_IPU_DC_RL1_CH_1_WR(x, (HW_IPU_DC_RL1_CH_1_RD(x) & ~BM_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1) | BF_IPU_DC_RL1_CH_1_COD_NFIELD_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_1 - DC Routine Link Register 2 Channel 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_1 - DC Routine Link Register 2 Channel 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_1_bitfields
|
|
{
|
|
unsigned COD_EOL_PRIORITY_CHAN_1 : 4; //!< [3:0] This field defines the priority of the end of line event (associated with channel #1)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOL_START_CHAN_1 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of line event resides (associated with channel #1)
|
|
unsigned COD_EOFIELD_PRIORITY_CHAN_1 : 4; //!< [19:16] This field defines the priority of the end of field event (associated with channel #1)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_EOFIELD_START_CHAN_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the end of field event resides (associated with channel #1)
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58030)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_1(x) (*(volatile hw_ipu_dc_rl2_ch_1_t *) HW_IPU_DC_RL2_CH_1_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_1_RD(x) (HW_IPU_DC_RL2_CH_1(x).U)
|
|
#define HW_IPU_DC_RL2_CH_1_WR(x, v) (HW_IPU_DC_RL2_CH_1(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_1_SET(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, HW_IPU_DC_RL2_CH_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_1_CLR(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, HW_IPU_DC_RL2_CH_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_1_TOG(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, HW_IPU_DC_RL2_CH_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_1, field COD_EOL_PRIORITY_CHAN_1[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the end of line event (associated with channel #1) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1 (0) //!< Bit position for IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1.
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|
|
|
//! @brief Get value of IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1) >> BP_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1) & BM_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, (HW_IPU_DC_RL2_CH_1_RD(x) & ~BM_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1) | BF_IPU_DC_RL2_CH_1_COD_EOL_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_1, field COD_EOL_START_CHAN_1[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of line event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1 (8) //!< Bit position for IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1.
|
|
#define BM_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1) >> BP_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1.
|
|
#define BF_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1) & BM_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, (HW_IPU_DC_RL2_CH_1_RD(x) & ~BM_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1) | BF_IPU_DC_RL2_CH_1_COD_EOL_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_1, field COD_EOFIELD_PRIORITY_CHAN_1[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the end of field event (associated with channel #1) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1 (16) //!< Bit position for IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1 (0x000f0000) //!< Bit mask for IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1) >> BP_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1) & BM_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, (HW_IPU_DC_RL2_CH_1_RD(x) & ~BM_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1) | BF_IPU_DC_RL2_CH_1_COD_EOFIELD_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_1, field COD_EOFIELD_START_CHAN_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of field event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1 (24) //!< Bit position for IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1.
|
|
#define BM_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1) >> BP_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1.
|
|
#define BF_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1) & BM_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1(x, v) (HW_IPU_DC_RL2_CH_1_WR(x, (HW_IPU_DC_RL2_CH_1_RD(x) & ~BM_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1) | BF_IPU_DC_RL2_CH_1_COD_EOFIELD_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL3_CH_1 - DC Routine Link Register 3 Channel 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL3_CH_1 - DC Routine Link Register 3 Channel 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl3_ch_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl3_ch_1_bitfields
|
|
{
|
|
unsigned COD_NEW_ADDR_PRIORITY_CHAN_1 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #1)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_1 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #1)
|
|
unsigned COD_NEW_CHAN_PRIORITY_CHAN_1 : 4; //!< [19:16] This field defines the priority of the new channel event (associated with channel #1)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #1)
|
|
} B;
|
|
} hw_ipu_dc_rl3_ch_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL3_CH_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL3_CH_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58032)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL3_CH_1(x) (*(volatile hw_ipu_dc_rl3_ch_1_t *) HW_IPU_DC_RL3_CH_1_ADDR(x))
|
|
#define HW_IPU_DC_RL3_CH_1_RD(x) (HW_IPU_DC_RL3_CH_1(x).U)
|
|
#define HW_IPU_DC_RL3_CH_1_WR(x, v) (HW_IPU_DC_RL3_CH_1(x).U = (v))
|
|
#define HW_IPU_DC_RL3_CH_1_SET(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, HW_IPU_DC_RL3_CH_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL3_CH_1_CLR(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, HW_IPU_DC_RL3_CH_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL3_CH_1_TOG(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, HW_IPU_DC_RL3_CH_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL3_CH_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_1, field COD_NEW_ADDR_PRIORITY_CHAN_1[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new address event (associated with channel #1) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1 (0) //!< Bit position for IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1) >> BP_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1) & BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, (HW_IPU_DC_RL3_CH_1_RD(x) & ~BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1) | BF_IPU_DC_RL3_CH_1_COD_NEW_ADDR_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_1, field COD_NEW_ADDR_START_CHAN_1[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1 (8) //!< Bit position for IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1.
|
|
#define BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1) >> BP_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1.
|
|
#define BF_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1) & BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, (HW_IPU_DC_RL3_CH_1_RD(x) & ~BM_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1) | BF_IPU_DC_RL3_CH_1_COD_NEW_ADDR_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_1, field COD_NEW_CHAN_PRIORITY_CHAN_1[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new channel event (associated with channel #1) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1 (16) //!< Bit position for IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1 (0x000f0000) //!< Bit mask for IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1) >> BP_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1) & BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, (HW_IPU_DC_RL3_CH_1_RD(x) & ~BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1) | BF_IPU_DC_RL3_CH_1_COD_NEW_CHAN_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_1, field COD_NEW_CHAN_START_CHAN_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1 (24) //!< Bit position for IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1.
|
|
#define BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1) >> BP_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1.
|
|
#define BF_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1) & BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1(x, v) (HW_IPU_DC_RL3_CH_1_WR(x, (HW_IPU_DC_RL3_CH_1_RD(x) & ~BM_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1) | BF_IPU_DC_RL3_CH_1_COD_NEW_CHAN_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL4_CH_1 - DC Routine Link Register 4 Channel 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL4_CH_1 - DC Routine Link Register 4 Channel 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl4_ch_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl4_ch_1_bitfields
|
|
{
|
|
unsigned COD_NEW_DATA_PRIORITY_CHAN_1 : 4; //!< [3:0] This field defines the priority of the new data event (associated with channel #1)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_1 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #1)
|
|
unsigned RESERVED1 : 16; //!< [31:16] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_rl4_ch_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL4_CH_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL4_CH_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58034)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL4_CH_1(x) (*(volatile hw_ipu_dc_rl4_ch_1_t *) HW_IPU_DC_RL4_CH_1_ADDR(x))
|
|
#define HW_IPU_DC_RL4_CH_1_RD(x) (HW_IPU_DC_RL4_CH_1(x).U)
|
|
#define HW_IPU_DC_RL4_CH_1_WR(x, v) (HW_IPU_DC_RL4_CH_1(x).U = (v))
|
|
#define HW_IPU_DC_RL4_CH_1_SET(x, v) (HW_IPU_DC_RL4_CH_1_WR(x, HW_IPU_DC_RL4_CH_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL4_CH_1_CLR(x, v) (HW_IPU_DC_RL4_CH_1_WR(x, HW_IPU_DC_RL4_CH_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL4_CH_1_TOG(x, v) (HW_IPU_DC_RL4_CH_1_WR(x, HW_IPU_DC_RL4_CH_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_1, field COD_NEW_DATA_PRIORITY_CHAN_1[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new data event (associated with channel #1) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1 (0) //!< Bit position for IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1.
|
|
#define BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1 (0x0000000f) //!< Bit mask for IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1) >> BP_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1.
|
|
#define BF_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1) & BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1(x, v) (HW_IPU_DC_RL4_CH_1_WR(x, (HW_IPU_DC_RL4_CH_1_RD(x) & ~BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1) | BF_IPU_DC_RL4_CH_1_COD_NEW_DATA_PRIORITY_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_1, field COD_NEW_DATA_START_CHAN_1[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #1)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1 (8) //!< Bit position for IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1.
|
|
#define BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1) >> BP_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1.
|
|
#define BF_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1) & BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_1 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1(x, v) (HW_IPU_DC_RL4_CH_1_WR(x, (HW_IPU_DC_RL4_CH_1_RD(x) & ~BM_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1) | BF_IPU_DC_RL4_CH_1_COD_NEW_DATA_START_CHAN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF_2 - DC Write Channel 2 Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF_2 - DC Write Channel 2 Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf_2_bitfields
|
|
{
|
|
unsigned W_SIZE_2 : 2; //!< [1:0] Word Size
|
|
unsigned PROG_DI_ID_2 : 1; //!< [2] This bit select the DI which a transaction associated with channel #2 can be performed to
|
|
unsigned PROG_DISP_ID_2 : 2; //!< [4:3] The field defines which one of the 4 displays is associated with channel #2.
|
|
unsigned PROG_CHAN_TYP_2 : 3; //!< [7:5] This field define the mode of operation of channel #2
|
|
unsigned CHAN_MASK_DEFAULT_2 : 1; //!< [8] Event mask bit for channel #2
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned PROG_START_TIME_2 : 11; //!< [26:16] This field defines the delay between display 's vertical synchronization pulse and the start time point of DC's channel 2 window.
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58038)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF_2(x) (*(volatile hw_ipu_dc_wr_ch_conf_2_t *) HW_IPU_DC_WR_CH_CONF_2_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF_2_RD(x) (HW_IPU_DC_WR_CH_CONF_2(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF_2_WR(x, v) (HW_IPU_DC_WR_CH_CONF_2(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF_2_SET(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, HW_IPU_DC_WR_CH_CONF_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_2_CLR(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_2_TOG(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, HW_IPU_DC_WR_CH_CONF_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_2, field W_SIZE_2[1:0] (RW)
|
|
*
|
|
* Word Size The data coming from the IDMAC is 32bit wide. This field defines the size of the word
|
|
* used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_2_W_SIZE_2 (0) //!< Bit position for IPU_DC_WR_CH_CONF_2_W_SIZE_2.
|
|
#define BM_IPU_DC_WR_CH_CONF_2_W_SIZE_2 (0x00000003) //!< Bit mask for IPU_DC_WR_CH_CONF_2_W_SIZE_2.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_2_W_SIZE_2 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_2_W_SIZE_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_2_W_SIZE_2) >> BP_IPU_DC_WR_CH_CONF_2_W_SIZE_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_2_W_SIZE_2.
|
|
#define BF_IPU_DC_WR_CH_CONF_2_W_SIZE_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_2_W_SIZE_2) & BM_IPU_DC_WR_CH_CONF_2_W_SIZE_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_2 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_2_W_SIZE_2(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, (HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~BM_IPU_DC_WR_CH_CONF_2_W_SIZE_2) | BF_IPU_DC_WR_CH_CONF_2_W_SIZE_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_2, field PROG_DI_ID_2[2] (RW)
|
|
*
|
|
* This bit select the DI which a transaction associated with channel #2 can be performed to
|
|
*
|
|
* Values:
|
|
* - 0 - DI #0
|
|
* - 1 - DI #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2 (2) //!< Bit position for IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2.
|
|
#define BM_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2 (0x00000004) //!< Bit mask for IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2) >> BP_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2.
|
|
#define BF_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2) & BM_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DI_ID_2 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, (HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~BM_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2) | BF_IPU_DC_WR_CH_CONF_2_PROG_DI_ID_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_2, field PROG_DISP_ID_2[4:3] (RW)
|
|
*
|
|
* The field defines which one of the 4 displays is associated with channel #2.
|
|
*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
|
|
* - 10 - display #2
|
|
* - 11 - display #3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2 (3) //!< Bit position for IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2.
|
|
#define BM_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2 (0x00000018) //!< Bit mask for IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2) >> BP_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2.
|
|
#define BF_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2) & BM_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DISP_ID_2 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, (HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~BM_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2) | BF_IPU_DC_WR_CH_CONF_2_PROG_DISP_ID_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_2, field PROG_CHAN_TYP_2[7:5] (RW)
|
|
*
|
|
* This field define the mode of operation of channel #2
|
|
*
|
|
* Values:
|
|
* - 000 - Disable
|
|
* - 001 - Reserved
|
|
* - 010 - Reserved
|
|
* - 100 - Normal mode without anti-tearing. For sync display this is the only mode allowed
|
|
* - 101 - Normal mode with anti-tearing
|
|
* - 110 - Reserved
|
|
* - 111 - Additional command channel is added to the flow handled by DC channel #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2 (5) //!< Bit position for IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2.
|
|
#define BM_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2 (0x000000e0) //!< Bit mask for IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2) >> BP_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2.
|
|
#define BF_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2) & BM_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_CHAN_TYP_2 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, (HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~BM_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2) | BF_IPU_DC_WR_CH_CONF_2_PROG_CHAN_TYP_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_2, field CHAN_MASK_DEFAULT_2[8] (RW)
|
|
*
|
|
* Event mask bit for channel #2 When more then one event is used during a flow (EOF, EOL, NL, NF,
|
|
* EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
|
|
* event
|
|
*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
|
* - 1 - All the events are used - no mask
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2 (8) //!< Bit position for IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2.
|
|
#define BM_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2 (0x00000100) //!< Bit mask for IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2.
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//! @brief Get value of IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2) >> BP_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2.
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#define BF_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2) & BM_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CHAN_MASK_DEFAULT_2 field to a new value.
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#define BW_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, (HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~BM_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2) | BF_IPU_DC_WR_CH_CONF_2_CHAN_MASK_DEFAULT_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_WR_CH_CONF_2, field PROG_START_TIME_2[26:16] (RW)
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*
|
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* This field defines the delay between display 's vertical synchronization pulse and the start time
|
|
* point of DC's channel 2 window. The delay is defined in pairs of rows. It is used for tearing
|
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* elimination
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*/
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//@{
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|
#define BP_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2 (16) //!< Bit position for IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2.
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#define BM_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2 (0x07ff0000) //!< Bit mask for IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2.
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//! @brief Get value of IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2) >> BP_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2.
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#define BF_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2) & BM_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PROG_START_TIME_2 field to a new value.
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#define BW_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2(x, v) (HW_IPU_DC_WR_CH_CONF_2_WR(x, (HW_IPU_DC_WR_CH_CONF_2_RD(x) & ~BM_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2) | BF_IPU_DC_WR_CH_CONF_2_PROG_START_TIME_2(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_WR_CH_ADDR_2 - DC Write Channel 2 Address Configuration Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_DC_WR_CH_ADDR_2 - DC Write Channel 2 Address Configuration Register (RW)
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*
|
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_wr_ch_addr_2
|
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{
|
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reg32_t U;
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struct _hw_ipu_dc_wr_ch_addr_2_bitfields
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{
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unsigned ST_ADDR_2 : 29; //!< [28:0] This field defines the start address within the display's memory space where the write transactions will be done to for channel #2.
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unsigned RESERVED0 : 3; //!< [31:29] Reserved.
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} B;
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|
} hw_ipu_dc_wr_ch_addr_2_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_ADDR_2 register
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|
*/
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|
//@{
|
|
#define HW_IPU_DC_WR_CH_ADDR_2_ADDR(x) (REGS_IPU_BASE(x) + 0x5803c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_WR_CH_ADDR_2(x) (*(volatile hw_ipu_dc_wr_ch_addr_2_t *) HW_IPU_DC_WR_CH_ADDR_2_ADDR(x))
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#define HW_IPU_DC_WR_CH_ADDR_2_RD(x) (HW_IPU_DC_WR_CH_ADDR_2(x).U)
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#define HW_IPU_DC_WR_CH_ADDR_2_WR(x, v) (HW_IPU_DC_WR_CH_ADDR_2(x).U = (v))
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|
#define HW_IPU_DC_WR_CH_ADDR_2_SET(x, v) (HW_IPU_DC_WR_CH_ADDR_2_WR(x, HW_IPU_DC_WR_CH_ADDR_2_RD(x) | (v)))
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#define HW_IPU_DC_WR_CH_ADDR_2_CLR(x, v) (HW_IPU_DC_WR_CH_ADDR_2_WR(x, HW_IPU_DC_WR_CH_ADDR_2_RD(x) & ~(v)))
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#define HW_IPU_DC_WR_CH_ADDR_2_TOG(x, v) (HW_IPU_DC_WR_CH_ADDR_2_WR(x, HW_IPU_DC_WR_CH_ADDR_2_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_ADDR_2 bitfields
|
|
*/
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/*! @name Register IPU_DC_WR_CH_ADDR_2, field ST_ADDR_2[28:0] (RW)
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|
*
|
|
* This field defines the start address within the display's memory space where the write
|
|
* transactions will be done to for channel #2.
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|
*/
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|
//@{
|
|
#define BP_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2 (0) //!< Bit position for IPU_DC_WR_CH_ADDR_2_ST_ADDR_2.
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|
#define BM_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2 (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_ADDR_2_ST_ADDR_2.
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|
|
//! @brief Get value of IPU_DC_WR_CH_ADDR_2_ST_ADDR_2 from a register value.
|
|
#define BG_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2) >> BP_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2)
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|
//! @brief Format value for bitfield IPU_DC_WR_CH_ADDR_2_ST_ADDR_2.
|
|
#define BF_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2) & BM_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ST_ADDR_2 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2(x, v) (HW_IPU_DC_WR_CH_ADDR_2_WR(x, (HW_IPU_DC_WR_CH_ADDR_2_RD(x) & ~BM_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2) | BF_IPU_DC_WR_CH_ADDR_2_ST_ADDR_2(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL0_CH_2 - DC Routine Link Register 0 Channel 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL0_CH_2 - DC Routine Link Register 0 Channel 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl0_ch_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl0_ch_2_bitfields
|
|
{
|
|
unsigned COD_NF_PRIORITY_CHAN_2 : 4; //!< [3:0] This field defines the priority of the new frame event (associated with channel #2)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NF_START_CHAN_2 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new frame event resides (associated with channel #2)
|
|
unsigned COD_NL_PRIORITY_CHAN_2 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #2)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NL_START_CHAN_2 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new line event resides (associated with channel #2)
|
|
} B;
|
|
} hw_ipu_dc_rl0_ch_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL0_CH_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL0_CH_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58040)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL0_CH_2(x) (*(volatile hw_ipu_dc_rl0_ch_2_t *) HW_IPU_DC_RL0_CH_2_ADDR(x))
|
|
#define HW_IPU_DC_RL0_CH_2_RD(x) (HW_IPU_DC_RL0_CH_2(x).U)
|
|
#define HW_IPU_DC_RL0_CH_2_WR(x, v) (HW_IPU_DC_RL0_CH_2(x).U = (v))
|
|
#define HW_IPU_DC_RL0_CH_2_SET(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, HW_IPU_DC_RL0_CH_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL0_CH_2_CLR(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, HW_IPU_DC_RL0_CH_2_RD(x) & ~(v)))
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|
#define HW_IPU_DC_RL0_CH_2_TOG(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, HW_IPU_DC_RL0_CH_2_RD(x) ^ (v)))
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|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL0_CH_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_2, field COD_NF_PRIORITY_CHAN_2[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new frame event (associated with channel #2) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2 (0) //!< Bit position for IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2.
|
|
#define BM_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2 (0x0000000f) //!< Bit mask for IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2) >> BP_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2.
|
|
#define BF_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2) & BM_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, (HW_IPU_DC_RL0_CH_2_RD(x) & ~BM_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2) | BF_IPU_DC_RL0_CH_2_COD_NF_PRIORITY_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_2, field COD_NF_START_CHAN_2[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new frame event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2 (8) //!< Bit position for IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2.
|
|
#define BM_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2 (0x0000ff00) //!< Bit mask for IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2) >> BP_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2.
|
|
#define BF_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2) & BM_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, (HW_IPU_DC_RL0_CH_2_RD(x) & ~BM_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2) | BF_IPU_DC_RL0_CH_2_COD_NF_START_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_2, field COD_NL_PRIORITY_CHAN_2[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #2) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2 (16) //!< Bit position for IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2.
|
|
#define BM_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2 (0x000f0000) //!< Bit mask for IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2) >> BP_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2.
|
|
#define BF_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2) & BM_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, (HW_IPU_DC_RL0_CH_2_RD(x) & ~BM_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2) | BF_IPU_DC_RL0_CH_2_COD_NL_PRIORITY_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_2, field COD_NL_START_CHAN_2[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new line event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2 (24) //!< Bit position for IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2.
|
|
#define BM_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2 (0xff000000) //!< Bit mask for IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2) >> BP_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2.
|
|
#define BF_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2) & BM_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2(x, v) (HW_IPU_DC_RL0_CH_2_WR(x, (HW_IPU_DC_RL0_CH_2_RD(x) & ~BM_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2) | BF_IPU_DC_RL0_CH_2_COD_NL_START_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL1_CH_2 - DC Routine Link Register 1 Channel 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_2 - DC Routine Link Register 1 Channel 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl1_ch_2_bitfields
|
|
{
|
|
unsigned COD_EOF_PRIORITY_CHAN_2 : 4; //!< [3:0] This field defines the priority of the end of frame event (associated with channel #2)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOF_START_CHAN_2 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of frame event resides (associated with channel #2)
|
|
unsigned COD_NFIELD_PRIORITY_CHAN_2 : 4; //!< [19:16] This field defines the priority of the new field event (associated with channel #2)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NFIELD_START_CHAN_2 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new field event resides (associated with channel #2)
|
|
} B;
|
|
} hw_ipu_dc_rl1_ch_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_2 register
|
|
*/
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//@{
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#define HW_IPU_DC_RL1_CH_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58044)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL1_CH_2(x) (*(volatile hw_ipu_dc_rl1_ch_2_t *) HW_IPU_DC_RL1_CH_2_ADDR(x))
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#define HW_IPU_DC_RL1_CH_2_RD(x) (HW_IPU_DC_RL1_CH_2(x).U)
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#define HW_IPU_DC_RL1_CH_2_WR(x, v) (HW_IPU_DC_RL1_CH_2(x).U = (v))
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#define HW_IPU_DC_RL1_CH_2_SET(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, HW_IPU_DC_RL1_CH_2_RD(x) | (v)))
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#define HW_IPU_DC_RL1_CH_2_CLR(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, HW_IPU_DC_RL1_CH_2_RD(x) & ~(v)))
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#define HW_IPU_DC_RL1_CH_2_TOG(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, HW_IPU_DC_RL1_CH_2_RD(x) ^ (v)))
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#endif
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//@}
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/*
|
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* constants & macros for individual IPU_DC_RL1_CH_2 bitfields
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*/
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/*! @name Register IPU_DC_RL1_CH_2, field COD_EOF_PRIORITY_CHAN_2[3:0] (RW)
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*
|
|
* This field defines the priority of the end of frame event (associated with channel #2) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
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|
* - 0010 - Priority #2
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* - 1101 - Priority #13 (highest)
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* - 1110 - Reserved
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* - 1111 - Reserved
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*/
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|
//@{
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#define BP_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2 (0) //!< Bit position for IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2.
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#define BM_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2.
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//! @brief Get value of IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2 from a register value.
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#define BG_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2) >> BP_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2)
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//! @brief Format value for bitfield IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2.
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#define BF_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2) & BM_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_EOF_PRIORITY_CHAN_2 field to a new value.
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#define BW_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, (HW_IPU_DC_RL1_CH_2_RD(x) & ~BM_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2) | BF_IPU_DC_RL1_CH_2_COD_EOF_PRIORITY_CHAN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL1_CH_2, field COD_EOF_START_CHAN_2[15:8] (RW)
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*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of frame event resides (associated with channel #2)
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|
*/
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|
//@{
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|
#define BP_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2 (8) //!< Bit position for IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2.
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#define BM_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2.
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//! @brief Get value of IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2 from a register value.
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#define BG_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2) >> BP_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2)
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//! @brief Format value for bitfield IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2.
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|
#define BF_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2) & BM_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, (HW_IPU_DC_RL1_CH_2_RD(x) & ~BM_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2) | BF_IPU_DC_RL1_CH_2_COD_EOF_START_CHAN_2(v)))
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|
#endif
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|
//@}
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|
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/*! @name Register IPU_DC_RL1_CH_2, field COD_NFIELD_PRIORITY_CHAN_2[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #2) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2 (16) //!< Bit position for IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2.
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|
#define BM_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2 (0x000f0000) //!< Bit mask for IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2.
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//! @brief Get value of IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2 from a register value.
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|
#define BG_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2) >> BP_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2.
|
|
#define BF_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2) & BM_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, (HW_IPU_DC_RL1_CH_2_RD(x) & ~BM_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2) | BF_IPU_DC_RL1_CH_2_COD_NFIELD_PRIORITY_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_2, field COD_NFIELD_START_CHAN_2[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new field event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2 (24) //!< Bit position for IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2.
|
|
#define BM_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2.
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|
|
|
//! @brief Get value of IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2) >> BP_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2.
|
|
#define BF_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2) & BM_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2(x, v) (HW_IPU_DC_RL1_CH_2_WR(x, (HW_IPU_DC_RL1_CH_2_RD(x) & ~BM_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2) | BF_IPU_DC_RL1_CH_2_COD_NFIELD_START_CHAN_2(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_2 - DC Routine Link Register 2 Channel 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_2 - DC Routine Link Register 2 Channel 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_2_bitfields
|
|
{
|
|
unsigned COD_EOL_PRIORITY_CHAN_2 : 4; //!< [3:0] This field defines the priority of the end of line event (associated with channel #2)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOL_START_CHAN_2 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of line event resides (associated with channel #2)
|
|
unsigned COD_EOFIELD_PRIORITY_CHAN_2 : 4; //!< [19:16] This field defines the priority of the end of field event (associated with channel #2)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_EOFIELD_START_CHAN_2 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the end of field event resides (associated with channel #2)
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58048)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_2(x) (*(volatile hw_ipu_dc_rl2_ch_2_t *) HW_IPU_DC_RL2_CH_2_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_2_RD(x) (HW_IPU_DC_RL2_CH_2(x).U)
|
|
#define HW_IPU_DC_RL2_CH_2_WR(x, v) (HW_IPU_DC_RL2_CH_2(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_2_SET(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, HW_IPU_DC_RL2_CH_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_2_CLR(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, HW_IPU_DC_RL2_CH_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_2_TOG(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, HW_IPU_DC_RL2_CH_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_2, field COD_EOL_PRIORITY_CHAN_2[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the end of line event (associated with channel #2) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2 (0) //!< Bit position for IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2.
|
|
#define BM_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2) >> BP_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2.
|
|
#define BF_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2) & BM_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, (HW_IPU_DC_RL2_CH_2_RD(x) & ~BM_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2) | BF_IPU_DC_RL2_CH_2_COD_EOL_PRIORITY_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_2, field COD_EOL_START_CHAN_2[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of line event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2 (8) //!< Bit position for IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2.
|
|
#define BM_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2) >> BP_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2.
|
|
#define BF_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2) & BM_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, (HW_IPU_DC_RL2_CH_2_RD(x) & ~BM_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2) | BF_IPU_DC_RL2_CH_2_COD_EOL_START_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_2, field COD_EOFIELD_PRIORITY_CHAN_2[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the end of field event (associated with channel #2) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2 (16) //!< Bit position for IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2.
|
|
#define BM_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2 (0x000f0000) //!< Bit mask for IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2) >> BP_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2.
|
|
#define BF_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2) & BM_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, (HW_IPU_DC_RL2_CH_2_RD(x) & ~BM_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2) | BF_IPU_DC_RL2_CH_2_COD_EOFIELD_PRIORITY_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_2, field COD_EOFIELD_START_CHAN_2[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of field event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2 (24) //!< Bit position for IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2.
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#define BM_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2.
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//! @brief Get value of IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2 from a register value.
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#define BG_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2) >> BP_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2)
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//! @brief Format value for bitfield IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2.
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#define BF_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2) & BM_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_EOFIELD_START_CHAN_2 field to a new value.
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#define BW_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2(x, v) (HW_IPU_DC_RL2_CH_2_WR(x, (HW_IPU_DC_RL2_CH_2_RD(x) & ~BM_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2) | BF_IPU_DC_RL2_CH_2_COD_EOFIELD_START_CHAN_2(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_RL3_CH_2 - DC Routine Link Register 3 Channel 2
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DC_RL3_CH_2 - DC Routine Link Register 3 Channel 2 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_rl3_ch_2
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{
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reg32_t U;
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struct _hw_ipu_dc_rl3_ch_2_bitfields
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{
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unsigned COD_NEW_ADDR_PRIORITY_CHAN_2 : 4; //!< [3:0] This field defines the priority of the end of line event (associated with channel #2)
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unsigned RESERVED0 : 4; //!< [7:4] Reserved.
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unsigned COD_NEW_ADDR_START_CHAN_2 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #2)
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unsigned COD_NEW_CHAN_PRIORITY_CHAN_2 : 4; //!< [19:16] This field defines the priority of the end of line event (associated with channel #2)
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unsigned RESERVED1 : 4; //!< [23:20] Reserved.
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unsigned COD_NEW_CHAN_START_CHAN_2 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #2)
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} B;
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} hw_ipu_dc_rl3_ch_2_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DC_RL3_CH_2 register
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*/
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//@{
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#define HW_IPU_DC_RL3_CH_2_ADDR(x) (REGS_IPU_BASE(x) + 0x5804c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL3_CH_2(x) (*(volatile hw_ipu_dc_rl3_ch_2_t *) HW_IPU_DC_RL3_CH_2_ADDR(x))
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#define HW_IPU_DC_RL3_CH_2_RD(x) (HW_IPU_DC_RL3_CH_2(x).U)
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#define HW_IPU_DC_RL3_CH_2_WR(x, v) (HW_IPU_DC_RL3_CH_2(x).U = (v))
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#define HW_IPU_DC_RL3_CH_2_SET(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, HW_IPU_DC_RL3_CH_2_RD(x) | (v)))
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#define HW_IPU_DC_RL3_CH_2_CLR(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, HW_IPU_DC_RL3_CH_2_RD(x) & ~(v)))
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#define HW_IPU_DC_RL3_CH_2_TOG(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, HW_IPU_DC_RL3_CH_2_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DC_RL3_CH_2 bitfields
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*/
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/*! @name Register IPU_DC_RL3_CH_2, field COD_NEW_ADDR_PRIORITY_CHAN_2[3:0] (RW)
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*
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* This field defines the priority of the end of line event (associated with channel #2) The
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* priority between the events should be set to a unique value. i.e. two events must not have the
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* same priority (except 0000 - disable)
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*
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* Values:
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* - 0000 - disable
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* - 0001 - Priority #1 (lowest)
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* - 0010 - Priority #2
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* - 1101 - Priority #13 (highest)
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* - 1110 - Reserved
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* - 1111 - Reserved
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*/
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//@{
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#define BP_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2 (0) //!< Bit position for IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2.
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#define BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2.
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//! @brief Get value of IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2 from a register value.
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#define BG_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2) >> BP_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2.
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#define BF_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2) & BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_2 field to a new value.
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#define BW_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, (HW_IPU_DC_RL3_CH_2_RD(x) & ~BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2) | BF_IPU_DC_RL3_CH_2_COD_NEW_ADDR_PRIORITY_CHAN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL3_CH_2, field COD_NEW_ADDR_START_CHAN_2[15:8] (RW)
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*
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|
* This field is a pointer to the address within the microcode memory where the routine that handles
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* the new address event resides (associated with channel #2)
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|
*/
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//@{
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#define BP_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2 (8) //!< Bit position for IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2.
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#define BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2.
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//! @brief Get value of IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2 from a register value.
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#define BG_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2) >> BP_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2.
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#define BF_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2) & BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2)
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|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_ADDR_START_CHAN_2 field to a new value.
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#define BW_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, (HW_IPU_DC_RL3_CH_2_RD(x) & ~BM_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2) | BF_IPU_DC_RL3_CH_2_COD_NEW_ADDR_START_CHAN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL3_CH_2, field COD_NEW_CHAN_PRIORITY_CHAN_2[19:16] (RW)
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|
*
|
|
* This field defines the priority of the end of line event (associated with channel #2) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
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|
* - 0001 - Priority #1 (lowest)
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|
* - 0010 - Priority #2
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* - 1101 - Priority #13 (highest)
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* - 1110 - Reserved
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* - 1111 - Reserved
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*/
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//@{
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|
#define BP_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2 (16) //!< Bit position for IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2.
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#define BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2 (0x000f0000) //!< Bit mask for IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2.
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//! @brief Get value of IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2 from a register value.
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#define BG_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2) >> BP_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2.
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#define BF_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2) & BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2)
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|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, (HW_IPU_DC_RL3_CH_2_RD(x) & ~BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2) | BF_IPU_DC_RL3_CH_2_COD_NEW_CHAN_PRIORITY_CHAN_2(v)))
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#endif
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|
//@}
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|
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|
/*! @name Register IPU_DC_RL3_CH_2, field COD_NEW_CHAN_START_CHAN_2[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2 (24) //!< Bit position for IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2.
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|
#define BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2.
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|
//! @brief Get value of IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2 from a register value.
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|
#define BG_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2) >> BP_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2)
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|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2.
|
|
#define BF_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2) & BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2(x, v) (HW_IPU_DC_RL3_CH_2_WR(x, (HW_IPU_DC_RL3_CH_2_RD(x) & ~BM_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2) | BF_IPU_DC_RL3_CH_2_COD_NEW_CHAN_START_CHAN_2(v)))
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|
#endif
|
|
//@}
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|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL4_CH_2 - DC Routine Link Register 4 Channel 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL4_CH_2 - DC Routine Link Register 4 Channel 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl4_ch_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl4_ch_2_bitfields
|
|
{
|
|
unsigned COD_NEW_DATA_PRIORITY_CHAN_2 : 4; //!< [3:0] This field defines the priority of the end of line event (associated with channel #2)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_2 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #2)
|
|
unsigned RESERVED1 : 16; //!< [31:16] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_rl4_ch_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL4_CH_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL4_CH_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58050)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL4_CH_2(x) (*(volatile hw_ipu_dc_rl4_ch_2_t *) HW_IPU_DC_RL4_CH_2_ADDR(x))
|
|
#define HW_IPU_DC_RL4_CH_2_RD(x) (HW_IPU_DC_RL4_CH_2(x).U)
|
|
#define HW_IPU_DC_RL4_CH_2_WR(x, v) (HW_IPU_DC_RL4_CH_2(x).U = (v))
|
|
#define HW_IPU_DC_RL4_CH_2_SET(x, v) (HW_IPU_DC_RL4_CH_2_WR(x, HW_IPU_DC_RL4_CH_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL4_CH_2_CLR(x, v) (HW_IPU_DC_RL4_CH_2_WR(x, HW_IPU_DC_RL4_CH_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL4_CH_2_TOG(x, v) (HW_IPU_DC_RL4_CH_2_WR(x, HW_IPU_DC_RL4_CH_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_2, field COD_NEW_DATA_PRIORITY_CHAN_2[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the end of line event (associated with channel #2) The
|
|
* priority between the events should be set to a unique value. i.e. two events must not have the
|
|
* same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2 (0) //!< Bit position for IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2.
|
|
#define BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2 (0x0000000f) //!< Bit mask for IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2) >> BP_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2.
|
|
#define BF_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2) & BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2(x, v) (HW_IPU_DC_RL4_CH_2_WR(x, (HW_IPU_DC_RL4_CH_2_RD(x) & ~BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2) | BF_IPU_DC_RL4_CH_2_COD_NEW_DATA_PRIORITY_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_2, field COD_NEW_DATA_START_CHAN_2[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #2)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2 (8) //!< Bit position for IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2.
|
|
#define BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2) >> BP_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2.
|
|
#define BF_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2) & BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_2 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2(x, v) (HW_IPU_DC_RL4_CH_2_WR(x, (HW_IPU_DC_RL4_CH_2_RD(x) & ~BM_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2) | BF_IPU_DC_RL4_CH_2_COD_NEW_DATA_START_CHAN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_CMD_CH_CONF_3 - DC Command Channel 3 Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_CMD_CH_CONF_3 - DC Command Channel 3 Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_cmd_ch_conf_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_cmd_ch_conf_3_bitfields
|
|
{
|
|
unsigned W_SIZE_3 : 2; //!< [1:0] Word Size associated with channel #3
|
|
unsigned RESERVED0 : 6; //!< [7:2] Reserved.
|
|
unsigned COD_CMND_START_CHAN_RS0_3 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the command start event resides (associated with channel #3); This field is relevant when RS is equal to 0
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_CMND_START_CHAN_RS1_3 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the command start event resides (associated with channel #3); This field is relevant when RS is equal to 1
|
|
} B;
|
|
} hw_ipu_dc_cmd_ch_conf_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_CMD_CH_CONF_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_CMD_CH_CONF_3_ADDR(x) (REGS_IPU_BASE(x) + 0x58054)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_CMD_CH_CONF_3(x) (*(volatile hw_ipu_dc_cmd_ch_conf_3_t *) HW_IPU_DC_CMD_CH_CONF_3_ADDR(x))
|
|
#define HW_IPU_DC_CMD_CH_CONF_3_RD(x) (HW_IPU_DC_CMD_CH_CONF_3(x).U)
|
|
#define HW_IPU_DC_CMD_CH_CONF_3_WR(x, v) (HW_IPU_DC_CMD_CH_CONF_3(x).U = (v))
|
|
#define HW_IPU_DC_CMD_CH_CONF_3_SET(x, v) (HW_IPU_DC_CMD_CH_CONF_3_WR(x, HW_IPU_DC_CMD_CH_CONF_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_CMD_CH_CONF_3_CLR(x, v) (HW_IPU_DC_CMD_CH_CONF_3_WR(x, HW_IPU_DC_CMD_CH_CONF_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_CMD_CH_CONF_3_TOG(x, v) (HW_IPU_DC_CMD_CH_CONF_3_WR(x, HW_IPU_DC_CMD_CH_CONF_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_CMD_CH_CONF_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_CMD_CH_CONF_3, field W_SIZE_3[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #3 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_CMD_CH_CONF_3_W_SIZE_3 (0) //!< Bit position for IPU_DC_CMD_CH_CONF_3_W_SIZE_3.
|
|
#define BM_IPU_DC_CMD_CH_CONF_3_W_SIZE_3 (0x00000003) //!< Bit mask for IPU_DC_CMD_CH_CONF_3_W_SIZE_3.
|
|
|
|
//! @brief Get value of IPU_DC_CMD_CH_CONF_3_W_SIZE_3 from a register value.
|
|
#define BG_IPU_DC_CMD_CH_CONF_3_W_SIZE_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_CMD_CH_CONF_3_W_SIZE_3) >> BP_IPU_DC_CMD_CH_CONF_3_W_SIZE_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_CMD_CH_CONF_3_W_SIZE_3.
|
|
#define BF_IPU_DC_CMD_CH_CONF_3_W_SIZE_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_CMD_CH_CONF_3_W_SIZE_3) & BM_IPU_DC_CMD_CH_CONF_3_W_SIZE_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_3 field to a new value.
|
|
#define BW_IPU_DC_CMD_CH_CONF_3_W_SIZE_3(x, v) (HW_IPU_DC_CMD_CH_CONF_3_WR(x, (HW_IPU_DC_CMD_CH_CONF_3_RD(x) & ~BM_IPU_DC_CMD_CH_CONF_3_W_SIZE_3) | BF_IPU_DC_CMD_CH_CONF_3_W_SIZE_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_CMD_CH_CONF_3, field COD_CMND_START_CHAN_RS0_3[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the command start event resides (associated with channel #3); This field is relevant when RS is
|
|
* equal to 0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3 (8) //!< Bit position for IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3.
|
|
#define BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3 (0x0000ff00) //!< Bit mask for IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3.
|
|
|
|
//! @brief Get value of IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3 from a register value.
|
|
#define BG_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3) >> BP_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3.
|
|
#define BF_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3) & BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_CMND_START_CHAN_RS0_3 field to a new value.
|
|
#define BW_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3(x, v) (HW_IPU_DC_CMD_CH_CONF_3_WR(x, (HW_IPU_DC_CMD_CH_CONF_3_RD(x) & ~BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3) | BF_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS0_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_CMD_CH_CONF_3, field COD_CMND_START_CHAN_RS1_3[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the command start event resides (associated with channel #3); This field is relevant when RS is
|
|
* equal to 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3 (24) //!< Bit position for IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3.
|
|
#define BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3 (0xff000000) //!< Bit mask for IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3.
|
|
|
|
//! @brief Get value of IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3 from a register value.
|
|
#define BG_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3) >> BP_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3.
|
|
#define BF_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3) & BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_CMND_START_CHAN_RS1_3 field to a new value.
|
|
#define BW_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3(x, v) (HW_IPU_DC_CMD_CH_CONF_3_WR(x, (HW_IPU_DC_CMD_CH_CONF_3_RD(x) & ~BM_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3) | BF_IPU_DC_CMD_CH_CONF_3_COD_CMND_START_CHAN_RS1_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_CMD_CH_CONF_4 - DC Command Channel 4 Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_CMD_CH_CONF_4 - DC Command Channel 4 Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_cmd_ch_conf_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_cmd_ch_conf_4_bitfields
|
|
{
|
|
unsigned W_SIZE_4 : 2; //!< [1:0] Word Size associated with channel #4
|
|
unsigned RESERVED0 : 6; //!< [7:2] Reserved.
|
|
unsigned COD_CMND_START_CHAN_RS0_4 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the command start event resides (associated with channel #4); This field is relevant when RS is equal to 0
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_CMND_START_CHAN_RS1_4 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the command start event resides (associated with channel #4); This field is relevant when RS is equal to 1
|
|
} B;
|
|
} hw_ipu_dc_cmd_ch_conf_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_CMD_CH_CONF_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_CMD_CH_CONF_4_ADDR(x) (REGS_IPU_BASE(x) + 0x58058)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_CMD_CH_CONF_4(x) (*(volatile hw_ipu_dc_cmd_ch_conf_4_t *) HW_IPU_DC_CMD_CH_CONF_4_ADDR(x))
|
|
#define HW_IPU_DC_CMD_CH_CONF_4_RD(x) (HW_IPU_DC_CMD_CH_CONF_4(x).U)
|
|
#define HW_IPU_DC_CMD_CH_CONF_4_WR(x, v) (HW_IPU_DC_CMD_CH_CONF_4(x).U = (v))
|
|
#define HW_IPU_DC_CMD_CH_CONF_4_SET(x, v) (HW_IPU_DC_CMD_CH_CONF_4_WR(x, HW_IPU_DC_CMD_CH_CONF_4_RD(x) | (v)))
|
|
#define HW_IPU_DC_CMD_CH_CONF_4_CLR(x, v) (HW_IPU_DC_CMD_CH_CONF_4_WR(x, HW_IPU_DC_CMD_CH_CONF_4_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_CMD_CH_CONF_4_TOG(x, v) (HW_IPU_DC_CMD_CH_CONF_4_WR(x, HW_IPU_DC_CMD_CH_CONF_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_CMD_CH_CONF_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_CMD_CH_CONF_4, field W_SIZE_4[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #4 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_CMD_CH_CONF_4_W_SIZE_4 (0) //!< Bit position for IPU_DC_CMD_CH_CONF_4_W_SIZE_4.
|
|
#define BM_IPU_DC_CMD_CH_CONF_4_W_SIZE_4 (0x00000003) //!< Bit mask for IPU_DC_CMD_CH_CONF_4_W_SIZE_4.
|
|
|
|
//! @brief Get value of IPU_DC_CMD_CH_CONF_4_W_SIZE_4 from a register value.
|
|
#define BG_IPU_DC_CMD_CH_CONF_4_W_SIZE_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_CMD_CH_CONF_4_W_SIZE_4) >> BP_IPU_DC_CMD_CH_CONF_4_W_SIZE_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_CMD_CH_CONF_4_W_SIZE_4.
|
|
#define BF_IPU_DC_CMD_CH_CONF_4_W_SIZE_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_CMD_CH_CONF_4_W_SIZE_4) & BM_IPU_DC_CMD_CH_CONF_4_W_SIZE_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_4 field to a new value.
|
|
#define BW_IPU_DC_CMD_CH_CONF_4_W_SIZE_4(x, v) (HW_IPU_DC_CMD_CH_CONF_4_WR(x, (HW_IPU_DC_CMD_CH_CONF_4_RD(x) & ~BM_IPU_DC_CMD_CH_CONF_4_W_SIZE_4) | BF_IPU_DC_CMD_CH_CONF_4_W_SIZE_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_CMD_CH_CONF_4, field COD_CMND_START_CHAN_RS0_4[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the command start event resides (associated with channel #4); This field is relevant when RS is
|
|
* equal to 0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4 (8) //!< Bit position for IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4.
|
|
#define BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4 (0x0000ff00) //!< Bit mask for IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4.
|
|
|
|
//! @brief Get value of IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4 from a register value.
|
|
#define BG_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4) >> BP_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4.
|
|
#define BF_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4) & BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_CMND_START_CHAN_RS0_4 field to a new value.
|
|
#define BW_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4(x, v) (HW_IPU_DC_CMD_CH_CONF_4_WR(x, (HW_IPU_DC_CMD_CH_CONF_4_RD(x) & ~BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4) | BF_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS0_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_CMD_CH_CONF_4, field COD_CMND_START_CHAN_RS1_4[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the command start event resides (associated with channel #4); This field is relevant when RS is
|
|
* equal to 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4 (24) //!< Bit position for IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4.
|
|
#define BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4 (0xff000000) //!< Bit mask for IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4.
|
|
|
|
//! @brief Get value of IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4 from a register value.
|
|
#define BG_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4) >> BP_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4.
|
|
#define BF_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4) & BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_CMND_START_CHAN_RS1_4 field to a new value.
|
|
#define BW_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4(x, v) (HW_IPU_DC_CMD_CH_CONF_4_WR(x, (HW_IPU_DC_CMD_CH_CONF_4_RD(x) & ~BM_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4) | BF_IPU_DC_CMD_CH_CONF_4_COD_CMND_START_CHAN_RS1_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF_5 - DC Write Channel 5Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF_5 - DC Write Channel 5Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf_5_bitfields
|
|
{
|
|
unsigned W_SIZE_5 : 2; //!< [1:0] Word Size associated with channel #5
|
|
unsigned PROG_DI_ID_5 : 1; //!< [2] This bit select the DI which a transaction associated with channel #5 can be performed to.
|
|
unsigned PROG_DISP_ID_5 : 2; //!< [4:3] The field defines which one of the 4 displays is associated with channel #5.
|
|
unsigned PROG_CHAN_TYP_5 : 3; //!< [7:5] This field define the mode of operation of channel #5
|
|
unsigned CHAN_MASK_DEFAULT_5 : 1; //!< [8] Event mask bit for channel #5
|
|
unsigned FIELD_MODE_5 : 1; //!< [9] Field mode bit for channel #5
|
|
unsigned RESERVED0 : 6; //!< [15:10] Reserved.
|
|
unsigned PROG_START_TIME_5 : 11; //!< [26:16] This field defines the delay between display 's vertical synchronization pulse and the start time point of DC's channel 5 window.
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF_5_ADDR(x) (REGS_IPU_BASE(x) + 0x5805c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF_5(x) (*(volatile hw_ipu_dc_wr_ch_conf_5_t *) HW_IPU_DC_WR_CH_CONF_5_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF_5_RD(x) (HW_IPU_DC_WR_CH_CONF_5(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF_5_WR(x, v) (HW_IPU_DC_WR_CH_CONF_5(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF_5_SET(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, HW_IPU_DC_WR_CH_CONF_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_5_CLR(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_5_TOG(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, HW_IPU_DC_WR_CH_CONF_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field W_SIZE_5[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #5 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_W_SIZE_5 (0) //!< Bit position for IPU_DC_WR_CH_CONF_5_W_SIZE_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_W_SIZE_5 (0x00000003) //!< Bit mask for IPU_DC_WR_CH_CONF_5_W_SIZE_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_W_SIZE_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_W_SIZE_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_W_SIZE_5) >> BP_IPU_DC_WR_CH_CONF_5_W_SIZE_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_W_SIZE_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_W_SIZE_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_W_SIZE_5) & BM_IPU_DC_WR_CH_CONF_5_W_SIZE_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_W_SIZE_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_W_SIZE_5) | BF_IPU_DC_WR_CH_CONF_5_W_SIZE_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field PROG_DI_ID_5[2] (RW)
|
|
*
|
|
* This bit select the DI which a transaction associated with channel #5 can be performed to. When
|
|
* channel 28 is connected to DI0, channel 23 must be connected to DI1 even if ch23 is not used.
|
|
* This is done by writing 1 to this bit.
|
|
*
|
|
* Values:
|
|
* - 0 - DI #0
|
|
* - 1 - DI #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5 (2) //!< Bit position for IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5 (0x00000004) //!< Bit mask for IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5) >> BP_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5) & BM_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DI_ID_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5) | BF_IPU_DC_WR_CH_CONF_5_PROG_DI_ID_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field PROG_DISP_ID_5[4:3] (RW)
|
|
*
|
|
* The field defines which one of the 4 displays is associated with channel #5.
|
|
*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
|
|
* - 10 - display #2
|
|
* - 11 - display #3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5 (3) //!< Bit position for IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5 (0x00000018) //!< Bit mask for IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5) >> BP_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5) & BM_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DISP_ID_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5) | BF_IPU_DC_WR_CH_CONF_5_PROG_DISP_ID_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field PROG_CHAN_TYP_5[7:5] (RW)
|
|
*
|
|
* This field define the mode of operation of channel #5
|
|
*
|
|
* Values:
|
|
* - 000 - Disable
|
|
* - 001 - Reserved
|
|
* - 010 - Reserved
|
|
* - 100 - Normal mode without anti-tearing. For sync display this is the only mode allowed
|
|
* - 101 - Normal mode with anti-tearing
|
|
* - 110 - Reserved
|
|
* - 111 - Additional command channel is added to the flow handled by DC channel #5
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5 (5) //!< Bit position for IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5 (0x000000e0) //!< Bit mask for IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5) >> BP_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5) & BM_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_CHAN_TYP_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5) | BF_IPU_DC_WR_CH_CONF_5_PROG_CHAN_TYP_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field CHAN_MASK_DEFAULT_5[8] (RW)
|
|
*
|
|
* Event mask bit for channel #5 When more then one event is used during a flow (EOF, EOL, NL, NF,
|
|
* EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
|
|
* event
|
|
*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
|
* - 1 - All the events are used - no mask
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5 (8) //!< Bit position for IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5 (0x00000100) //!< Bit mask for IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5) >> BP_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5) & BM_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CHAN_MASK_DEFAULT_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5) | BF_IPU_DC_WR_CH_CONF_5_CHAN_MASK_DEFAULT_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field FIELD_MODE_5[9] (RW)
|
|
*
|
|
* Field mode bit for channel #5 This bit defines if the channel works in field mode or frame mode;
|
|
* This bit is relevant if the flow is sync flow
|
|
*
|
|
* Values:
|
|
* - 0 - Frame mode
|
|
* - 1 - Field mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5 (9) //!< Bit position for IPU_DC_WR_CH_CONF_5_FIELD_MODE_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5 (0x00000200) //!< Bit mask for IPU_DC_WR_CH_CONF_5_FIELD_MODE_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_FIELD_MODE_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5) >> BP_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_FIELD_MODE_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5) & BM_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the FIELD_MODE_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5) | BF_IPU_DC_WR_CH_CONF_5_FIELD_MODE_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_5, field PROG_START_TIME_5[26:16] (RW)
|
|
*
|
|
* This field defines the delay between display 's vertical synchronization pulse and the start time
|
|
* point of DC's channel 5 window. The delay is defined in pairs of rows. It is used for tearing
|
|
* elimination
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5 (16) //!< Bit position for IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5.
|
|
#define BM_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5 (0x07ff0000) //!< Bit mask for IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5) >> BP_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5.
|
|
#define BF_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5) & BM_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_START_TIME_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5(x, v) (HW_IPU_DC_WR_CH_CONF_5_WR(x, (HW_IPU_DC_WR_CH_CONF_5_RD(x) & ~BM_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5) | BF_IPU_DC_WR_CH_CONF_5_PROG_START_TIME_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_ADDR_5 - DC Write Channel 5Address Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_ADDR_5 - DC Write Channel 5Address Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_addr_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_addr_5_bitfields
|
|
{
|
|
unsigned ST_ADDR_5 : 29; //!< [28:0] This field defines the start address within the display's memory space where the write transactions will be done to for channel #5.
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_addr_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_ADDR_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ADDR(x) (REGS_IPU_BASE(x) + 0x58060)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_ADDR_5(x) (*(volatile hw_ipu_dc_wr_ch_addr_5_t *) HW_IPU_DC_WR_CH_ADDR_5_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_RD(x) (HW_IPU_DC_WR_CH_ADDR_5(x).U)
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_WR(x, v) (HW_IPU_DC_WR_CH_ADDR_5(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_SET(x, v) (HW_IPU_DC_WR_CH_ADDR_5_WR(x, HW_IPU_DC_WR_CH_ADDR_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_CLR(x, v) (HW_IPU_DC_WR_CH_ADDR_5_WR(x, HW_IPU_DC_WR_CH_ADDR_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_TOG(x, v) (HW_IPU_DC_WR_CH_ADDR_5_WR(x, HW_IPU_DC_WR_CH_ADDR_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_ADDR_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_ADDR_5, field ST_ADDR_5[28:0] (RW)
|
|
*
|
|
* This field defines the start address within the display's memory space where the write
|
|
* transactions will be done to for channel #5.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5 (0) //!< Bit position for IPU_DC_WR_CH_ADDR_5_ST_ADDR_5.
|
|
#define BM_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5 (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_ADDR_5_ST_ADDR_5.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_ADDR_5_ST_ADDR_5 from a register value.
|
|
#define BG_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5) >> BP_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_ADDR_5_ST_ADDR_5.
|
|
#define BF_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5) & BM_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ST_ADDR_5 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5(x, v) (HW_IPU_DC_WR_CH_ADDR_5_WR(x, (HW_IPU_DC_WR_CH_ADDR_5_RD(x) & ~BM_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5) | BF_IPU_DC_WR_CH_ADDR_5_ST_ADDR_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL0_CH_5 - DC Routine Link Register 0 Channel 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL0_CH_5 - DC Routine Link Register 0 Channel 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl0_ch_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl0_ch_5_bitfields
|
|
{
|
|
unsigned COD_NF_PRIORITY_CHAN_5 : 4; //!< [3:0] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NF_START_CHAN_5 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new frame event resides (associated with channel #5)
|
|
unsigned COD_NL_PRIORITY_CHAN_5 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NL_START_CHAN_5 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new line event resides (associated with channel #5)
|
|
} B;
|
|
} hw_ipu_dc_rl0_ch_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL0_CH_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL0_CH_5_ADDR(x) (REGS_IPU_BASE(x) + 0x58064)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL0_CH_5(x) (*(volatile hw_ipu_dc_rl0_ch_5_t *) HW_IPU_DC_RL0_CH_5_ADDR(x))
|
|
#define HW_IPU_DC_RL0_CH_5_RD(x) (HW_IPU_DC_RL0_CH_5(x).U)
|
|
#define HW_IPU_DC_RL0_CH_5_WR(x, v) (HW_IPU_DC_RL0_CH_5(x).U = (v))
|
|
#define HW_IPU_DC_RL0_CH_5_SET(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, HW_IPU_DC_RL0_CH_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL0_CH_5_CLR(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, HW_IPU_DC_RL0_CH_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL0_CH_5_TOG(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, HW_IPU_DC_RL0_CH_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL0_CH_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_5, field COD_NF_PRIORITY_CHAN_5[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5 (0) //!< Bit position for IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5 (0x0000000f) //!< Bit mask for IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5.
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|
|
|
//! @brief Get value of IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5) >> BP_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5) & BM_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, (HW_IPU_DC_RL0_CH_5_RD(x) & ~BM_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5) | BF_IPU_DC_RL0_CH_5_COD_NF_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_5, field COD_NF_START_CHAN_5[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new frame event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5 (8) //!< Bit position for IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5.
|
|
#define BM_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5 (0x0000ff00) //!< Bit mask for IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5) >> BP_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5.
|
|
#define BF_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5) & BM_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, (HW_IPU_DC_RL0_CH_5_RD(x) & ~BM_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5) | BF_IPU_DC_RL0_CH_5_COD_NF_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_5, field COD_NL_PRIORITY_CHAN_5[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5 (16) //!< Bit position for IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5 (0x000f0000) //!< Bit mask for IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5) >> BP_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5) & BM_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, (HW_IPU_DC_RL0_CH_5_RD(x) & ~BM_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5) | BF_IPU_DC_RL0_CH_5_COD_NL_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_5, field COD_NL_START_CHAN_5[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new line event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5 (24) //!< Bit position for IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5.
|
|
#define BM_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5 (0xff000000) //!< Bit mask for IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5) >> BP_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5.
|
|
#define BF_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5) & BM_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5(x, v) (HW_IPU_DC_RL0_CH_5_WR(x, (HW_IPU_DC_RL0_CH_5_RD(x) & ~BM_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5) | BF_IPU_DC_RL0_CH_5_COD_NL_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL1_CH_5 - DC Routine Link Register 1 Channel 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_5 - DC Routine Link Register 1 Channel 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl1_ch_5_bitfields
|
|
{
|
|
unsigned COD_EOF_PRIORITY_CHAN_5 : 4; //!< [3:0] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOF_START_CHAN_5 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of frame event resides (associated with channel #5)
|
|
unsigned COD_NFIELD_PRIORITY_CHAN_5 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NFIELD_START_CHAN_5 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new field event resides (associated with channel #5)
|
|
} B;
|
|
} hw_ipu_dc_rl1_ch_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL1_CH_5_ADDR(x) (REGS_IPU_BASE(x) + 0x58068)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL1_CH_5(x) (*(volatile hw_ipu_dc_rl1_ch_5_t *) HW_IPU_DC_RL1_CH_5_ADDR(x))
|
|
#define HW_IPU_DC_RL1_CH_5_RD(x) (HW_IPU_DC_RL1_CH_5(x).U)
|
|
#define HW_IPU_DC_RL1_CH_5_WR(x, v) (HW_IPU_DC_RL1_CH_5(x).U = (v))
|
|
#define HW_IPU_DC_RL1_CH_5_SET(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, HW_IPU_DC_RL1_CH_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL1_CH_5_CLR(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, HW_IPU_DC_RL1_CH_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL1_CH_5_TOG(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, HW_IPU_DC_RL1_CH_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL1_CH_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_5, field COD_EOF_PRIORITY_CHAN_5[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5 (0) //!< Bit position for IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5) >> BP_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5) & BM_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, (HW_IPU_DC_RL1_CH_5_RD(x) & ~BM_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5) | BF_IPU_DC_RL1_CH_5_COD_EOF_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_5, field COD_EOF_START_CHAN_5[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of frame event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5 (8) //!< Bit position for IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5.
|
|
#define BM_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5) >> BP_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5.
|
|
#define BF_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5) & BM_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, (HW_IPU_DC_RL1_CH_5_RD(x) & ~BM_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5) | BF_IPU_DC_RL1_CH_5_COD_EOF_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_5, field COD_NFIELD_PRIORITY_CHAN_5[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5 (16) //!< Bit position for IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5 (0x000f0000) //!< Bit mask for IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5) >> BP_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5) & BM_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, (HW_IPU_DC_RL1_CH_5_RD(x) & ~BM_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5) | BF_IPU_DC_RL1_CH_5_COD_NFIELD_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_5, field COD_NFIELD_START_CHAN_5[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new field event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5 (24) //!< Bit position for IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5.
|
|
#define BM_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5) >> BP_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5.
|
|
#define BF_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5) & BM_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5(x, v) (HW_IPU_DC_RL1_CH_5_WR(x, (HW_IPU_DC_RL1_CH_5_RD(x) & ~BM_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5) | BF_IPU_DC_RL1_CH_5_COD_NFIELD_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_5 - DC Routine Link Register 2 Channel 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_5 - DC Routine Link Register 2 Channel 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_5_bitfields
|
|
{
|
|
unsigned COD_EOL_PRIORITY_CHAN_5 : 4; //!< [3:0] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOL_START_CHAN_5 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of line event resides (associated with channel #5)
|
|
unsigned COD_EOFIELD_PRIORITY_CHAN_5 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_EOFIELD_START_CHAN_5 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the end of field event resides (associated with channel #5)
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_5_ADDR(x) (REGS_IPU_BASE(x) + 0x5806c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_5(x) (*(volatile hw_ipu_dc_rl2_ch_5_t *) HW_IPU_DC_RL2_CH_5_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_5_RD(x) (HW_IPU_DC_RL2_CH_5(x).U)
|
|
#define HW_IPU_DC_RL2_CH_5_WR(x, v) (HW_IPU_DC_RL2_CH_5(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_5_SET(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, HW_IPU_DC_RL2_CH_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_5_CLR(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, HW_IPU_DC_RL2_CH_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_5_TOG(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, HW_IPU_DC_RL2_CH_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_5, field COD_EOL_PRIORITY_CHAN_5[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5 (0) //!< Bit position for IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5) >> BP_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5) & BM_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, (HW_IPU_DC_RL2_CH_5_RD(x) & ~BM_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5) | BF_IPU_DC_RL2_CH_5_COD_EOL_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_5, field COD_EOL_START_CHAN_5[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of line event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5 (8) //!< Bit position for IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5.
|
|
#define BM_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5) >> BP_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5.
|
|
#define BF_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5) & BM_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, (HW_IPU_DC_RL2_CH_5_RD(x) & ~BM_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5) | BF_IPU_DC_RL2_CH_5_COD_EOL_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_5, field COD_EOFIELD_PRIORITY_CHAN_5[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5 (16) //!< Bit position for IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5 (0x000f0000) //!< Bit mask for IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5) >> BP_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5) & BM_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, (HW_IPU_DC_RL2_CH_5_RD(x) & ~BM_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5) | BF_IPU_DC_RL2_CH_5_COD_EOFIELD_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_5, field COD_EOFIELD_START_CHAN_5[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of field event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5 (24) //!< Bit position for IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5.
|
|
#define BM_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5) >> BP_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5.
|
|
#define BF_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5) & BM_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOFIELD_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5(x, v) (HW_IPU_DC_RL2_CH_5_WR(x, (HW_IPU_DC_RL2_CH_5_RD(x) & ~BM_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5) | BF_IPU_DC_RL2_CH_5_COD_EOFIELD_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL3_CH_5 - DC Routine Link Register3 Channel 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL3_CH_5 - DC Routine Link Register3 Channel 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl3_ch_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl3_ch_5_bitfields
|
|
{
|
|
unsigned COD_NEW_ADDR_PRIORITY_CHAN_5 : 4; //!< [3:0] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_5 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #5)
|
|
unsigned COD_NEW_CHAN_PRIORITY_CHAN_5 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #5)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_5 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #5)
|
|
} B;
|
|
} hw_ipu_dc_rl3_ch_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL3_CH_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL3_CH_5_ADDR(x) (REGS_IPU_BASE(x) + 0x58070)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL3_CH_5(x) (*(volatile hw_ipu_dc_rl3_ch_5_t *) HW_IPU_DC_RL3_CH_5_ADDR(x))
|
|
#define HW_IPU_DC_RL3_CH_5_RD(x) (HW_IPU_DC_RL3_CH_5(x).U)
|
|
#define HW_IPU_DC_RL3_CH_5_WR(x, v) (HW_IPU_DC_RL3_CH_5(x).U = (v))
|
|
#define HW_IPU_DC_RL3_CH_5_SET(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, HW_IPU_DC_RL3_CH_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL3_CH_5_CLR(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, HW_IPU_DC_RL3_CH_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL3_CH_5_TOG(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, HW_IPU_DC_RL3_CH_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL3_CH_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_5, field COD_NEW_ADDR_PRIORITY_CHAN_5[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5 (0) //!< Bit position for IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5.
|
|
#define BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5) >> BP_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5) & BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, (HW_IPU_DC_RL3_CH_5_RD(x) & ~BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5) | BF_IPU_DC_RL3_CH_5_COD_NEW_ADDR_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_5, field COD_NEW_ADDR_START_CHAN_5[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5 (8) //!< Bit position for IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5.
|
|
#define BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5) >> BP_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5.
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#define BF_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5) & BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_ADDR_START_CHAN_5 field to a new value.
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#define BW_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, (HW_IPU_DC_RL3_CH_5_RD(x) & ~BM_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5) | BF_IPU_DC_RL3_CH_5_COD_NEW_ADDR_START_CHAN_5(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL3_CH_5, field COD_NEW_CHAN_PRIORITY_CHAN_5[19:16] (RW)
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*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
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|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
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|
*
|
|
* Values:
|
|
* - 0000 - disable
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|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
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|
* - 1101 - Priority #13 (highest)
|
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* - 1110 - Reserved
|
|
* - 1111 - Reserved
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|
*/
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//@{
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|
#define BP_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5 (16) //!< Bit position for IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5.
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#define BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5 (0x000f0000) //!< Bit mask for IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5.
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//! @brief Get value of IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5 from a register value.
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#define BG_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5) >> BP_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5.
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#define BF_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5) & BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_5 field to a new value.
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#define BW_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, (HW_IPU_DC_RL3_CH_5_RD(x) & ~BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5) | BF_IPU_DC_RL3_CH_5_COD_NEW_CHAN_PRIORITY_CHAN_5(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL3_CH_5, field COD_NEW_CHAN_START_CHAN_5[31:24] (RW)
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*
|
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* This field is a pointer to the address within the microcode memory where the routine that handles
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* the new channel event resides (associated with channel #5)
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*/
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|
//@{
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|
#define BP_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5 (24) //!< Bit position for IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5.
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#define BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5.
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//! @brief Get value of IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5 from a register value.
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#define BG_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5) >> BP_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5.
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|
#define BF_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5) & BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_5 field to a new value.
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|
#define BW_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5(x, v) (HW_IPU_DC_RL3_CH_5_WR(x, (HW_IPU_DC_RL3_CH_5_RD(x) & ~BM_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5) | BF_IPU_DC_RL3_CH_5_COD_NEW_CHAN_START_CHAN_5(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_RL4_CH_5 - DC Routine Link Register 4 Channel 5
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//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
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|
/*!
|
|
* @brief HW_IPU_DC_RL4_CH_5 - DC Routine Link Register 4 Channel 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl4_ch_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl4_ch_5_bitfields
|
|
{
|
|
unsigned COD_NEW_DATA_PRIORITY_CHAN_5 : 4; //!< [3:0] This field defines the priority of the new line event (associated with channel #5)
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|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
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|
unsigned COD_NEW_DATA_START_CHAN_5 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #5)
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|
unsigned RESERVED1 : 16; //!< [31:16] Reserved.
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|
} B;
|
|
} hw_ipu_dc_rl4_ch_5_t;
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|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL4_CH_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL4_CH_5_ADDR(x) (REGS_IPU_BASE(x) + 0x58074)
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|
|
#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_DC_RL4_CH_5(x) (*(volatile hw_ipu_dc_rl4_ch_5_t *) HW_IPU_DC_RL4_CH_5_ADDR(x))
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|
#define HW_IPU_DC_RL4_CH_5_RD(x) (HW_IPU_DC_RL4_CH_5(x).U)
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|
#define HW_IPU_DC_RL4_CH_5_WR(x, v) (HW_IPU_DC_RL4_CH_5(x).U = (v))
|
|
#define HW_IPU_DC_RL4_CH_5_SET(x, v) (HW_IPU_DC_RL4_CH_5_WR(x, HW_IPU_DC_RL4_CH_5_RD(x) | (v)))
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|
#define HW_IPU_DC_RL4_CH_5_CLR(x, v) (HW_IPU_DC_RL4_CH_5_WR(x, HW_IPU_DC_RL4_CH_5_RD(x) & ~(v)))
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|
#define HW_IPU_DC_RL4_CH_5_TOG(x, v) (HW_IPU_DC_RL4_CH_5_WR(x, HW_IPU_DC_RL4_CH_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_5, field COD_NEW_DATA_PRIORITY_CHAN_5[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #5) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5 (0) //!< Bit position for IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5.
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|
#define BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5 (0x0000000f) //!< Bit mask for IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5.
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|
|
//! @brief Get value of IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5 from a register value.
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|
#define BG_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5) >> BP_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5)
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|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5.
|
|
#define BF_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5) & BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5(x, v) (HW_IPU_DC_RL4_CH_5_WR(x, (HW_IPU_DC_RL4_CH_5_RD(x) & ~BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5) | BF_IPU_DC_RL4_CH_5_COD_NEW_DATA_PRIORITY_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_5, field COD_NEW_DATA_START_CHAN_5[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #5)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5 (8) //!< Bit position for IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5.
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|
#define BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5.
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|
|
|
//! @brief Get value of IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5) >> BP_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5.
|
|
#define BF_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5) & BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5(x, v) (HW_IPU_DC_RL4_CH_5_WR(x, (HW_IPU_DC_RL4_CH_5_RD(x) & ~BM_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5) | BF_IPU_DC_RL4_CH_5_COD_NEW_DATA_START_CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF_6 - DC Write Channel 6 Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF_6 - DC Write Channel 6 Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf_6_bitfields
|
|
{
|
|
unsigned W_SIZE_6 : 2; //!< [1:0] Word Size associated with channel #6
|
|
unsigned PROG_DI_ID_6 : 1; //!< [2] This bit select the DI which a transaction associated with channel #6 can be performed to
|
|
unsigned PROG_DISP_ID_6 : 2; //!< [4:3] The field defines which one of the 4 displays is associated with channel #6.
|
|
unsigned PROG_CHAN_TYP_6 : 3; //!< [7:5] This field define the mode of operation of channel #6
|
|
unsigned CHAN_MASK_DEFAULT_6 : 1; //!< [8] Event mask bit for channel #6
|
|
unsigned RESERVED0 : 7; //!< [15:9] Reserved.
|
|
unsigned PROG_START_TIME_6 : 11; //!< [26:16] This field defines the delay between display 's vertical synchronization pulse and the start time point of DC's channel 6 window.
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF_6_ADDR(x) (REGS_IPU_BASE(x) + 0x58078)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF_6(x) (*(volatile hw_ipu_dc_wr_ch_conf_6_t *) HW_IPU_DC_WR_CH_CONF_6_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF_6_RD(x) (HW_IPU_DC_WR_CH_CONF_6(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF_6_WR(x, v) (HW_IPU_DC_WR_CH_CONF_6(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF_6_SET(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, HW_IPU_DC_WR_CH_CONF_6_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_6_CLR(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF_6_TOG(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, HW_IPU_DC_WR_CH_CONF_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_6, field W_SIZE_6[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #6 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_6_W_SIZE_6 (0) //!< Bit position for IPU_DC_WR_CH_CONF_6_W_SIZE_6.
|
|
#define BM_IPU_DC_WR_CH_CONF_6_W_SIZE_6 (0x00000003) //!< Bit mask for IPU_DC_WR_CH_CONF_6_W_SIZE_6.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_6_W_SIZE_6 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_6_W_SIZE_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_6_W_SIZE_6) >> BP_IPU_DC_WR_CH_CONF_6_W_SIZE_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_6_W_SIZE_6.
|
|
#define BF_IPU_DC_WR_CH_CONF_6_W_SIZE_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_6_W_SIZE_6) & BM_IPU_DC_WR_CH_CONF_6_W_SIZE_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_6 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_6_W_SIZE_6(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, (HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~BM_IPU_DC_WR_CH_CONF_6_W_SIZE_6) | BF_IPU_DC_WR_CH_CONF_6_W_SIZE_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_6, field PROG_DI_ID_6[2] (RW)
|
|
*
|
|
* This bit select the DI which a transaction associated with channel #6 can be performed to
|
|
*
|
|
* Values:
|
|
* - 0 - DI #0
|
|
* - 1 - DI #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6 (2) //!< Bit position for IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6.
|
|
#define BM_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6 (0x00000004) //!< Bit mask for IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6) >> BP_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6.
|
|
#define BF_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6) & BM_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_DI_ID_6 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, (HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~BM_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6) | BF_IPU_DC_WR_CH_CONF_6_PROG_DI_ID_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF_6, field PROG_DISP_ID_6[4:3] (RW)
|
|
*
|
|
* The field defines which one of the 4 displays is associated with channel #6.
|
|
*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
|
|
* - 10 - display #2
|
|
* - 11 - display #3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6 (3) //!< Bit position for IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6.
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#define BM_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6 (0x00000018) //!< Bit mask for IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6.
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//! @brief Get value of IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6) >> BP_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6.
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#define BF_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6) & BM_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PROG_DISP_ID_6 field to a new value.
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#define BW_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, (HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~BM_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6) | BF_IPU_DC_WR_CH_CONF_6_PROG_DISP_ID_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_WR_CH_CONF_6, field PROG_CHAN_TYP_6[7:5] (RW)
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*
|
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* This field define the mode of operation of channel #6
|
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*
|
|
* Values:
|
|
* - 000 - Disable
|
|
* - 001 - Reserved
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* - 010 - Reserved
|
|
* - 100 - Normal mode without anti-tearing. For sync display this is the only mode allowed
|
|
* - 101 - Normal mode with anti-tearing
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* - 110 - Reserved
|
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* - 111 - Additional command channel is added to the flow handled by DC channel #6
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*/
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//@{
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#define BP_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6 (5) //!< Bit position for IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6.
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#define BM_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6 (0x000000e0) //!< Bit mask for IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6.
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//! @brief Get value of IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6) >> BP_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6.
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#define BF_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6) & BM_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PROG_CHAN_TYP_6 field to a new value.
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#define BW_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, (HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~BM_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6) | BF_IPU_DC_WR_CH_CONF_6_PROG_CHAN_TYP_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_WR_CH_CONF_6, field CHAN_MASK_DEFAULT_6[8] (RW)
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*
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* Event mask bit for channel #6 When more then one event is used during a flow (EOF, EOL, NL, NF,
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* EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
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* event
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*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
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* - 1 - All the events are used - no mask
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*/
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//@{
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#define BP_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6 (8) //!< Bit position for IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6.
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#define BM_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6 (0x00000100) //!< Bit mask for IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6.
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//! @brief Get value of IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6 from a register value.
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#define BG_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6) >> BP_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6)
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//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6.
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#define BF_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6) & BM_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6)
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|
#ifndef __LANGUAGE_ASM__
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//! @brief Set the CHAN_MASK_DEFAULT_6 field to a new value.
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|
#define BW_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, (HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~BM_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6) | BF_IPU_DC_WR_CH_CONF_6_CHAN_MASK_DEFAULT_6(v)))
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|
#endif
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|
//@}
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/*! @name Register IPU_DC_WR_CH_CONF_6, field PROG_START_TIME_6[26:16] (RW)
|
|
*
|
|
* This field defines the delay between display 's vertical synchronization pulse and the start time
|
|
* point of DC's channel 6 window. The delay is defined in pairs of rows. It is used for tearing
|
|
* elimination
|
|
*/
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|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6 (16) //!< Bit position for IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6.
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#define BM_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6 (0x07ff0000) //!< Bit mask for IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6.
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//! @brief Get value of IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6 from a register value.
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|
#define BG_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6) >> BP_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6)
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|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6.
|
|
#define BF_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6) & BM_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the PROG_START_TIME_6 field to a new value.
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|
#define BW_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6(x, v) (HW_IPU_DC_WR_CH_CONF_6_WR(x, (HW_IPU_DC_WR_CH_CONF_6_RD(x) & ~BM_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6) | BF_IPU_DC_WR_CH_CONF_6_PROG_START_TIME_6(v)))
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|
#endif
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|
//@}
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|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_ADDR_6 - DC Write Channel 6 Address Configuration Register
|
|
//-------------------------------------------------------------------------------------------
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|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_ADDR_6 - DC Write Channel 6 Address Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_addr_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_addr_6_bitfields
|
|
{
|
|
unsigned ST_ADDR_6 : 29; //!< [28:0] This field defines the start address within the display's memory space where the write transactions will be done to for channel #6.
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|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_addr_6_t;
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|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_ADDR_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_ADDR_6_ADDR(x) (REGS_IPU_BASE(x) + 0x5807c)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_ADDR_6(x) (*(volatile hw_ipu_dc_wr_ch_addr_6_t *) HW_IPU_DC_WR_CH_ADDR_6_ADDR(x))
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|
#define HW_IPU_DC_WR_CH_ADDR_6_RD(x) (HW_IPU_DC_WR_CH_ADDR_6(x).U)
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|
#define HW_IPU_DC_WR_CH_ADDR_6_WR(x, v) (HW_IPU_DC_WR_CH_ADDR_6(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_ADDR_6_SET(x, v) (HW_IPU_DC_WR_CH_ADDR_6_WR(x, HW_IPU_DC_WR_CH_ADDR_6_RD(x) | (v)))
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|
#define HW_IPU_DC_WR_CH_ADDR_6_CLR(x, v) (HW_IPU_DC_WR_CH_ADDR_6_WR(x, HW_IPU_DC_WR_CH_ADDR_6_RD(x) & ~(v)))
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|
#define HW_IPU_DC_WR_CH_ADDR_6_TOG(x, v) (HW_IPU_DC_WR_CH_ADDR_6_WR(x, HW_IPU_DC_WR_CH_ADDR_6_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_ADDR_6 bitfields
|
|
*/
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|
|
|
/*! @name Register IPU_DC_WR_CH_ADDR_6, field ST_ADDR_6[28:0] (RW)
|
|
*
|
|
* This field defines the start address within the display's memory space where the write
|
|
* transactions will be done to for channel #6.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6 (0) //!< Bit position for IPU_DC_WR_CH_ADDR_6_ST_ADDR_6.
|
|
#define BM_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6 (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_ADDR_6_ST_ADDR_6.
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|
|
|
//! @brief Get value of IPU_DC_WR_CH_ADDR_6_ST_ADDR_6 from a register value.
|
|
#define BG_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6) >> BP_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_ADDR_6_ST_ADDR_6.
|
|
#define BF_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6) & BM_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ST_ADDR_6 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6(x, v) (HW_IPU_DC_WR_CH_ADDR_6_WR(x, (HW_IPU_DC_WR_CH_ADDR_6_RD(x) & ~BM_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6) | BF_IPU_DC_WR_CH_ADDR_6_ST_ADDR_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL0_CH_6 - DC Routine Link Register 0Channel 6
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL0_CH_6 - DC Routine Link Register 0Channel 6 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl0_ch_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl0_ch_6_bitfields
|
|
{
|
|
unsigned COD_NF_PRIORITY_CHAN_6 : 4; //!< [3:0] This field defines the priority of the new frame event (associated with channel #6)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NF_START_CHAN_6 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new frame event resides (associated with channel #6)
|
|
unsigned COD_NL_PRIORITY_CHAN_6 : 4; //!< [19:16] This field defines the priority of the new line event (associated with channel #6)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NL_START_CHAN_6 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new line event resides (associated with channel #6)
|
|
} B;
|
|
} hw_ipu_dc_rl0_ch_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL0_CH_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL0_CH_6_ADDR(x) (REGS_IPU_BASE(x) + 0x58080)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL0_CH_6(x) (*(volatile hw_ipu_dc_rl0_ch_6_t *) HW_IPU_DC_RL0_CH_6_ADDR(x))
|
|
#define HW_IPU_DC_RL0_CH_6_RD(x) (HW_IPU_DC_RL0_CH_6(x).U)
|
|
#define HW_IPU_DC_RL0_CH_6_WR(x, v) (HW_IPU_DC_RL0_CH_6(x).U = (v))
|
|
#define HW_IPU_DC_RL0_CH_6_SET(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, HW_IPU_DC_RL0_CH_6_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL0_CH_6_CLR(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, HW_IPU_DC_RL0_CH_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL0_CH_6_TOG(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, HW_IPU_DC_RL0_CH_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL0_CH_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_6, field COD_NF_PRIORITY_CHAN_6[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new frame event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6 (0) //!< Bit position for IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6.
|
|
#define BM_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6 (0x0000000f) //!< Bit mask for IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6) >> BP_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6) & BM_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, (HW_IPU_DC_RL0_CH_6_RD(x) & ~BM_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6) | BF_IPU_DC_RL0_CH_6_COD_NF_PRIORITY_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_6, field COD_NF_START_CHAN_6[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new frame event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6 (8) //!< Bit position for IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6.
|
|
#define BM_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6 (0x0000ff00) //!< Bit mask for IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6) >> BP_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6.
|
|
#define BF_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6) & BM_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NF_START_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, (HW_IPU_DC_RL0_CH_6_RD(x) & ~BM_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6) | BF_IPU_DC_RL0_CH_6_COD_NF_START_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL0_CH_6, field COD_NL_PRIORITY_CHAN_6[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new line event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6 (16) //!< Bit position for IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6.
|
|
#define BM_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6 (0x000f0000) //!< Bit mask for IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6) >> BP_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6)
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//! @brief Format value for bitfield IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6) & BM_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NL_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, (HW_IPU_DC_RL0_CH_6_RD(x) & ~BM_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6) | BF_IPU_DC_RL0_CH_6_COD_NL_PRIORITY_CHAN_6(v)))
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|
#endif
|
|
//@}
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|
|
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/*! @name Register IPU_DC_RL0_CH_6, field COD_NL_START_CHAN_6[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new line event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6 (24) //!< Bit position for IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6.
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#define BM_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6 (0xff000000) //!< Bit mask for IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6.
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//! @brief Get value of IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6) >> BP_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6)
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//! @brief Format value for bitfield IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6.
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|
#define BF_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6) & BM_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the COD_NL_START_CHAN_6 field to a new value.
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|
#define BW_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6(x, v) (HW_IPU_DC_RL0_CH_6_WR(x, (HW_IPU_DC_RL0_CH_6_RD(x) & ~BM_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6) | BF_IPU_DC_RL0_CH_6_COD_NL_START_CHAN_6(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_RL1_CH_6 - DC Routine Link Register 1 Channel 6
|
|
//-------------------------------------------------------------------------------------------
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_6 - DC Routine Link Register 1 Channel 6 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_6
|
|
{
|
|
reg32_t U;
|
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struct _hw_ipu_dc_rl1_ch_6_bitfields
|
|
{
|
|
unsigned COD_EOF_PRIORITY_CHAN_6 : 4; //!< [3:0] This field defines the priority of the new field event (associated with channel #6)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOF_START_CHAN_6 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of frame event resides (associated with channel #6)
|
|
unsigned COD_NFIELD_PRIORITY_CHAN_6 : 4; //!< [19:16] This field defines the priority of the new field event (associated with channel #6)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_NFIELD_START_CHAN_6 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new field event resides (associated with channel #6)
|
|
} B;
|
|
} hw_ipu_dc_rl1_ch_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL1_CH_6_ADDR(x) (REGS_IPU_BASE(x) + 0x58084)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL1_CH_6(x) (*(volatile hw_ipu_dc_rl1_ch_6_t *) HW_IPU_DC_RL1_CH_6_ADDR(x))
|
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#define HW_IPU_DC_RL1_CH_6_RD(x) (HW_IPU_DC_RL1_CH_6(x).U)
|
|
#define HW_IPU_DC_RL1_CH_6_WR(x, v) (HW_IPU_DC_RL1_CH_6(x).U = (v))
|
|
#define HW_IPU_DC_RL1_CH_6_SET(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, HW_IPU_DC_RL1_CH_6_RD(x) | (v)))
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|
#define HW_IPU_DC_RL1_CH_6_CLR(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, HW_IPU_DC_RL1_CH_6_RD(x) & ~(v)))
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|
#define HW_IPU_DC_RL1_CH_6_TOG(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, HW_IPU_DC_RL1_CH_6_RD(x) ^ (v)))
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|
#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL1_CH_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_6, field COD_EOF_PRIORITY_CHAN_6[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6 (0) //!< Bit position for IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6.
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|
#define BM_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6.
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|
|
|
//! @brief Get value of IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6) >> BP_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6) & BM_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, (HW_IPU_DC_RL1_CH_6_RD(x) & ~BM_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6) | BF_IPU_DC_RL1_CH_6_COD_EOF_PRIORITY_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_6, field COD_EOF_START_CHAN_6[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of frame event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6 (8) //!< Bit position for IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6.
|
|
#define BM_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6.
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|
|
|
//! @brief Get value of IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6) >> BP_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6.
|
|
#define BF_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6) & BM_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOF_START_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, (HW_IPU_DC_RL1_CH_6_RD(x) & ~BM_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6) | BF_IPU_DC_RL1_CH_6_COD_EOF_START_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_6, field COD_NFIELD_PRIORITY_CHAN_6[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6 (16) //!< Bit position for IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6.
|
|
#define BM_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6 (0x000f0000) //!< Bit mask for IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6) >> BP_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6) & BM_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, (HW_IPU_DC_RL1_CH_6_RD(x) & ~BM_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6) | BF_IPU_DC_RL1_CH_6_COD_NFIELD_PRIORITY_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_6, field COD_NFIELD_START_CHAN_6[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new field event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6 (24) //!< Bit position for IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6.
|
|
#define BM_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6) >> BP_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6.
|
|
#define BF_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6) & BM_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NFIELD_START_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6(x, v) (HW_IPU_DC_RL1_CH_6_WR(x, (HW_IPU_DC_RL1_CH_6_RD(x) & ~BM_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6) | BF_IPU_DC_RL1_CH_6_COD_NFIELD_START_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_6 - DC Routine Link Register 2 Channel 6
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_6 - DC Routine Link Register 2 Channel 6 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_6_bitfields
|
|
{
|
|
unsigned COD_EOL_PRIORITY_CHAN_6 : 4; //!< [3:0] This field defines the priority of the new field event (associated with channel #6)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_EOL_START_CHAN_6 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the end of line event resides (associated with channel #6)
|
|
unsigned COD_EOFIELD_PRIORITY_CHAN_6 : 4; //!< [19:16] This field defines the priority of the new field event (associated with channel #6)
|
|
unsigned RESERVED1 : 4; //!< [23:20] Reserved.
|
|
unsigned COD_EOFIELD_START_CHAN_6 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the end of field event resides (associated with channel #6)
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_6_ADDR(x) (REGS_IPU_BASE(x) + 0x58088)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_6(x) (*(volatile hw_ipu_dc_rl2_ch_6_t *) HW_IPU_DC_RL2_CH_6_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_6_RD(x) (HW_IPU_DC_RL2_CH_6(x).U)
|
|
#define HW_IPU_DC_RL2_CH_6_WR(x, v) (HW_IPU_DC_RL2_CH_6(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_6_SET(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, HW_IPU_DC_RL2_CH_6_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_6_CLR(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, HW_IPU_DC_RL2_CH_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_6_TOG(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, HW_IPU_DC_RL2_CH_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_6, field COD_EOL_PRIORITY_CHAN_6[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6 (0) //!< Bit position for IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6.
|
|
#define BM_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6) >> BP_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6) & BM_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EOL_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, (HW_IPU_DC_RL2_CH_6_RD(x) & ~BM_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6) | BF_IPU_DC_RL2_CH_6_COD_EOL_PRIORITY_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_6, field COD_EOL_START_CHAN_6[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the end of line event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6 (8) //!< Bit position for IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6.
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#define BM_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6.
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//! @brief Get value of IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6 from a register value.
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#define BG_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6) >> BP_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6)
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//! @brief Format value for bitfield IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6.
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#define BF_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6) & BM_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_EOL_START_CHAN_6 field to a new value.
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#define BW_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, (HW_IPU_DC_RL2_CH_6_RD(x) & ~BM_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6) | BF_IPU_DC_RL2_CH_6_COD_EOL_START_CHAN_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL2_CH_6, field COD_EOFIELD_PRIORITY_CHAN_6[19:16] (RW)
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*
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* This field defines the priority of the new field event (associated with channel #6) The priority
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|
* between the events should be set to a unique value. i.e. two events must not have the same
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|
* priority (except 0000 - disable)
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*
|
|
* Values:
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* - 0000 - disable
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|
* - 0001 - Priority #1 (lowest)
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* - 0010 - Priority #2
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* - 1101 - Priority #13 (highest)
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* - 1110 - Reserved
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* - 1111 - Reserved
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*/
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//@{
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#define BP_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6 (16) //!< Bit position for IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6.
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#define BM_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6 (0x000f0000) //!< Bit mask for IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6.
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//! @brief Get value of IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6 from a register value.
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#define BG_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6) >> BP_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6)
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//! @brief Format value for bitfield IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6.
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#define BF_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6) & BM_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_EOFIELD_PRIORITY_CHAN_6 field to a new value.
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#define BW_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, (HW_IPU_DC_RL2_CH_6_RD(x) & ~BM_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6) | BF_IPU_DC_RL2_CH_6_COD_EOFIELD_PRIORITY_CHAN_6(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL2_CH_6, field COD_EOFIELD_START_CHAN_6[31:24] (RW)
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*
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* This field is a pointer to the address within the microcode memory where the routine that handles
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* the end of field event resides (associated with channel #6)
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*/
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//@{
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#define BP_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6 (24) //!< Bit position for IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6.
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#define BM_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6.
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//! @brief Get value of IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6 from a register value.
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#define BG_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6) >> BP_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6)
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//! @brief Format value for bitfield IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6.
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#define BF_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6) & BM_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_EOFIELD_START_CHAN_6 field to a new value.
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|
#define BW_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6(x, v) (HW_IPU_DC_RL2_CH_6_WR(x, (HW_IPU_DC_RL2_CH_6_RD(x) & ~BM_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6) | BF_IPU_DC_RL2_CH_6_COD_EOFIELD_START_CHAN_6(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_RL3_CH_6 - DC Routine Link Register 3 Channel 6
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
|
|
* @brief HW_IPU_DC_RL3_CH_6 - DC Routine Link Register 3 Channel 6 (RW)
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|
*
|
|
* Reset value: 0x00000000
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|
*/
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|
typedef union _hw_ipu_dc_rl3_ch_6
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{
|
|
reg32_t U;
|
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struct _hw_ipu_dc_rl3_ch_6_bitfields
|
|
{
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|
unsigned COD_NEW_ADDR_PRIORITY_CHAN_6 : 4; //!< [3:0] This field defines the priority of the new field event (associated with channel #6)
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unsigned RESERVED0 : 4; //!< [7:4] Reserved.
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unsigned COD_NEW_ADDR_START_CHAN_6 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #6)
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|
unsigned COD_NEW_CHAN_PRIORITY_CHAN_6 : 4; //!< [19:16] This field defines the priority of the new field event (associated with channel #6)
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unsigned RESERVED1 : 4; //!< [23:20] Reserved.
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|
unsigned COD_NEW_CHAN_START_CHAN_6 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #6)
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} B;
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|
} hw_ipu_dc_rl3_ch_6_t;
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|
#endif
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/*!
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|
* @name Constants and macros for entire IPU_DC_RL3_CH_6 register
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|
*/
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|
//@{
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|
#define HW_IPU_DC_RL3_CH_6_ADDR(x) (REGS_IPU_BASE(x) + 0x5808c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL3_CH_6(x) (*(volatile hw_ipu_dc_rl3_ch_6_t *) HW_IPU_DC_RL3_CH_6_ADDR(x))
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#define HW_IPU_DC_RL3_CH_6_RD(x) (HW_IPU_DC_RL3_CH_6(x).U)
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#define HW_IPU_DC_RL3_CH_6_WR(x, v) (HW_IPU_DC_RL3_CH_6(x).U = (v))
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#define HW_IPU_DC_RL3_CH_6_SET(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, HW_IPU_DC_RL3_CH_6_RD(x) | (v)))
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#define HW_IPU_DC_RL3_CH_6_CLR(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, HW_IPU_DC_RL3_CH_6_RD(x) & ~(v)))
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#define HW_IPU_DC_RL3_CH_6_TOG(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, HW_IPU_DC_RL3_CH_6_RD(x) ^ (v)))
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|
#endif
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|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL3_CH_6 bitfields
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|
*/
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|
|
|
/*! @name Register IPU_DC_RL3_CH_6, field COD_NEW_ADDR_PRIORITY_CHAN_6[3:0] (RW)
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|
*
|
|
* This field defines the priority of the new field event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
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|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
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|
* - 1111 - Reserved
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|
*/
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|
//@{
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|
#define BP_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6 (0) //!< Bit position for IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6.
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#define BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6.
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//! @brief Get value of IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6 from a register value.
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|
#define BG_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6) >> BP_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6)
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|
//! @brief Format value for bitfield IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6.
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|
#define BF_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6) & BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, (HW_IPU_DC_RL3_CH_6_RD(x) & ~BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6) | BF_IPU_DC_RL3_CH_6_COD_NEW_ADDR_PRIORITY_CHAN_6(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DC_RL3_CH_6, field COD_NEW_ADDR_START_CHAN_6[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6 (8) //!< Bit position for IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6.
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|
#define BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6.
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|
|
//! @brief Get value of IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6 from a register value.
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|
#define BG_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6) >> BP_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6.
|
|
#define BF_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6) & BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, (HW_IPU_DC_RL3_CH_6_RD(x) & ~BM_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6) | BF_IPU_DC_RL3_CH_6_COD_NEW_ADDR_START_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_6, field COD_NEW_CHAN_PRIORITY_CHAN_6[19:16] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6 (16) //!< Bit position for IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6.
|
|
#define BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6 (0x000f0000) //!< Bit mask for IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6.
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|
|
|
//! @brief Get value of IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6) >> BP_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6) & BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, (HW_IPU_DC_RL3_CH_6_RD(x) & ~BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6) | BF_IPU_DC_RL3_CH_6_COD_NEW_CHAN_PRIORITY_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_6, field COD_NEW_CHAN_START_CHAN_6[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6 (24) //!< Bit position for IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6.
|
|
#define BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6) >> BP_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6.
|
|
#define BF_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6) & BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6(x, v) (HW_IPU_DC_RL3_CH_6_WR(x, (HW_IPU_DC_RL3_CH_6_RD(x) & ~BM_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6) | BF_IPU_DC_RL3_CH_6_COD_NEW_CHAN_START_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL4_CH_6 - DC Routine Link Register 4 Channel 6
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL4_CH_6 - DC Routine Link Register 4 Channel 6 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl4_ch_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl4_ch_6_bitfields
|
|
{
|
|
unsigned COD_NEW_DATA_PRIORITY_CHAN_6 : 4; //!< [3:0] This field defines the priority of the new field event (associated with channel #6)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_6 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #6)
|
|
unsigned RESERVED1 : 16; //!< [31:16] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_rl4_ch_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL4_CH_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL4_CH_6_ADDR(x) (REGS_IPU_BASE(x) + 0x58090)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL4_CH_6(x) (*(volatile hw_ipu_dc_rl4_ch_6_t *) HW_IPU_DC_RL4_CH_6_ADDR(x))
|
|
#define HW_IPU_DC_RL4_CH_6_RD(x) (HW_IPU_DC_RL4_CH_6(x).U)
|
|
#define HW_IPU_DC_RL4_CH_6_WR(x, v) (HW_IPU_DC_RL4_CH_6(x).U = (v))
|
|
#define HW_IPU_DC_RL4_CH_6_SET(x, v) (HW_IPU_DC_RL4_CH_6_WR(x, HW_IPU_DC_RL4_CH_6_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL4_CH_6_CLR(x, v) (HW_IPU_DC_RL4_CH_6_WR(x, HW_IPU_DC_RL4_CH_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL4_CH_6_TOG(x, v) (HW_IPU_DC_RL4_CH_6_WR(x, HW_IPU_DC_RL4_CH_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_6, field COD_NEW_DATA_PRIORITY_CHAN_6[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new field event (associated with channel #6) The priority
|
|
* between the events should be set to a unique value. i.e. two events must not have the same
|
|
* priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6 (0) //!< Bit position for IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6.
|
|
#define BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6 (0x0000000f) //!< Bit mask for IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6) >> BP_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6.
|
|
#define BF_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6) & BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6(x, v) (HW_IPU_DC_RL4_CH_6_WR(x, (HW_IPU_DC_RL4_CH_6_RD(x) & ~BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6) | BF_IPU_DC_RL4_CH_6_COD_NEW_DATA_PRIORITY_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_6, field COD_NEW_DATA_START_CHAN_6[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #6)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6 (8) //!< Bit position for IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6.
|
|
#define BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6) >> BP_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6.
|
|
#define BF_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6) & BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_6 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6(x, v) (HW_IPU_DC_RL4_CH_6_WR(x, (HW_IPU_DC_RL4_CH_6_RD(x) & ~BM_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6) | BF_IPU_DC_RL4_CH_6_COD_NEW_DATA_START_CHAN_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF1_8 - DC Write Channel 8 Configuration 1Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF1_8 - DC Write Channel 8 Configuration 1Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf1_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf1_8_bitfields
|
|
{
|
|
unsigned W_SIZE_8 : 2; //!< [1:0] Word Size associated with channel #8
|
|
unsigned CHAN_MASK_DEFAULT_8 : 1; //!< [2] Event mask bit for channel #8
|
|
unsigned MCU_DISP_ID_8 : 2; //!< [4:3] The field defines which one of the 4 displays is associated with channel #8.
|
|
unsigned RESERVED0 : 27; //!< [31:5] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf1_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF1_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF1_8_ADDR(x) (REGS_IPU_BASE(x) + 0x58094)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF1_8(x) (*(volatile hw_ipu_dc_wr_ch_conf1_8_t *) HW_IPU_DC_WR_CH_CONF1_8_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF1_8_RD(x) (HW_IPU_DC_WR_CH_CONF1_8(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF1_8_WR(x, v) (HW_IPU_DC_WR_CH_CONF1_8(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF1_8_SET(x, v) (HW_IPU_DC_WR_CH_CONF1_8_WR(x, HW_IPU_DC_WR_CH_CONF1_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF1_8_CLR(x, v) (HW_IPU_DC_WR_CH_CONF1_8_WR(x, HW_IPU_DC_WR_CH_CONF1_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF1_8_TOG(x, v) (HW_IPU_DC_WR_CH_CONF1_8_WR(x, HW_IPU_DC_WR_CH_CONF1_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF1_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF1_8, field W_SIZE_8[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #8 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF1_8_W_SIZE_8 (0) //!< Bit position for IPU_DC_WR_CH_CONF1_8_W_SIZE_8.
|
|
#define BM_IPU_DC_WR_CH_CONF1_8_W_SIZE_8 (0x00000003) //!< Bit mask for IPU_DC_WR_CH_CONF1_8_W_SIZE_8.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF1_8_W_SIZE_8 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF1_8_W_SIZE_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF1_8_W_SIZE_8) >> BP_IPU_DC_WR_CH_CONF1_8_W_SIZE_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF1_8_W_SIZE_8.
|
|
#define BF_IPU_DC_WR_CH_CONF1_8_W_SIZE_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF1_8_W_SIZE_8) & BM_IPU_DC_WR_CH_CONF1_8_W_SIZE_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_8 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF1_8_W_SIZE_8(x, v) (HW_IPU_DC_WR_CH_CONF1_8_WR(x, (HW_IPU_DC_WR_CH_CONF1_8_RD(x) & ~BM_IPU_DC_WR_CH_CONF1_8_W_SIZE_8) | BF_IPU_DC_WR_CH_CONF1_8_W_SIZE_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF1_8, field CHAN_MASK_DEFAULT_8[2] (RW)
|
|
*
|
|
* Event mask bit for channel #8 When more then one event is used during a flow (EOF, EOL, NL, NF,
|
|
* EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
|
|
* event
|
|
*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
|
* - 1 - All the events are used - no mask
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8 (2) //!< Bit position for IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8.
|
|
#define BM_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8 (0x00000004) //!< Bit mask for IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8) >> BP_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8.
|
|
#define BF_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8) & BM_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CHAN_MASK_DEFAULT_8 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8(x, v) (HW_IPU_DC_WR_CH_CONF1_8_WR(x, (HW_IPU_DC_WR_CH_CONF1_8_RD(x) & ~BM_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8) | BF_IPU_DC_WR_CH_CONF1_8_CHAN_MASK_DEFAULT_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF1_8, field MCU_DISP_ID_8[4:3] (RW)
|
|
*
|
|
* The field defines which one of the 4 displays is associated with channel #8.
|
|
*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
|
|
* - 10 - display #2
|
|
* - 11 - display #3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8 (3) //!< Bit position for IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8.
|
|
#define BM_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8 (0x00000018) //!< Bit mask for IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8) >> BP_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8.
|
|
#define BF_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8) & BM_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_DISP_ID_8 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8(x, v) (HW_IPU_DC_WR_CH_CONF1_8_WR(x, (HW_IPU_DC_WR_CH_CONF1_8_RD(x) & ~BM_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8) | BF_IPU_DC_WR_CH_CONF1_8_MCU_DISP_ID_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF2_8 - DC Write Channel 8 Configuration 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF2_8 - DC Write Channel 8 Configuration 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf2_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf2_8_bitfields
|
|
{
|
|
unsigned NEW_ADDR_SPACE_SA_8 : 29; //!< [28:0] Channel #8 is used for ARM platform direct access to the display.
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf2_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF2_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF2_8_ADDR(x) (REGS_IPU_BASE(x) + 0x58098)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF2_8(x) (*(volatile hw_ipu_dc_wr_ch_conf2_8_t *) HW_IPU_DC_WR_CH_CONF2_8_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF2_8_RD(x) (HW_IPU_DC_WR_CH_CONF2_8(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF2_8_WR(x, v) (HW_IPU_DC_WR_CH_CONF2_8(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF2_8_SET(x, v) (HW_IPU_DC_WR_CH_CONF2_8_WR(x, HW_IPU_DC_WR_CH_CONF2_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF2_8_CLR(x, v) (HW_IPU_DC_WR_CH_CONF2_8_WR(x, HW_IPU_DC_WR_CH_CONF2_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF2_8_TOG(x, v) (HW_IPU_DC_WR_CH_CONF2_8_WR(x, HW_IPU_DC_WR_CH_CONF2_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF2_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF2_8, field NEW_ADDR_SPACE_SA_8[28:0] (RW)
|
|
*
|
|
* Channel #8 is used for ARM platform direct access to the display. This field defines the base
|
|
* address of the second region accessible on the display
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8 (0) //!< Bit position for IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8.
|
|
#define BM_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8 (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8) >> BP_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8.
|
|
#define BF_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8) & BM_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NEW_ADDR_SPACE_SA_8 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8(x, v) (HW_IPU_DC_WR_CH_CONF2_8_WR(x, (HW_IPU_DC_WR_CH_CONF2_8_RD(x) & ~BM_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8) | BF_IPU_DC_WR_CH_CONF2_8_NEW_ADDR_SPACE_SA_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL1_CH_8 - DC Routine Link Register 1 Channel 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_8 - DC Routine Link Register 1 Channel 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl1_ch_8_bitfields
|
|
{
|
|
unsigned COD_NEW_ADDR_PRIORITY_CHAN_8 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #8, both regions)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_W_8_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #8, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_W_8_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #8, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl1_ch_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL1_CH_8_ADDR(x) (REGS_IPU_BASE(x) + 0x5809c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL1_CH_8(x) (*(volatile hw_ipu_dc_rl1_ch_8_t *) HW_IPU_DC_RL1_CH_8_ADDR(x))
|
|
#define HW_IPU_DC_RL1_CH_8_RD(x) (HW_IPU_DC_RL1_CH_8(x).U)
|
|
#define HW_IPU_DC_RL1_CH_8_WR(x, v) (HW_IPU_DC_RL1_CH_8(x).U = (v))
|
|
#define HW_IPU_DC_RL1_CH_8_SET(x, v) (HW_IPU_DC_RL1_CH_8_WR(x, HW_IPU_DC_RL1_CH_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL1_CH_8_CLR(x, v) (HW_IPU_DC_RL1_CH_8_WR(x, HW_IPU_DC_RL1_CH_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL1_CH_8_TOG(x, v) (HW_IPU_DC_RL1_CH_8_WR(x, HW_IPU_DC_RL1_CH_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL1_CH_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_8, field COD_NEW_ADDR_PRIORITY_CHAN_8[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new address event (associated with channel #8, both
|
|
* regions) The priority between the events should be set to a unique value. i.e. two events must
|
|
* not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8 (0) //!< Bit position for IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8.
|
|
#define BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8) >> BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8.
|
|
#define BF_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8) & BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_8 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8(x, v) (HW_IPU_DC_RL1_CH_8_WR(x, (HW_IPU_DC_RL1_CH_8_RD(x) & ~BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8) | BF_IPU_DC_RL1_CH_8_COD_NEW_ADDR_PRIORITY_CHAN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_8, field COD_NEW_ADDR_START_CHAN_W_8_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #8, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0 (8) //!< Bit position for IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0.
|
|
#define BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0) >> BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0.
|
|
#define BF_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0) & BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_W_8_0 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0(x, v) (HW_IPU_DC_RL1_CH_8_WR(x, (HW_IPU_DC_RL1_CH_8_RD(x) & ~BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0) | BF_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_8, field COD_NEW_ADDR_START_CHAN_W_8_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #8, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1 (24) //!< Bit position for IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1.
|
|
#define BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1) >> BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1.
|
|
#define BF_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1) & BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_W_8_1 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1(x, v) (HW_IPU_DC_RL1_CH_8_WR(x, (HW_IPU_DC_RL1_CH_8_RD(x) & ~BM_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1) | BF_IPU_DC_RL1_CH_8_COD_NEW_ADDR_START_CHAN_W_8_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_8 - DC Routine Link Register 2 Channel 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_8 - DC Routine Link Register 2 Channel 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_8_bitfields
|
|
{
|
|
unsigned COD_NEW_CHAN_PRIORITY_CHAN_8 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #8, both regions)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_W_8_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #8, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_W_8_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #8, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_8_ADDR(x) (REGS_IPU_BASE(x) + 0x580a0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_8(x) (*(volatile hw_ipu_dc_rl2_ch_8_t *) HW_IPU_DC_RL2_CH_8_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_8_RD(x) (HW_IPU_DC_RL2_CH_8(x).U)
|
|
#define HW_IPU_DC_RL2_CH_8_WR(x, v) (HW_IPU_DC_RL2_CH_8(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_8_SET(x, v) (HW_IPU_DC_RL2_CH_8_WR(x, HW_IPU_DC_RL2_CH_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_8_CLR(x, v) (HW_IPU_DC_RL2_CH_8_WR(x, HW_IPU_DC_RL2_CH_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_8_TOG(x, v) (HW_IPU_DC_RL2_CH_8_WR(x, HW_IPU_DC_RL2_CH_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_8, field COD_NEW_CHAN_PRIORITY_CHAN_8[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new address event (associated with channel #8, both
|
|
* regions) The priority between the events should be set to a unique value. i.e. two events must
|
|
* not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8 (0) //!< Bit position for IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8.
|
|
#define BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8) >> BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8.
|
|
#define BF_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8) & BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_8 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8(x, v) (HW_IPU_DC_RL2_CH_8_WR(x, (HW_IPU_DC_RL2_CH_8_RD(x) & ~BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8) | BF_IPU_DC_RL2_CH_8_COD_NEW_CHAN_PRIORITY_CHAN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_8, field COD_NEW_CHAN_START_CHAN_W_8_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #8, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0 (8) //!< Bit position for IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0.
|
|
#define BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0) >> BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0.
|
|
#define BF_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0) & BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_W_8_0 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0(x, v) (HW_IPU_DC_RL2_CH_8_WR(x, (HW_IPU_DC_RL2_CH_8_RD(x) & ~BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0) | BF_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_8, field COD_NEW_CHAN_START_CHAN_W_8_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #8, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1 (24) //!< Bit position for IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1.
|
|
#define BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1) >> BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1.
|
|
#define BF_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1) & BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_W_8_1 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1(x, v) (HW_IPU_DC_RL2_CH_8_WR(x, (HW_IPU_DC_RL2_CH_8_RD(x) & ~BM_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1) | BF_IPU_DC_RL2_CH_8_COD_NEW_CHAN_START_CHAN_W_8_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL3_CH_8 - DC Routine Link Register 3 Channel 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL3_CH_8 - DC Routine Link Register 3 Channel 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl3_ch_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl3_ch_8_bitfields
|
|
{
|
|
unsigned COD_NEW_DATA_PRIORITY_CHAN_8 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #8, both regions)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_W_8_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #8, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_W_8_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #8,second region)
|
|
} B;
|
|
} hw_ipu_dc_rl3_ch_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL3_CH_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL3_CH_8_ADDR(x) (REGS_IPU_BASE(x) + 0x580a4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL3_CH_8(x) (*(volatile hw_ipu_dc_rl3_ch_8_t *) HW_IPU_DC_RL3_CH_8_ADDR(x))
|
|
#define HW_IPU_DC_RL3_CH_8_RD(x) (HW_IPU_DC_RL3_CH_8(x).U)
|
|
#define HW_IPU_DC_RL3_CH_8_WR(x, v) (HW_IPU_DC_RL3_CH_8(x).U = (v))
|
|
#define HW_IPU_DC_RL3_CH_8_SET(x, v) (HW_IPU_DC_RL3_CH_8_WR(x, HW_IPU_DC_RL3_CH_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL3_CH_8_CLR(x, v) (HW_IPU_DC_RL3_CH_8_WR(x, HW_IPU_DC_RL3_CH_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL3_CH_8_TOG(x, v) (HW_IPU_DC_RL3_CH_8_WR(x, HW_IPU_DC_RL3_CH_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL3_CH_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_8, field COD_NEW_DATA_PRIORITY_CHAN_8[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new address event (associated with channel #8, both
|
|
* regions) The priority between the events should be set to a unique value. i.e. two events must
|
|
* not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8 (0) //!< Bit position for IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8.
|
|
#define BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8.
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|
|
|
//! @brief Get value of IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8) >> BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8.
|
|
#define BF_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8) & BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_8 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8(x, v) (HW_IPU_DC_RL3_CH_8_WR(x, (HW_IPU_DC_RL3_CH_8_RD(x) & ~BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8) | BF_IPU_DC_RL3_CH_8_COD_NEW_DATA_PRIORITY_CHAN_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_8, field COD_NEW_DATA_START_CHAN_W_8_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #8, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0 (8) //!< Bit position for IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0.
|
|
#define BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0.
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|
|
|
//! @brief Get value of IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0) >> BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0.
|
|
#define BF_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0) & BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_W_8_0 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0(x, v) (HW_IPU_DC_RL3_CH_8_WR(x, (HW_IPU_DC_RL3_CH_8_RD(x) & ~BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0) | BF_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL3_CH_8, field COD_NEW_DATA_START_CHAN_W_8_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #8,second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1 (24) //!< Bit position for IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1.
|
|
#define BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1 from a register value.
|
|
#define BG_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1) >> BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1.
|
|
#define BF_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1) & BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_W_8_1 field to a new value.
|
|
#define BW_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1(x, v) (HW_IPU_DC_RL3_CH_8_WR(x, (HW_IPU_DC_RL3_CH_8_RD(x) & ~BM_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1) | BF_IPU_DC_RL3_CH_8_COD_NEW_DATA_START_CHAN_W_8_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL4_CH_8 - DC Routine Link Register 4 Channel 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL4_CH_8 - DC Routine Link Register 4 Channel 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl4_ch_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl4_ch_8_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_R_8_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #8, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_ADDR_START_CHAN_R_8_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #8, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl4_ch_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL4_CH_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL4_CH_8_ADDR(x) (REGS_IPU_BASE(x) + 0x580a8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL4_CH_8(x) (*(volatile hw_ipu_dc_rl4_ch_8_t *) HW_IPU_DC_RL4_CH_8_ADDR(x))
|
|
#define HW_IPU_DC_RL4_CH_8_RD(x) (HW_IPU_DC_RL4_CH_8(x).U)
|
|
#define HW_IPU_DC_RL4_CH_8_WR(x, v) (HW_IPU_DC_RL4_CH_8(x).U = (v))
|
|
#define HW_IPU_DC_RL4_CH_8_SET(x, v) (HW_IPU_DC_RL4_CH_8_WR(x, HW_IPU_DC_RL4_CH_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL4_CH_8_CLR(x, v) (HW_IPU_DC_RL4_CH_8_WR(x, HW_IPU_DC_RL4_CH_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL4_CH_8_TOG(x, v) (HW_IPU_DC_RL4_CH_8_WR(x, HW_IPU_DC_RL4_CH_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_8, field COD_NEW_ADDR_START_CHAN_R_8_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #8, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0 (8) //!< Bit position for IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0.
|
|
#define BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0) >> BP_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0.
|
|
#define BF_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0) & BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_R_8_0 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0(x, v) (HW_IPU_DC_RL4_CH_8_WR(x, (HW_IPU_DC_RL4_CH_8_RD(x) & ~BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0) | BF_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL4_CH_8, field COD_NEW_ADDR_START_CHAN_R_8_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #8, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1 (24) //!< Bit position for IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1.
|
|
#define BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1 (0xff000000) //!< Bit mask for IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1 from a register value.
|
|
#define BG_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1) >> BP_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1.
|
|
#define BF_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1) & BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_R_8_1 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1(x, v) (HW_IPU_DC_RL4_CH_8_WR(x, (HW_IPU_DC_RL4_CH_8_RD(x) & ~BM_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1) | BF_IPU_DC_RL4_CH_8_COD_NEW_ADDR_START_CHAN_R_8_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL5_CH_8 - DC Routine Link Register 5 Channel 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL5_CH_8 - DC Routine Link Register 5 Channel 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl5_ch_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl5_ch_8_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_R_8_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #8, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_R_8_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #8, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl5_ch_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL5_CH_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL5_CH_8_ADDR(x) (REGS_IPU_BASE(x) + 0x580ac)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL5_CH_8(x) (*(volatile hw_ipu_dc_rl5_ch_8_t *) HW_IPU_DC_RL5_CH_8_ADDR(x))
|
|
#define HW_IPU_DC_RL5_CH_8_RD(x) (HW_IPU_DC_RL5_CH_8(x).U)
|
|
#define HW_IPU_DC_RL5_CH_8_WR(x, v) (HW_IPU_DC_RL5_CH_8(x).U = (v))
|
|
#define HW_IPU_DC_RL5_CH_8_SET(x, v) (HW_IPU_DC_RL5_CH_8_WR(x, HW_IPU_DC_RL5_CH_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL5_CH_8_CLR(x, v) (HW_IPU_DC_RL5_CH_8_WR(x, HW_IPU_DC_RL5_CH_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL5_CH_8_TOG(x, v) (HW_IPU_DC_RL5_CH_8_WR(x, HW_IPU_DC_RL5_CH_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL5_CH_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL5_CH_8, field COD_NEW_CHAN_START_CHAN_R_8_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #8, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0 (8) //!< Bit position for IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0.
|
|
#define BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0 from a register value.
|
|
#define BG_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0) >> BP_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0.
|
|
#define BF_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0) & BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_R_8_0 field to a new value.
|
|
#define BW_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0(x, v) (HW_IPU_DC_RL5_CH_8_WR(x, (HW_IPU_DC_RL5_CH_8_RD(x) & ~BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0) | BF_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL5_CH_8, field COD_NEW_CHAN_START_CHAN_R_8_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #8, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1 (24) //!< Bit position for IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1.
|
|
#define BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1 (0xff000000) //!< Bit mask for IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1 from a register value.
|
|
#define BG_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1) >> BP_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1.
|
|
#define BF_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1) & BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_R_8_1 field to a new value.
|
|
#define BW_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1(x, v) (HW_IPU_DC_RL5_CH_8_WR(x, (HW_IPU_DC_RL5_CH_8_RD(x) & ~BM_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1) | BF_IPU_DC_RL5_CH_8_COD_NEW_CHAN_START_CHAN_R_8_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL6_CH_8 - DC Routine Link Register 6 Channel 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL6_CH_8 - DC Routine Link Register 6 Channel 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl6_ch_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl6_ch_8_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_R_8_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #8, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_DATA_START_CHAN_R_8_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #8, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl6_ch_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL6_CH_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL6_CH_8_ADDR(x) (REGS_IPU_BASE(x) + 0x580b0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL6_CH_8(x) (*(volatile hw_ipu_dc_rl6_ch_8_t *) HW_IPU_DC_RL6_CH_8_ADDR(x))
|
|
#define HW_IPU_DC_RL6_CH_8_RD(x) (HW_IPU_DC_RL6_CH_8(x).U)
|
|
#define HW_IPU_DC_RL6_CH_8_WR(x, v) (HW_IPU_DC_RL6_CH_8(x).U = (v))
|
|
#define HW_IPU_DC_RL6_CH_8_SET(x, v) (HW_IPU_DC_RL6_CH_8_WR(x, HW_IPU_DC_RL6_CH_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL6_CH_8_CLR(x, v) (HW_IPU_DC_RL6_CH_8_WR(x, HW_IPU_DC_RL6_CH_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL6_CH_8_TOG(x, v) (HW_IPU_DC_RL6_CH_8_WR(x, HW_IPU_DC_RL6_CH_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL6_CH_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL6_CH_8, field COD_NEW_DATA_START_CHAN_R_8_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #8, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0 (8) //!< Bit position for IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0.
|
|
#define BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0 from a register value.
|
|
#define BG_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0) >> BP_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0.
|
|
#define BF_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0) & BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_R_8_0 field to a new value.
|
|
#define BW_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0(x, v) (HW_IPU_DC_RL6_CH_8_WR(x, (HW_IPU_DC_RL6_CH_8_RD(x) & ~BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0) | BF_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL6_CH_8, field COD_NEW_DATA_START_CHAN_R_8_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #8, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1 (24) //!< Bit position for IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1.
|
|
#define BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1 (0xff000000) //!< Bit mask for IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1 from a register value.
|
|
#define BG_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1) >> BP_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1.
|
|
#define BF_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1) & BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_R_8_1 field to a new value.
|
|
#define BW_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1(x, v) (HW_IPU_DC_RL6_CH_8_WR(x, (HW_IPU_DC_RL6_CH_8_RD(x) & ~BM_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1) | BF_IPU_DC_RL6_CH_8_COD_NEW_DATA_START_CHAN_R_8_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF1_9 - DC Write Channel 9 Configuration 1Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF1_9 - DC Write Channel 9 Configuration 1Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf1_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf1_9_bitfields
|
|
{
|
|
unsigned W_SIZE_9 : 2; //!< [1:0] Word Size associated with channel #9
|
|
unsigned CHAN_MASK_DEFAULT_9 : 1; //!< [2] Event mask bit for channel #9
|
|
unsigned MCU_DISP_ID_9 : 2; //!< [4:3] The field defines which one of the 4 displays is associated with channel #9.
|
|
unsigned RESERVED0 : 27; //!< [31:5] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf1_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF1_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF1_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580b4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF1_9(x) (*(volatile hw_ipu_dc_wr_ch_conf1_9_t *) HW_IPU_DC_WR_CH_CONF1_9_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF1_9_RD(x) (HW_IPU_DC_WR_CH_CONF1_9(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF1_9_WR(x, v) (HW_IPU_DC_WR_CH_CONF1_9(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF1_9_SET(x, v) (HW_IPU_DC_WR_CH_CONF1_9_WR(x, HW_IPU_DC_WR_CH_CONF1_9_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF1_9_CLR(x, v) (HW_IPU_DC_WR_CH_CONF1_9_WR(x, HW_IPU_DC_WR_CH_CONF1_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF1_9_TOG(x, v) (HW_IPU_DC_WR_CH_CONF1_9_WR(x, HW_IPU_DC_WR_CH_CONF1_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF1_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF1_9, field W_SIZE_9[1:0] (RW)
|
|
*
|
|
* Word Size associated with channel #9 The data coming from the IDMAC is 32bit wide. This field
|
|
* defines the size of the word used by the DC
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bits are used - a 32 bit words includes 4X8bit valid words.
|
|
* - 01 - 16 LSB bits - a 32 bit words includes 2 X16bit valid words.
|
|
* - 10 - 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC
|
|
* - 11 - 32 bits are used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF1_9_W_SIZE_9 (0) //!< Bit position for IPU_DC_WR_CH_CONF1_9_W_SIZE_9.
|
|
#define BM_IPU_DC_WR_CH_CONF1_9_W_SIZE_9 (0x00000003) //!< Bit mask for IPU_DC_WR_CH_CONF1_9_W_SIZE_9.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF1_9_W_SIZE_9 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF1_9_W_SIZE_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF1_9_W_SIZE_9) >> BP_IPU_DC_WR_CH_CONF1_9_W_SIZE_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF1_9_W_SIZE_9.
|
|
#define BF_IPU_DC_WR_CH_CONF1_9_W_SIZE_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF1_9_W_SIZE_9) & BM_IPU_DC_WR_CH_CONF1_9_W_SIZE_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the W_SIZE_9 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF1_9_W_SIZE_9(x, v) (HW_IPU_DC_WR_CH_CONF1_9_WR(x, (HW_IPU_DC_WR_CH_CONF1_9_RD(x) & ~BM_IPU_DC_WR_CH_CONF1_9_W_SIZE_9) | BF_IPU_DC_WR_CH_CONF1_9_W_SIZE_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF1_9, field CHAN_MASK_DEFAULT_9[2] (RW)
|
|
*
|
|
* Event mask bit for channel #9 When more then one event is used during a flow (EOF, EOL, NL, NF,
|
|
* EOFIELD, etc.) masks all the event besides the event that is defined as the highest priority
|
|
* event
|
|
*
|
|
* Values:
|
|
* - 0 - Only the highest priority event is used, the rest are masked
|
|
* - 1 - All the events are used - no mask
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9 (2) //!< Bit position for IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9.
|
|
#define BM_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9 (0x00000004) //!< Bit mask for IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9) >> BP_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9.
|
|
#define BF_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9) & BM_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the CHAN_MASK_DEFAULT_9 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9(x, v) (HW_IPU_DC_WR_CH_CONF1_9_WR(x, (HW_IPU_DC_WR_CH_CONF1_9_RD(x) & ~BM_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9) | BF_IPU_DC_WR_CH_CONF1_9_CHAN_MASK_DEFAULT_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF1_9, field MCU_DISP_ID_9[4:3] (RW)
|
|
*
|
|
* The field defines which one of the 4 displays is associated with channel #9.
|
|
*
|
|
* Values:
|
|
* - 00 - display #0
|
|
* - 01 - display #1
|
|
* - 10 - display #2
|
|
* - 11 - display #3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9 (3) //!< Bit position for IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9.
|
|
#define BM_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9 (0x00000018) //!< Bit mask for IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9) >> BP_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9.
|
|
#define BF_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9) & BM_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_DISP_ID_9 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9(x, v) (HW_IPU_DC_WR_CH_CONF1_9_WR(x, (HW_IPU_DC_WR_CH_CONF1_9_RD(x) & ~BM_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9) | BF_IPU_DC_WR_CH_CONF1_9_MCU_DISP_ID_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_CONF2_9 - DC Write Channel 9Configuration 2Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_CONF2_9 - DC Write Channel 9Configuration 2Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_conf2_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_conf2_9_bitfields
|
|
{
|
|
unsigned NEW_ADDR_SPACE_SA_9 : 29; //!< [28:0] Channel #8 is used for ARM platform direct access to the display.
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_conf2_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_CONF2_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_CONF2_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580b8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_CONF2_9(x) (*(volatile hw_ipu_dc_wr_ch_conf2_9_t *) HW_IPU_DC_WR_CH_CONF2_9_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_CONF2_9_RD(x) (HW_IPU_DC_WR_CH_CONF2_9(x).U)
|
|
#define HW_IPU_DC_WR_CH_CONF2_9_WR(x, v) (HW_IPU_DC_WR_CH_CONF2_9(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_CONF2_9_SET(x, v) (HW_IPU_DC_WR_CH_CONF2_9_WR(x, HW_IPU_DC_WR_CH_CONF2_9_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_CONF2_9_CLR(x, v) (HW_IPU_DC_WR_CH_CONF2_9_WR(x, HW_IPU_DC_WR_CH_CONF2_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_CONF2_9_TOG(x, v) (HW_IPU_DC_WR_CH_CONF2_9_WR(x, HW_IPU_DC_WR_CH_CONF2_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_CONF2_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_CONF2_9, field NEW_ADDR_SPACE_SA_9[28:0] (RW)
|
|
*
|
|
* Channel #8 is used for ARM platform direct access to the display. This field defines the base
|
|
* address of the second region accessible on the display
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9 (0) //!< Bit position for IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9.
|
|
#define BM_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9 (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9 from a register value.
|
|
#define BG_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9) >> BP_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9.
|
|
#define BF_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9) & BM_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9)
|
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NEW_ADDR_SPACE_SA_9 field to a new value.
|
|
#define BW_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9(x, v) (HW_IPU_DC_WR_CH_CONF2_9_WR(x, (HW_IPU_DC_WR_CH_CONF2_9_RD(x) & ~BM_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9) | BF_IPU_DC_WR_CH_CONF2_9_NEW_ADDR_SPACE_SA_9(v)))
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|
#endif
|
|
//@}
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|
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//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL1_CH_9 - DC Routine Link Register 1 Channel 9
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL1_CH_9 - DC Routine Link Register 1 Channel 9 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl1_ch_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl1_ch_9_bitfields
|
|
{
|
|
unsigned COD_NEW_ADDR_PRIORITY_CHAN_9 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #9, both regions)
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|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
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|
unsigned COD_NEW_ADDR_START_CHAN_W_9_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #9, first region)
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unsigned RESERVED1 : 8; //!< [23:16] Reserved.
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|
unsigned COD_NEW_ADDR_START_CHAN_W_9_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #9, second region)
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} B;
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|
} hw_ipu_dc_rl1_ch_9_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_DC_RL1_CH_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL1_CH_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580bc)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL1_CH_9(x) (*(volatile hw_ipu_dc_rl1_ch_9_t *) HW_IPU_DC_RL1_CH_9_ADDR(x))
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#define HW_IPU_DC_RL1_CH_9_RD(x) (HW_IPU_DC_RL1_CH_9(x).U)
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#define HW_IPU_DC_RL1_CH_9_WR(x, v) (HW_IPU_DC_RL1_CH_9(x).U = (v))
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#define HW_IPU_DC_RL1_CH_9_SET(x, v) (HW_IPU_DC_RL1_CH_9_WR(x, HW_IPU_DC_RL1_CH_9_RD(x) | (v)))
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#define HW_IPU_DC_RL1_CH_9_CLR(x, v) (HW_IPU_DC_RL1_CH_9_WR(x, HW_IPU_DC_RL1_CH_9_RD(x) & ~(v)))
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#define HW_IPU_DC_RL1_CH_9_TOG(x, v) (HW_IPU_DC_RL1_CH_9_WR(x, HW_IPU_DC_RL1_CH_9_RD(x) ^ (v)))
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#endif
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|
//@}
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|
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/*
|
|
* constants & macros for individual IPU_DC_RL1_CH_9 bitfields
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|
*/
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|
/*! @name Register IPU_DC_RL1_CH_9, field COD_NEW_ADDR_PRIORITY_CHAN_9[3:0] (RW)
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|
*
|
|
* This field defines the priority of the new address event (associated with channel #9, both
|
|
* regions) The priority between the events should be set to a unique value. i.e. two events must
|
|
* not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9 (0) //!< Bit position for IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9.
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|
#define BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9 (0x0000000f) //!< Bit mask for IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9.
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//! @brief Get value of IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9 from a register value.
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|
#define BG_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9) >> BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9)
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//! @brief Format value for bitfield IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9.
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|
#define BF_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9) & BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_PRIORITY_CHAN_9 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9(x, v) (HW_IPU_DC_RL1_CH_9_WR(x, (HW_IPU_DC_RL1_CH_9_RD(x) & ~BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9) | BF_IPU_DC_RL1_CH_9_COD_NEW_ADDR_PRIORITY_CHAN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_9, field COD_NEW_ADDR_START_CHAN_W_9_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #9, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0 (8) //!< Bit position for IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0.
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|
#define BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0.
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|
|
|
//! @brief Get value of IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0) >> BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0.
|
|
#define BF_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0) & BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_W_9_0 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0(x, v) (HW_IPU_DC_RL1_CH_9_WR(x, (HW_IPU_DC_RL1_CH_9_RD(x) & ~BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0) | BF_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL1_CH_9, field COD_NEW_ADDR_START_CHAN_W_9_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #9, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1 (24) //!< Bit position for IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1.
|
|
#define BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1 (0xff000000) //!< Bit mask for IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1.
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|
|
|
//! @brief Get value of IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1 from a register value.
|
|
#define BG_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1) >> BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1)
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|
|
|
//! @brief Format value for bitfield IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1.
|
|
#define BF_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1) & BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_W_9_1 field to a new value.
|
|
#define BW_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1(x, v) (HW_IPU_DC_RL1_CH_9_WR(x, (HW_IPU_DC_RL1_CH_9_RD(x) & ~BM_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1) | BF_IPU_DC_RL1_CH_9_COD_NEW_ADDR_START_CHAN_W_9_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL2_CH_9 - DC Routine Link Register 2 Channel 9
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL2_CH_9 - DC Routine Link Register 2 Channel 9 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl2_ch_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl2_ch_9_bitfields
|
|
{
|
|
unsigned COD_NEW_CHAN_PRIORITY_CHAN_9 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #9, both regions)
|
|
unsigned RESERVED0 : 4; //!< [7:4] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_W_9_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #9, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_W_9_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #9, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl2_ch_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL2_CH_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL2_CH_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580c0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL2_CH_9(x) (*(volatile hw_ipu_dc_rl2_ch_9_t *) HW_IPU_DC_RL2_CH_9_ADDR(x))
|
|
#define HW_IPU_DC_RL2_CH_9_RD(x) (HW_IPU_DC_RL2_CH_9(x).U)
|
|
#define HW_IPU_DC_RL2_CH_9_WR(x, v) (HW_IPU_DC_RL2_CH_9(x).U = (v))
|
|
#define HW_IPU_DC_RL2_CH_9_SET(x, v) (HW_IPU_DC_RL2_CH_9_WR(x, HW_IPU_DC_RL2_CH_9_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL2_CH_9_CLR(x, v) (HW_IPU_DC_RL2_CH_9_WR(x, HW_IPU_DC_RL2_CH_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL2_CH_9_TOG(x, v) (HW_IPU_DC_RL2_CH_9_WR(x, HW_IPU_DC_RL2_CH_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL2_CH_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_9, field COD_NEW_CHAN_PRIORITY_CHAN_9[3:0] (RW)
|
|
*
|
|
* This field defines the priority of the new address event (associated with channel #9, both
|
|
* regions) The priority between the events should be set to a unique value. i.e. two events must
|
|
* not have the same priority (except 0000 - disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9 (0) //!< Bit position for IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9.
|
|
#define BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9 (0x0000000f) //!< Bit mask for IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9) >> BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9.
|
|
#define BF_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9) & BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_PRIORITY_CHAN_9 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9(x, v) (HW_IPU_DC_RL2_CH_9_WR(x, (HW_IPU_DC_RL2_CH_9_RD(x) & ~BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9) | BF_IPU_DC_RL2_CH_9_COD_NEW_CHAN_PRIORITY_CHAN_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_9, field COD_NEW_CHAN_START_CHAN_W_9_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #9, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0 (8) //!< Bit position for IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0.
|
|
#define BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0) >> BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0.
|
|
#define BF_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0) & BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_W_9_0 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0(x, v) (HW_IPU_DC_RL2_CH_9_WR(x, (HW_IPU_DC_RL2_CH_9_RD(x) & ~BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0) | BF_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_RL2_CH_9, field COD_NEW_CHAN_START_CHAN_W_9_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #9, second region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1 (24) //!< Bit position for IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1.
|
|
#define BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1 (0xff000000) //!< Bit mask for IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1.
|
|
|
|
//! @brief Get value of IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1 from a register value.
|
|
#define BG_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1) >> BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1.
|
|
#define BF_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1) & BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_CHAN_START_CHAN_W_9_1 field to a new value.
|
|
#define BW_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1(x, v) (HW_IPU_DC_RL2_CH_9_WR(x, (HW_IPU_DC_RL2_CH_9_RD(x) & ~BM_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1) | BF_IPU_DC_RL2_CH_9_COD_NEW_CHAN_START_CHAN_W_9_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_RL3_CH_9 - DC Routine Link Register 3Channel 9
|
|
//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DC_RL3_CH_9 - DC Routine Link Register 3Channel 9 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_rl3_ch_9
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{
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reg32_t U;
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struct _hw_ipu_dc_rl3_ch_9_bitfields
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{
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unsigned COD_NEW_DATA_PRIORITY_CHAN_9 : 4; //!< [3:0] This field defines the priority of the new address event (associated with channel #9, both regions)
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unsigned RESERVED0 : 4; //!< [7:4] Reserved.
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unsigned COD_NEW_DATA_START_CHAN_W_9_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #9, first region)
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unsigned RESERVED1 : 8; //!< [23:16] Reserved.
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unsigned COD_NEW_DATA_START_CHAN_W_9_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #9, second region)
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} B;
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} hw_ipu_dc_rl3_ch_9_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DC_RL3_CH_9 register
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*/
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//@{
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#define HW_IPU_DC_RL3_CH_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580c4)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL3_CH_9(x) (*(volatile hw_ipu_dc_rl3_ch_9_t *) HW_IPU_DC_RL3_CH_9_ADDR(x))
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#define HW_IPU_DC_RL3_CH_9_RD(x) (HW_IPU_DC_RL3_CH_9(x).U)
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#define HW_IPU_DC_RL3_CH_9_WR(x, v) (HW_IPU_DC_RL3_CH_9(x).U = (v))
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#define HW_IPU_DC_RL3_CH_9_SET(x, v) (HW_IPU_DC_RL3_CH_9_WR(x, HW_IPU_DC_RL3_CH_9_RD(x) | (v)))
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#define HW_IPU_DC_RL3_CH_9_CLR(x, v) (HW_IPU_DC_RL3_CH_9_WR(x, HW_IPU_DC_RL3_CH_9_RD(x) & ~(v)))
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#define HW_IPU_DC_RL3_CH_9_TOG(x, v) (HW_IPU_DC_RL3_CH_9_WR(x, HW_IPU_DC_RL3_CH_9_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DC_RL3_CH_9 bitfields
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*/
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/*! @name Register IPU_DC_RL3_CH_9, field COD_NEW_DATA_PRIORITY_CHAN_9[3:0] (RW)
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*
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* This field defines the priority of the new address event (associated with channel #9, both
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* regions) The priority between the events should be set to a unique value. i.e. two events must
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* not have the same priority (except 0000 - disable)
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*
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* Values:
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* - 0000 - disable
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* - 0001 - Priority #1 (lowest)
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* - 0010 - Priority #2
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* - 1101 - Priority #13 (highest)
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* - 1110 - Reserved
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* - 1111 - Reserved
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*/
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//@{
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#define BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9 (0) //!< Bit position for IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9.
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#define BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9 (0x0000000f) //!< Bit mask for IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9.
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//! @brief Get value of IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9 from a register value.
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#define BG_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9) >> BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9.
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#define BF_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9) & BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_DATA_PRIORITY_CHAN_9 field to a new value.
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#define BW_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9(x, v) (HW_IPU_DC_RL3_CH_9_WR(x, (HW_IPU_DC_RL3_CH_9_RD(x) & ~BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9) | BF_IPU_DC_RL3_CH_9_COD_NEW_DATA_PRIORITY_CHAN_9(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL3_CH_9, field COD_NEW_DATA_START_CHAN_W_9_0[15:8] (RW)
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*
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* This field is a pointer to the address within the microcode memory where the routine that handles
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* the new data event resides (associated with channel #9, first region)
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*/
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//@{
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#define BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0 (8) //!< Bit position for IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0.
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#define BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0.
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//! @brief Get value of IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0 from a register value.
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#define BG_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0) >> BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0.
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#define BF_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0) & BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_DATA_START_CHAN_W_9_0 field to a new value.
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#define BW_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0(x, v) (HW_IPU_DC_RL3_CH_9_WR(x, (HW_IPU_DC_RL3_CH_9_RD(x) & ~BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0) | BF_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_0(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL3_CH_9, field COD_NEW_DATA_START_CHAN_W_9_1[31:24] (RW)
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*
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* This field is a pointer to the address within the microcode memory where the routine that handles
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* the new data event resides (associated with channel #9, second region)
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*/
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//@{
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#define BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1 (24) //!< Bit position for IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1.
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#define BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1 (0xff000000) //!< Bit mask for IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1.
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//! @brief Get value of IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1 from a register value.
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#define BG_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1) >> BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1)
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//! @brief Format value for bitfield IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1.
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#define BF_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1) & BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_DATA_START_CHAN_W_9_1 field to a new value.
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#define BW_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1(x, v) (HW_IPU_DC_RL3_CH_9_WR(x, (HW_IPU_DC_RL3_CH_9_RD(x) & ~BM_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1) | BF_IPU_DC_RL3_CH_9_COD_NEW_DATA_START_CHAN_W_9_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_RL4_CH_9 - DC Routine Link Register 4 Channel 9
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DC_RL4_CH_9 - DC Routine Link Register 4 Channel 9 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_rl4_ch_9
|
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{
|
|
reg32_t U;
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|
struct _hw_ipu_dc_rl4_ch_9_bitfields
|
|
{
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unsigned RESERVED0 : 8; //!< [7:0] Reserved.
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unsigned COD_NEW_ADDR_START_CHAN_R_9_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #9, first region)
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unsigned RESERVED1 : 8; //!< [23:16] Reserved.
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unsigned COD_NEW_ADDR_START_CHAN_R_9_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new address event resides (associated with channel #9, second region)
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} B;
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} hw_ipu_dc_rl4_ch_9_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DC_RL4_CH_9 register
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*/
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//@{
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#define HW_IPU_DC_RL4_CH_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580c8)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL4_CH_9(x) (*(volatile hw_ipu_dc_rl4_ch_9_t *) HW_IPU_DC_RL4_CH_9_ADDR(x))
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#define HW_IPU_DC_RL4_CH_9_RD(x) (HW_IPU_DC_RL4_CH_9(x).U)
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#define HW_IPU_DC_RL4_CH_9_WR(x, v) (HW_IPU_DC_RL4_CH_9(x).U = (v))
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#define HW_IPU_DC_RL4_CH_9_SET(x, v) (HW_IPU_DC_RL4_CH_9_WR(x, HW_IPU_DC_RL4_CH_9_RD(x) | (v)))
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#define HW_IPU_DC_RL4_CH_9_CLR(x, v) (HW_IPU_DC_RL4_CH_9_WR(x, HW_IPU_DC_RL4_CH_9_RD(x) & ~(v)))
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#define HW_IPU_DC_RL4_CH_9_TOG(x, v) (HW_IPU_DC_RL4_CH_9_WR(x, HW_IPU_DC_RL4_CH_9_RD(x) ^ (v)))
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#endif
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//@}
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|
|
/*
|
|
* constants & macros for individual IPU_DC_RL4_CH_9 bitfields
|
|
*/
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|
/*! @name Register IPU_DC_RL4_CH_9, field COD_NEW_ADDR_START_CHAN_R_9_0[15:8] (RW)
|
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*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new address event resides (associated with channel #9, first region)
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*/
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//@{
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#define BP_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0 (8) //!< Bit position for IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0.
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#define BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0.
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//! @brief Get value of IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0 from a register value.
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#define BG_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0) >> BP_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0)
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//! @brief Format value for bitfield IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0.
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#define BF_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0) & BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_ADDR_START_CHAN_R_9_0 field to a new value.
|
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#define BW_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0(x, v) (HW_IPU_DC_RL4_CH_9_WR(x, (HW_IPU_DC_RL4_CH_9_RD(x) & ~BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0) | BF_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_0(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL4_CH_9, field COD_NEW_ADDR_START_CHAN_R_9_1[31:24] (RW)
|
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*
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* This field is a pointer to the address within the microcode memory where the routine that handles
|
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* the new address event resides (associated with channel #9, second region)
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*/
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//@{
|
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#define BP_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1 (24) //!< Bit position for IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1.
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#define BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1 (0xff000000) //!< Bit mask for IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1.
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//! @brief Get value of IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1 from a register value.
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#define BG_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1) >> BP_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1)
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//! @brief Format value for bitfield IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1.
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#define BF_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1) & BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1)
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|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_ADDR_START_CHAN_R_9_1 field to a new value.
|
|
#define BW_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1(x, v) (HW_IPU_DC_RL4_CH_9_WR(x, (HW_IPU_DC_RL4_CH_9_RD(x) & ~BM_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1) | BF_IPU_DC_RL4_CH_9_COD_NEW_ADDR_START_CHAN_R_9_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
|
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// HW_IPU_DC_RL5_CH_9 - DC Routine Link Register 5 Channel 9
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_RL5_CH_9 - DC Routine Link Register 5 Channel 9 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_rl5_ch_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_rl5_ch_9_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_R_9_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #9, first region)
|
|
unsigned RESERVED1 : 8; //!< [23:16] Reserved.
|
|
unsigned COD_NEW_CHAN_START_CHAN_R_9_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new channel event resides (associated with channel #9, second region)
|
|
} B;
|
|
} hw_ipu_dc_rl5_ch_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_RL5_CH_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_RL5_CH_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580cc)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_RL5_CH_9(x) (*(volatile hw_ipu_dc_rl5_ch_9_t *) HW_IPU_DC_RL5_CH_9_ADDR(x))
|
|
#define HW_IPU_DC_RL5_CH_9_RD(x) (HW_IPU_DC_RL5_CH_9(x).U)
|
|
#define HW_IPU_DC_RL5_CH_9_WR(x, v) (HW_IPU_DC_RL5_CH_9(x).U = (v))
|
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#define HW_IPU_DC_RL5_CH_9_SET(x, v) (HW_IPU_DC_RL5_CH_9_WR(x, HW_IPU_DC_RL5_CH_9_RD(x) | (v)))
|
|
#define HW_IPU_DC_RL5_CH_9_CLR(x, v) (HW_IPU_DC_RL5_CH_9_WR(x, HW_IPU_DC_RL5_CH_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_RL5_CH_9_TOG(x, v) (HW_IPU_DC_RL5_CH_9_WR(x, HW_IPU_DC_RL5_CH_9_RD(x) ^ (v)))
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#endif
|
|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DC_RL5_CH_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_RL5_CH_9, field COD_NEW_CHAN_START_CHAN_R_9_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new channel event resides (associated with channel #9, first region)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0 (8) //!< Bit position for IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0.
|
|
#define BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0.
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|
|
|
//! @brief Get value of IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0 from a register value.
|
|
#define BG_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0) >> BP_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0)
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//! @brief Format value for bitfield IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0.
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#define BF_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0) & BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_CHAN_START_CHAN_R_9_0 field to a new value.
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#define BW_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0(x, v) (HW_IPU_DC_RL5_CH_9_WR(x, (HW_IPU_DC_RL5_CH_9_RD(x) & ~BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0) | BF_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_0(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_RL5_CH_9, field COD_NEW_CHAN_START_CHAN_R_9_1[31:24] (RW)
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*
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|
* This field is a pointer to the address within the microcode memory where the routine that handles
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* the new channel event resides (associated with channel #9, second region)
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*/
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//@{
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|
#define BP_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1 (24) //!< Bit position for IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1.
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#define BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1 (0xff000000) //!< Bit mask for IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1.
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//! @brief Get value of IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1 from a register value.
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#define BG_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1) >> BP_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1)
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//! @brief Format value for bitfield IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1.
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#define BF_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1) & BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the COD_NEW_CHAN_START_CHAN_R_9_1 field to a new value.
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#define BW_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1(x, v) (HW_IPU_DC_RL5_CH_9_WR(x, (HW_IPU_DC_RL5_CH_9_RD(x) & ~BM_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1) | BF_IPU_DC_RL5_CH_9_COD_NEW_CHAN_START_CHAN_R_9_1(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_RL6_CH_9 - DC Routine Link Register 6 Channel 9
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DC_RL6_CH_9 - DC Routine Link Register 6 Channel 9 (RW)
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*
|
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_rl6_ch_9
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{
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reg32_t U;
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struct _hw_ipu_dc_rl6_ch_9_bitfields
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{
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unsigned RESERVED0 : 8; //!< [7:0] Reserved.
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unsigned COD_NEW_DATA_START_CHAN_R_9_0 : 8; //!< [15:8] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #9, first region)
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unsigned RESERVED1 : 8; //!< [23:16] Reserved.
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unsigned COD_NEW_DATA_START_CHAN_R_9_1 : 8; //!< [31:24] This field is a pointer to the address within the microcode memory where the routine that handles the new data event resides (associated with channel #9, second region)
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} B;
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} hw_ipu_dc_rl6_ch_9_t;
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#endif
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/*!
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|
* @name Constants and macros for entire IPU_DC_RL6_CH_9 register
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*/
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//@{
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|
#define HW_IPU_DC_RL6_CH_9_ADDR(x) (REGS_IPU_BASE(x) + 0x580d0)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_RL6_CH_9(x) (*(volatile hw_ipu_dc_rl6_ch_9_t *) HW_IPU_DC_RL6_CH_9_ADDR(x))
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#define HW_IPU_DC_RL6_CH_9_RD(x) (HW_IPU_DC_RL6_CH_9(x).U)
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#define HW_IPU_DC_RL6_CH_9_WR(x, v) (HW_IPU_DC_RL6_CH_9(x).U = (v))
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#define HW_IPU_DC_RL6_CH_9_SET(x, v) (HW_IPU_DC_RL6_CH_9_WR(x, HW_IPU_DC_RL6_CH_9_RD(x) | (v)))
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#define HW_IPU_DC_RL6_CH_9_CLR(x, v) (HW_IPU_DC_RL6_CH_9_WR(x, HW_IPU_DC_RL6_CH_9_RD(x) & ~(v)))
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#define HW_IPU_DC_RL6_CH_9_TOG(x, v) (HW_IPU_DC_RL6_CH_9_WR(x, HW_IPU_DC_RL6_CH_9_RD(x) ^ (v)))
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#endif
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|
//@}
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|
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/*
|
|
* constants & macros for individual IPU_DC_RL6_CH_9 bitfields
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|
*/
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|
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/*! @name Register IPU_DC_RL6_CH_9, field COD_NEW_DATA_START_CHAN_R_9_0[15:8] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
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|
* the new data event resides (associated with channel #9, first region)
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|
*/
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|
//@{
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|
#define BP_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0 (8) //!< Bit position for IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0.
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#define BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0 (0x0000ff00) //!< Bit mask for IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0.
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//! @brief Get value of IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0 from a register value.
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|
#define BG_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0) >> BP_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0)
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|
//! @brief Format value for bitfield IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0.
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|
#define BF_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0) & BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_R_9_0 field to a new value.
|
|
#define BW_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0(x, v) (HW_IPU_DC_RL6_CH_9_WR(x, (HW_IPU_DC_RL6_CH_9_RD(x) & ~BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0) | BF_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_0(v)))
|
|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DC_RL6_CH_9, field COD_NEW_DATA_START_CHAN_R_9_1[31:24] (RW)
|
|
*
|
|
* This field is a pointer to the address within the microcode memory where the routine that handles
|
|
* the new data event resides (associated with channel #9, second region)
|
|
*/
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|
//@{
|
|
#define BP_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1 (24) //!< Bit position for IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1.
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|
#define BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1 (0xff000000) //!< Bit mask for IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1.
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|
//! @brief Get value of IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1 from a register value.
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|
#define BG_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1) >> BP_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1)
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|
//! @brief Format value for bitfield IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1.
|
|
#define BF_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1) & BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_NEW_DATA_START_CHAN_R_9_1 field to a new value.
|
|
#define BW_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1(x, v) (HW_IPU_DC_RL6_CH_9_WR(x, (HW_IPU_DC_RL6_CH_9_RD(x) & ~BM_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1) | BF_IPU_DC_RL6_CH_9_COD_NEW_DATA_START_CHAN_R_9_1(v)))
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|
#endif
|
|
//@}
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|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_GEN - DC General Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_GEN - DC General Register (RW)
|
|
*
|
|
* Reset value: 0x00000060
|
|
*/
|
|
typedef union _hw_ipu_dc_gen
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_gen_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved
|
|
unsigned SYNC_1_6 : 2; //!< [2:1] This field
|
|
unsigned RESERVED1 : 1; //!< [3] Reserved
|
|
unsigned MASK_EN : 1; //!< [4] Enable of the mask channel
|
|
unsigned MASK4CHAN_5 : 1; //!< [5] Sync flow can be associated with a mask channel.
|
|
unsigned SYNC_PRIORITY_5 : 1; //!< [6] When 2 sync flows are running, this bit sets the priority of channel #5.
|
|
unsigned SYNC_PRIORITY_1 : 1; //!< [7] When 2 sync flows are running, this bit sets the priority of channel #1.
|
|
unsigned DC_CH5_TYPE : 1; //!< [8] Channel 5 is used for synchronous flow.
|
|
unsigned RESERVED2 : 7; //!< [15:9] Reserved.
|
|
unsigned DC_BKDIV : 8; //!< [23:16] Blinking Rate
|
|
unsigned DC_BK_EN : 1; //!< [24] Cursor blinking enable
|
|
unsigned RESERVED3 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_gen_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_GEN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_GEN_ADDR(x) (REGS_IPU_BASE(x) + 0x580d4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_GEN(x) (*(volatile hw_ipu_dc_gen_t *) HW_IPU_DC_GEN_ADDR(x))
|
|
#define HW_IPU_DC_GEN_RD(x) (HW_IPU_DC_GEN(x).U)
|
|
#define HW_IPU_DC_GEN_WR(x, v) (HW_IPU_DC_GEN(x).U = (v))
|
|
#define HW_IPU_DC_GEN_SET(x, v) (HW_IPU_DC_GEN_WR(x, HW_IPU_DC_GEN_RD(x) | (v)))
|
|
#define HW_IPU_DC_GEN_CLR(x, v) (HW_IPU_DC_GEN_WR(x, HW_IPU_DC_GEN_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_GEN_TOG(x, v) (HW_IPU_DC_GEN_WR(x, HW_IPU_DC_GEN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_GEN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_GEN, field SYNC_1_6[2:1] (RW)
|
|
*
|
|
* This field
|
|
*
|
|
* Values:
|
|
* - 00 - Channel 1 of the DC handles async flow
|
|
* - 01 - Illegal
|
|
* - 10 - Channel 1 of the DC handles sync flow
|
|
* - 11 - illegal
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_SYNC_1_6 (1) //!< Bit position for IPU_DC_GEN_SYNC_1_6.
|
|
#define BM_IPU_DC_GEN_SYNC_1_6 (0x00000006) //!< Bit mask for IPU_DC_GEN_SYNC_1_6.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_SYNC_1_6 from a register value.
|
|
#define BG_IPU_DC_GEN_SYNC_1_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_SYNC_1_6) >> BP_IPU_DC_GEN_SYNC_1_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_SYNC_1_6.
|
|
#define BF_IPU_DC_GEN_SYNC_1_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_SYNC_1_6) & BM_IPU_DC_GEN_SYNC_1_6)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SYNC_1_6 field to a new value.
|
|
#define BW_IPU_DC_GEN_SYNC_1_6(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_SYNC_1_6) | BF_IPU_DC_GEN_SYNC_1_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field MASK_EN[4] (RW)
|
|
*
|
|
* Enable of the mask channel
|
|
*
|
|
* Values:
|
|
* - 0 - mask channel is disabled
|
|
* - 1 - mask channel is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_MASK_EN (4) //!< Bit position for IPU_DC_GEN_MASK_EN.
|
|
#define BM_IPU_DC_GEN_MASK_EN (0x00000010) //!< Bit mask for IPU_DC_GEN_MASK_EN.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_MASK_EN from a register value.
|
|
#define BG_IPU_DC_GEN_MASK_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_MASK_EN) >> BP_IPU_DC_GEN_MASK_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_MASK_EN.
|
|
#define BF_IPU_DC_GEN_MASK_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_MASK_EN) & BM_IPU_DC_GEN_MASK_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MASK_EN field to a new value.
|
|
#define BW_IPU_DC_GEN_MASK_EN(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_MASK_EN) | BF_IPU_DC_GEN_MASK_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field MASK4CHAN_5[5] (RW)
|
|
*
|
|
* Sync flow can be associated with a mask channel. Only one sync flow can have a mask. This bit is
|
|
* ignored if MASK_EN is clear
|
|
*
|
|
* Values:
|
|
* - 0 - mask channel is associated to the sync flow via DC (without DP)
|
|
* - 1 - mask channel is associated to the sync flow via DP
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_MASK4CHAN_5 (5) //!< Bit position for IPU_DC_GEN_MASK4CHAN_5.
|
|
#define BM_IPU_DC_GEN_MASK4CHAN_5 (0x00000020) //!< Bit mask for IPU_DC_GEN_MASK4CHAN_5.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_MASK4CHAN_5 from a register value.
|
|
#define BG_IPU_DC_GEN_MASK4CHAN_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_MASK4CHAN_5) >> BP_IPU_DC_GEN_MASK4CHAN_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_MASK4CHAN_5.
|
|
#define BF_IPU_DC_GEN_MASK4CHAN_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_MASK4CHAN_5) & BM_IPU_DC_GEN_MASK4CHAN_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MASK4CHAN_5 field to a new value.
|
|
#define BW_IPU_DC_GEN_MASK4CHAN_5(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_MASK4CHAN_5) | BF_IPU_DC_GEN_MASK4CHAN_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field SYNC_PRIORITY_5[6] (RW)
|
|
*
|
|
* When 2 sync flows are running, this bit sets the priority of channel #5. both SYNC_PRIORITY_5 and
|
|
* SYNC_PRIORITY_1 should not have the value of 0 This bit should be
|
|
*
|
|
* Values:
|
|
* - 0 - low Priority
|
|
* - 1 - high priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_SYNC_PRIORITY_5 (6) //!< Bit position for IPU_DC_GEN_SYNC_PRIORITY_5.
|
|
#define BM_IPU_DC_GEN_SYNC_PRIORITY_5 (0x00000040) //!< Bit mask for IPU_DC_GEN_SYNC_PRIORITY_5.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_SYNC_PRIORITY_5 from a register value.
|
|
#define BG_IPU_DC_GEN_SYNC_PRIORITY_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_SYNC_PRIORITY_5) >> BP_IPU_DC_GEN_SYNC_PRIORITY_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_SYNC_PRIORITY_5.
|
|
#define BF_IPU_DC_GEN_SYNC_PRIORITY_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_SYNC_PRIORITY_5) & BM_IPU_DC_GEN_SYNC_PRIORITY_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SYNC_PRIORITY_5 field to a new value.
|
|
#define BW_IPU_DC_GEN_SYNC_PRIORITY_5(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_SYNC_PRIORITY_5) | BF_IPU_DC_GEN_SYNC_PRIORITY_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field SYNC_PRIORITY_1[7] (RW)
|
|
*
|
|
* When 2 sync flows are running, this bit sets the priority of channel #1. both SYNC_PRIORITY_5 and
|
|
* SYNC_PRIORITY_1 should not have the value of 0 This bit should be
|
|
*
|
|
* Values:
|
|
* - 0 - low Priority
|
|
* - 1 - high Priority
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_SYNC_PRIORITY_1 (7) //!< Bit position for IPU_DC_GEN_SYNC_PRIORITY_1.
|
|
#define BM_IPU_DC_GEN_SYNC_PRIORITY_1 (0x00000080) //!< Bit mask for IPU_DC_GEN_SYNC_PRIORITY_1.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_SYNC_PRIORITY_1 from a register value.
|
|
#define BG_IPU_DC_GEN_SYNC_PRIORITY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_SYNC_PRIORITY_1) >> BP_IPU_DC_GEN_SYNC_PRIORITY_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_SYNC_PRIORITY_1.
|
|
#define BF_IPU_DC_GEN_SYNC_PRIORITY_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_SYNC_PRIORITY_1) & BM_IPU_DC_GEN_SYNC_PRIORITY_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SYNC_PRIORITY_1 field to a new value.
|
|
#define BW_IPU_DC_GEN_SYNC_PRIORITY_1(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_SYNC_PRIORITY_1) | BF_IPU_DC_GEN_SYNC_PRIORITY_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field DC_CH5_TYPE[8] (RW)
|
|
*
|
|
* Channel 5 is used for synchronous flow. When this channel is used for accessing asynchronous
|
|
* display that is activated in a synchronous way
|
|
*
|
|
* Values:
|
|
* - 0 - normal mode, synchronous flow via channel 5
|
|
* - 1 - Enable the asynchronous interface via channel 5
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_DC_CH5_TYPE (8) //!< Bit position for IPU_DC_GEN_DC_CH5_TYPE.
|
|
#define BM_IPU_DC_GEN_DC_CH5_TYPE (0x00000100) //!< Bit mask for IPU_DC_GEN_DC_CH5_TYPE.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_DC_CH5_TYPE from a register value.
|
|
#define BG_IPU_DC_GEN_DC_CH5_TYPE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_DC_CH5_TYPE) >> BP_IPU_DC_GEN_DC_CH5_TYPE)
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|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_DC_CH5_TYPE.
|
|
#define BF_IPU_DC_GEN_DC_CH5_TYPE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_DC_CH5_TYPE) & BM_IPU_DC_GEN_DC_CH5_TYPE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_CH5_TYPE field to a new value.
|
|
#define BW_IPU_DC_GEN_DC_CH5_TYPE(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_DC_CH5_TYPE) | BF_IPU_DC_GEN_DC_CH5_TYPE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field DC_BKDIV[23:16] (RW)
|
|
*
|
|
* Blinking Rate This field defines the blinking rate. The blinking occurs every N-th frame While N
|
|
* is defined by DC_BKDIV
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_DC_BKDIV (16) //!< Bit position for IPU_DC_GEN_DC_BKDIV.
|
|
#define BM_IPU_DC_GEN_DC_BKDIV (0x00ff0000) //!< Bit mask for IPU_DC_GEN_DC_BKDIV.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_DC_BKDIV from a register value.
|
|
#define BG_IPU_DC_GEN_DC_BKDIV(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_DC_BKDIV) >> BP_IPU_DC_GEN_DC_BKDIV)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_DC_BKDIV.
|
|
#define BF_IPU_DC_GEN_DC_BKDIV(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_DC_BKDIV) & BM_IPU_DC_GEN_DC_BKDIV)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_BKDIV field to a new value.
|
|
#define BW_IPU_DC_GEN_DC_BKDIV(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_DC_BKDIV) | BF_IPU_DC_GEN_DC_BKDIV(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_GEN, field DC_BK_EN[24] (RW)
|
|
*
|
|
* Cursor blinking enable
|
|
*
|
|
* Values:
|
|
* - 0 - blinking is disabled
|
|
* - 1 - blinking is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_GEN_DC_BK_EN (24) //!< Bit position for IPU_DC_GEN_DC_BK_EN.
|
|
#define BM_IPU_DC_GEN_DC_BK_EN (0x01000000) //!< Bit mask for IPU_DC_GEN_DC_BK_EN.
|
|
|
|
//! @brief Get value of IPU_DC_GEN_DC_BK_EN from a register value.
|
|
#define BG_IPU_DC_GEN_DC_BK_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_GEN_DC_BK_EN) >> BP_IPU_DC_GEN_DC_BK_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_GEN_DC_BK_EN.
|
|
#define BF_IPU_DC_GEN_DC_BK_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_GEN_DC_BK_EN) & BM_IPU_DC_GEN_DC_BK_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DC_BK_EN field to a new value.
|
|
#define BW_IPU_DC_GEN_DC_BK_EN(x, v) (HW_IPU_DC_GEN_WR(x, (HW_IPU_DC_GEN_RD(x) & ~BM_IPU_DC_GEN_DC_BK_EN) | BF_IPU_DC_GEN_DC_BK_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF1_0 - DC Display Configuration 1 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF1_0 - DC Display Configuration 1 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000042
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf1_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf1_0_bitfields
|
|
{
|
|
unsigned DISP_TYP_0 : 2; //!< [1:0] This field defines the type of the display
|
|
unsigned ADDR_INCREMENT_0 : 2; //!< [3:2] This field is the increment step for auto increment mode
|
|
unsigned ADDR_BE_L_INC_0 : 2; //!< [5:4] This bits define the increment mode when the latest access was done with some of the byte enable signals are low, in that case different increment should be done instead of the normal auto increment of the address
|
|
unsigned MCU_ACC_LB_MASK_0 : 1; //!< [6] The DC compares between the current access to the a calculated address.
|
|
unsigned DISP_RD_VALUE_PTR_0 : 1; //!< [7] When the display works in wait for status mode.
|
|
unsigned RESERVED0 : 24; //!< [31:8] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf1_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF1_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF1_0_ADDR(x) (REGS_IPU_BASE(x) + 0x580d8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF1_0(x) (*(volatile hw_ipu_dc_disp_conf1_0_t *) HW_IPU_DC_DISP_CONF1_0_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF1_0_RD(x) (HW_IPU_DC_DISP_CONF1_0(x).U)
|
|
#define HW_IPU_DC_DISP_CONF1_0_WR(x, v) (HW_IPU_DC_DISP_CONF1_0(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF1_0_SET(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, HW_IPU_DC_DISP_CONF1_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF1_0_CLR(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, HW_IPU_DC_DISP_CONF1_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF1_0_TOG(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, HW_IPU_DC_DISP_CONF1_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF1_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_0, field DISP_TYP_0[1:0] (RW)
|
|
*
|
|
* This field defines the type of the display
|
|
*
|
|
* Values:
|
|
* - 00 - Serial accesses display
|
|
* - 01 - Reserved
|
|
* - 10 - parallel display, without byte_enable support
|
|
* - 11 - parallel display, with byte_enable support
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_0_DISP_TYP_0 (0) //!< Bit position for IPU_DC_DISP_CONF1_0_DISP_TYP_0.
|
|
#define BM_IPU_DC_DISP_CONF1_0_DISP_TYP_0 (0x00000003) //!< Bit mask for IPU_DC_DISP_CONF1_0_DISP_TYP_0.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_0_DISP_TYP_0 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_0_DISP_TYP_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_0_DISP_TYP_0) >> BP_IPU_DC_DISP_CONF1_0_DISP_TYP_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_0_DISP_TYP_0.
|
|
#define BF_IPU_DC_DISP_CONF1_0_DISP_TYP_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_0_DISP_TYP_0) & BM_IPU_DC_DISP_CONF1_0_DISP_TYP_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DISP_TYP_0 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_0_DISP_TYP_0(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, (HW_IPU_DC_DISP_CONF1_0_RD(x) & ~BM_IPU_DC_DISP_CONF1_0_DISP_TYP_0) | BF_IPU_DC_DISP_CONF1_0_DISP_TYP_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_0, field ADDR_INCREMENT_0[3:2] (RW)
|
|
*
|
|
* This field is the increment step for auto increment mode
|
|
*
|
|
* Values:
|
|
* - 00 - Increment the address by 1
|
|
* - 01 - Increment the address by 2
|
|
* - 10 - Increment the address by 3
|
|
* - 11 - Increment the address by 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0 (2) //!< Bit position for IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0.
|
|
#define BM_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0 (0x0000000c) //!< Bit mask for IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0) >> BP_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0.
|
|
#define BF_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0) & BM_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_INCREMENT_0 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, (HW_IPU_DC_DISP_CONF1_0_RD(x) & ~BM_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0) | BF_IPU_DC_DISP_CONF1_0_ADDR_INCREMENT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_0, field ADDR_BE_L_INC_0[5:4] (RW)
|
|
*
|
|
* This bits define the increment mode when the latest access was done with some of the byte enable
|
|
* signals are low, in that case different increment should be done instead of the normal auto
|
|
* increment of the address IF MCU_ACC_LB_MASK_0 is 0 then only 00 and 10 values are allowed.
|
|
*
|
|
* Values:
|
|
* - 00 - No increment
|
|
* - 01 - Increment by 1
|
|
* - 10 - Increment by 2
|
|
* - 11 - Increment by 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0 (4) //!< Bit position for IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0.
|
|
#define BM_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0 (0x00000030) //!< Bit mask for IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0) >> BP_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0.
|
|
#define BF_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0) & BM_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_BE_L_INC_0 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, (HW_IPU_DC_DISP_CONF1_0_RD(x) & ~BM_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0) | BF_IPU_DC_DISP_CONF1_0_ADDR_BE_L_INC_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_0, field MCU_ACC_LB_MASK_0[6] (RW)
|
|
*
|
|
* The DC compares between the current access to the a calculated address. The calculated address is
|
|
* the next consecutive address following the last address. This bit defines the comparing mode
|
|
*
|
|
* Values:
|
|
* - 0 - The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored
|
|
* - 1 - The 2 addresses are fully compared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0 (6) //!< Bit position for IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0.
|
|
#define BM_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0 (0x00000040) //!< Bit mask for IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0) >> BP_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0.
|
|
#define BF_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0) & BM_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_ACC_LB_MASK_0 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, (HW_IPU_DC_DISP_CONF1_0_RD(x) & ~BM_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0) | BF_IPU_DC_DISP_CONF1_0_MCU_ACC_LB_MASK_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_0, field DISP_RD_VALUE_PTR_0[7] (RW)
|
|
*
|
|
* When the display works in wait for status mode. The IPU polls the display and compare the value
|
|
* to the value stored on the status DI_READ_DATA_ACK_VALUE and mask it with DI_READ_DATA_MASK. The
|
|
* DC holds 2 sets of mask and value. This field holds a pointer to the corresponding set of mask
|
|
* and value.
|
|
*
|
|
* Values:
|
|
* - 0 - DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 0
|
|
* - 1 - DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0 (7) //!< Bit position for IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0.
|
|
#define BM_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0 (0x00000080) //!< Bit mask for IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0) >> BP_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0.
|
|
#define BF_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0) & BM_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DISP_RD_VALUE_PTR_0 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0(x, v) (HW_IPU_DC_DISP_CONF1_0_WR(x, (HW_IPU_DC_DISP_CONF1_0_RD(x) & ~BM_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0) | BF_IPU_DC_DISP_CONF1_0_DISP_RD_VALUE_PTR_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF1_1 - DC Display Configuration 1 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF1_1 - DC Display Configuration 1 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000042
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf1_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf1_1_bitfields
|
|
{
|
|
unsigned DISP_TYP_1 : 2; //!< [1:0] This field defines the type of the display
|
|
unsigned ADDR_INCREMENT_1 : 2; //!< [3:2] This field is the increment step for auto increment mode
|
|
unsigned ADDR_BE_L_INC_1 : 2; //!< [5:4] This bits define the increment mode when the latest access was done with some of the byte enable signals are low, in that case different increment should be done instead of the normal auto increment of the address
|
|
unsigned MCU_ACC_LB_MASK_1 : 1; //!< [6] The DC compares between the current access to the a calculated address.
|
|
unsigned DISP_RD_VALUE_PTR_1 : 1; //!< [7] When the display works in wait for status mode.
|
|
unsigned RESERVED0 : 24; //!< [31:8] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf1_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF1_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF1_1_ADDR(x) (REGS_IPU_BASE(x) + 0x580dc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF1_1(x) (*(volatile hw_ipu_dc_disp_conf1_1_t *) HW_IPU_DC_DISP_CONF1_1_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF1_1_RD(x) (HW_IPU_DC_DISP_CONF1_1(x).U)
|
|
#define HW_IPU_DC_DISP_CONF1_1_WR(x, v) (HW_IPU_DC_DISP_CONF1_1(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF1_1_SET(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, HW_IPU_DC_DISP_CONF1_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF1_1_CLR(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, HW_IPU_DC_DISP_CONF1_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF1_1_TOG(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, HW_IPU_DC_DISP_CONF1_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF1_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_1, field DISP_TYP_1[1:0] (RW)
|
|
*
|
|
* This field defines the type of the display
|
|
*
|
|
* Values:
|
|
* - 00 - Serial accesses display
|
|
* - 01 - Reserved
|
|
* - 10 - parallel display, without byte_enable support
|
|
* - 11 - parallel display, with byte_enable support
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_1_DISP_TYP_1 (0) //!< Bit position for IPU_DC_DISP_CONF1_1_DISP_TYP_1.
|
|
#define BM_IPU_DC_DISP_CONF1_1_DISP_TYP_1 (0x00000003) //!< Bit mask for IPU_DC_DISP_CONF1_1_DISP_TYP_1.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_1_DISP_TYP_1 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_1_DISP_TYP_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_1_DISP_TYP_1) >> BP_IPU_DC_DISP_CONF1_1_DISP_TYP_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_1_DISP_TYP_1.
|
|
#define BF_IPU_DC_DISP_CONF1_1_DISP_TYP_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_1_DISP_TYP_1) & BM_IPU_DC_DISP_CONF1_1_DISP_TYP_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DISP_TYP_1 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_1_DISP_TYP_1(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, (HW_IPU_DC_DISP_CONF1_1_RD(x) & ~BM_IPU_DC_DISP_CONF1_1_DISP_TYP_1) | BF_IPU_DC_DISP_CONF1_1_DISP_TYP_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_1, field ADDR_INCREMENT_1[3:2] (RW)
|
|
*
|
|
* This field is the increment step for auto increment mode
|
|
*
|
|
* Values:
|
|
* - 00 - Increment the address by 1
|
|
* - 01 - Increment the address by 2
|
|
* - 10 - Increment the address by 3
|
|
* - 11 - Increment the address by 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1 (2) //!< Bit position for IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1.
|
|
#define BM_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1 (0x0000000c) //!< Bit mask for IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1) >> BP_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1.
|
|
#define BF_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1) & BM_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_INCREMENT_1 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, (HW_IPU_DC_DISP_CONF1_1_RD(x) & ~BM_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1) | BF_IPU_DC_DISP_CONF1_1_ADDR_INCREMENT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_1, field ADDR_BE_L_INC_1[5:4] (RW)
|
|
*
|
|
* This bits define the increment mode when the latest access was done with some of the byte enable
|
|
* signals are low, in that case different increment should be done instead of the normal auto
|
|
* increment of the address IF MCU_ACC_LB_MASK_1 is 0 then only 00 and 10 values are allowed.
|
|
*
|
|
* Values:
|
|
* - 00 - No increment
|
|
* - 01 - Increment by 1
|
|
* - 10 - Increment by 2
|
|
* - 11 - Increment by 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1 (4) //!< Bit position for IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1.
|
|
#define BM_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1 (0x00000030) //!< Bit mask for IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1) >> BP_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1.
|
|
#define BF_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1) & BM_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_BE_L_INC_1 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, (HW_IPU_DC_DISP_CONF1_1_RD(x) & ~BM_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1) | BF_IPU_DC_DISP_CONF1_1_ADDR_BE_L_INC_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_1, field MCU_ACC_LB_MASK_1[6] (RW)
|
|
*
|
|
* The DC compares between the current access to the a calculated address. The calculated address is
|
|
* the next consecutive address following the last address. This bit defines the comparing mode
|
|
*
|
|
* Values:
|
|
* - 0 - The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored
|
|
* - 1 - The 2 addresses are fully compared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1 (6) //!< Bit position for IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1.
|
|
#define BM_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1 (0x00000040) //!< Bit mask for IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1) >> BP_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1.
|
|
#define BF_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1) & BM_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_ACC_LB_MASK_1 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, (HW_IPU_DC_DISP_CONF1_1_RD(x) & ~BM_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1) | BF_IPU_DC_DISP_CONF1_1_MCU_ACC_LB_MASK_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_1, field DISP_RD_VALUE_PTR_1[7] (RW)
|
|
*
|
|
* When the display works in wait for status mode. The IPU polls the display and compare the value
|
|
* to the value stored on the status DI_READ_DATA_ACK_VALUE and mask it with DI_READ_DATA_MASK. The
|
|
* DC holds 2 sets of mask and value. This field holds a pointer to the corresponding set of mask
|
|
* and value.
|
|
*
|
|
* Values:
|
|
* - 0 - DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 1
|
|
* - 1 - DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1 (7) //!< Bit position for IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1.
|
|
#define BM_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1 (0x00000080) //!< Bit mask for IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1) >> BP_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1.
|
|
#define BF_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1) & BM_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DISP_RD_VALUE_PTR_1 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1(x, v) (HW_IPU_DC_DISP_CONF1_1_WR(x, (HW_IPU_DC_DISP_CONF1_1_RD(x) & ~BM_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1) | BF_IPU_DC_DISP_CONF1_1_DISP_RD_VALUE_PTR_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF1_2 - DC Display Configuration 1 Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF1_2 - DC Display Configuration 1 Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000042
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf1_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf1_2_bitfields
|
|
{
|
|
unsigned DISP_TYP_2 : 2; //!< [1:0] This field defines the type of the display
|
|
unsigned ADDR_INCREMENT_2 : 2; //!< [3:2] This field is the increment step for auto increment mode
|
|
unsigned ADDR_BE_L_INC_2 : 2; //!< [5:4] This bits define the increment mode when the latest access was done with some of the byte enable signals are low, in that case different increment should be done instead of the normal auto increment of the address
|
|
unsigned MCU_ACC_LB_MASK_2 : 1; //!< [6] The DC compares between the current access to the a calculated address.
|
|
unsigned DISP_RD_VALUE_PTR_2 : 1; //!< [7] When the display works in wait for status mode.
|
|
unsigned RESERVED0 : 24; //!< [31:8] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf1_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF1_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF1_2_ADDR(x) (REGS_IPU_BASE(x) + 0x580e0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF1_2(x) (*(volatile hw_ipu_dc_disp_conf1_2_t *) HW_IPU_DC_DISP_CONF1_2_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF1_2_RD(x) (HW_IPU_DC_DISP_CONF1_2(x).U)
|
|
#define HW_IPU_DC_DISP_CONF1_2_WR(x, v) (HW_IPU_DC_DISP_CONF1_2(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF1_2_SET(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, HW_IPU_DC_DISP_CONF1_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF1_2_CLR(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, HW_IPU_DC_DISP_CONF1_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF1_2_TOG(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, HW_IPU_DC_DISP_CONF1_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF1_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_2, field DISP_TYP_2[1:0] (RW)
|
|
*
|
|
* This field defines the type of the display
|
|
*
|
|
* Values:
|
|
* - 00 - Serial accesses display
|
|
* - 01 - Reserved
|
|
* - 10 - parallel display, without byte_enable support
|
|
* - 11 - parallel display, with byte_enable support
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_2_DISP_TYP_2 (0) //!< Bit position for IPU_DC_DISP_CONF1_2_DISP_TYP_2.
|
|
#define BM_IPU_DC_DISP_CONF1_2_DISP_TYP_2 (0x00000003) //!< Bit mask for IPU_DC_DISP_CONF1_2_DISP_TYP_2.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_2_DISP_TYP_2 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_2_DISP_TYP_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_2_DISP_TYP_2) >> BP_IPU_DC_DISP_CONF1_2_DISP_TYP_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_2_DISP_TYP_2.
|
|
#define BF_IPU_DC_DISP_CONF1_2_DISP_TYP_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_2_DISP_TYP_2) & BM_IPU_DC_DISP_CONF1_2_DISP_TYP_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DISP_TYP_2 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_2_DISP_TYP_2(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, (HW_IPU_DC_DISP_CONF1_2_RD(x) & ~BM_IPU_DC_DISP_CONF1_2_DISP_TYP_2) | BF_IPU_DC_DISP_CONF1_2_DISP_TYP_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_2, field ADDR_INCREMENT_2[3:2] (RW)
|
|
*
|
|
* This field is the increment step for auto increment mode
|
|
*
|
|
* Values:
|
|
* - 00 - Increment the address by 1
|
|
* - 01 - Increment the address by 2
|
|
* - 10 - Increment the address by 3
|
|
* - 11 - Increment the address by 4
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2 (2) //!< Bit position for IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2.
|
|
#define BM_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2 (0x0000000c) //!< Bit mask for IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2) >> BP_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2.
|
|
#define BF_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2) & BM_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_INCREMENT_2 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, (HW_IPU_DC_DISP_CONF1_2_RD(x) & ~BM_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2) | BF_IPU_DC_DISP_CONF1_2_ADDR_INCREMENT_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_2, field ADDR_BE_L_INC_2[5:4] (RW)
|
|
*
|
|
* This bits define the increment mode when the latest access was done with some of the byte enable
|
|
* signals are low, in that case different increment should be done instead of the normal auto
|
|
* increment of the address IF MCU_ACC_LB_MASK_2 is 0 then only 00 and 10 values are allowed.
|
|
*
|
|
* Values:
|
|
* - 00 - No increment
|
|
* - 01 - Increment by 1
|
|
* - 10 - Increment by 2
|
|
* - 11 - Increment by 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2 (4) //!< Bit position for IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2.
|
|
#define BM_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2 (0x00000030) //!< Bit mask for IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2) >> BP_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2)
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//! @brief Format value for bitfield IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2.
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#define BF_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2) & BM_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ADDR_BE_L_INC_2 field to a new value.
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#define BW_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, (HW_IPU_DC_DISP_CONF1_2_RD(x) & ~BM_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2) | BF_IPU_DC_DISP_CONF1_2_ADDR_BE_L_INC_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_DISP_CONF1_2, field MCU_ACC_LB_MASK_2[6] (RW)
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*
|
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* The DC compares between the current access to the a calculated address. The calculated address is
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* the next consecutive address following the last address. This bit defines the comparing mode
|
|
*
|
|
* Values:
|
|
* - 0 - The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored
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* - 1 - The 2 addresses are fully compared
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|
*/
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//@{
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|
#define BP_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2 (6) //!< Bit position for IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2.
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#define BM_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2 (0x00000040) //!< Bit mask for IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2.
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//! @brief Get value of IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2 from a register value.
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#define BG_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2) >> BP_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2)
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//! @brief Format value for bitfield IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2.
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#define BF_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2) & BM_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MCU_ACC_LB_MASK_2 field to a new value.
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#define BW_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, (HW_IPU_DC_DISP_CONF1_2_RD(x) & ~BM_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2) | BF_IPU_DC_DISP_CONF1_2_MCU_ACC_LB_MASK_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_DISP_CONF1_2, field DISP_RD_VALUE_PTR_2[7] (RW)
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*
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* When the display works in wait for status mode. The IPU polls the display and compare the value
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* to the value stored on the status DI_READ_DATA_ACK_VALUE and mask it with DI_READ_DATA_MASK. The
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* DC holds 2 sets of mask and value. This field holds a pointer to the corresponding set of mask
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* and value.
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*
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* Values:
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* - 0 - DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 2
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* - 1 - DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 2
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*/
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//@{
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#define BP_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2 (7) //!< Bit position for IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2.
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#define BM_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2 (0x00000080) //!< Bit mask for IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2.
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//! @brief Get value of IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2 from a register value.
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#define BG_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2) >> BP_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2)
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//! @brief Format value for bitfield IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2.
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#define BF_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2) & BM_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DISP_RD_VALUE_PTR_2 field to a new value.
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#define BW_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2(x, v) (HW_IPU_DC_DISP_CONF1_2_WR(x, (HW_IPU_DC_DISP_CONF1_2_RD(x) & ~BM_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2) | BF_IPU_DC_DISP_CONF1_2_DISP_RD_VALUE_PTR_2(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_DISP_CONF1_3 - DC Display Configuration 1 Register 3
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
|
|
/*!
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|
* @brief HW_IPU_DC_DISP_CONF1_3 - DC Display Configuration 1 Register 3 (RW)
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|
*
|
|
* Reset value: 0x00000042
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|
*/
|
|
typedef union _hw_ipu_dc_disp_conf1_3
|
|
{
|
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reg32_t U;
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struct _hw_ipu_dc_disp_conf1_3_bitfields
|
|
{
|
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unsigned DISP_TYP_3 : 2; //!< [1:0] This field defines the type of the display
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unsigned ADDR_INCREMENT_3 : 2; //!< [3:2] This field is the increment step for auto increment mode
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unsigned ADDR_BE_L_INC_3 : 2; //!< [5:4] This bits define the increment mode when the latest access was done with some of the byte enable signals are low, in that case different increment should be done instead of the normal auto increment of the address
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unsigned MCU_ACC_LB_MASK_3 : 1; //!< [6] The DC compares between the current access to the a calculated address.
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unsigned DISP_RD_VALUE_PTR_3 : 1; //!< [7] When the display works in wait for status mode.
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unsigned RESERVED0 : 24; //!< [31:8] Reserved.
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|
} B;
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|
} hw_ipu_dc_disp_conf1_3_t;
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|
#endif
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|
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/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF1_3 register
|
|
*/
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|
//@{
|
|
#define HW_IPU_DC_DISP_CONF1_3_ADDR(x) (REGS_IPU_BASE(x) + 0x580e4)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF1_3(x) (*(volatile hw_ipu_dc_disp_conf1_3_t *) HW_IPU_DC_DISP_CONF1_3_ADDR(x))
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#define HW_IPU_DC_DISP_CONF1_3_RD(x) (HW_IPU_DC_DISP_CONF1_3(x).U)
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#define HW_IPU_DC_DISP_CONF1_3_WR(x, v) (HW_IPU_DC_DISP_CONF1_3(x).U = (v))
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#define HW_IPU_DC_DISP_CONF1_3_SET(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, HW_IPU_DC_DISP_CONF1_3_RD(x) | (v)))
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#define HW_IPU_DC_DISP_CONF1_3_CLR(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, HW_IPU_DC_DISP_CONF1_3_RD(x) & ~(v)))
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|
#define HW_IPU_DC_DISP_CONF1_3_TOG(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, HW_IPU_DC_DISP_CONF1_3_RD(x) ^ (v)))
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|
#endif
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|
//@}
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|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF1_3 bitfields
|
|
*/
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|
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/*! @name Register IPU_DC_DISP_CONF1_3, field DISP_TYP_3[1:0] (RW)
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|
*
|
|
* This field defines the type of the display
|
|
*
|
|
* Values:
|
|
* - 00 - Serial accesses display
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|
* - 01 - Reserved
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|
* - 10 - parallel display, without byte_enable support
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|
* - 11 - parallel display, with byte_enable support
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|
*/
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|
//@{
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|
#define BP_IPU_DC_DISP_CONF1_3_DISP_TYP_3 (0) //!< Bit position for IPU_DC_DISP_CONF1_3_DISP_TYP_3.
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#define BM_IPU_DC_DISP_CONF1_3_DISP_TYP_3 (0x00000003) //!< Bit mask for IPU_DC_DISP_CONF1_3_DISP_TYP_3.
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|
//! @brief Get value of IPU_DC_DISP_CONF1_3_DISP_TYP_3 from a register value.
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|
#define BG_IPU_DC_DISP_CONF1_3_DISP_TYP_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_3_DISP_TYP_3) >> BP_IPU_DC_DISP_CONF1_3_DISP_TYP_3)
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//! @brief Format value for bitfield IPU_DC_DISP_CONF1_3_DISP_TYP_3.
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|
#define BF_IPU_DC_DISP_CONF1_3_DISP_TYP_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_3_DISP_TYP_3) & BM_IPU_DC_DISP_CONF1_3_DISP_TYP_3)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DISP_TYP_3 field to a new value.
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|
#define BW_IPU_DC_DISP_CONF1_3_DISP_TYP_3(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, (HW_IPU_DC_DISP_CONF1_3_RD(x) & ~BM_IPU_DC_DISP_CONF1_3_DISP_TYP_3) | BF_IPU_DC_DISP_CONF1_3_DISP_TYP_3(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_3, field ADDR_INCREMENT_3[3:2] (RW)
|
|
*
|
|
* This field is the increment step for auto increment mode
|
|
*
|
|
* Values:
|
|
* - 00 - Increment the address by 1
|
|
* - 01 - Increment the address by 2
|
|
* - 10 - Increment the address by 3
|
|
* - 11 - Increment the address by 4
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|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3 (2) //!< Bit position for IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3.
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|
#define BM_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3 (0x0000000c) //!< Bit mask for IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3.
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|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3) >> BP_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3)
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|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3.
|
|
#define BF_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3) & BM_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_INCREMENT_3 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, (HW_IPU_DC_DISP_CONF1_3_RD(x) & ~BM_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3) | BF_IPU_DC_DISP_CONF1_3_ADDR_INCREMENT_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_3, field ADDR_BE_L_INC_3[5:4] (RW)
|
|
*
|
|
* This bits define the increment mode when the latest access was done with some of the byte enable
|
|
* signals are low, in that case different increment should be done instead of the normal auto
|
|
* increment of the address IF MCU_ACC_LB_MASK_3 is 0 then only 00 and 10 values are allowed.
|
|
*
|
|
* Values:
|
|
* - 00 - No increment
|
|
* - 01 - Increment by 1
|
|
* - 10 - Increment by 2
|
|
* - 11 - Increment by 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3 (4) //!< Bit position for IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3.
|
|
#define BM_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3 (0x00000030) //!< Bit mask for IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3) >> BP_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3.
|
|
#define BF_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3) & BM_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDR_BE_L_INC_3 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, (HW_IPU_DC_DISP_CONF1_3_RD(x) & ~BM_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3) | BF_IPU_DC_DISP_CONF1_3_ADDR_BE_L_INC_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_3, field MCU_ACC_LB_MASK_3[6] (RW)
|
|
*
|
|
* The DC compares between the current access to the a calculated address. The calculated address is
|
|
* the next consecutive address following the last address. This bit defines the comparing mode
|
|
*
|
|
* Values:
|
|
* - 0 - The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored
|
|
* - 1 - The 2 addresses are fully compared
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3 (6) //!< Bit position for IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3.
|
|
#define BM_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3 (0x00000040) //!< Bit mask for IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3) >> BP_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3.
|
|
#define BF_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3) & BM_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_ACC_LB_MASK_3 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, (HW_IPU_DC_DISP_CONF1_3_RD(x) & ~BM_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3) | BF_IPU_DC_DISP_CONF1_3_MCU_ACC_LB_MASK_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF1_3, field DISP_RD_VALUE_PTR_3[7] (RW)
|
|
*
|
|
* When the display works in wait for status mode. The IPU polls the display and compare the value
|
|
* to the value stored on the status DI_READ_DATA_ACK_VALUE and mask it with DI_READ_DATA_MASK. The
|
|
* DC holds 2 sets of mask and value. This field holds a pointer to the corresponding set of mask
|
|
* and value.
|
|
*
|
|
* Values:
|
|
* - 0 - DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 3
|
|
* - 1 - DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3 (7) //!< Bit position for IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3.
|
|
#define BM_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3 (0x00000080) //!< Bit mask for IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3) >> BP_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3.
|
|
#define BF_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3) & BM_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DISP_RD_VALUE_PTR_3 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3(x, v) (HW_IPU_DC_DISP_CONF1_3_WR(x, (HW_IPU_DC_DISP_CONF1_3_RD(x) & ~BM_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3) | BF_IPU_DC_DISP_CONF1_3_DISP_RD_VALUE_PTR_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF2_0 - DC Display Configuration 2 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF2_0 - DC Display Configuration 2 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf2_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf2_0_bitfields
|
|
{
|
|
unsigned SL_0 : 29; //!< [28:0] Stride line of display 0
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf2_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF2_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF2_0_ADDR(x) (REGS_IPU_BASE(x) + 0x580e8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF2_0(x) (*(volatile hw_ipu_dc_disp_conf2_0_t *) HW_IPU_DC_DISP_CONF2_0_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF2_0_RD(x) (HW_IPU_DC_DISP_CONF2_0(x).U)
|
|
#define HW_IPU_DC_DISP_CONF2_0_WR(x, v) (HW_IPU_DC_DISP_CONF2_0(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF2_0_SET(x, v) (HW_IPU_DC_DISP_CONF2_0_WR(x, HW_IPU_DC_DISP_CONF2_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF2_0_CLR(x, v) (HW_IPU_DC_DISP_CONF2_0_WR(x, HW_IPU_DC_DISP_CONF2_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF2_0_TOG(x, v) (HW_IPU_DC_DISP_CONF2_0_WR(x, HW_IPU_DC_DISP_CONF2_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF2_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF2_0, field SL_0[28:0] (RW)
|
|
*
|
|
* Stride line of display 0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF2_0_SL_0 (0) //!< Bit position for IPU_DC_DISP_CONF2_0_SL_0.
|
|
#define BM_IPU_DC_DISP_CONF2_0_SL_0 (0x1fffffff) //!< Bit mask for IPU_DC_DISP_CONF2_0_SL_0.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF2_0_SL_0 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF2_0_SL_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF2_0_SL_0) >> BP_IPU_DC_DISP_CONF2_0_SL_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF2_0_SL_0.
|
|
#define BF_IPU_DC_DISP_CONF2_0_SL_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF2_0_SL_0) & BM_IPU_DC_DISP_CONF2_0_SL_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SL_0 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF2_0_SL_0(x, v) (HW_IPU_DC_DISP_CONF2_0_WR(x, (HW_IPU_DC_DISP_CONF2_0_RD(x) & ~BM_IPU_DC_DISP_CONF2_0_SL_0) | BF_IPU_DC_DISP_CONF2_0_SL_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF2_1 - DC Display Configuration 2 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF2_1 - DC Display Configuration 2 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf2_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf2_1_bitfields
|
|
{
|
|
unsigned SL_1 : 29; //!< [28:0] Stride line of display 1
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf2_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF2_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF2_1_ADDR(x) (REGS_IPU_BASE(x) + 0x580ec)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF2_1(x) (*(volatile hw_ipu_dc_disp_conf2_1_t *) HW_IPU_DC_DISP_CONF2_1_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF2_1_RD(x) (HW_IPU_DC_DISP_CONF2_1(x).U)
|
|
#define HW_IPU_DC_DISP_CONF2_1_WR(x, v) (HW_IPU_DC_DISP_CONF2_1(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF2_1_SET(x, v) (HW_IPU_DC_DISP_CONF2_1_WR(x, HW_IPU_DC_DISP_CONF2_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF2_1_CLR(x, v) (HW_IPU_DC_DISP_CONF2_1_WR(x, HW_IPU_DC_DISP_CONF2_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF2_1_TOG(x, v) (HW_IPU_DC_DISP_CONF2_1_WR(x, HW_IPU_DC_DISP_CONF2_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF2_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF2_1, field SL_1[28:0] (RW)
|
|
*
|
|
* Stride line of display 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF2_1_SL_1 (0) //!< Bit position for IPU_DC_DISP_CONF2_1_SL_1.
|
|
#define BM_IPU_DC_DISP_CONF2_1_SL_1 (0x1fffffff) //!< Bit mask for IPU_DC_DISP_CONF2_1_SL_1.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF2_1_SL_1 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF2_1_SL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF2_1_SL_1) >> BP_IPU_DC_DISP_CONF2_1_SL_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF2_1_SL_1.
|
|
#define BF_IPU_DC_DISP_CONF2_1_SL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF2_1_SL_1) & BM_IPU_DC_DISP_CONF2_1_SL_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SL_1 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF2_1_SL_1(x, v) (HW_IPU_DC_DISP_CONF2_1_WR(x, (HW_IPU_DC_DISP_CONF2_1_RD(x) & ~BM_IPU_DC_DISP_CONF2_1_SL_1) | BF_IPU_DC_DISP_CONF2_1_SL_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF2_2 - DC Display Configuration 2 Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF2_2 - DC Display Configuration 2 Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf2_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf2_2_bitfields
|
|
{
|
|
unsigned SL_2 : 29; //!< [28:0] Stride line of display 2
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf2_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF2_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF2_2_ADDR(x) (REGS_IPU_BASE(x) + 0x580f0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF2_2(x) (*(volatile hw_ipu_dc_disp_conf2_2_t *) HW_IPU_DC_DISP_CONF2_2_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF2_2_RD(x) (HW_IPU_DC_DISP_CONF2_2(x).U)
|
|
#define HW_IPU_DC_DISP_CONF2_2_WR(x, v) (HW_IPU_DC_DISP_CONF2_2(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF2_2_SET(x, v) (HW_IPU_DC_DISP_CONF2_2_WR(x, HW_IPU_DC_DISP_CONF2_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF2_2_CLR(x, v) (HW_IPU_DC_DISP_CONF2_2_WR(x, HW_IPU_DC_DISP_CONF2_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF2_2_TOG(x, v) (HW_IPU_DC_DISP_CONF2_2_WR(x, HW_IPU_DC_DISP_CONF2_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF2_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF2_2, field SL_2[28:0] (RW)
|
|
*
|
|
* Stride line of display 2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF2_2_SL_2 (0) //!< Bit position for IPU_DC_DISP_CONF2_2_SL_2.
|
|
#define BM_IPU_DC_DISP_CONF2_2_SL_2 (0x1fffffff) //!< Bit mask for IPU_DC_DISP_CONF2_2_SL_2.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF2_2_SL_2 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF2_2_SL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF2_2_SL_2) >> BP_IPU_DC_DISP_CONF2_2_SL_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF2_2_SL_2.
|
|
#define BF_IPU_DC_DISP_CONF2_2_SL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF2_2_SL_2) & BM_IPU_DC_DISP_CONF2_2_SL_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SL_2 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF2_2_SL_2(x, v) (HW_IPU_DC_DISP_CONF2_2_WR(x, (HW_IPU_DC_DISP_CONF2_2_RD(x) & ~BM_IPU_DC_DISP_CONF2_2_SL_2) | BF_IPU_DC_DISP_CONF2_2_SL_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DISP_CONF2_3 - DC Display Configuration 2 Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DISP_CONF2_3 - DC Display Configuration 2 Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_disp_conf2_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_disp_conf2_3_bitfields
|
|
{
|
|
unsigned SL_3 : 29; //!< [28:0] Stride line of display 3
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_disp_conf2_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DISP_CONF2_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DISP_CONF2_3_ADDR(x) (REGS_IPU_BASE(x) + 0x580f4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DISP_CONF2_3(x) (*(volatile hw_ipu_dc_disp_conf2_3_t *) HW_IPU_DC_DISP_CONF2_3_ADDR(x))
|
|
#define HW_IPU_DC_DISP_CONF2_3_RD(x) (HW_IPU_DC_DISP_CONF2_3(x).U)
|
|
#define HW_IPU_DC_DISP_CONF2_3_WR(x, v) (HW_IPU_DC_DISP_CONF2_3(x).U = (v))
|
|
#define HW_IPU_DC_DISP_CONF2_3_SET(x, v) (HW_IPU_DC_DISP_CONF2_3_WR(x, HW_IPU_DC_DISP_CONF2_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_DISP_CONF2_3_CLR(x, v) (HW_IPU_DC_DISP_CONF2_3_WR(x, HW_IPU_DC_DISP_CONF2_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DISP_CONF2_3_TOG(x, v) (HW_IPU_DC_DISP_CONF2_3_WR(x, HW_IPU_DC_DISP_CONF2_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DISP_CONF2_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DISP_CONF2_3, field SL_3[28:0] (RW)
|
|
*
|
|
* Stride line of display 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DISP_CONF2_3_SL_3 (0) //!< Bit position for IPU_DC_DISP_CONF2_3_SL_3.
|
|
#define BM_IPU_DC_DISP_CONF2_3_SL_3 (0x1fffffff) //!< Bit mask for IPU_DC_DISP_CONF2_3_SL_3.
|
|
|
|
//! @brief Get value of IPU_DC_DISP_CONF2_3_SL_3 from a register value.
|
|
#define BG_IPU_DC_DISP_CONF2_3_SL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DISP_CONF2_3_SL_3) >> BP_IPU_DC_DISP_CONF2_3_SL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DISP_CONF2_3_SL_3.
|
|
#define BF_IPU_DC_DISP_CONF2_3_SL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DISP_CONF2_3_SL_3) & BM_IPU_DC_DISP_CONF2_3_SL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SL_3 field to a new value.
|
|
#define BW_IPU_DC_DISP_CONF2_3_SL_3(x, v) (HW_IPU_DC_DISP_CONF2_3_WR(x, (HW_IPU_DC_DISP_CONF2_3_RD(x) & ~BM_IPU_DC_DISP_CONF2_3_SL_3) | BF_IPU_DC_DISP_CONF2_3_SL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DI0_CONF_1 - DC DI0Configuration Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DI0_CONF_1 - DC DI0Configuration Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_di0_conf_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_di0_conf_1_bitfields
|
|
{
|
|
unsigned DI_READ_DATA_MASK_0 : 32; //!< [31:0] This field defines the mask value of the data read from the display.
|
|
} B;
|
|
} hw_ipu_dc_di0_conf_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DI0_CONF_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DI0_CONF_1_ADDR(x) (REGS_IPU_BASE(x) + 0x580f8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DI0_CONF_1(x) (*(volatile hw_ipu_dc_di0_conf_1_t *) HW_IPU_DC_DI0_CONF_1_ADDR(x))
|
|
#define HW_IPU_DC_DI0_CONF_1_RD(x) (HW_IPU_DC_DI0_CONF_1(x).U)
|
|
#define HW_IPU_DC_DI0_CONF_1_WR(x, v) (HW_IPU_DC_DI0_CONF_1(x).U = (v))
|
|
#define HW_IPU_DC_DI0_CONF_1_SET(x, v) (HW_IPU_DC_DI0_CONF_1_WR(x, HW_IPU_DC_DI0_CONF_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_DI0_CONF_1_CLR(x, v) (HW_IPU_DC_DI0_CONF_1_WR(x, HW_IPU_DC_DI0_CONF_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DI0_CONF_1_TOG(x, v) (HW_IPU_DC_DI0_CONF_1_WR(x, HW_IPU_DC_DI0_CONF_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DI0_CONF_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DI0_CONF_1, field DI_READ_DATA_MASK_0[31:0] (RW)
|
|
*
|
|
* This field defines the mask value of the data read from the display.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0 (0) //!< Bit position for IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0.
|
|
#define BM_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0 (0xffffffff) //!< Bit mask for IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0.
|
|
|
|
//! @brief Get value of IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0 from a register value.
|
|
#define BG_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0) >> BP_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0.
|
|
#define BF_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0) & BM_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_READ_DATA_MASK_0 field to a new value.
|
|
#define BW_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0(x, v) (HW_IPU_DC_DI0_CONF_1_WR(x, (HW_IPU_DC_DI0_CONF_1_RD(x) & ~BM_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0) | BF_IPU_DC_DI0_CONF_1_DI_READ_DATA_MASK_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DI0_CONF_2 - DC DI0Configuration Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DI0_CONF_2 - DC DI0Configuration Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_di0_conf_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_di0_conf_2_bitfields
|
|
{
|
|
unsigned DI_READ_DATA_ACK_VALUE_0 : 32; //!< [31:0] This is the expected data to be read from the display.
|
|
} B;
|
|
} hw_ipu_dc_di0_conf_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DI0_CONF_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DI0_CONF_2_ADDR(x) (REGS_IPU_BASE(x) + 0x580fc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DI0_CONF_2(x) (*(volatile hw_ipu_dc_di0_conf_2_t *) HW_IPU_DC_DI0_CONF_2_ADDR(x))
|
|
#define HW_IPU_DC_DI0_CONF_2_RD(x) (HW_IPU_DC_DI0_CONF_2(x).U)
|
|
#define HW_IPU_DC_DI0_CONF_2_WR(x, v) (HW_IPU_DC_DI0_CONF_2(x).U = (v))
|
|
#define HW_IPU_DC_DI0_CONF_2_SET(x, v) (HW_IPU_DC_DI0_CONF_2_WR(x, HW_IPU_DC_DI0_CONF_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_DI0_CONF_2_CLR(x, v) (HW_IPU_DC_DI0_CONF_2_WR(x, HW_IPU_DC_DI0_CONF_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DI0_CONF_2_TOG(x, v) (HW_IPU_DC_DI0_CONF_2_WR(x, HW_IPU_DC_DI0_CONF_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DI0_CONF_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DI0_CONF_2, field DI_READ_DATA_ACK_VALUE_0[31:0] (RW)
|
|
*
|
|
* This is the expected data to be read from the display. The value reads from the display is anded
|
|
* with the DI_READ_DATA_MASK_0 and compared with the DI_READ_DATA_ACK_VALUE_0. This field is used
|
|
* for the READ_STATUS task of the DC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0 (0) //!< Bit position for IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0.
|
|
#define BM_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0 (0xffffffff) //!< Bit mask for IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0.
|
|
|
|
//! @brief Get value of IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0 from a register value.
|
|
#define BG_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0) >> BP_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0.
|
|
#define BF_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0) & BM_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_READ_DATA_ACK_VALUE_0 field to a new value.
|
|
#define BW_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0(x, v) (HW_IPU_DC_DI0_CONF_2_WR(x, (HW_IPU_DC_DI0_CONF_2_RD(x) & ~BM_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0) | BF_IPU_DC_DI0_CONF_2_DI_READ_DATA_ACK_VALUE_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DI1_CONF_1 - DC DI1Configuration Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DI1_CONF_1 - DC DI1Configuration Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_di1_conf_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_di1_conf_1_bitfields
|
|
{
|
|
unsigned DI_READ_DATA_MASK_1 : 32; //!< [31:0] This field defines the mask value of the data read from the display.
|
|
} B;
|
|
} hw_ipu_dc_di1_conf_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DI1_CONF_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DI1_CONF_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58100)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DI1_CONF_1(x) (*(volatile hw_ipu_dc_di1_conf_1_t *) HW_IPU_DC_DI1_CONF_1_ADDR(x))
|
|
#define HW_IPU_DC_DI1_CONF_1_RD(x) (HW_IPU_DC_DI1_CONF_1(x).U)
|
|
#define HW_IPU_DC_DI1_CONF_1_WR(x, v) (HW_IPU_DC_DI1_CONF_1(x).U = (v))
|
|
#define HW_IPU_DC_DI1_CONF_1_SET(x, v) (HW_IPU_DC_DI1_CONF_1_WR(x, HW_IPU_DC_DI1_CONF_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_DI1_CONF_1_CLR(x, v) (HW_IPU_DC_DI1_CONF_1_WR(x, HW_IPU_DC_DI1_CONF_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DI1_CONF_1_TOG(x, v) (HW_IPU_DC_DI1_CONF_1_WR(x, HW_IPU_DC_DI1_CONF_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DI1_CONF_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DI1_CONF_1, field DI_READ_DATA_MASK_1[31:0] (RW)
|
|
*
|
|
* This field defines the mask value of the data read from the display.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1 (0) //!< Bit position for IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1.
|
|
#define BM_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1 (0xffffffff) //!< Bit mask for IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1.
|
|
|
|
//! @brief Get value of IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1 from a register value.
|
|
#define BG_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1) >> BP_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1.
|
|
#define BF_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1) & BM_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_READ_DATA_MASK_1 field to a new value.
|
|
#define BW_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1(x, v) (HW_IPU_DC_DI1_CONF_1_WR(x, (HW_IPU_DC_DI1_CONF_1_RD(x) & ~BM_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1) | BF_IPU_DC_DI1_CONF_1_DI_READ_DATA_MASK_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_DI1_CONF_2 - DC DI1Configuration Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_DI1_CONF_2 - DC DI1Configuration Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_di1_conf_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_di1_conf_2_bitfields
|
|
{
|
|
unsigned DI_READ_DATA_ACK_VALUE_1 : 32; //!< [31:0] This is the expected data to be read from the display.
|
|
} B;
|
|
} hw_ipu_dc_di1_conf_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_DI1_CONF_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_DI1_CONF_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58104)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_DI1_CONF_2(x) (*(volatile hw_ipu_dc_di1_conf_2_t *) HW_IPU_DC_DI1_CONF_2_ADDR(x))
|
|
#define HW_IPU_DC_DI1_CONF_2_RD(x) (HW_IPU_DC_DI1_CONF_2(x).U)
|
|
#define HW_IPU_DC_DI1_CONF_2_WR(x, v) (HW_IPU_DC_DI1_CONF_2(x).U = (v))
|
|
#define HW_IPU_DC_DI1_CONF_2_SET(x, v) (HW_IPU_DC_DI1_CONF_2_WR(x, HW_IPU_DC_DI1_CONF_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_DI1_CONF_2_CLR(x, v) (HW_IPU_DC_DI1_CONF_2_WR(x, HW_IPU_DC_DI1_CONF_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_DI1_CONF_2_TOG(x, v) (HW_IPU_DC_DI1_CONF_2_WR(x, HW_IPU_DC_DI1_CONF_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_DI1_CONF_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_DI1_CONF_2, field DI_READ_DATA_ACK_VALUE_1[31:0] (RW)
|
|
*
|
|
* This is the expected data to be read from the display. The value reads from the display is anded
|
|
* with the DI_READ_DATA_MASK_1 and compared with the DI_READ_DATA_ACK_VALUE_1 This field is used
|
|
* for the READ_STATUS task of the DC
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1 (0) //!< Bit position for IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1.
|
|
#define BM_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1 (0xffffffff) //!< Bit mask for IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1.
|
|
|
|
//! @brief Get value of IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1 from a register value.
|
|
#define BG_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1) >> BP_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1.
|
|
#define BF_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1) & BM_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DI_READ_DATA_ACK_VALUE_1 field to a new value.
|
|
#define BW_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1(x, v) (HW_IPU_DC_DI1_CONF_2_WR(x, (HW_IPU_DC_DI1_CONF_2_RD(x) & ~BM_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1) | BF_IPU_DC_DI1_CONF_2_DI_READ_DATA_ACK_VALUE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_0 - DC Mapping Configuration Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_0 - DC Mapping Configuration Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_0_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_0 : 5; //!< [4:0] Mapping pointer #0 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_0 : 5; //!< [9:5] Mapping pointer #0 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_0 : 5; //!< [14:10] Mapping pointer #0 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_1 : 5; //!< [20:16] Mapping pointer #1 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_1 : 5; //!< [25:21] Mapping pointer #1 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_1 : 5; //!< [30:26] Mapping pointer #1 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58108)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_0(x) (*(volatile hw_ipu_dc_map_conf_0_t *) HW_IPU_DC_MAP_CONF_0_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_0_RD(x) (HW_IPU_DC_MAP_CONF_0(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_0_WR(x, v) (HW_IPU_DC_MAP_CONF_0(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_0_SET(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, HW_IPU_DC_MAP_CONF_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_0_CLR(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, HW_IPU_DC_MAP_CONF_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_0_TOG(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, HW_IPU_DC_MAP_CONF_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_0, field MAPPING_PNTR_BYTE0_0[4:0] (RW)
|
|
*
|
|
* Mapping pointer #0 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0 (0) //!< Bit position for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0.
|
|
#define BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0) >> BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0.
|
|
#define BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_0 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, (HW_IPU_DC_MAP_CONF_0_RD(x) & ~BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0) | BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_0, field MAPPING_PNTR_BYTE1_0[9:5] (RW)
|
|
*
|
|
* Mapping pointer #0 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0 (5) //!< Bit position for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0.
|
|
#define BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0) >> BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0.
|
|
#define BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_0 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, (HW_IPU_DC_MAP_CONF_0_RD(x) & ~BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0) | BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_0, field MAPPING_PNTR_BYTE2_0[14:10] (RW)
|
|
*
|
|
* Mapping pointer #0 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0 (10) //!< Bit position for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0.
|
|
#define BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0) >> BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0.
|
|
#define BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_0 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, (HW_IPU_DC_MAP_CONF_0_RD(x) & ~BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0) | BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_0, field MAPPING_PNTR_BYTE0_1[20:16] (RW)
|
|
*
|
|
* Mapping pointer #1 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1 (16) //!< Bit position for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1.
|
|
#define BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1) >> BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1.
|
|
#define BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_1 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, (HW_IPU_DC_MAP_CONF_0_RD(x) & ~BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1) | BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE0_1(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_0, field MAPPING_PNTR_BYTE1_1[25:21] (RW)
|
|
*
|
|
* Mapping pointer #1 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1 (21) //!< Bit position for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1.
|
|
#define BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1.
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|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1) >> BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1)
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|
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1.
|
|
#define BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_1 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, (HW_IPU_DC_MAP_CONF_0_RD(x) & ~BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1) | BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE1_1(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_0, field MAPPING_PNTR_BYTE2_1[30:26] (RW)
|
|
*
|
|
* Mapping pointer #1 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1 (26) //!< Bit position for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1.
|
|
#define BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1.
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|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1) >> BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1)
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|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1.
|
|
#define BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1) & BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_1 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1(x, v) (HW_IPU_DC_MAP_CONF_0_WR(x, (HW_IPU_DC_MAP_CONF_0_RD(x) & ~BM_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1) | BF_IPU_DC_MAP_CONF_0_MAPPING_PNTR_BYTE2_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_1 - DC Mapping Configuration Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_1 - DC Mapping Configuration Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_1_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_2 : 5; //!< [4:0] Mapping pointer #1 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_2 : 5; //!< [9:5] Mapping pointer #1 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_2 : 5; //!< [14:10] Mapping pointer #1 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_3 : 5; //!< [20:16] Mapping pointer #3 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_3 : 5; //!< [25:21] Mapping pointer #3 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_3 : 5; //!< [30:26] Mapping pointer #3 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_1_ADDR(x) (REGS_IPU_BASE(x) + 0x5810c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_1(x) (*(volatile hw_ipu_dc_map_conf_1_t *) HW_IPU_DC_MAP_CONF_1_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_1_RD(x) (HW_IPU_DC_MAP_CONF_1(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_1_WR(x, v) (HW_IPU_DC_MAP_CONF_1(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_1_SET(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, HW_IPU_DC_MAP_CONF_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_1_CLR(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, HW_IPU_DC_MAP_CONF_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_1_TOG(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, HW_IPU_DC_MAP_CONF_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_1, field MAPPING_PNTR_BYTE0_2[4:0] (RW)
|
|
*
|
|
* Mapping pointer #1 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2 (0) //!< Bit position for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2.
|
|
#define BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2) >> BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2.
|
|
#define BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_2 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, (HW_IPU_DC_MAP_CONF_1_RD(x) & ~BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2) | BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_1, field MAPPING_PNTR_BYTE1_2[9:5] (RW)
|
|
*
|
|
* Mapping pointer #1 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2 (5) //!< Bit position for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2.
|
|
#define BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2) >> BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2.
|
|
#define BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_2 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, (HW_IPU_DC_MAP_CONF_1_RD(x) & ~BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2) | BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_1, field MAPPING_PNTR_BYTE2_2[14:10] (RW)
|
|
*
|
|
* Mapping pointer #1 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2 (10) //!< Bit position for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2.
|
|
#define BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2) >> BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2.
|
|
#define BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_2 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, (HW_IPU_DC_MAP_CONF_1_RD(x) & ~BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2) | BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_1, field MAPPING_PNTR_BYTE0_3[20:16] (RW)
|
|
*
|
|
* Mapping pointer #3 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3 (16) //!< Bit position for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3.
|
|
#define BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3) >> BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3.
|
|
#define BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_3 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, (HW_IPU_DC_MAP_CONF_1_RD(x) & ~BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3) | BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE0_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_1, field MAPPING_PNTR_BYTE1_3[25:21] (RW)
|
|
*
|
|
* Mapping pointer #3 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3 (21) //!< Bit position for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3.
|
|
#define BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3) >> BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3.
|
|
#define BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_3 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, (HW_IPU_DC_MAP_CONF_1_RD(x) & ~BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3) | BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE1_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_1, field MAPPING_PNTR_BYTE2_3[30:26] (RW)
|
|
*
|
|
* Mapping pointer #3 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3 (26) //!< Bit position for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3.
|
|
#define BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3) >> BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3.
|
|
#define BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3) & BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_3 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3(x, v) (HW_IPU_DC_MAP_CONF_1_WR(x, (HW_IPU_DC_MAP_CONF_1_RD(x) & ~BM_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3) | BF_IPU_DC_MAP_CONF_1_MAPPING_PNTR_BYTE2_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_2 - DC Mapping Configuration Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_2 - DC Mapping Configuration Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_2_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_4 : 5; //!< [4:0] Mapping pointer #4 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_4 : 5; //!< [9:5] Mapping pointer #4 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_4 : 5; //!< [14:10] Mapping pointer #4 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_5 : 5; //!< [20:16] Mapping pointer #5 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_5 : 5; //!< [25:21] Mapping pointer #5 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_5 : 5; //!< [30:26] Mapping pointer #5 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_2_ADDR(x) (REGS_IPU_BASE(x) + 0x58110)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_2(x) (*(volatile hw_ipu_dc_map_conf_2_t *) HW_IPU_DC_MAP_CONF_2_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_2_RD(x) (HW_IPU_DC_MAP_CONF_2(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_2_WR(x, v) (HW_IPU_DC_MAP_CONF_2(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_2_SET(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, HW_IPU_DC_MAP_CONF_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_2_CLR(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, HW_IPU_DC_MAP_CONF_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_2_TOG(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, HW_IPU_DC_MAP_CONF_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_2, field MAPPING_PNTR_BYTE0_4[4:0] (RW)
|
|
*
|
|
* Mapping pointer #4 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4 (0) //!< Bit position for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4.
|
|
#define BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4) >> BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4.
|
|
#define BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_4 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, (HW_IPU_DC_MAP_CONF_2_RD(x) & ~BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4) | BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_2, field MAPPING_PNTR_BYTE1_4[9:5] (RW)
|
|
*
|
|
* Mapping pointer #4 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4 (5) //!< Bit position for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4.
|
|
#define BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4) >> BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4.
|
|
#define BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_4 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, (HW_IPU_DC_MAP_CONF_2_RD(x) & ~BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4) | BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_2, field MAPPING_PNTR_BYTE2_4[14:10] (RW)
|
|
*
|
|
* Mapping pointer #4 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4 (10) //!< Bit position for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4.
|
|
#define BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4) >> BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4.
|
|
#define BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_4 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, (HW_IPU_DC_MAP_CONF_2_RD(x) & ~BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4) | BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_2, field MAPPING_PNTR_BYTE0_5[20:16] (RW)
|
|
*
|
|
* Mapping pointer #5 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5 (16) //!< Bit position for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5.
|
|
#define BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5) >> BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5.
|
|
#define BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_5 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, (HW_IPU_DC_MAP_CONF_2_RD(x) & ~BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5) | BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE0_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_2, field MAPPING_PNTR_BYTE1_5[25:21] (RW)
|
|
*
|
|
* Mapping pointer #5 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5 (21) //!< Bit position for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5.
|
|
#define BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5) >> BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5.
|
|
#define BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_5 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, (HW_IPU_DC_MAP_CONF_2_RD(x) & ~BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5) | BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE1_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_2, field MAPPING_PNTR_BYTE2_5[30:26] (RW)
|
|
*
|
|
* Mapping pointer #5 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5 (26) //!< Bit position for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5.
|
|
#define BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5) >> BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5.
|
|
#define BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5) & BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_5 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5(x, v) (HW_IPU_DC_MAP_CONF_2_WR(x, (HW_IPU_DC_MAP_CONF_2_RD(x) & ~BM_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5) | BF_IPU_DC_MAP_CONF_2_MAPPING_PNTR_BYTE2_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_3 - DC Mapping Configuration Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_3 - DC Mapping Configuration Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_3_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_6 : 5; //!< [4:0] Mapping pointer #6 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_6 : 5; //!< [9:5] Mapping pointer #6 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_6 : 5; //!< [14:10] Mapping pointer #6 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_7 : 5; //!< [20:16] Mapping pointer #7 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_7 : 5; //!< [25:21] Mapping pointer #7 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_7 : 5; //!< [30:26] Mapping pointer #7 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_3_ADDR(x) (REGS_IPU_BASE(x) + 0x58114)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_3(x) (*(volatile hw_ipu_dc_map_conf_3_t *) HW_IPU_DC_MAP_CONF_3_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_3_RD(x) (HW_IPU_DC_MAP_CONF_3(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_3_WR(x, v) (HW_IPU_DC_MAP_CONF_3(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_3_SET(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, HW_IPU_DC_MAP_CONF_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_3_CLR(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, HW_IPU_DC_MAP_CONF_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_3_TOG(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, HW_IPU_DC_MAP_CONF_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_3, field MAPPING_PNTR_BYTE0_6[4:0] (RW)
|
|
*
|
|
* Mapping pointer #6 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6 (0) //!< Bit position for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6.
|
|
#define BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6) >> BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6.
|
|
#define BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_6 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, (HW_IPU_DC_MAP_CONF_3_RD(x) & ~BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6) | BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_3, field MAPPING_PNTR_BYTE1_6[9:5] (RW)
|
|
*
|
|
* Mapping pointer #6 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6 (5) //!< Bit position for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6.
|
|
#define BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6) >> BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6.
|
|
#define BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_6 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, (HW_IPU_DC_MAP_CONF_3_RD(x) & ~BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6) | BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_3, field MAPPING_PNTR_BYTE2_6[14:10] (RW)
|
|
*
|
|
* Mapping pointer #6 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6 (10) //!< Bit position for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6.
|
|
#define BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6) >> BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6.
|
|
#define BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_6 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, (HW_IPU_DC_MAP_CONF_3_RD(x) & ~BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6) | BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_3, field MAPPING_PNTR_BYTE0_7[20:16] (RW)
|
|
*
|
|
* Mapping pointer #7 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7 (16) //!< Bit position for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7.
|
|
#define BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7) >> BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7.
|
|
#define BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_7 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, (HW_IPU_DC_MAP_CONF_3_RD(x) & ~BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7) | BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE0_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_3, field MAPPING_PNTR_BYTE1_7[25:21] (RW)
|
|
*
|
|
* Mapping pointer #7 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7 (21) //!< Bit position for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7.
|
|
#define BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7) >> BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7.
|
|
#define BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_7 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, (HW_IPU_DC_MAP_CONF_3_RD(x) & ~BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7) | BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE1_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_3, field MAPPING_PNTR_BYTE2_7[30:26] (RW)
|
|
*
|
|
* Mapping pointer #7 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7 (26) //!< Bit position for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7.
|
|
#define BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7) >> BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7.
|
|
#define BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7) & BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_7 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7(x, v) (HW_IPU_DC_MAP_CONF_3_WR(x, (HW_IPU_DC_MAP_CONF_3_RD(x) & ~BM_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7) | BF_IPU_DC_MAP_CONF_3_MAPPING_PNTR_BYTE2_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_4 - DC Mapping Configuration Register 4
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_4 - DC Mapping Configuration Register 4 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_4_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_8 : 5; //!< [4:0] Mapping pointer #8 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_8 : 5; //!< [9:5] Mapping pointer #8 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_8 : 5; //!< [14:10] Mapping pointer #8 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_9 : 5; //!< [20:16] Mapping pointer #9 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_1 : 5; //!< [25:21] Mapping pointer #9 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_9 : 5; //!< [30:26] Mapping pointer #9 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_4_ADDR(x) (REGS_IPU_BASE(x) + 0x58118)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_4(x) (*(volatile hw_ipu_dc_map_conf_4_t *) HW_IPU_DC_MAP_CONF_4_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_4_RD(x) (HW_IPU_DC_MAP_CONF_4(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_4_WR(x, v) (HW_IPU_DC_MAP_CONF_4(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_4_SET(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, HW_IPU_DC_MAP_CONF_4_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_4_CLR(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, HW_IPU_DC_MAP_CONF_4_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_4_TOG(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, HW_IPU_DC_MAP_CONF_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_4, field MAPPING_PNTR_BYTE0_8[4:0] (RW)
|
|
*
|
|
* Mapping pointer #8 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8 (0) //!< Bit position for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8.
|
|
#define BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8) >> BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8.
|
|
#define BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_8 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, (HW_IPU_DC_MAP_CONF_4_RD(x) & ~BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8) | BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_4, field MAPPING_PNTR_BYTE1_8[9:5] (RW)
|
|
*
|
|
* Mapping pointer #8 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8 (5) //!< Bit position for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8.
|
|
#define BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8) >> BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8.
|
|
#define BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_8 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, (HW_IPU_DC_MAP_CONF_4_RD(x) & ~BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8) | BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_4, field MAPPING_PNTR_BYTE2_8[14:10] (RW)
|
|
*
|
|
* Mapping pointer #8 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8 (10) //!< Bit position for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8.
|
|
#define BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8) >> BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8.
|
|
#define BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_8 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, (HW_IPU_DC_MAP_CONF_4_RD(x) & ~BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8) | BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_4, field MAPPING_PNTR_BYTE0_9[20:16] (RW)
|
|
*
|
|
* Mapping pointer #9 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9 (16) //!< Bit position for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9.
|
|
#define BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9) >> BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9.
|
|
#define BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_9 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, (HW_IPU_DC_MAP_CONF_4_RD(x) & ~BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9) | BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE0_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_4, field MAPPING_PNTR_BYTE1_1[25:21] (RW)
|
|
*
|
|
* Mapping pointer #9 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1 (21) //!< Bit position for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1.
|
|
#define BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1) >> BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1.
|
|
#define BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_1 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, (HW_IPU_DC_MAP_CONF_4_RD(x) & ~BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1) | BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE1_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_4, field MAPPING_PNTR_BYTE2_9[30:26] (RW)
|
|
*
|
|
* Mapping pointer #9 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and MD_MASK_<i>
|
|
* used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9 (26) //!< Bit position for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9.
|
|
#define BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9) >> BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9.
|
|
#define BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9) & BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_9 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9(x, v) (HW_IPU_DC_MAP_CONF_4_WR(x, (HW_IPU_DC_MAP_CONF_4_RD(x) & ~BM_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9) | BF_IPU_DC_MAP_CONF_4_MAPPING_PNTR_BYTE2_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_5 - DC Mapping Configuration Register 5
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_5 - DC Mapping Configuration Register 5 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_5
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_5_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_10 : 5; //!< [4:0] Mapping pointer #10 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_10 : 5; //!< [9:5] Mapping pointer #10 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_10 : 5; //!< [14:10] Mapping pointer #10 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_11 : 5; //!< [20:16] Mapping pointer #11 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_11 : 5; //!< [25:21] Mapping pointer #11 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_11 : 5; //!< [30:26] Mapping pointer #11 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_5_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_5 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_5_ADDR(x) (REGS_IPU_BASE(x) + 0x5811c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_5(x) (*(volatile hw_ipu_dc_map_conf_5_t *) HW_IPU_DC_MAP_CONF_5_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_5_RD(x) (HW_IPU_DC_MAP_CONF_5(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_5_WR(x, v) (HW_IPU_DC_MAP_CONF_5(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_5_SET(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, HW_IPU_DC_MAP_CONF_5_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_5_CLR(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, HW_IPU_DC_MAP_CONF_5_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_5_TOG(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, HW_IPU_DC_MAP_CONF_5_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_5 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_5, field MAPPING_PNTR_BYTE0_10[4:0] (RW)
|
|
*
|
|
* Mapping pointer #10 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10 (0) //!< Bit position for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10.
|
|
#define BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10) >> BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10.
|
|
#define BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_10 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, (HW_IPU_DC_MAP_CONF_5_RD(x) & ~BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10) | BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_5, field MAPPING_PNTR_BYTE1_10[9:5] (RW)
|
|
*
|
|
* Mapping pointer #10 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10 (5) //!< Bit position for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10.
|
|
#define BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10) >> BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10.
|
|
#define BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_10 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, (HW_IPU_DC_MAP_CONF_5_RD(x) & ~BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10) | BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_5, field MAPPING_PNTR_BYTE2_10[14:10] (RW)
|
|
*
|
|
* Mapping pointer #10 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10 (10) //!< Bit position for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10.
|
|
#define BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10) >> BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10.
|
|
#define BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_10 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, (HW_IPU_DC_MAP_CONF_5_RD(x) & ~BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10) | BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_5, field MAPPING_PNTR_BYTE0_11[20:16] (RW)
|
|
*
|
|
* Mapping pointer #11 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11 (16) //!< Bit position for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11.
|
|
#define BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11) >> BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11.
|
|
#define BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_11 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, (HW_IPU_DC_MAP_CONF_5_RD(x) & ~BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11) | BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE0_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_5, field MAPPING_PNTR_BYTE1_11[25:21] (RW)
|
|
*
|
|
* Mapping pointer #11 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11 (21) //!< Bit position for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11.
|
|
#define BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11) >> BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11.
|
|
#define BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_11 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, (HW_IPU_DC_MAP_CONF_5_RD(x) & ~BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11) | BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE1_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_5, field MAPPING_PNTR_BYTE2_11[30:26] (RW)
|
|
*
|
|
* Mapping pointer #11 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11 (26) //!< Bit position for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11.
|
|
#define BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11) >> BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11.
|
|
#define BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11) & BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_11 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11(x, v) (HW_IPU_DC_MAP_CONF_5_WR(x, (HW_IPU_DC_MAP_CONF_5_RD(x) & ~BM_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11) | BF_IPU_DC_MAP_CONF_5_MAPPING_PNTR_BYTE2_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_6 - DC Mapping Configuration Register 6
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_6 - DC Mapping Configuration Register 6 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_6
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_6_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_12 : 5; //!< [4:0] Mapping pointer #12 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_12 : 5; //!< [9:5] Mapping pointer #12 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_12 : 5; //!< [14:10] Mapping pointer #12 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_13 : 5; //!< [20:16] Mapping pointer #13 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_13 : 5; //!< [25:21] Mapping pointer #13 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_13 : 5; //!< [30:26] Mapping pointer #13 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_6_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_6 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_6_ADDR(x) (REGS_IPU_BASE(x) + 0x58120)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_6(x) (*(volatile hw_ipu_dc_map_conf_6_t *) HW_IPU_DC_MAP_CONF_6_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_6_RD(x) (HW_IPU_DC_MAP_CONF_6(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_6_WR(x, v) (HW_IPU_DC_MAP_CONF_6(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_6_SET(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, HW_IPU_DC_MAP_CONF_6_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_6_CLR(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, HW_IPU_DC_MAP_CONF_6_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_6_TOG(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, HW_IPU_DC_MAP_CONF_6_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_6 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_6, field MAPPING_PNTR_BYTE0_12[4:0] (RW)
|
|
*
|
|
* Mapping pointer #12 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12 (0) //!< Bit position for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12.
|
|
#define BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12) >> BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12.
|
|
#define BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_12 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, (HW_IPU_DC_MAP_CONF_6_RD(x) & ~BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12) | BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_6, field MAPPING_PNTR_BYTE1_12[9:5] (RW)
|
|
*
|
|
* Mapping pointer #12 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12 (5) //!< Bit position for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12.
|
|
#define BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12) >> BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12.
|
|
#define BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_12 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, (HW_IPU_DC_MAP_CONF_6_RD(x) & ~BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12) | BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_6, field MAPPING_PNTR_BYTE2_12[14:10] (RW)
|
|
*
|
|
* Mapping pointer #12 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12 (10) //!< Bit position for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12.
|
|
#define BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12) >> BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12.
|
|
#define BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_12 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, (HW_IPU_DC_MAP_CONF_6_RD(x) & ~BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12) | BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_6, field MAPPING_PNTR_BYTE0_13[20:16] (RW)
|
|
*
|
|
* Mapping pointer #13 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13 (16) //!< Bit position for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13.
|
|
#define BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13) >> BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13.
|
|
#define BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_13 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, (HW_IPU_DC_MAP_CONF_6_RD(x) & ~BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13) | BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE0_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_6, field MAPPING_PNTR_BYTE1_13[25:21] (RW)
|
|
*
|
|
* Mapping pointer #13 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13 (21) //!< Bit position for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13.
|
|
#define BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13) >> BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13.
|
|
#define BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_13 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, (HW_IPU_DC_MAP_CONF_6_RD(x) & ~BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13) | BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE1_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_6, field MAPPING_PNTR_BYTE2_13[30:26] (RW)
|
|
*
|
|
* Mapping pointer #13 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13 (26) //!< Bit position for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13.
|
|
#define BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13) >> BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13.
|
|
#define BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13) & BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_13 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13(x, v) (HW_IPU_DC_MAP_CONF_6_WR(x, (HW_IPU_DC_MAP_CONF_6_RD(x) & ~BM_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13) | BF_IPU_DC_MAP_CONF_6_MAPPING_PNTR_BYTE2_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_7 - DC Mapping Configuration Register 7
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_7 - DC Mapping Configuration Register 7 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_7
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_7_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_14 : 5; //!< [4:0] Mapping pointer #14 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_14 : 5; //!< [9:5] Mapping pointer #14 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_14 : 5; //!< [14:10] Mapping pointer #14 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_15 : 5; //!< [20:16] Mapping pointer #15 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_15 : 5; //!< [25:21] Mapping pointer #15 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_15 : 5; //!< [30:26] Mapping pointer #15 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_7_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_7 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_7_ADDR(x) (REGS_IPU_BASE(x) + 0x58124)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_7(x) (*(volatile hw_ipu_dc_map_conf_7_t *) HW_IPU_DC_MAP_CONF_7_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_7_RD(x) (HW_IPU_DC_MAP_CONF_7(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_7_WR(x, v) (HW_IPU_DC_MAP_CONF_7(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_7_SET(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, HW_IPU_DC_MAP_CONF_7_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_7_CLR(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, HW_IPU_DC_MAP_CONF_7_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_7_TOG(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, HW_IPU_DC_MAP_CONF_7_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_7 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_7, field MAPPING_PNTR_BYTE0_14[4:0] (RW)
|
|
*
|
|
* Mapping pointer #14 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14 (0) //!< Bit position for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14.
|
|
#define BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14) >> BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14.
|
|
#define BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_14 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, (HW_IPU_DC_MAP_CONF_7_RD(x) & ~BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14) | BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_7, field MAPPING_PNTR_BYTE1_14[9:5] (RW)
|
|
*
|
|
* Mapping pointer #14 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14 (5) //!< Bit position for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14.
|
|
#define BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14) >> BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14.
|
|
#define BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_14 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, (HW_IPU_DC_MAP_CONF_7_RD(x) & ~BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14) | BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_7, field MAPPING_PNTR_BYTE2_14[14:10] (RW)
|
|
*
|
|
* Mapping pointer #14 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14 (10) //!< Bit position for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14.
|
|
#define BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14) >> BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14.
|
|
#define BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_14 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, (HW_IPU_DC_MAP_CONF_7_RD(x) & ~BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14) | BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_7, field MAPPING_PNTR_BYTE0_15[20:16] (RW)
|
|
*
|
|
* Mapping pointer #15 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15 (16) //!< Bit position for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15.
|
|
#define BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15) >> BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15.
|
|
#define BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_15 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, (HW_IPU_DC_MAP_CONF_7_RD(x) & ~BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15) | BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE0_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_7, field MAPPING_PNTR_BYTE1_15[25:21] (RW)
|
|
*
|
|
* Mapping pointer #15 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15 (21) //!< Bit position for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15.
|
|
#define BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15) >> BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15.
|
|
#define BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_15 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, (HW_IPU_DC_MAP_CONF_7_RD(x) & ~BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15) | BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE1_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_7, field MAPPING_PNTR_BYTE2_15[30:26] (RW)
|
|
*
|
|
* Mapping pointer #15 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15 (26) //!< Bit position for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15.
|
|
#define BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15) >> BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15.
|
|
#define BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15) & BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_15 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15(x, v) (HW_IPU_DC_MAP_CONF_7_WR(x, (HW_IPU_DC_MAP_CONF_7_RD(x) & ~BM_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15) | BF_IPU_DC_MAP_CONF_7_MAPPING_PNTR_BYTE2_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_8 - DC Mapping Configuration Register 8
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_8 - DC Mapping Configuration Register 8 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_8
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_8_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_16 : 5; //!< [4:0] Mapping pointer #16 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_16 : 5; //!< [9:5] Mapping pointer #16 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_16 : 5; //!< [14:10] Mapping pointer #16 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_17 : 5; //!< [20:16] Mapping pointer #17 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_17 : 5; //!< [25:21] Mapping pointer #17 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_17 : 5; //!< [30:26] Mapping pointer #17 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_8_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_8 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_8_ADDR(x) (REGS_IPU_BASE(x) + 0x58128)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_8(x) (*(volatile hw_ipu_dc_map_conf_8_t *) HW_IPU_DC_MAP_CONF_8_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_8_RD(x) (HW_IPU_DC_MAP_CONF_8(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_8_WR(x, v) (HW_IPU_DC_MAP_CONF_8(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_8_SET(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, HW_IPU_DC_MAP_CONF_8_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_8_CLR(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, HW_IPU_DC_MAP_CONF_8_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_8_TOG(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, HW_IPU_DC_MAP_CONF_8_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_8 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_8, field MAPPING_PNTR_BYTE0_16[4:0] (RW)
|
|
*
|
|
* Mapping pointer #16 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16 (0) //!< Bit position for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16.
|
|
#define BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16) >> BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16.
|
|
#define BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_16 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, (HW_IPU_DC_MAP_CONF_8_RD(x) & ~BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16) | BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_8, field MAPPING_PNTR_BYTE1_16[9:5] (RW)
|
|
*
|
|
* Mapping pointer #16 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16 (5) //!< Bit position for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16.
|
|
#define BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16) >> BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16.
|
|
#define BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_16 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, (HW_IPU_DC_MAP_CONF_8_RD(x) & ~BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16) | BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_8, field MAPPING_PNTR_BYTE2_16[14:10] (RW)
|
|
*
|
|
* Mapping pointer #16 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16 (10) //!< Bit position for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16.
|
|
#define BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16) >> BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16.
|
|
#define BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_16 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, (HW_IPU_DC_MAP_CONF_8_RD(x) & ~BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16) | BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_8, field MAPPING_PNTR_BYTE0_17[20:16] (RW)
|
|
*
|
|
* Mapping pointer #17 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17 (16) //!< Bit position for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17.
|
|
#define BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17) >> BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17.
|
|
#define BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_17 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, (HW_IPU_DC_MAP_CONF_8_RD(x) & ~BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17) | BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE0_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_8, field MAPPING_PNTR_BYTE1_17[25:21] (RW)
|
|
*
|
|
* Mapping pointer #17 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17 (21) //!< Bit position for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17.
|
|
#define BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17) >> BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17.
|
|
#define BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_17 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, (HW_IPU_DC_MAP_CONF_8_RD(x) & ~BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17) | BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE1_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_8, field MAPPING_PNTR_BYTE2_17[30:26] (RW)
|
|
*
|
|
* Mapping pointer #17 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17 (26) //!< Bit position for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17.
|
|
#define BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17) >> BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17.
|
|
#define BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17) & BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_17 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17(x, v) (HW_IPU_DC_MAP_CONF_8_WR(x, (HW_IPU_DC_MAP_CONF_8_RD(x) & ~BM_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17) | BF_IPU_DC_MAP_CONF_8_MAPPING_PNTR_BYTE2_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_9 - DC Mapping Configuration Register 9
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_9 - DC Mapping Configuration Register 9 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_9
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_9_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_18 : 5; //!< [4:0] Mapping pointer #18 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_18 : 5; //!< [9:5] Mapping pointer #18 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_18 : 5; //!< [14:10] Mapping pointer #18 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_19 : 5; //!< [20:16] Mapping pointer #19 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_19 : 5; //!< [25:21] Mapping pointer #19 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_19 : 5; //!< [30:26] Mapping pointer #19 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_9_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_9 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_9_ADDR(x) (REGS_IPU_BASE(x) + 0x5812c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_9(x) (*(volatile hw_ipu_dc_map_conf_9_t *) HW_IPU_DC_MAP_CONF_9_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_9_RD(x) (HW_IPU_DC_MAP_CONF_9(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_9_WR(x, v) (HW_IPU_DC_MAP_CONF_9(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_9_SET(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, HW_IPU_DC_MAP_CONF_9_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_9_CLR(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, HW_IPU_DC_MAP_CONF_9_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_9_TOG(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, HW_IPU_DC_MAP_CONF_9_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_9 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_9, field MAPPING_PNTR_BYTE0_18[4:0] (RW)
|
|
*
|
|
* Mapping pointer #18 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18 (0) //!< Bit position for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18.
|
|
#define BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18) >> BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18.
|
|
#define BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_18 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, (HW_IPU_DC_MAP_CONF_9_RD(x) & ~BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18) | BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_9, field MAPPING_PNTR_BYTE1_18[9:5] (RW)
|
|
*
|
|
* Mapping pointer #18 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18 (5) //!< Bit position for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18.
|
|
#define BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18.
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//! @brief Get value of IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18 from a register value.
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#define BG_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18) >> BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18.
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#define BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE1_18 field to a new value.
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#define BW_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, (HW_IPU_DC_MAP_CONF_9_RD(x) & ~BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18) | BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_18(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_9, field MAPPING_PNTR_BYTE2_18[14:10] (RW)
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*
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* Mapping pointer #18 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #2
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18 (10) //!< Bit position for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18.
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#define BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18.
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//! @brief Get value of IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18 from a register value.
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#define BG_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18) >> BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18.
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#define BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE2_18 field to a new value.
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#define BW_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, (HW_IPU_DC_MAP_CONF_9_RD(x) & ~BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18) | BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_18(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_9, field MAPPING_PNTR_BYTE0_19[20:16] (RW)
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*
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* Mapping pointer #19 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #0
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19 (16) //!< Bit position for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19.
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#define BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19.
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//! @brief Get value of IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19 from a register value.
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#define BG_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19) >> BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19.
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#define BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE0_19 field to a new value.
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#define BW_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, (HW_IPU_DC_MAP_CONF_9_RD(x) & ~BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19) | BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE0_19(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_9, field MAPPING_PNTR_BYTE1_19[25:21] (RW)
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*
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* Mapping pointer #19 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #1
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19 (21) //!< Bit position for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19.
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#define BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19.
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//! @brief Get value of IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19 from a register value.
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#define BG_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19) >> BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19.
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#define BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE1_19 field to a new value.
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#define BW_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, (HW_IPU_DC_MAP_CONF_9_RD(x) & ~BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19) | BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE1_19(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_9, field MAPPING_PNTR_BYTE2_19[30:26] (RW)
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*
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* Mapping pointer #19 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #2
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19 (26) //!< Bit position for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19.
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#define BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19.
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//! @brief Get value of IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19 from a register value.
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#define BG_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19) >> BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19.
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#define BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19) & BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE2_19 field to a new value.
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#define BW_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19(x, v) (HW_IPU_DC_MAP_CONF_9_WR(x, (HW_IPU_DC_MAP_CONF_9_RD(x) & ~BM_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19) | BF_IPU_DC_MAP_CONF_9_MAPPING_PNTR_BYTE2_19(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_MAP_CONF_10 - DC Mapping Configuration Register 10
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DC_MAP_CONF_10 - DC Mapping Configuration Register 10 (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_map_conf_10
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{
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reg32_t U;
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struct _hw_ipu_dc_map_conf_10_bitfields
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{
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unsigned MAPPING_PNTR_BYTE0_20 : 5; //!< [4:0] Mapping pointer #20 for Byte 0
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unsigned MAPPING_PNTR_BYTE1_20 : 5; //!< [9:5] Mapping pointer #20 for Byte 1
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unsigned MAPPING_PNTR_BYTE2_20 : 5; //!< [14:10] Mapping pointer #20 for Byte 2
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unsigned RESERVED0 : 1; //!< [15] Reserved.
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unsigned MAPPING_PNTR_BYTE0_21 : 5; //!< [20:16] Mapping pointer #21 for Byte 0
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unsigned MAPPING_PNTR_BYTE1_21 : 5; //!< [25:21] Mapping pointer #21 for Byte 1
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unsigned MAPPING_PNTR_BYTE2_21 : 5; //!< [30:26] Mapping pointer #21 for Byte 2
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_dc_map_conf_10_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DC_MAP_CONF_10 register
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*/
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//@{
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#define HW_IPU_DC_MAP_CONF_10_ADDR(x) (REGS_IPU_BASE(x) + 0x58130)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_MAP_CONF_10(x) (*(volatile hw_ipu_dc_map_conf_10_t *) HW_IPU_DC_MAP_CONF_10_ADDR(x))
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#define HW_IPU_DC_MAP_CONF_10_RD(x) (HW_IPU_DC_MAP_CONF_10(x).U)
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#define HW_IPU_DC_MAP_CONF_10_WR(x, v) (HW_IPU_DC_MAP_CONF_10(x).U = (v))
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#define HW_IPU_DC_MAP_CONF_10_SET(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, HW_IPU_DC_MAP_CONF_10_RD(x) | (v)))
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#define HW_IPU_DC_MAP_CONF_10_CLR(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, HW_IPU_DC_MAP_CONF_10_RD(x) & ~(v)))
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#define HW_IPU_DC_MAP_CONF_10_TOG(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, HW_IPU_DC_MAP_CONF_10_RD(x) ^ (v)))
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#endif
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//@}
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|
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/*
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* constants & macros for individual IPU_DC_MAP_CONF_10 bitfields
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*/
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/*! @name Register IPU_DC_MAP_CONF_10, field MAPPING_PNTR_BYTE0_20[4:0] (RW)
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*
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* Mapping pointer #20 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #0
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20 (0) //!< Bit position for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20.
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#define BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20.
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//! @brief Get value of IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20 from a register value.
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#define BG_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20) >> BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20.
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#define BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20)
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|
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#ifndef __LANGUAGE_ASM__
|
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//! @brief Set the MAPPING_PNTR_BYTE0_20 field to a new value.
|
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#define BW_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, (HW_IPU_DC_MAP_CONF_10_RD(x) & ~BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20) | BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_20(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_10, field MAPPING_PNTR_BYTE1_20[9:5] (RW)
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*
|
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* Mapping pointer #20 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
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//@{
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#define BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20 (5) //!< Bit position for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20.
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#define BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20.
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//! @brief Get value of IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20 from a register value.
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#define BG_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20) >> BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20.
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#define BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20)
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|
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_20 field to a new value.
|
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#define BW_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, (HW_IPU_DC_MAP_CONF_10_RD(x) & ~BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20) | BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_20(v)))
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#endif
|
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//@}
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/*! @name Register IPU_DC_MAP_CONF_10, field MAPPING_PNTR_BYTE2_20[14:10] (RW)
|
|
*
|
|
* Mapping pointer #20 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
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|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20 (10) //!< Bit position for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20.
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|
#define BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20.
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|
|
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//! @brief Get value of IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20) >> BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20)
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|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20.
|
|
#define BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_20 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, (HW_IPU_DC_MAP_CONF_10_RD(x) & ~BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20) | BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_10, field MAPPING_PNTR_BYTE0_21[20:16] (RW)
|
|
*
|
|
* Mapping pointer #21 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21 (16) //!< Bit position for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21.
|
|
#define BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21) >> BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21.
|
|
#define BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_21 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, (HW_IPU_DC_MAP_CONF_10_RD(x) & ~BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21) | BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE0_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_10, field MAPPING_PNTR_BYTE1_21[25:21] (RW)
|
|
*
|
|
* Mapping pointer #21 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21 (21) //!< Bit position for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21.
|
|
#define BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21) >> BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21.
|
|
#define BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_21 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, (HW_IPU_DC_MAP_CONF_10_RD(x) & ~BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21) | BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE1_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_10, field MAPPING_PNTR_BYTE2_21[30:26] (RW)
|
|
*
|
|
* Mapping pointer #21 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21 (26) //!< Bit position for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21.
|
|
#define BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21) >> BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21.
|
|
#define BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21) & BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_21 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21(x, v) (HW_IPU_DC_MAP_CONF_10_WR(x, (HW_IPU_DC_MAP_CONF_10_RD(x) & ~BM_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21) | BF_IPU_DC_MAP_CONF_10_MAPPING_PNTR_BYTE2_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_11 - DC Mapping Configuration Register 11
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_11 - DC Mapping Configuration Register 11 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_11
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_11_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_22 : 5; //!< [4:0] Mapping pointer #22 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_22 : 5; //!< [9:5] Mapping pointer #22 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_22 : 5; //!< [14:10] Mapping pointer #22 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_23 : 5; //!< [20:16] Mapping pointer #23 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_23 : 5; //!< [25:21] Mapping pointer #23 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_23 : 5; //!< [30:26] Mapping pointer #23 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_11_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_11 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_11_ADDR(x) (REGS_IPU_BASE(x) + 0x58134)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_11(x) (*(volatile hw_ipu_dc_map_conf_11_t *) HW_IPU_DC_MAP_CONF_11_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_11_RD(x) (HW_IPU_DC_MAP_CONF_11(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_11_WR(x, v) (HW_IPU_DC_MAP_CONF_11(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_11_SET(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, HW_IPU_DC_MAP_CONF_11_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_11_CLR(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, HW_IPU_DC_MAP_CONF_11_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_11_TOG(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, HW_IPU_DC_MAP_CONF_11_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_11 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_11, field MAPPING_PNTR_BYTE0_22[4:0] (RW)
|
|
*
|
|
* Mapping pointer #22 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22 (0) //!< Bit position for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22.
|
|
#define BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22) >> BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22.
|
|
#define BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_22 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, (HW_IPU_DC_MAP_CONF_11_RD(x) & ~BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22) | BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_11, field MAPPING_PNTR_BYTE1_22[9:5] (RW)
|
|
*
|
|
* Mapping pointer #22 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22 (5) //!< Bit position for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22.
|
|
#define BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22) >> BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22.
|
|
#define BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_22 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, (HW_IPU_DC_MAP_CONF_11_RD(x) & ~BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22) | BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_11, field MAPPING_PNTR_BYTE2_22[14:10] (RW)
|
|
*
|
|
* Mapping pointer #22 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22 (10) //!< Bit position for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22.
|
|
#define BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22) >> BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22.
|
|
#define BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_22 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, (HW_IPU_DC_MAP_CONF_11_RD(x) & ~BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22) | BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_11, field MAPPING_PNTR_BYTE0_23[20:16] (RW)
|
|
*
|
|
* Mapping pointer #23 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23 (16) //!< Bit position for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23.
|
|
#define BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23) >> BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23.
|
|
#define BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_23 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, (HW_IPU_DC_MAP_CONF_11_RD(x) & ~BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23) | BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE0_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_11, field MAPPING_PNTR_BYTE1_23[25:21] (RW)
|
|
*
|
|
* Mapping pointer #23 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23 (21) //!< Bit position for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23.
|
|
#define BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23) >> BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23.
|
|
#define BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_23 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, (HW_IPU_DC_MAP_CONF_11_RD(x) & ~BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23) | BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE1_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_11, field MAPPING_PNTR_BYTE2_23[30:26] (RW)
|
|
*
|
|
* Mapping pointer #23 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23 (26) //!< Bit position for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23.
|
|
#define BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23) >> BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23.
|
|
#define BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23) & BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_23 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23(x, v) (HW_IPU_DC_MAP_CONF_11_WR(x, (HW_IPU_DC_MAP_CONF_11_RD(x) & ~BM_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23) | BF_IPU_DC_MAP_CONF_11_MAPPING_PNTR_BYTE2_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_12 - DC Mapping Configuration Register 12
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_12 - DC Mapping Configuration Register 12 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_12
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_12_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE0_24 : 5; //!< [4:0] Mapping pointer #24 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_24 : 5; //!< [9:5] Mapping pointer #24 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_24 : 5; //!< [14:10] Mapping pointer #24 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_25 : 5; //!< [20:16] Mapping pointer #25 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_25 : 5; //!< [25:21] Mapping pointer #25 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_25 : 5; //!< [30:26] Mapping pointer #25 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_12_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_12 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_12_ADDR(x) (REGS_IPU_BASE(x) + 0x58138)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_12(x) (*(volatile hw_ipu_dc_map_conf_12_t *) HW_IPU_DC_MAP_CONF_12_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_12_RD(x) (HW_IPU_DC_MAP_CONF_12(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_12_WR(x, v) (HW_IPU_DC_MAP_CONF_12(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_12_SET(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, HW_IPU_DC_MAP_CONF_12_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_12_CLR(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, HW_IPU_DC_MAP_CONF_12_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_12_TOG(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, HW_IPU_DC_MAP_CONF_12_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_12 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_12, field MAPPING_PNTR_BYTE0_24[4:0] (RW)
|
|
*
|
|
* Mapping pointer #24 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24 (0) //!< Bit position for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24.
|
|
#define BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24) >> BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24.
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#define BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE0_24 field to a new value.
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#define BW_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, (HW_IPU_DC_MAP_CONF_12_RD(x) & ~BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24) | BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_24(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_12, field MAPPING_PNTR_BYTE1_24[9:5] (RW)
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*
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* Mapping pointer #24 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #1
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24 (5) //!< Bit position for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24.
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#define BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24.
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//! @brief Get value of IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24 from a register value.
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#define BG_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24) >> BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24.
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#define BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE1_24 field to a new value.
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#define BW_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, (HW_IPU_DC_MAP_CONF_12_RD(x) & ~BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24) | BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_24(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_12, field MAPPING_PNTR_BYTE2_24[14:10] (RW)
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*
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* Mapping pointer #24 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #2
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24 (10) //!< Bit position for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24.
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#define BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24.
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//! @brief Get value of IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24 from a register value.
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#define BG_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24) >> BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24.
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#define BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE2_24 field to a new value.
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#define BW_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, (HW_IPU_DC_MAP_CONF_12_RD(x) & ~BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24) | BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_24(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_12, field MAPPING_PNTR_BYTE0_25[20:16] (RW)
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*
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* Mapping pointer #25 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #0
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25 (16) //!< Bit position for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25.
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#define BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25.
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//! @brief Get value of IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25 from a register value.
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#define BG_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25) >> BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25.
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#define BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE0_25 field to a new value.
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#define BW_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, (HW_IPU_DC_MAP_CONF_12_RD(x) & ~BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25) | BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE0_25(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_12, field MAPPING_PNTR_BYTE1_25[25:21] (RW)
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*
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* Mapping pointer #25 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #1
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25 (21) //!< Bit position for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25.
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#define BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25.
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//! @brief Get value of IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25 from a register value.
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#define BG_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25) >> BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25.
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#define BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE1_25 field to a new value.
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#define BW_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, (HW_IPU_DC_MAP_CONF_12_RD(x) & ~BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25) | BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE1_25(v)))
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#endif
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//@}
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/*! @name Register IPU_DC_MAP_CONF_12, field MAPPING_PNTR_BYTE2_25[30:26] (RW)
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*
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* Mapping pointer #25 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
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* MD_MASK_<i> used for mapping byte #2
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*/
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//@{
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#define BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25 (26) //!< Bit position for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25.
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#define BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25.
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//! @brief Get value of IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25 from a register value.
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#define BG_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25) >> BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25.
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#define BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25) & BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MAPPING_PNTR_BYTE2_25 field to a new value.
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#define BW_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25(x, v) (HW_IPU_DC_MAP_CONF_12_WR(x, (HW_IPU_DC_MAP_CONF_12_RD(x) & ~BM_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25) | BF_IPU_DC_MAP_CONF_12_MAPPING_PNTR_BYTE2_25(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DC_MAP_CONF_13 - DC Mapping Configuration Register 13
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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|
* @brief HW_IPU_DC_MAP_CONF_13 - DC Mapping Configuration Register 13 (RW)
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*
|
|
* Reset value: 0x00000000
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*/
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typedef union _hw_ipu_dc_map_conf_13
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|
{
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reg32_t U;
|
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struct _hw_ipu_dc_map_conf_13_bitfields
|
|
{
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unsigned MAPPING_PNTR_BYTE0_26 : 5; //!< [4:0] Mapping pointer #26 for Byte 0
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unsigned MAPPING_PNTR_BYTE1_26 : 5; //!< [9:5] Mapping pointer #26 for Byte 1
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unsigned MAPPING_PNTR_BYTE2_26 : 5; //!< [14:10] Mapping pointer #26 for Byte 2
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unsigned RESERVED0 : 1; //!< [15] Reserved.
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unsigned MAPPING_PNTR_BYTE0_27 : 5; //!< [20:16] Mapping pointer #27 for Byte 0
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unsigned MAPPING_PNTR_BYTE1_27 : 5; //!< [25:21] Mapping pointer #27 for Byte 1
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unsigned MAPPING_PNTR_BYTE2_27 : 5; //!< [30:26] Mapping pointer #27 for Byte 2
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unsigned RESERVED1 : 1; //!< [31] Reserved.
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} B;
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} hw_ipu_dc_map_conf_13_t;
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|
#endif
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|
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/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_13 register
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|
*/
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//@{
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|
#define HW_IPU_DC_MAP_CONF_13_ADDR(x) (REGS_IPU_BASE(x) + 0x5813c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DC_MAP_CONF_13(x) (*(volatile hw_ipu_dc_map_conf_13_t *) HW_IPU_DC_MAP_CONF_13_ADDR(x))
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#define HW_IPU_DC_MAP_CONF_13_RD(x) (HW_IPU_DC_MAP_CONF_13(x).U)
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#define HW_IPU_DC_MAP_CONF_13_WR(x, v) (HW_IPU_DC_MAP_CONF_13(x).U = (v))
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#define HW_IPU_DC_MAP_CONF_13_SET(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, HW_IPU_DC_MAP_CONF_13_RD(x) | (v)))
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#define HW_IPU_DC_MAP_CONF_13_CLR(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, HW_IPU_DC_MAP_CONF_13_RD(x) & ~(v)))
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#define HW_IPU_DC_MAP_CONF_13_TOG(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, HW_IPU_DC_MAP_CONF_13_RD(x) ^ (v)))
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#endif
|
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//@}
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|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_13 bitfields
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|
*/
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/*! @name Register IPU_DC_MAP_CONF_13, field MAPPING_PNTR_BYTE0_26[4:0] (RW)
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|
*
|
|
* Mapping pointer #26 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
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|
*/
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|
//@{
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|
#define BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26 (0) //!< Bit position for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26.
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#define BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26.
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//! @brief Get value of IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26 from a register value.
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#define BG_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26) >> BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26)
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26.
|
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#define BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_26 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, (HW_IPU_DC_MAP_CONF_13_RD(x) & ~BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26) | BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_26(v)))
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#endif
|
|
//@}
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/*! @name Register IPU_DC_MAP_CONF_13, field MAPPING_PNTR_BYTE1_26[9:5] (RW)
|
|
*
|
|
* Mapping pointer #26 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
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|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26 (5) //!< Bit position for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26.
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|
#define BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26.
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//! @brief Get value of IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26) >> BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26)
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|
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//! @brief Format value for bitfield IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26.
|
|
#define BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_26 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, (HW_IPU_DC_MAP_CONF_13_RD(x) & ~BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26) | BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_13, field MAPPING_PNTR_BYTE2_26[14:10] (RW)
|
|
*
|
|
* Mapping pointer #26 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26 (10) //!< Bit position for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26.
|
|
#define BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26 (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26) >> BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26.
|
|
#define BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_26 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, (HW_IPU_DC_MAP_CONF_13_RD(x) & ~BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26) | BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_26(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_13, field MAPPING_PNTR_BYTE0_27[20:16] (RW)
|
|
*
|
|
* Mapping pointer #27 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27 (16) //!< Bit position for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27.
|
|
#define BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27) >> BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27.
|
|
#define BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_27 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, (HW_IPU_DC_MAP_CONF_13_RD(x) & ~BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27) | BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE0_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_13, field MAPPING_PNTR_BYTE1_27[25:21] (RW)
|
|
*
|
|
* Mapping pointer #27 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27 (21) //!< Bit position for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27.
|
|
#define BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27) >> BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27.
|
|
#define BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_27 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, (HW_IPU_DC_MAP_CONF_13_RD(x) & ~BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27) | BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE1_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_13, field MAPPING_PNTR_BYTE2_27[30:26] (RW)
|
|
*
|
|
* Mapping pointer #27 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27 (26) //!< Bit position for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27.
|
|
#define BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27) >> BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27.
|
|
#define BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27) & BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_27 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27(x, v) (HW_IPU_DC_MAP_CONF_13_WR(x, (HW_IPU_DC_MAP_CONF_13_RD(x) & ~BM_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27) | BF_IPU_DC_MAP_CONF_13_MAPPING_PNTR_BYTE2_27(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_14 - DC Mapping Configuration Register 14
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_14 - DC Mapping Configuration Register 14 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_14
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_14_bitfields
|
|
{
|
|
unsigned MAPPING_PNTR_BYTE2_28 : 5; //!< [4:0] Mapping pointer #28 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_28 : 5; //!< [9:5] Mapping pointer #28 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_28F : 5; //!< [14:10] Mapping pointer #28 for Byte 2
|
|
unsigned RESERVED0 : 1; //!< [15] Reserved.
|
|
unsigned MAPPING_PNTR_BYTE0_29 : 5; //!< [20:16] Mapping pointer #29 for Byte 0
|
|
unsigned MAPPING_PNTR_BYTE1_29 : 5; //!< [25:21] Mapping pointer #29 for Byte 1
|
|
unsigned MAPPING_PNTR_BYTE2_29 : 5; //!< [30:26] Mapping pointer #29 for Byte 2
|
|
unsigned RESERVED1 : 1; //!< [31] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_14_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_14 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_14_ADDR(x) (REGS_IPU_BASE(x) + 0x58140)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_14(x) (*(volatile hw_ipu_dc_map_conf_14_t *) HW_IPU_DC_MAP_CONF_14_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_14_RD(x) (HW_IPU_DC_MAP_CONF_14(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_14_WR(x, v) (HW_IPU_DC_MAP_CONF_14(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_14_SET(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, HW_IPU_DC_MAP_CONF_14_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_14_CLR(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, HW_IPU_DC_MAP_CONF_14_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_14_TOG(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, HW_IPU_DC_MAP_CONF_14_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_14 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_14, field MAPPING_PNTR_BYTE2_28[4:0] (RW)
|
|
*
|
|
* Mapping pointer #28 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28 (0) //!< Bit position for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28.
|
|
#define BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28 (0x0000001f) //!< Bit mask for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28) >> BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28.
|
|
#define BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_28 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, (HW_IPU_DC_MAP_CONF_14_RD(x) & ~BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28) | BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_14, field MAPPING_PNTR_BYTE1_28[9:5] (RW)
|
|
*
|
|
* Mapping pointer #28 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28 (5) //!< Bit position for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28.
|
|
#define BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28 (0x000003e0) //!< Bit mask for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28) >> BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28.
|
|
#define BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_28 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, (HW_IPU_DC_MAP_CONF_14_RD(x) & ~BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28) | BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_28(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_14, field MAPPING_PNTR_BYTE2_28F[14:10] (RW)
|
|
*
|
|
* Mapping pointer #28 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F (10) //!< Bit position for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F.
|
|
#define BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F (0x00007c00) //!< Bit mask for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F) >> BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F.
|
|
#define BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_28F field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, (HW_IPU_DC_MAP_CONF_14_RD(x) & ~BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F) | BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_28F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_14, field MAPPING_PNTR_BYTE0_29[20:16] (RW)
|
|
*
|
|
* Mapping pointer #29 for Byte 0 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #0
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29 (16) //!< Bit position for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29.
|
|
#define BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29 (0x001f0000) //!< Bit mask for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29) >> BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29.
|
|
#define BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE0_29 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, (HW_IPU_DC_MAP_CONF_14_RD(x) & ~BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29) | BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE0_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_14, field MAPPING_PNTR_BYTE1_29[25:21] (RW)
|
|
*
|
|
* Mapping pointer #29 for Byte 1 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29 (21) //!< Bit position for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29.
|
|
#define BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29 (0x03e00000) //!< Bit mask for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29) >> BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29.
|
|
#define BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE1_29 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, (HW_IPU_DC_MAP_CONF_14_RD(x) & ~BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29) | BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE1_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_14, field MAPPING_PNTR_BYTE2_29[30:26] (RW)
|
|
*
|
|
* Mapping pointer #29 for Byte 2 This field is a pointer to the set of MD_OFFSET_<i> and
|
|
* MD_MASK_<i> used for mapping byte #2
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29 (26) //!< Bit position for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29.
|
|
#define BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29 (0x7c000000) //!< Bit mask for IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29) >> BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29.
|
|
#define BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29) & BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MAPPING_PNTR_BYTE2_29 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29(x, v) (HW_IPU_DC_MAP_CONF_14_WR(x, (HW_IPU_DC_MAP_CONF_14_RD(x) & ~BM_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29) | BF_IPU_DC_MAP_CONF_14_MAPPING_PNTR_BYTE2_29(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_15 - DC Mapping Configuration Register 15
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_15 - DC Mapping Configuration Register 15 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_15
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_15_bitfields
|
|
{
|
|
unsigned MD_MASK_0 : 8; //!< [7:0] Mapping unit's mask value #0
|
|
unsigned MD_OFFSET_0 : 5; //!< [12:8] Mapping unit's offset parameter #0
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_1 : 8; //!< [23:16] Mapping unit's mask value #1
|
|
unsigned MD_OFFSET_1 : 5; //!< [28:24] Mapping unit's offset parameter #1
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_15_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_15 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_15_ADDR(x) (REGS_IPU_BASE(x) + 0x58144)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_15(x) (*(volatile hw_ipu_dc_map_conf_15_t *) HW_IPU_DC_MAP_CONF_15_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_15_RD(x) (HW_IPU_DC_MAP_CONF_15(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_15_WR(x, v) (HW_IPU_DC_MAP_CONF_15(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_15_SET(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, HW_IPU_DC_MAP_CONF_15_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_15_CLR(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, HW_IPU_DC_MAP_CONF_15_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_15_TOG(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, HW_IPU_DC_MAP_CONF_15_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_15 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_15, field MD_MASK_0[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #0 This field defines the mask value #0 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_15_MD_MASK_0 (0) //!< Bit position for IPU_DC_MAP_CONF_15_MD_MASK_0.
|
|
#define BM_IPU_DC_MAP_CONF_15_MD_MASK_0 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_15_MD_MASK_0.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_15_MD_MASK_0 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_15_MD_MASK_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_15_MD_MASK_0) >> BP_IPU_DC_MAP_CONF_15_MD_MASK_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_15_MD_MASK_0.
|
|
#define BF_IPU_DC_MAP_CONF_15_MD_MASK_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_15_MD_MASK_0) & BM_IPU_DC_MAP_CONF_15_MD_MASK_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_0 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_15_MD_MASK_0(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, (HW_IPU_DC_MAP_CONF_15_RD(x) & ~BM_IPU_DC_MAP_CONF_15_MD_MASK_0) | BF_IPU_DC_MAP_CONF_15_MD_MASK_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_15, field MD_OFFSET_0[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #0 This field defines the offset parameter #0 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_15_MD_OFFSET_0 (8) //!< Bit position for IPU_DC_MAP_CONF_15_MD_OFFSET_0.
|
|
#define BM_IPU_DC_MAP_CONF_15_MD_OFFSET_0 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_15_MD_OFFSET_0.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_15_MD_OFFSET_0 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_15_MD_OFFSET_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_15_MD_OFFSET_0) >> BP_IPU_DC_MAP_CONF_15_MD_OFFSET_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_15_MD_OFFSET_0.
|
|
#define BF_IPU_DC_MAP_CONF_15_MD_OFFSET_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_15_MD_OFFSET_0) & BM_IPU_DC_MAP_CONF_15_MD_OFFSET_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_0 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_15_MD_OFFSET_0(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, (HW_IPU_DC_MAP_CONF_15_RD(x) & ~BM_IPU_DC_MAP_CONF_15_MD_OFFSET_0) | BF_IPU_DC_MAP_CONF_15_MD_OFFSET_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_15, field MD_MASK_1[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #1 This field defines the mask value #1 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_15_MD_MASK_1 (16) //!< Bit position for IPU_DC_MAP_CONF_15_MD_MASK_1.
|
|
#define BM_IPU_DC_MAP_CONF_15_MD_MASK_1 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_15_MD_MASK_1.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_15_MD_MASK_1 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_15_MD_MASK_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_15_MD_MASK_1) >> BP_IPU_DC_MAP_CONF_15_MD_MASK_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_15_MD_MASK_1.
|
|
#define BF_IPU_DC_MAP_CONF_15_MD_MASK_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_15_MD_MASK_1) & BM_IPU_DC_MAP_CONF_15_MD_MASK_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_1 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_15_MD_MASK_1(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, (HW_IPU_DC_MAP_CONF_15_RD(x) & ~BM_IPU_DC_MAP_CONF_15_MD_MASK_1) | BF_IPU_DC_MAP_CONF_15_MD_MASK_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_15, field MD_OFFSET_1[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #1 This field defines the offset parameter #1 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_15_MD_OFFSET_1 (24) //!< Bit position for IPU_DC_MAP_CONF_15_MD_OFFSET_1.
|
|
#define BM_IPU_DC_MAP_CONF_15_MD_OFFSET_1 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_15_MD_OFFSET_1.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_15_MD_OFFSET_1 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_15_MD_OFFSET_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_15_MD_OFFSET_1) >> BP_IPU_DC_MAP_CONF_15_MD_OFFSET_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_15_MD_OFFSET_1.
|
|
#define BF_IPU_DC_MAP_CONF_15_MD_OFFSET_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_15_MD_OFFSET_1) & BM_IPU_DC_MAP_CONF_15_MD_OFFSET_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_1 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_15_MD_OFFSET_1(x, v) (HW_IPU_DC_MAP_CONF_15_WR(x, (HW_IPU_DC_MAP_CONF_15_RD(x) & ~BM_IPU_DC_MAP_CONF_15_MD_OFFSET_1) | BF_IPU_DC_MAP_CONF_15_MD_OFFSET_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_16 - DC Mapping Configuration Register 16
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_16 - DC Mapping Configuration Register 16 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_16
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_16_bitfields
|
|
{
|
|
unsigned MD_MASK_0 : 8; //!< [7:0] Mapping unit's mask value #2
|
|
unsigned MD_OFFSET_2 : 5; //!< [12:8] Mapping unit's offset parameter #2
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_3 : 8; //!< [23:16] Mapping unit's mask value #3
|
|
unsigned MD_OFFSET_3 : 5; //!< [28:24] Mapping unit's offset parameter #3
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_16_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_16 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_16_ADDR(x) (REGS_IPU_BASE(x) + 0x58148)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_16(x) (*(volatile hw_ipu_dc_map_conf_16_t *) HW_IPU_DC_MAP_CONF_16_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_16_RD(x) (HW_IPU_DC_MAP_CONF_16(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_16_WR(x, v) (HW_IPU_DC_MAP_CONF_16(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_16_SET(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, HW_IPU_DC_MAP_CONF_16_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_16_CLR(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, HW_IPU_DC_MAP_CONF_16_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_16_TOG(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, HW_IPU_DC_MAP_CONF_16_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_16 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_16, field MD_MASK_0[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #2 This field defines the mask value #2 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_16_MD_MASK_0 (0) //!< Bit position for IPU_DC_MAP_CONF_16_MD_MASK_0.
|
|
#define BM_IPU_DC_MAP_CONF_16_MD_MASK_0 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_16_MD_MASK_0.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_16_MD_MASK_0 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_16_MD_MASK_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_16_MD_MASK_0) >> BP_IPU_DC_MAP_CONF_16_MD_MASK_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_16_MD_MASK_0.
|
|
#define BF_IPU_DC_MAP_CONF_16_MD_MASK_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_16_MD_MASK_0) & BM_IPU_DC_MAP_CONF_16_MD_MASK_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_0 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_16_MD_MASK_0(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, (HW_IPU_DC_MAP_CONF_16_RD(x) & ~BM_IPU_DC_MAP_CONF_16_MD_MASK_0) | BF_IPU_DC_MAP_CONF_16_MD_MASK_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_16, field MD_OFFSET_2[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #2 This field defines the offset parameter #2 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_16_MD_OFFSET_2 (8) //!< Bit position for IPU_DC_MAP_CONF_16_MD_OFFSET_2.
|
|
#define BM_IPU_DC_MAP_CONF_16_MD_OFFSET_2 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_16_MD_OFFSET_2.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_16_MD_OFFSET_2 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_16_MD_OFFSET_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_16_MD_OFFSET_2) >> BP_IPU_DC_MAP_CONF_16_MD_OFFSET_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_16_MD_OFFSET_2.
|
|
#define BF_IPU_DC_MAP_CONF_16_MD_OFFSET_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_16_MD_OFFSET_2) & BM_IPU_DC_MAP_CONF_16_MD_OFFSET_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_2 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_16_MD_OFFSET_2(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, (HW_IPU_DC_MAP_CONF_16_RD(x) & ~BM_IPU_DC_MAP_CONF_16_MD_OFFSET_2) | BF_IPU_DC_MAP_CONF_16_MD_OFFSET_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_16, field MD_MASK_3[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #3 This field defines the mask value #3 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_16_MD_MASK_3 (16) //!< Bit position for IPU_DC_MAP_CONF_16_MD_MASK_3.
|
|
#define BM_IPU_DC_MAP_CONF_16_MD_MASK_3 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_16_MD_MASK_3.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_16_MD_MASK_3 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_16_MD_MASK_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_16_MD_MASK_3) >> BP_IPU_DC_MAP_CONF_16_MD_MASK_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_16_MD_MASK_3.
|
|
#define BF_IPU_DC_MAP_CONF_16_MD_MASK_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_16_MD_MASK_3) & BM_IPU_DC_MAP_CONF_16_MD_MASK_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_3 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_16_MD_MASK_3(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, (HW_IPU_DC_MAP_CONF_16_RD(x) & ~BM_IPU_DC_MAP_CONF_16_MD_MASK_3) | BF_IPU_DC_MAP_CONF_16_MD_MASK_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_16, field MD_OFFSET_3[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #3 This field defines the offset parameter #3 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_16_MD_OFFSET_3 (24) //!< Bit position for IPU_DC_MAP_CONF_16_MD_OFFSET_3.
|
|
#define BM_IPU_DC_MAP_CONF_16_MD_OFFSET_3 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_16_MD_OFFSET_3.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_16_MD_OFFSET_3 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_16_MD_OFFSET_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_16_MD_OFFSET_3) >> BP_IPU_DC_MAP_CONF_16_MD_OFFSET_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_16_MD_OFFSET_3.
|
|
#define BF_IPU_DC_MAP_CONF_16_MD_OFFSET_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_16_MD_OFFSET_3) & BM_IPU_DC_MAP_CONF_16_MD_OFFSET_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_3 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_16_MD_OFFSET_3(x, v) (HW_IPU_DC_MAP_CONF_16_WR(x, (HW_IPU_DC_MAP_CONF_16_RD(x) & ~BM_IPU_DC_MAP_CONF_16_MD_OFFSET_3) | BF_IPU_DC_MAP_CONF_16_MD_OFFSET_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_17 - DC Mapping Configuration Register 17
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_17 - DC Mapping Configuration Register 17 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_17
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_17_bitfields
|
|
{
|
|
unsigned MD_MASK_4 : 8; //!< [7:0] Mapping unit's mask value #4
|
|
unsigned MD_OFFSET_4 : 5; //!< [12:8] Mapping unit's offset parameter #4
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_5 : 8; //!< [23:16] Mapping unit's mask value #5
|
|
unsigned MD_OFFSET_5 : 5; //!< [28:24] Mapping unit's offset parameter #5
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_17_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_17 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_17_ADDR(x) (REGS_IPU_BASE(x) + 0x5814c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_17(x) (*(volatile hw_ipu_dc_map_conf_17_t *) HW_IPU_DC_MAP_CONF_17_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_17_RD(x) (HW_IPU_DC_MAP_CONF_17(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_17_WR(x, v) (HW_IPU_DC_MAP_CONF_17(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_17_SET(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, HW_IPU_DC_MAP_CONF_17_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_17_CLR(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, HW_IPU_DC_MAP_CONF_17_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_17_TOG(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, HW_IPU_DC_MAP_CONF_17_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_17 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_17, field MD_MASK_4[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #4 This field defines the mask value #4 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_17_MD_MASK_4 (0) //!< Bit position for IPU_DC_MAP_CONF_17_MD_MASK_4.
|
|
#define BM_IPU_DC_MAP_CONF_17_MD_MASK_4 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_17_MD_MASK_4.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_17_MD_MASK_4 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_17_MD_MASK_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_17_MD_MASK_4) >> BP_IPU_DC_MAP_CONF_17_MD_MASK_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_17_MD_MASK_4.
|
|
#define BF_IPU_DC_MAP_CONF_17_MD_MASK_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_17_MD_MASK_4) & BM_IPU_DC_MAP_CONF_17_MD_MASK_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_4 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_17_MD_MASK_4(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, (HW_IPU_DC_MAP_CONF_17_RD(x) & ~BM_IPU_DC_MAP_CONF_17_MD_MASK_4) | BF_IPU_DC_MAP_CONF_17_MD_MASK_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_17, field MD_OFFSET_4[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #4 This field defines the offset parameter #4 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_17_MD_OFFSET_4 (8) //!< Bit position for IPU_DC_MAP_CONF_17_MD_OFFSET_4.
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|
#define BM_IPU_DC_MAP_CONF_17_MD_OFFSET_4 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_17_MD_OFFSET_4.
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|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_17_MD_OFFSET_4 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_17_MD_OFFSET_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_17_MD_OFFSET_4) >> BP_IPU_DC_MAP_CONF_17_MD_OFFSET_4)
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|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_17_MD_OFFSET_4.
|
|
#define BF_IPU_DC_MAP_CONF_17_MD_OFFSET_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_17_MD_OFFSET_4) & BM_IPU_DC_MAP_CONF_17_MD_OFFSET_4)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_4 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_17_MD_OFFSET_4(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, (HW_IPU_DC_MAP_CONF_17_RD(x) & ~BM_IPU_DC_MAP_CONF_17_MD_OFFSET_4) | BF_IPU_DC_MAP_CONF_17_MD_OFFSET_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_17, field MD_MASK_5[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #5 This field defines the mask value #5 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_17_MD_MASK_5 (16) //!< Bit position for IPU_DC_MAP_CONF_17_MD_MASK_5.
|
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#define BM_IPU_DC_MAP_CONF_17_MD_MASK_5 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_17_MD_MASK_5.
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|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_17_MD_MASK_5 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_17_MD_MASK_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_17_MD_MASK_5) >> BP_IPU_DC_MAP_CONF_17_MD_MASK_5)
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|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_17_MD_MASK_5.
|
|
#define BF_IPU_DC_MAP_CONF_17_MD_MASK_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_17_MD_MASK_5) & BM_IPU_DC_MAP_CONF_17_MD_MASK_5)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_5 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_17_MD_MASK_5(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, (HW_IPU_DC_MAP_CONF_17_RD(x) & ~BM_IPU_DC_MAP_CONF_17_MD_MASK_5) | BF_IPU_DC_MAP_CONF_17_MD_MASK_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_17, field MD_OFFSET_5[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #5 This field defines the offset parameter #5 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_17_MD_OFFSET_5 (24) //!< Bit position for IPU_DC_MAP_CONF_17_MD_OFFSET_5.
|
|
#define BM_IPU_DC_MAP_CONF_17_MD_OFFSET_5 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_17_MD_OFFSET_5.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_17_MD_OFFSET_5 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_17_MD_OFFSET_5(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_17_MD_OFFSET_5) >> BP_IPU_DC_MAP_CONF_17_MD_OFFSET_5)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_17_MD_OFFSET_5.
|
|
#define BF_IPU_DC_MAP_CONF_17_MD_OFFSET_5(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_17_MD_OFFSET_5) & BM_IPU_DC_MAP_CONF_17_MD_OFFSET_5)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_5 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_17_MD_OFFSET_5(x, v) (HW_IPU_DC_MAP_CONF_17_WR(x, (HW_IPU_DC_MAP_CONF_17_RD(x) & ~BM_IPU_DC_MAP_CONF_17_MD_OFFSET_5) | BF_IPU_DC_MAP_CONF_17_MD_OFFSET_5(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_18 - DC Mapping Configuration Register 18
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_18 - DC Mapping Configuration Register 18 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_18
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_18_bitfields
|
|
{
|
|
unsigned MD_MASK_6 : 8; //!< [7:0] Mapping unit's mask value #6
|
|
unsigned MD_OFFSET_6 : 5; //!< [12:8] Mapping unit's offset parameter #6
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_7 : 8; //!< [23:16] Mapping unit's mask value #7
|
|
unsigned MD_OFFSET_7 : 5; //!< [28:24] Mapping unit's offset parameter #7
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_18_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_18 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_18_ADDR(x) (REGS_IPU_BASE(x) + 0x58150)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_18(x) (*(volatile hw_ipu_dc_map_conf_18_t *) HW_IPU_DC_MAP_CONF_18_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_18_RD(x) (HW_IPU_DC_MAP_CONF_18(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_18_WR(x, v) (HW_IPU_DC_MAP_CONF_18(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_18_SET(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, HW_IPU_DC_MAP_CONF_18_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_18_CLR(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, HW_IPU_DC_MAP_CONF_18_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_18_TOG(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, HW_IPU_DC_MAP_CONF_18_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_18 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_18, field MD_MASK_6[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #6 This field defines the mask value #6 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_18_MD_MASK_6 (0) //!< Bit position for IPU_DC_MAP_CONF_18_MD_MASK_6.
|
|
#define BM_IPU_DC_MAP_CONF_18_MD_MASK_6 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_18_MD_MASK_6.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_18_MD_MASK_6 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_18_MD_MASK_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_18_MD_MASK_6) >> BP_IPU_DC_MAP_CONF_18_MD_MASK_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_18_MD_MASK_6.
|
|
#define BF_IPU_DC_MAP_CONF_18_MD_MASK_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_18_MD_MASK_6) & BM_IPU_DC_MAP_CONF_18_MD_MASK_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_6 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_18_MD_MASK_6(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, (HW_IPU_DC_MAP_CONF_18_RD(x) & ~BM_IPU_DC_MAP_CONF_18_MD_MASK_6) | BF_IPU_DC_MAP_CONF_18_MD_MASK_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_18, field MD_OFFSET_6[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #6 This field defines the offset parameter #6 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_18_MD_OFFSET_6 (8) //!< Bit position for IPU_DC_MAP_CONF_18_MD_OFFSET_6.
|
|
#define BM_IPU_DC_MAP_CONF_18_MD_OFFSET_6 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_18_MD_OFFSET_6.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_18_MD_OFFSET_6 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_18_MD_OFFSET_6(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_18_MD_OFFSET_6) >> BP_IPU_DC_MAP_CONF_18_MD_OFFSET_6)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_18_MD_OFFSET_6.
|
|
#define BF_IPU_DC_MAP_CONF_18_MD_OFFSET_6(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_18_MD_OFFSET_6) & BM_IPU_DC_MAP_CONF_18_MD_OFFSET_6)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_6 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_18_MD_OFFSET_6(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, (HW_IPU_DC_MAP_CONF_18_RD(x) & ~BM_IPU_DC_MAP_CONF_18_MD_OFFSET_6) | BF_IPU_DC_MAP_CONF_18_MD_OFFSET_6(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_18, field MD_MASK_7[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #7 This field defines the mask value #7 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_18_MD_MASK_7 (16) //!< Bit position for IPU_DC_MAP_CONF_18_MD_MASK_7.
|
|
#define BM_IPU_DC_MAP_CONF_18_MD_MASK_7 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_18_MD_MASK_7.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_18_MD_MASK_7 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_18_MD_MASK_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_18_MD_MASK_7) >> BP_IPU_DC_MAP_CONF_18_MD_MASK_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_18_MD_MASK_7.
|
|
#define BF_IPU_DC_MAP_CONF_18_MD_MASK_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_18_MD_MASK_7) & BM_IPU_DC_MAP_CONF_18_MD_MASK_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_7 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_18_MD_MASK_7(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, (HW_IPU_DC_MAP_CONF_18_RD(x) & ~BM_IPU_DC_MAP_CONF_18_MD_MASK_7) | BF_IPU_DC_MAP_CONF_18_MD_MASK_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_18, field MD_OFFSET_7[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #7 This field defines the offset parameter #7 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_18_MD_OFFSET_7 (24) //!< Bit position for IPU_DC_MAP_CONF_18_MD_OFFSET_7.
|
|
#define BM_IPU_DC_MAP_CONF_18_MD_OFFSET_7 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_18_MD_OFFSET_7.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_18_MD_OFFSET_7 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_18_MD_OFFSET_7(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_18_MD_OFFSET_7) >> BP_IPU_DC_MAP_CONF_18_MD_OFFSET_7)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_18_MD_OFFSET_7.
|
|
#define BF_IPU_DC_MAP_CONF_18_MD_OFFSET_7(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_18_MD_OFFSET_7) & BM_IPU_DC_MAP_CONF_18_MD_OFFSET_7)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_7 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_18_MD_OFFSET_7(x, v) (HW_IPU_DC_MAP_CONF_18_WR(x, (HW_IPU_DC_MAP_CONF_18_RD(x) & ~BM_IPU_DC_MAP_CONF_18_MD_OFFSET_7) | BF_IPU_DC_MAP_CONF_18_MD_OFFSET_7(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_19 - DC Mapping Configuration Register 19
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_19 - DC Mapping Configuration Register 19 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_19
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_19_bitfields
|
|
{
|
|
unsigned MD_MASK_8 : 8; //!< [7:0] Mapping unit's mask value #8
|
|
unsigned MD_OFFSET_8 : 5; //!< [12:8] Mapping unit's offset parameter #8
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_9 : 8; //!< [23:16] Mapping unit's mask value #9
|
|
unsigned MD_OFFSET_9 : 5; //!< [28:24] Mapping unit's offset parameter #9
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_19_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_19 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_19_ADDR(x) (REGS_IPU_BASE(x) + 0x58154)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_19(x) (*(volatile hw_ipu_dc_map_conf_19_t *) HW_IPU_DC_MAP_CONF_19_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_19_RD(x) (HW_IPU_DC_MAP_CONF_19(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_19_WR(x, v) (HW_IPU_DC_MAP_CONF_19(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_19_SET(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, HW_IPU_DC_MAP_CONF_19_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_19_CLR(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, HW_IPU_DC_MAP_CONF_19_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_19_TOG(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, HW_IPU_DC_MAP_CONF_19_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_19 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_19, field MD_MASK_8[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #8 This field defines the mask value #8 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_19_MD_MASK_8 (0) //!< Bit position for IPU_DC_MAP_CONF_19_MD_MASK_8.
|
|
#define BM_IPU_DC_MAP_CONF_19_MD_MASK_8 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_19_MD_MASK_8.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_19_MD_MASK_8 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_19_MD_MASK_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_19_MD_MASK_8) >> BP_IPU_DC_MAP_CONF_19_MD_MASK_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_19_MD_MASK_8.
|
|
#define BF_IPU_DC_MAP_CONF_19_MD_MASK_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_19_MD_MASK_8) & BM_IPU_DC_MAP_CONF_19_MD_MASK_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_8 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_19_MD_MASK_8(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, (HW_IPU_DC_MAP_CONF_19_RD(x) & ~BM_IPU_DC_MAP_CONF_19_MD_MASK_8) | BF_IPU_DC_MAP_CONF_19_MD_MASK_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_19, field MD_OFFSET_8[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #8 This field defines the offset parameter #8 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_19_MD_OFFSET_8 (8) //!< Bit position for IPU_DC_MAP_CONF_19_MD_OFFSET_8.
|
|
#define BM_IPU_DC_MAP_CONF_19_MD_OFFSET_8 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_19_MD_OFFSET_8.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_19_MD_OFFSET_8 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_19_MD_OFFSET_8(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_19_MD_OFFSET_8) >> BP_IPU_DC_MAP_CONF_19_MD_OFFSET_8)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_19_MD_OFFSET_8.
|
|
#define BF_IPU_DC_MAP_CONF_19_MD_OFFSET_8(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_19_MD_OFFSET_8) & BM_IPU_DC_MAP_CONF_19_MD_OFFSET_8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_8 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_19_MD_OFFSET_8(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, (HW_IPU_DC_MAP_CONF_19_RD(x) & ~BM_IPU_DC_MAP_CONF_19_MD_OFFSET_8) | BF_IPU_DC_MAP_CONF_19_MD_OFFSET_8(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_19, field MD_MASK_9[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #9 This field defines the mask value #9 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_19_MD_MASK_9 (16) //!< Bit position for IPU_DC_MAP_CONF_19_MD_MASK_9.
|
|
#define BM_IPU_DC_MAP_CONF_19_MD_MASK_9 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_19_MD_MASK_9.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_19_MD_MASK_9 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_19_MD_MASK_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_19_MD_MASK_9) >> BP_IPU_DC_MAP_CONF_19_MD_MASK_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_19_MD_MASK_9.
|
|
#define BF_IPU_DC_MAP_CONF_19_MD_MASK_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_19_MD_MASK_9) & BM_IPU_DC_MAP_CONF_19_MD_MASK_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_9 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_19_MD_MASK_9(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, (HW_IPU_DC_MAP_CONF_19_RD(x) & ~BM_IPU_DC_MAP_CONF_19_MD_MASK_9) | BF_IPU_DC_MAP_CONF_19_MD_MASK_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_19, field MD_OFFSET_9[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #9 This field defines the offset parameter #9 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_19_MD_OFFSET_9 (24) //!< Bit position for IPU_DC_MAP_CONF_19_MD_OFFSET_9.
|
|
#define BM_IPU_DC_MAP_CONF_19_MD_OFFSET_9 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_19_MD_OFFSET_9.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_19_MD_OFFSET_9 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_19_MD_OFFSET_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_19_MD_OFFSET_9) >> BP_IPU_DC_MAP_CONF_19_MD_OFFSET_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_19_MD_OFFSET_9.
|
|
#define BF_IPU_DC_MAP_CONF_19_MD_OFFSET_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_19_MD_OFFSET_9) & BM_IPU_DC_MAP_CONF_19_MD_OFFSET_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_9 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_19_MD_OFFSET_9(x, v) (HW_IPU_DC_MAP_CONF_19_WR(x, (HW_IPU_DC_MAP_CONF_19_RD(x) & ~BM_IPU_DC_MAP_CONF_19_MD_OFFSET_9) | BF_IPU_DC_MAP_CONF_19_MD_OFFSET_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_20 - DC Mapping Configuration Register 20
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_20 - DC Mapping Configuration Register 20 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_20
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_20_bitfields
|
|
{
|
|
unsigned MD_MASK_10 : 8; //!< [7:0] Mapping unit's mask value #10
|
|
unsigned MD_OFFSET_10 : 5; //!< [12:8] Mapping unit's offset parameter #10
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_11 : 8; //!< [23:16] Mapping unit's mask value #11
|
|
unsigned MD_OFFSET_11 : 5; //!< [28:24] Mapping unit's offset parameter #11
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_20_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_20 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_20_ADDR(x) (REGS_IPU_BASE(x) + 0x58158)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_20(x) (*(volatile hw_ipu_dc_map_conf_20_t *) HW_IPU_DC_MAP_CONF_20_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_20_RD(x) (HW_IPU_DC_MAP_CONF_20(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_20_WR(x, v) (HW_IPU_DC_MAP_CONF_20(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_20_SET(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, HW_IPU_DC_MAP_CONF_20_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_20_CLR(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, HW_IPU_DC_MAP_CONF_20_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_20_TOG(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, HW_IPU_DC_MAP_CONF_20_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_20 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_20, field MD_MASK_10[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #10 This field defines the mask value #10 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_20_MD_MASK_10 (0) //!< Bit position for IPU_DC_MAP_CONF_20_MD_MASK_10.
|
|
#define BM_IPU_DC_MAP_CONF_20_MD_MASK_10 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_20_MD_MASK_10.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_20_MD_MASK_10 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_20_MD_MASK_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_20_MD_MASK_10) >> BP_IPU_DC_MAP_CONF_20_MD_MASK_10)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_20_MD_MASK_10.
|
|
#define BF_IPU_DC_MAP_CONF_20_MD_MASK_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_20_MD_MASK_10) & BM_IPU_DC_MAP_CONF_20_MD_MASK_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_10 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_20_MD_MASK_10(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, (HW_IPU_DC_MAP_CONF_20_RD(x) & ~BM_IPU_DC_MAP_CONF_20_MD_MASK_10) | BF_IPU_DC_MAP_CONF_20_MD_MASK_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_20, field MD_OFFSET_10[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #10 This field defines the offset parameter #10 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_20_MD_OFFSET_10 (8) //!< Bit position for IPU_DC_MAP_CONF_20_MD_OFFSET_10.
|
|
#define BM_IPU_DC_MAP_CONF_20_MD_OFFSET_10 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_20_MD_OFFSET_10.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_20_MD_OFFSET_10 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_20_MD_OFFSET_10(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_20_MD_OFFSET_10) >> BP_IPU_DC_MAP_CONF_20_MD_OFFSET_10)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_20_MD_OFFSET_10.
|
|
#define BF_IPU_DC_MAP_CONF_20_MD_OFFSET_10(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_20_MD_OFFSET_10) & BM_IPU_DC_MAP_CONF_20_MD_OFFSET_10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_10 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_20_MD_OFFSET_10(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, (HW_IPU_DC_MAP_CONF_20_RD(x) & ~BM_IPU_DC_MAP_CONF_20_MD_OFFSET_10) | BF_IPU_DC_MAP_CONF_20_MD_OFFSET_10(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_20, field MD_MASK_11[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #11 This field defines the mask value #11 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_20_MD_MASK_11 (16) //!< Bit position for IPU_DC_MAP_CONF_20_MD_MASK_11.
|
|
#define BM_IPU_DC_MAP_CONF_20_MD_MASK_11 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_20_MD_MASK_11.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_20_MD_MASK_11 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_20_MD_MASK_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_20_MD_MASK_11) >> BP_IPU_DC_MAP_CONF_20_MD_MASK_11)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_20_MD_MASK_11.
|
|
#define BF_IPU_DC_MAP_CONF_20_MD_MASK_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_20_MD_MASK_11) & BM_IPU_DC_MAP_CONF_20_MD_MASK_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_11 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_20_MD_MASK_11(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, (HW_IPU_DC_MAP_CONF_20_RD(x) & ~BM_IPU_DC_MAP_CONF_20_MD_MASK_11) | BF_IPU_DC_MAP_CONF_20_MD_MASK_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_20, field MD_OFFSET_11[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #11 This field defines the offset parameter #11 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_20_MD_OFFSET_11 (24) //!< Bit position for IPU_DC_MAP_CONF_20_MD_OFFSET_11.
|
|
#define BM_IPU_DC_MAP_CONF_20_MD_OFFSET_11 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_20_MD_OFFSET_11.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_20_MD_OFFSET_11 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_20_MD_OFFSET_11(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_20_MD_OFFSET_11) >> BP_IPU_DC_MAP_CONF_20_MD_OFFSET_11)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_20_MD_OFFSET_11.
|
|
#define BF_IPU_DC_MAP_CONF_20_MD_OFFSET_11(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_20_MD_OFFSET_11) & BM_IPU_DC_MAP_CONF_20_MD_OFFSET_11)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_11 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_20_MD_OFFSET_11(x, v) (HW_IPU_DC_MAP_CONF_20_WR(x, (HW_IPU_DC_MAP_CONF_20_RD(x) & ~BM_IPU_DC_MAP_CONF_20_MD_OFFSET_11) | BF_IPU_DC_MAP_CONF_20_MD_OFFSET_11(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_21 - DC Mapping Configuration Register 21
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_21 - DC Mapping Configuration Register 21 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_21
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_21_bitfields
|
|
{
|
|
unsigned MD_MASK_12 : 8; //!< [7:0] Mapping unit's mask value #12
|
|
unsigned MD_OFFSET_12 : 5; //!< [12:8] Mapping unit's offset parameter #12
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_13 : 8; //!< [23:16] Mapping unit's mask value #13
|
|
unsigned MD_OFFSET_13 : 5; //!< [28:24] Mapping unit's offset parameter #13
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_21_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_21 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_21_ADDR(x) (REGS_IPU_BASE(x) + 0x5815c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_21(x) (*(volatile hw_ipu_dc_map_conf_21_t *) HW_IPU_DC_MAP_CONF_21_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_21_RD(x) (HW_IPU_DC_MAP_CONF_21(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_21_WR(x, v) (HW_IPU_DC_MAP_CONF_21(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_21_SET(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, HW_IPU_DC_MAP_CONF_21_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_21_CLR(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, HW_IPU_DC_MAP_CONF_21_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_21_TOG(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, HW_IPU_DC_MAP_CONF_21_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_21 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_21, field MD_MASK_12[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #12 This field defines the mask value #12 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_21_MD_MASK_12 (0) //!< Bit position for IPU_DC_MAP_CONF_21_MD_MASK_12.
|
|
#define BM_IPU_DC_MAP_CONF_21_MD_MASK_12 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_21_MD_MASK_12.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_21_MD_MASK_12 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_21_MD_MASK_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_21_MD_MASK_12) >> BP_IPU_DC_MAP_CONF_21_MD_MASK_12)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_21_MD_MASK_12.
|
|
#define BF_IPU_DC_MAP_CONF_21_MD_MASK_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_21_MD_MASK_12) & BM_IPU_DC_MAP_CONF_21_MD_MASK_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_12 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_21_MD_MASK_12(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, (HW_IPU_DC_MAP_CONF_21_RD(x) & ~BM_IPU_DC_MAP_CONF_21_MD_MASK_12) | BF_IPU_DC_MAP_CONF_21_MD_MASK_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_21, field MD_OFFSET_12[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #12 This field defines the offset parameter #12 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_21_MD_OFFSET_12 (8) //!< Bit position for IPU_DC_MAP_CONF_21_MD_OFFSET_12.
|
|
#define BM_IPU_DC_MAP_CONF_21_MD_OFFSET_12 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_21_MD_OFFSET_12.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_21_MD_OFFSET_12 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_21_MD_OFFSET_12(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_21_MD_OFFSET_12) >> BP_IPU_DC_MAP_CONF_21_MD_OFFSET_12)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_21_MD_OFFSET_12.
|
|
#define BF_IPU_DC_MAP_CONF_21_MD_OFFSET_12(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_21_MD_OFFSET_12) & BM_IPU_DC_MAP_CONF_21_MD_OFFSET_12)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_12 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_21_MD_OFFSET_12(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, (HW_IPU_DC_MAP_CONF_21_RD(x) & ~BM_IPU_DC_MAP_CONF_21_MD_OFFSET_12) | BF_IPU_DC_MAP_CONF_21_MD_OFFSET_12(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_21, field MD_MASK_13[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #13 This field defines the mask value #13 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_21_MD_MASK_13 (16) //!< Bit position for IPU_DC_MAP_CONF_21_MD_MASK_13.
|
|
#define BM_IPU_DC_MAP_CONF_21_MD_MASK_13 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_21_MD_MASK_13.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_21_MD_MASK_13 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_21_MD_MASK_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_21_MD_MASK_13) >> BP_IPU_DC_MAP_CONF_21_MD_MASK_13)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_21_MD_MASK_13.
|
|
#define BF_IPU_DC_MAP_CONF_21_MD_MASK_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_21_MD_MASK_13) & BM_IPU_DC_MAP_CONF_21_MD_MASK_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_13 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_21_MD_MASK_13(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, (HW_IPU_DC_MAP_CONF_21_RD(x) & ~BM_IPU_DC_MAP_CONF_21_MD_MASK_13) | BF_IPU_DC_MAP_CONF_21_MD_MASK_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_21, field MD_OFFSET_13[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #13 This field defines the offset parameter #13 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_21_MD_OFFSET_13 (24) //!< Bit position for IPU_DC_MAP_CONF_21_MD_OFFSET_13.
|
|
#define BM_IPU_DC_MAP_CONF_21_MD_OFFSET_13 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_21_MD_OFFSET_13.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_21_MD_OFFSET_13 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_21_MD_OFFSET_13(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_21_MD_OFFSET_13) >> BP_IPU_DC_MAP_CONF_21_MD_OFFSET_13)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_21_MD_OFFSET_13.
|
|
#define BF_IPU_DC_MAP_CONF_21_MD_OFFSET_13(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_21_MD_OFFSET_13) & BM_IPU_DC_MAP_CONF_21_MD_OFFSET_13)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_13 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_21_MD_OFFSET_13(x, v) (HW_IPU_DC_MAP_CONF_21_WR(x, (HW_IPU_DC_MAP_CONF_21_RD(x) & ~BM_IPU_DC_MAP_CONF_21_MD_OFFSET_13) | BF_IPU_DC_MAP_CONF_21_MD_OFFSET_13(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_22 - DC Mapping Configuration Register 22
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_22 - DC Mapping Configuration Register 22 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_22
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_22_bitfields
|
|
{
|
|
unsigned MD_MASK_14 : 8; //!< [7:0] Mapping unit's mask value #14
|
|
unsigned MD_OFFSET_14 : 5; //!< [12:8] Mapping unit's offset parameter #14
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_15 : 8; //!< [23:16] Mapping unit's mask value #15
|
|
unsigned MD_OFFSET_15 : 5; //!< [28:24] Mapping unit's offset parameter #15
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_22_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_22 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_22_ADDR(x) (REGS_IPU_BASE(x) + 0x58160)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_22(x) (*(volatile hw_ipu_dc_map_conf_22_t *) HW_IPU_DC_MAP_CONF_22_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_22_RD(x) (HW_IPU_DC_MAP_CONF_22(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_22_WR(x, v) (HW_IPU_DC_MAP_CONF_22(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_22_SET(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, HW_IPU_DC_MAP_CONF_22_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_22_CLR(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, HW_IPU_DC_MAP_CONF_22_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_22_TOG(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, HW_IPU_DC_MAP_CONF_22_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_22 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_22, field MD_MASK_14[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #14 This field defines the mask value #14 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_22_MD_MASK_14 (0) //!< Bit position for IPU_DC_MAP_CONF_22_MD_MASK_14.
|
|
#define BM_IPU_DC_MAP_CONF_22_MD_MASK_14 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_22_MD_MASK_14.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_22_MD_MASK_14 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_22_MD_MASK_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_22_MD_MASK_14) >> BP_IPU_DC_MAP_CONF_22_MD_MASK_14)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_22_MD_MASK_14.
|
|
#define BF_IPU_DC_MAP_CONF_22_MD_MASK_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_22_MD_MASK_14) & BM_IPU_DC_MAP_CONF_22_MD_MASK_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_14 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_22_MD_MASK_14(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, (HW_IPU_DC_MAP_CONF_22_RD(x) & ~BM_IPU_DC_MAP_CONF_22_MD_MASK_14) | BF_IPU_DC_MAP_CONF_22_MD_MASK_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_22, field MD_OFFSET_14[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #14 This field defines the offset parameter #14 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_22_MD_OFFSET_14 (8) //!< Bit position for IPU_DC_MAP_CONF_22_MD_OFFSET_14.
|
|
#define BM_IPU_DC_MAP_CONF_22_MD_OFFSET_14 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_22_MD_OFFSET_14.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_22_MD_OFFSET_14 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_22_MD_OFFSET_14(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_22_MD_OFFSET_14) >> BP_IPU_DC_MAP_CONF_22_MD_OFFSET_14)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_22_MD_OFFSET_14.
|
|
#define BF_IPU_DC_MAP_CONF_22_MD_OFFSET_14(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_22_MD_OFFSET_14) & BM_IPU_DC_MAP_CONF_22_MD_OFFSET_14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_14 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_22_MD_OFFSET_14(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, (HW_IPU_DC_MAP_CONF_22_RD(x) & ~BM_IPU_DC_MAP_CONF_22_MD_OFFSET_14) | BF_IPU_DC_MAP_CONF_22_MD_OFFSET_14(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_22, field MD_MASK_15[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #15 This field defines the mask value #15 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_22_MD_MASK_15 (16) //!< Bit position for IPU_DC_MAP_CONF_22_MD_MASK_15.
|
|
#define BM_IPU_DC_MAP_CONF_22_MD_MASK_15 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_22_MD_MASK_15.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_22_MD_MASK_15 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_22_MD_MASK_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_22_MD_MASK_15) >> BP_IPU_DC_MAP_CONF_22_MD_MASK_15)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_22_MD_MASK_15.
|
|
#define BF_IPU_DC_MAP_CONF_22_MD_MASK_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_22_MD_MASK_15) & BM_IPU_DC_MAP_CONF_22_MD_MASK_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_15 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_22_MD_MASK_15(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, (HW_IPU_DC_MAP_CONF_22_RD(x) & ~BM_IPU_DC_MAP_CONF_22_MD_MASK_15) | BF_IPU_DC_MAP_CONF_22_MD_MASK_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_22, field MD_OFFSET_15[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #15 This field defines the offset parameter #15 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_22_MD_OFFSET_15 (24) //!< Bit position for IPU_DC_MAP_CONF_22_MD_OFFSET_15.
|
|
#define BM_IPU_DC_MAP_CONF_22_MD_OFFSET_15 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_22_MD_OFFSET_15.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_22_MD_OFFSET_15 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_22_MD_OFFSET_15(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_22_MD_OFFSET_15) >> BP_IPU_DC_MAP_CONF_22_MD_OFFSET_15)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_22_MD_OFFSET_15.
|
|
#define BF_IPU_DC_MAP_CONF_22_MD_OFFSET_15(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_22_MD_OFFSET_15) & BM_IPU_DC_MAP_CONF_22_MD_OFFSET_15)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_15 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_22_MD_OFFSET_15(x, v) (HW_IPU_DC_MAP_CONF_22_WR(x, (HW_IPU_DC_MAP_CONF_22_RD(x) & ~BM_IPU_DC_MAP_CONF_22_MD_OFFSET_15) | BF_IPU_DC_MAP_CONF_22_MD_OFFSET_15(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_23 - DC Mapping Configuration Register 23
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_23 - DC Mapping Configuration Register 23 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_23
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_23_bitfields
|
|
{
|
|
unsigned MD_MASK_16 : 8; //!< [7:0] Mapping unit's mask value #16
|
|
unsigned MD_OFFSET_16 : 5; //!< [12:8] Mapping unit's offset parameter #16
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_17 : 8; //!< [23:16] Mapping unit's mask value #17
|
|
unsigned MD_OFFSET_17 : 5; //!< [28:24] Mapping unit's offset parameter #17
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_23_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_23 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_23_ADDR(x) (REGS_IPU_BASE(x) + 0x58164)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_23(x) (*(volatile hw_ipu_dc_map_conf_23_t *) HW_IPU_DC_MAP_CONF_23_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_23_RD(x) (HW_IPU_DC_MAP_CONF_23(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_23_WR(x, v) (HW_IPU_DC_MAP_CONF_23(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_23_SET(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, HW_IPU_DC_MAP_CONF_23_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_23_CLR(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, HW_IPU_DC_MAP_CONF_23_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_23_TOG(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, HW_IPU_DC_MAP_CONF_23_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_23 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_23, field MD_MASK_16[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #16 This field defines the mask value #16 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_23_MD_MASK_16 (0) //!< Bit position for IPU_DC_MAP_CONF_23_MD_MASK_16.
|
|
#define BM_IPU_DC_MAP_CONF_23_MD_MASK_16 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_23_MD_MASK_16.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_23_MD_MASK_16 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_23_MD_MASK_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_23_MD_MASK_16) >> BP_IPU_DC_MAP_CONF_23_MD_MASK_16)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_23_MD_MASK_16.
|
|
#define BF_IPU_DC_MAP_CONF_23_MD_MASK_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_23_MD_MASK_16) & BM_IPU_DC_MAP_CONF_23_MD_MASK_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_16 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_23_MD_MASK_16(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, (HW_IPU_DC_MAP_CONF_23_RD(x) & ~BM_IPU_DC_MAP_CONF_23_MD_MASK_16) | BF_IPU_DC_MAP_CONF_23_MD_MASK_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_23, field MD_OFFSET_16[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #16 This field defines the offset parameter #16 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_23_MD_OFFSET_16 (8) //!< Bit position for IPU_DC_MAP_CONF_23_MD_OFFSET_16.
|
|
#define BM_IPU_DC_MAP_CONF_23_MD_OFFSET_16 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_23_MD_OFFSET_16.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_23_MD_OFFSET_16 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_23_MD_OFFSET_16(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_23_MD_OFFSET_16) >> BP_IPU_DC_MAP_CONF_23_MD_OFFSET_16)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_23_MD_OFFSET_16.
|
|
#define BF_IPU_DC_MAP_CONF_23_MD_OFFSET_16(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_23_MD_OFFSET_16) & BM_IPU_DC_MAP_CONF_23_MD_OFFSET_16)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_16 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_23_MD_OFFSET_16(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, (HW_IPU_DC_MAP_CONF_23_RD(x) & ~BM_IPU_DC_MAP_CONF_23_MD_OFFSET_16) | BF_IPU_DC_MAP_CONF_23_MD_OFFSET_16(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_23, field MD_MASK_17[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #17 This field defines the mask value #17 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_23_MD_MASK_17 (16) //!< Bit position for IPU_DC_MAP_CONF_23_MD_MASK_17.
|
|
#define BM_IPU_DC_MAP_CONF_23_MD_MASK_17 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_23_MD_MASK_17.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_23_MD_MASK_17 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_23_MD_MASK_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_23_MD_MASK_17) >> BP_IPU_DC_MAP_CONF_23_MD_MASK_17)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_23_MD_MASK_17.
|
|
#define BF_IPU_DC_MAP_CONF_23_MD_MASK_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_23_MD_MASK_17) & BM_IPU_DC_MAP_CONF_23_MD_MASK_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_17 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_23_MD_MASK_17(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, (HW_IPU_DC_MAP_CONF_23_RD(x) & ~BM_IPU_DC_MAP_CONF_23_MD_MASK_17) | BF_IPU_DC_MAP_CONF_23_MD_MASK_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_23, field MD_OFFSET_17[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #17 This field defines the offset parameter #17 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_23_MD_OFFSET_17 (24) //!< Bit position for IPU_DC_MAP_CONF_23_MD_OFFSET_17.
|
|
#define BM_IPU_DC_MAP_CONF_23_MD_OFFSET_17 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_23_MD_OFFSET_17.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_23_MD_OFFSET_17 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_23_MD_OFFSET_17(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_23_MD_OFFSET_17) >> BP_IPU_DC_MAP_CONF_23_MD_OFFSET_17)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_23_MD_OFFSET_17.
|
|
#define BF_IPU_DC_MAP_CONF_23_MD_OFFSET_17(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_23_MD_OFFSET_17) & BM_IPU_DC_MAP_CONF_23_MD_OFFSET_17)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_17 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_23_MD_OFFSET_17(x, v) (HW_IPU_DC_MAP_CONF_23_WR(x, (HW_IPU_DC_MAP_CONF_23_RD(x) & ~BM_IPU_DC_MAP_CONF_23_MD_OFFSET_17) | BF_IPU_DC_MAP_CONF_23_MD_OFFSET_17(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_24 - DC Mapping Configuration Register 24
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_24 - DC Mapping Configuration Register 24 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_24
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_24_bitfields
|
|
{
|
|
unsigned MD_MASK_18 : 8; //!< [7:0] Mapping unit's mask value #18
|
|
unsigned MD_OFFSET_18 : 5; //!< [12:8] Mapping unit's offset parameter #18
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_19 : 8; //!< [23:16] Mapping unit's mask value #19
|
|
unsigned MD_OFFSET_19 : 5; //!< [28:24] Mapping unit's offset parameter #19
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_24_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_24 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_24_ADDR(x) (REGS_IPU_BASE(x) + 0x58168)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_24(x) (*(volatile hw_ipu_dc_map_conf_24_t *) HW_IPU_DC_MAP_CONF_24_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_24_RD(x) (HW_IPU_DC_MAP_CONF_24(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_24_WR(x, v) (HW_IPU_DC_MAP_CONF_24(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_24_SET(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, HW_IPU_DC_MAP_CONF_24_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_24_CLR(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, HW_IPU_DC_MAP_CONF_24_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_24_TOG(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, HW_IPU_DC_MAP_CONF_24_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_24 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_24, field MD_MASK_18[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #18 This field defines the mask value #18 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_24_MD_MASK_18 (0) //!< Bit position for IPU_DC_MAP_CONF_24_MD_MASK_18.
|
|
#define BM_IPU_DC_MAP_CONF_24_MD_MASK_18 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_24_MD_MASK_18.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_24_MD_MASK_18 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_24_MD_MASK_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_24_MD_MASK_18) >> BP_IPU_DC_MAP_CONF_24_MD_MASK_18)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_24_MD_MASK_18.
|
|
#define BF_IPU_DC_MAP_CONF_24_MD_MASK_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_24_MD_MASK_18) & BM_IPU_DC_MAP_CONF_24_MD_MASK_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_18 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_24_MD_MASK_18(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, (HW_IPU_DC_MAP_CONF_24_RD(x) & ~BM_IPU_DC_MAP_CONF_24_MD_MASK_18) | BF_IPU_DC_MAP_CONF_24_MD_MASK_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_24, field MD_OFFSET_18[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #18 This field defines the offset parameter #18 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_24_MD_OFFSET_18 (8) //!< Bit position for IPU_DC_MAP_CONF_24_MD_OFFSET_18.
|
|
#define BM_IPU_DC_MAP_CONF_24_MD_OFFSET_18 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_24_MD_OFFSET_18.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_24_MD_OFFSET_18 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_24_MD_OFFSET_18(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_24_MD_OFFSET_18) >> BP_IPU_DC_MAP_CONF_24_MD_OFFSET_18)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_24_MD_OFFSET_18.
|
|
#define BF_IPU_DC_MAP_CONF_24_MD_OFFSET_18(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_24_MD_OFFSET_18) & BM_IPU_DC_MAP_CONF_24_MD_OFFSET_18)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_18 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_24_MD_OFFSET_18(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, (HW_IPU_DC_MAP_CONF_24_RD(x) & ~BM_IPU_DC_MAP_CONF_24_MD_OFFSET_18) | BF_IPU_DC_MAP_CONF_24_MD_OFFSET_18(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_24, field MD_MASK_19[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #19 This field defines the mask value #19 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_24_MD_MASK_19 (16) //!< Bit position for IPU_DC_MAP_CONF_24_MD_MASK_19.
|
|
#define BM_IPU_DC_MAP_CONF_24_MD_MASK_19 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_24_MD_MASK_19.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_24_MD_MASK_19 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_24_MD_MASK_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_24_MD_MASK_19) >> BP_IPU_DC_MAP_CONF_24_MD_MASK_19)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_24_MD_MASK_19.
|
|
#define BF_IPU_DC_MAP_CONF_24_MD_MASK_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_24_MD_MASK_19) & BM_IPU_DC_MAP_CONF_24_MD_MASK_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_19 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_24_MD_MASK_19(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, (HW_IPU_DC_MAP_CONF_24_RD(x) & ~BM_IPU_DC_MAP_CONF_24_MD_MASK_19) | BF_IPU_DC_MAP_CONF_24_MD_MASK_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_24, field MD_OFFSET_19[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #19 This field defines the offset parameter #19 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_24_MD_OFFSET_19 (24) //!< Bit position for IPU_DC_MAP_CONF_24_MD_OFFSET_19.
|
|
#define BM_IPU_DC_MAP_CONF_24_MD_OFFSET_19 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_24_MD_OFFSET_19.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_24_MD_OFFSET_19 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_24_MD_OFFSET_19(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_24_MD_OFFSET_19) >> BP_IPU_DC_MAP_CONF_24_MD_OFFSET_19)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_24_MD_OFFSET_19.
|
|
#define BF_IPU_DC_MAP_CONF_24_MD_OFFSET_19(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_24_MD_OFFSET_19) & BM_IPU_DC_MAP_CONF_24_MD_OFFSET_19)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_19 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_24_MD_OFFSET_19(x, v) (HW_IPU_DC_MAP_CONF_24_WR(x, (HW_IPU_DC_MAP_CONF_24_RD(x) & ~BM_IPU_DC_MAP_CONF_24_MD_OFFSET_19) | BF_IPU_DC_MAP_CONF_24_MD_OFFSET_19(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_25 - DC Mapping Configuration Register 25
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_25 - DC Mapping Configuration Register 25 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_25
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_25_bitfields
|
|
{
|
|
unsigned MD_MASK_20 : 8; //!< [7:0] Mapping unit's mask value #20
|
|
unsigned MD_OFFSET_20 : 5; //!< [12:8] Mapping unit's offset parameter #20
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_21 : 8; //!< [23:16] Mapping unit's mask value #21
|
|
unsigned MD_OFFSET_21 : 5; //!< [28:24] Mapping unit's offset parameter #21
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_25_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_25 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_25_ADDR(x) (REGS_IPU_BASE(x) + 0x5816c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_25(x) (*(volatile hw_ipu_dc_map_conf_25_t *) HW_IPU_DC_MAP_CONF_25_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_25_RD(x) (HW_IPU_DC_MAP_CONF_25(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_25_WR(x, v) (HW_IPU_DC_MAP_CONF_25(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_25_SET(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, HW_IPU_DC_MAP_CONF_25_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_25_CLR(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, HW_IPU_DC_MAP_CONF_25_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_25_TOG(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, HW_IPU_DC_MAP_CONF_25_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_25 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_25, field MD_MASK_20[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #20 This field defines the mask value #20 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_25_MD_MASK_20 (0) //!< Bit position for IPU_DC_MAP_CONF_25_MD_MASK_20.
|
|
#define BM_IPU_DC_MAP_CONF_25_MD_MASK_20 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_25_MD_MASK_20.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_25_MD_MASK_20 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_25_MD_MASK_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_25_MD_MASK_20) >> BP_IPU_DC_MAP_CONF_25_MD_MASK_20)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_25_MD_MASK_20.
|
|
#define BF_IPU_DC_MAP_CONF_25_MD_MASK_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_25_MD_MASK_20) & BM_IPU_DC_MAP_CONF_25_MD_MASK_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_20 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_25_MD_MASK_20(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, (HW_IPU_DC_MAP_CONF_25_RD(x) & ~BM_IPU_DC_MAP_CONF_25_MD_MASK_20) | BF_IPU_DC_MAP_CONF_25_MD_MASK_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_25, field MD_OFFSET_20[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #20 This field defines the offset parameter #20 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_25_MD_OFFSET_20 (8) //!< Bit position for IPU_DC_MAP_CONF_25_MD_OFFSET_20.
|
|
#define BM_IPU_DC_MAP_CONF_25_MD_OFFSET_20 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_25_MD_OFFSET_20.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_25_MD_OFFSET_20 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_25_MD_OFFSET_20(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_25_MD_OFFSET_20) >> BP_IPU_DC_MAP_CONF_25_MD_OFFSET_20)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_25_MD_OFFSET_20.
|
|
#define BF_IPU_DC_MAP_CONF_25_MD_OFFSET_20(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_25_MD_OFFSET_20) & BM_IPU_DC_MAP_CONF_25_MD_OFFSET_20)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_20 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_25_MD_OFFSET_20(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, (HW_IPU_DC_MAP_CONF_25_RD(x) & ~BM_IPU_DC_MAP_CONF_25_MD_OFFSET_20) | BF_IPU_DC_MAP_CONF_25_MD_OFFSET_20(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_25, field MD_MASK_21[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #21 This field defines the mask value #21 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_25_MD_MASK_21 (16) //!< Bit position for IPU_DC_MAP_CONF_25_MD_MASK_21.
|
|
#define BM_IPU_DC_MAP_CONF_25_MD_MASK_21 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_25_MD_MASK_21.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_25_MD_MASK_21 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_25_MD_MASK_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_25_MD_MASK_21) >> BP_IPU_DC_MAP_CONF_25_MD_MASK_21)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_25_MD_MASK_21.
|
|
#define BF_IPU_DC_MAP_CONF_25_MD_MASK_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_25_MD_MASK_21) & BM_IPU_DC_MAP_CONF_25_MD_MASK_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_21 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_25_MD_MASK_21(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, (HW_IPU_DC_MAP_CONF_25_RD(x) & ~BM_IPU_DC_MAP_CONF_25_MD_MASK_21) | BF_IPU_DC_MAP_CONF_25_MD_MASK_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_25, field MD_OFFSET_21[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #21 This field defines the offset parameter #21 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_25_MD_OFFSET_21 (24) //!< Bit position for IPU_DC_MAP_CONF_25_MD_OFFSET_21.
|
|
#define BM_IPU_DC_MAP_CONF_25_MD_OFFSET_21 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_25_MD_OFFSET_21.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_25_MD_OFFSET_21 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_25_MD_OFFSET_21(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_25_MD_OFFSET_21) >> BP_IPU_DC_MAP_CONF_25_MD_OFFSET_21)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_25_MD_OFFSET_21.
|
|
#define BF_IPU_DC_MAP_CONF_25_MD_OFFSET_21(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_25_MD_OFFSET_21) & BM_IPU_DC_MAP_CONF_25_MD_OFFSET_21)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_21 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_25_MD_OFFSET_21(x, v) (HW_IPU_DC_MAP_CONF_25_WR(x, (HW_IPU_DC_MAP_CONF_25_RD(x) & ~BM_IPU_DC_MAP_CONF_25_MD_OFFSET_21) | BF_IPU_DC_MAP_CONF_25_MD_OFFSET_21(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_MAP_CONF_26 - DC Mapping Configuration Register 26
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_MAP_CONF_26 - DC Mapping Configuration Register 26 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_map_conf_26
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_map_conf_26_bitfields
|
|
{
|
|
unsigned MD_MASK_22 : 8; //!< [7:0] Mapping unit's mask value #22
|
|
unsigned MD_OFFSET_22 : 5; //!< [12:8] Mapping unit's offset parameter #22
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned MD_MASK_23 : 8; //!< [23:16] Mapping unit's mask value #23
|
|
unsigned MD_OFFSET_23 : 5; //!< [28:24] Mapping unit's offset parameter #23
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_map_conf_26_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_MAP_CONF_26 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_MAP_CONF_26_ADDR(x) (REGS_IPU_BASE(x) + 0x58170)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_MAP_CONF_26(x) (*(volatile hw_ipu_dc_map_conf_26_t *) HW_IPU_DC_MAP_CONF_26_ADDR(x))
|
|
#define HW_IPU_DC_MAP_CONF_26_RD(x) (HW_IPU_DC_MAP_CONF_26(x).U)
|
|
#define HW_IPU_DC_MAP_CONF_26_WR(x, v) (HW_IPU_DC_MAP_CONF_26(x).U = (v))
|
|
#define HW_IPU_DC_MAP_CONF_26_SET(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, HW_IPU_DC_MAP_CONF_26_RD(x) | (v)))
|
|
#define HW_IPU_DC_MAP_CONF_26_CLR(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, HW_IPU_DC_MAP_CONF_26_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_MAP_CONF_26_TOG(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, HW_IPU_DC_MAP_CONF_26_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_MAP_CONF_26 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_26, field MD_MASK_22[7:0] (RW)
|
|
*
|
|
* Mapping unit's mask value #22 This field defines the mask value #22 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_26_MD_MASK_22 (0) //!< Bit position for IPU_DC_MAP_CONF_26_MD_MASK_22.
|
|
#define BM_IPU_DC_MAP_CONF_26_MD_MASK_22 (0x000000ff) //!< Bit mask for IPU_DC_MAP_CONF_26_MD_MASK_22.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_26_MD_MASK_22 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_26_MD_MASK_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_26_MD_MASK_22) >> BP_IPU_DC_MAP_CONF_26_MD_MASK_22)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_26_MD_MASK_22.
|
|
#define BF_IPU_DC_MAP_CONF_26_MD_MASK_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_26_MD_MASK_22) & BM_IPU_DC_MAP_CONF_26_MD_MASK_22)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_22 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_26_MD_MASK_22(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, (HW_IPU_DC_MAP_CONF_26_RD(x) & ~BM_IPU_DC_MAP_CONF_26_MD_MASK_22) | BF_IPU_DC_MAP_CONF_26_MD_MASK_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_26, field MD_OFFSET_22[12:8] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #22 This field defines the offset parameter #22 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_26_MD_OFFSET_22 (8) //!< Bit position for IPU_DC_MAP_CONF_26_MD_OFFSET_22.
|
|
#define BM_IPU_DC_MAP_CONF_26_MD_OFFSET_22 (0x00001f00) //!< Bit mask for IPU_DC_MAP_CONF_26_MD_OFFSET_22.
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|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_26_MD_OFFSET_22 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_26_MD_OFFSET_22(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_26_MD_OFFSET_22) >> BP_IPU_DC_MAP_CONF_26_MD_OFFSET_22)
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|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_26_MD_OFFSET_22.
|
|
#define BF_IPU_DC_MAP_CONF_26_MD_OFFSET_22(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_26_MD_OFFSET_22) & BM_IPU_DC_MAP_CONF_26_MD_OFFSET_22)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_22 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_26_MD_OFFSET_22(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, (HW_IPU_DC_MAP_CONF_26_RD(x) & ~BM_IPU_DC_MAP_CONF_26_MD_OFFSET_22) | BF_IPU_DC_MAP_CONF_26_MD_OFFSET_22(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_26, field MD_MASK_23[23:16] (RW)
|
|
*
|
|
* Mapping unit's mask value #23 This field defines the mask value #23 within the 8bit word coming
|
|
* from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_26_MD_MASK_23 (16) //!< Bit position for IPU_DC_MAP_CONF_26_MD_MASK_23.
|
|
#define BM_IPU_DC_MAP_CONF_26_MD_MASK_23 (0x00ff0000) //!< Bit mask for IPU_DC_MAP_CONF_26_MD_MASK_23.
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|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_26_MD_MASK_23 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_26_MD_MASK_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_26_MD_MASK_23) >> BP_IPU_DC_MAP_CONF_26_MD_MASK_23)
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|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_26_MD_MASK_23.
|
|
#define BF_IPU_DC_MAP_CONF_26_MD_MASK_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_26_MD_MASK_23) & BM_IPU_DC_MAP_CONF_26_MD_MASK_23)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_MASK_23 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_26_MD_MASK_23(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, (HW_IPU_DC_MAP_CONF_26_RD(x) & ~BM_IPU_DC_MAP_CONF_26_MD_MASK_23) | BF_IPU_DC_MAP_CONF_26_MD_MASK_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_MAP_CONF_26, field MD_OFFSET_23[28:24] (RW)
|
|
*
|
|
* Mapping unit's offset parameter #23 This field defines the offset parameter #23 within the 24bit
|
|
* word coming from the DC.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_MAP_CONF_26_MD_OFFSET_23 (24) //!< Bit position for IPU_DC_MAP_CONF_26_MD_OFFSET_23.
|
|
#define BM_IPU_DC_MAP_CONF_26_MD_OFFSET_23 (0x1f000000) //!< Bit mask for IPU_DC_MAP_CONF_26_MD_OFFSET_23.
|
|
|
|
//! @brief Get value of IPU_DC_MAP_CONF_26_MD_OFFSET_23 from a register value.
|
|
#define BG_IPU_DC_MAP_CONF_26_MD_OFFSET_23(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_MAP_CONF_26_MD_OFFSET_23) >> BP_IPU_DC_MAP_CONF_26_MD_OFFSET_23)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_MAP_CONF_26_MD_OFFSET_23.
|
|
#define BF_IPU_DC_MAP_CONF_26_MD_OFFSET_23(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_MAP_CONF_26_MD_OFFSET_23) & BM_IPU_DC_MAP_CONF_26_MD_OFFSET_23)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MD_OFFSET_23 field to a new value.
|
|
#define BW_IPU_DC_MAP_CONF_26_MD_OFFSET_23(x, v) (HW_IPU_DC_MAP_CONF_26_WR(x, (HW_IPU_DC_MAP_CONF_26_RD(x) & ~BM_IPU_DC_MAP_CONF_26_MD_OFFSET_23) | BF_IPU_DC_MAP_CONF_26_MD_OFFSET_23(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE0_0 - DC User General Data Event 0 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE0_0 - DC User General Data Event 0 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde0_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde0_0_bitfields
|
|
{
|
|
unsigned ID_CODED_0 : 3; //!< [2:0] This field defines the number of DC channel number that user's general event #0 will be associated to.
|
|
unsigned COD_EV_PRIORITY_0 : 4; //!< [6:3] This field defines the priority of the user general event #0
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved
|
|
unsigned COD_EV_START_0 : 8; //!< [15:8] This field holds a pointer in the microcode holding the routine to be performed following the user general event #0.
|
|
unsigned COD_ODD_START_0 : 8; //!< [23:16] This field holds a pointer in the microcode holding the routine to be performed following the user general event #0.
|
|
unsigned RESERVED1 : 1; //!< [24] Reserved.
|
|
unsigned ODD_EN_0 : 1; //!< [25] The user's general event #0 may be split into 2 internal signals.
|
|
unsigned AUTORESTART_0 : 1; //!< [26] User's general event #0 auto restart mode
|
|
unsigned NF_NL_0 : 2; //!< [28:27] the user may attach his general event #0 to New-line New-Frame and New-field events.
|
|
unsigned RESERVED2 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde0_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE0_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE0_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58174)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE0_0(x) (*(volatile hw_ipu_dc_ugde0_0_t *) HW_IPU_DC_UGDE0_0_ADDR(x))
|
|
#define HW_IPU_DC_UGDE0_0_RD(x) (HW_IPU_DC_UGDE0_0(x).U)
|
|
#define HW_IPU_DC_UGDE0_0_WR(x, v) (HW_IPU_DC_UGDE0_0(x).U = (v))
|
|
#define HW_IPU_DC_UGDE0_0_SET(x, v) (HW_IPU_DC_UGDE0_0_WR(x, HW_IPU_DC_UGDE0_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE0_0_CLR(x, v) (HW_IPU_DC_UGDE0_0_WR(x, HW_IPU_DC_UGDE0_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE0_0_TOG(x, v) (HW_IPU_DC_UGDE0_0_WR(x, HW_IPU_DC_UGDE0_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE0_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field ID_CODED_0[2:0] (RW)
|
|
*
|
|
* This field defines the number of DC channel number that user's general event #0 will be
|
|
* associated to.
|
|
*
|
|
* Values:
|
|
* - 000 - DC channel_0
|
|
* - 001 - DC channel_1
|
|
* - 010 - DC channel_2
|
|
* - 011 - DC channel_5 (DP_SYNC)
|
|
* - 100 - DC channel_6 (DP ASYNC)
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved.
|
|
* - 111 - Reserved.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_ID_CODED_0 (0) //!< Bit position for IPU_DC_UGDE0_0_ID_CODED_0.
|
|
#define BM_IPU_DC_UGDE0_0_ID_CODED_0 (0x00000007) //!< Bit mask for IPU_DC_UGDE0_0_ID_CODED_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_ID_CODED_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_ID_CODED_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_ID_CODED_0) >> BP_IPU_DC_UGDE0_0_ID_CODED_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_ID_CODED_0.
|
|
#define BF_IPU_DC_UGDE0_0_ID_CODED_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_ID_CODED_0) & BM_IPU_DC_UGDE0_0_ID_CODED_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ID_CODED_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_ID_CODED_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_ID_CODED_0) | BF_IPU_DC_UGDE0_0_ID_CODED_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field COD_EV_PRIORITY_0[6:3] (RW)
|
|
*
|
|
* This field defines the priority of the user general event #0 The priority between the events
|
|
* should be set to a unique value. i.e. two events must not have the same priority (except 0000 -
|
|
* disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0 (3) //!< Bit position for IPU_DC_UGDE0_0_COD_EV_PRIORITY_0.
|
|
#define BM_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0 (0x00000078) //!< Bit mask for IPU_DC_UGDE0_0_COD_EV_PRIORITY_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_COD_EV_PRIORITY_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0) >> BP_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_COD_EV_PRIORITY_0.
|
|
#define BF_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0) & BM_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_PRIORITY_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0) | BF_IPU_DC_UGDE0_0_COD_EV_PRIORITY_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field COD_EV_START_0[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #0. When ODD_MODE is enabled, only the even events will use this pointer When
|
|
* ODD_MODE is disabled, all the events will use this pointer
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_COD_EV_START_0 (8) //!< Bit position for IPU_DC_UGDE0_0_COD_EV_START_0.
|
|
#define BM_IPU_DC_UGDE0_0_COD_EV_START_0 (0x0000ff00) //!< Bit mask for IPU_DC_UGDE0_0_COD_EV_START_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_COD_EV_START_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_COD_EV_START_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_COD_EV_START_0) >> BP_IPU_DC_UGDE0_0_COD_EV_START_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_COD_EV_START_0.
|
|
#define BF_IPU_DC_UGDE0_0_COD_EV_START_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_COD_EV_START_0) & BM_IPU_DC_UGDE0_0_COD_EV_START_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_START_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_COD_EV_START_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_COD_EV_START_0) | BF_IPU_DC_UGDE0_0_COD_EV_START_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field COD_ODD_START_0[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #0. When ODD_MODE is enabled, only the odd events will use this pointer When
|
|
* ODD_MODE is disabled this field is ignored
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_COD_ODD_START_0 (16) //!< Bit position for IPU_DC_UGDE0_0_COD_ODD_START_0.
|
|
#define BM_IPU_DC_UGDE0_0_COD_ODD_START_0 (0x00ff0000) //!< Bit mask for IPU_DC_UGDE0_0_COD_ODD_START_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_COD_ODD_START_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_COD_ODD_START_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_COD_ODD_START_0) >> BP_IPU_DC_UGDE0_0_COD_ODD_START_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_COD_ODD_START_0.
|
|
#define BF_IPU_DC_UGDE0_0_COD_ODD_START_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_COD_ODD_START_0) & BM_IPU_DC_UGDE0_0_COD_ODD_START_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_ODD_START_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_COD_ODD_START_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_COD_ODD_START_0) | BF_IPU_DC_UGDE0_0_COD_ODD_START_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field ODD_EN_0[25] (RW)
|
|
*
|
|
* The user's general event #0 may be split into 2 internal signals. One one mode all the events are
|
|
* sent on one signal, on the second mode odd events are sent over one signal while even events are
|
|
* sent over the other signal (ODD_MODE)
|
|
*
|
|
* Values:
|
|
* - 0 - ODD_MODE is disabled
|
|
* - 1 - ODD_MODE is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_ODD_EN_0 (25) //!< Bit position for IPU_DC_UGDE0_0_ODD_EN_0.
|
|
#define BM_IPU_DC_UGDE0_0_ODD_EN_0 (0x02000000) //!< Bit mask for IPU_DC_UGDE0_0_ODD_EN_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_ODD_EN_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_ODD_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_ODD_EN_0) >> BP_IPU_DC_UGDE0_0_ODD_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_ODD_EN_0.
|
|
#define BF_IPU_DC_UGDE0_0_ODD_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_ODD_EN_0) & BM_IPU_DC_UGDE0_0_ODD_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ODD_EN_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_ODD_EN_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_ODD_EN_0) | BF_IPU_DC_UGDE0_0_ODD_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field AUTORESTART_0[26] (RW)
|
|
*
|
|
* User's general event #0 auto restart mode
|
|
*
|
|
* Values:
|
|
* - 0 - disable
|
|
* - 1 - User's general event #0's counter is automatically restarted.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_AUTORESTART_0 (26) //!< Bit position for IPU_DC_UGDE0_0_AUTORESTART_0.
|
|
#define BM_IPU_DC_UGDE0_0_AUTORESTART_0 (0x04000000) //!< Bit mask for IPU_DC_UGDE0_0_AUTORESTART_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_AUTORESTART_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_AUTORESTART_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_AUTORESTART_0) >> BP_IPU_DC_UGDE0_0_AUTORESTART_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_AUTORESTART_0.
|
|
#define BF_IPU_DC_UGDE0_0_AUTORESTART_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_AUTORESTART_0) & BM_IPU_DC_UGDE0_0_AUTORESTART_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AUTORESTART_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_AUTORESTART_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_AUTORESTART_0) | BF_IPU_DC_UGDE0_0_AUTORESTART_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE0_0, field NF_NL_0[28:27] (RW)
|
|
*
|
|
* the user may attach his general event #0 to New-line New-Frame and New-field events. One of these
|
|
* event triggers the user's general event #0's counter. The actual internal trigger is the pixel
|
|
* following the occurrence of the selected event.
|
|
*
|
|
* Values:
|
|
* - 00 - New Line
|
|
* - 01 - New Frame
|
|
* - 10 - New Field
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_0_NF_NL_0 (27) //!< Bit position for IPU_DC_UGDE0_0_NF_NL_0.
|
|
#define BM_IPU_DC_UGDE0_0_NF_NL_0 (0x18000000) //!< Bit mask for IPU_DC_UGDE0_0_NF_NL_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_0_NF_NL_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_0_NF_NL_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_0_NF_NL_0) >> BP_IPU_DC_UGDE0_0_NF_NL_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_0_NF_NL_0.
|
|
#define BF_IPU_DC_UGDE0_0_NF_NL_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_0_NF_NL_0) & BM_IPU_DC_UGDE0_0_NF_NL_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NF_NL_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_0_NF_NL_0(x, v) (HW_IPU_DC_UGDE0_0_WR(x, (HW_IPU_DC_UGDE0_0_RD(x) & ~BM_IPU_DC_UGDE0_0_NF_NL_0) | BF_IPU_DC_UGDE0_0_NF_NL_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE0_1 - DC User General Data Event 0 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE0_1 - DC User General Data Event 0 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde0_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde0_1_bitfields
|
|
{
|
|
unsigned STEP_0 : 29; //!< [28:0] This field holds the pre defined value that the counter counts too.
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde0_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE0_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE0_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58178)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE0_1(x) (*(volatile hw_ipu_dc_ugde0_1_t *) HW_IPU_DC_UGDE0_1_ADDR(x))
|
|
#define HW_IPU_DC_UGDE0_1_RD(x) (HW_IPU_DC_UGDE0_1(x).U)
|
|
#define HW_IPU_DC_UGDE0_1_WR(x, v) (HW_IPU_DC_UGDE0_1(x).U = (v))
|
|
#define HW_IPU_DC_UGDE0_1_SET(x, v) (HW_IPU_DC_UGDE0_1_WR(x, HW_IPU_DC_UGDE0_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE0_1_CLR(x, v) (HW_IPU_DC_UGDE0_1_WR(x, HW_IPU_DC_UGDE0_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE0_1_TOG(x, v) (HW_IPU_DC_UGDE0_1_WR(x, HW_IPU_DC_UGDE0_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE0_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE0_1, field STEP_0[28:0] (RW)
|
|
*
|
|
* This field holds the pre defined value that the counter counts too.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_1_STEP_0 (0) //!< Bit position for IPU_DC_UGDE0_1_STEP_0.
|
|
#define BM_IPU_DC_UGDE0_1_STEP_0 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE0_1_STEP_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_1_STEP_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_1_STEP_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_1_STEP_0) >> BP_IPU_DC_UGDE0_1_STEP_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_1_STEP_0.
|
|
#define BF_IPU_DC_UGDE0_1_STEP_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_1_STEP_0) & BM_IPU_DC_UGDE0_1_STEP_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_1_STEP_0(x, v) (HW_IPU_DC_UGDE0_1_WR(x, (HW_IPU_DC_UGDE0_1_RD(x) & ~BM_IPU_DC_UGDE0_1_STEP_0) | BF_IPU_DC_UGDE0_1_STEP_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE0_2 - DC User General Data Event 0 Register2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE0_2 - DC User General Data Event 0 Register2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde0_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde0_2_bitfields
|
|
{
|
|
unsigned OFFSET_DT_0 : 29; //!< [28:0] This field defines the offset value from which the counter of user general event #0 will start counting from
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde0_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE0_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE0_2_ADDR(x) (REGS_IPU_BASE(x) + 0x5817c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE0_2(x) (*(volatile hw_ipu_dc_ugde0_2_t *) HW_IPU_DC_UGDE0_2_ADDR(x))
|
|
#define HW_IPU_DC_UGDE0_2_RD(x) (HW_IPU_DC_UGDE0_2(x).U)
|
|
#define HW_IPU_DC_UGDE0_2_WR(x, v) (HW_IPU_DC_UGDE0_2(x).U = (v))
|
|
#define HW_IPU_DC_UGDE0_2_SET(x, v) (HW_IPU_DC_UGDE0_2_WR(x, HW_IPU_DC_UGDE0_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE0_2_CLR(x, v) (HW_IPU_DC_UGDE0_2_WR(x, HW_IPU_DC_UGDE0_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE0_2_TOG(x, v) (HW_IPU_DC_UGDE0_2_WR(x, HW_IPU_DC_UGDE0_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE0_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE0_2, field OFFSET_DT_0[28:0] (RW)
|
|
*
|
|
* This field defines the offset value from which the counter of user general event #0 will start
|
|
* counting from
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_2_OFFSET_DT_0 (0) //!< Bit position for IPU_DC_UGDE0_2_OFFSET_DT_0.
|
|
#define BM_IPU_DC_UGDE0_2_OFFSET_DT_0 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE0_2_OFFSET_DT_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_2_OFFSET_DT_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_2_OFFSET_DT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_2_OFFSET_DT_0) >> BP_IPU_DC_UGDE0_2_OFFSET_DT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_2_OFFSET_DT_0.
|
|
#define BF_IPU_DC_UGDE0_2_OFFSET_DT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_2_OFFSET_DT_0) & BM_IPU_DC_UGDE0_2_OFFSET_DT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_DT_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_2_OFFSET_DT_0(x, v) (HW_IPU_DC_UGDE0_2_WR(x, (HW_IPU_DC_UGDE0_2_RD(x) & ~BM_IPU_DC_UGDE0_2_OFFSET_DT_0) | BF_IPU_DC_UGDE0_2_OFFSET_DT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE0_3 - DC User General Data Event 0 Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE0_3 - DC User General Data Event 0 Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde0_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde0_3_bitfields
|
|
{
|
|
unsigned STEP_REPEAT_0 : 29; //!< [28:0] When auto reload mode is disabled this field defines the number of events that will be generated by the user general event #0 mechanism
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde0_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE0_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE0_3_ADDR(x) (REGS_IPU_BASE(x) + 0x58180)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE0_3(x) (*(volatile hw_ipu_dc_ugde0_3_t *) HW_IPU_DC_UGDE0_3_ADDR(x))
|
|
#define HW_IPU_DC_UGDE0_3_RD(x) (HW_IPU_DC_UGDE0_3(x).U)
|
|
#define HW_IPU_DC_UGDE0_3_WR(x, v) (HW_IPU_DC_UGDE0_3(x).U = (v))
|
|
#define HW_IPU_DC_UGDE0_3_SET(x, v) (HW_IPU_DC_UGDE0_3_WR(x, HW_IPU_DC_UGDE0_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE0_3_CLR(x, v) (HW_IPU_DC_UGDE0_3_WR(x, HW_IPU_DC_UGDE0_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE0_3_TOG(x, v) (HW_IPU_DC_UGDE0_3_WR(x, HW_IPU_DC_UGDE0_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE0_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE0_3, field STEP_REPEAT_0[28:0] (RW)
|
|
*
|
|
* When auto reload mode is disabled this field defines the number of events that will be generated
|
|
* by the user general event #0 mechanism
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE0_3_STEP_REPEAT_0 (0) //!< Bit position for IPU_DC_UGDE0_3_STEP_REPEAT_0.
|
|
#define BM_IPU_DC_UGDE0_3_STEP_REPEAT_0 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE0_3_STEP_REPEAT_0.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE0_3_STEP_REPEAT_0 from a register value.
|
|
#define BG_IPU_DC_UGDE0_3_STEP_REPEAT_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE0_3_STEP_REPEAT_0) >> BP_IPU_DC_UGDE0_3_STEP_REPEAT_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE0_3_STEP_REPEAT_0.
|
|
#define BF_IPU_DC_UGDE0_3_STEP_REPEAT_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE0_3_STEP_REPEAT_0) & BM_IPU_DC_UGDE0_3_STEP_REPEAT_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_REPEAT_0 field to a new value.
|
|
#define BW_IPU_DC_UGDE0_3_STEP_REPEAT_0(x, v) (HW_IPU_DC_UGDE0_3_WR(x, (HW_IPU_DC_UGDE0_3_RD(x) & ~BM_IPU_DC_UGDE0_3_STEP_REPEAT_0) | BF_IPU_DC_UGDE0_3_STEP_REPEAT_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE1_0 - DC User General Data Event 1Register0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE1_0 - DC User General Data Event 1Register0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde1_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde1_0_bitfields
|
|
{
|
|
unsigned ID_CODED_1 : 3; //!< [2:0] This field defines the number of DC channel number that user's general event #1 will be associated to
|
|
unsigned COD_EV_PRIORITY_1 : 4; //!< [6:3] This field defines the priority of the user general event #1
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved
|
|
unsigned COD_EV_START_1 : 8; //!< [15:8] This field holds a pointer in the microcode holding the routine to be performed following the user general event #1.
|
|
unsigned COD_ODD_START_1 : 8; //!< [23:16] This field holds a pointer in the microcode holding the routine to be performed following the user general event #1.
|
|
unsigned RESERVED1 : 1; //!< [24] Reserved.
|
|
unsigned ODD_EN_1 : 1; //!< [25] The user's general event #1 may be split into 2 internal signals.
|
|
unsigned AUTORESTART_1 : 1; //!< [26] User's general event #1 auto restart mode
|
|
unsigned NF_NL_1 : 2; //!< [28:27] the user may attach his general event #1 to New-line New-Frame and New-field events.
|
|
unsigned RESERVED2 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde1_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE1_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE1_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58184)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE1_0(x) (*(volatile hw_ipu_dc_ugde1_0_t *) HW_IPU_DC_UGDE1_0_ADDR(x))
|
|
#define HW_IPU_DC_UGDE1_0_RD(x) (HW_IPU_DC_UGDE1_0(x).U)
|
|
#define HW_IPU_DC_UGDE1_0_WR(x, v) (HW_IPU_DC_UGDE1_0(x).U = (v))
|
|
#define HW_IPU_DC_UGDE1_0_SET(x, v) (HW_IPU_DC_UGDE1_0_WR(x, HW_IPU_DC_UGDE1_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE1_0_CLR(x, v) (HW_IPU_DC_UGDE1_0_WR(x, HW_IPU_DC_UGDE1_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE1_0_TOG(x, v) (HW_IPU_DC_UGDE1_0_WR(x, HW_IPU_DC_UGDE1_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE1_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field ID_CODED_1[2:0] (RW)
|
|
*
|
|
* This field defines the number of DC channel number that user's general event #1 will be
|
|
* associated to
|
|
*
|
|
* Values:
|
|
* - 000 - DC channel_0
|
|
* - 001 - DC channel_1
|
|
* - 010 - DC channel_2
|
|
* - 011 - DC channel_5 (DP_SYNC)
|
|
* - 100 - DC channel_6 (DP ASYNC)
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_ID_CODED_1 (0) //!< Bit position for IPU_DC_UGDE1_0_ID_CODED_1.
|
|
#define BM_IPU_DC_UGDE1_0_ID_CODED_1 (0x00000007) //!< Bit mask for IPU_DC_UGDE1_0_ID_CODED_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_ID_CODED_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_ID_CODED_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_ID_CODED_1) >> BP_IPU_DC_UGDE1_0_ID_CODED_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_ID_CODED_1.
|
|
#define BF_IPU_DC_UGDE1_0_ID_CODED_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_ID_CODED_1) & BM_IPU_DC_UGDE1_0_ID_CODED_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ID_CODED_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_ID_CODED_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_ID_CODED_1) | BF_IPU_DC_UGDE1_0_ID_CODED_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field COD_EV_PRIORITY_1[6:3] (RW)
|
|
*
|
|
* This field defines the priority of the user general event #1 The priority between the events
|
|
* should be set to a unique value. i.e. two events must not have the same priority (except 0000 -
|
|
* disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1 (3) //!< Bit position for IPU_DC_UGDE1_0_COD_EV_PRIORITY_1.
|
|
#define BM_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1 (0x00000078) //!< Bit mask for IPU_DC_UGDE1_0_COD_EV_PRIORITY_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_COD_EV_PRIORITY_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1) >> BP_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_COD_EV_PRIORITY_1.
|
|
#define BF_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1) & BM_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_PRIORITY_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1) | BF_IPU_DC_UGDE1_0_COD_EV_PRIORITY_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field COD_EV_START_1[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #1. When ODD_MODE is enabled, only the even events will use this pointer When
|
|
* ODD_MODE is disabled, all the events will use this pointer
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_COD_EV_START_1 (8) //!< Bit position for IPU_DC_UGDE1_0_COD_EV_START_1.
|
|
#define BM_IPU_DC_UGDE1_0_COD_EV_START_1 (0x0000ff00) //!< Bit mask for IPU_DC_UGDE1_0_COD_EV_START_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_COD_EV_START_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_COD_EV_START_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_COD_EV_START_1) >> BP_IPU_DC_UGDE1_0_COD_EV_START_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_COD_EV_START_1.
|
|
#define BF_IPU_DC_UGDE1_0_COD_EV_START_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_COD_EV_START_1) & BM_IPU_DC_UGDE1_0_COD_EV_START_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_START_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_COD_EV_START_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_COD_EV_START_1) | BF_IPU_DC_UGDE1_0_COD_EV_START_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field COD_ODD_START_1[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #1. When ODD_MODE is enabled, only the odd events will use this pointer When
|
|
* ODD_MODE is disabled this field is ignored
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_COD_ODD_START_1 (16) //!< Bit position for IPU_DC_UGDE1_0_COD_ODD_START_1.
|
|
#define BM_IPU_DC_UGDE1_0_COD_ODD_START_1 (0x00ff0000) //!< Bit mask for IPU_DC_UGDE1_0_COD_ODD_START_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_COD_ODD_START_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_COD_ODD_START_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_COD_ODD_START_1) >> BP_IPU_DC_UGDE1_0_COD_ODD_START_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_COD_ODD_START_1.
|
|
#define BF_IPU_DC_UGDE1_0_COD_ODD_START_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_COD_ODD_START_1) & BM_IPU_DC_UGDE1_0_COD_ODD_START_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_ODD_START_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_COD_ODD_START_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_COD_ODD_START_1) | BF_IPU_DC_UGDE1_0_COD_ODD_START_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field ODD_EN_1[25] (RW)
|
|
*
|
|
* The user's general event #1 may be split into 2 internal signals. One one mode all the events are
|
|
* sent on one signal, on the second mode odd events are sent over one signal while even events are
|
|
* sent over the other signal (ODD_MODE)
|
|
*
|
|
* Values:
|
|
* - 0 - ODD_MODE is disabled
|
|
* - 1 - ODD_MODE is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_ODD_EN_1 (25) //!< Bit position for IPU_DC_UGDE1_0_ODD_EN_1.
|
|
#define BM_IPU_DC_UGDE1_0_ODD_EN_1 (0x02000000) //!< Bit mask for IPU_DC_UGDE1_0_ODD_EN_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_ODD_EN_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_ODD_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_ODD_EN_1) >> BP_IPU_DC_UGDE1_0_ODD_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_ODD_EN_1.
|
|
#define BF_IPU_DC_UGDE1_0_ODD_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_ODD_EN_1) & BM_IPU_DC_UGDE1_0_ODD_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ODD_EN_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_ODD_EN_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_ODD_EN_1) | BF_IPU_DC_UGDE1_0_ODD_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field AUTORESTART_1[26] (RW)
|
|
*
|
|
* User's general event #1 auto restart mode
|
|
*
|
|
* Values:
|
|
* - 0 - disable
|
|
* - 1 - User's general event #1's counter is automatically restarted.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_AUTORESTART_1 (26) //!< Bit position for IPU_DC_UGDE1_0_AUTORESTART_1.
|
|
#define BM_IPU_DC_UGDE1_0_AUTORESTART_1 (0x04000000) //!< Bit mask for IPU_DC_UGDE1_0_AUTORESTART_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_AUTORESTART_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_AUTORESTART_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_AUTORESTART_1) >> BP_IPU_DC_UGDE1_0_AUTORESTART_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_AUTORESTART_1.
|
|
#define BF_IPU_DC_UGDE1_0_AUTORESTART_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_AUTORESTART_1) & BM_IPU_DC_UGDE1_0_AUTORESTART_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AUTORESTART_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_AUTORESTART_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_AUTORESTART_1) | BF_IPU_DC_UGDE1_0_AUTORESTART_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE1_0, field NF_NL_1[28:27] (RW)
|
|
*
|
|
* the user may attach his general event #1 to New-line New-Frame and New-field events. One of these
|
|
* event triggers the user's general event #1's counter. The actual internal trigger is the pixel
|
|
* following the occurrence of the selected event.
|
|
*
|
|
* Values:
|
|
* - 00 - New Line
|
|
* - 01 - New Frame
|
|
* - 10 - New Field
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_0_NF_NL_1 (27) //!< Bit position for IPU_DC_UGDE1_0_NF_NL_1.
|
|
#define BM_IPU_DC_UGDE1_0_NF_NL_1 (0x18000000) //!< Bit mask for IPU_DC_UGDE1_0_NF_NL_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_0_NF_NL_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_0_NF_NL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_0_NF_NL_1) >> BP_IPU_DC_UGDE1_0_NF_NL_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_0_NF_NL_1.
|
|
#define BF_IPU_DC_UGDE1_0_NF_NL_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_0_NF_NL_1) & BM_IPU_DC_UGDE1_0_NF_NL_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NF_NL_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_0_NF_NL_1(x, v) (HW_IPU_DC_UGDE1_0_WR(x, (HW_IPU_DC_UGDE1_0_RD(x) & ~BM_IPU_DC_UGDE1_0_NF_NL_1) | BF_IPU_DC_UGDE1_0_NF_NL_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE1_1 - DC User General Data Event 1 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE1_1 - DC User General Data Event 1 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde1_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde1_1_bitfields
|
|
{
|
|
unsigned STEP_1 : 29; //!< [28:0] This field hold the pre defined value that the counter counts too
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde1_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE1_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE1_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58188)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE1_1(x) (*(volatile hw_ipu_dc_ugde1_1_t *) HW_IPU_DC_UGDE1_1_ADDR(x))
|
|
#define HW_IPU_DC_UGDE1_1_RD(x) (HW_IPU_DC_UGDE1_1(x).U)
|
|
#define HW_IPU_DC_UGDE1_1_WR(x, v) (HW_IPU_DC_UGDE1_1(x).U = (v))
|
|
#define HW_IPU_DC_UGDE1_1_SET(x, v) (HW_IPU_DC_UGDE1_1_WR(x, HW_IPU_DC_UGDE1_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE1_1_CLR(x, v) (HW_IPU_DC_UGDE1_1_WR(x, HW_IPU_DC_UGDE1_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE1_1_TOG(x, v) (HW_IPU_DC_UGDE1_1_WR(x, HW_IPU_DC_UGDE1_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE1_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE1_1, field STEP_1[28:0] (RW)
|
|
*
|
|
* This field hold the pre defined value that the counter counts too
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_1_STEP_1 (0) //!< Bit position for IPU_DC_UGDE1_1_STEP_1.
|
|
#define BM_IPU_DC_UGDE1_1_STEP_1 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE1_1_STEP_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_1_STEP_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_1_STEP_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_1_STEP_1) >> BP_IPU_DC_UGDE1_1_STEP_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_1_STEP_1.
|
|
#define BF_IPU_DC_UGDE1_1_STEP_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_1_STEP_1) & BM_IPU_DC_UGDE1_1_STEP_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_1_STEP_1(x, v) (HW_IPU_DC_UGDE1_1_WR(x, (HW_IPU_DC_UGDE1_1_RD(x) & ~BM_IPU_DC_UGDE1_1_STEP_1) | BF_IPU_DC_UGDE1_1_STEP_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE1_2 - DC User General Data Event 1Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE1_2 - DC User General Data Event 1Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde1_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde1_2_bitfields
|
|
{
|
|
unsigned OFFSET_DT_1 : 29; //!< [28:0] This field defines the offset value from which the counter of user general event #1 will start counting from
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde1_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE1_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE1_2_ADDR(x) (REGS_IPU_BASE(x) + 0x5818c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE1_2(x) (*(volatile hw_ipu_dc_ugde1_2_t *) HW_IPU_DC_UGDE1_2_ADDR(x))
|
|
#define HW_IPU_DC_UGDE1_2_RD(x) (HW_IPU_DC_UGDE1_2(x).U)
|
|
#define HW_IPU_DC_UGDE1_2_WR(x, v) (HW_IPU_DC_UGDE1_2(x).U = (v))
|
|
#define HW_IPU_DC_UGDE1_2_SET(x, v) (HW_IPU_DC_UGDE1_2_WR(x, HW_IPU_DC_UGDE1_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE1_2_CLR(x, v) (HW_IPU_DC_UGDE1_2_WR(x, HW_IPU_DC_UGDE1_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE1_2_TOG(x, v) (HW_IPU_DC_UGDE1_2_WR(x, HW_IPU_DC_UGDE1_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE1_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE1_2, field OFFSET_DT_1[28:0] (RW)
|
|
*
|
|
* This field defines the offset value from which the counter of user general event #1 will start
|
|
* counting from
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_2_OFFSET_DT_1 (0) //!< Bit position for IPU_DC_UGDE1_2_OFFSET_DT_1.
|
|
#define BM_IPU_DC_UGDE1_2_OFFSET_DT_1 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE1_2_OFFSET_DT_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_2_OFFSET_DT_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_2_OFFSET_DT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_2_OFFSET_DT_1) >> BP_IPU_DC_UGDE1_2_OFFSET_DT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_2_OFFSET_DT_1.
|
|
#define BF_IPU_DC_UGDE1_2_OFFSET_DT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_2_OFFSET_DT_1) & BM_IPU_DC_UGDE1_2_OFFSET_DT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_DT_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_2_OFFSET_DT_1(x, v) (HW_IPU_DC_UGDE1_2_WR(x, (HW_IPU_DC_UGDE1_2_RD(x) & ~BM_IPU_DC_UGDE1_2_OFFSET_DT_1) | BF_IPU_DC_UGDE1_2_OFFSET_DT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE1_3 - DC User General Data Event 1Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE1_3 - DC User General Data Event 1Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde1_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde1_3_bitfields
|
|
{
|
|
unsigned STEP_REPEAT_1 : 29; //!< [28:0] When auto reload mode is disabled this field defines the number of events that will be generated by the user general event #1 mechanism
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde1_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE1_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE1_3_ADDR(x) (REGS_IPU_BASE(x) + 0x58190)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE1_3(x) (*(volatile hw_ipu_dc_ugde1_3_t *) HW_IPU_DC_UGDE1_3_ADDR(x))
|
|
#define HW_IPU_DC_UGDE1_3_RD(x) (HW_IPU_DC_UGDE1_3(x).U)
|
|
#define HW_IPU_DC_UGDE1_3_WR(x, v) (HW_IPU_DC_UGDE1_3(x).U = (v))
|
|
#define HW_IPU_DC_UGDE1_3_SET(x, v) (HW_IPU_DC_UGDE1_3_WR(x, HW_IPU_DC_UGDE1_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE1_3_CLR(x, v) (HW_IPU_DC_UGDE1_3_WR(x, HW_IPU_DC_UGDE1_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE1_3_TOG(x, v) (HW_IPU_DC_UGDE1_3_WR(x, HW_IPU_DC_UGDE1_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE1_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE1_3, field STEP_REPEAT_1[28:0] (RW)
|
|
*
|
|
* When auto reload mode is disabled this field defines the number of events that will be generated
|
|
* by the user general event #1 mechanism
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE1_3_STEP_REPEAT_1 (0) //!< Bit position for IPU_DC_UGDE1_3_STEP_REPEAT_1.
|
|
#define BM_IPU_DC_UGDE1_3_STEP_REPEAT_1 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE1_3_STEP_REPEAT_1.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE1_3_STEP_REPEAT_1 from a register value.
|
|
#define BG_IPU_DC_UGDE1_3_STEP_REPEAT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE1_3_STEP_REPEAT_1) >> BP_IPU_DC_UGDE1_3_STEP_REPEAT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE1_3_STEP_REPEAT_1.
|
|
#define BF_IPU_DC_UGDE1_3_STEP_REPEAT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE1_3_STEP_REPEAT_1) & BM_IPU_DC_UGDE1_3_STEP_REPEAT_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_REPEAT_1 field to a new value.
|
|
#define BW_IPU_DC_UGDE1_3_STEP_REPEAT_1(x, v) (HW_IPU_DC_UGDE1_3_WR(x, (HW_IPU_DC_UGDE1_3_RD(x) & ~BM_IPU_DC_UGDE1_3_STEP_REPEAT_1) | BF_IPU_DC_UGDE1_3_STEP_REPEAT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE2_0 - DC User General Data Event 2 Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE2_0 - DC User General Data Event 2 Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde2_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde2_0_bitfields
|
|
{
|
|
unsigned ID_CODED_2 : 3; //!< [2:0] This field defines the number of DC channel number that user's general event #2 will be associated to
|
|
unsigned COD_EV_PRIORITY_2 : 4; //!< [6:3] This field defines the priority of the user general event #2
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved
|
|
unsigned COD_EV_START_2 : 8; //!< [15:8] This field holds a pointer in the microcode holding the routine to be performed following the user general event #2.
|
|
unsigned COD_ODD_START_2 : 8; //!< [23:16] This field holds a pointer in the microcode holding the routine to be performed following the user general event #2 When ODD_MODE is enabled, only the odd events will use this pointer
|
|
unsigned RESERVED1 : 1; //!< [24] Reserved.
|
|
unsigned ODD_EN_2 : 1; //!< [25] The user's general event #2 may be split into 2 internal signals.
|
|
unsigned AUTORESTART_2 : 1; //!< [26] User's general event #2 auto restart mode
|
|
unsigned NF_NL_2 : 2; //!< [28:27] the user may attach his general event #2 to New-line New-Frame and New-field events.
|
|
unsigned RESERVED2 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde2_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE2_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE2_0_ADDR(x) (REGS_IPU_BASE(x) + 0x58194)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE2_0(x) (*(volatile hw_ipu_dc_ugde2_0_t *) HW_IPU_DC_UGDE2_0_ADDR(x))
|
|
#define HW_IPU_DC_UGDE2_0_RD(x) (HW_IPU_DC_UGDE2_0(x).U)
|
|
#define HW_IPU_DC_UGDE2_0_WR(x, v) (HW_IPU_DC_UGDE2_0(x).U = (v))
|
|
#define HW_IPU_DC_UGDE2_0_SET(x, v) (HW_IPU_DC_UGDE2_0_WR(x, HW_IPU_DC_UGDE2_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE2_0_CLR(x, v) (HW_IPU_DC_UGDE2_0_WR(x, HW_IPU_DC_UGDE2_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE2_0_TOG(x, v) (HW_IPU_DC_UGDE2_0_WR(x, HW_IPU_DC_UGDE2_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE2_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field ID_CODED_2[2:0] (RW)
|
|
*
|
|
* This field defines the number of DC channel number that user's general event #2 will be
|
|
* associated to
|
|
*
|
|
* Values:
|
|
* - 000 - DC channel_0
|
|
* - 001 - DC channel_1
|
|
* - 010 - DC channel_2
|
|
* - 011 - DC channel_5 (DP_SYNC)
|
|
* - 100 - DC channel_6 (DP ASYNC)
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_ID_CODED_2 (0) //!< Bit position for IPU_DC_UGDE2_0_ID_CODED_2.
|
|
#define BM_IPU_DC_UGDE2_0_ID_CODED_2 (0x00000007) //!< Bit mask for IPU_DC_UGDE2_0_ID_CODED_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_ID_CODED_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_ID_CODED_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_ID_CODED_2) >> BP_IPU_DC_UGDE2_0_ID_CODED_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_ID_CODED_2.
|
|
#define BF_IPU_DC_UGDE2_0_ID_CODED_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_ID_CODED_2) & BM_IPU_DC_UGDE2_0_ID_CODED_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ID_CODED_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_ID_CODED_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_ID_CODED_2) | BF_IPU_DC_UGDE2_0_ID_CODED_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field COD_EV_PRIORITY_2[6:3] (RW)
|
|
*
|
|
* This field defines the priority of the user general event #2 The priority between the events
|
|
* should be set to a unique value. i.e. two events must not have the same priority (except 0000 -
|
|
* disable)
|
|
*
|
|
* Values:
|
|
* - 0000 - disable
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2 (3) //!< Bit position for IPU_DC_UGDE2_0_COD_EV_PRIORITY_2.
|
|
#define BM_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2 (0x00000078) //!< Bit mask for IPU_DC_UGDE2_0_COD_EV_PRIORITY_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_COD_EV_PRIORITY_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2) >> BP_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_COD_EV_PRIORITY_2.
|
|
#define BF_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2) & BM_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_PRIORITY_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2) | BF_IPU_DC_UGDE2_0_COD_EV_PRIORITY_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field COD_EV_START_2[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #2. When ODD_MODE is enabled, only the even events will use this pointer When
|
|
* ODD_MODE is disabled, all the events will use this pointer
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_COD_EV_START_2 (8) //!< Bit position for IPU_DC_UGDE2_0_COD_EV_START_2.
|
|
#define BM_IPU_DC_UGDE2_0_COD_EV_START_2 (0x0000ff00) //!< Bit mask for IPU_DC_UGDE2_0_COD_EV_START_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_COD_EV_START_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_COD_EV_START_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_COD_EV_START_2) >> BP_IPU_DC_UGDE2_0_COD_EV_START_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_COD_EV_START_2.
|
|
#define BF_IPU_DC_UGDE2_0_COD_EV_START_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_COD_EV_START_2) & BM_IPU_DC_UGDE2_0_COD_EV_START_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_START_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_COD_EV_START_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_COD_EV_START_2) | BF_IPU_DC_UGDE2_0_COD_EV_START_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field COD_ODD_START_2[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #2 When ODD_MODE is enabled, only the odd events will use this pointer When
|
|
* ODD_MODE is disabled this field is ignored
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_COD_ODD_START_2 (16) //!< Bit position for IPU_DC_UGDE2_0_COD_ODD_START_2.
|
|
#define BM_IPU_DC_UGDE2_0_COD_ODD_START_2 (0x00ff0000) //!< Bit mask for IPU_DC_UGDE2_0_COD_ODD_START_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_COD_ODD_START_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_COD_ODD_START_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_COD_ODD_START_2) >> BP_IPU_DC_UGDE2_0_COD_ODD_START_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_COD_ODD_START_2.
|
|
#define BF_IPU_DC_UGDE2_0_COD_ODD_START_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_COD_ODD_START_2) & BM_IPU_DC_UGDE2_0_COD_ODD_START_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_ODD_START_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_COD_ODD_START_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_COD_ODD_START_2) | BF_IPU_DC_UGDE2_0_COD_ODD_START_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field ODD_EN_2[25] (RW)
|
|
*
|
|
* The user's general event #2 may be split into 2 internal signals. One one mode all the events are
|
|
* sent on one signal, on the second mode odd events are sent over one signal while even events are
|
|
* sent over the other signal (ODD_MODE)
|
|
*
|
|
* Values:
|
|
* - 0 - ODD_MODE is disabled
|
|
* - 1 - ODD_MODE is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_ODD_EN_2 (25) //!< Bit position for IPU_DC_UGDE2_0_ODD_EN_2.
|
|
#define BM_IPU_DC_UGDE2_0_ODD_EN_2 (0x02000000) //!< Bit mask for IPU_DC_UGDE2_0_ODD_EN_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_ODD_EN_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_ODD_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_ODD_EN_2) >> BP_IPU_DC_UGDE2_0_ODD_EN_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_ODD_EN_2.
|
|
#define BF_IPU_DC_UGDE2_0_ODD_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_ODD_EN_2) & BM_IPU_DC_UGDE2_0_ODD_EN_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ODD_EN_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_ODD_EN_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_ODD_EN_2) | BF_IPU_DC_UGDE2_0_ODD_EN_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field AUTORESTART_2[26] (RW)
|
|
*
|
|
* User's general event #2 auto restart mode
|
|
*
|
|
* Values:
|
|
* - 0 - disable
|
|
* - 1 - User's general event #2's counter is automatically restarted.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_AUTORESTART_2 (26) //!< Bit position for IPU_DC_UGDE2_0_AUTORESTART_2.
|
|
#define BM_IPU_DC_UGDE2_0_AUTORESTART_2 (0x04000000) //!< Bit mask for IPU_DC_UGDE2_0_AUTORESTART_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_AUTORESTART_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_AUTORESTART_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_AUTORESTART_2) >> BP_IPU_DC_UGDE2_0_AUTORESTART_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_AUTORESTART_2.
|
|
#define BF_IPU_DC_UGDE2_0_AUTORESTART_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_AUTORESTART_2) & BM_IPU_DC_UGDE2_0_AUTORESTART_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AUTORESTART_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_AUTORESTART_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_AUTORESTART_2) | BF_IPU_DC_UGDE2_0_AUTORESTART_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE2_0, field NF_NL_2[28:27] (RW)
|
|
*
|
|
* the user may attach his general event #2 to New-line New-Frame and New-field events. One of these
|
|
* event triggers the user's general event #2's counter. The actual internal trigger is the pixel
|
|
* following the occurrence of the selected event.
|
|
*
|
|
* Values:
|
|
* - 00 - New Line
|
|
* - 01 - New Frame
|
|
* - 10 - New Field
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_0_NF_NL_2 (27) //!< Bit position for IPU_DC_UGDE2_0_NF_NL_2.
|
|
#define BM_IPU_DC_UGDE2_0_NF_NL_2 (0x18000000) //!< Bit mask for IPU_DC_UGDE2_0_NF_NL_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_0_NF_NL_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_0_NF_NL_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_0_NF_NL_2) >> BP_IPU_DC_UGDE2_0_NF_NL_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_0_NF_NL_2.
|
|
#define BF_IPU_DC_UGDE2_0_NF_NL_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_0_NF_NL_2) & BM_IPU_DC_UGDE2_0_NF_NL_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NF_NL_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_0_NF_NL_2(x, v) (HW_IPU_DC_UGDE2_0_WR(x, (HW_IPU_DC_UGDE2_0_RD(x) & ~BM_IPU_DC_UGDE2_0_NF_NL_2) | BF_IPU_DC_UGDE2_0_NF_NL_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE2_1 - DC User General Data Event 2 Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE2_1 - DC User General Data Event 2 Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde2_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde2_1_bitfields
|
|
{
|
|
unsigned STEP_2 : 29; //!< [28:0] This field hold the pre defined value that the counter counts too
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde2_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE2_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE2_1_ADDR(x) (REGS_IPU_BASE(x) + 0x58198)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE2_1(x) (*(volatile hw_ipu_dc_ugde2_1_t *) HW_IPU_DC_UGDE2_1_ADDR(x))
|
|
#define HW_IPU_DC_UGDE2_1_RD(x) (HW_IPU_DC_UGDE2_1(x).U)
|
|
#define HW_IPU_DC_UGDE2_1_WR(x, v) (HW_IPU_DC_UGDE2_1(x).U = (v))
|
|
#define HW_IPU_DC_UGDE2_1_SET(x, v) (HW_IPU_DC_UGDE2_1_WR(x, HW_IPU_DC_UGDE2_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE2_1_CLR(x, v) (HW_IPU_DC_UGDE2_1_WR(x, HW_IPU_DC_UGDE2_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE2_1_TOG(x, v) (HW_IPU_DC_UGDE2_1_WR(x, HW_IPU_DC_UGDE2_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE2_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE2_1, field STEP_2[28:0] (RW)
|
|
*
|
|
* This field hold the pre defined value that the counter counts too
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_1_STEP_2 (0) //!< Bit position for IPU_DC_UGDE2_1_STEP_2.
|
|
#define BM_IPU_DC_UGDE2_1_STEP_2 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE2_1_STEP_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_1_STEP_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_1_STEP_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_1_STEP_2) >> BP_IPU_DC_UGDE2_1_STEP_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_1_STEP_2.
|
|
#define BF_IPU_DC_UGDE2_1_STEP_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_1_STEP_2) & BM_IPU_DC_UGDE2_1_STEP_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_1_STEP_2(x, v) (HW_IPU_DC_UGDE2_1_WR(x, (HW_IPU_DC_UGDE2_1_RD(x) & ~BM_IPU_DC_UGDE2_1_STEP_2) | BF_IPU_DC_UGDE2_1_STEP_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE2_2 - DC User General Data Event 2Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE2_2 - DC User General Data Event 2Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde2_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde2_2_bitfields
|
|
{
|
|
unsigned OFFSET_DT_2 : 29; //!< [28:0] This field defines the offset value from which the counter of user general event #2 will start counting from
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde2_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE2_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE2_2_ADDR(x) (REGS_IPU_BASE(x) + 0x5819c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE2_2(x) (*(volatile hw_ipu_dc_ugde2_2_t *) HW_IPU_DC_UGDE2_2_ADDR(x))
|
|
#define HW_IPU_DC_UGDE2_2_RD(x) (HW_IPU_DC_UGDE2_2(x).U)
|
|
#define HW_IPU_DC_UGDE2_2_WR(x, v) (HW_IPU_DC_UGDE2_2(x).U = (v))
|
|
#define HW_IPU_DC_UGDE2_2_SET(x, v) (HW_IPU_DC_UGDE2_2_WR(x, HW_IPU_DC_UGDE2_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE2_2_CLR(x, v) (HW_IPU_DC_UGDE2_2_WR(x, HW_IPU_DC_UGDE2_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE2_2_TOG(x, v) (HW_IPU_DC_UGDE2_2_WR(x, HW_IPU_DC_UGDE2_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE2_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE2_2, field OFFSET_DT_2[28:0] (RW)
|
|
*
|
|
* This field defines the offset value from which the counter of user general event #2 will start
|
|
* counting from
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_2_OFFSET_DT_2 (0) //!< Bit position for IPU_DC_UGDE2_2_OFFSET_DT_2.
|
|
#define BM_IPU_DC_UGDE2_2_OFFSET_DT_2 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE2_2_OFFSET_DT_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_2_OFFSET_DT_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_2_OFFSET_DT_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_2_OFFSET_DT_2) >> BP_IPU_DC_UGDE2_2_OFFSET_DT_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_2_OFFSET_DT_2.
|
|
#define BF_IPU_DC_UGDE2_2_OFFSET_DT_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_2_OFFSET_DT_2) & BM_IPU_DC_UGDE2_2_OFFSET_DT_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_DT_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_2_OFFSET_DT_2(x, v) (HW_IPU_DC_UGDE2_2_WR(x, (HW_IPU_DC_UGDE2_2_RD(x) & ~BM_IPU_DC_UGDE2_2_OFFSET_DT_2) | BF_IPU_DC_UGDE2_2_OFFSET_DT_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE2_3 - DC User General Data Event 2Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE2_3 - DC User General Data Event 2Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde2_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde2_3_bitfields
|
|
{
|
|
unsigned STEP_REPEAT_2 : 29; //!< [28:0] When auto reload mode is disabled this field defines the number of events that will be generated by the user general event #2 mechanism
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde2_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE2_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE2_3_ADDR(x) (REGS_IPU_BASE(x) + 0x581a0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE2_3(x) (*(volatile hw_ipu_dc_ugde2_3_t *) HW_IPU_DC_UGDE2_3_ADDR(x))
|
|
#define HW_IPU_DC_UGDE2_3_RD(x) (HW_IPU_DC_UGDE2_3(x).U)
|
|
#define HW_IPU_DC_UGDE2_3_WR(x, v) (HW_IPU_DC_UGDE2_3(x).U = (v))
|
|
#define HW_IPU_DC_UGDE2_3_SET(x, v) (HW_IPU_DC_UGDE2_3_WR(x, HW_IPU_DC_UGDE2_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE2_3_CLR(x, v) (HW_IPU_DC_UGDE2_3_WR(x, HW_IPU_DC_UGDE2_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE2_3_TOG(x, v) (HW_IPU_DC_UGDE2_3_WR(x, HW_IPU_DC_UGDE2_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE2_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE2_3, field STEP_REPEAT_2[28:0] (RW)
|
|
*
|
|
* When auto reload mode is disabled this field defines the number of events that will be generated
|
|
* by the user general event #2 mechanism
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE2_3_STEP_REPEAT_2 (0) //!< Bit position for IPU_DC_UGDE2_3_STEP_REPEAT_2.
|
|
#define BM_IPU_DC_UGDE2_3_STEP_REPEAT_2 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE2_3_STEP_REPEAT_2.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE2_3_STEP_REPEAT_2 from a register value.
|
|
#define BG_IPU_DC_UGDE2_3_STEP_REPEAT_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE2_3_STEP_REPEAT_2) >> BP_IPU_DC_UGDE2_3_STEP_REPEAT_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE2_3_STEP_REPEAT_2.
|
|
#define BF_IPU_DC_UGDE2_3_STEP_REPEAT_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE2_3_STEP_REPEAT_2) & BM_IPU_DC_UGDE2_3_STEP_REPEAT_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_REPEAT_2 field to a new value.
|
|
#define BW_IPU_DC_UGDE2_3_STEP_REPEAT_2(x, v) (HW_IPU_DC_UGDE2_3_WR(x, (HW_IPU_DC_UGDE2_3_RD(x) & ~BM_IPU_DC_UGDE2_3_STEP_REPEAT_2) | BF_IPU_DC_UGDE2_3_STEP_REPEAT_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE3_0 - DC User General Data Event 3Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE3_0 - DC User General Data Event 3Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde3_0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde3_0_bitfields
|
|
{
|
|
unsigned ID_CODED_3 : 3; //!< [2:0] This field defines the number of DC channel number that user's general event #3 will be associated to
|
|
unsigned COD_EV_PRIORITY_3 : 4; //!< [6:3] This field defines the priority of the user general event #3
|
|
unsigned RESERVED0 : 1; //!< [7] Reserved
|
|
unsigned COD_EV_START_3 : 8; //!< [15:8] This field holds a pointer in the microcode holding the routine to be performed following the user general event #3.
|
|
unsigned COD_ODD_START_3 : 8; //!< [23:16] This field holds a pointer in the microcode holding the routine to be performed following the user general event #3.
|
|
unsigned RESERVED1 : 1; //!< [24] Reserved.
|
|
unsigned ODD_EN_3 : 1; //!< [25] The user's general event #3 may be split into 2 internal signals.
|
|
unsigned AUTORESTART_3 : 1; //!< [26] User's general event #3 auto restart mode
|
|
unsigned NF_NL_3 : 2; //!< [28:27] the user may attach his general event #3 to New-line New-Frame and New-field events.
|
|
unsigned RESERVED2 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde3_0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE3_0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE3_0_ADDR(x) (REGS_IPU_BASE(x) + 0x581a4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE3_0(x) (*(volatile hw_ipu_dc_ugde3_0_t *) HW_IPU_DC_UGDE3_0_ADDR(x))
|
|
#define HW_IPU_DC_UGDE3_0_RD(x) (HW_IPU_DC_UGDE3_0(x).U)
|
|
#define HW_IPU_DC_UGDE3_0_WR(x, v) (HW_IPU_DC_UGDE3_0(x).U = (v))
|
|
#define HW_IPU_DC_UGDE3_0_SET(x, v) (HW_IPU_DC_UGDE3_0_WR(x, HW_IPU_DC_UGDE3_0_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE3_0_CLR(x, v) (HW_IPU_DC_UGDE3_0_WR(x, HW_IPU_DC_UGDE3_0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE3_0_TOG(x, v) (HW_IPU_DC_UGDE3_0_WR(x, HW_IPU_DC_UGDE3_0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE3_0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field ID_CODED_3[2:0] (RW)
|
|
*
|
|
* This field defines the number of DC channel number that user's general event #3 will be
|
|
* associated to
|
|
*
|
|
* Values:
|
|
* - 000 - DC channel_0
|
|
* - 001 - DC channel_1
|
|
* - 010 - DC channel_2
|
|
* - 011 - DC channel_5 (DP_SYNC)
|
|
* - 100 - DC channel_6 (DP ASYNC)
|
|
* - 101 - Reserved
|
|
* - 110 - Reserved
|
|
* - 111 - Reserved.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_ID_CODED_3 (0) //!< Bit position for IPU_DC_UGDE3_0_ID_CODED_3.
|
|
#define BM_IPU_DC_UGDE3_0_ID_CODED_3 (0x00000007) //!< Bit mask for IPU_DC_UGDE3_0_ID_CODED_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_ID_CODED_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_ID_CODED_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_ID_CODED_3) >> BP_IPU_DC_UGDE3_0_ID_CODED_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_ID_CODED_3.
|
|
#define BF_IPU_DC_UGDE3_0_ID_CODED_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_ID_CODED_3) & BM_IPU_DC_UGDE3_0_ID_CODED_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ID_CODED_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_ID_CODED_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_ID_CODED_3) | BF_IPU_DC_UGDE3_0_ID_CODED_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field COD_EV_PRIORITY_3[6:3] (RW)
|
|
*
|
|
* This field defines the priority of the user general event #3
|
|
*
|
|
* Values:
|
|
* - 0000 - disable The priority between the events should be set to a unique value. i.e. two events must not
|
|
* have the same priority (except 0000 - disable)
|
|
* - 0001 - Priority #1 (lowest)
|
|
* - 0010 - Priority #2
|
|
* - 1101 - Priority #13 (highest)
|
|
* - 1110 - Reserved
|
|
* - 1111 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3 (3) //!< Bit position for IPU_DC_UGDE3_0_COD_EV_PRIORITY_3.
|
|
#define BM_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3 (0x00000078) //!< Bit mask for IPU_DC_UGDE3_0_COD_EV_PRIORITY_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_COD_EV_PRIORITY_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3) >> BP_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_COD_EV_PRIORITY_3.
|
|
#define BF_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3) & BM_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_PRIORITY_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3) | BF_IPU_DC_UGDE3_0_COD_EV_PRIORITY_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field COD_EV_START_3[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #3. When ODD_MODE is enabled, only the even events will use this pointer When
|
|
* ODD_MODE is disabled, all the events will use this pointer
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_COD_EV_START_3 (8) //!< Bit position for IPU_DC_UGDE3_0_COD_EV_START_3.
|
|
#define BM_IPU_DC_UGDE3_0_COD_EV_START_3 (0x0000ff00) //!< Bit mask for IPU_DC_UGDE3_0_COD_EV_START_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_COD_EV_START_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_COD_EV_START_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_COD_EV_START_3) >> BP_IPU_DC_UGDE3_0_COD_EV_START_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_COD_EV_START_3.
|
|
#define BF_IPU_DC_UGDE3_0_COD_EV_START_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_COD_EV_START_3) & BM_IPU_DC_UGDE3_0_COD_EV_START_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_EV_START_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_COD_EV_START_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_COD_EV_START_3) | BF_IPU_DC_UGDE3_0_COD_EV_START_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field COD_ODD_START_3[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode holding the routine to be performed following the
|
|
* user general event #3. When ODD_MODE is enabled, only the odd events will use this pointer When
|
|
* ODD_MODE is disabled this field is ignored
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_COD_ODD_START_3 (16) //!< Bit position for IPU_DC_UGDE3_0_COD_ODD_START_3.
|
|
#define BM_IPU_DC_UGDE3_0_COD_ODD_START_3 (0x00ff0000) //!< Bit mask for IPU_DC_UGDE3_0_COD_ODD_START_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_COD_ODD_START_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_COD_ODD_START_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_COD_ODD_START_3) >> BP_IPU_DC_UGDE3_0_COD_ODD_START_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_COD_ODD_START_3.
|
|
#define BF_IPU_DC_UGDE3_0_COD_ODD_START_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_COD_ODD_START_3) & BM_IPU_DC_UGDE3_0_COD_ODD_START_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the COD_ODD_START_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_COD_ODD_START_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_COD_ODD_START_3) | BF_IPU_DC_UGDE3_0_COD_ODD_START_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field ODD_EN_3[25] (RW)
|
|
*
|
|
* The user's general event #3 may be split into 2 internal signals. One one mode all the events are
|
|
* sent on one signal, on the second mode odd events are sent over one signal while even events are
|
|
* sent over the other signal (ODD_MODE)
|
|
*
|
|
* Values:
|
|
* - 0 - ODD_MODE is disabled
|
|
* - 1 - ODD_MODE is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_ODD_EN_3 (25) //!< Bit position for IPU_DC_UGDE3_0_ODD_EN_3.
|
|
#define BM_IPU_DC_UGDE3_0_ODD_EN_3 (0x02000000) //!< Bit mask for IPU_DC_UGDE3_0_ODD_EN_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_ODD_EN_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_ODD_EN_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_ODD_EN_3) >> BP_IPU_DC_UGDE3_0_ODD_EN_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_ODD_EN_3.
|
|
#define BF_IPU_DC_UGDE3_0_ODD_EN_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_ODD_EN_3) & BM_IPU_DC_UGDE3_0_ODD_EN_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ODD_EN_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_ODD_EN_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_ODD_EN_3) | BF_IPU_DC_UGDE3_0_ODD_EN_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field AUTORESTART_3[26] (RW)
|
|
*
|
|
* User's general event #3 auto restart mode
|
|
*
|
|
* Values:
|
|
* - 0 - disable
|
|
* - 1 - User's general event #3's counter is automatically restarted.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_AUTORESTART_3 (26) //!< Bit position for IPU_DC_UGDE3_0_AUTORESTART_3.
|
|
#define BM_IPU_DC_UGDE3_0_AUTORESTART_3 (0x04000000) //!< Bit mask for IPU_DC_UGDE3_0_AUTORESTART_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_AUTORESTART_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_AUTORESTART_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_AUTORESTART_3) >> BP_IPU_DC_UGDE3_0_AUTORESTART_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_AUTORESTART_3.
|
|
#define BF_IPU_DC_UGDE3_0_AUTORESTART_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_AUTORESTART_3) & BM_IPU_DC_UGDE3_0_AUTORESTART_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the AUTORESTART_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_AUTORESTART_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_AUTORESTART_3) | BF_IPU_DC_UGDE3_0_AUTORESTART_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_UGDE3_0, field NF_NL_3[28:27] (RW)
|
|
*
|
|
* the user may attach his general event #3 to New-line New-Frame and New-field events. One of these
|
|
* event triggers the user's general event #3's counter. The actual internal trigger is the pixel
|
|
* following the occurrence of the selected event.
|
|
*
|
|
* Values:
|
|
* - 00 - New Line
|
|
* - 01 - New Frame
|
|
* - 10 - New Field
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_0_NF_NL_3 (27) //!< Bit position for IPU_DC_UGDE3_0_NF_NL_3.
|
|
#define BM_IPU_DC_UGDE3_0_NF_NL_3 (0x18000000) //!< Bit mask for IPU_DC_UGDE3_0_NF_NL_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_0_NF_NL_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_0_NF_NL_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_0_NF_NL_3) >> BP_IPU_DC_UGDE3_0_NF_NL_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_0_NF_NL_3.
|
|
#define BF_IPU_DC_UGDE3_0_NF_NL_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_0_NF_NL_3) & BM_IPU_DC_UGDE3_0_NF_NL_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the NF_NL_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_0_NF_NL_3(x, v) (HW_IPU_DC_UGDE3_0_WR(x, (HW_IPU_DC_UGDE3_0_RD(x) & ~BM_IPU_DC_UGDE3_0_NF_NL_3) | BF_IPU_DC_UGDE3_0_NF_NL_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE3_1 - DC User General Data Event 3Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE3_1 - DC User General Data Event 3Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde3_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde3_1_bitfields
|
|
{
|
|
unsigned STEP_3 : 29; //!< [28:0] This field hold the pre defined value that the counter counts too
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde3_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE3_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE3_1_ADDR(x) (REGS_IPU_BASE(x) + 0x581a8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE3_1(x) (*(volatile hw_ipu_dc_ugde3_1_t *) HW_IPU_DC_UGDE3_1_ADDR(x))
|
|
#define HW_IPU_DC_UGDE3_1_RD(x) (HW_IPU_DC_UGDE3_1(x).U)
|
|
#define HW_IPU_DC_UGDE3_1_WR(x, v) (HW_IPU_DC_UGDE3_1(x).U = (v))
|
|
#define HW_IPU_DC_UGDE3_1_SET(x, v) (HW_IPU_DC_UGDE3_1_WR(x, HW_IPU_DC_UGDE3_1_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE3_1_CLR(x, v) (HW_IPU_DC_UGDE3_1_WR(x, HW_IPU_DC_UGDE3_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE3_1_TOG(x, v) (HW_IPU_DC_UGDE3_1_WR(x, HW_IPU_DC_UGDE3_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE3_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE3_1, field STEP_3[28:0] (RW)
|
|
*
|
|
* This field hold the pre defined value that the counter counts too
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_1_STEP_3 (0) //!< Bit position for IPU_DC_UGDE3_1_STEP_3.
|
|
#define BM_IPU_DC_UGDE3_1_STEP_3 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE3_1_STEP_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_1_STEP_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_1_STEP_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_1_STEP_3) >> BP_IPU_DC_UGDE3_1_STEP_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_1_STEP_3.
|
|
#define BF_IPU_DC_UGDE3_1_STEP_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_1_STEP_3) & BM_IPU_DC_UGDE3_1_STEP_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_1_STEP_3(x, v) (HW_IPU_DC_UGDE3_1_WR(x, (HW_IPU_DC_UGDE3_1_RD(x) & ~BM_IPU_DC_UGDE3_1_STEP_3) | BF_IPU_DC_UGDE3_1_STEP_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE3_2 - DC User General Data Event 3Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE3_2 - DC User General Data Event 3Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde3_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde3_2_bitfields
|
|
{
|
|
unsigned OFFSET_DT_3 : 29; //!< [28:0] This field defines the offset value from which the counter of user general event #3 will start counting from
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde3_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE3_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE3_2_ADDR(x) (REGS_IPU_BASE(x) + 0x581ac)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE3_2(x) (*(volatile hw_ipu_dc_ugde3_2_t *) HW_IPU_DC_UGDE3_2_ADDR(x))
|
|
#define HW_IPU_DC_UGDE3_2_RD(x) (HW_IPU_DC_UGDE3_2(x).U)
|
|
#define HW_IPU_DC_UGDE3_2_WR(x, v) (HW_IPU_DC_UGDE3_2(x).U = (v))
|
|
#define HW_IPU_DC_UGDE3_2_SET(x, v) (HW_IPU_DC_UGDE3_2_WR(x, HW_IPU_DC_UGDE3_2_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE3_2_CLR(x, v) (HW_IPU_DC_UGDE3_2_WR(x, HW_IPU_DC_UGDE3_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE3_2_TOG(x, v) (HW_IPU_DC_UGDE3_2_WR(x, HW_IPU_DC_UGDE3_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE3_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE3_2, field OFFSET_DT_3[28:0] (RW)
|
|
*
|
|
* This field defines the offset value from which the counter of user general event #3 will start
|
|
* counting from
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_2_OFFSET_DT_3 (0) //!< Bit position for IPU_DC_UGDE3_2_OFFSET_DT_3.
|
|
#define BM_IPU_DC_UGDE3_2_OFFSET_DT_3 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE3_2_OFFSET_DT_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_2_OFFSET_DT_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_2_OFFSET_DT_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_2_OFFSET_DT_3) >> BP_IPU_DC_UGDE3_2_OFFSET_DT_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_2_OFFSET_DT_3.
|
|
#define BF_IPU_DC_UGDE3_2_OFFSET_DT_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_2_OFFSET_DT_3) & BM_IPU_DC_UGDE3_2_OFFSET_DT_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the OFFSET_DT_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_2_OFFSET_DT_3(x, v) (HW_IPU_DC_UGDE3_2_WR(x, (HW_IPU_DC_UGDE3_2_RD(x) & ~BM_IPU_DC_UGDE3_2_OFFSET_DT_3) | BF_IPU_DC_UGDE3_2_OFFSET_DT_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_UGDE3_3 - DC User General Data Event 3Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_UGDE3_3 - DC User General Data Event 3Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_ugde3_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_ugde3_3_bitfields
|
|
{
|
|
unsigned STEP_REPEAT_3 : 29; //!< [28:0] When auto reload mode is disabled this field defines the number of events that will be generated by the user general event #3 mechanism
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_ugde3_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_UGDE3_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_UGDE3_3_ADDR(x) (REGS_IPU_BASE(x) + 0x581b0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_UGDE3_3(x) (*(volatile hw_ipu_dc_ugde3_3_t *) HW_IPU_DC_UGDE3_3_ADDR(x))
|
|
#define HW_IPU_DC_UGDE3_3_RD(x) (HW_IPU_DC_UGDE3_3(x).U)
|
|
#define HW_IPU_DC_UGDE3_3_WR(x, v) (HW_IPU_DC_UGDE3_3(x).U = (v))
|
|
#define HW_IPU_DC_UGDE3_3_SET(x, v) (HW_IPU_DC_UGDE3_3_WR(x, HW_IPU_DC_UGDE3_3_RD(x) | (v)))
|
|
#define HW_IPU_DC_UGDE3_3_CLR(x, v) (HW_IPU_DC_UGDE3_3_WR(x, HW_IPU_DC_UGDE3_3_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_UGDE3_3_TOG(x, v) (HW_IPU_DC_UGDE3_3_WR(x, HW_IPU_DC_UGDE3_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_UGDE3_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_UGDE3_3, field STEP_REPEAT_3[28:0] (RW)
|
|
*
|
|
* When auto reload mode is disabled this field defines the number of events that will be generated
|
|
* by the user general event #3 mechanism
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_UGDE3_3_STEP_REPEAT_3 (0) //!< Bit position for IPU_DC_UGDE3_3_STEP_REPEAT_3.
|
|
#define BM_IPU_DC_UGDE3_3_STEP_REPEAT_3 (0x1fffffff) //!< Bit mask for IPU_DC_UGDE3_3_STEP_REPEAT_3.
|
|
|
|
//! @brief Get value of IPU_DC_UGDE3_3_STEP_REPEAT_3 from a register value.
|
|
#define BG_IPU_DC_UGDE3_3_STEP_REPEAT_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_UGDE3_3_STEP_REPEAT_3) >> BP_IPU_DC_UGDE3_3_STEP_REPEAT_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_UGDE3_3_STEP_REPEAT_3.
|
|
#define BF_IPU_DC_UGDE3_3_STEP_REPEAT_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_UGDE3_3_STEP_REPEAT_3) & BM_IPU_DC_UGDE3_3_STEP_REPEAT_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the STEP_REPEAT_3 field to a new value.
|
|
#define BW_IPU_DC_UGDE3_3_STEP_REPEAT_3(x, v) (HW_IPU_DC_UGDE3_3_WR(x, (HW_IPU_DC_UGDE3_3_RD(x) & ~BM_IPU_DC_UGDE3_3_STEP_REPEAT_3) | BF_IPU_DC_UGDE3_3_STEP_REPEAT_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_LLA0 - DC Low Level Access Control Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_LLA0 - DC Low Level Access Control Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_lla0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_lla0_bitfields
|
|
{
|
|
unsigned MCU_RS_0_0 : 8; //!< [7:0] This field holds a pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_8, when in Low level access mode,
|
|
unsigned MCU_RS_1_0 : 8; //!< [15:8] This field holds a pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_8, when in Low level access mode,
|
|
unsigned MCU_RS_2_0 : 8; //!< [23:16] This field holds a pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_8, when in Low level access mode,
|
|
unsigned MCU_RS_3_0 : 8; //!< [31:24] This field holds a pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_8, when in Low level access mode,
|
|
} B;
|
|
} hw_ipu_dc_lla0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_LLA0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_LLA0_ADDR(x) (REGS_IPU_BASE(x) + 0x581b4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_LLA0(x) (*(volatile hw_ipu_dc_lla0_t *) HW_IPU_DC_LLA0_ADDR(x))
|
|
#define HW_IPU_DC_LLA0_RD(x) (HW_IPU_DC_LLA0(x).U)
|
|
#define HW_IPU_DC_LLA0_WR(x, v) (HW_IPU_DC_LLA0(x).U = (v))
|
|
#define HW_IPU_DC_LLA0_SET(x, v) (HW_IPU_DC_LLA0_WR(x, HW_IPU_DC_LLA0_RD(x) | (v)))
|
|
#define HW_IPU_DC_LLA0_CLR(x, v) (HW_IPU_DC_LLA0_WR(x, HW_IPU_DC_LLA0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_LLA0_TOG(x, v) (HW_IPU_DC_LLA0_WR(x, HW_IPU_DC_LLA0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_LLA0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_LLA0, field MCU_RS_0_0[7:0] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_0 routine for the display defined at
|
|
* DISP_ID_8, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA0_MCU_RS_0_0 (0) //!< Bit position for IPU_DC_LLA0_MCU_RS_0_0.
|
|
#define BM_IPU_DC_LLA0_MCU_RS_0_0 (0x000000ff) //!< Bit mask for IPU_DC_LLA0_MCU_RS_0_0.
|
|
|
|
//! @brief Get value of IPU_DC_LLA0_MCU_RS_0_0 from a register value.
|
|
#define BG_IPU_DC_LLA0_MCU_RS_0_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA0_MCU_RS_0_0) >> BP_IPU_DC_LLA0_MCU_RS_0_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA0_MCU_RS_0_0.
|
|
#define BF_IPU_DC_LLA0_MCU_RS_0_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA0_MCU_RS_0_0) & BM_IPU_DC_LLA0_MCU_RS_0_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_0_0 field to a new value.
|
|
#define BW_IPU_DC_LLA0_MCU_RS_0_0(x, v) (HW_IPU_DC_LLA0_WR(x, (HW_IPU_DC_LLA0_RD(x) & ~BM_IPU_DC_LLA0_MCU_RS_0_0) | BF_IPU_DC_LLA0_MCU_RS_0_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_LLA0, field MCU_RS_1_0[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_1 routine for the display defined at
|
|
* DISP_ID_8, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA0_MCU_RS_1_0 (8) //!< Bit position for IPU_DC_LLA0_MCU_RS_1_0.
|
|
#define BM_IPU_DC_LLA0_MCU_RS_1_0 (0x0000ff00) //!< Bit mask for IPU_DC_LLA0_MCU_RS_1_0.
|
|
|
|
//! @brief Get value of IPU_DC_LLA0_MCU_RS_1_0 from a register value.
|
|
#define BG_IPU_DC_LLA0_MCU_RS_1_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA0_MCU_RS_1_0) >> BP_IPU_DC_LLA0_MCU_RS_1_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA0_MCU_RS_1_0.
|
|
#define BF_IPU_DC_LLA0_MCU_RS_1_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA0_MCU_RS_1_0) & BM_IPU_DC_LLA0_MCU_RS_1_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_1_0 field to a new value.
|
|
#define BW_IPU_DC_LLA0_MCU_RS_1_0(x, v) (HW_IPU_DC_LLA0_WR(x, (HW_IPU_DC_LLA0_RD(x) & ~BM_IPU_DC_LLA0_MCU_RS_1_0) | BF_IPU_DC_LLA0_MCU_RS_1_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_LLA0, field MCU_RS_2_0[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_2 routine for the display defined at
|
|
* DISP_ID_8, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA0_MCU_RS_2_0 (16) //!< Bit position for IPU_DC_LLA0_MCU_RS_2_0.
|
|
#define BM_IPU_DC_LLA0_MCU_RS_2_0 (0x00ff0000) //!< Bit mask for IPU_DC_LLA0_MCU_RS_2_0.
|
|
|
|
//! @brief Get value of IPU_DC_LLA0_MCU_RS_2_0 from a register value.
|
|
#define BG_IPU_DC_LLA0_MCU_RS_2_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA0_MCU_RS_2_0) >> BP_IPU_DC_LLA0_MCU_RS_2_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA0_MCU_RS_2_0.
|
|
#define BF_IPU_DC_LLA0_MCU_RS_2_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA0_MCU_RS_2_0) & BM_IPU_DC_LLA0_MCU_RS_2_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_2_0 field to a new value.
|
|
#define BW_IPU_DC_LLA0_MCU_RS_2_0(x, v) (HW_IPU_DC_LLA0_WR(x, (HW_IPU_DC_LLA0_RD(x) & ~BM_IPU_DC_LLA0_MCU_RS_2_0) | BF_IPU_DC_LLA0_MCU_RS_2_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_LLA0, field MCU_RS_3_0[31:24] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_3 routine for the display defined at
|
|
* DISP_ID_8, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA0_MCU_RS_3_0 (24) //!< Bit position for IPU_DC_LLA0_MCU_RS_3_0.
|
|
#define BM_IPU_DC_LLA0_MCU_RS_3_0 (0xff000000) //!< Bit mask for IPU_DC_LLA0_MCU_RS_3_0.
|
|
|
|
//! @brief Get value of IPU_DC_LLA0_MCU_RS_3_0 from a register value.
|
|
#define BG_IPU_DC_LLA0_MCU_RS_3_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA0_MCU_RS_3_0) >> BP_IPU_DC_LLA0_MCU_RS_3_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA0_MCU_RS_3_0.
|
|
#define BF_IPU_DC_LLA0_MCU_RS_3_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA0_MCU_RS_3_0) & BM_IPU_DC_LLA0_MCU_RS_3_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_3_0 field to a new value.
|
|
#define BW_IPU_DC_LLA0_MCU_RS_3_0(x, v) (HW_IPU_DC_LLA0_WR(x, (HW_IPU_DC_LLA0_RD(x) & ~BM_IPU_DC_LLA0_MCU_RS_3_0) | BF_IPU_DC_LLA0_MCU_RS_3_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_LLA1 - DC Low Level Access Control Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_LLA1 - DC Low Level Access Control Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_lla1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_lla1_bitfields
|
|
{
|
|
unsigned MCU_RS_0_1 : 8; //!< [7:0] This field holds a pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_9, when in Low level access mode,
|
|
unsigned MCU_RS_1_1 : 8; //!< [15:8] This field holds a pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_9, when in Low level access mode,
|
|
unsigned MCU_RS_2_1 : 8; //!< [23:16] This field holds a pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_9, when in Low level access mode,
|
|
unsigned MCU_RS_3_1 : 8; //!< [31:24] This field holds a pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_9, when in Low level access mode,
|
|
} B;
|
|
} hw_ipu_dc_lla1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_LLA1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_LLA1_ADDR(x) (REGS_IPU_BASE(x) + 0x581b8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_LLA1(x) (*(volatile hw_ipu_dc_lla1_t *) HW_IPU_DC_LLA1_ADDR(x))
|
|
#define HW_IPU_DC_LLA1_RD(x) (HW_IPU_DC_LLA1(x).U)
|
|
#define HW_IPU_DC_LLA1_WR(x, v) (HW_IPU_DC_LLA1(x).U = (v))
|
|
#define HW_IPU_DC_LLA1_SET(x, v) (HW_IPU_DC_LLA1_WR(x, HW_IPU_DC_LLA1_RD(x) | (v)))
|
|
#define HW_IPU_DC_LLA1_CLR(x, v) (HW_IPU_DC_LLA1_WR(x, HW_IPU_DC_LLA1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_LLA1_TOG(x, v) (HW_IPU_DC_LLA1_WR(x, HW_IPU_DC_LLA1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_LLA1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_LLA1, field MCU_RS_0_1[7:0] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_0 routine for the display defined at
|
|
* DISP_ID_9, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA1_MCU_RS_0_1 (0) //!< Bit position for IPU_DC_LLA1_MCU_RS_0_1.
|
|
#define BM_IPU_DC_LLA1_MCU_RS_0_1 (0x000000ff) //!< Bit mask for IPU_DC_LLA1_MCU_RS_0_1.
|
|
|
|
//! @brief Get value of IPU_DC_LLA1_MCU_RS_0_1 from a register value.
|
|
#define BG_IPU_DC_LLA1_MCU_RS_0_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA1_MCU_RS_0_1) >> BP_IPU_DC_LLA1_MCU_RS_0_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA1_MCU_RS_0_1.
|
|
#define BF_IPU_DC_LLA1_MCU_RS_0_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA1_MCU_RS_0_1) & BM_IPU_DC_LLA1_MCU_RS_0_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_0_1 field to a new value.
|
|
#define BW_IPU_DC_LLA1_MCU_RS_0_1(x, v) (HW_IPU_DC_LLA1_WR(x, (HW_IPU_DC_LLA1_RD(x) & ~BM_IPU_DC_LLA1_MCU_RS_0_1) | BF_IPU_DC_LLA1_MCU_RS_0_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_LLA1, field MCU_RS_1_1[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_1 routine for the display defined at
|
|
* DISP_ID_9, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA1_MCU_RS_1_1 (8) //!< Bit position for IPU_DC_LLA1_MCU_RS_1_1.
|
|
#define BM_IPU_DC_LLA1_MCU_RS_1_1 (0x0000ff00) //!< Bit mask for IPU_DC_LLA1_MCU_RS_1_1.
|
|
|
|
//! @brief Get value of IPU_DC_LLA1_MCU_RS_1_1 from a register value.
|
|
#define BG_IPU_DC_LLA1_MCU_RS_1_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA1_MCU_RS_1_1) >> BP_IPU_DC_LLA1_MCU_RS_1_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA1_MCU_RS_1_1.
|
|
#define BF_IPU_DC_LLA1_MCU_RS_1_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA1_MCU_RS_1_1) & BM_IPU_DC_LLA1_MCU_RS_1_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_1_1 field to a new value.
|
|
#define BW_IPU_DC_LLA1_MCU_RS_1_1(x, v) (HW_IPU_DC_LLA1_WR(x, (HW_IPU_DC_LLA1_RD(x) & ~BM_IPU_DC_LLA1_MCU_RS_1_1) | BF_IPU_DC_LLA1_MCU_RS_1_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_LLA1, field MCU_RS_2_1[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_2 routine for the display defined at
|
|
* DISP_ID_9, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA1_MCU_RS_2_1 (16) //!< Bit position for IPU_DC_LLA1_MCU_RS_2_1.
|
|
#define BM_IPU_DC_LLA1_MCU_RS_2_1 (0x00ff0000) //!< Bit mask for IPU_DC_LLA1_MCU_RS_2_1.
|
|
|
|
//! @brief Get value of IPU_DC_LLA1_MCU_RS_2_1 from a register value.
|
|
#define BG_IPU_DC_LLA1_MCU_RS_2_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA1_MCU_RS_2_1) >> BP_IPU_DC_LLA1_MCU_RS_2_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA1_MCU_RS_2_1.
|
|
#define BF_IPU_DC_LLA1_MCU_RS_2_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA1_MCU_RS_2_1) & BM_IPU_DC_LLA1_MCU_RS_2_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_2_1 field to a new value.
|
|
#define BW_IPU_DC_LLA1_MCU_RS_2_1(x, v) (HW_IPU_DC_LLA1_WR(x, (HW_IPU_DC_LLA1_RD(x) & ~BM_IPU_DC_LLA1_MCU_RS_2_1) | BF_IPU_DC_LLA1_MCU_RS_2_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_LLA1, field MCU_RS_3_1[31:24] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_3 routine for the display defined at
|
|
* DISP_ID_9, when in Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_LLA1_MCU_RS_3_1 (24) //!< Bit position for IPU_DC_LLA1_MCU_RS_3_1.
|
|
#define BM_IPU_DC_LLA1_MCU_RS_3_1 (0xff000000) //!< Bit mask for IPU_DC_LLA1_MCU_RS_3_1.
|
|
|
|
//! @brief Get value of IPU_DC_LLA1_MCU_RS_3_1 from a register value.
|
|
#define BG_IPU_DC_LLA1_MCU_RS_3_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_LLA1_MCU_RS_3_1) >> BP_IPU_DC_LLA1_MCU_RS_3_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_LLA1_MCU_RS_3_1.
|
|
#define BF_IPU_DC_LLA1_MCU_RS_3_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_LLA1_MCU_RS_3_1) & BM_IPU_DC_LLA1_MCU_RS_3_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_3_1 field to a new value.
|
|
#define BW_IPU_DC_LLA1_MCU_RS_3_1(x, v) (HW_IPU_DC_LLA1_WR(x, (HW_IPU_DC_LLA1_RD(x) & ~BM_IPU_DC_LLA1_MCU_RS_3_1) | BF_IPU_DC_LLA1_MCU_RS_3_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_R_LLA0 - DC Read Low Level Read Access Control Register 0
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_R_LLA0 - DC Read Low Level Read Access Control Register 0 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_r_lla0
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_r_lla0_bitfields
|
|
{
|
|
unsigned MCU_RS_R_0_0 : 8; //!< [7:0] This field holds a pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_8, when in Read Low level access mode,
|
|
unsigned MCU_RS_R_1_0 : 8; //!< [15:8] This field holds a pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_8, when in Read Low level access mode,
|
|
unsigned MCU_RS_2_0 : 8; //!< [23:16] This field holds a pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_8, when in Read Low level access mode,
|
|
unsigned MCU_RS_3_0 : 8; //!< [31:24] This field holds a pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_8, when in Read Low level access mode,
|
|
} B;
|
|
} hw_ipu_dc_r_lla0_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_R_LLA0 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_R_LLA0_ADDR(x) (REGS_IPU_BASE(x) + 0x581bc)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_R_LLA0(x) (*(volatile hw_ipu_dc_r_lla0_t *) HW_IPU_DC_R_LLA0_ADDR(x))
|
|
#define HW_IPU_DC_R_LLA0_RD(x) (HW_IPU_DC_R_LLA0(x).U)
|
|
#define HW_IPU_DC_R_LLA0_WR(x, v) (HW_IPU_DC_R_LLA0(x).U = (v))
|
|
#define HW_IPU_DC_R_LLA0_SET(x, v) (HW_IPU_DC_R_LLA0_WR(x, HW_IPU_DC_R_LLA0_RD(x) | (v)))
|
|
#define HW_IPU_DC_R_LLA0_CLR(x, v) (HW_IPU_DC_R_LLA0_WR(x, HW_IPU_DC_R_LLA0_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_R_LLA0_TOG(x, v) (HW_IPU_DC_R_LLA0_WR(x, HW_IPU_DC_R_LLA0_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_R_LLA0 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_R_LLA0, field MCU_RS_R_0_0[7:0] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_0 routine for the display defined at
|
|
* DISP_ID_8, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA0_MCU_RS_R_0_0 (0) //!< Bit position for IPU_DC_R_LLA0_MCU_RS_R_0_0.
|
|
#define BM_IPU_DC_R_LLA0_MCU_RS_R_0_0 (0x000000ff) //!< Bit mask for IPU_DC_R_LLA0_MCU_RS_R_0_0.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA0_MCU_RS_R_0_0 from a register value.
|
|
#define BG_IPU_DC_R_LLA0_MCU_RS_R_0_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA0_MCU_RS_R_0_0) >> BP_IPU_DC_R_LLA0_MCU_RS_R_0_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA0_MCU_RS_R_0_0.
|
|
#define BF_IPU_DC_R_LLA0_MCU_RS_R_0_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA0_MCU_RS_R_0_0) & BM_IPU_DC_R_LLA0_MCU_RS_R_0_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_R_0_0 field to a new value.
|
|
#define BW_IPU_DC_R_LLA0_MCU_RS_R_0_0(x, v) (HW_IPU_DC_R_LLA0_WR(x, (HW_IPU_DC_R_LLA0_RD(x) & ~BM_IPU_DC_R_LLA0_MCU_RS_R_0_0) | BF_IPU_DC_R_LLA0_MCU_RS_R_0_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_R_LLA0, field MCU_RS_R_1_0[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_1 routine for the display defined at
|
|
* DISP_ID_8, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA0_MCU_RS_R_1_0 (8) //!< Bit position for IPU_DC_R_LLA0_MCU_RS_R_1_0.
|
|
#define BM_IPU_DC_R_LLA0_MCU_RS_R_1_0 (0x0000ff00) //!< Bit mask for IPU_DC_R_LLA0_MCU_RS_R_1_0.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA0_MCU_RS_R_1_0 from a register value.
|
|
#define BG_IPU_DC_R_LLA0_MCU_RS_R_1_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA0_MCU_RS_R_1_0) >> BP_IPU_DC_R_LLA0_MCU_RS_R_1_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA0_MCU_RS_R_1_0.
|
|
#define BF_IPU_DC_R_LLA0_MCU_RS_R_1_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA0_MCU_RS_R_1_0) & BM_IPU_DC_R_LLA0_MCU_RS_R_1_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_R_1_0 field to a new value.
|
|
#define BW_IPU_DC_R_LLA0_MCU_RS_R_1_0(x, v) (HW_IPU_DC_R_LLA0_WR(x, (HW_IPU_DC_R_LLA0_RD(x) & ~BM_IPU_DC_R_LLA0_MCU_RS_R_1_0) | BF_IPU_DC_R_LLA0_MCU_RS_R_1_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_R_LLA0, field MCU_RS_2_0[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_2 routine for the display defined at
|
|
* DISP_ID_8, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA0_MCU_RS_2_0 (16) //!< Bit position for IPU_DC_R_LLA0_MCU_RS_2_0.
|
|
#define BM_IPU_DC_R_LLA0_MCU_RS_2_0 (0x00ff0000) //!< Bit mask for IPU_DC_R_LLA0_MCU_RS_2_0.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA0_MCU_RS_2_0 from a register value.
|
|
#define BG_IPU_DC_R_LLA0_MCU_RS_2_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA0_MCU_RS_2_0) >> BP_IPU_DC_R_LLA0_MCU_RS_2_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA0_MCU_RS_2_0.
|
|
#define BF_IPU_DC_R_LLA0_MCU_RS_2_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA0_MCU_RS_2_0) & BM_IPU_DC_R_LLA0_MCU_RS_2_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_2_0 field to a new value.
|
|
#define BW_IPU_DC_R_LLA0_MCU_RS_2_0(x, v) (HW_IPU_DC_R_LLA0_WR(x, (HW_IPU_DC_R_LLA0_RD(x) & ~BM_IPU_DC_R_LLA0_MCU_RS_2_0) | BF_IPU_DC_R_LLA0_MCU_RS_2_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_R_LLA0, field MCU_RS_3_0[31:24] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_3 routine for the display defined at
|
|
* DISP_ID_8, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA0_MCU_RS_3_0 (24) //!< Bit position for IPU_DC_R_LLA0_MCU_RS_3_0.
|
|
#define BM_IPU_DC_R_LLA0_MCU_RS_3_0 (0xff000000) //!< Bit mask for IPU_DC_R_LLA0_MCU_RS_3_0.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA0_MCU_RS_3_0 from a register value.
|
|
#define BG_IPU_DC_R_LLA0_MCU_RS_3_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA0_MCU_RS_3_0) >> BP_IPU_DC_R_LLA0_MCU_RS_3_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA0_MCU_RS_3_0.
|
|
#define BF_IPU_DC_R_LLA0_MCU_RS_3_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA0_MCU_RS_3_0) & BM_IPU_DC_R_LLA0_MCU_RS_3_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_3_0 field to a new value.
|
|
#define BW_IPU_DC_R_LLA0_MCU_RS_3_0(x, v) (HW_IPU_DC_R_LLA0_WR(x, (HW_IPU_DC_R_LLA0_RD(x) & ~BM_IPU_DC_R_LLA0_MCU_RS_3_0) | BF_IPU_DC_R_LLA0_MCU_RS_3_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_R_LLA1 - DC Read Low Level Read Access Control Register1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_R_LLA1 - DC Read Low Level Read Access Control Register1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_r_lla1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_r_lla1_bitfields
|
|
{
|
|
unsigned MCU_RS_R_0_1 : 8; //!< [7:0] This field holds a pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_9, when in Read Low level access mode,
|
|
unsigned MCU_RS_R_1_1 : 8; //!< [15:8] This field holds a pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_9, when in Read Low level access mode,
|
|
unsigned MCU_RS_R_2_1 : 8; //!< [23:16] This field holds a pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_9, when in Read Low level access mode,
|
|
unsigned MCU_RS_R_3_1 : 8; //!< [31:24] This field holds a pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_9, when in Read Low level access mode,
|
|
} B;
|
|
} hw_ipu_dc_r_lla1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_R_LLA1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_R_LLA1_ADDR(x) (REGS_IPU_BASE(x) + 0x581c0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_R_LLA1(x) (*(volatile hw_ipu_dc_r_lla1_t *) HW_IPU_DC_R_LLA1_ADDR(x))
|
|
#define HW_IPU_DC_R_LLA1_RD(x) (HW_IPU_DC_R_LLA1(x).U)
|
|
#define HW_IPU_DC_R_LLA1_WR(x, v) (HW_IPU_DC_R_LLA1(x).U = (v))
|
|
#define HW_IPU_DC_R_LLA1_SET(x, v) (HW_IPU_DC_R_LLA1_WR(x, HW_IPU_DC_R_LLA1_RD(x) | (v)))
|
|
#define HW_IPU_DC_R_LLA1_CLR(x, v) (HW_IPU_DC_R_LLA1_WR(x, HW_IPU_DC_R_LLA1_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_R_LLA1_TOG(x, v) (HW_IPU_DC_R_LLA1_WR(x, HW_IPU_DC_R_LLA1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_R_LLA1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_R_LLA1, field MCU_RS_R_0_1[7:0] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_0 routine for the display defined at
|
|
* DISP_ID_9, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA1_MCU_RS_R_0_1 (0) //!< Bit position for IPU_DC_R_LLA1_MCU_RS_R_0_1.
|
|
#define BM_IPU_DC_R_LLA1_MCU_RS_R_0_1 (0x000000ff) //!< Bit mask for IPU_DC_R_LLA1_MCU_RS_R_0_1.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA1_MCU_RS_R_0_1 from a register value.
|
|
#define BG_IPU_DC_R_LLA1_MCU_RS_R_0_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA1_MCU_RS_R_0_1) >> BP_IPU_DC_R_LLA1_MCU_RS_R_0_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA1_MCU_RS_R_0_1.
|
|
#define BF_IPU_DC_R_LLA1_MCU_RS_R_0_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA1_MCU_RS_R_0_1) & BM_IPU_DC_R_LLA1_MCU_RS_R_0_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_R_0_1 field to a new value.
|
|
#define BW_IPU_DC_R_LLA1_MCU_RS_R_0_1(x, v) (HW_IPU_DC_R_LLA1_WR(x, (HW_IPU_DC_R_LLA1_RD(x) & ~BM_IPU_DC_R_LLA1_MCU_RS_R_0_1) | BF_IPU_DC_R_LLA1_MCU_RS_R_0_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_R_LLA1, field MCU_RS_R_1_1[15:8] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_1 routine for the display defined at
|
|
* DISP_ID_9, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA1_MCU_RS_R_1_1 (8) //!< Bit position for IPU_DC_R_LLA1_MCU_RS_R_1_1.
|
|
#define BM_IPU_DC_R_LLA1_MCU_RS_R_1_1 (0x0000ff00) //!< Bit mask for IPU_DC_R_LLA1_MCU_RS_R_1_1.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA1_MCU_RS_R_1_1 from a register value.
|
|
#define BG_IPU_DC_R_LLA1_MCU_RS_R_1_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA1_MCU_RS_R_1_1) >> BP_IPU_DC_R_LLA1_MCU_RS_R_1_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA1_MCU_RS_R_1_1.
|
|
#define BF_IPU_DC_R_LLA1_MCU_RS_R_1_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA1_MCU_RS_R_1_1) & BM_IPU_DC_R_LLA1_MCU_RS_R_1_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_R_1_1 field to a new value.
|
|
#define BW_IPU_DC_R_LLA1_MCU_RS_R_1_1(x, v) (HW_IPU_DC_R_LLA1_WR(x, (HW_IPU_DC_R_LLA1_RD(x) & ~BM_IPU_DC_R_LLA1_MCU_RS_R_1_1) | BF_IPU_DC_R_LLA1_MCU_RS_R_1_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_R_LLA1, field MCU_RS_R_2_1[23:16] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_2 routine for the display defined at
|
|
* DISP_ID_9, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA1_MCU_RS_R_2_1 (16) //!< Bit position for IPU_DC_R_LLA1_MCU_RS_R_2_1.
|
|
#define BM_IPU_DC_R_LLA1_MCU_RS_R_2_1 (0x00ff0000) //!< Bit mask for IPU_DC_R_LLA1_MCU_RS_R_2_1.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA1_MCU_RS_R_2_1 from a register value.
|
|
#define BG_IPU_DC_R_LLA1_MCU_RS_R_2_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA1_MCU_RS_R_2_1) >> BP_IPU_DC_R_LLA1_MCU_RS_R_2_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA1_MCU_RS_R_2_1.
|
|
#define BF_IPU_DC_R_LLA1_MCU_RS_R_2_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA1_MCU_RS_R_2_1) & BM_IPU_DC_R_LLA1_MCU_RS_R_2_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_R_2_1 field to a new value.
|
|
#define BW_IPU_DC_R_LLA1_MCU_RS_R_2_1(x, v) (HW_IPU_DC_R_LLA1_WR(x, (HW_IPU_DC_R_LLA1_RD(x) & ~BM_IPU_DC_R_LLA1_MCU_RS_R_2_1) | BF_IPU_DC_R_LLA1_MCU_RS_R_2_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_R_LLA1, field MCU_RS_R_3_1[31:24] (RW)
|
|
*
|
|
* This field holds a pointer in the microcode handling the RS_3 routine for the display defined at
|
|
* DISP_ID_9, when in Read Low level access mode,
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_R_LLA1_MCU_RS_R_3_1 (24) //!< Bit position for IPU_DC_R_LLA1_MCU_RS_R_3_1.
|
|
#define BM_IPU_DC_R_LLA1_MCU_RS_R_3_1 (0xff000000) //!< Bit mask for IPU_DC_R_LLA1_MCU_RS_R_3_1.
|
|
|
|
//! @brief Get value of IPU_DC_R_LLA1_MCU_RS_R_3_1 from a register value.
|
|
#define BG_IPU_DC_R_LLA1_MCU_RS_R_3_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_R_LLA1_MCU_RS_R_3_1) >> BP_IPU_DC_R_LLA1_MCU_RS_R_3_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_R_LLA1_MCU_RS_R_3_1.
|
|
#define BF_IPU_DC_R_LLA1_MCU_RS_R_3_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_R_LLA1_MCU_RS_R_3_1) & BM_IPU_DC_R_LLA1_MCU_RS_R_3_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the MCU_RS_R_3_1 field to a new value.
|
|
#define BW_IPU_DC_R_LLA1_MCU_RS_R_3_1(x, v) (HW_IPU_DC_R_LLA1_WR(x, (HW_IPU_DC_R_LLA1_RD(x) & ~BM_IPU_DC_R_LLA1_MCU_RS_R_3_1) | BF_IPU_DC_R_LLA1_MCU_RS_R_3_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_WR_CH_ADDR_5_ALT - DC Write Channel 5 Configuration Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_WR_CH_ADDR_5_ALT - DC Write Channel 5 Configuration Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dc_wr_ch_addr_5_alt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_wr_ch_addr_5_alt_bitfields
|
|
{
|
|
unsigned ST_ADDR_5_ALT : 29; //!< [28:0] This field defines the start address within the display's memory space where the write transactions will be done to for channel #5, when alternate flow is performed via channel #5
|
|
unsigned RESERVED0 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_wr_ch_addr_5_alt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_WR_CH_ADDR_5_ALT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x581c4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT(x) (*(volatile hw_ipu_dc_wr_ch_addr_5_alt_t *) HW_IPU_DC_WR_CH_ADDR_5_ALT_ADDR(x))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT_RD(x) (HW_IPU_DC_WR_CH_ADDR_5_ALT(x).U)
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT_WR(x, v) (HW_IPU_DC_WR_CH_ADDR_5_ALT(x).U = (v))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT_SET(x, v) (HW_IPU_DC_WR_CH_ADDR_5_ALT_WR(x, HW_IPU_DC_WR_CH_ADDR_5_ALT_RD(x) | (v)))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT_CLR(x, v) (HW_IPU_DC_WR_CH_ADDR_5_ALT_WR(x, HW_IPU_DC_WR_CH_ADDR_5_ALT_RD(x) & ~(v)))
|
|
#define HW_IPU_DC_WR_CH_ADDR_5_ALT_TOG(x, v) (HW_IPU_DC_WR_CH_ADDR_5_ALT_WR(x, HW_IPU_DC_WR_CH_ADDR_5_ALT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_WR_CH_ADDR_5_ALT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_WR_CH_ADDR_5_ALT, field ST_ADDR_5_ALT[28:0] (RW)
|
|
*
|
|
* This field defines the start address within the display's memory space where the write
|
|
* transactions will be done to for channel #5, when alternate flow is performed via channel #5
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT (0) //!< Bit position for IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT.
|
|
#define BM_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT (0x1fffffff) //!< Bit mask for IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT.
|
|
|
|
//! @brief Get value of IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT from a register value.
|
|
#define BG_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT) >> BP_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT.
|
|
#define BF_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT) & BM_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ST_ADDR_5_ALT field to a new value.
|
|
#define BW_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT(x, v) (HW_IPU_DC_WR_CH_ADDR_5_ALT_WR(x, (HW_IPU_DC_WR_CH_ADDR_5_ALT_RD(x) & ~BM_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT) | BF_IPU_DC_WR_CH_ADDR_5_ALT_ST_ADDR_5_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DC_STAT - DC Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DC_STAT - DC Status Register (RO)
|
|
*
|
|
* Reset value: 0x000000aa
|
|
*/
|
|
typedef union _hw_ipu_dc_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dc_stat_bitfields
|
|
{
|
|
unsigned DC_TRIPLE_BUF_CNT_FULL_0 : 1; //!< [0] This bit indicates a FIFO full state on the DC FIFO accessing DI0 when write to the display flow is used
|
|
unsigned DC_TRIPLE_BUF_CNT_EMPTY_0 : 1; //!< [1] This bit indicates a FIFO empty state on the DC FIFO accessing DI0 when write to the display flow is used
|
|
unsigned DC_TRIPLE_BUF_DATA_FULL_0 : 1; //!< [2] This bit indicates a FIFO full state on the DC FIFO accessing DI0 when read from the display flow is used
|
|
unsigned DC_TRIPLE_BUF_DATA_EMPTY_0 : 1; //!< [3] This bit indicates a FIFO empty state on the DC FIFO accessing DI0 when read from the display flow is used
|
|
unsigned DC_TRIPLE_BUF_CNT_FULL_1 : 1; //!< [4] This bit indicates a FIFO full state on the DC FIFO accessing DI1 when write to the display flow is used
|
|
unsigned DC_TRIPLE_BUF_CNT_EMPTY_1 : 1; //!< [5] This bit indicates a FIFO empty state on the DC FIFO accessing DI1 when write to the display flow is used
|
|
unsigned DC_TRIPLE_BUF_DATA_FULL_1 : 1; //!< [6] This bit indicates a FIFO empty state on the DC FIFO accessing DI1 when read from the display flow is used
|
|
unsigned DC_TRIPLE_BUF_DATA_EMPTY_1 : 1; //!< [7] This bit indicates a FIFO full state on the DC FIFO accessing DI1 when write to the display flow is used
|
|
unsigned RESERVED0 : 24; //!< [31:8] Reserved.
|
|
} B;
|
|
} hw_ipu_dc_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DC_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DC_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x581c8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DC_STAT(x) (*(volatile hw_ipu_dc_stat_t *) HW_IPU_DC_STAT_ADDR(x))
|
|
#define HW_IPU_DC_STAT_RD(x) (HW_IPU_DC_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DC_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_CNT_FULL_0[0] (RO)
|
|
*
|
|
* This bit indicates a FIFO full state on the DC FIFO accessing DI0 when write to the display flow
|
|
* is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0 (0) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0 (0x00000001) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_CNT_EMPTY_0[1] (RO)
|
|
*
|
|
* This bit indicates a FIFO empty state on the DC FIFO accessing DI0 when write to the display flow
|
|
* is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0 (1) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0 (0x00000002) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_DATA_FULL_0[2] (RO)
|
|
*
|
|
* This bit indicates a FIFO full state on the DC FIFO accessing DI0 when read from the display flow
|
|
* is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0 (2) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0 (0x00000004) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_DATA_EMPTY_0[3] (RO)
|
|
*
|
|
* This bit indicates a FIFO empty state on the DC FIFO accessing DI0 when read from the display
|
|
* flow is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0 (3) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0 (0x00000008) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_0)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_CNT_FULL_1[4] (RO)
|
|
*
|
|
* This bit indicates a FIFO full state on the DC FIFO accessing DI1 when write to the display flow
|
|
* is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1 (4) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1 (0x00000010) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_FULL_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_CNT_EMPTY_1[5] (RO)
|
|
*
|
|
* This bit indicates a FIFO empty state on the DC FIFO accessing DI1 when write to the display flow
|
|
* is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1 (5) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1 (0x00000020) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_CNT_EMPTY_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_DATA_FULL_1[6] (RO)
|
|
*
|
|
* This bit indicates a FIFO empty state on the DC FIFO accessing DI1 when read from the display
|
|
* flow is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1 (6) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1 (0x00000040) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_FULL_1)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DC_STAT, field DC_TRIPLE_BUF_DATA_EMPTY_1[7] (RO)
|
|
*
|
|
* This bit indicates a FIFO full state on the DC FIFO accessing DI1 when write to the display flow
|
|
* is used
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1 (7) //!< Bit position for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1.
|
|
#define BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1 (0x00000080) //!< Bit mask for IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1.
|
|
|
|
//! @brief Get value of IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1 from a register value.
|
|
#define BG_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1) >> BP_IPU_DC_STAT_DC_TRIPLE_BUF_DATA_EMPTY_1)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_RD_CHAN - DMFC Read Channel Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_RD_CHAN - DMFC Read Channel Register (RW)
|
|
*
|
|
* Reset value: 0x00000200
|
|
*/
|
|
typedef union _hw_ipu_dmfc_rd_chan
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_rd_chan_bitfields
|
|
{
|
|
unsigned RESERVED0 : 6; //!< [5:0] Reserved.
|
|
unsigned DMFC_BURST_SIZE_0 : 2; //!< [7:6] Read burst Size
|
|
unsigned RESERVED1 : 9; //!< [16:8] Reserved.
|
|
unsigned DMFC_WM_EN_0 : 1; //!< [17] Watermark enable.
|
|
unsigned DMFC_WM_SET_0 : 3; //!< [20:18] Watermark Set
|
|
unsigned DMFC_WM_CLR_0 : 3; //!< [23:21] Watermark Clear
|
|
unsigned DMFC_PPW_C : 2; //!< [25:24] Pixel Per Word coded.
|
|
unsigned RESERVED2 : 6; //!< [31:26] Reserved.
|
|
} B;
|
|
} hw_ipu_dmfc_rd_chan_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_RD_CHAN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_RD_CHAN_ADDR(x) (REGS_IPU_BASE(x) + 0x60000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_RD_CHAN(x) (*(volatile hw_ipu_dmfc_rd_chan_t *) HW_IPU_DMFC_RD_CHAN_ADDR(x))
|
|
#define HW_IPU_DMFC_RD_CHAN_RD(x) (HW_IPU_DMFC_RD_CHAN(x).U)
|
|
#define HW_IPU_DMFC_RD_CHAN_WR(x, v) (HW_IPU_DMFC_RD_CHAN(x).U = (v))
|
|
#define HW_IPU_DMFC_RD_CHAN_SET(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, HW_IPU_DMFC_RD_CHAN_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_RD_CHAN_CLR(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, HW_IPU_DMFC_RD_CHAN_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_RD_CHAN_TOG(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, HW_IPU_DMFC_RD_CHAN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_RD_CHAN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_RD_CHAN, field DMFC_BURST_SIZE_0[7:6] (RW)
|
|
*
|
|
* Read burst Size This field defines the burst size of the DMFC's read accesses. This settings must
|
|
* match the settings in the corresponding IDMAC channel's settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, going to the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0 (6) //!< Bit position for IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0.
|
|
#define BM_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0 (0x000000c0) //!< Bit mask for IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0.
|
|
|
|
//! @brief Get value of IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0 from a register value.
|
|
#define BG_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0) >> BP_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0.
|
|
#define BF_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0) & BM_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_0 field to a new value.
|
|
#define BW_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, (HW_IPU_DMFC_RD_CHAN_RD(x) & ~BM_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0) | BF_IPU_DMFC_RD_CHAN_DMFC_BURST_SIZE_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_RD_CHAN, field DMFC_WM_EN_0[17] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0 (17) //!< Bit position for IPU_DMFC_RD_CHAN_DMFC_WM_EN_0.
|
|
#define BM_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0 (0x00020000) //!< Bit mask for IPU_DMFC_RD_CHAN_DMFC_WM_EN_0.
|
|
|
|
//! @brief Get value of IPU_DMFC_RD_CHAN_DMFC_WM_EN_0 from a register value.
|
|
#define BG_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0) >> BP_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_RD_CHAN_DMFC_WM_EN_0.
|
|
#define BF_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0) & BM_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_0 field to a new value.
|
|
#define BW_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, (HW_IPU_DMFC_RD_CHAN_RD(x) & ~BM_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0) | BF_IPU_DMFC_RD_CHAN_DMFC_WM_EN_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_RD_CHAN, field DMFC_WM_SET_0[20:18] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC read FIFO. Crossing this level
|
|
* will send the watermark signal to the IDMAC. The WM level is the amount of free bursts at the
|
|
* FIFO (dmfc_wm_clr_0 > dmfc_wm_set_0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0 (18) //!< Bit position for IPU_DMFC_RD_CHAN_DMFC_WM_SET_0.
|
|
#define BM_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0 (0x001c0000) //!< Bit mask for IPU_DMFC_RD_CHAN_DMFC_WM_SET_0.
|
|
|
|
//! @brief Get value of IPU_DMFC_RD_CHAN_DMFC_WM_SET_0 from a register value.
|
|
#define BG_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0) >> BP_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_RD_CHAN_DMFC_WM_SET_0.
|
|
#define BF_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0) & BM_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_0 field to a new value.
|
|
#define BW_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, (HW_IPU_DMFC_RD_CHAN_RD(x) & ~BM_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0) | BF_IPU_DMFC_RD_CHAN_DMFC_WM_SET_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_RD_CHAN, field DMFC_WM_CLR_0[23:21] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC read FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of free bursts at
|
|
* the FIFO (dmfc_wm_clr_0 > dmfc_wm_set_0)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0 (21) //!< Bit position for IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0.
|
|
#define BM_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0 (0x00e00000) //!< Bit mask for IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0.
|
|
|
|
//! @brief Get value of IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0 from a register value.
|
|
#define BG_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0) >> BP_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0.
|
|
#define BF_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0) & BM_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_0 field to a new value.
|
|
#define BW_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, (HW_IPU_DMFC_RD_CHAN_RD(x) & ~BM_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0) | BF_IPU_DMFC_RD_CHAN_DMFC_WM_CLR_0(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_RD_CHAN, field DMFC_PPW_C[25:24] (RW)
|
|
*
|
|
* Pixel Per Word coded. This field defines the size of the read data from the display.
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bit per pixel
|
|
* - 01 - 16 bit per pixel
|
|
* - 10 - 24 (rgb) bit per pixel or 32 bit per pixel
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_RD_CHAN_DMFC_PPW_C (24) //!< Bit position for IPU_DMFC_RD_CHAN_DMFC_PPW_C.
|
|
#define BM_IPU_DMFC_RD_CHAN_DMFC_PPW_C (0x03000000) //!< Bit mask for IPU_DMFC_RD_CHAN_DMFC_PPW_C.
|
|
|
|
//! @brief Get value of IPU_DMFC_RD_CHAN_DMFC_PPW_C from a register value.
|
|
#define BG_IPU_DMFC_RD_CHAN_DMFC_PPW_C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_RD_CHAN_DMFC_PPW_C) >> BP_IPU_DMFC_RD_CHAN_DMFC_PPW_C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_RD_CHAN_DMFC_PPW_C.
|
|
#define BF_IPU_DMFC_RD_CHAN_DMFC_PPW_C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_RD_CHAN_DMFC_PPW_C) & BM_IPU_DMFC_RD_CHAN_DMFC_PPW_C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_PPW_C field to a new value.
|
|
#define BW_IPU_DMFC_RD_CHAN_DMFC_PPW_C(x, v) (HW_IPU_DMFC_RD_CHAN_WR(x, (HW_IPU_DMFC_RD_CHAN_RD(x) & ~BM_IPU_DMFC_RD_CHAN_DMFC_PPW_C) | BF_IPU_DMFC_RD_CHAN_DMFC_PPW_C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_WR_CHAN - DMFC Write Channel Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_WR_CHAN - DMFC Write Channel Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_wr_chan
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_wr_chan_bitfields
|
|
{
|
|
unsigned DMFC_ST_ADDR_1 : 3; //!< [2:0] DMFC Start Address for IDMAC's channel 28
|
|
unsigned DMFC_FIFO_SIZE_1 : 3; //!< [5:3] DMFC FIFO size for IDMAC's channel 28
|
|
unsigned DMFC_BURST_SIZE_1 : 2; //!< [7:6] Burst size of IDMAC's channel 28
|
|
unsigned DMFC_ST_ADDR_2 : 3; //!< [10:8] DMFC Start Address for IDMAC's channel 41
|
|
unsigned DMFC_FIFO_SIZE_2 : 3; //!< [13:11] DMFC FIFO size for IDMAC's channel 41
|
|
unsigned DMFC_BURST_SIZE_2 : 2; //!< [15:14] Burst size of IDMAC's channel 41
|
|
unsigned DMFC_ST_ADDR_1C : 3; //!< [18:16] DMFC Start Address for IDMAC's channel 42
|
|
unsigned DMFC_FIFO_SIZE_1C : 3; //!< [21:19] DMFC FIFO size for IDMAC's channel 42
|
|
unsigned DMFC_BURST_SIZE_1C : 2; //!< [23:22] Burst size of IDMAC's channel 42
|
|
unsigned DMFC_ST_ADDR_2C : 3; //!< [26:24] DMFC Start Address for IDMAC's channel 43
|
|
unsigned DMFC_FIFO_SIZE_2C : 3; //!< [29:27] DMFC FIFO size for IDMAC's channel 43
|
|
unsigned DMFC_BURST_SIZE_2C : 2; //!< [31:30] Burst size of IDMAC's channel 43
|
|
} B;
|
|
} hw_ipu_dmfc_wr_chan_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_WR_CHAN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_WR_CHAN_ADDR(x) (REGS_IPU_BASE(x) + 0x60004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_WR_CHAN(x) (*(volatile hw_ipu_dmfc_wr_chan_t *) HW_IPU_DMFC_WR_CHAN_ADDR(x))
|
|
#define HW_IPU_DMFC_WR_CHAN_RD(x) (HW_IPU_DMFC_WR_CHAN(x).U)
|
|
#define HW_IPU_DMFC_WR_CHAN_WR(x, v) (HW_IPU_DMFC_WR_CHAN(x).U = (v))
|
|
#define HW_IPU_DMFC_WR_CHAN_SET(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, HW_IPU_DMFC_WR_CHAN_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_CLR(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, HW_IPU_DMFC_WR_CHAN_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_TOG(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, HW_IPU_DMFC_WR_CHAN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_WR_CHAN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_ST_ADDR_1[2:0] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 28 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 28. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1 (0) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1 (0x00000007) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1) >> BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_1 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1) | BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_FIFO_SIZE_1[5:3] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 28 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 28
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1 (3) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1 (0x00000038) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1) >> BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_1 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1) | BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_BURST_SIZE_1[7:6] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 28 This field defines the burst size of the IDMAC's channel 28
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 1hbit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1 (6) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1 (0x000000c0) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1) >> BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_1 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1) | BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_ST_ADDR_2[10:8] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 41 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 41. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2 (8) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2 (0x00000700) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2) >> BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_2 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2) | BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_FIFO_SIZE_2[13:11] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 41 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 41
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2 (11) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2 (0x00003800) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2) >> BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_2 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2) | BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_BURST_SIZE_2[15:14] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 41 This field defines the burst size of the IDMAC's channel 41
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2 (14) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2 (0x0000c000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2) >> BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_2 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2) | BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_ST_ADDR_1C[18:16] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 42 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 42. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C (16) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C (0x00070000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C) >> BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_1C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C) | BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_1C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_FIFO_SIZE_1C[21:19] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 42 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 42
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C (19) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C (0x00380000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C) >> BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_1C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C) | BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_1C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_BURST_SIZE_1C[23:22] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 42 This field defines the burst size of the IDMAC's channel 42
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C (22) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C (0x00c00000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C) >> BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_1C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C) | BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_1C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_ST_ADDR_2C[26:24] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 43 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 43. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C (24) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C (0x07000000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C) >> BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C) & BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_2C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C) | BF_IPU_DMFC_WR_CHAN_DMFC_ST_ADDR_2C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_FIFO_SIZE_2C[29:27] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 43 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 43
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C (27) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C (0x38000000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C) >> BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C) & BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_2C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C) | BF_IPU_DMFC_WR_CHAN_DMFC_FIFO_SIZE_2C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN, field DMFC_BURST_SIZE_2C[31:30] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 43 This field defines the burst size of the IDMAC's channel 43
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C (30) //!< Bit position for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C.
|
|
#define BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C (0xc0000000) //!< Bit mask for IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C) >> BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C) & BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_2C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C(x, v) (HW_IPU_DMFC_WR_CHAN_WR(x, (HW_IPU_DMFC_WR_CHAN_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C) | BF_IPU_DMFC_WR_CHAN_DMFC_BURST_SIZE_2C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_WR_CHAN_DEF - DMFC Write Channel Definition Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_WR_CHAN_DEF - DMFC Write Channel Definition Register (RW)
|
|
*
|
|
* Reset value: 0x20202020
|
|
*/
|
|
typedef union _hw_ipu_dmfc_wr_chan_def
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_wr_chan_def_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved
|
|
unsigned DMFC_WM_EN_1 : 1; //!< [1] Watermark enable.
|
|
unsigned DMFC_WM_SET_1 : 3; //!< [4:2] Watermark Set
|
|
unsigned DMFC_WM_CLR_1 : 3; //!< [7:5] Watermark Clear
|
|
unsigned RESERVED1 : 1; //!< [8] Reserved
|
|
unsigned DMFC_WM_EN_2 : 1; //!< [9] Watermark enable.
|
|
unsigned DMFC_WM_SET_2 : 3; //!< [12:10] Watermark Set
|
|
unsigned DMFC_WM_CLR_2 : 3; //!< [15:13] Watermark Clear
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved
|
|
unsigned DMFC_WM_EN_1C : 1; //!< [17] Watermark enable.
|
|
unsigned DMFC_WM_SET_1C : 3; //!< [20:18] Watermark Set
|
|
unsigned DMFC_WM_CLR_1C : 3; //!< [23:21] Watermark Clear
|
|
unsigned RESERVED3 : 1; //!< [24] Reserved
|
|
unsigned DMFC_WM_EN_2C : 1; //!< [25] Watermark enable.
|
|
unsigned DMFC_WM_SET_2C : 3; //!< [28:26] Watermark Set
|
|
unsigned DMFC_WM_CLR_2C : 3; //!< [31:29] Watermark Clear
|
|
} B;
|
|
} hw_ipu_dmfc_wr_chan_def_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_WR_CHAN_DEF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ADDR(x) (REGS_IPU_BASE(x) + 0x60008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF(x) (*(volatile hw_ipu_dmfc_wr_chan_def_t *) HW_IPU_DMFC_WR_CHAN_DEF_ADDR(x))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_RD(x) (HW_IPU_DMFC_WR_CHAN_DEF(x).U)
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_WR(x, v) (HW_IPU_DMFC_WR_CHAN_DEF(x).U = (v))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_SET(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, HW_IPU_DMFC_WR_CHAN_DEF_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_CLR(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_TOG(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, HW_IPU_DMFC_WR_CHAN_DEF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_WR_CHAN_DEF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_EN_1[1] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1 (1) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1.
|
|
#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1 (0x00000002) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_1 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_SET_1[4:2] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1 (2) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1.
|
|
#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1 (0x0000001c) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_1 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_CLR_1[7:5] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1 (5) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1.
|
|
#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1 (0x000000e0) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1 from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_1 field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_EN_2[9] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
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#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2 (9) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2 (0x00000200) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2 from a register value.
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#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2.
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#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_EN_2 field to a new value.
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#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_SET_2[12:10] (RW)
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*
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* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
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* at the FIFO (dmfc_wm_clr > dmfc_wm_set
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*/
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//@{
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#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2 (10) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2 (0x00001c00) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2 from a register value.
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#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2.
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#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_SET_2 field to a new value.
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#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_CLR_2[15:13] (RW)
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*
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* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
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* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
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* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
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*/
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//@{
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#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2 (13) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2 (0x0000e000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2 from a register value.
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#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2.
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#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_CLR_2 field to a new value.
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#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_EN_1C[17] (RW)
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*
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|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
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|
*/
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//@{
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#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C (17) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C (0x00020000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C from a register value.
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#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C.
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#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DMFC_WM_EN_1C field to a new value.
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|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_1C(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_SET_1C[20:18] (RW)
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*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
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|
*/
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|
//@{
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|
#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C (18) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C (0x001c0000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C from a register value.
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|
#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C.
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|
#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_SET_1C field to a new value.
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|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_1C(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_CLR_1C[23:21] (RW)
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*
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* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
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*/
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//@{
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#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C (21) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C (0x00e00000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C from a register value.
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#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C.
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#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_CLR_1C field to a new value.
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#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_1C(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_EN_2C[25] (RW)
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|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
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|
* - 1 - WM feature is enabled
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*/
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//@{
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#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C (25) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C (0x02000000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C from a register value.
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#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C)
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//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C.
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#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C)
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|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_2C field to a new value.
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|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_EN_2C(v)))
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#endif
|
|
//@}
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/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_SET_2C[28:26] (RW)
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|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
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|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C (26) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C.
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#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C (0x1c000000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C.
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//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C)
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|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_2C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_SET_2C(v)))
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|
#endif
|
|
//@}
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|
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|
/*! @name Register IPU_DMFC_WR_CHAN_DEF, field DMFC_WM_CLR_2C[31:29] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C (29) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C.
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|
#define BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C (0xe0000000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C.
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|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C) >> BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C) & BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_2C field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C) | BF_IPU_DMFC_WR_CHAN_DEF_DMFC_WM_CLR_2C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_DP_CHAN - DMFC Display Processor Channel Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_DP_CHAN - DMFC Display Processor Channel Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_dp_chan
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_dp_chan_bitfields
|
|
{
|
|
unsigned DMFC_ST_ADDR_5B : 3; //!< [2:0] DMFC Start Address for IDMAC's channel 23
|
|
unsigned DMFC_FIFO_SIZE_5B : 3; //!< [5:3] DMFC FIFO size for IDMAC's channel 23
|
|
unsigned DMFC_BURST_SIZE_5B : 2; //!< [7:6] Burst size of IDMAC's channel 23
|
|
unsigned DMFC_ST_ADDR_5F : 3; //!< [10:8] DMFC Start Address for IDMAC's channel 27
|
|
unsigned DMFC_FIFO_SIZE_5F : 3; //!< [13:11] DMFC FIFO size for IDMAC's channel 27
|
|
unsigned DMFC_BURST_SIZE_5F : 2; //!< [15:14] Burst size of IDMAC's channel 27
|
|
unsigned DMFC_ST_ADDR_6B : 3; //!< [18:16] DMFC Start Address for IDMAC's channel 24
|
|
unsigned DMFC_FIFO_SIZE_6B : 3; //!< [21:19] DMFC FIFO size for IDMAC's channel 24
|
|
unsigned DMFC_BURST_SIZE_6B : 2; //!< [23:22] Burst size of IDMAC's channel 24
|
|
unsigned DMFC_ST_ADDR_6F : 3; //!< [26:24] DMFC Start Address for IDMAC's channel 29
|
|
unsigned DMFC_FIFO_SIZE_6F : 3; //!< [29:27] DMFC FIFO size for IDMAC's channel 29
|
|
unsigned DMFC_BURST_SIZE_6F : 2; //!< [31:30] Burst size of IDMAC's channel 29
|
|
} B;
|
|
} hw_ipu_dmfc_dp_chan_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_DP_CHAN register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_DP_CHAN_ADDR(x) (REGS_IPU_BASE(x) + 0x6000c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_DP_CHAN(x) (*(volatile hw_ipu_dmfc_dp_chan_t *) HW_IPU_DMFC_DP_CHAN_ADDR(x))
|
|
#define HW_IPU_DMFC_DP_CHAN_RD(x) (HW_IPU_DMFC_DP_CHAN(x).U)
|
|
#define HW_IPU_DMFC_DP_CHAN_WR(x, v) (HW_IPU_DMFC_DP_CHAN(x).U = (v))
|
|
#define HW_IPU_DMFC_DP_CHAN_SET(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, HW_IPU_DMFC_DP_CHAN_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_DP_CHAN_CLR(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, HW_IPU_DMFC_DP_CHAN_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_DP_CHAN_TOG(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, HW_IPU_DMFC_DP_CHAN_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_DP_CHAN bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_ST_ADDR_5B[2:0] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 23 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 23. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B (0) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B (0x00000007) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B) >> BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_5B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B) | BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_FIFO_SIZE_5B[5:3] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 23 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 23
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B (3) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B (0x00000038) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B) >> BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_5B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B) | BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_BURST_SIZE_5B[7:6] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 23 This field defines the burst size of the IDMAC's channel 23
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B (6) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B (0x000000c0) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B) >> BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_5B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B) | BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_ST_ADDR_5F[10:8] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 27 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 27. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F (8) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F (0x00000700) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F) >> BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_5F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F) | BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_FIFO_SIZE_5F[13:11] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 27 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 27
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F (11) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F (0x00003800) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F) >> BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_5F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F) | BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_BURST_SIZE_5F[15:14] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 27 This field defines the burst size of the IDMAC's channel 27
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F (14) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F (0x0000c000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F) >> BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_5F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F) | BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_ST_ADDR_6B[18:16] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 24 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 24. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B (16) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B (0x00070000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B) >> BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_6B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B) | BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_FIFO_SIZE_6B[21:19] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 24 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 24
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B (19) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B (0x00380000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B) >> BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_6B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B) | BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_BURST_SIZE_6B[23:22] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 24 This field defines the burst size of the IDMAC's channel 24
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B (22) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B (0x00c00000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B) >> BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_6B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B) | BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_ST_ADDR_6F[26:24] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 29 This field defines the base address at the DMFC's FIFO
|
|
* of the partition allocated to the channel connected to IDMAC's channel 29. The FIFO is
|
|
* partitioned to 8 equal segments. Each segment is 64X128 words The value of this field is the
|
|
* number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F (24) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F (0x07000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F) >> BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F) & BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_6F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F) | BF_IPU_DMFC_DP_CHAN_DMFC_ST_ADDR_6F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_FIFO_SIZE_6F[29:27] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 29 This field defines the FIFO partition for the DMFC channel
|
|
* connected to IDMAC's channel 29
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F (27) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F (0x38000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F) >> BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F) & BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_6F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F) | BF_IPU_DMFC_DP_CHAN_DMFC_FIFO_SIZE_6F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN, field DMFC_BURST_SIZE_6F[31:30] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 29 This field defines the burst size of the IDMAC's channel 29
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F (30) //!< Bit position for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F (0xc0000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F) >> BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F) & BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_6F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F(x, v) (HW_IPU_DMFC_DP_CHAN_WR(x, (HW_IPU_DMFC_DP_CHAN_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F) | BF_IPU_DMFC_DP_CHAN_DMFC_BURST_SIZE_6F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_DP_CHAN_DEF - DMFC Display Processor Channel Definition Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_DP_CHAN_DEF - DMFC Display Processor Channel Definition Register (RW)
|
|
*
|
|
* Reset value: 0x20202020
|
|
*/
|
|
typedef union _hw_ipu_dmfc_dp_chan_def
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_dp_chan_def_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved
|
|
unsigned DMFC_WM_EN_5B : 1; //!< [1] Watermark enable.
|
|
unsigned DMFC_WM_SET_5B : 3; //!< [4:2] Watermark Set
|
|
unsigned DMFC_WM_CLR_5B : 3; //!< [7:5] Watermark Clear
|
|
unsigned RESERVED1 : 1; //!< [8] Reserved
|
|
unsigned DMFC_WM_EN_5F : 1; //!< [9] Watermark enable.
|
|
unsigned DMFC_WM_SET_5F : 3; //!< [12:10] Watermark Set
|
|
unsigned DMFC_WM_CLR_5F : 3; //!< [15:13] Watermark Clear
|
|
unsigned RESERVED2 : 1; //!< [16] Reserved
|
|
unsigned DMFC_WM_EN_6B : 1; //!< [17] Watermark enable.
|
|
unsigned DMFC_WM_SET_6B : 3; //!< [20:18] Watermark Set
|
|
unsigned DMFC_WM_CLR_6B : 3; //!< [23:21] Watermark Clear
|
|
unsigned RESERVED3 : 1; //!< [24] Reserved
|
|
unsigned DMFC_WM_EN_6F : 1; //!< [25] Watermark enable.
|
|
unsigned DMFC_WM_SET_6F : 3; //!< [28:26] Watermark Set
|
|
unsigned DMFC_WM_CLR_6F : 3; //!< [31:29] Watermark Clear
|
|
} B;
|
|
} hw_ipu_dmfc_dp_chan_def_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_DP_CHAN_DEF register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF_ADDR(x) (REGS_IPU_BASE(x) + 0x60010)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF(x) (*(volatile hw_ipu_dmfc_dp_chan_def_t *) HW_IPU_DMFC_DP_CHAN_DEF_ADDR(x))
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF_RD(x) (HW_IPU_DMFC_DP_CHAN_DEF(x).U)
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF_WR(x, v) (HW_IPU_DMFC_DP_CHAN_DEF(x).U = (v))
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF_SET(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, HW_IPU_DMFC_DP_CHAN_DEF_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF_CLR(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_DP_CHAN_DEF_TOG(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, HW_IPU_DMFC_DP_CHAN_DEF_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_DP_CHAN_DEF bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_EN_5B[1] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B (1) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B (0x00000002) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_5B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_SET_5B[4:2] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B (2) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B (0x0000001c) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_5B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_CLR_5B[7:5] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B (5) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B (0x000000e0) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_5B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_EN_5F[9] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F (9) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F (0x00000200) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_5F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_SET_5F[12:10] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F (10) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F (0x00001c00) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_5F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_CLR_5F[15:13] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F (13) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F (0x0000e000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_5F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_EN_6B[17] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B (17) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B (0x00020000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B.
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|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_6B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_SET_6B[20:18] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B (18) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B.
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|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B (0x001c0000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B.
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|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_6B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_CLR_6B[23:21] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B (21) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B (0x00e00000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B.
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|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_6B field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_EN_6F[25] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F (25) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F (0x02000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_6F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_EN_6F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_SET_6F[28:26] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F (26) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F (0x1c000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_6F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_SET_6F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF, field DMFC_WM_CLR_6F[31:29] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F (29) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F (0xe0000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F) >> BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F) & BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_6F field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F) | BF_IPU_DMFC_DP_CHAN_DEF_DMFC_WM_CLR_6F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_GENERAL_1 - DMFC General 1 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_GENERAL_1 - DMFC General 1 Register (RW)
|
|
*
|
|
* Reset value: 0x00000003
|
|
*/
|
|
typedef union _hw_ipu_dmfc_general_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_general_1_bitfields
|
|
{
|
|
unsigned DMFC_DCDP_SYNC_PR : 2; //!< [1:0] DMFC's memory access priority settings for simultaneous synchronous flows from DC & DP
|
|
unsigned RESERVED0 : 3; //!< [4:2] Reserved.
|
|
unsigned DMFC_BURST_SIZE_9 : 2; //!< [6:5] Burst size of IDMAC's channel 44
|
|
unsigned RESERVED1 : 2; //!< [8:7] Reserved.
|
|
unsigned DMFC_WM_EN_9 : 1; //!< [9] Watermark enable.
|
|
unsigned DMFC_WM_SET_9 : 3; //!< [12:10] Watermark Set
|
|
unsigned DMFC_WM_CLR_9 : 3; //!< [15:13] Watermark Clear
|
|
unsigned WAIT4EOT_1 : 1; //!< [16] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_2 : 1; //!< [17] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_3 : 1; //!< [18] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_4 : 1; //!< [19] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_5B : 1; //!< [20] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_5F : 1; //!< [21] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_6B : 1; //!< [22] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_6F : 1; //!< [23] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_9 : 1; //!< [24] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned RESERVED2 : 7; //!< [31:25] Reserved.
|
|
} B;
|
|
} hw_ipu_dmfc_general_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_GENERAL_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_GENERAL_1_ADDR(x) (REGS_IPU_BASE(x) + 0x60014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_GENERAL_1(x) (*(volatile hw_ipu_dmfc_general_1_t *) HW_IPU_DMFC_GENERAL_1_ADDR(x))
|
|
#define HW_IPU_DMFC_GENERAL_1_RD(x) (HW_IPU_DMFC_GENERAL_1(x).U)
|
|
#define HW_IPU_DMFC_GENERAL_1_WR(x, v) (HW_IPU_DMFC_GENERAL_1(x).U = (v))
|
|
#define HW_IPU_DMFC_GENERAL_1_SET(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, HW_IPU_DMFC_GENERAL_1_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_GENERAL_1_CLR(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, HW_IPU_DMFC_GENERAL_1_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_GENERAL_1_TOG(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, HW_IPU_DMFC_GENERAL_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_GENERAL_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field DMFC_DCDP_SYNC_PR[1:0] (RW)
|
|
*
|
|
* DMFC's memory access priority settings for simultaneous synchronous flows from DC & DP
|
|
*
|
|
* Values:
|
|
* - 00 - Forbidden - should not be used.
|
|
* - 01 - DC has higher priority over DP
|
|
* - 10 - DP has higher priority over DC
|
|
* - 11 - Round Robin
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR (0) //!< Bit position for IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR.
|
|
#define BM_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR (0x00000003) //!< Bit mask for IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR) >> BP_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR.
|
|
#define BF_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR) & BM_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_DCDP_SYNC_PR field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR) | BF_IPU_DMFC_GENERAL_1_DMFC_DCDP_SYNC_PR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field DMFC_BURST_SIZE_9[6:5] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 44 This field defines the burst size of the IDMAC's channel 44
|
|
* write accesses. This settings must match the settings in the corresponding IDMAC channel's
|
|
* settings. This channel is targeted for MASK - the FIFO size is always 32X128; The base address is
|
|
* always the upper half of the 8th segment
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9 (5) //!< Bit position for IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9.
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|
#define BM_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9 (0x00000060) //!< Bit mask for IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9.
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|
|
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//! @brief Get value of IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9) >> BP_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9)
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|
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//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9.
|
|
#define BF_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9) & BM_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_9 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9) | BF_IPU_DMFC_GENERAL_1_DMFC_BURST_SIZE_9(v)))
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|
#endif
|
|
//@}
|
|
|
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/*! @name Register IPU_DMFC_GENERAL_1, field DMFC_WM_EN_9[9] (RW)
|
|
*
|
|
* Watermark enable. This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9 (9) //!< Bit position for IPU_DMFC_GENERAL_1_DMFC_WM_EN_9.
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#define BM_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9 (0x00000200) //!< Bit mask for IPU_DMFC_GENERAL_1_DMFC_WM_EN_9.
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|
|
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//! @brief Get value of IPU_DMFC_GENERAL_1_DMFC_WM_EN_9 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9) >> BP_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9)
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//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_DMFC_WM_EN_9.
|
|
#define BF_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9) & BM_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_9 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9) | BF_IPU_DMFC_GENERAL_1_DMFC_WM_EN_9(v)))
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|
#endif
|
|
//@}
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|
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/*! @name Register IPU_DMFC_GENERAL_1, field DMFC_WM_SET_9[12:10] (RW)
|
|
*
|
|
* Watermark Set This field defines the watermark's level of the DMFC write FIFO. Crossing this
|
|
* level will send the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9 (10) //!< Bit position for IPU_DMFC_GENERAL_1_DMFC_WM_SET_9.
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#define BM_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9 (0x00001c00) //!< Bit mask for IPU_DMFC_GENERAL_1_DMFC_WM_SET_9.
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|
|
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//! @brief Get value of IPU_DMFC_GENERAL_1_DMFC_WM_SET_9 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9) >> BP_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9)
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|
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//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_DMFC_WM_SET_9.
|
|
#define BF_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9) & BM_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_9 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9) | BF_IPU_DMFC_GENERAL_1_DMFC_WM_SET_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field DMFC_WM_CLR_9[15:13] (RW)
|
|
*
|
|
* Watermark Clear This field defines the watermark's level of the DMFC's write FIFO. Crossing this
|
|
* level will clear the watermark signal to the IDMAC. The WM level is the amount of occupied bursts
|
|
* at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9 (13) //!< Bit position for IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9.
|
|
#define BM_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9 (0x0000e000) //!< Bit mask for IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9.
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|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9) >> BP_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9.
|
|
#define BF_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9) & BM_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_9 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9) | BF_IPU_DMFC_GENERAL_1_DMFC_WM_CLR_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_1[16] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #1 is in normal mode
|
|
* - 1 - FIFO #1 is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_1 (16) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_1.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_1 (0x00010000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_1.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_1 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_1) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_1)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_1.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_1) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_1)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_1 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_1(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_1) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_2[17] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #2 is in normal mode
|
|
* - 1 - FIFO #2 is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_2 (17) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_2.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_2 (0x00020000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_2.
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|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_2 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_2) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_2)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_2.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_2) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_2 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_2(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_2) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_3[18] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #3 is in normal mode
|
|
* - 1 - FIFO #3 is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_3 (18) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_3.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_3 (0x00040000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_3.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_3 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_3) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_3)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_3.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_3) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_3 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_3(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_3) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_4[19] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #4 is in normal mode
|
|
* - 1 - FIFO #4 is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_4 (19) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_4.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_4 (0x00080000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_4.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_4 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_4) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_4)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_4.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_4) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_4)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_4 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_4(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_4) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_4(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_5B[20] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #5B is in normal mode
|
|
* - 1 - FIFO #5B is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_5B (20) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_5B.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5B (0x00100000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_5B.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_5B from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_5B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5B) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_5B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_5B.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_5B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_5B) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5B)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_5B field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_5B(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5B) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_5B(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_5F[21] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #5F is in normal mode
|
|
* - 1 - FIFO #5F is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_5F (21) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_5F.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5F (0x00200000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_5F.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_5F from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_5F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5F) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_5F)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_5F.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_5F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_5F) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5F)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_5F field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_5F(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_5F) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_5F(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_6B[22] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #6B is in normal mode
|
|
* - 1 - FIFO #6B is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_6B (22) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_6B.
|
|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6B (0x00400000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_6B.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_6B from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_6B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6B) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_6B)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_6B.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_6B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_6B) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6B)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_6B field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_6B(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6B) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_6B(v)))
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|
#endif
|
|
//@}
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|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_6F[23] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #6F is in normal mode
|
|
* - 1 - FIFO #6F is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_6F (23) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_6F.
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|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6F (0x00800000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_6F.
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|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_6F from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_6F(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6F) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_6F)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_6F.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_6F(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_6F) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6F)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_6F field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_6F(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_6F) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_6F(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_1, field WAIT4EOT_9[24] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #9 is in normal mode
|
|
* - 1 - FIFO #9 is in wait4eot mode
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_1_WAIT4EOT_9 (24) //!< Bit position for IPU_DMFC_GENERAL_1_WAIT4EOT_9.
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|
#define BM_IPU_DMFC_GENERAL_1_WAIT4EOT_9 (0x01000000) //!< Bit mask for IPU_DMFC_GENERAL_1_WAIT4EOT_9.
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|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_1_WAIT4EOT_9 from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_1_WAIT4EOT_9(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_9) >> BP_IPU_DMFC_GENERAL_1_WAIT4EOT_9)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_1_WAIT4EOT_9.
|
|
#define BF_IPU_DMFC_GENERAL_1_WAIT4EOT_9(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_1_WAIT4EOT_9) & BM_IPU_DMFC_GENERAL_1_WAIT4EOT_9)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_9 field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_1_WAIT4EOT_9(x, v) (HW_IPU_DMFC_GENERAL_1_WR(x, (HW_IPU_DMFC_GENERAL_1_RD(x) & ~BM_IPU_DMFC_GENERAL_1_WAIT4EOT_9) | BF_IPU_DMFC_GENERAL_1_WAIT4EOT_9(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_GENERAL_2 - DMFC General 2 Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_GENERAL_2 - DMFC General 2 Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_general_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_general_2_bitfields
|
|
{
|
|
unsigned DMFC_FRAME_WIDTH_RD : 13; //!< [12:0] Frame width for read channel from the display to the IDMAC; Units are pixels
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved.
|
|
unsigned DMFC_FRAME_HEIGHT_RD : 13; //!< [28:16] Frame height for read channel from the display to the IDMAC; Units are pixels
|
|
unsigned RESERVED1 : 3; //!< [31:29] Reserved.
|
|
} B;
|
|
} hw_ipu_dmfc_general_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_GENERAL_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_GENERAL_2_ADDR(x) (REGS_IPU_BASE(x) + 0x60018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_GENERAL_2(x) (*(volatile hw_ipu_dmfc_general_2_t *) HW_IPU_DMFC_GENERAL_2_ADDR(x))
|
|
#define HW_IPU_DMFC_GENERAL_2_RD(x) (HW_IPU_DMFC_GENERAL_2(x).U)
|
|
#define HW_IPU_DMFC_GENERAL_2_WR(x, v) (HW_IPU_DMFC_GENERAL_2(x).U = (v))
|
|
#define HW_IPU_DMFC_GENERAL_2_SET(x, v) (HW_IPU_DMFC_GENERAL_2_WR(x, HW_IPU_DMFC_GENERAL_2_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_GENERAL_2_CLR(x, v) (HW_IPU_DMFC_GENERAL_2_WR(x, HW_IPU_DMFC_GENERAL_2_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_GENERAL_2_TOG(x, v) (HW_IPU_DMFC_GENERAL_2_WR(x, HW_IPU_DMFC_GENERAL_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_GENERAL_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_2, field DMFC_FRAME_WIDTH_RD[12:0] (RW)
|
|
*
|
|
* Frame width for read channel from the display to the IDMAC; Units are pixels
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD (0) //!< Bit position for IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD.
|
|
#define BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD (0x00001fff) //!< Bit mask for IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD) >> BP_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD.
|
|
#define BF_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD) & BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FRAME_WIDTH_RD field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD(x, v) (HW_IPU_DMFC_GENERAL_2_WR(x, (HW_IPU_DMFC_GENERAL_2_RD(x) & ~BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD) | BF_IPU_DMFC_GENERAL_2_DMFC_FRAME_WIDTH_RD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL_2, field DMFC_FRAME_HEIGHT_RD[28:16] (RW)
|
|
*
|
|
* Frame height for read channel from the display to the IDMAC; Units are pixels
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD (16) //!< Bit position for IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD.
|
|
#define BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD (0x1fff0000) //!< Bit mask for IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD from a register value.
|
|
#define BG_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD) >> BP_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD.
|
|
#define BF_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD) & BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FRAME_HEIGHT_RD field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD(x, v) (HW_IPU_DMFC_GENERAL_2_WR(x, (HW_IPU_DMFC_GENERAL_2_RD(x) & ~BM_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD) | BF_IPU_DMFC_GENERAL_2_DMFC_FRAME_HEIGHT_RD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_IC_CTRL - DMFC IC Interface Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_IC_CTRL - DMFC IC Interface Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000002
|
|
*/
|
|
typedef union _hw_ipu_dmfc_ic_ctrl
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_ic_ctrl_bitfields
|
|
{
|
|
unsigned DMFC_IC_IN_PORT : 3; //!< [2:0] DMFC input port
|
|
unsigned RESERVED0 : 1; //!< [3] Reserved
|
|
unsigned DMFC_IC_PPW_C : 2; //!< [5:4] Pixel Per Word coded from IC.
|
|
unsigned DMFC_IC_FRAME_WIDTH_RD : 13; //!< [18:6] Frame's width for the channel coming from IC.
|
|
unsigned DMFC_IC_FRAME_HEIGHT_RD : 13; //!< [31:19] Frame's height for the channel coming from IC.
|
|
} B;
|
|
} hw_ipu_dmfc_ic_ctrl_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_IC_CTRL register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_IC_CTRL_ADDR(x) (REGS_IPU_BASE(x) + 0x6001c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_IC_CTRL(x) (*(volatile hw_ipu_dmfc_ic_ctrl_t *) HW_IPU_DMFC_IC_CTRL_ADDR(x))
|
|
#define HW_IPU_DMFC_IC_CTRL_RD(x) (HW_IPU_DMFC_IC_CTRL(x).U)
|
|
#define HW_IPU_DMFC_IC_CTRL_WR(x, v) (HW_IPU_DMFC_IC_CTRL(x).U = (v))
|
|
#define HW_IPU_DMFC_IC_CTRL_SET(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, HW_IPU_DMFC_IC_CTRL_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_IC_CTRL_CLR(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, HW_IPU_DMFC_IC_CTRL_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_IC_CTRL_TOG(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, HW_IPU_DMFC_IC_CTRL_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_IC_CTRL bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_IC_CTRL, field DMFC_IC_IN_PORT[2:0] (RW)
|
|
*
|
|
* DMFC input port When data is coming from the IC, the IC channel replaces one of the IDMAC's
|
|
* channels connected to the DMFC. This field defines which IDMAC's channel is replaced by the IC
|
|
* channel.
|
|
*
|
|
* Values:
|
|
* - 000 - CH28
|
|
* - 001 - CH41
|
|
* - 010 - Reserved, IC channel is disabled
|
|
* - 011 - Reserved, IC channel is disabled
|
|
* - 100 - CH23
|
|
* - 101 - CH27
|
|
* - 110 - CH24
|
|
* - 111 - CH29
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT (0) //!< Bit position for IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT.
|
|
#define BM_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT (0x00000007) //!< Bit mask for IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT.
|
|
|
|
//! @brief Get value of IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT from a register value.
|
|
#define BG_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT) >> BP_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT.
|
|
#define BF_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_IC_IN_PORT field to a new value.
|
|
#define BW_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, (HW_IPU_DMFC_IC_CTRL_RD(x) & ~BM_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT) | BF_IPU_DMFC_IC_CTRL_DMFC_IC_IN_PORT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_IC_CTRL, field DMFC_IC_PPW_C[5:4] (RW)
|
|
*
|
|
* Pixel Per Word coded from IC. This field defines the size of the data coming from the IC.
|
|
*
|
|
* Values:
|
|
* - 00 - 8 bit per pixel
|
|
* - 01 - 16 bit per pixel
|
|
* - 10 - 24 bit per pixel
|
|
* - 11 - Reserved
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C (4) //!< Bit position for IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C.
|
|
#define BM_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C (0x00000030) //!< Bit mask for IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C.
|
|
|
|
//! @brief Get value of IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C from a register value.
|
|
#define BG_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C) >> BP_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C.
|
|
#define BF_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_IC_PPW_C field to a new value.
|
|
#define BW_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, (HW_IPU_DMFC_IC_CTRL_RD(x) & ~BM_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C) | BF_IPU_DMFC_IC_CTRL_DMFC_IC_PPW_C(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_IC_CTRL, field DMFC_IC_FRAME_WIDTH_RD[18:6] (RW)
|
|
*
|
|
* Frame's width for the channel coming from IC. Units are pixels
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD (6) //!< Bit position for IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD.
|
|
#define BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD (0x0007ffc0) //!< Bit mask for IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD.
|
|
|
|
//! @brief Get value of IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD from a register value.
|
|
#define BG_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD) >> BP_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD.
|
|
#define BF_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_IC_FRAME_WIDTH_RD field to a new value.
|
|
#define BW_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, (HW_IPU_DMFC_IC_CTRL_RD(x) & ~BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD) | BF_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_WIDTH_RD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_IC_CTRL, field DMFC_IC_FRAME_HEIGHT_RD[31:19] (RW)
|
|
*
|
|
* Frame's height for the channel coming from IC. Units are lines
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD (19) //!< Bit position for IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD.
|
|
#define BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD (0xfff80000) //!< Bit mask for IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD.
|
|
|
|
//! @brief Get value of IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD from a register value.
|
|
#define BG_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD) >> BP_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD.
|
|
#define BF_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD) & BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_IC_FRAME_HEIGHT_RD field to a new value.
|
|
#define BW_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD(x, v) (HW_IPU_DMFC_IC_CTRL_WR(x, (HW_IPU_DMFC_IC_CTRL_RD(x) & ~BM_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD) | BF_IPU_DMFC_IC_CTRL_DMFC_IC_FRAME_HEIGHT_RD(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_WR_CHAN_ALT - DMFC Write Channel Alternate Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_WR_CHAN_ALT - DMFC Write Channel Alternate Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_wr_chan_alt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_wr_chan_alt_bitfields
|
|
{
|
|
unsigned RESERVED0 : 8; //!< [7:0] Reserved
|
|
unsigned DMFC_ST_ADDR_2_ALT : 3; //!< [10:8] DMFC Start Address for IDMAC's channel 41 (for alternate flow)
|
|
unsigned DMFC_FIFO_SIZE_2_ALT : 3; //!< [13:11] DMFC FIFO size for IDMAC's channel 41 (for alternate flow)
|
|
unsigned DMFC_BURST_SIZE_2_ALT : 2; //!< [15:14] Burst size of IDMAC's channel 41 (for alternate flow)
|
|
unsigned RESERVED1 : 16; //!< [31:16] Reserved
|
|
} B;
|
|
} hw_ipu_dmfc_wr_chan_alt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_WR_CHAN_ALT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x60020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT(x) (*(volatile hw_ipu_dmfc_wr_chan_alt_t *) HW_IPU_DMFC_WR_CHAN_ALT_ADDR(x))
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT_RD(x) (HW_IPU_DMFC_WR_CHAN_ALT(x).U)
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT_WR(x, v) (HW_IPU_DMFC_WR_CHAN_ALT(x).U = (v))
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT_SET(x, v) (HW_IPU_DMFC_WR_CHAN_ALT_WR(x, HW_IPU_DMFC_WR_CHAN_ALT_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT_CLR(x, v) (HW_IPU_DMFC_WR_CHAN_ALT_WR(x, HW_IPU_DMFC_WR_CHAN_ALT_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_ALT_TOG(x, v) (HW_IPU_DMFC_WR_CHAN_ALT_WR(x, HW_IPU_DMFC_WR_CHAN_ALT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_WR_CHAN_ALT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_ALT, field DMFC_ST_ADDR_2_ALT[10:8] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 41 (for alternate flow) This field defines the base
|
|
* address at the DMFC's FIFO of the partition allocated to the channel connected to IDMAC's channel
|
|
* 41. The FIFO is partitioned to 8 equal segments. Each segment is 64X128 words The value of this
|
|
* field is the number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT (8) //!< Bit position for IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT.
|
|
#define BM_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT (0x00000700) //!< Bit mask for IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT) >> BP_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT.
|
|
#define BF_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT) & BM_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT(x, v) (HW_IPU_DMFC_WR_CHAN_ALT_WR(x, (HW_IPU_DMFC_WR_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT) | BF_IPU_DMFC_WR_CHAN_ALT_DMFC_ST_ADDR_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_ALT, field DMFC_FIFO_SIZE_2_ALT[13:11] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 41 (for alternate flow) This field defines the FIFO partition
|
|
* for the DMFC channel connected to IDMAC's channel 41
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT (11) //!< Bit position for IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT.
|
|
#define BM_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT (0x00003800) //!< Bit mask for IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT) >> BP_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT.
|
|
#define BF_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT) & BM_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT(x, v) (HW_IPU_DMFC_WR_CHAN_ALT_WR(x, (HW_IPU_DMFC_WR_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT) | BF_IPU_DMFC_WR_CHAN_ALT_DMFC_FIFO_SIZE_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_ALT, field DMFC_BURST_SIZE_2_ALT[15:14] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 41 (for alternate flow) This field defines the burst size of the
|
|
* IDMAC's channel 41 write accesses. This settings must match the settings in the corresponding
|
|
* IDMAC channel's settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT (14) //!< Bit position for IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT.
|
|
#define BM_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT (0x0000c000) //!< Bit mask for IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT) >> BP_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT.
|
|
#define BF_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT) & BM_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT(x, v) (HW_IPU_DMFC_WR_CHAN_ALT_WR(x, (HW_IPU_DMFC_WR_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT) | BF_IPU_DMFC_WR_CHAN_ALT_DMFC_BURST_SIZE_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_WR_CHAN_DEF_ALT - DMFC Write Channel Definition Alternate Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_WR_CHAN_DEF_ALT - DMFC Write Channel Definition Alternate Register (RW)
|
|
*
|
|
* Reset value: 0x00002000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_wr_chan_def_alt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_wr_chan_def_alt_bitfields
|
|
{
|
|
unsigned RESERVED0 : 9; //!< [8:0] Reserved
|
|
unsigned DMFC_WM_EN_2_ALT : 1; //!< [9] Watermark enable.
|
|
unsigned DMFC_WM_SET_2_ALT : 3; //!< [12:10] Watermark Set (for alternate flow)
|
|
unsigned DMFC_WM_CLR_2_ALT : 3; //!< [15:13] Watermark Clear (for alternate flow)
|
|
unsigned RESERVED1 : 16; //!< [31:16] Reserved
|
|
} B;
|
|
} hw_ipu_dmfc_wr_chan_def_alt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_WR_CHAN_DEF_ALT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x60024)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT(x) (*(volatile hw_ipu_dmfc_wr_chan_def_alt_t *) HW_IPU_DMFC_WR_CHAN_DEF_ALT_ADDR(x))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) (HW_IPU_DMFC_WR_CHAN_DEF_ALT(x).U)
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT(x).U = (v))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT_SET(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT_CLR(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_WR_CHAN_DEF_ALT_TOG(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_WR_CHAN_DEF_ALT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF_ALT, field DMFC_WM_EN_2_ALT[9] (RW)
|
|
*
|
|
* Watermark enable. (for alternate flow) This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT (9) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT.
|
|
#define BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT (0x00000200) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT) >> BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT) & BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT) | BF_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_EN_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF_ALT, field DMFC_WM_SET_2_ALT[12:10] (RW)
|
|
*
|
|
* Watermark Set (for alternate flow) This field defines the watermark's level of the DMFC write
|
|
* FIFO. Crossing this level will send the watermark signal to the IDMAC. The WM level is the amount
|
|
* of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT (10) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT.
|
|
#define BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT (0x00001c00) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT) >> BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT) & BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT) | BF_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_SET_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_WR_CHAN_DEF_ALT, field DMFC_WM_CLR_2_ALT[15:13] (RW)
|
|
*
|
|
* Watermark Clear (for alternate flow) This field defines the watermark's level of the DMFC's write
|
|
* FIFO. Crossing this level will clear the watermark signal to the IDMAC. The WM level is the
|
|
* amount of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT (13) //!< Bit position for IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT.
|
|
#define BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT (0x0000e000) //!< Bit mask for IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT) >> BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT.
|
|
#define BF_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT) & BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT(x, v) (HW_IPU_DMFC_WR_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_WR_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT) | BF_IPU_DMFC_WR_CHAN_DEF_ALT_DMFC_WM_CLR_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_DP_CHAN_ALT - DMFC MFC Display Processor Channel Alternate Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_DP_CHAN_ALT - DMFC MFC Display Processor Channel Alternate Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_dp_chan_alt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_dp_chan_alt_bitfields
|
|
{
|
|
unsigned DMFC_ST_ADDR_5B_ALT : 3; //!< [2:0] DMFC Start Address for IDMAC's channel 23 (for alternate flow)
|
|
unsigned DMFC_FIFO_SIZE_5B_ALT : 3; //!< [5:3] DMFC FIFO size for IDMAC's channel 23 (for alternate flow)
|
|
unsigned DMFC_BURST_SIZE_5B_ALT : 2; //!< [7:6] Burst size of IDMAC's channel 23 (for alternate flow)
|
|
unsigned RESERVED0 : 8; //!< [15:8] Reserved
|
|
unsigned DMFC_ST_ADDR_6B_ALT : 3; //!< [18:16] DMFC Start Address for IDMAC's channel 24 (for alternate flow)
|
|
unsigned DMFC_FIFO_SIZE_6B_ALT : 3; //!< [21:19] DMFC FIFO size for IDMAC's channel 24 (for alternate flow)
|
|
unsigned DMFC_BURST_SIZE_6B_ALT : 2; //!< [23:22] Burst size of IDMAC's channel 24 (for alternate flow)
|
|
unsigned DMFC_ST_ADDR_6F_ALT : 3; //!< [26:24] DMFC Start Address for IDMAC's channel 29 (for alternate flow)
|
|
unsigned DMFC_FIFO_SIZE_6F_ALT : 3; //!< [29:27] DMFC FIFO size for IDMAC's channel 29 (for alternate flow)
|
|
unsigned DMFC_BURST_SIZE_6F_ALT : 2; //!< [31:30] Burst size of IDMAC's channel 29 (for alternate flow)
|
|
} B;
|
|
} hw_ipu_dmfc_dp_chan_alt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_DP_CHAN_ALT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x60028)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT(x) (*(volatile hw_ipu_dmfc_dp_chan_alt_t *) HW_IPU_DMFC_DP_CHAN_ALT_ADDR(x))
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT_RD(x) (HW_IPU_DMFC_DP_CHAN_ALT(x).U)
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT_WR(x, v) (HW_IPU_DMFC_DP_CHAN_ALT(x).U = (v))
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT_SET(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, HW_IPU_DMFC_DP_CHAN_ALT_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT_CLR(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_DP_CHAN_ALT_TOG(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, HW_IPU_DMFC_DP_CHAN_ALT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_DP_CHAN_ALT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_ST_ADDR_5B_ALT[2:0] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 23 (for alternate flow) This field defines the base
|
|
* address at the DMFC's FIFO of the partition allocated to the channel connected to IDMAC's channel
|
|
* 23. The FIFO is partitioned to 8 equal segments. Each segment is 64X128 words The value of this
|
|
* field is the number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT (0) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT (0x00000007) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_5B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_5B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_FIFO_SIZE_5B_ALT[5:3] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 23 (for alternate flow) This field defines the FIFO partition
|
|
* for the DMFC channel connected to IDMAC's channel 23
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT (3) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT (0x00000038) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_5B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_5B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_BURST_SIZE_5B_ALT[7:6] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 23 (for alternate flow) This field defines the burst size of the
|
|
* IDMAC's channel 23 write accesses. This settings must match the settings in the corresponding
|
|
* IDMAC channel's settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT (6) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT (0x000000c0) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_5B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_5B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_ST_ADDR_6B_ALT[18:16] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 24 (for alternate flow) This field defines the base
|
|
* address at the DMFC's FIFO of the partition allocated to the channel connected to IDMAC's channel
|
|
* 24. The FIFO is partitioned to 8 equal segments. Each segment is 64X128 words The value of this
|
|
* field is the number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT (16) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT (0x00070000) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_6B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_FIFO_SIZE_6B_ALT[21:19] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 24 (for alternate flow) This field defines the FIFO partition
|
|
* for the DMFC channel connected to IDMAC's channel 24
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT (19) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT (0x00380000) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_FIFO_SIZE_6B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_BURST_SIZE_6B_ALT[23:22] (RW)
|
|
*
|
|
* Burst size of IDMAC's channel 24 (for alternate flow) This field defines the burst size of the
|
|
* IDMAC's channel 24 write accesses. This settings must match the settings in the corresponding
|
|
* IDMAC channel's settings.
|
|
*
|
|
* Values:
|
|
* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
|
|
* - 01 - 16 words of 128 bit
|
|
* - 10 - 8 words of 128 bit
|
|
* - 11 - 4 words of 128 bit
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT (22) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT (0x00c00000) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_BURST_SIZE_6B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_ST_ADDR_6F_ALT[26:24] (RW)
|
|
*
|
|
* DMFC Start Address for IDMAC's channel 29 (for alternate flow) This field defines the base
|
|
* address at the DMFC's FIFO of the partition allocated to the channel connected to IDMAC's channel
|
|
* 29. The FIFO is partitioned to 8 equal segments. Each segment is 64X128 words The value of this
|
|
* field is the number of the segment
|
|
*
|
|
* Values:
|
|
* - 000 - Segment 0
|
|
* - 001 - Segment 1
|
|
* - 111 - Segment 7
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT (24) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT (0x07000000) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_ST_ADDR_6F_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_ST_ADDR_6F_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_FIFO_SIZE_6F_ALT[29:27] (RW)
|
|
*
|
|
* DMFC FIFO size for IDMAC's channel 29 (for alternate flow) This field defines the FIFO partition
|
|
* for the DMFC channel connected to IDMAC's channel 29
|
|
*
|
|
* Values:
|
|
* - 000 - All (512X128 words) the DMFC's FIFO is allocated to this channel
|
|
* - 001 - 256X128 words are allocated to this channel
|
|
* - 010 - 128X128 words are allocated to this channel
|
|
* - 011 - 64X128 words are allocated to this channel
|
|
* - 100 - 32X128 words are allocated to this channel
|
|
* - 101 - 16X128 words are allocated to this channel
|
|
* - 110 - 8X128 words are allocated to this channel
|
|
* - 111 - 4X128 words are allocated to this channel
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT (27) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT.
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|
#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT (0x38000000) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT.
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#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_FIFO_SIZE_6F_ALT field to a new value.
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#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_FIFO_SIZE_6F_ALT(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_DP_CHAN_ALT, field DMFC_BURST_SIZE_6F_ALT[31:30] (RW)
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*
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* Burst size of IDMAC's channel 29 (for alternate flow) This field defines the burst size of the
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* IDMAC's channel 29 write accesses. This settings must match the settings in the corresponding
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* IDMAC channel's settings.
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*
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* Values:
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* - 00 - 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC)
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* - 01 - 16 words of 128 bit
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* - 10 - 8 words of 128 bit
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* - 11 - 4 words of 128 bit
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*/
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//@{
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#define BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT (30) //!< Bit position for IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT.
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#define BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT (0xc0000000) //!< Bit mask for IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT) >> BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT.
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#define BF_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT) & BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_BURST_SIZE_6F_ALT field to a new value.
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#define BW_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT) | BF_IPU_DMFC_DP_CHAN_ALT_DMFC_BURST_SIZE_6F_ALT(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_DMFC_DP_CHAN_DEF_ALT - DMFC Display Channel Definition Alternate Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_IPU_DMFC_DP_CHAN_DEF_ALT - DMFC Display Channel Definition Alternate Register (RW)
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*
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* Reset value: 0x20200020
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*/
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typedef union _hw_ipu_dmfc_dp_chan_def_alt
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{
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reg32_t U;
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struct _hw_ipu_dmfc_dp_chan_def_alt_bitfields
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{
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unsigned RESERVED0 : 1; //!< [0] Reserved
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unsigned DMFC_WM_EN_5B_ALT : 1; //!< [1] Watermark enable.
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unsigned DMFC_WM_SET_5B_ALT : 3; //!< [4:2] Watermark Set (for alternate flow)
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unsigned DMFC_WM_CLR_5B_ALT : 3; //!< [7:5] Watermark Clear (for alternate flow)
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unsigned RESERVED1 : 9; //!< [16:8] Reserved
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unsigned DMFC_WM_EN_6B_ALT : 1; //!< [17] Watermark enable.
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unsigned DMFC_WM_SET_6B_ALT : 3; //!< [20:18] Watermark Set (for alternate flow)
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unsigned DMFC_WM_CLR_6B_ALT : 3; //!< [23:21] Watermark Clear (for alternate flow)
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unsigned RESERVED2 : 1; //!< [24] Reserved
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unsigned DMFC_WM_EN_6F_ALT : 1; //!< [25] Watermark enable.
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unsigned DMFC_WM_SET_6F_ALT : 3; //!< [28:26] Watermark Set (for alternate flow)
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unsigned DMFC_WM_CLR_6F_ALT : 3; //!< [31:29] Watermark Clear (for alternate flow)
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} B;
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} hw_ipu_dmfc_dp_chan_def_alt_t;
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#endif
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/*!
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* @name Constants and macros for entire IPU_DMFC_DP_CHAN_DEF_ALT register
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*/
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//@{
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x6002c)
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#ifndef __LANGUAGE_ASM__
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT(x) (*(volatile hw_ipu_dmfc_dp_chan_def_alt_t *) HW_IPU_DMFC_DP_CHAN_DEF_ALT_ADDR(x))
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) (HW_IPU_DMFC_DP_CHAN_DEF_ALT(x).U)
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT(x).U = (v))
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT_SET(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) | (v)))
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT_CLR(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~(v)))
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#define HW_IPU_DMFC_DP_CHAN_DEF_ALT_TOG(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_DMFC_DP_CHAN_DEF_ALT bitfields
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*/
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/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_EN_5B_ALT[1] (RW)
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*
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* Watermark enable. (for alternate flow) This bit enables the watermark feature of the FIFO
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*
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* Values:
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* - 0 - WM feature is disabled
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* - 1 - WM feature is enabled
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*/
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//@{
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#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT (1) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT.
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#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT (0x00000002) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT.
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#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_EN_5B_ALT field to a new value.
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#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_5B_ALT(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_SET_5B_ALT[4:2] (RW)
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*
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* Watermark Set (for alternate flow) This field defines the watermark's level of the DMFC write
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* FIFO. Crossing this level will send the watermark signal to the IDMAC. The WM level is the amount
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* of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set
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*/
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//@{
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#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT (2) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT.
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#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT (0x0000001c) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT.
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#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_SET_5B_ALT field to a new value.
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#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_5B_ALT(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_CLR_5B_ALT[7:5] (RW)
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*
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* Watermark Clear (for alternate flow) This field defines the watermark's level of the DMFC's write
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* FIFO. Crossing this level will clear the watermark signal to the IDMAC. The WM level is the
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* amount of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set)
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*/
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//@{
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#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT (5) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT.
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#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT (0x000000e0) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT.
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#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_CLR_5B_ALT field to a new value.
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#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_5B_ALT(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_EN_6B_ALT[17] (RW)
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*
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* Watermark enable. (for alternate flow) This bit enables the watermark feature of the FIFO
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*
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|
* Values:
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* - 0 - WM feature is disabled
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* - 1 - WM feature is enabled
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*/
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//@{
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#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT (17) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT.
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#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT (0x00020000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT.
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#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DMFC_WM_EN_6B_ALT field to a new value.
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#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6B_ALT(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_SET_6B_ALT[20:18] (RW)
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*
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* Watermark Set (for alternate flow) This field defines the watermark's level of the DMFC write
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|
* FIFO. Crossing this level will send the watermark signal to the IDMAC. The WM level is the amount
|
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* of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set
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*/
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//@{
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#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT (18) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT.
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#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT (0x001c0000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT.
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#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT)
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#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the DMFC_WM_SET_6B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6B_ALT(v)))
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#endif
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//@}
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/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_CLR_6B_ALT[23:21] (RW)
|
|
*
|
|
* Watermark Clear (for alternate flow) This field defines the watermark's level of the DMFC's write
|
|
* FIFO. Crossing this level will clear the watermark signal to the IDMAC. The WM level is the
|
|
* amount of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
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|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT (21) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT.
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#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT (0x00e00000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT.
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//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT from a register value.
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#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT)
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//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT.
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|
#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT)
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#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_6B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6B_ALT(v)))
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|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_EN_6F_ALT[25] (RW)
|
|
*
|
|
* Watermark enable. (for alternate flow) This bit enables the watermark feature of the FIFO
|
|
*
|
|
* Values:
|
|
* - 0 - WM feature is disabled
|
|
* - 1 - WM feature is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT (25) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT (0x02000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT.
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|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_EN_6F_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_EN_6F_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_SET_6F_ALT[28:26] (RW)
|
|
*
|
|
* Watermark Set (for alternate flow) This field defines the watermark's level of the DMFC write
|
|
* FIFO. Crossing this level will send the watermark signal to the IDMAC. The WM level is the amount
|
|
* of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT (26) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT.
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|
#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT (0x1c000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT.
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|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT)
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|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_SET_6F_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_SET_6F_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_DP_CHAN_DEF_ALT, field DMFC_WM_CLR_6F_ALT[31:29] (RW)
|
|
*
|
|
* Watermark Clear (for alternate flow) This field defines the watermark's level of the DMFC's write
|
|
* FIFO. Crossing this level will clear the watermark signal to the IDMAC. The WM level is the
|
|
* amount of occupied bursts at the FIFO (dmfc_wm_clr > dmfc_wm_set)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT (29) //!< Bit position for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT.
|
|
#define BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT (0xe0000000) //!< Bit mask for IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT from a register value.
|
|
#define BG_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT) >> BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT.
|
|
#define BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT) & BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the DMFC_WM_CLR_6F_ALT field to a new value.
|
|
#define BW_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT(x, v) (HW_IPU_DMFC_DP_CHAN_DEF_ALT_WR(x, (HW_IPU_DMFC_DP_CHAN_DEF_ALT_RD(x) & ~BM_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT) | BF_IPU_DMFC_DP_CHAN_DEF_ALT_DMFC_WM_CLR_6F_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_GENERAL1_ALT - DMFC General 1 Alternate Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_GENERAL1_ALT - DMFC General 1 Alternate Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_ipu_dmfc_general1_alt
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_general1_alt_bitfields
|
|
{
|
|
unsigned RESERVED0 : 17; //!< [16:0] Reserved.
|
|
unsigned WAIT4EOT_2_ALT : 1; //!< [17] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned RESERVED1 : 2; //!< [19:18] Reserved
|
|
unsigned WAIT4EOT_5B_ALT : 1; //!< [20] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned RESERVED2 : 1; //!< [21] Reserved
|
|
unsigned WAIT4EOT_6B_ALT : 1; //!< [22] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned WAIT4EOT_6F_ALT : 1; //!< [23] In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO.
|
|
unsigned RESERVED3 : 8; //!< [31:24] Reserved.
|
|
} B;
|
|
} hw_ipu_dmfc_general1_alt_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_GENERAL1_ALT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_GENERAL1_ALT_ADDR(x) (REGS_IPU_BASE(x) + 0x60030)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_GENERAL1_ALT(x) (*(volatile hw_ipu_dmfc_general1_alt_t *) HW_IPU_DMFC_GENERAL1_ALT_ADDR(x))
|
|
#define HW_IPU_DMFC_GENERAL1_ALT_RD(x) (HW_IPU_DMFC_GENERAL1_ALT(x).U)
|
|
#define HW_IPU_DMFC_GENERAL1_ALT_WR(x, v) (HW_IPU_DMFC_GENERAL1_ALT(x).U = (v))
|
|
#define HW_IPU_DMFC_GENERAL1_ALT_SET(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, HW_IPU_DMFC_GENERAL1_ALT_RD(x) | (v)))
|
|
#define HW_IPU_DMFC_GENERAL1_ALT_CLR(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, HW_IPU_DMFC_GENERAL1_ALT_RD(x) & ~(v)))
|
|
#define HW_IPU_DMFC_GENERAL1_ALT_TOG(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, HW_IPU_DMFC_GENERAL1_ALT_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_GENERAL1_ALT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL1_ALT, field WAIT4EOT_2_ALT[17] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #2 is in normal mode (for alternate flow)
|
|
* - 1 - FIFO #2 is in wait4eot mode (for alternate flow)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT (17) //!< Bit position for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT.
|
|
#define BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT (0x00020000) //!< Bit mask for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT from a register value.
|
|
#define BG_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT) >> BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT.
|
|
#define BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_2_ALT field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, (HW_IPU_DMFC_GENERAL1_ALT_RD(x) & ~BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT) | BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL1_ALT, field WAIT4EOT_5B_ALT[20] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #5B is in normal mode (for alternate flow)
|
|
* - 1 - FIFO #5B is in wait4eot mode (for alternate flow)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT (20) //!< Bit position for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT.
|
|
#define BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT (0x00100000) //!< Bit mask for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT from a register value.
|
|
#define BG_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT) >> BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT.
|
|
#define BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_5B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, (HW_IPU_DMFC_GENERAL1_ALT_RD(x) & ~BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT) | BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL1_ALT, field WAIT4EOT_6B_ALT[22] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #6B is in normal mode (for alternate flow)
|
|
* - 1 - FIFO #6B is in wait4eot mode (for alternate flow)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT (22) //!< Bit position for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT.
|
|
#define BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT (0x00400000) //!< Bit mask for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT from a register value.
|
|
#define BG_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT) >> BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT.
|
|
#define BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_6B_ALT field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, (HW_IPU_DMFC_GENERAL1_ALT_RD(x) & ~BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT) | BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_GENERAL1_ALT, field WAIT4EOT_6F_ALT[23] (RW)
|
|
*
|
|
* In normal operation the DMFC sends requests to the IDMAC whenever there is room in the FIFO. When
|
|
* this bit is set the DMFC sends the request only after the current transfer is terminated,
|
|
* (wait4eot mode) When the FIFO is larger then the size of the line, the user should work in
|
|
* wait4eot mode.
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #6F is in normal mode (for alternate flow)
|
|
* - 1 - FIFO #6F is in wait4eot mode (for alternate flow)
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT (23) //!< Bit position for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT.
|
|
#define BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT (0x00800000) //!< Bit mask for IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT.
|
|
|
|
//! @brief Get value of IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT from a register value.
|
|
#define BG_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT) >> BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT)
|
|
|
|
//! @brief Format value for bitfield IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT.
|
|
#define BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT) & BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the WAIT4EOT_6F_ALT field to a new value.
|
|
#define BW_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT(x, v) (HW_IPU_DMFC_GENERAL1_ALT_WR(x, (HW_IPU_DMFC_GENERAL1_ALT_RD(x) & ~BM_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT) | BF_IPU_DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_DMFC_STAT - DMFC Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_DMFC_STAT - DMFC Status Register (RO)
|
|
*
|
|
* Reset value: 0x02fff000
|
|
*
|
|
* This register contains DMFC's status bits. All the bits in this register are read-only.
|
|
*/
|
|
typedef union _hw_ipu_dmfc_stat
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_dmfc_stat_bitfields
|
|
{
|
|
unsigned DMFC_FIFO_FULL_I : 12; //!< [11:0] This bit indicates on a DMFC FIFO#<i> full condition.
|
|
unsigned DMFC_FIFO_EMPTY_I : 12; //!< [23:12] This bit indicates on a DMFC FIFO#<i> empty condition.
|
|
unsigned DMFC_IC_BUFFER_FULL : 1; //!< [24] This bit indicates on a IC FIFO, inside the DMFC, full condition.
|
|
unsigned DMFC_IC_BUFFER_EMPTY : 1; //!< [25] This bit indicates on a IC FIFO, inside the DMFC, empty condition.
|
|
unsigned RESERVED0 : 6; //!< [31:26] Reserved
|
|
} B;
|
|
} hw_ipu_dmfc_stat_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_DMFC_STAT register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_DMFC_STAT_ADDR(x) (REGS_IPU_BASE(x) + 0x60034)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_DMFC_STAT(x) (*(volatile hw_ipu_dmfc_stat_t *) HW_IPU_DMFC_STAT_ADDR(x))
|
|
#define HW_IPU_DMFC_STAT_RD(x) (HW_IPU_DMFC_STAT(x).U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_DMFC_STAT bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_DMFC_STAT, field DMFC_FIFO_FULL_I[11:0] (RO)
|
|
*
|
|
* This bit indicates on a DMFC FIFO#<i> full condition. Mapping of these bit to an actual FIFO
|
|
* number is as follows: bit 0 => 0 bit 1=> 1 bit 2 => 2 bit 3 =>1c bit 4 => 2c bit 5 => 5b bit 6 =>
|
|
* 5f bit 7 => 6b bit 8 => 6f bit 9 => 9 bit 10 => 10 (ARM platform access) bit 11 => 11 (ARM
|
|
* platform access)
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #<i> is not full
|
|
* - 1 - FIFO #<i> is full
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_STAT_DMFC_FIFO_FULL_I (0) //!< Bit position for IPU_DMFC_STAT_DMFC_FIFO_FULL_I.
|
|
#define BM_IPU_DMFC_STAT_DMFC_FIFO_FULL_I (0x00000fff) //!< Bit mask for IPU_DMFC_STAT_DMFC_FIFO_FULL_I.
|
|
|
|
//! @brief Get value of IPU_DMFC_STAT_DMFC_FIFO_FULL_I from a register value.
|
|
#define BG_IPU_DMFC_STAT_DMFC_FIFO_FULL_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_STAT_DMFC_FIFO_FULL_I) >> BP_IPU_DMFC_STAT_DMFC_FIFO_FULL_I)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_STAT, field DMFC_FIFO_EMPTY_I[23:12] (RO)
|
|
*
|
|
* This bit indicates on a DMFC FIFO#<i> empty condition. Mapping of these bit to an actual FIFO
|
|
* number is as follows: bit 0 => 0 bit 1=> 1 bit 2 => 2 bit 3 =>1c bit 4 => 2c bit 5 => 5b bit 6 =>
|
|
* 5f bit 7 => 6b bit 8 => 6f bit 9 => 9 bit 10 => 10 (ARM platform access) bit 11 => 11 (ARM
|
|
* platform access)
|
|
*
|
|
* Values:
|
|
* - 0 - FIFO #<i> is not empty
|
|
* - 1 - FIFO #<i> is empty
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I (12) //!< Bit position for IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I.
|
|
#define BM_IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I (0x00fff000) //!< Bit mask for IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I.
|
|
|
|
//! @brief Get value of IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I from a register value.
|
|
#define BG_IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I) >> BP_IPU_DMFC_STAT_DMFC_FIFO_EMPTY_I)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_STAT, field DMFC_IC_BUFFER_FULL[24] (RO)
|
|
*
|
|
* This bit indicates on a IC FIFO, inside the DMFC, full condition.
|
|
*
|
|
* Values:
|
|
* - 0 - IC FIFO not full
|
|
* - 1 - IC FIFO is full
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL (24) //!< Bit position for IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL.
|
|
#define BM_IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL (0x01000000) //!< Bit mask for IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL.
|
|
|
|
//! @brief Get value of IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL from a register value.
|
|
#define BG_IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL) >> BP_IPU_DMFC_STAT_DMFC_IC_BUFFER_FULL)
|
|
//@}
|
|
|
|
/*! @name Register IPU_DMFC_STAT, field DMFC_IC_BUFFER_EMPTY[25] (RO)
|
|
*
|
|
* This bit indicates on a IC FIFO, inside the DMFC, empty condition.
|
|
*
|
|
* Values:
|
|
* - 0 - IC FIFO not empty
|
|
* - 1 - IC FIFO is empty
|
|
*/
|
|
//@{
|
|
#define BP_IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY (25) //!< Bit position for IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY.
|
|
#define BM_IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY (0x02000000) //!< Bit mask for IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY.
|
|
|
|
//! @brief Get value of IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY from a register value.
|
|
#define BG_IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY) >> BP_IPU_DMFC_STAT_DMFC_IC_BUFFER_EMPTY)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_FSIZE - VDI Field Size Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_FSIZE - VDI Field Size Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register used to control size of VDI C input fields.
|
|
*/
|
|
typedef union _hw_ipu_vdi_fsize
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_fsize_bitfields
|
|
{
|
|
unsigned VDI_FWIDTH : 11; //!< [10:0] Frame width.
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned VDI_FHEIGHT : 11; //!< [26:16] Frame height
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved
|
|
} B;
|
|
} hw_ipu_vdi_fsize_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_FSIZE register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_FSIZE_ADDR(x) (REGS_IPU_BASE(x) + 0x68000)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_FSIZE(x) (*(volatile hw_ipu_vdi_fsize_t *) HW_IPU_VDI_FSIZE_ADDR(x))
|
|
#define HW_IPU_VDI_FSIZE_RD(x) (HW_IPU_VDI_FSIZE(x).U)
|
|
#define HW_IPU_VDI_FSIZE_WR(x, v) (HW_IPU_VDI_FSIZE(x).U = (v))
|
|
#define HW_IPU_VDI_FSIZE_SET(x, v) (HW_IPU_VDI_FSIZE_WR(x, HW_IPU_VDI_FSIZE_RD(x) | (v)))
|
|
#define HW_IPU_VDI_FSIZE_CLR(x, v) (HW_IPU_VDI_FSIZE_WR(x, HW_IPU_VDI_FSIZE_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_FSIZE_TOG(x, v) (HW_IPU_VDI_FSIZE_WR(x, HW_IPU_VDI_FSIZE_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_FSIZE bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_FSIZE, field VDI_FWIDTH[10:0] (RW)
|
|
*
|
|
* Frame width. The value to be written to this register is the frame's width minus 1. The Frame
|
|
* width should not be smaller than 16. The width must be even. When VDI_CMB_EN bit is clear The
|
|
* Frame width should not be greater than 720968. When VDI_CMB_EN bit is set: The Frame width should
|
|
* not be greater than 1920.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_FSIZE_VDI_FWIDTH (0) //!< Bit position for IPU_VDI_FSIZE_VDI_FWIDTH.
|
|
#define BM_IPU_VDI_FSIZE_VDI_FWIDTH (0x000007ff) //!< Bit mask for IPU_VDI_FSIZE_VDI_FWIDTH.
|
|
|
|
//! @brief Get value of IPU_VDI_FSIZE_VDI_FWIDTH from a register value.
|
|
#define BG_IPU_VDI_FSIZE_VDI_FWIDTH(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_FSIZE_VDI_FWIDTH) >> BP_IPU_VDI_FSIZE_VDI_FWIDTH)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_FSIZE_VDI_FWIDTH.
|
|
#define BF_IPU_VDI_FSIZE_VDI_FWIDTH(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_FSIZE_VDI_FWIDTH) & BM_IPU_VDI_FSIZE_VDI_FWIDTH)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FWIDTH field to a new value.
|
|
#define BW_IPU_VDI_FSIZE_VDI_FWIDTH(x, v) (HW_IPU_VDI_FSIZE_WR(x, (HW_IPU_VDI_FSIZE_RD(x) & ~BM_IPU_VDI_FSIZE_VDI_FWIDTH) | BF_IPU_VDI_FSIZE_VDI_FWIDTH(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_FSIZE, field VDI_FHEIGHT[26:16] (RW)
|
|
*
|
|
* Frame height The value to be written to this register is the frame's height minus 1. The frame
|
|
* height should not be smaller than 16. When VDI_CMB_EN bit is clear: The frame height should not
|
|
* be greater than 1080. The frame's height must be even (which means that both fields have the same
|
|
* height) The frame's height in 4:2:0 format, must be multiple of 4 (which means that both chroma
|
|
* fields have the same height) When VDI_CMB_EN bit is set: The frame height should not be greater
|
|
* than 1200.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_FSIZE_VDI_FHEIGHT (16) //!< Bit position for IPU_VDI_FSIZE_VDI_FHEIGHT.
|
|
#define BM_IPU_VDI_FSIZE_VDI_FHEIGHT (0x07ff0000) //!< Bit mask for IPU_VDI_FSIZE_VDI_FHEIGHT.
|
|
|
|
//! @brief Get value of IPU_VDI_FSIZE_VDI_FHEIGHT from a register value.
|
|
#define BG_IPU_VDI_FSIZE_VDI_FHEIGHT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_FSIZE_VDI_FHEIGHT) >> BP_IPU_VDI_FSIZE_VDI_FHEIGHT)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_FSIZE_VDI_FHEIGHT.
|
|
#define BF_IPU_VDI_FSIZE_VDI_FHEIGHT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_FSIZE_VDI_FHEIGHT) & BM_IPU_VDI_FSIZE_VDI_FHEIGHT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FHEIGHT field to a new value.
|
|
#define BW_IPU_VDI_FSIZE_VDI_FHEIGHT(x, v) (HW_IPU_VDI_FSIZE_WR(x, (HW_IPU_VDI_FSIZE_RD(x) & ~BM_IPU_VDI_FSIZE_VDI_FHEIGHT) | BF_IPU_VDI_FSIZE_VDI_FHEIGHT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_C - VDI Control Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_C - VDI Control Register (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register used to control modes of operations of VDI C module.
|
|
*/
|
|
typedef union _hw_ipu_vdi_c
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_c_bitfields
|
|
{
|
|
unsigned RESERVED0 : 1; //!< [0] Reserved
|
|
unsigned VDI_CH_422 : 1; //!< [1] Chroma format at input and output of VDI C .
|
|
unsigned VDI_MOT_SEL : 2; //!< [3:2] Motion select.
|
|
unsigned VDI_BURST_SIZE1 : 4; //!< [7:4] Burst Size for channels 1 or 4 (channels 1 and 4 are not working simultaneously).
|
|
unsigned VDI_BURST_SIZE2 : 4; //!< [11:8] Burst Size for channel 2.
|
|
unsigned VDI_BURST_SIZE3 : 4; //!< [15:12] Burst Size for channel 3.
|
|
unsigned VDI_VWM1_SET : 3; //!< [18:16] VDI C WaterMark "set" level for channel 1 or channel 2 (channels 1 and 4 are not working simultaneously).
|
|
unsigned VDI_VWM1_CLR : 3; //!< [21:19] VDI C WaterMark "clear" level for channel 1 or channel 4 (channels 1 and 4 are not working simultaneously).
|
|
unsigned VDI_VWM3_SET : 3; //!< [24:22] VDI C WaterMark "set" level for channel 3.
|
|
unsigned VDI_VWM3_CLR : 3; //!< [27:25] VDI C WaterMark "clear" level for channel 3.
|
|
unsigned RESERVED2 : 4; //!< [31:28] Reserved.
|
|
} B;
|
|
} hw_ipu_vdi_c_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_C register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_C_ADDR(x) (REGS_IPU_BASE(x) + 0x68004)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_C(x) (*(volatile hw_ipu_vdi_c_t *) HW_IPU_VDI_C_ADDR(x))
|
|
#define HW_IPU_VDI_C_RD(x) (HW_IPU_VDI_C(x).U)
|
|
#define HW_IPU_VDI_C_WR(x, v) (HW_IPU_VDI_C(x).U = (v))
|
|
#define HW_IPU_VDI_C_SET(x, v) (HW_IPU_VDI_C_WR(x, HW_IPU_VDI_C_RD(x) | (v)))
|
|
#define HW_IPU_VDI_C_CLR(x, v) (HW_IPU_VDI_C_WR(x, HW_IPU_VDI_C_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_C_TOG(x, v) (HW_IPU_VDI_C_WR(x, HW_IPU_VDI_C_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_C bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_CH_422[1] (RW)
|
|
*
|
|
* Chroma format at input and output of VDI C .
|
|
*
|
|
* Values:
|
|
* - 0 - Chroma format is 420.
|
|
* - 1 - Chroma format is 422.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_CH_422 (1) //!< Bit position for IPU_VDI_C_VDI_CH_422.
|
|
#define BM_IPU_VDI_C_VDI_CH_422 (0x00000002) //!< Bit mask for IPU_VDI_C_VDI_CH_422.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_CH_422 from a register value.
|
|
#define BG_IPU_VDI_C_VDI_CH_422(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_CH_422) >> BP_IPU_VDI_C_VDI_CH_422)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_CH_422.
|
|
#define BF_IPU_VDI_C_VDI_CH_422(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_CH_422) & BM_IPU_VDI_C_VDI_CH_422)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_CH_422 field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_CH_422(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_CH_422) | BF_IPU_VDI_C_VDI_CH_422(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_MOT_SEL[3:2] (RW)
|
|
*
|
|
* Motion select.
|
|
*
|
|
* Values:
|
|
* - 0 - Motion determined by ROM "1" (shared toward medium/high motion).
|
|
* - 1 - Motion determined by ROM "2" (This option will not work well for high motion).
|
|
* - 2 - Full motion, only vertical filter is used
|
|
* - 3 - Forbidden.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_MOT_SEL (2) //!< Bit position for IPU_VDI_C_VDI_MOT_SEL.
|
|
#define BM_IPU_VDI_C_VDI_MOT_SEL (0x0000000c) //!< Bit mask for IPU_VDI_C_VDI_MOT_SEL.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_MOT_SEL from a register value.
|
|
#define BG_IPU_VDI_C_VDI_MOT_SEL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_MOT_SEL) >> BP_IPU_VDI_C_VDI_MOT_SEL)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_MOT_SEL.
|
|
#define BF_IPU_VDI_C_VDI_MOT_SEL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_MOT_SEL) & BM_IPU_VDI_C_VDI_MOT_SEL)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_MOT_SEL field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_MOT_SEL(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_MOT_SEL) | BF_IPU_VDI_C_VDI_MOT_SEL(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_BURST_SIZE1[7:4] (RW)
|
|
*
|
|
* Burst Size for channels 1 or 4 (channels 1 and 4 are not working simultaneously). The VDI C 's
|
|
* burst size is restrict by the IDMAC's restriction - This value must match the IDMAC settings and
|
|
* follow the IDMAC's restrictions
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 1 access.
|
|
* - 1 - Burst size is 2 accesses.
|
|
* - 15 - Burst size is 16 accesses.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_BURST_SIZE1 (4) //!< Bit position for IPU_VDI_C_VDI_BURST_SIZE1.
|
|
#define BM_IPU_VDI_C_VDI_BURST_SIZE1 (0x000000f0) //!< Bit mask for IPU_VDI_C_VDI_BURST_SIZE1.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_BURST_SIZE1 from a register value.
|
|
#define BG_IPU_VDI_C_VDI_BURST_SIZE1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_BURST_SIZE1) >> BP_IPU_VDI_C_VDI_BURST_SIZE1)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_BURST_SIZE1.
|
|
#define BF_IPU_VDI_C_VDI_BURST_SIZE1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_BURST_SIZE1) & BM_IPU_VDI_C_VDI_BURST_SIZE1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_BURST_SIZE1 field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_BURST_SIZE1(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_BURST_SIZE1) | BF_IPU_VDI_C_VDI_BURST_SIZE1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_BURST_SIZE2[11:8] (RW)
|
|
*
|
|
* Burst Size for channel 2. The VDI C 's burst size is restrict by the IDMAC's restriction - This
|
|
* value must match the IDMAC settings and follow the IDMAC's restrictions
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 1 access.
|
|
* - 1 - Burst size is 2 accesses.
|
|
* - 15 - Burst size is 16 accesses.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_BURST_SIZE2 (8) //!< Bit position for IPU_VDI_C_VDI_BURST_SIZE2.
|
|
#define BM_IPU_VDI_C_VDI_BURST_SIZE2 (0x00000f00) //!< Bit mask for IPU_VDI_C_VDI_BURST_SIZE2.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_BURST_SIZE2 from a register value.
|
|
#define BG_IPU_VDI_C_VDI_BURST_SIZE2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_BURST_SIZE2) >> BP_IPU_VDI_C_VDI_BURST_SIZE2)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_BURST_SIZE2.
|
|
#define BF_IPU_VDI_C_VDI_BURST_SIZE2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_BURST_SIZE2) & BM_IPU_VDI_C_VDI_BURST_SIZE2)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_BURST_SIZE2 field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_BURST_SIZE2(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_BURST_SIZE2) | BF_IPU_VDI_C_VDI_BURST_SIZE2(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_BURST_SIZE3[15:12] (RW)
|
|
*
|
|
* Burst Size for channel 3. The VDI C 's burst size is restrict by the IDMAC's restriction - This
|
|
* value must match the IDMAC settings and follow the IDMAC's restrictions
|
|
*
|
|
* Values:
|
|
* - 0 - Burst size is 1 access.
|
|
* - 1 - Burst size is 2 accesses.
|
|
* - 15 - Burst size is 16 accesses.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_BURST_SIZE3 (12) //!< Bit position for IPU_VDI_C_VDI_BURST_SIZE3.
|
|
#define BM_IPU_VDI_C_VDI_BURST_SIZE3 (0x0000f000) //!< Bit mask for IPU_VDI_C_VDI_BURST_SIZE3.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_BURST_SIZE3 from a register value.
|
|
#define BG_IPU_VDI_C_VDI_BURST_SIZE3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_BURST_SIZE3) >> BP_IPU_VDI_C_VDI_BURST_SIZE3)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_BURST_SIZE3.
|
|
#define BF_IPU_VDI_C_VDI_BURST_SIZE3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_BURST_SIZE3) & BM_IPU_VDI_C_VDI_BURST_SIZE3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_BURST_SIZE3 field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_BURST_SIZE3(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_BURST_SIZE3) | BF_IPU_VDI_C_VDI_BURST_SIZE3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_VWM1_SET[18:16] (RW)
|
|
*
|
|
* VDI C WaterMark "set" level for channel 1 or channel 2 (channels 1 and 4 are not working
|
|
* simultaneously).
|
|
*
|
|
* Values:
|
|
* - 0 - set watermark level when FIFO1 is full on 1/8 of their size.
|
|
* - 1 - set watermark level when FIFO1 is full on 2/8 of their size.
|
|
* - 7 - set watermark level when FIFO1 is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_VWM1_SET (16) //!< Bit position for IPU_VDI_C_VDI_VWM1_SET.
|
|
#define BM_IPU_VDI_C_VDI_VWM1_SET (0x00070000) //!< Bit mask for IPU_VDI_C_VDI_VWM1_SET.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_VWM1_SET from a register value.
|
|
#define BG_IPU_VDI_C_VDI_VWM1_SET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_VWM1_SET) >> BP_IPU_VDI_C_VDI_VWM1_SET)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_VWM1_SET.
|
|
#define BF_IPU_VDI_C_VDI_VWM1_SET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_VWM1_SET) & BM_IPU_VDI_C_VDI_VWM1_SET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_VWM1_SET field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_VWM1_SET(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_VWM1_SET) | BF_IPU_VDI_C_VDI_VWM1_SET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_VWM1_CLR[21:19] (RW)
|
|
*
|
|
* VDI C WaterMark "clear" level for channel 1 or channel 4 (channels 1 and 4 are not working
|
|
* simultaneously).
|
|
*
|
|
* Values:
|
|
* - 0 - clear watermark level when FIFO1 is full on 1/8 of their size.
|
|
* - 1 - clear watermark level when FIFO1 is full on 2/8 of their size.
|
|
* - 7 - clear watermark level when FIFO1 is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_VWM1_CLR (19) //!< Bit position for IPU_VDI_C_VDI_VWM1_CLR.
|
|
#define BM_IPU_VDI_C_VDI_VWM1_CLR (0x00380000) //!< Bit mask for IPU_VDI_C_VDI_VWM1_CLR.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_VWM1_CLR from a register value.
|
|
#define BG_IPU_VDI_C_VDI_VWM1_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_VWM1_CLR) >> BP_IPU_VDI_C_VDI_VWM1_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_VWM1_CLR.
|
|
#define BF_IPU_VDI_C_VDI_VWM1_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_VWM1_CLR) & BM_IPU_VDI_C_VDI_VWM1_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_VWM1_CLR field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_VWM1_CLR(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_VWM1_CLR) | BF_IPU_VDI_C_VDI_VWM1_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_VWM3_SET[24:22] (RW)
|
|
*
|
|
* VDI C WaterMark "set" level for channel 3.
|
|
*
|
|
* Values:
|
|
* - 0 - set watermark level when FIFO3 is full on 1/8 of their size.
|
|
* - 1 - set watermark level when FIFO3 is full on 2/8 of their size.
|
|
* - 7 - set watermark level when FIFO3 is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_VWM3_SET (22) //!< Bit position for IPU_VDI_C_VDI_VWM3_SET.
|
|
#define BM_IPU_VDI_C_VDI_VWM3_SET (0x01c00000) //!< Bit mask for IPU_VDI_C_VDI_VWM3_SET.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_VWM3_SET from a register value.
|
|
#define BG_IPU_VDI_C_VDI_VWM3_SET(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_VWM3_SET) >> BP_IPU_VDI_C_VDI_VWM3_SET)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_VWM3_SET.
|
|
#define BF_IPU_VDI_C_VDI_VWM3_SET(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_VWM3_SET) & BM_IPU_VDI_C_VDI_VWM3_SET)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_VWM3_SET field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_VWM3_SET(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_VWM3_SET) | BF_IPU_VDI_C_VDI_VWM3_SET(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C, field VDI_VWM3_CLR[27:25] (RW)
|
|
*
|
|
* VDI C WaterMark "clear" level for channel 3.
|
|
*
|
|
* Values:
|
|
* - 0 - clear watermark level when FIFO3 is full on 1/8 of their size.
|
|
* - 1 - clear watermark level when FIFO3 is full on 2/8 of their size.
|
|
* - 7 - clear watermark level when FIFO3 is full.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C_VDI_VWM3_CLR (25) //!< Bit position for IPU_VDI_C_VDI_VWM3_CLR.
|
|
#define BM_IPU_VDI_C_VDI_VWM3_CLR (0x0e000000) //!< Bit mask for IPU_VDI_C_VDI_VWM3_CLR.
|
|
|
|
//! @brief Get value of IPU_VDI_C_VDI_VWM3_CLR from a register value.
|
|
#define BG_IPU_VDI_C_VDI_VWM3_CLR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C_VDI_VWM3_CLR) >> BP_IPU_VDI_C_VDI_VWM3_CLR)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C_VDI_VWM3_CLR.
|
|
#define BF_IPU_VDI_C_VDI_VWM3_CLR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C_VDI_VWM3_CLR) & BM_IPU_VDI_C_VDI_VWM3_CLR)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_VWM3_CLR field to a new value.
|
|
#define BW_IPU_VDI_C_VDI_VWM3_CLR(x, v) (HW_IPU_VDI_C_WR(x, (HW_IPU_VDI_C_RD(x) & ~BM_IPU_VDI_C_VDI_VWM3_CLR) | BF_IPU_VDI_C_VDI_VWM3_CLR(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_C2 - VDI Control Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_C2 - VDI Control Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register used to control modes of operations of VDIC module.
|
|
*/
|
|
typedef union _hw_ipu_vdi_c2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_c2_bitfields
|
|
{
|
|
unsigned VDI_CMB_EN : 1; //!< [0] Combining enable
|
|
unsigned VDI_KEY_COLOR_EN : 1; //!< [1] Key Color Enable
|
|
unsigned VDI_GLB_A_EN : 1; //!< [2] Global alpha enable
|
|
unsigned VDI_PLANE_1_EN : 1; //!< [3] Plane 1 enable
|
|
unsigned RESERVED0 : 28; //!< [31:4] Reserved
|
|
} B;
|
|
} hw_ipu_vdi_c2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_C2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_C2_ADDR(x) (REGS_IPU_BASE(x) + 0x68008)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_C2(x) (*(volatile hw_ipu_vdi_c2_t *) HW_IPU_VDI_C2_ADDR(x))
|
|
#define HW_IPU_VDI_C2_RD(x) (HW_IPU_VDI_C2(x).U)
|
|
#define HW_IPU_VDI_C2_WR(x, v) (HW_IPU_VDI_C2(x).U = (v))
|
|
#define HW_IPU_VDI_C2_SET(x, v) (HW_IPU_VDI_C2_WR(x, HW_IPU_VDI_C2_RD(x) | (v)))
|
|
#define HW_IPU_VDI_C2_CLR(x, v) (HW_IPU_VDI_C2_WR(x, HW_IPU_VDI_C2_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_C2_TOG(x, v) (HW_IPU_VDI_C2_WR(x, HW_IPU_VDI_C2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_C2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_C2, field VDI_CMB_EN[0] (RW)
|
|
*
|
|
* Combining enable
|
|
*
|
|
* Values:
|
|
* - 0 - Combining disabled. The VDIC works in de-interlacing mode
|
|
* - 1 - Combining enabled. The de-interlacing mode is not functional
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C2_VDI_CMB_EN (0) //!< Bit position for IPU_VDI_C2_VDI_CMB_EN.
|
|
#define BM_IPU_VDI_C2_VDI_CMB_EN (0x00000001) //!< Bit mask for IPU_VDI_C2_VDI_CMB_EN.
|
|
|
|
//! @brief Get value of IPU_VDI_C2_VDI_CMB_EN from a register value.
|
|
#define BG_IPU_VDI_C2_VDI_CMB_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C2_VDI_CMB_EN) >> BP_IPU_VDI_C2_VDI_CMB_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C2_VDI_CMB_EN.
|
|
#define BF_IPU_VDI_C2_VDI_CMB_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C2_VDI_CMB_EN) & BM_IPU_VDI_C2_VDI_CMB_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_CMB_EN field to a new value.
|
|
#define BW_IPU_VDI_C2_VDI_CMB_EN(x, v) (HW_IPU_VDI_C2_WR(x, (HW_IPU_VDI_C2_RD(x) & ~BM_IPU_VDI_C2_VDI_CMB_EN) | BF_IPU_VDI_C2_VDI_CMB_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C2, field VDI_KEY_COLOR_EN[1] (RW)
|
|
*
|
|
* Key Color Enable
|
|
*
|
|
* Values:
|
|
* - 0 - Key Color disabled.
|
|
* - 1 - Key color enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C2_VDI_KEY_COLOR_EN (1) //!< Bit position for IPU_VDI_C2_VDI_KEY_COLOR_EN.
|
|
#define BM_IPU_VDI_C2_VDI_KEY_COLOR_EN (0x00000002) //!< Bit mask for IPU_VDI_C2_VDI_KEY_COLOR_EN.
|
|
|
|
//! @brief Get value of IPU_VDI_C2_VDI_KEY_COLOR_EN from a register value.
|
|
#define BG_IPU_VDI_C2_VDI_KEY_COLOR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C2_VDI_KEY_COLOR_EN) >> BP_IPU_VDI_C2_VDI_KEY_COLOR_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C2_VDI_KEY_COLOR_EN.
|
|
#define BF_IPU_VDI_C2_VDI_KEY_COLOR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C2_VDI_KEY_COLOR_EN) & BM_IPU_VDI_C2_VDI_KEY_COLOR_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_KEY_COLOR_EN field to a new value.
|
|
#define BW_IPU_VDI_C2_VDI_KEY_COLOR_EN(x, v) (HW_IPU_VDI_C2_WR(x, (HW_IPU_VDI_C2_RD(x) & ~BM_IPU_VDI_C2_VDI_KEY_COLOR_EN) | BF_IPU_VDI_C2_VDI_KEY_COLOR_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C2, field VDI_GLB_A_EN[2] (RW)
|
|
*
|
|
* Global alpha enable
|
|
*
|
|
* Values:
|
|
* - 0 - Alpha is local
|
|
* - 1 - Alpha is global
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C2_VDI_GLB_A_EN (2) //!< Bit position for IPU_VDI_C2_VDI_GLB_A_EN.
|
|
#define BM_IPU_VDI_C2_VDI_GLB_A_EN (0x00000004) //!< Bit mask for IPU_VDI_C2_VDI_GLB_A_EN.
|
|
|
|
//! @brief Get value of IPU_VDI_C2_VDI_GLB_A_EN from a register value.
|
|
#define BG_IPU_VDI_C2_VDI_GLB_A_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C2_VDI_GLB_A_EN) >> BP_IPU_VDI_C2_VDI_GLB_A_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C2_VDI_GLB_A_EN.
|
|
#define BF_IPU_VDI_C2_VDI_GLB_A_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C2_VDI_GLB_A_EN) & BM_IPU_VDI_C2_VDI_GLB_A_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_GLB_A_EN field to a new value.
|
|
#define BW_IPU_VDI_C2_VDI_GLB_A_EN(x, v) (HW_IPU_VDI_C2_WR(x, (HW_IPU_VDI_C2_RD(x) & ~BM_IPU_VDI_C2_VDI_GLB_A_EN) | BF_IPU_VDI_C2_VDI_GLB_A_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_C2, field VDI_PLANE_1_EN[3] (RW)
|
|
*
|
|
* Plane 1 enable
|
|
*
|
|
* Values:
|
|
* - 0 - plane #1 is disabled
|
|
* - 1 - plane #1 is enabled
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_C2_VDI_PLANE_1_EN (3) //!< Bit position for IPU_VDI_C2_VDI_PLANE_1_EN.
|
|
#define BM_IPU_VDI_C2_VDI_PLANE_1_EN (0x00000008) //!< Bit mask for IPU_VDI_C2_VDI_PLANE_1_EN.
|
|
|
|
//! @brief Get value of IPU_VDI_C2_VDI_PLANE_1_EN from a register value.
|
|
#define BG_IPU_VDI_C2_VDI_PLANE_1_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_C2_VDI_PLANE_1_EN) >> BP_IPU_VDI_C2_VDI_PLANE_1_EN)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_C2_VDI_PLANE_1_EN.
|
|
#define BF_IPU_VDI_C2_VDI_PLANE_1_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_C2_VDI_PLANE_1_EN) & BM_IPU_VDI_C2_VDI_PLANE_1_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_PLANE_1_EN field to a new value.
|
|
#define BW_IPU_VDI_C2_VDI_PLANE_1_EN(x, v) (HW_IPU_VDI_C2_WR(x, (HW_IPU_VDI_C2_RD(x) & ~BM_IPU_VDI_C2_VDI_PLANE_1_EN) | BF_IPU_VDI_C2_VDI_PLANE_1_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_CMDP_1 - VDI Combining Parameters Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_CMDP_1 - VDI Combining Parameters Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register holds combining paramemters.
|
|
*/
|
|
typedef union _hw_ipu_vdi_cmdp_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_cmdp_1_bitfields
|
|
{
|
|
unsigned VDI_KEY_COLOR_B : 8; //!< [7:0] Blue component of Key Color
|
|
unsigned VDI_KEY_COLOR_G : 8; //!< [15:8] Green component of Key Color
|
|
unsigned VDI_KEY_COLOR_R : 8; //!< [23:16] Red component of Key Color
|
|
unsigned VDI_ALPHA : 8; //!< [31:24] Global Alpha
|
|
} B;
|
|
} hw_ipu_vdi_cmdp_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_CMDP_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_CMDP_1_ADDR(x) (REGS_IPU_BASE(x) + 0x6800c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
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#define HW_IPU_VDI_CMDP_1(x) (*(volatile hw_ipu_vdi_cmdp_1_t *) HW_IPU_VDI_CMDP_1_ADDR(x))
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#define HW_IPU_VDI_CMDP_1_RD(x) (HW_IPU_VDI_CMDP_1(x).U)
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#define HW_IPU_VDI_CMDP_1_WR(x, v) (HW_IPU_VDI_CMDP_1(x).U = (v))
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#define HW_IPU_VDI_CMDP_1_SET(x, v) (HW_IPU_VDI_CMDP_1_WR(x, HW_IPU_VDI_CMDP_1_RD(x) | (v)))
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#define HW_IPU_VDI_CMDP_1_CLR(x, v) (HW_IPU_VDI_CMDP_1_WR(x, HW_IPU_VDI_CMDP_1_RD(x) & ~(v)))
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#define HW_IPU_VDI_CMDP_1_TOG(x, v) (HW_IPU_VDI_CMDP_1_WR(x, HW_IPU_VDI_CMDP_1_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual IPU_VDI_CMDP_1 bitfields
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*/
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/*! @name Register IPU_VDI_CMDP_1, field VDI_KEY_COLOR_B[7:0] (RW)
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*
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* Blue component of Key Color
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*/
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//@{
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#define BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B (0) //!< Bit position for IPU_VDI_CMDP_1_VDI_KEY_COLOR_B.
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#define BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B (0x000000ff) //!< Bit mask for IPU_VDI_CMDP_1_VDI_KEY_COLOR_B.
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//! @brief Get value of IPU_VDI_CMDP_1_VDI_KEY_COLOR_B from a register value.
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#define BG_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B) >> BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B)
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//! @brief Format value for bitfield IPU_VDI_CMDP_1_VDI_KEY_COLOR_B.
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#define BF_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B) & BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the VDI_KEY_COLOR_B field to a new value.
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#define BW_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B(x, v) (HW_IPU_VDI_CMDP_1_WR(x, (HW_IPU_VDI_CMDP_1_RD(x) & ~BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B) | BF_IPU_VDI_CMDP_1_VDI_KEY_COLOR_B(v)))
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#endif
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//@}
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/*! @name Register IPU_VDI_CMDP_1, field VDI_KEY_COLOR_G[15:8] (RW)
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*
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* Green component of Key Color
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*/
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//@{
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#define BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G (8) //!< Bit position for IPU_VDI_CMDP_1_VDI_KEY_COLOR_G.
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#define BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G (0x0000ff00) //!< Bit mask for IPU_VDI_CMDP_1_VDI_KEY_COLOR_G.
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//! @brief Get value of IPU_VDI_CMDP_1_VDI_KEY_COLOR_G from a register value.
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#define BG_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G) >> BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G)
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//! @brief Format value for bitfield IPU_VDI_CMDP_1_VDI_KEY_COLOR_G.
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#define BF_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G) & BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the VDI_KEY_COLOR_G field to a new value.
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#define BW_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G(x, v) (HW_IPU_VDI_CMDP_1_WR(x, (HW_IPU_VDI_CMDP_1_RD(x) & ~BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G) | BF_IPU_VDI_CMDP_1_VDI_KEY_COLOR_G(v)))
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#endif
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//@}
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/*! @name Register IPU_VDI_CMDP_1, field VDI_KEY_COLOR_R[23:16] (RW)
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*
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* Red component of Key Color
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*/
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//@{
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#define BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R (16) //!< Bit position for IPU_VDI_CMDP_1_VDI_KEY_COLOR_R.
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#define BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R (0x00ff0000) //!< Bit mask for IPU_VDI_CMDP_1_VDI_KEY_COLOR_R.
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//! @brief Get value of IPU_VDI_CMDP_1_VDI_KEY_COLOR_R from a register value.
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#define BG_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R) >> BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R)
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//! @brief Format value for bitfield IPU_VDI_CMDP_1_VDI_KEY_COLOR_R.
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#define BF_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R) & BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the VDI_KEY_COLOR_R field to a new value.
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#define BW_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R(x, v) (HW_IPU_VDI_CMDP_1_WR(x, (HW_IPU_VDI_CMDP_1_RD(x) & ~BM_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R) | BF_IPU_VDI_CMDP_1_VDI_KEY_COLOR_R(v)))
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#endif
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//@}
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/*! @name Register IPU_VDI_CMDP_1, field VDI_ALPHA[31:24] (RW)
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*
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* Global Alpha Actual value of the alpha is VDI_ALPHA + VDI_ALPHA[7]
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*/
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//@{
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#define BP_IPU_VDI_CMDP_1_VDI_ALPHA (24) //!< Bit position for IPU_VDI_CMDP_1_VDI_ALPHA.
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#define BM_IPU_VDI_CMDP_1_VDI_ALPHA (0xff000000) //!< Bit mask for IPU_VDI_CMDP_1_VDI_ALPHA.
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//! @brief Get value of IPU_VDI_CMDP_1_VDI_ALPHA from a register value.
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#define BG_IPU_VDI_CMDP_1_VDI_ALPHA(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_1_VDI_ALPHA) >> BP_IPU_VDI_CMDP_1_VDI_ALPHA)
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//! @brief Format value for bitfield IPU_VDI_CMDP_1_VDI_ALPHA.
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#define BF_IPU_VDI_CMDP_1_VDI_ALPHA(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_1_VDI_ALPHA) & BM_IPU_VDI_CMDP_1_VDI_ALPHA)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the VDI_ALPHA field to a new value.
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#define BW_IPU_VDI_CMDP_1_VDI_ALPHA(x, v) (HW_IPU_VDI_CMDP_1_WR(x, (HW_IPU_VDI_CMDP_1_RD(x) & ~BM_IPU_VDI_CMDP_1_VDI_ALPHA) | BF_IPU_VDI_CMDP_1_VDI_ALPHA(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_IPU_VDI_CMDP_2 - VDI Combining Parameters Register 2
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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|
/*!
|
|
* @brief HW_IPU_VDI_CMDP_2 - VDI Combining Parameters Register 2 (RW)
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|
*
|
|
* Reset value: 0x00000000
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|
*
|
|
* The register holds combining paramemters.
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|
*/
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|
typedef union _hw_ipu_vdi_cmdp_2
|
|
{
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|
reg32_t U;
|
|
struct _hw_ipu_vdi_cmdp_2_bitfields
|
|
{
|
|
unsigned VDI_KEY_COLOR_B : 8; //!< [7:0] Blue component of background Color
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unsigned VDI_KEY_COLOR_G : 8; //!< [15:8] Green component of background Color
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unsigned VDI_KEY_COLOR_R : 8; //!< [23:16] Red component of background Color
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unsigned RESERVED0 : 8; //!< [31:24] Reserved
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} B;
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|
} hw_ipu_vdi_cmdp_2_t;
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|
#endif
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/*!
|
|
* @name Constants and macros for entire IPU_VDI_CMDP_2 register
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|
*/
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|
//@{
|
|
#define HW_IPU_VDI_CMDP_2_ADDR(x) (REGS_IPU_BASE(x) + 0x68010)
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|
#ifndef __LANGUAGE_ASM__
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|
#define HW_IPU_VDI_CMDP_2(x) (*(volatile hw_ipu_vdi_cmdp_2_t *) HW_IPU_VDI_CMDP_2_ADDR(x))
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#define HW_IPU_VDI_CMDP_2_RD(x) (HW_IPU_VDI_CMDP_2(x).U)
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#define HW_IPU_VDI_CMDP_2_WR(x, v) (HW_IPU_VDI_CMDP_2(x).U = (v))
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#define HW_IPU_VDI_CMDP_2_SET(x, v) (HW_IPU_VDI_CMDP_2_WR(x, HW_IPU_VDI_CMDP_2_RD(x) | (v)))
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#define HW_IPU_VDI_CMDP_2_CLR(x, v) (HW_IPU_VDI_CMDP_2_WR(x, HW_IPU_VDI_CMDP_2_RD(x) & ~(v)))
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#define HW_IPU_VDI_CMDP_2_TOG(x, v) (HW_IPU_VDI_CMDP_2_WR(x, HW_IPU_VDI_CMDP_2_RD(x) ^ (v)))
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#endif
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//@}
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|
|
/*
|
|
* constants & macros for individual IPU_VDI_CMDP_2 bitfields
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|
*/
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/*! @name Register IPU_VDI_CMDP_2, field VDI_KEY_COLOR_B[7:0] (RW)
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|
*
|
|
* Blue component of background Color
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|
*/
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|
//@{
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|
#define BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B (0) //!< Bit position for IPU_VDI_CMDP_2_VDI_KEY_COLOR_B.
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|
#define BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B (0x000000ff) //!< Bit mask for IPU_VDI_CMDP_2_VDI_KEY_COLOR_B.
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|
|
//! @brief Get value of IPU_VDI_CMDP_2_VDI_KEY_COLOR_B from a register value.
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|
#define BG_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B) >> BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B)
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//! @brief Format value for bitfield IPU_VDI_CMDP_2_VDI_KEY_COLOR_B.
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|
#define BF_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B) & BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B)
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|
|
#ifndef __LANGUAGE_ASM__
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|
//! @brief Set the VDI_KEY_COLOR_B field to a new value.
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|
#define BW_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B(x, v) (HW_IPU_VDI_CMDP_2_WR(x, (HW_IPU_VDI_CMDP_2_RD(x) & ~BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B) | BF_IPU_VDI_CMDP_2_VDI_KEY_COLOR_B(v)))
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#endif
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//@}
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/*! @name Register IPU_VDI_CMDP_2, field VDI_KEY_COLOR_G[15:8] (RW)
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|
*
|
|
* Green component of background Color
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|
*/
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|
//@{
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|
#define BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G (8) //!< Bit position for IPU_VDI_CMDP_2_VDI_KEY_COLOR_G.
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#define BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G (0x0000ff00) //!< Bit mask for IPU_VDI_CMDP_2_VDI_KEY_COLOR_G.
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|
//! @brief Get value of IPU_VDI_CMDP_2_VDI_KEY_COLOR_G from a register value.
|
|
#define BG_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G) >> BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G)
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|
|
//! @brief Format value for bitfield IPU_VDI_CMDP_2_VDI_KEY_COLOR_G.
|
|
#define BF_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G) & BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G)
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|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_KEY_COLOR_G field to a new value.
|
|
#define BW_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G(x, v) (HW_IPU_VDI_CMDP_2_WR(x, (HW_IPU_VDI_CMDP_2_RD(x) & ~BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G) | BF_IPU_VDI_CMDP_2_VDI_KEY_COLOR_G(v)))
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|
#endif
|
|
//@}
|
|
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|
/*! @name Register IPU_VDI_CMDP_2, field VDI_KEY_COLOR_R[23:16] (RW)
|
|
*
|
|
* Red component of background Color
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R (16) //!< Bit position for IPU_VDI_CMDP_2_VDI_KEY_COLOR_R.
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#define BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R (0x00ff0000) //!< Bit mask for IPU_VDI_CMDP_2_VDI_KEY_COLOR_R.
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|
|
//! @brief Get value of IPU_VDI_CMDP_2_VDI_KEY_COLOR_R from a register value.
|
|
#define BG_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R) >> BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R)
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|
|
|
//! @brief Format value for bitfield IPU_VDI_CMDP_2_VDI_KEY_COLOR_R.
|
|
#define BF_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R) & BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_KEY_COLOR_R field to a new value.
|
|
#define BW_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R(x, v) (HW_IPU_VDI_CMDP_2_WR(x, (HW_IPU_VDI_CMDP_2_RD(x) & ~BM_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R) | BF_IPU_VDI_CMDP_2_VDI_KEY_COLOR_R(v)))
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|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_PS_1 - VDI Plane Size Register 1
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_PS_1 - VDI Plane Size Register 1 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register holds the plane size's paramemters.
|
|
*/
|
|
typedef union _hw_ipu_vdi_ps_1
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_ps_1_bitfields
|
|
{
|
|
unsigned VDI_FWIDTH1 : 11; //!< [10:0] Plane 1 width.
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned VDI_FHEIGHT1 : 11; //!< [26:16] Plane 1 height
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_vdi_ps_1_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_PS_1 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_PS_1_ADDR(x) (REGS_IPU_BASE(x) + 0x68014)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_PS_1(x) (*(volatile hw_ipu_vdi_ps_1_t *) HW_IPU_VDI_PS_1_ADDR(x))
|
|
#define HW_IPU_VDI_PS_1_RD(x) (HW_IPU_VDI_PS_1(x).U)
|
|
#define HW_IPU_VDI_PS_1_WR(x, v) (HW_IPU_VDI_PS_1(x).U = (v))
|
|
#define HW_IPU_VDI_PS_1_SET(x, v) (HW_IPU_VDI_PS_1_WR(x, HW_IPU_VDI_PS_1_RD(x) | (v)))
|
|
#define HW_IPU_VDI_PS_1_CLR(x, v) (HW_IPU_VDI_PS_1_WR(x, HW_IPU_VDI_PS_1_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_PS_1_TOG(x, v) (HW_IPU_VDI_PS_1_WR(x, HW_IPU_VDI_PS_1_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_PS_1 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_PS_1, field VDI_FWIDTH1[10:0] (RW)
|
|
*
|
|
* Plane 1 width. The value to be written to this register is the plane's width minus 1. The Plane
|
|
* width should not be smaller than 16. The Plane width should not be greater than 1920. The width
|
|
* must be even.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_1_VDI_FWIDTH1 (0) //!< Bit position for IPU_VDI_PS_1_VDI_FWIDTH1.
|
|
#define BM_IPU_VDI_PS_1_VDI_FWIDTH1 (0x000007ff) //!< Bit mask for IPU_VDI_PS_1_VDI_FWIDTH1.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_1_VDI_FWIDTH1 from a register value.
|
|
#define BG_IPU_VDI_PS_1_VDI_FWIDTH1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_1_VDI_FWIDTH1) >> BP_IPU_VDI_PS_1_VDI_FWIDTH1)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_1_VDI_FWIDTH1.
|
|
#define BF_IPU_VDI_PS_1_VDI_FWIDTH1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_1_VDI_FWIDTH1) & BM_IPU_VDI_PS_1_VDI_FWIDTH1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FWIDTH1 field to a new value.
|
|
#define BW_IPU_VDI_PS_1_VDI_FWIDTH1(x, v) (HW_IPU_VDI_PS_1_WR(x, (HW_IPU_VDI_PS_1_RD(x) & ~BM_IPU_VDI_PS_1_VDI_FWIDTH1) | BF_IPU_VDI_PS_1_VDI_FWIDTH1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_PS_1, field VDI_FHEIGHT1[26:16] (RW)
|
|
*
|
|
* Plane 1 height The value to be written to this register is the plane's height minus 1. The Plane
|
|
* height should not be smaller than 16. The Plane height should not be greater than 1200. The
|
|
* Plane's height must be even
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_1_VDI_FHEIGHT1 (16) //!< Bit position for IPU_VDI_PS_1_VDI_FHEIGHT1.
|
|
#define BM_IPU_VDI_PS_1_VDI_FHEIGHT1 (0x07ff0000) //!< Bit mask for IPU_VDI_PS_1_VDI_FHEIGHT1.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_1_VDI_FHEIGHT1 from a register value.
|
|
#define BG_IPU_VDI_PS_1_VDI_FHEIGHT1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_1_VDI_FHEIGHT1) >> BP_IPU_VDI_PS_1_VDI_FHEIGHT1)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_1_VDI_FHEIGHT1.
|
|
#define BF_IPU_VDI_PS_1_VDI_FHEIGHT1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_1_VDI_FHEIGHT1) & BM_IPU_VDI_PS_1_VDI_FHEIGHT1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FHEIGHT1 field to a new value.
|
|
#define BW_IPU_VDI_PS_1_VDI_FHEIGHT1(x, v) (HW_IPU_VDI_PS_1_WR(x, (HW_IPU_VDI_PS_1_RD(x) & ~BM_IPU_VDI_PS_1_VDI_FHEIGHT1) | BF_IPU_VDI_PS_1_VDI_FHEIGHT1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_PS_2 - VDI Plane Size Register 2
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_PS_2 - VDI Plane Size Register 2 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register holds the plane's offset paramemters.
|
|
*/
|
|
typedef union _hw_ipu_vdi_ps_2
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_ps_2_bitfields
|
|
{
|
|
unsigned VDI_OFFSET_HOR1 : 11; //!< [10:0] Horizontal offset of plane 1
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned VDI_OFFSET_VER1 : 11; //!< [26:16] Vertical offset of plane 1
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_vdi_ps_2_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_PS_2 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_PS_2_ADDR(x) (REGS_IPU_BASE(x) + 0x68018)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_PS_2(x) (*(volatile hw_ipu_vdi_ps_2_t *) HW_IPU_VDI_PS_2_ADDR(x))
|
|
#define HW_IPU_VDI_PS_2_RD(x) (HW_IPU_VDI_PS_2(x).U)
|
|
#define HW_IPU_VDI_PS_2_WR(x, v) (HW_IPU_VDI_PS_2(x).U = (v))
|
|
#define HW_IPU_VDI_PS_2_SET(x, v) (HW_IPU_VDI_PS_2_WR(x, HW_IPU_VDI_PS_2_RD(x) | (v)))
|
|
#define HW_IPU_VDI_PS_2_CLR(x, v) (HW_IPU_VDI_PS_2_WR(x, HW_IPU_VDI_PS_2_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_PS_2_TOG(x, v) (HW_IPU_VDI_PS_2_WR(x, HW_IPU_VDI_PS_2_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_PS_2 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_PS_2, field VDI_OFFSET_HOR1[10:0] (RW)
|
|
*
|
|
* Horizontal offset of plane 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_2_VDI_OFFSET_HOR1 (0) //!< Bit position for IPU_VDI_PS_2_VDI_OFFSET_HOR1.
|
|
#define BM_IPU_VDI_PS_2_VDI_OFFSET_HOR1 (0x000007ff) //!< Bit mask for IPU_VDI_PS_2_VDI_OFFSET_HOR1.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_2_VDI_OFFSET_HOR1 from a register value.
|
|
#define BG_IPU_VDI_PS_2_VDI_OFFSET_HOR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_2_VDI_OFFSET_HOR1) >> BP_IPU_VDI_PS_2_VDI_OFFSET_HOR1)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_2_VDI_OFFSET_HOR1.
|
|
#define BF_IPU_VDI_PS_2_VDI_OFFSET_HOR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_2_VDI_OFFSET_HOR1) & BM_IPU_VDI_PS_2_VDI_OFFSET_HOR1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_OFFSET_HOR1 field to a new value.
|
|
#define BW_IPU_VDI_PS_2_VDI_OFFSET_HOR1(x, v) (HW_IPU_VDI_PS_2_WR(x, (HW_IPU_VDI_PS_2_RD(x) & ~BM_IPU_VDI_PS_2_VDI_OFFSET_HOR1) | BF_IPU_VDI_PS_2_VDI_OFFSET_HOR1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_PS_2, field VDI_OFFSET_VER1[26:16] (RW)
|
|
*
|
|
* Vertical offset of plane 1
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_2_VDI_OFFSET_VER1 (16) //!< Bit position for IPU_VDI_PS_2_VDI_OFFSET_VER1.
|
|
#define BM_IPU_VDI_PS_2_VDI_OFFSET_VER1 (0x07ff0000) //!< Bit mask for IPU_VDI_PS_2_VDI_OFFSET_VER1.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_2_VDI_OFFSET_VER1 from a register value.
|
|
#define BG_IPU_VDI_PS_2_VDI_OFFSET_VER1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_2_VDI_OFFSET_VER1) >> BP_IPU_VDI_PS_2_VDI_OFFSET_VER1)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_2_VDI_OFFSET_VER1.
|
|
#define BF_IPU_VDI_PS_2_VDI_OFFSET_VER1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_2_VDI_OFFSET_VER1) & BM_IPU_VDI_PS_2_VDI_OFFSET_VER1)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_OFFSET_VER1 field to a new value.
|
|
#define BW_IPU_VDI_PS_2_VDI_OFFSET_VER1(x, v) (HW_IPU_VDI_PS_2_WR(x, (HW_IPU_VDI_PS_2_RD(x) & ~BM_IPU_VDI_PS_2_VDI_OFFSET_VER1) | BF_IPU_VDI_PS_2_VDI_OFFSET_VER1(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_PS_3 - VDI Plane Size Register 3
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_PS_3 - VDI Plane Size Register 3 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register holds the plane size's paramemters.
|
|
*/
|
|
typedef union _hw_ipu_vdi_ps_3
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_ps_3_bitfields
|
|
{
|
|
unsigned VDI_FWIDTH3 : 11; //!< [10:0] Plane 3 width.
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned VDI_FHEIGHT3 : 11; //!< [26:16] Plane 3 height
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_vdi_ps_3_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_PS_3 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_PS_3_ADDR(x) (REGS_IPU_BASE(x) + 0x6801c)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_PS_3(x) (*(volatile hw_ipu_vdi_ps_3_t *) HW_IPU_VDI_PS_3_ADDR(x))
|
|
#define HW_IPU_VDI_PS_3_RD(x) (HW_IPU_VDI_PS_3(x).U)
|
|
#define HW_IPU_VDI_PS_3_WR(x, v) (HW_IPU_VDI_PS_3(x).U = (v))
|
|
#define HW_IPU_VDI_PS_3_SET(x, v) (HW_IPU_VDI_PS_3_WR(x, HW_IPU_VDI_PS_3_RD(x) | (v)))
|
|
#define HW_IPU_VDI_PS_3_CLR(x, v) (HW_IPU_VDI_PS_3_WR(x, HW_IPU_VDI_PS_3_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_PS_3_TOG(x, v) (HW_IPU_VDI_PS_3_WR(x, HW_IPU_VDI_PS_3_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_PS_3 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_PS_3, field VDI_FWIDTH3[10:0] (RW)
|
|
*
|
|
* Plane 3 width. The value to be written to this register is the plane's width minus 1. The Plane
|
|
* width should not be smaller than 16. The Plane width should not be greater than 1920. The width
|
|
* must be even.
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_3_VDI_FWIDTH3 (0) //!< Bit position for IPU_VDI_PS_3_VDI_FWIDTH3.
|
|
#define BM_IPU_VDI_PS_3_VDI_FWIDTH3 (0x000007ff) //!< Bit mask for IPU_VDI_PS_3_VDI_FWIDTH3.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_3_VDI_FWIDTH3 from a register value.
|
|
#define BG_IPU_VDI_PS_3_VDI_FWIDTH3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_3_VDI_FWIDTH3) >> BP_IPU_VDI_PS_3_VDI_FWIDTH3)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_3_VDI_FWIDTH3.
|
|
#define BF_IPU_VDI_PS_3_VDI_FWIDTH3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_3_VDI_FWIDTH3) & BM_IPU_VDI_PS_3_VDI_FWIDTH3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FWIDTH3 field to a new value.
|
|
#define BW_IPU_VDI_PS_3_VDI_FWIDTH3(x, v) (HW_IPU_VDI_PS_3_WR(x, (HW_IPU_VDI_PS_3_RD(x) & ~BM_IPU_VDI_PS_3_VDI_FWIDTH3) | BF_IPU_VDI_PS_3_VDI_FWIDTH3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_PS_3, field VDI_FHEIGHT3[26:16] (RW)
|
|
*
|
|
* Plane 3 height The value to be written to this register is the plane's height minus 1. The Plane
|
|
* height should not be smaller than 16. The Plane height should not be greater than 1200. The
|
|
* Plane's height must be even
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_3_VDI_FHEIGHT3 (16) //!< Bit position for IPU_VDI_PS_3_VDI_FHEIGHT3.
|
|
#define BM_IPU_VDI_PS_3_VDI_FHEIGHT3 (0x07ff0000) //!< Bit mask for IPU_VDI_PS_3_VDI_FHEIGHT3.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_3_VDI_FHEIGHT3 from a register value.
|
|
#define BG_IPU_VDI_PS_3_VDI_FHEIGHT3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_3_VDI_FHEIGHT3) >> BP_IPU_VDI_PS_3_VDI_FHEIGHT3)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_3_VDI_FHEIGHT3.
|
|
#define BF_IPU_VDI_PS_3_VDI_FHEIGHT3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_3_VDI_FHEIGHT3) & BM_IPU_VDI_PS_3_VDI_FHEIGHT3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_FHEIGHT3 field to a new value.
|
|
#define BW_IPU_VDI_PS_3_VDI_FHEIGHT3(x, v) (HW_IPU_VDI_PS_3_WR(x, (HW_IPU_VDI_PS_3_RD(x) & ~BM_IPU_VDI_PS_3_VDI_FHEIGHT3) | BF_IPU_VDI_PS_3_VDI_FHEIGHT3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_IPU_VDI_PS_4 - VDI Plane Size Register 4
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_IPU_VDI_PS_4 - VDI Plane Size Register 4 (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The register holds the plane's offset paramemters.
|
|
*/
|
|
typedef union _hw_ipu_vdi_ps_4
|
|
{
|
|
reg32_t U;
|
|
struct _hw_ipu_vdi_ps_4_bitfields
|
|
{
|
|
unsigned VDI_OFFSET_HOR3 : 11; //!< [10:0] Horizontal offset of plane 3
|
|
unsigned RESERVED0 : 5; //!< [15:11] Reserved
|
|
unsigned VDI_OFFSET_VER3 : 11; //!< [26:16] Vertical offset of plane 3
|
|
unsigned RESERVED1 : 5; //!< [31:27] Reserved.
|
|
} B;
|
|
} hw_ipu_vdi_ps_4_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire IPU_VDI_PS_4 register
|
|
*/
|
|
//@{
|
|
#define HW_IPU_VDI_PS_4_ADDR(x) (REGS_IPU_BASE(x) + 0x68020)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_IPU_VDI_PS_4(x) (*(volatile hw_ipu_vdi_ps_4_t *) HW_IPU_VDI_PS_4_ADDR(x))
|
|
#define HW_IPU_VDI_PS_4_RD(x) (HW_IPU_VDI_PS_4(x).U)
|
|
#define HW_IPU_VDI_PS_4_WR(x, v) (HW_IPU_VDI_PS_4(x).U = (v))
|
|
#define HW_IPU_VDI_PS_4_SET(x, v) (HW_IPU_VDI_PS_4_WR(x, HW_IPU_VDI_PS_4_RD(x) | (v)))
|
|
#define HW_IPU_VDI_PS_4_CLR(x, v) (HW_IPU_VDI_PS_4_WR(x, HW_IPU_VDI_PS_4_RD(x) & ~(v)))
|
|
#define HW_IPU_VDI_PS_4_TOG(x, v) (HW_IPU_VDI_PS_4_WR(x, HW_IPU_VDI_PS_4_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual IPU_VDI_PS_4 bitfields
|
|
*/
|
|
|
|
/*! @name Register IPU_VDI_PS_4, field VDI_OFFSET_HOR3[10:0] (RW)
|
|
*
|
|
* Horizontal offset of plane 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_4_VDI_OFFSET_HOR3 (0) //!< Bit position for IPU_VDI_PS_4_VDI_OFFSET_HOR3.
|
|
#define BM_IPU_VDI_PS_4_VDI_OFFSET_HOR3 (0x000007ff) //!< Bit mask for IPU_VDI_PS_4_VDI_OFFSET_HOR3.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_4_VDI_OFFSET_HOR3 from a register value.
|
|
#define BG_IPU_VDI_PS_4_VDI_OFFSET_HOR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_4_VDI_OFFSET_HOR3) >> BP_IPU_VDI_PS_4_VDI_OFFSET_HOR3)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_4_VDI_OFFSET_HOR3.
|
|
#define BF_IPU_VDI_PS_4_VDI_OFFSET_HOR3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_4_VDI_OFFSET_HOR3) & BM_IPU_VDI_PS_4_VDI_OFFSET_HOR3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_OFFSET_HOR3 field to a new value.
|
|
#define BW_IPU_VDI_PS_4_VDI_OFFSET_HOR3(x, v) (HW_IPU_VDI_PS_4_WR(x, (HW_IPU_VDI_PS_4_RD(x) & ~BM_IPU_VDI_PS_4_VDI_OFFSET_HOR3) | BF_IPU_VDI_PS_4_VDI_OFFSET_HOR3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register IPU_VDI_PS_4, field VDI_OFFSET_VER3[26:16] (RW)
|
|
*
|
|
* Vertical offset of plane 3
|
|
*/
|
|
//@{
|
|
#define BP_IPU_VDI_PS_4_VDI_OFFSET_VER3 (16) //!< Bit position for IPU_VDI_PS_4_VDI_OFFSET_VER3.
|
|
#define BM_IPU_VDI_PS_4_VDI_OFFSET_VER3 (0x07ff0000) //!< Bit mask for IPU_VDI_PS_4_VDI_OFFSET_VER3.
|
|
|
|
//! @brief Get value of IPU_VDI_PS_4_VDI_OFFSET_VER3 from a register value.
|
|
#define BG_IPU_VDI_PS_4_VDI_OFFSET_VER3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_IPU_VDI_PS_4_VDI_OFFSET_VER3) >> BP_IPU_VDI_PS_4_VDI_OFFSET_VER3)
|
|
|
|
//! @brief Format value for bitfield IPU_VDI_PS_4_VDI_OFFSET_VER3.
|
|
#define BF_IPU_VDI_PS_4_VDI_OFFSET_VER3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_IPU_VDI_PS_4_VDI_OFFSET_VER3) & BM_IPU_VDI_PS_4_VDI_OFFSET_VER3)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the VDI_OFFSET_VER3 field to a new value.
|
|
#define BW_IPU_VDI_PS_4_VDI_OFFSET_VER3(x, v) (HW_IPU_VDI_PS_4_WR(x, (HW_IPU_VDI_PS_4_RD(x) & ~BM_IPU_VDI_PS_4_VDI_OFFSET_VER3) | BF_IPU_VDI_PS_4_VDI_OFFSET_VER3(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// hw_ipu_t - module struct
|
|
//-------------------------------------------------------------------------------------------
|
|
/*!
|
|
* @brief All IPU module registers.
|
|
*/
|
|
#ifndef __LANGUAGE_ASM__
|
|
#pragma pack(1)
|
|
typedef struct _hw_ipu
|
|
{
|
|
volatile hw_ipu_conf_t CONF; //!< Configuration Register
|
|
volatile hw_ipu_sisg_ctrl0_t SISG_CTRL0; //!< SISG Control 0 Register
|
|
volatile hw_ipu_sisg_ctrl1_t SISG_CTRL1; //!< SISG Control 1 Register
|
|
volatile hw_ipu_sisg_set_i_t SISG_SET_I; //!< SISG Set<i> Register
|
|
reg32_t _reserved0[5];
|
|
volatile hw_ipu_sisg_clr_i_t SISG_CLR_I; //!< SISG Clear <i> Register
|
|
reg32_t _reserved1[5];
|
|
volatile hw_ipu_int_ctrl_1_t INT_CTRL_1; //!< Interrupt Control Register 1
|
|
volatile hw_ipu_int_ctrl_2_t INT_CTRL_2; //!< Interrupt Control Register 2
|
|
volatile hw_ipu_int_ctrl_3_t INT_CTRL_3; //!< Interrupt Control Register 3
|
|
volatile hw_ipu_int_ctrl_4_t INT_CTRL_4; //!< Interrupt Control Register 4
|
|
volatile hw_ipu_int_ctrl_5_t INT_CTRL_5; //!< Interrupt Control Register 5
|
|
volatile hw_ipu_int_ctrl_6_t INT_CTRL_6; //!< Interrupt Control Register 6
|
|
volatile hw_ipu_int_ctrl_7_t INT_CTRL_7; //!< Interrupt Control Register 7
|
|
volatile hw_ipu_int_ctrl_8_t INT_CTRL_8; //!< Interrupt Control Register 8
|
|
volatile hw_ipu_int_ctrl_9_t INT_CTRL_9; //!< Interrupt Control Register 9
|
|
volatile hw_ipu_int_ctrl_10_t INT_CTRL_10; //!< Interrupt Control Register 10
|
|
volatile hw_ipu_int_ctrl_11_t INT_CTRL_11; //!< Interrupt Control Register 11
|
|
volatile hw_ipu_int_ctrl_12_t INT_CTRL_12; //!< Interrupt Control Register 12
|
|
volatile hw_ipu_int_ctrl_13_t INT_CTRL_13; //!< Interrupt Control Register 13
|
|
volatile hw_ipu_int_ctrl_14_t INT_CTRL_14; //!< Interrupt Control Register 14
|
|
volatile hw_ipu_int_ctrl_15_t INT_CTRL_15; //!< Interrupt Control Register15
|
|
volatile hw_ipu_sdma_event_1_t SDMA_EVENT_1; //!< SDMA Event Control Register 1
|
|
volatile hw_ipu_sdma_event_2_t SDMA_EVENT_2; //!< SDMA Event Control Register 2
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volatile hw_ipu_sdma_event_3_t SDMA_EVENT_3; //!< SDMA Event Control Register 3
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volatile hw_ipu_sdma_event_4_t SDMA_EVENT_4; //!< SDMA Event Control Register 4
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volatile hw_ipu_sdma_event_7_t SDMA_EVENT_7; //!< SDMA Event Control Register 7
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volatile hw_ipu_sdma_event_8_t SDMA_EVENT_8; //!< SDMA Event Control Register 8
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volatile hw_ipu_sdma_event_11_t SDMA_EVENT_11; //!< SDMA Event Control Register 11
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volatile hw_ipu_sdma_event_12_t SDMA_EVENT_12; //!< SDMA Event Control Register 12
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volatile hw_ipu_sdma_event_13_t SDMA_EVENT_13; //!< SDMA Event Control Register 13
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volatile hw_ipu_sdma_event_14_t SDMA_EVENT_14; //!< SDMA Event Control Register 14
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volatile hw_ipu_srm_pri1_t SRM_PRI1; //!< Shadow Registers Memory Priority 1 Register
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volatile hw_ipu_srm_pri2_t SRM_PRI2; //!< Shadow Registers Memory Priority 2 Register
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volatile hw_ipu_fs_proc_flow1_t FS_PROC_FLOW1; //!< FSU Processing Flow 1 Register
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volatile hw_ipu_fs_proc_flow2_t FS_PROC_FLOW2; //!< FSU Processing Flow 2 Register
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volatile hw_ipu_fs_proc_flow3_t FS_PROC_FLOW3; //!< FSU Processing Flow 3 Register
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volatile hw_ipu_fs_disp_flow1_t FS_DISP_FLOW1; //!< FSU Displaying Flow 1 Register
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volatile hw_ipu_fs_disp_flow2_t FS_DISP_FLOW2; //!< FSU Displaying Flow 2 Register
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volatile hw_ipu_skip_t SKIP; //!< SKIP Register
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volatile hw_ipu_disp_alt_conf_t DISP_ALT_CONF; //!< Display Alternate Configuration Register
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volatile hw_ipu_disp_gen_t DISP_GEN; //!< Display General Control Register
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volatile hw_ipu_disp_alt1_t DISP_ALT1; //!< Display Alternate Flow Control Register 1
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volatile hw_ipu_disp_alt2_t DISP_ALT2; //!< Display Alternate Flow Control Register 2
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volatile hw_ipu_disp_alt3_t DISP_ALT3; //!< Display Alternate Flow Control Register 3
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volatile hw_ipu_disp_alt4_t DISP_ALT4; //!< Display Alternate Flow Control Register 4
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reg32_t _reserved2;
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volatile hw_ipu_mem_rst_t MEM_RST; //!< Memory Reset Control Register
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volatile hw_ipu_pm_t PM; //!< Power Modes Control Register
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volatile hw_ipu_gpr_t GPR; //!< General Purpose Register
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reg32_t _reserved3[27];
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volatile hw_ipu_ch_db_mode_sel1_t CH_DB_MODE_SEL1; //!< Channel Double Buffer Mode Select 1 Register
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reg32_t _reserved4[4];
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volatile hw_ipu_alt_ch_db_mode_sel0_t ALT_CH_DB_MODE_SEL0; //!< Alternate Channel Double Buffer Mode Select 0 Register
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volatile hw_ipu_alt_ch_db_mode_sel1_t ALT_CH_DB_MODE_SEL1; //!< Alternate Channel Double Buffer Mode Select1 Register
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reg32_t _reserved5[2];
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volatile hw_ipu_alt_ch_trb_mode_sel0_t ALT_CH_TRB_MODE_SEL0; //!< Alternate Channel Triple Buffer Mode Select 0 Register
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volatile hw_ipu_alt_ch_trb_mode_sel1_t ALT_CH_TRB_MODE_SEL1; //!< Alternate Channel Triple Buffer Mode Select 1 Register
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reg32_t _reserved6[32];
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volatile hw_ipu_int_stat_1_t INT_STAT_1; //!< Interrupt Status Register 1
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volatile hw_ipu_int_stat_2_t INT_STAT_2; //!< Interrupt Status Register2
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volatile hw_ipu_int_stat_3_t INT_STAT_3; //!< Interrupt Status Register 3
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volatile hw_ipu_int_stat_4_t INT_STAT_4; //!< Interrupt Status Register 4
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volatile hw_ipu_int_stat_5_t INT_STAT_5; //!< Interrupt Status Register 5
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volatile hw_ipu_int_stat_6_t INT_STAT_6; //!< Interrupt Status Register 6
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volatile hw_ipu_int_stat_7_t INT_STAT_7; //!< Interrupt Status Register7 1
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volatile hw_ipu_int_stat_8_t INT_STAT_8; //!< Interrupt Status Register 8
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volatile hw_ipu_int_stat_9_t INT_STAT_9; //!< Interrupt Status Register 9
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volatile hw_ipu_int_stat_10_t INT_STAT_10; //!< Interrupt Status Register 10
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volatile hw_ipu_int_stat_11_t INT_STAT_11; //!< Interrupt Status Register 11
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volatile hw_ipu_int_stat_12_t INT_STAT_12; //!< Interrupt Status Register 12
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volatile hw_ipu_int_stat_13_t INT_STAT_13; //!< Interrupt Status Register 13
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volatile hw_ipu_int_stat_14_t INT_STAT_14; //!< Interrupt Status Register 14
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volatile hw_ipu_int_stat_15_t INT_STAT_15; //!< Interrupt Status Register 15
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volatile hw_ipu_cur_buf_0_t CUR_BUF_0; //!< Current Buffer Register 0
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volatile hw_ipu_cur_buf_1_t CUR_BUF_1; //!< Current Buffer Register 1
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volatile hw_ipu_alt_cur_0_t ALT_CUR_0; //!< Alternate Current Buffer Register 0
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volatile hw_ipu_alt_cur_1_t ALT_CUR_1; //!< Alternate Current Buffer Register 1
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volatile hw_ipu_srm_stat_t SRM_STAT; //!< Shadow Registers Memory Status Register
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volatile hw_ipu_proc_tasks_stat_t PROC_TASKS_STAT; //!< Processing Status Tasks Register
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volatile hw_ipu_disp_tasks_stat_t DISP_TASKS_STAT; //!< Display Tasks Status Register
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volatile hw_ipu_triple_cur_buf_0_t TRIPLE_CUR_BUF_0; //!< Triple Current Buffer Register 0
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volatile hw_ipu_triple_cur_buf_1_t TRIPLE_CUR_BUF_1; //!< Triple Current Buffer Register 1
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volatile hw_ipu_triple_cur_buf_2_t TRIPLE_CUR_BUF_2; //!< Triple Current Buffer Register 2
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volatile hw_ipu_triple_cur_buf_3_t TRIPLE_CUR_BUF_3; //!< Triple Current Buffer Register 3
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volatile hw_ipu_ch_buf0_rdy0_t CH_BUF0_RDY0; //!< IPU Channels Buffer 0 Ready 0 Register
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volatile hw_ipu_ch_buf0_rdy1_t CH_BUF0_RDY1; //!< IPU Channels Buffer 0 Ready 1 Register
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volatile hw_ipu_ch_buf1_rdy0_t CH_BUF1_RDY0; //!< IPU Channels Buffer 1 Ready 0 Register
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volatile hw_ipu_ch_buf1_rdy1_t CH_BUF1_RDY1; //!< IPU Channels Buffer 1 Ready 1Register
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volatile hw_ipu_alt_ch_buf0_rdy0_t ALT_CH_BUF0_RDY0; //!< IPU Alternate Channels Buffer 0 Ready 0 Register
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volatile hw_ipu_alt_ch_buf0_rdy1_t ALT_CH_BUF0_RDY1; //!< IPU Alternate Channels Buffer 0 Ready 1 Register
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volatile hw_ipu_alt_ch_buf1_rdy0_t ALT_CH_BUF1_RDY0; //!< IPU Alternate Channels Buffer1 Ready 0 Register
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volatile hw_ipu_alt_ch_buf1_rdy1_t ALT_CH_BUF1_RDY1; //!< IPU Alternate Channels Buffer 1 Ready 1 Register
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volatile hw_ipu_ch_buf2_rdy0_t CH_BUF2_RDY0; //!< IPU Channels Buffer 2 Ready 0 Register
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volatile hw_ipu_ch_buf2_rdy1_t CH_BUF2_RDY1; //!< IPU Channels Buffer 2 Ready 1 Register
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reg32_t _reserved7[1836];
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volatile hw_ipu_idmac_conf_t IDMAC_CONF; //!< IDMAC Configuration Register
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volatile hw_ipu_idmac_ch_en_1_t IDMAC_CH_EN_1; //!< IDMAC Channel Enable 1 Register
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volatile hw_ipu_idmac_ch_en_2_t IDMAC_CH_EN_2; //!< IDMAC Channel Enable 2 Register
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volatile hw_ipu_idmac_alt_sep_alpha_t IDMAC_ALT_SEP_ALPHA; //!< IDMAC Alternate Separate Alpha Indication Register
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volatile hw_ipu_idmac_ch_pri_1_t IDMAC_CH_PRI_1; //!< IDMAC Channel Priority 1 Register
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volatile hw_ipu_idmac_ch_pri_2_t IDMAC_CH_PRI_2; //!< IDMAC Channel Priority 2 Register
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volatile hw_ipu_idmac_wm_en_2_t IDMAC_WM_EN_2; //!< IDMAC Channel Watermark Enable 2 Register
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volatile hw_ipu_idmac_lock_en_1_t IDMAC_LOCK_EN_1; //!< IDMAC Channel Lock Enable 1Register
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volatile hw_ipu_idmac_lock_en_2_t IDMAC_LOCK_EN_2; //!< IDMAC Channel Lock Enable 2Register
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volatile hw_ipu_idmac_sub_addr_1_t IDMAC_SUB_ADDR_1; //!< IDMAC Channel Alternate Address 1 Register
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volatile hw_ipu_idmac_sub_addr_2_t IDMAC_SUB_ADDR_2; //!< IDMAC Channel Alternate Address 2 Register
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volatile hw_ipu_idmac_sub_addr_3_t IDMAC_SUB_ADDR_3; //!< IDMAC Channel Alternate Address 3 Register
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volatile hw_ipu_idmac_bndm_en_1_t IDMAC_BNDM_EN_1; //!< IDMAC Band Mode Enable 1 Register
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volatile hw_ipu_idmac_bndm_en_2_t IDMAC_BNDM_EN_2; //!< IDMAC Band Mode Enable 2 Register
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volatile hw_ipu_idmac_sc_cord_t IDMAC_SC_CORD; //!< IDMAC Scroll Coordinations Register
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reg32_t _reserved8[10];
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volatile hw_ipu_idmac_ch_busy_1_t IDMAC_CH_BUSY_1; //!< IDMAC Channel Busy 1 Register
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volatile hw_ipu_idmac_ch_busy_2_t IDMAC_CH_BUSY_2; //!< IDMAC Channel Busy 2 Register
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reg32_t _reserved9[6168];
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volatile hw_ipu_idmac_sep_alpha_t IDMAC_SEP_ALPHA; //!< IDMAC Separate Alpha Indication Register
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reg32_t _reserved10[3];
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volatile hw_ipu_idmac_wm_en_1_t IDMAC_WM_EN_1; //!< IDMAC Channel Watermark Enable 1 Register
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reg32_t _reserved11[3];
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volatile hw_ipu_idmac_sub_addr_0_t IDMAC_SUB_ADDR_0; //!< IDMAC Channel Alternate Address 0 Register
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reg32_t _reserved12[3];
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volatile hw_ipu_idmac_sub_addr_4_t IDMAC_SUB_ADDR_4; //!< IDMAC Channel Alternate Address 4 Register
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reg32_t _reserved13[3];
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volatile hw_ipu_idmac_sc_cord_1_t IDMAC_SC_CORD_1; //!< IDMAC Scroll Coordinations Register 1
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reg32_t _reserved14[16364];
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volatile hw_ipu_dp_com_conf_sync_t DP_COM_CONF_SYNC; //!< DP Common Configuration Sync Flow Register
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volatile hw_ipu_dp_graph_wind_ctrl_sync_t DP_GRAPH_WIND_CTRL_SYNC; //!< DP Graphic Window Control Sync Flow Register
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volatile hw_ipu_dp_fg_pos_sync_t DP_FG_POS_SYNC; //!< DP Partial Plane Window Position Sync Flow Register
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volatile hw_ipu_dp_cur_pos_sync_t DP_CUR_POS_SYNC; //!< DP Cursor Position and Size Sync Flow Register
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volatile hw_ipu_dp_cur_map_sync_t DP_CUR_MAP_SYNC; //!< DP Color Cursor Mapping Sync Flow Register
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volatile hw_ipu_dp_gamma_c_sync_i_t DP_GAMMA_C_SYNC_I; //!< DP Gamma Constants Sync Flow Register i
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reg32_t _reserved15[7];
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volatile hw_ipu_dp_gamma_s_sync_i_t DP_GAMMA_S_SYNC_I; //!< DP Gamma Correction Slope Sync Flow Register i
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reg32_t _reserved16[3];
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volatile hw_ipu_dp_csca_sync_i_t DP_CSCA_SYNC_I; //!< DP Color Space Conversion Control Sync Flow Registers
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reg32_t _reserved17[3];
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volatile hw_ipu_dp_scs_sync_0_t DP_SCS_SYNC_0; //!< DP Color Conversion Control Sync Flow Register 0
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volatile hw_ipu_dp_scs_sync_1_t DP_SCS_SYNC_1; //!< DP Color Conversion Control Sync Flow Register 1
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volatile hw_ipu_dp_cur_pos_alt_t DP_CUR_POS_ALT; //!< DP Cursor Position and Size Alternate Register
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volatile hw_ipu_dp_com_conf_async0_t DP_COM_CONF_ASYNC0; //!< DP Common Configuration Async 0 Flow Register
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volatile hw_ipu_dp_graph_wind_ctrl_async0_t DP_GRAPH_WIND_CTRL_ASYNC0; //!< DP Graphic Window Control Async 0 Flow Register
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volatile hw_ipu_dp_fg_pos_async0_t DP_FG_POS_ASYNC0; //!< DP Partial Plane Window Position Async 0 Flow Register
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volatile hw_ipu_dp_cur_pos_async0_t DP_CUR_POS_ASYNC0; //!< DP Cursor Position and Size Async 0 Flow Register
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volatile hw_ipu_dp_cur_map_async0_t DP_CUR_MAP_ASYNC0; //!< DP Color Cursor Mapping Async 0 Flow Register
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volatile hw_ipu_dp_gamma_c_async0_i_t DP_GAMMA_C_ASYNC0_I; //!< DP Gamma Constant Async 0 Flow Register i
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reg32_t _reserved18[7];
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volatile hw_ipu_dp_gamma_s_async0_i_t DP_GAMMA_S_ASYNC0_I; //!< DP Gamma Correction Slope Async 0 Flow Register i
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reg32_t _reserved19[3];
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volatile hw_ipu_dp_csca_async0_i_t DP_CSCA_ASYNC0_I; //!< DP Color Space Conversion Control Async 0 Flow Register i
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reg32_t _reserved20[3];
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volatile hw_ipu_dp_csc_async0_0_t DP_CSC_ASYNC0_0; //!< DP Color Conversion Control Async 0 Flow Register 0
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volatile hw_ipu_dp_csc_async_1_t DP_CSC_ASYNC_1; //!< DP Color Conversion Control Async 1 Flow Register
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volatile hw_ipu_dp_com_conf_async1_t DP_COM_CONF_ASYNC1; //!< DP Common Configuration Async 1 Flow Register
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volatile hw_ipu_dp_debug_cnt_t DP_DEBUG_CNT; //!< DP Debug Control Register
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volatile hw_ipu_dp_graph_wind_ctrl_async1_t DP_GRAPH_WIND_CTRL_ASYNC1; //!< DP Graphic Window Control Async 1 Flow Register
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volatile hw_ipu_dp_debug_stat_t DP_DEBUG_STAT; //!< DP Debug Status Register
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volatile hw_ipu_dp_fg_pos_async1_t DP_FG_POS_ASYNC1; //!< DP Partial Plane Window Position Async 1 Flow Register
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volatile hw_ipu_dp_cur_pos_async1_t DP_CUR_POS_ASYNC1; //!< DP Cursor Postion and Size Async 1 Flow Register
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volatile hw_ipu_dp_cur_map_async1_t DP_CUR_MAP_ASYNC1; //!< DP Color Cursor Mapping Async 1 Flow Register
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volatile hw_ipu_dp_gamma_c_async1_i_t DP_GAMMA_C_ASYNC1_I; //!< DP Gamma Constants Async 1 Flow Register i
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reg32_t _reserved21[5];
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volatile hw_ipu_dp_gamma_s_asyn1_i_t DP_GAMMA_S_ASYN1_I; //!< DP Gamma Correction Slope Async 1 Flow Register i
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reg32_t _reserved22[3];
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volatile hw_ipu_dp_csca_async1_i_t DP_CSCA_ASYNC1_I; //!< DP Color Space Converstion Control Async 1 Flow Register i
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reg32_t _reserved23[3];
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volatile hw_ipu_dp_csc_async1_0_t DP_CSC_ASYNC1_0; //!< DP Color Conversion Control Async 1 Flow Register 0
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volatile hw_ipu_dp_csc_async1_1_t DP_CSC_ASYNC1_1; //!< DP Color Conversion Control Async 1 Flow Register 1
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reg32_t _reserved24[8122];
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volatile hw_ipu_ic_conf_t IC_CONF; //!< IC Configuration Register
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volatile hw_ipu_ic_prp_enc_rsc_t IC_PRP_ENC_RSC; //!< IC Preprocessing Encoder Resizing Coefficients Register
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volatile hw_ipu_ic_prp_vf_rsc_t IC_PRP_VF_RSC; //!< IC Preprocessing View-Finder Resizing Coefficients Register
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volatile hw_ipu_ic_pp_rsc_t IC_PP_RSC; //!< IC Postprocessing Encoder Resizing Coefficients Register
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volatile hw_ipu_ic_cmbp_1_t IC_CMBP_1; //!< IC Combining Parameters Register 1
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volatile hw_ipu_ic_cmbp_2_t IC_CMBP_2; //!< IC Combining Parameters Register 2
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volatile hw_ipu_ic_idmac_1_t IC_IDMAC_1; //!< IC IDMAC Parameters 1 Register
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volatile hw_ipu_ic_idmac_2_t IC_IDMAC_2; //!< IC IDMAC Parameters 2 Register
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volatile hw_ipu_ic_idmac_3_t IC_IDMAC_3; //!< IC IDMAC Parameters 3Register
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volatile hw_ipu_ic_idmac_4_t IC_IDMAC_4; //!< IC IDMAC Parameters 4 Register
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reg32_t _reserved25[16374];
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volatile hw_ipu_csi0_sens_conf_t CSI0_SENS_CONF; //!< CSI0 Sensor Configuration Register
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volatile hw_ipu_csi0_sens_frm_size_t CSI0_SENS_FRM_SIZE; //!< CSI0 Sense Frame Size Register
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volatile hw_ipu_csi0_act_frm_size_t CSI0_ACT_FRM_SIZE; //!< CSI0 Actual Frame Size Register
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volatile hw_ipu_csi0_out_frm_ctrl_t CSI0_OUT_FRM_CTRL; //!< CSI0 Output Control Register
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volatile hw_ipu_csi0_tst_ctrl_t CSI0_TST_CTRL; //!< CSIO Test Control Register
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volatile hw_ipu_csi0_ccir_code_1_t CSI0_CCIR_CODE_1; //!< CSIO CCIR Code Register 1
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volatile hw_ipu_csi0_ccir_code_2_t CSI0_CCIR_CODE_2; //!< CSIO CCIR Code Register 2
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volatile hw_ipu_csi0_ccir_code_3_t CSI0_CCIR_CODE_3; //!< CSIO CCIR Code Register 3
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volatile hw_ipu_csi0_di_t CSI0_DI; //!< CSI0 Data Identifier Register
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volatile hw_ipu_csi0_skip_t CSI0_SKIP; //!< CSI0 SKIP Register
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volatile hw_ipu_csio_cpd_ctrl_t CSIO_CPD_CTRL; //!< CSI0 Compander Control Register
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volatile hw_ipu_csio_cpd_rc_i_t CSIO_CPD_RC_I; //!< CSI0 Red Component Compander Constants Register <i>
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reg32_t _reserved26[7];
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volatile hw_ipu_csio_cpd_rs_i_t CSIO_CPD_RS_I; //!< CSI0 Red Component Compander SLOPE Register <i>
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reg32_t _reserved27[3];
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volatile hw_ipu_csio_cpd_grc_i_t CSIO_CPD_GRC_I; //!< CSI0 GR Component Compander Constants Register <i>
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reg32_t _reserved28[7];
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volatile hw_ipu_csio_cpd_grs_i_t CSIO_CPD_GRS_I; //!< CSI0 GR Component Compander SLOPE Register <i>
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reg32_t _reserved29[3];
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volatile hw_ipu_csio_cpd_gbc_i_t CSIO_CPD_GBC_I; //!< CSI0 GB Component Compander Constants Register <i>
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reg32_t _reserved30[7];
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volatile hw_ipu_csio_cpd_gbs_i_t CSIO_CPD_GBS_I; //!< CSI0 GB Component Compander SLOPE Register <i>
|
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reg32_t _reserved31[3];
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volatile hw_ipu_csio_cpd_bc_i_t CSIO_CPD_BC_I; //!< CSI0 Blue Component Compander Constants Register <i>
|
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reg32_t _reserved32[7];
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volatile hw_ipu_csio_cpd_bs_i_t CSIO_CPD_BS_I; //!< CSI0 Blue Component Compander SLOPE Register <i>
|
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reg32_t _reserved33[3];
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volatile hw_ipu_csi0_cpd_offset1_t CSI0_CPD_OFFSET1; //!< CSI0 Compander Offset Register 1
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volatile hw_ipu_csi0_cpd_offset2_t CSI0_CPD_OFFSET2; //!< CSI0 Compander Offset Register 2
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|
reg32_t _reserved34[8131];
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volatile hw_ipu_csi1_sens_conf_t CSI1_SENS_CONF; //!< CSI1 Sensor Configuration Register
|
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volatile hw_ipu_csi1_sens_frm_size_t CSI1_SENS_FRM_SIZE; //!< CSI1 Sense Frame Size Register
|
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volatile hw_ipu_csi1_act_frm_size_t CSI1_ACT_FRM_SIZE; //!< CSI1 Actual Frame Size Register
|
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volatile hw_ipu_csi1_out_frm_ctrl_t CSI1_OUT_FRM_CTRL; //!< CSI1 Output Control Register
|
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volatile hw_ipu_csi1_tst_ctrl_t CSI1_TST_CTRL; //!< CSI1 Test Control Register
|
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volatile hw_ipu_csi1_ccir_code_1_t CSI1_CCIR_CODE_1; //!< CSI1 CCIR Code Register 1
|
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volatile hw_ipu_csi1_ccir_code_2_t CSI1_CCIR_CODE_2; //!< CSI1 CCIR Code Register 2
|
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volatile hw_ipu_csi1_ccir_code_3_t CSI1_CCIR_CODE_3; //!< CSI1 CCIR Code Register 3
|
|
volatile hw_ipu_csi1_di_t CSI1_DI; //!< CSI1 Data Identifier Register
|
|
volatile hw_ipu_csi1_skip_t CSI1_SKIP; //!< CSI1 SKIP Register
|
|
volatile hw_ipu_csi1_cpd_ctrl_t CSI1_CPD_CTRL; //!< CSI1 Compander Control Register
|
|
volatile hw_ipu_csi1_cpd_rc_i_t CSI1_CPD_RC_I; //!< CSI1 Red Component Compander Constants Register <i>
|
|
reg32_t _reserved35[7];
|
|
volatile hw_ipu_csi1_cpd_rs_i_t CSI1_CPD_RS_I; //!< CSI1 Red Component Compander SLOPE Register <i>
|
|
reg32_t _reserved36[3];
|
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volatile hw_ipu_csi1_cpd_grc_i_t CSI1_CPD_GRC_I; //!< CSI1 GR Component Compander Constants Register <i>
|
|
reg32_t _reserved37[7];
|
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volatile hw_ipu_csi1_cpd_grs_i_t CSI1_CPD_GRS_I; //!< CSI1 GR Component Compander SLOPE Register <i>
|
|
reg32_t _reserved38[3];
|
|
volatile hw_ipu_csi1_cpd_gbc_i_t CSI1_CPD_GBC_I; //!< CSI1 GB Component Compander Constants Register <i>
|
|
reg32_t _reserved39[7];
|
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volatile hw_ipu_csi1_cpd_gbs_i_t CSI1_CPD_GBS_I; //!< CSI1 GB Component Compander SLOPE Register <i>
|
|
reg32_t _reserved40[3];
|
|
volatile hw_ipu_csi1_cpd_bc_i_t CSI1_CPD_BC_I; //!< CSI1 Blue Component Compander Constants Register <i>
|
|
reg32_t _reserved41[7];
|
|
volatile hw_ipu_csi1_cpd_bs_i_t CSI1_CPD_BS_I; //!< CSI1 Blue Component Compander SLOPE Register <i>
|
|
reg32_t _reserved42[3];
|
|
volatile hw_ipu_csi1_cpd_offset1_t CSI1_CPD_OFFSET1; //!< CSI1 Compander Offset Register 1
|
|
volatile hw_ipu_csi1_cpd_offset2_t CSI1_CPD_OFFSET2; //!< CSI1 Compander Offset Register 2
|
|
reg32_t _reserved43[8131];
|
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volatile hw_ipu_di0_general_t DI0_GENERAL; //!< DI0 General Register
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volatile hw_ipu_di0_bs_clkgen0_t DI0_BS_CLKGEN0; //!< DI0 Base Sync Clock Gen 0 Register
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volatile hw_ipu_di0_bs_clkgen1_t DI0_BS_CLKGEN1; //!< DI0 Base Sync Clock Gen 1 Register
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volatile hw_ipu_di0_sw_gen0_1_t DI0_SW_GEN0_1; //!< DI0 Sync Wave Gen 1 Register 0
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volatile hw_ipu_di0_sw_gen0_2_t DI0_SW_GEN0_2; //!< DI0 Sync Wave Gen 2 Register 0
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volatile hw_ipu_di0_sw_gen0_3_t DI0_SW_GEN0_3; //!< DI0 Sync Wave Gen 3 Register 0
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volatile hw_ipu_di0_sw_gen0_4_t DI0_SW_GEN0_4; //!< DI0 Sync Wave Gen 4 Register 0
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volatile hw_ipu_di0_sw_gen0_5_t DI0_SW_GEN0_5; //!< DI0 Sync Wave Gen 5 Register 0
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volatile hw_ipu_di0_sw_gen0_6_t DI0_SW_GEN0_6; //!< DI0 Sync Wave Gen 6 Register 0
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volatile hw_ipu_di0_sw_gen0_7_t DI0_SW_GEN0_7; //!< DI0 Sync Wave Gen 7 Register 0
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volatile hw_ipu_di0_sw_gen0_8_t DI0_SW_GEN0_8; //!< DI0 Sync Wave Gen 8 Register 0
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volatile hw_ipu_di0_sw_gen0_9_t DI0_SW_GEN0_9; //!< DI0 Sync Wave Gen 9 Register 0
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volatile hw_ipu_di0_sw_gen1_1_t DI0_SW_GEN1_1; //!< DI0 Sync Wave Gen 1 Register 1
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volatile hw_ipu_di0_sw_gen1_2_t DI0_SW_GEN1_2; //!< DI0 Sync Wave Gen 2 Register 1
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volatile hw_ipu_di0_sw_gen1_3_t DI0_SW_GEN1_3; //!< DI0 Sync Wave Gen 3 Register 1
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volatile hw_ipu_di0_sw_gen1_4_t DI0_SW_GEN1_4; //!< DI0 Sync Wave Gen 4 Register 1
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volatile hw_ipu_di0_sw_gen1_5_t DI0_SW_GEN1_5; //!< DI0 Sync Wave Gen 5 Register 1
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volatile hw_ipu_di0_sw_gen1_6_t DI0_SW_GEN1_6; //!< DI0 Sync Wave Gen 6 Register 1
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volatile hw_ipu_di0_sw_gen1_7_t DI0_SW_GEN1_7; //!< DI0 Sync Wave Gen 7 Register 1
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volatile hw_ipu_di0_sw_gen1_8_t DI0_SW_GEN1_8; //!< DI0 Sync Wave Gen 8 Register 1
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volatile hw_ipu_di0_sw_gen1_9_t DI0_SW_GEN1_9; //!< DI0 Sync Wave Gen 9 Register 1
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volatile hw_ipu_di0_sync_as_gen_t DI0_SYNC_AS_GEN; //!< DI0 Sync Assistance Gen Register
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volatile hw_ipu_di0_dw_gen_i_t DI0_DW_GEN_I; //!< DI0 Data Wave Gen <i> Register
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reg32_t _reserved44[11];
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volatile hw_ipu_di0_dw_set0_i_t DI0_DW_SET0_I; //!< DI0 Data Wave Set 0 <i> Register
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reg32_t _reserved45[11];
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volatile hw_ipu_di0_dw_set1_i_t DI0_DW_SET1_I; //!< DI0 Data Wave Set 1 <i> Register
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reg32_t _reserved46[11];
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volatile hw_ipu_di0_dw_set2_i_t DI0_DW_SET2_I; //!< DI0 Data Wave Set 2 <i> Register
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reg32_t _reserved47[11];
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volatile hw_ipu_di0_dw_set3_i_t DI0_DW_SET3_I; //!< DI0 Data Wave Set 3 <i> Register
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reg32_t _reserved48[11];
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volatile hw_ipu_di0_stp_rep_i_t DI0_STP_REP_I; //!< DI0 Step Repeat <i> Registers
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reg32_t _reserved49[3];
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volatile hw_ipu_di0_stp_rep_9_t DI0_STP_REP_9; //!< DI0 Step Repeat 9 Registers
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volatile hw_ipu_di0_ser_conf_t DI0_SER_CONF; //!< DI0 Serial Display Control Register
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volatile hw_ipu_di0_ssc_t DI0_SSC; //!< DI0 Special Signals Control Register
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volatile hw_ipu_di0_pol_t DI0_POL; //!< DI0 Polarity Register
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volatile hw_ipu_di0_aw0_t DI0_AW0; //!< DI0 Active Window 0 Register
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volatile hw_ipu_di0_aw1_t DI0_AW1; //!< DI0 Active Window 1 Register
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volatile hw_ipu_di0_scr_conf_t DI0_SCR_CONF; //!< DI0 Screen Configuration Register
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volatile hw_ipu_di0_stat_t DI0_STAT; //!< DI0 Status Register
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reg32_t _reserved50[8098];
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volatile hw_ipu_di1_general_t DI1_GENERAL; //!< DI1General Register
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volatile hw_ipu_di1_bs_clkgen0_t DI1_BS_CLKGEN0; //!< DI1 Base Sync Clock Gen 0 Register
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volatile hw_ipu_di1_bs_clkgen1_t DI1_BS_CLKGEN1; //!< DI1 Base Sync Clock Gen 1 Register
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volatile hw_ipu_di1_sw_gen0_1_t DI1_SW_GEN0_1; //!< DI1 Sync Wave Gen 1 Register 0
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volatile hw_ipu_di1_sw_gen0_2_t DI1_SW_GEN0_2; //!< DI1 Sync Wave Gen 2 Register 0
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volatile hw_ipu_di1_sw_gen0_3_t DI1_SW_GEN0_3; //!< DI1 Sync Wave Gen 3 Register 0
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volatile hw_ipu_di1_sw_gen0_4_t DI1_SW_GEN0_4; //!< DI1 Sync Wave Gen 4 Register 0
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volatile hw_ipu_di1_sw_gen0_5_t DI1_SW_GEN0_5; //!< DI1 Sync Wave Gen 5 Register 0
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volatile hw_ipu_di1_sw_gen0_6_t DI1_SW_GEN0_6; //!< DI1 Sync Wave Gen 6 Register 0
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volatile hw_ipu_di1_sw_gen0_7_t DI1_SW_GEN0_7; //!< DI1 Sync Wave Gen 7 Register 0
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volatile hw_ipu_di1_sw_gen0_8_t DI1_SW_GEN0_8; //!< DI1 Sync Wave Gen 8 Register 0
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volatile hw_ipu_di1_sw_gen0_9_t DI1_SW_GEN0_9; //!< DI1Sync Wave Gen 9 Register 0
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volatile hw_ipu_di1_sw_gen1_1_t DI1_SW_GEN1_1; //!< DI1 Sync Wave Gen 1 Register 1
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volatile hw_ipu_di1_sw_gen1_2_t DI1_SW_GEN1_2; //!< DI1 Sync Wave Gen 2 Register 1
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volatile hw_ipu_di1_sw_gen1_3_t DI1_SW_GEN1_3; //!< DI1 Sync Wave Gen 3 Register 1
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volatile hw_ipu_di1_sw_gen1_4_t DI1_SW_GEN1_4; //!< DI1 Sync Wave Gen 4 Register 1
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volatile hw_ipu_di1_sw_gen1_5_t DI1_SW_GEN1_5; //!< DI1 Sync Wave Gen 5 Register 1
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volatile hw_ipu_di1_sw_gen1_6_t DI1_SW_GEN1_6; //!< DI1 Sync Wave Gen 6 Register 1
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volatile hw_ipu_di1_sw_gen1_7_t DI1_SW_GEN1_7; //!< DI1Sync Wave Gen 7 Register 1
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volatile hw_ipu_di1_sw_gen1_8_t DI1_SW_GEN1_8; //!< DI1 Sync Wave Gen 8 Register 1
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volatile hw_ipu_di1_sw_gen1_9_t DI1_SW_GEN1_9; //!< DI1 Sync Wave Gen 9 Register 1
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volatile hw_ipu_di1_sync_as_gen_t DI1_SYNC_AS_GEN; //!< DI1 Sync Assistance Gen Register
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volatile hw_ipu_di1_dw_gen_i_t DI1_DW_GEN_I; //!< DI1 Data Wave Gen <i> Register
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reg32_t _reserved51[11];
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volatile hw_ipu_di1_dw_set0_i_t DI1_DW_SET0_I; //!< DI1 Data Wave Set 0 <i> Register
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reg32_t _reserved52[11];
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volatile hw_ipu_di1_dw_set1_i_t DI1_DW_SET1_I; //!< DI1 Data Wave Set 1 <i> Register
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reg32_t _reserved53[11];
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volatile hw_ipu_di1_dw_set2_i_t DI1_DW_SET2_I; //!< DI1 Data Wave Set 2 <i> Register
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reg32_t _reserved54[11];
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volatile hw_ipu_di1_dw_set3_i_t DI1_DW_SET3_I; //!< DI1 Data Wave Set 3 <i> Register
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reg32_t _reserved55[11];
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volatile hw_ipu_d1_stp_rep_i_t D1_STP_REP_I; //!< DI1 Step Repeat <i> Registers
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reg32_t _reserved56[3];
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volatile hw_ipu_di1_stp_rep_9_t DI1_STP_REP_9; //!< DI1Step Repeat 9 Registers
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volatile hw_ipu_di1_ser_conf_t DI1_SER_CONF; //!< DI1 Serial Display Control Register
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volatile hw_ipu_di1_ssc_t DI1_SSC; //!< DI1 Special Signals Control Register
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volatile hw_ipu_di1_pol_t DI1_POL; //!< DI1 Polarity Register
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volatile hw_ipu_di1_aw0_t DI1_AW0; //!< DI1Active Window 0 Register
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volatile hw_ipu_di1_aw1_t DI1_AW1; //!< DI1 Active Window 1 Register
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volatile hw_ipu_di1_scr_conf_t DI1_SCR_CONF; //!< DI1 Screen Configuration Register
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volatile hw_ipu_di1_stat_t DI1_STAT; //!< DI1 Status Register
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reg32_t _reserved57[8098];
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volatile hw_ipu_smfc_map_t SMFC_MAP; //!< SMFC Mapping Register
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volatile hw_ipu_smfc_wmc_t SMFC_WMC; //!< SMFC Watermark Control Register
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volatile hw_ipu_smfc_bs_t SMFC_BS; //!< SMFC Burst Size Register
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reg32_t _reserved58[8189];
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volatile hw_ipu_dc_read_ch_conf_t DC_READ_CH_CONF; //!< DC Read Channel Configuration Register
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volatile hw_ipu_dc_read_sh_addr_t DC_READ_SH_ADDR; //!< DC Read Channel Start Address Register
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volatile hw_ipu_dc_rl0_ch_0_t DC_RL0_CH_0; //!< DC Routine Link Register 0 Channel 0
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volatile hw_ipu_dc_rl1_ch_0_t DC_RL1_CH_0; //!< DC Routine Link Register 1 Channel 0
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volatile hw_ipu_dc_rl2_ch_0_t DC_RL2_CH_0; //!< DC Routine Link Register2 Channel 0
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volatile hw_ipu_dc_rl3_ch_0_t DC_RL3_CH_0; //!< DC Routine Link Registe3 Channel 0
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volatile hw_ipu_dc_rl4_ch_0_t DC_RL4_CH_0; //!< DC Routine Link Register 4 Channel 0
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volatile hw_ipu_dc_wr_ch_conf_1_t DC_WR_CH_CONF_1; //!< DC Write Channel 1 Configuration Register
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volatile hw_ipu_dc_wr_ch_addr_1_t DC_WR_CH_ADDR_1; //!< DC Write Channel 1 Address Configuration Register
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volatile hw_ipu_dc_rl0_ch_1_t DC_RL0_CH_1; //!< DC Routine Link Register 0 Channel 1
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volatile hw_ipu_dc_rl1_ch_1_t DC_RL1_CH_1; //!< DC Routine Link Register 1 Channel 1
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reg32_t _reserved59;
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volatile hw_ipu_dc_rl2_ch_1_t DC_RL2_CH_1; //!< DC Routine Link Register 2 Channel 1
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volatile hw_ipu_dc_rl3_ch_1_t DC_RL3_CH_1; //!< DC Routine Link Register 3 Channel 1
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volatile hw_ipu_dc_rl4_ch_1_t DC_RL4_CH_1; //!< DC Routine Link Register 4 Channel 1
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volatile hw_ipu_dc_wr_ch_conf_2_t DC_WR_CH_CONF_2; //!< DC Write Channel 2 Configuration Register
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volatile hw_ipu_dc_wr_ch_addr_2_t DC_WR_CH_ADDR_2; //!< DC Write Channel 2 Address Configuration Register
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volatile hw_ipu_dc_rl0_ch_2_t DC_RL0_CH_2; //!< DC Routine Link Register 0 Channel 2
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volatile hw_ipu_dc_rl1_ch_2_t DC_RL1_CH_2; //!< DC Routine Link Register 1 Channel 2
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volatile hw_ipu_dc_rl2_ch_2_t DC_RL2_CH_2; //!< DC Routine Link Register 2 Channel 2
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volatile hw_ipu_dc_rl3_ch_2_t DC_RL3_CH_2; //!< DC Routine Link Register 3 Channel 2
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volatile hw_ipu_dc_rl4_ch_2_t DC_RL4_CH_2; //!< DC Routine Link Register 4 Channel 2
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volatile hw_ipu_dc_cmd_ch_conf_3_t DC_CMD_CH_CONF_3; //!< DC Command Channel 3 Configuration Register
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volatile hw_ipu_dc_cmd_ch_conf_4_t DC_CMD_CH_CONF_4; //!< DC Command Channel 4 Configuration Register
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volatile hw_ipu_dc_wr_ch_conf_5_t DC_WR_CH_CONF_5; //!< DC Write Channel 5Configuration Register
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volatile hw_ipu_dc_wr_ch_addr_5_t DC_WR_CH_ADDR_5; //!< DC Write Channel 5Address Configuration Register
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volatile hw_ipu_dc_rl0_ch_5_t DC_RL0_CH_5; //!< DC Routine Link Register 0 Channel 5
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volatile hw_ipu_dc_rl1_ch_5_t DC_RL1_CH_5; //!< DC Routine Link Register 1 Channel 5
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volatile hw_ipu_dc_rl2_ch_5_t DC_RL2_CH_5; //!< DC Routine Link Register 2 Channel 5
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volatile hw_ipu_dc_rl3_ch_5_t DC_RL3_CH_5; //!< DC Routine Link Register3 Channel 5
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volatile hw_ipu_dc_rl4_ch_5_t DC_RL4_CH_5; //!< DC Routine Link Register 4 Channel 5
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volatile hw_ipu_dc_wr_ch_conf_6_t DC_WR_CH_CONF_6; //!< DC Write Channel 6 Configuration Register
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volatile hw_ipu_dc_wr_ch_addr_6_t DC_WR_CH_ADDR_6; //!< DC Write Channel 6 Address Configuration Register
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volatile hw_ipu_dc_rl0_ch_6_t DC_RL0_CH_6; //!< DC Routine Link Register 0Channel 6
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volatile hw_ipu_dc_rl1_ch_6_t DC_RL1_CH_6; //!< DC Routine Link Register 1 Channel 6
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volatile hw_ipu_dc_rl2_ch_6_t DC_RL2_CH_6; //!< DC Routine Link Register 2 Channel 6
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volatile hw_ipu_dc_rl3_ch_6_t DC_RL3_CH_6; //!< DC Routine Link Register 3 Channel 6
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volatile hw_ipu_dc_rl4_ch_6_t DC_RL4_CH_6; //!< DC Routine Link Register 4 Channel 6
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volatile hw_ipu_dc_wr_ch_conf1_8_t DC_WR_CH_CONF1_8; //!< DC Write Channel 8 Configuration 1Register
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volatile hw_ipu_dc_wr_ch_conf2_8_t DC_WR_CH_CONF2_8; //!< DC Write Channel 8 Configuration 2 Register
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volatile hw_ipu_dc_rl1_ch_8_t DC_RL1_CH_8; //!< DC Routine Link Register 1 Channel 8
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volatile hw_ipu_dc_rl2_ch_8_t DC_RL2_CH_8; //!< DC Routine Link Register 2 Channel 8
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volatile hw_ipu_dc_rl3_ch_8_t DC_RL3_CH_8; //!< DC Routine Link Register 3 Channel 8
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volatile hw_ipu_dc_rl4_ch_8_t DC_RL4_CH_8; //!< DC Routine Link Register 4 Channel 8
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volatile hw_ipu_dc_rl5_ch_8_t DC_RL5_CH_8; //!< DC Routine Link Register 5 Channel 8
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volatile hw_ipu_dc_rl6_ch_8_t DC_RL6_CH_8; //!< DC Routine Link Register 6 Channel 8
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volatile hw_ipu_dc_wr_ch_conf1_9_t DC_WR_CH_CONF1_9; //!< DC Write Channel 9 Configuration 1Register
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volatile hw_ipu_dc_wr_ch_conf2_9_t DC_WR_CH_CONF2_9; //!< DC Write Channel 9Configuration 2Register
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volatile hw_ipu_dc_rl1_ch_9_t DC_RL1_CH_9; //!< DC Routine Link Register 1 Channel 9
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volatile hw_ipu_dc_rl2_ch_9_t DC_RL2_CH_9; //!< DC Routine Link Register 2 Channel 9
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volatile hw_ipu_dc_rl3_ch_9_t DC_RL3_CH_9; //!< DC Routine Link Register 3Channel 9
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volatile hw_ipu_dc_rl4_ch_9_t DC_RL4_CH_9; //!< DC Routine Link Register 4 Channel 9
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volatile hw_ipu_dc_rl5_ch_9_t DC_RL5_CH_9; //!< DC Routine Link Register 5 Channel 9
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volatile hw_ipu_dc_rl6_ch_9_t DC_RL6_CH_9; //!< DC Routine Link Register 6 Channel 9
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volatile hw_ipu_dc_gen_t DC_GEN; //!< DC General Register
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volatile hw_ipu_dc_disp_conf1_0_t DC_DISP_CONF1_0; //!< DC Display Configuration 1 Register 0
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volatile hw_ipu_dc_disp_conf1_1_t DC_DISP_CONF1_1; //!< DC Display Configuration 1 Register 1
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volatile hw_ipu_dc_disp_conf1_2_t DC_DISP_CONF1_2; //!< DC Display Configuration 1 Register 2
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volatile hw_ipu_dc_disp_conf1_3_t DC_DISP_CONF1_3; //!< DC Display Configuration 1 Register 3
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volatile hw_ipu_dc_disp_conf2_0_t DC_DISP_CONF2_0; //!< DC Display Configuration 2 Register 0
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volatile hw_ipu_dc_disp_conf2_1_t DC_DISP_CONF2_1; //!< DC Display Configuration 2 Register 1
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volatile hw_ipu_dc_disp_conf2_2_t DC_DISP_CONF2_2; //!< DC Display Configuration 2 Register 2
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volatile hw_ipu_dc_disp_conf2_3_t DC_DISP_CONF2_3; //!< DC Display Configuration 2 Register 3
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volatile hw_ipu_dc_di0_conf_1_t DC_DI0_CONF_1; //!< DC DI0Configuration Register 1
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volatile hw_ipu_dc_di0_conf_2_t DC_DI0_CONF_2; //!< DC DI0Configuration Register 2
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volatile hw_ipu_dc_di1_conf_1_t DC_DI1_CONF_1; //!< DC DI1Configuration Register 1
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volatile hw_ipu_dc_di1_conf_2_t DC_DI1_CONF_2; //!< DC DI1Configuration Register 2
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volatile hw_ipu_dc_map_conf_0_t DC_MAP_CONF_0; //!< DC Mapping Configuration Register 0
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volatile hw_ipu_dc_map_conf_1_t DC_MAP_CONF_1; //!< DC Mapping Configuration Register 1
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volatile hw_ipu_dc_map_conf_2_t DC_MAP_CONF_2; //!< DC Mapping Configuration Register 2
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volatile hw_ipu_dc_map_conf_3_t DC_MAP_CONF_3; //!< DC Mapping Configuration Register 3
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volatile hw_ipu_dc_map_conf_4_t DC_MAP_CONF_4; //!< DC Mapping Configuration Register 4
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volatile hw_ipu_dc_map_conf_5_t DC_MAP_CONF_5; //!< DC Mapping Configuration Register 5
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volatile hw_ipu_dc_map_conf_6_t DC_MAP_CONF_6; //!< DC Mapping Configuration Register 6
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volatile hw_ipu_dc_map_conf_7_t DC_MAP_CONF_7; //!< DC Mapping Configuration Register 7
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volatile hw_ipu_dc_map_conf_8_t DC_MAP_CONF_8; //!< DC Mapping Configuration Register 8
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volatile hw_ipu_dc_map_conf_9_t DC_MAP_CONF_9; //!< DC Mapping Configuration Register 9
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volatile hw_ipu_dc_map_conf_10_t DC_MAP_CONF_10; //!< DC Mapping Configuration Register 10
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volatile hw_ipu_dc_map_conf_11_t DC_MAP_CONF_11; //!< DC Mapping Configuration Register 11
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volatile hw_ipu_dc_map_conf_12_t DC_MAP_CONF_12; //!< DC Mapping Configuration Register 12
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volatile hw_ipu_dc_map_conf_13_t DC_MAP_CONF_13; //!< DC Mapping Configuration Register 13
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volatile hw_ipu_dc_map_conf_14_t DC_MAP_CONF_14; //!< DC Mapping Configuration Register 14
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volatile hw_ipu_dc_map_conf_15_t DC_MAP_CONF_15; //!< DC Mapping Configuration Register 15
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volatile hw_ipu_dc_map_conf_16_t DC_MAP_CONF_16; //!< DC Mapping Configuration Register 16
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volatile hw_ipu_dc_map_conf_17_t DC_MAP_CONF_17; //!< DC Mapping Configuration Register 17
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volatile hw_ipu_dc_map_conf_18_t DC_MAP_CONF_18; //!< DC Mapping Configuration Register 18
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volatile hw_ipu_dc_map_conf_19_t DC_MAP_CONF_19; //!< DC Mapping Configuration Register 19
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volatile hw_ipu_dc_map_conf_20_t DC_MAP_CONF_20; //!< DC Mapping Configuration Register 20
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volatile hw_ipu_dc_map_conf_21_t DC_MAP_CONF_21; //!< DC Mapping Configuration Register 21
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volatile hw_ipu_dc_map_conf_22_t DC_MAP_CONF_22; //!< DC Mapping Configuration Register 22
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volatile hw_ipu_dc_map_conf_23_t DC_MAP_CONF_23; //!< DC Mapping Configuration Register 23
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volatile hw_ipu_dc_map_conf_24_t DC_MAP_CONF_24; //!< DC Mapping Configuration Register 24
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volatile hw_ipu_dc_map_conf_25_t DC_MAP_CONF_25; //!< DC Mapping Configuration Register 25
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volatile hw_ipu_dc_map_conf_26_t DC_MAP_CONF_26; //!< DC Mapping Configuration Register 26
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volatile hw_ipu_dc_ugde0_0_t DC_UGDE0_0; //!< DC User General Data Event 0 Register 0
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volatile hw_ipu_dc_ugde0_1_t DC_UGDE0_1; //!< DC User General Data Event 0 Register 1
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volatile hw_ipu_dc_ugde0_2_t DC_UGDE0_2; //!< DC User General Data Event 0 Register2
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volatile hw_ipu_dc_ugde0_3_t DC_UGDE0_3; //!< DC User General Data Event 0 Register 3
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volatile hw_ipu_dc_ugde1_0_t DC_UGDE1_0; //!< DC User General Data Event 1Register0
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volatile hw_ipu_dc_ugde1_1_t DC_UGDE1_1; //!< DC User General Data Event 1 Register 1
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volatile hw_ipu_dc_ugde1_2_t DC_UGDE1_2; //!< DC User General Data Event 1Register 2
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volatile hw_ipu_dc_ugde1_3_t DC_UGDE1_3; //!< DC User General Data Event 1Register 3
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volatile hw_ipu_dc_ugde2_0_t DC_UGDE2_0; //!< DC User General Data Event 2 Register 0
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volatile hw_ipu_dc_ugde2_1_t DC_UGDE2_1; //!< DC User General Data Event 2 Register 1
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volatile hw_ipu_dc_ugde2_2_t DC_UGDE2_2; //!< DC User General Data Event 2Register 2
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volatile hw_ipu_dc_ugde2_3_t DC_UGDE2_3; //!< DC User General Data Event 2Register 3
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volatile hw_ipu_dc_ugde3_0_t DC_UGDE3_0; //!< DC User General Data Event 3Register 0
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volatile hw_ipu_dc_ugde3_1_t DC_UGDE3_1; //!< DC User General Data Event 3Register 1
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volatile hw_ipu_dc_ugde3_2_t DC_UGDE3_2; //!< DC User General Data Event 3Register 2
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volatile hw_ipu_dc_ugde3_3_t DC_UGDE3_3; //!< DC User General Data Event 3Register 2
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volatile hw_ipu_dc_lla0_t DC_LLA0; //!< DC Low Level Access Control Register 0
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volatile hw_ipu_dc_lla1_t DC_LLA1; //!< DC Low Level Access Control Register 1
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volatile hw_ipu_dc_r_lla0_t DC_R_LLA0; //!< DC Read Low Level Read Access Control Register 0
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volatile hw_ipu_dc_r_lla1_t DC_R_LLA1; //!< DC Read Low Level Read Access Control Register1
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volatile hw_ipu_dc_wr_ch_addr_5_alt_t DC_WR_CH_ADDR_5_ALT; //!< DC Write Channel 5 Configuration Register
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volatile hw_ipu_dc_stat_t DC_STAT; //!< DC Status Register
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reg32_t _reserved60[8076];
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volatile hw_ipu_dmfc_rd_chan_t DMFC_RD_CHAN; //!< DMFC Read Channel Register
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volatile hw_ipu_dmfc_wr_chan_t DMFC_WR_CHAN; //!< DMFC Write Channel Register
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volatile hw_ipu_dmfc_wr_chan_def_t DMFC_WR_CHAN_DEF; //!< DMFC Write Channel Definition Register
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volatile hw_ipu_dmfc_dp_chan_t DMFC_DP_CHAN; //!< DMFC Display Processor Channel Register
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volatile hw_ipu_dmfc_dp_chan_def_t DMFC_DP_CHAN_DEF; //!< DMFC Display Processor Channel Definition Register
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volatile hw_ipu_dmfc_general_1_t DMFC_GENERAL_1; //!< DMFC General 1 Register
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volatile hw_ipu_dmfc_general_2_t DMFC_GENERAL_2; //!< DMFC General 2 Register
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volatile hw_ipu_dmfc_ic_ctrl_t DMFC_IC_CTRL; //!< DMFC IC Interface Control Register
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volatile hw_ipu_dmfc_wr_chan_alt_t DMFC_WR_CHAN_ALT; //!< DMFC Write Channel Alternate Register
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volatile hw_ipu_dmfc_wr_chan_def_alt_t DMFC_WR_CHAN_DEF_ALT; //!< DMFC Write Channel Definition Alternate Register
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volatile hw_ipu_dmfc_dp_chan_alt_t DMFC_DP_CHAN_ALT; //!< DMFC MFC Display Processor Channel Alternate Register
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volatile hw_ipu_dmfc_dp_chan_def_alt_t DMFC_DP_CHAN_DEF_ALT; //!< DMFC Display Channel Definition Alternate Register
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volatile hw_ipu_dmfc_general1_alt_t DMFC_GENERAL1_ALT; //!< DMFC General 1 Alternate Register
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volatile hw_ipu_dmfc_stat_t DMFC_STAT; //!< DMFC Status Register
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reg32_t _reserved61[8178];
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volatile hw_ipu_vdi_fsize_t VDI_FSIZE; //!< VDI Field Size Register
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volatile hw_ipu_vdi_c_t VDI_C; //!< VDI Control Register
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volatile hw_ipu_vdi_c2_t VDI_C2; //!< VDI Control Register 2
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volatile hw_ipu_vdi_cmdp_1_t VDI_CMDP_1; //!< VDI Combining Parameters Register 1
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volatile hw_ipu_vdi_cmdp_2_t VDI_CMDP_2; //!< VDI Combining Parameters Register 2
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volatile hw_ipu_vdi_ps_1_t VDI_PS_1; //!< VDI Plane Size Register 1
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volatile hw_ipu_vdi_ps_2_t VDI_PS_2; //!< VDI Plane Size Register 2
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volatile hw_ipu_vdi_ps_3_t VDI_PS_3; //!< VDI Plane Size Register 3
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volatile hw_ipu_vdi_ps_4_t VDI_PS_4; //!< VDI Plane Size Register 4
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} hw_ipu_t;
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#pragma pack()
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//! @brief Macro to access all IPU registers.
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//! @param x IPU instance number.
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//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
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//! use the '&' operator, like <code>&HW_IPU(0)</code>.
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#define HW_IPU(x) (*(hw_ipu_t *) REGS_IPU_BASE(x))
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#endif
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#endif // __HW_IPU_REGISTERS_H__
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// v18/121106/1.2.2
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// EOF
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