forked from xuos/xiuos
104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
#define __SYSCALL_LL_E(x) \
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((union { long long ll; long l[2]; }){ .ll = x }).l[0], \
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((union { long long ll; long l[2]; }){ .ll = x }).l[1]
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#define __SYSCALL_LL_O(x) 0, __SYSCALL_LL_E((x))
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#ifdef __thumb__
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/* Avoid use of r7 in asm constraints when producing thumb code,
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* since it's reserved as frame pointer and might not be supported. */
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#define __ASM____R7__
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#define __asm_syscall(...) do { \
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__asm__ __volatile__ ( "mov %1,r7 ; mov r7,%2 ; svc 0 ; mov r7,%1" \
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: "=r"(r0), "=&r"((int){0}) : __VA_ARGS__ : "memory"); \
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return r0; \
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} while (0)
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#else
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#define __ASM____R7__ __asm__("r7")
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#define __asm_syscall(...) do { \
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__asm__ __volatile__ ( "svc 0" \
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: "=r"(r0) : __VA_ARGS__ : "memory"); \
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return r0; \
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} while (0)
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#endif
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/* For thumb2, we can allow 8-bit immediate syscall numbers, saving a
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* register in the above dance around r7. Does not work for thumb1 where
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* only movs, not mov, supports immediates, and we can't use movs because
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* it doesn't support high regs. */
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#ifdef __thumb2__
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#define R7_OPERAND "rI"(r7)
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#else
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#define R7_OPERAND "r"(r7)
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#endif
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static inline long __syscall0(long n)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0");
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__asm_syscall(R7_OPERAND);
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}
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static inline long __syscall1(long n, long a)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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__asm_syscall(R7_OPERAND, "0"(r0));
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}
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static inline long __syscall2(long n, long a, long b)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1));
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}
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static inline long __syscall3(long n, long a, long b, long c)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2));
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}
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static inline long __syscall4(long n, long a, long b, long c, long d)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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register long r3 __asm__("r3") = d;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3));
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}
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static inline long __syscall5(long n, long a, long b, long c, long d, long e)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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register long r3 __asm__("r3") = d;
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register long r4 __asm__("r4") = e;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3), "r"(r4));
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}
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static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
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{
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register long r7 __ASM____R7__ = n;
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register long r0 __asm__("r0") = a;
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register long r1 __asm__("r1") = b;
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register long r2 __asm__("r2") = c;
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register long r3 __asm__("r3") = d;
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register long r4 __asm__("r4") = e;
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register long r5 __asm__("r5") = f;
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__asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3), "r"(r4), "r"(r5));
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}
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#define SYSCALL_FADVISE_6_ARG
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#define SYSCALL_IPC_BROKEN_MODE
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