forked from xuos/xiuos
95 lines
3.4 KiB
C
95 lines
3.4 KiB
C
/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#include "libserial.h"
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#include "usyscall.h"
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enum {
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SW_INTERRUPT_3 = 3,
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};
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enum {
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ARM_PERIPHERAL_BASE = 0x00A00000,
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MX6Q_GICD_BASE_OFFSET = 0x1000,
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MX6Q_GICC_BASE_OFFSET = 0x100,
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ARM_PERIPHERAL_VIRT_BASE = 0x50000000,
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};
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enum _gicd_sgi_filter {
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//! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
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kGicSgiFilter_UseTargetList = 0,
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//! Forward the interrupt to all CPU interfaces except that of the processor that requested
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//! the interrupt.
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kGicSgiFilter_AllOtherCPUs = 1,
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//! Forward the interrupt only to the CPU interface of the processor that requested the
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//! interrupt.
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kGicSgiFilter_OnlyThisCPU = 2
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};
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struct _gicd_registers {
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uint32_t CTLR; //!< Distributor Control Register.
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uint32_t TYPER; //!< Interrupt Controller Type Register.
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uint32_t IIDR; //!< Distributor Implementer Identification Register.
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uint32_t _reserved0[29];
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uint32_t IGROUPRn[8]; //!< Interrupt Group Registers.
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uint32_t _reserved1[24];
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uint32_t ISENABLERn[32]; //!< Interrupt Set-Enable Registers.
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uint32_t ICENABLERn[32]; //!< Interrupt Clear-Enable Registers.
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uint32_t ISPENDRn[32]; //!< Interrupt Set-Pending Registers.
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uint32_t ICPENDRn[32]; //!< Interrupt Clear-Pending Registers.
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uint32_t ICDABRn[32]; //!< Active Bit Registers.
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uint32_t _reserved2[32];
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uint8_t IPRIORITYRn[255 * sizeof(uint32_t)]; //!< Interrupt Priority Registers. (Byte accessible)
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uint32_t _reserved3;
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uint8_t ITARGETSRn[255 * sizeof(uint32_t)]; //!< Interrupt Processor Targets Registers. (Byte accessible)
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uint32_t _reserved4;
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uint32_t ICFGRn[64]; //!< Interrupt Configuration Registers.
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uint32_t _reserved5[128];
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uint32_t SGIR; //!< Software Generated Interrupt Register
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};
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typedef volatile struct _gicd_registers gicd_t;
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enum _gicd_sgir_fields {
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kBP_GICD_SGIR_TargetListFilter = 24,
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kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter),
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kBP_GICD_SGIR_CPUTargetList = 16,
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kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList),
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kBP_GICD_SGIR_NSATT = 15,
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kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT),
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kBP_GICD_SGIR_SGIINTID = 0,
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kBM_GICD_SGIR_SGIINTID = 0xf
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};
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void gic_send_sgi(uint32_t irqID, uint32_t target_list, uint32_t filter_list)
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{
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gicd_t* gicd = (gicd_t*)(ARM_PERIPHERAL_VIRT_BASE + MX6Q_GICD_BASE_OFFSET);
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gicd->SGIR = (filter_list << kBP_GICD_SGIR_TargetListFilter) //
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| (target_list << kBP_GICD_SGIR_CPUTargetList) //
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| (irqID & 0xf);
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}
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int main()
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{
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static char prog_name[] = "TEST_IRQ_SEND";
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printf("%s: Mapping GIC\n", prog_name);
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mmap(ARM_PERIPHERAL_VIRT_BASE, ARM_PERIPHERAL_BASE, 0x2000, true);
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printf("%s: Sending soft interrupt\n", prog_name);
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gic_send_sgi(SW_INTERRUPT_3, 0xF, kGicSgiFilter_UseTargetList);
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printf("%s: Soft interrupt send done\n", prog_name);
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exit();
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} |