forked from xuos/xiuos
Wang_Weigen
230 lines
14 KiB
C
230 lines
14 KiB
C
/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if !defined(__IRQ_NUMBERS_H__)
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#define __IRQ_NUMBERS_H__
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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//! @brief i.MX6 interrupt numbers.
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//!
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//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series.
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//! Use these numbers when specifying an interrupt to the GIC.
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//!
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//! The first 16 interrupts are special in that they are reserved for software interrupts generated
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//! by the SWI instruction.
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enum _imx_interrupts
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{
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SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
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SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
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SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
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SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
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SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
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SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
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SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
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SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
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SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
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SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
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SW_INTERRUPT_10 = 10, //!< Software interrupt 10.
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SW_INTERRUPT_11 = 11, //!< Software interrupt 11.
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SW_INTERRUPT_12 = 12, //!< Software interrupt 12.
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SW_INTERRUPT_13 = 13, //!< Software interrupt 13.
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SW_INTERRUPT_14 = 14, //!< Software interrupt 14.
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SW_INTERRUPT_15 = 15, //!< Software interrupt 15.
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RSVD_INTERRUPT_16 = 16, //!< Reserved.
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RSVD_INTERRUPT_17 = 17, //!< Reserved.
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RSVD_INTERRUPT_18 = 18, //!< Reserved.
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RSVD_INTERRUPT_19 = 19, //!< Reserved.
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RSVD_INTERRUPT_20 = 20, //!< Reserved.
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RSVD_INTERRUPT_21 = 21, //!< Reserved.
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RSVD_INTERRUPT_22 = 22, //!< Reserved.
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RSVD_INTERRUPT_23 = 23, //!< Reserved.
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RSVD_INTERRUPT_24 = 24, //!< Reserved.
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RSVD_INTERRUPT_25 = 25, //!< Reserved.
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RSVD_INTERRUPT_26 = 26, //!< Reserved.
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RSVD_INTERRUPT_27 = 27, //!< Reserved.
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RSVD_INTERRUPT_28 = 28, //!< Reserved.
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RSVD_INTERRUPT_29 = 29, //!< Reserved.
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RSVD_INTERRUPT_30 = 30, //!< Reserved.
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RSVD_INTERRUPT_31 = 31, //!< Reserved.
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IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot.
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IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM
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IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels.
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IMX_INT_VPU_JPG = 35, //!< JPEG codec interrupt request.
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IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request.
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IMX_INT_IPU1_ERR = 37, //!< IPU1 error interrupt request.
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IMX_INT_IPU1_FUNC = 38, //!< IPU1 sync interrupt request.
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IMX_INT_IPU2_ERR = 39, //!< IPU2 error interrupt request.
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IMX_INT_IPU2_FUNC = 40, //!< IPU2 sync interrupt request.
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IMX_INT_GPU3D = 41, //!< GPU3D interrupt request.
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IMX_INT_GPU2D = 42, //!< Idle interrupt from GPU2D (for S/W power gating).
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IMX_INT_OPENVG_XAQ2 = 43, //!< GPU2D general interrupt request.
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IMX_INT_VPU_IPI = 44, //!< VPU interrupt request.
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IMX_INT_APBHDMA = 45, //!< Logical OR of 4 signals: dma_chan[0-3]_irq, GPMI operation channel description complete interrupt.
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IMX_INT_EIM = 46, //!< EIM interrupt request.
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IMX_INT_BCH = 47, //!< BCH operation complete interrupt.
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IMX_INT_GPMI = 48, //!< GPMI operation timeout error interrupt.
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IMX_INT_DTCP = 49, //!< DTCP interrupt request.
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IMX_INT_VDOA = 50, //!< Logical OR of VDOA interrupt requests.
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IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt.
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IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt.
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IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted.
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IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request.
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IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request.
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IMX_INT_USDHC3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request.
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IMX_INT_USDHC4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request.
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IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests.
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IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests.
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IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests.
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IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests.
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IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests.
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IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request.
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IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request.
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IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request.
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IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request.
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IMX_INT_ECSPI5 = 67, //!< eCSPI5 interrupt request.
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IMX_INT_I2C1 = 68, //!< I2C1 interrupt request.
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IMX_INT_I2C2 = 69, //!< I2C2 interrupt request.
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IMX_INT_I2C3 = 70, //!< I2C3 interrupt request.
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IMX_INT_SATA = 71, //!< SATA interrupt request.
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IMX_INT_USBOH3_UH1 = 72, //!< USB Host 1 interrupt request.
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IMX_INT_USBOH3_UH2 = 73, //!< USB Host 2 interrupt request.
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IMX_INT_USBOH3_UH3 = 74, //!< USB Host 3 interrupt request.
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IMX_INT_USBOH3_UOTG = 75, //!< USB OTG interrupt request.
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IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request.
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IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request.
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IMX_INT_SSI1 = 78, //!< SSI1 interrupt request.
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IMX_INT_SSI2 = 79, //!< SSI2 interrupt request.
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IMX_INT_SSI3 = 80, //!< SSI3 interrupt request.
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IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request.
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IMX_INT_ASRC = 82, //!< ASRC interrupt request.
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IMX_INT_ESAI = 83, //!< ESAI interrupt request.
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IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts.
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IMX_INT_MLB = 85, //!< MLB error interrupt request.
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IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request.
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IMX_INT_GPT = 87, //!< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines.
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IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt.
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IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt.
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IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request.
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IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request.
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IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request.
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IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request.
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IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request.
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IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request.
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IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request.
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IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request.
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IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15.
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IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31.
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IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15.
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IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31.
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IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15.
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IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31.
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IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15.
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IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31.
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IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15.
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IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31.
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IMX_INT_GPIO6_INT15_0 = 108, //!< Combined interrupt indication for GPIO6 signals 0 - 15.
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IMX_INT_GPIO6_INT31_16 = 109, //!< Combined interrupt indication for GPIO6 signals 16 - 31.
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IMX_INT_GPIO7_INT15_0 = 110, //!< Combined interrupt indication for GPIO7 signals 0 - 15.
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IMX_INT_GPIO7_INT31_16 = 111, //!< Combined interrupt indication for GPIO7 signals 16 - 31.
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IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request.
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IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request.
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IMX_INT_KPP = 114, //!< Key Pad interrupt request.
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IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
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IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
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IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
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IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
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IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1.
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IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2.
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IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1.
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IMX_INT_GPC_INT2 = 122, //!< GPC interrupt request 2.
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IMX_INT_SRC = 123, //!< SRC interrupt request.
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IMX_INT_CHEETAH_L2 = 124, //!< Logical OR of all L2 interrupt requests.
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IMX_INT_CHEETAH_PARITY = 125, //!< Parity Check error interrupt request.
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IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts.
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IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs.
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IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC.
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IMX_INT_INTERRUPT_129 = 129, //!< Reserved.
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IMX_INT_INTERRUPT_130 = 130, //!< Reserved.
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IMX_INT_INTERRUPT_131 = 131, //!< Reserved.
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IMX_INT_CSI_INTR1 = 132, //!< MIPI CSI interrupt request 1.
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IMX_INT_CSI_INTR2 = 133, //!< MIPI CSI interrupt request 2.
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IMX_INT_DSI = 134, //!< MIPI DSI interrupt request.
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IMX_INT_HSI = 135, //!< MIPI HSI interrupt request.
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IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register.
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IMX_INT_CAAM_INT0 = 137, //!< CAAM job ring 0 interrupt.
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IMX_INT_CAAM_INT1 = 138, //!< CAAM job ring 1 interrupt.
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IMX_INT_INTERRUPT_139 = 139, //!< Reserved.
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IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request.
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IMX_INT_TZASC2 = 141, //!< ASC2 interrupt request.
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IMX_INT_FLEXCAN1 = 142, //!< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
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IMX_INT_FLEXCAN2 = 143, //!< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
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IMX_INT_PERFMON1 = 144, //!< Reserved.
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IMX_INT_PERFMON2 = 145, //!< Reserved.
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IMX_INT_PERFMON3 = 146, //!< Reserved.
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IMX_INT_HDMI_TX = 147, //!< HDMI master interrupt request.
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IMX_INT_HDMI_TX_WAKEUP = 148, //!< HDMI CEC engine dedicated interrupt signal raised by a wake-up event.
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IMX_INT_MLB_AHB0 = 149, //!< Channels [31:0] interrupt requests.
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IMX_INT_ENET = 150, //!< MAC 0 IRQ, Logical OR of:
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//! - MAC 0 Periodic Timer Overflow
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//! - MAC 0 Time Stamp Available
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//! - MAC 0 Payload Receive Error
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//! - MAC 0 Transmit FIFO Underrun
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//! - MAC 0 Collision Retry Limit
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//! - MAC 0 Late Collision
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//! - MAC 0 Ethernet Bus Error
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//! - MAC 0 MII Data Transfer Done
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//! - MAC 0 Receive Buffer Done
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//! - MAC 0 Receive Frame Done
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//! - MAC 0 Transmit Buffer Done
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//! - MAC 0 Transmit Frame Done
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//! - MAC 0 Graceful Stop
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//! - MAC 0 Babbling Transmit Error
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//! - MAC 0 Babbling Receive Error
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//! - MAC 0 Wakeup Request [synchronous]
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IMX_INT_ENET_1588 = 151, //!< MAC 0 1588 Timer interrupt [synchronous] request.
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IMX_INT_PCIE_1 = 152, //!< PCIe interrupt request 1.
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IMX_INT_PCIE_2 = 153, //!< PCIe interrupt request 2.
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IMX_INT_PCIE_3 = 154, //!< PCIe interrupt request 3.
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IMX_INT_PCIE_4 = 155, //!< PCIe interrupt request 4.
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IMX_INT_DCIC1 = 156, //!< Logical OR of DCIC1 interrupt requests.
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IMX_INT_DCIC2 = 157, //!< Logical OR of DCIC2 interrupt requests.
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IMX_INT_MLB_AHB1 = 158, //!< Logical OR of channel[63:32] interrupt requests.
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IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request.
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IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts.
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};
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#endif // __IRQ_NUMBERS_H__
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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