forked from xuos/xiuos
193 lines
5.3 KiB
C
193 lines
5.3 KiB
C
/*
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* Copyright (c) 2022 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file l2_cache.h
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* @brief the general management of L2 cache
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* @version 3.0
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* @author AIIT XUOS Lab
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* @date 2023/08/10
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*/
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/*************************************************
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File name: l2_cache.h
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Description: the general management of L2 cache
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Others:
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History:
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1. Date: 2023-08-10
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Author: AIIT XUOS Lab
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Modification:
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1、define the l2 cache operations
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*************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#define CONFIG_ARCH_L2CACHE
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#ifdef CONFIG_ARCH_L2CACHE
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arm_l2ccinitialize
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*
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* Description:
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* One time configuration of the L2 cache. The L2 cache will be enabled
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* upon return.
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*
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* Input Parameters:
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* None. The L2 cache configuration is controlled by configuration
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* settings.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arm_l2ccinitialize(void);
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void pl310_flush_all(void);
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/****************************************************************************
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* Name: l2cc_enable
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*
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* Description:
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* Re-enable the L2CC-P310 L2 cache by setting the enable bit in the
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* Control Register (CR)
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*
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****************************************************************************/
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void EnableL2Cache(void);
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/****************************************************************************
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* Name: l2cc_disable
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*
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* Description:
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* Disable the L2 cache
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*
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****************************************************************************/
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void DisableL2Cache(void);
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/****************************************************************************
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* Name: l2cc_sync
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*
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* Description:
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* Drain the L2 cache.
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*
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****************************************************************************/
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void SyncL2Cache(void);
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/****************************************************************************
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* Name: l2cc_invalidate_all
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*
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* Description:
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* Invalidate the entire L2 cache.
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*
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****************************************************************************/
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void InvalidateL2CacheAll(void);
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/****************************************************************************
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* Name: l2cc_invalidate
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*
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* Description:
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* Invalidate a range of addresses in the L2 cache
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*
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****************************************************************************/
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void InvalidateL2Cache(uintptr_t startaddr, uintptr_t endaddr);
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/****************************************************************************
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* Name: l2cc_clean_all
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*
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* Description:
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* Clean the entire L2 cache.
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*
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****************************************************************************/
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void CleanL2CacheAll(void);
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/****************************************************************************
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* Name: l2cc_clean
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*
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* Description:
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* Clean a range of address within the L2 cache.
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*
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****************************************************************************/
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void CleanL2Cache(uintptr_t startaddr, uintptr_t endaddr);
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/****************************************************************************
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* Name: l2cc_flush_all
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*
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* Description:
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* Flush the entire L2 cache.
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*
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****************************************************************************/
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void FlushL2CacheAll(void);
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/****************************************************************************
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* Name: l2cc_flush
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*
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* Description:
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* Flush a range of address within the L2 cache.
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*
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****************************************************************************/
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void FlushL2Cache(uint32_t startaddr, uint32_t endaddr);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_ARCH_L2CACHE */
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/* Provide simple definitions to concentrate the inline conditional
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* compilation in one place.
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*/
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#define EnableL2Cache()
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#define DisableL2Cache()
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#define SyncL2Cache()
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#define InvalidateL2CacheAll()
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#define InvalidateL2Cache(s,e)
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#define CleanL2CacheAll()
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#define CleanL2Cache(s,e)
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#define FlushL2CacheAll()
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#define FlushL2Cache(s,e)
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#endif /* CONFIG_ARCH_L2CACHE */
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