forked from xuos/xiuos
130 lines
4.6 KiB
C
130 lines
4.6 KiB
C
/*
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* Copyright (c) 2022 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file l1cache.c
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* @brief PLC inovance am401 app
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* @version 3.0
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* @author AIIT XUOS Lab
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* @date 2023.8.10
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*/
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#include <stdint.h>
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#include <sys/types.h>
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#include "cortex_a9.h"
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/* Terms:
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* 1) Point of coherency (PoC)
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* The PoC is the point at which all agents that can access memory are
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* guaranteed to see the same copy of a memory location
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* 2) Point of unification (PoU)
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* The PoU is the point by which the instruction and data caches and the
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* translation table walks of the processor are guaranteed to see the same
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* copy of a memory location.
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*
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* L1 Cache Operations:
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*
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* CP15 Register: ICIALLUIS
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* Description: Invalidate entire instruction cache Inner Shareable.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c1, 0
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* CP15 Register: BPIALLIS
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* Description: Invalidate entire branch predictor array Inner
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* Shareable.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c1, 6
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* CP15 Register: ICIALLU
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* Description: Invalidate all instruction caches to PoU. Also flushes
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* branch target cache.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 0
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* CP15 Register: ICIMVAU
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* Description: Invalidate instruction cache by VA to PoU.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 1
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* CP15 Register: CP15ISB
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* Description: Instruction Synchronization Barrier operation
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* NOTE: Deprecated and no longer documented
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 4
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* CP15 Register: BPIALL
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* Description: Invalidate entire branch predictor array.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 6
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* CP15 Register: BPIMVA
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* Description: Invalidate VA from branch predictor array.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 7
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* CP15 Register: DCIMVAC
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* Description: Invalidate data cache line by VA to PoC.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c6, 1
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* CP15 Register: DCISW
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* Description: Invalidate data cache line by Set/Way.
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* Register Format: Set/Way
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* Instruction: MCR p15, 0, <Rd>, c7, c6, 2
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* CP15 Register: DCCMVAC
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* Description: Clean data cache line to PoC by VA.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 1
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* CP15 Register: DCCSW
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* Description: Clean data cache line by Set/Way.
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* Register Format: Set/Way
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 2
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* CP15 Register: CP15DSB
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* Description: Data Synchronization Barrier operation
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* NOTE: Deprecated and no longer documented
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 4
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* CP15 Register: CP15DMB
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* Description: Data Memory Barrier operation
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* NOTE: Deprecated and no longer documented
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 5
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* CP15 Register: DCCMVAU
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* Description: Clean data or unified cache line by VA to PoU.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c11, 1
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* CP15 Register: DCCIMVAC
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* Description: Clean and invalidate data cache line by VA to PoC.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c14, 1
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* CP15 Register: DCCISW
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* Description: Clean and invalidate data cache line by Set/Way.
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* Register Format: Set/Way
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* Instruction: MCR p15, 0, <Rd>, c7, c14, 2
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*/
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#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable
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#define BM_SCTLR_C (1 << 2) //!< Data cache enable
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void InvalidateL1Dcache(uintptr_t start, uintptr_t end);
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void InvalidateL1DcacheAll(void);
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void CleanL1Dcache(uintptr_t start, uintptr_t end);
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void CleanL1DcacheAll(void);
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void FlushL1Dcache(uintptr_t start, uintptr_t end);
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void FlushL1DcacheAll(void);
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void InvalidateL1IcacheAll(void);
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void InvalidateL1Icache(uintptr_t start, uintptr_t end);
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void EnableL1Icache(void);
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void DisableL1Icache();
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void EnableL1Dcache();
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void DisableL1Dcache(); |