forked from xuos/xiuos
279 lines
8.3 KiB
C
279 lines
8.3 KiB
C
#include "l1cache.h"
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#include "cp15_cacheops.h"
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#include "barriers.h"
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void InvalidateL1Dcache(uintptr_t start, uintptr_t end)
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{
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size_t length=end-start;
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void* addr=start;
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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// align the address with line
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const void * end_addr = (const void *)((uint32_t)addr + length);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 6, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void InvalidateL1DcacheAll(void)
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{
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uint32_t csid; // Cache Size ID
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uint32_t wayset; // wayset parameter
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int num_sets; // number of sets
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int num_ways; // number of ways
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_ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID
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// Fill number of sets and number of ways from csid register This walues are decremented by 1
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num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT)
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// Invalidation all lines (all Sets in all ways)
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while (num_ways >= 0)
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{
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num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT)
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while (num_sets >= 0 )
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{
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wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT)
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// invalidate line if we know set and way
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_ARM_MCR(15, 0, wayset, 7, 6, 2);
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num_sets--;
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}
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num_ways--;
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}
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void CleanL1Dcache(uintptr_t start, uintptr_t end)
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{
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void* addr=start;
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size_t length=end-start;
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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const void * end_addr = (const void *)((uint32_t)addr + length);
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 10, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void CleanL1DcacheAll(void)
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{
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uint32_t csid; // Cache Size ID
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uint32_t wayset; // wayset parameter
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int num_sets; // number of sets
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int num_ways; // number of ways
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_ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID
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// Fill number of sets and number of ways from csid register This walues are decremented by 1
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num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`)
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while (num_ways >= 0)
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{
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num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT )
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while (num_sets >= 0 )
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{
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wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT)
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// FLUSH (clean) line if we know set and way
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_ARM_MCR(15, 0, wayset, 7, 10, 2);
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num_sets--;
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}
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num_ways--;
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}
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void FlushL1Dcache(uintptr_t start, uintptr_t end)
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{
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void* addr=start;
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size_t length=end-start;
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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const void * end_addr = (const void *)((uint32_t)end);
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 14, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void FlushL1DcacheAll(void)
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{
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uint32_t csid; // Cache Size ID
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uint32_t wayset; // wayset parameter
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int num_sets; // number of sets
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int num_ways; // number of ways
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_ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID
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// Fill number of sets and number of ways from csid register This walues are decremented by 1
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num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`)
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while (num_ways >= 0)
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{
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num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT )
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while (num_sets >= 0 )
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{
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wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT)
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// FLUSH (clean) line if we know set and way
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_ARM_MCR(15, 0, wayset, 7, 14, 2);
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num_sets--;
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}
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num_ways--;
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}
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void InvalidateL1IcacheAll()
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{
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uint32_t SBZ = 0x0u;
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_ARM_MCR(15, 0, SBZ, 7, 5, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void InvalidateL1Icache(uintptr_t start, uintptr_t end)
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{
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void* addr=start;
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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const void * end_addr = (const void *)((uint32_t)end);
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 5, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void EnableL1Icache(void)
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{
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uint32_t sctlr ;// System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// ignore the operation if I is enabled already
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if(!(sctlr & BM_SCTLR_I))
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{
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// set I bit (instruction caching enable)
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sctlr |= BM_SCTLR_I;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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}
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void DisableL1Icache()
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{
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uint32_t sctlr ;// System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// Clear I bit (instruction caching enable)
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sctlr &= ~BM_SCTLR_I;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void EnableL1Dcache()
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{
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uint32_t sctlr; // System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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if (!(sctlr & BM_SCTLR_C))
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{
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// set C bit (data caching enable)
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sctlr |= BM_SCTLR_C;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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}
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void DisableL1Dcache()
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{
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uint32_t sctlr; // System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// set C bit (data caching enable)
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sctlr &= ~BM_SCTLR_C;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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} |