forked from xuos/xiuos
57 lines
1.5 KiB
C
Executable File
57 lines
1.5 KiB
C
Executable File
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#define CP15_TLBIALLIS(r) _CP15(0, r, c8, c3, 0) /* Invalidate entire unified TLB Inner Shareable */
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#define CP15_TLBIMVAIS(r) _CP15(0, r, c8, c3, 1) /* Invalidate unified TLB entry by MVA and ASID, Inner Shareable */
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#define CP15_TLBIASIDIS(r) _CP15(0, r, c8, c3, 2) /* Invalidate unified TLB by ASID match Inner Shareable */
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#define CP15_TLBIMVAAIS(r) _CP15(0, r, c8, c3, 3) /* Invalidate unified TLB entry by MVA all ASID Inner Shareable */
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#define CP15_TLBIALL(r,c) _CP15(0, r, c8, c, 0) /* Invalidate entire instruction TLB. CRm = c5, c6, or c7 */
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#define CP15_TLBIMVA(r,c) _CP15(0, r, c8, c, 1) /* Invalidate instruction TLB entry by MVA and ASID. CRm = c5, c6, or c7 */
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#define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2) /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */
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#define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3) /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */
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void InvalidateTlbsAll(void)
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{
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__asm__ __volatile__
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(
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"\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */
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:
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:
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: "r0", "memory"
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);
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}
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void InvalidateTlbMVA(uint32_t vaddr)
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{
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__asm__ __volatile__
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(
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"\tdsb\n"
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"\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */
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"\tdsb\n"
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"\tisb\n"
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:
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: "r" (vaddr)
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: "r1", "memory"
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);
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}
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void InvalidateTlbASID(uint32_t vaddr)
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{
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__asm__ __volatile__
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(
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"\tdsb\n"
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"\tmcr p15, 0, %0, c8, c7, 2\n" /* TLBIASID */
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"\tdsb\n"
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"\tisb\n"
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:
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: "r" (vaddr)
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: "r1", "memory"
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);
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}
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