Support double lwip eport, use mongoose.a from Tu_Yuyang

it is OK

APP_Framework/Applications/Kconfig

@@ -20,4 +20,5 @@ menu "Applications"
     source "$APP_DIR/Applications/sensor_app/Kconfig"
     source "$APP_DIR/Applications/embedded_database_app/Kconfig"
     source "$APP_DIR/Applications/webnet/Kconfig"
+    source "$APP_DIR/Applications/mongoose/Kconfig"
 endmenu

APP_Framework/Applications/Makefile

@@ -39,6 +39,10 @@ ifeq ($(CONFIG_ADD_XIZI_FEATURES),y)
     ifeq ($(CONFIG_APP_USING_WEBNET),y)
         SRC_DIR += webnet
     endif
+    
+    ifeq ($(CONFIG_USE_MONGOOSE),y)
+        SRC_DIR += mongoose
+    endif
 
     include $(KERNEL_ROOT)/compiler.mk
 endif

APP_Framework/Applications/app_test/test_socket.c

@@ -76,10 +76,12 @@ struct IperfParam {
 static void* TestIperfServer(void* param)
 {
     struct IperfParam* iperf_param = (struct IperfParam*)param;
-    int sock = socket(AF_INET, SOCK_STREAM, 0);
+    int sock = socket(AF_INET, SOCK_STREAM, 6);
     if (sock < 0) {
         printf("[%s] Err: Can't create socker.\n", __func__);
         return NULL;
+    } else {
+        printf("[%s] Info Create server socket %d\n", __func__, sock);
     }
 
     uint8_t* recv_data = (uint8_t*)malloc(IPERF_BUFSZ);
@@ -121,8 +123,9 @@ static void* TestIperfServer(void* param)
         socklen_t sin_size = sizeof(struct sockaddr_in);
         struct sockaddr_in client_addr;
         int connection = accept(sock, (struct sockaddr*)&client_addr, &sin_size);
-        printf("[%s] Info: New client connected from (%s, %d)\n", __func__,
+        printf("[%s] Info: New client connected from (%s, %d), connect: %d\n", __func__,
-            inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
+            inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port),
+            connection);
 
         int flag = 1;
         setsockopt(connection,
@@ -141,8 +144,8 @@ static void* TestIperfServer(void* param)
                     inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
                 break;
             } else if (bytes_received < 0) {
-                KPrintf("recv error, client: (%s, %d)\n",
+                KPrintf("recv error: %d, client: (%s, %d)\n",
-                    inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
+                    bytes_received, inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
                 break;
             }
 
@@ -258,8 +261,6 @@ enum IperfParamEnum {
 
 void TestSocket(int argc, char* argv[])
 {
-    lwip_config_tcp(0, lwip_ipaddr, lwip_netmask, lwip_gwaddr);
-
     static char usage_info[] = "Run either a iperf server or iperf client.";
     static char program_info[] = "Lwip socket test task, a simple iperf.";
     static const char* const usages[] = {

APP_Framework/Applications/mongoose/Kconfig

@@ -0,0 +1,3 @@
+menuconfig USE_MONGOOSE
+    bool "Use mongoose as webserver"
+    default n

APP_Framework/Applications/mongoose/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES += project.c
+
+include $(KERNEL_ROOT)/compiler.mk

APP_Framework/Applications/mongoose/lib/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES += mongoose.c 
+
+include $(KERNEL_ROOT)/compiler.mk

APP_Framework/Applications/mongoose/project.c

@@ -0,0 +1,142 @@
+// Copyright (c) 2022 Cesanta Software Limited
+// All rights reserved
+//
+// UI example
+// It implements the following endpoints:
+//    /api/config/get - respond with current config
+//    /api/config/set - POST a config change
+//    any other URI serves static files from s_root_dir
+// Data and results are JSON strings
+
+#include "ip_addr.h"
+#include "mongoose.h"
+#include "netdev.h"
+
+char index_path[] = "login.html";
+
+static const char* s_http_addr = "http://192.168.131.88:8000"; // HTTP port
+static const char* s_root_dir = "webserver";
+static const char* s_enable_hexdump = "no";
+static const char* s_ssi_pattern = "#.html";
+
+static const char* device_type = "Edu-ARM32";
+static const char* web_version = "XUOS Webserver 1.0";
+static int enable_4g = 0;
+
+static struct netdev* p_netdev;
+
+static struct config {
+    char *ip, *mask, *gw, *dns;
+} s_config;
+
+// Try to update a single configuration value
+static void update_config(struct mg_str json, const char* path, char** value)
+{
+    char* jval;
+    if ((jval = mg_json_get_str(json, path)) != NULL) {
+        free(*value);
+        *value = strdup(jval);
+    }
+}
+
+static void fn(struct mg_connection* c, int ev, void* ev_data, void* fn_data)
+{
+    if (ev == MG_EV_HTTP_MSG) {
+        struct mg_http_message *hm = (struct mg_http_message*)ev_data, tmp = { 0 };
+        if (mg_http_match_uri(hm, "/getSystemInfo")) {
+            mg_http_reply(c, 200, "Content-Type: application/json\r\n",
+                "{%m:%m, %m:%m, %m:%m, %m:%m, %m:%m, %m:%d}\n",
+                MG_ESC("ip"), MG_ESC(s_config.ip),
+                MG_ESC("deviceType"), MG_ESC(device_type),
+                MG_ESC("deviceNo"), MG_ESC("0"),
+                MG_ESC("systemTime"), MG_ESC("YYYY:MM:DD hh:mm:ss"),
+                MG_ESC("webVersion"), MG_ESC(web_version),
+                MG_ESC("statusOf4g"), enable_4g);
+        } else if (mg_http_match_uri(hm, "/net/get4gInfo")) {
+            mg_http_reply(c, 200, "Content-Type: application/json\r\n",
+                "{%m:%m}\n",
+                MG_ESC("enable4g"), MG_ESC(enable_4g));
+        } else if (mg_http_match_uri(hm, "/net/set4gInfo")) {
+            struct mg_str json = hm->body;
+            enable_4g = mg_json_get_long(json, "$.enable4g", 0);
+            mg_http_reply(c, 200, "Content-Type: application/json\r\n", "{\"status\":\"success\"}\r\n");
+            printf("Get enable 4g setting: %d\n", enable_4g);
+        } else if (mg_http_match_uri(hm, "/net/getEthernetInfo")) {
+            mg_http_reply(c, 200, "Content-Type: application/json\r\n",
+                "{%m:%m, %m:%m, %m:%m, %m:%m}\n",
+                MG_ESC("ip"), MG_ESC(s_config.ip),
+                MG_ESC("netmask"), MG_ESC(s_config.mask),
+                MG_ESC("gateway"), MG_ESC(s_config.gw),
+                MG_ESC("dns"), MG_ESC(s_config.dns));
+        } else if (mg_http_match_uri(hm, "/net/setEthernetInfo")) {
+            struct mg_str json = hm->body;
+            printf("json: %s\n", json.ptr);
+            update_config(json, "$.ip", &s_config.ip);
+            update_config(json, "$.netmask", &s_config.mask);
+            update_config(json, "$.gateway", &s_config.gw);
+            update_config(json, "$.dns", &s_config.dns);
+            mg_http_reply(c, 200, "Content-Type: application/json\r\n", "{\"status\":\"success\"}\r\n");
+
+            ip_addr_t ipaddr, maskaddr, gwaddr;
+            inet_aton(s_config.ip, &ipaddr);
+            inet_aton(s_config.mask, &maskaddr);
+            inet_aton(s_config.gw, &gwaddr);
+            p_netdev->ops->set_addr_info(p_netdev, &ipaddr, &maskaddr, &gwaddr);
+
+            printf("Board Net Configuration changed to [IP: %s, Mask: %s, GW: %s, DNS: %s]\n",
+                s_config.ip,
+                s_config.mask,
+                s_config.gw,
+                s_config.dns);
+        } else {
+            struct mg_str unknown = mg_str_n("?", 1), *cl;
+            struct mg_http_serve_opts opts = { .root_dir = s_root_dir, .ssi_pattern = s_ssi_pattern };
+            mg_http_serve_dir(c, hm, &opts);
+            mg_http_parse((char*)c->send.buf, c->send.len, &tmp);
+            cl = mg_http_get_header(&tmp, "Content-Length");
+            if (cl == NULL)
+                cl = &unknown;
+            MG_INFO(("%.*s %.*s %.*s %.*s", (int)hm->method.len, hm->method.ptr,
+                (int)hm->uri.len, hm->uri.ptr, (int)tmp.uri.len, tmp.uri.ptr,
+                (int)cl->len, cl->ptr));
+        }
+    }
+    (void)fn_data;
+}
+
+static void* do_webserver_demo(void* none)
+{
+    p_netdev = netdev_get_by_name("wz");
+    if (p_netdev == NULL) {
+        MG_INFO(("Did nto find wz netdev, use default.\n"));
+        p_netdev = NETDEV_DEFAULT;
+    }
+    MG_INFO(("Use Netdev %s", p_netdev->name));
+    s_config.ip = strdup(inet_ntoa(*p_netdev->ip_addr));
+    s_config.mask = strdup(inet_ntoa(*p_netdev->netmask));
+    s_config.gw = strdup(inet_ntoa(*p_netdev->gw));
+    s_config.dns = strdup(inet_ntoa(p_netdev->dns_servers[0]));
+
+    struct mg_mgr mgr; // Event manager
+    // mg_log_set(MG_LL_INFO); // Set to 3 to enable debug
+    mg_log_set(MG_LL_DEBUG); // Set to 3 to enable debug
+    mg_mgr_init(&mgr); // Initialise event manager
+    mg_http_listen(&mgr, s_http_addr, fn, NULL); // Create HTTP listener
+    for (;;)
+        mg_mgr_poll(&mgr, 50); // Infinite event loop
+    mg_mgr_free(&mgr);
+    return NULL;
+}
+
+int webserver_demo(int argc, char* argv[])
+{
+    pthread_t tid = -1;
+    pthread_attr_t attr;
+    attr.schedparam.sched_priority = 30;
+    attr.stacksize = 0x2000;
+
+    PrivTaskCreate(&tid, &attr, do_webserver_demo, NULL);
+
+    return 0;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(5), Webserver, webserver_demo, webserver for project);

Ubiquitous/XiZi_IIoT/Makefile

@@ -50,6 +50,7 @@ export SRC_DIR:= $(SRC_APP_DIR) $(SRC_KERNEL_DIR)
 export LIBCC 
 export MUSL_DIR := $(KERNEL_ROOT)/lib/musllib
 export LWIP_DIR := $(KERNEL_ROOT)/resources/ethernet
+export MONGOOSE_DIR := $(KERNEL_ROOT)/../../APP_Framework/Applications/mongoose/lib
 
 PART:=
 
@@ -74,6 +75,10 @@ ifeq ($(CONFIG_RESOURCES_LWIP), y)
 PART += COMPILE_LWIP
 endif
 
+ifeq ($(CONFIG_USE_MONGOOSE), y)
+# PART += COMPILE_MONGOOSE
+endif
+
 ifeq ($(CONFIG_MCUBOOT_BOOTLOADER), y)
 PART += COMPILE_BOOTLOADER
 else ifeq ($(CONFIG_MCUBOOT_APPLICATION), y)
@@ -130,6 +135,15 @@ COMPILE_LWIP:
 	@cp build/liblwip.a $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
 	@rm build/Makefile build/make.obj
 
+COMPILE_MONGOOSE: 
+	@for dir in $(MONGOOSE_DIR);do    \
+               $(MAKE) -C $$dir COMPILE_TYPE=$@;          \
+       done
+	@cp link_mongoose.mk build/Makefile
+	@$(MAKE) -C build TARGET=mongoose.a LINK_FLAGS=LFLAGS
+	@cp build/mongoose.a $(KERNEL_ROOT)/../../APP_Framework/Applications/mongoose/mongoose.a
+	@rm build/Makefile build/make.obj
+
 COMPILE_KERNEL:
 	@for dir in $(SRC_KERNEL_DIR);do    \
                $(MAKE) -C $$dir;          \

Ubiquitous/XiZi_IIoT/board/edu-arm32/config.mk

@@ -1,10 +1,10 @@
 export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
 
-export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O0 -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror -Wuninitialized
+export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O2 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb 
 # export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
 export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
 export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-edu-arm32.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
-export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O0 -Werror
+export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O2 -Werror
 # export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
 
 export APPLFLAGS := 

Ubiquitous/XiZi_IIoT/board/edu-arm32/third_party_driver/ethernet/eth_driver.c

@@ -278,10 +278,7 @@ struct pbuf* low_level_input(struct netif* netif)
     return p;
 }
 
-extern void LwipSetIPTest(int argc, char* argv[]);
 int HwEthInit(void)
 {
-    // lwip_config_tcp(0, lwip_ipaddr, lwip_netmask, lwip_gwaddr);
-    LwipSetIPTest(1, NULL);
     return EOK;
 }

Ubiquitous/XiZi_IIoT/board/edu-arm32/third_party_driver/ethernet/eth_netdev.c

@@ -76,6 +76,7 @@ static int lwip_netdev_set_addr_info(struct netdev* netdev, ip_addr_t* ip_addr,
             netif_set_gw((struct netif*)netdev->user_data, ip_2_ip4(gw));
         }
     }
+    return 0;
 }
 
 #ifdef LWIP_DNS
@@ -92,7 +93,7 @@ static int lwip_netdev_set_dns_server(struct netdev* netdev, uint8_t dns_num, ip
 }
 #endif
 
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
 static int lwip_netdev_set_dhcp(struct netdev* netdev, bool is_enabled)
 {
     netdev_low_level_set_dhcp_status(netdev, is_enabled);
@@ -120,7 +121,7 @@ static const struct netdev_ops lwip_netdev_ops = {
 #ifdef LWIP_DNS
     .set_dns_server = lwip_netdev_set_dns_server,
 #endif
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
     .set_dhcp = lwip_netdev_set_dhcp,
 #endif
     .set_default = lwip_netdev_set_default,
@@ -179,9 +180,9 @@ int lwip_netdev_add(struct netif* lwip_netif)
     netdev->ops = &lwip_netdev_ops;
     netdev->hwaddr_len = lwip_netif->hwaddr_len;
     memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
-    netdev->ip_addr = lwip_netif->ip_addr;
+    netdev->ip_addr = &lwip_netif->ip_addr;
-    netdev->gw = lwip_netif->gw;
+    netdev->gw = &lwip_netif->gw;
-    netdev->netmask = lwip_netif->netmask;
+    netdev->netmask = &lwip_netif->netmask;
 
     return result;
 }

Ubiquitous/XiZi_IIoT/board/edu-riscv64/third_party_driver/ethernet/Makefile

@@ -1,4 +1,4 @@
 # SRC_FILES := socket.c connect_w5500.c w5500.c wizchip_conf.c spi_interface.c wiz_ping.c connect_w5500_test.c wiz_iperf.c
-SRC_FILES := socket.c connect_w5500.c w5500.c wizchip_conf.c spi_interface.c wiz_ping.c connect_w5500_test.c w5x00_lwip.c wiz_iperf.c
+SRC_FILES := socket.c connect_w5500.c w5500.c wizchip_conf.c spi_interface.c w5x00_lwip.c
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/edu-riscv64/third_party_driver/ethernet/connect_w5500.c

@@ -328,8 +328,12 @@ int HwWiznetInit(void)
     setSHAR(wiz_mac);
     ctlwizchip(CW_RESET_PHY, 0);
 
+    network_init();
+
     wiz_interrupt_init(0, wiz_irq_handler);
 
+    network_init();
+
     setSn_RXBUF_SIZE(0, 16);
     setSn_TXBUF_SIZE(0, 16);
 #define SOCK_ANY_PORT_NUM 0xC000
@@ -349,7 +353,5 @@ int HwWiznetInit(void)
         }
     }
 
-    network_init();
-
     return EOK;
 }

Ubiquitous/XiZi_IIoT/board/edu-riscv64/third_party_driver/spi/connect_spi.c

@@ -152,6 +152,9 @@ static uint32 SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info
 
 static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
 {
+#define WRITE_BUF_SIZE 1600
+    static uint32_t write_buf[4 * WRITE_BUF_SIZE] = { 0 };
+
     SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
 
     uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
@@ -184,10 +187,15 @@ static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStan
                 dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, &dummy, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
                             DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
             } else {
-                tx_buff = x_malloc(spi_datacfg->length * 4);
+                if (spi_datacfg->length > WRITE_BUF_SIZE) {
-                if (!tx_buff) {
+                    tx_buff = x_malloc(spi_datacfg->length * 4);
-                    goto transfer_done;
+                    if (!tx_buff) {
+                        goto transfer_done;
+                    }
+                } else {
+                    tx_buff = write_buf;
                 }
+
                 for (i = 0; i < spi_datacfg->length; i++) {
                     tx_buff[i] = ((uint8_t *)spi_datacfg->tx_buff)[i];
                 }
@@ -201,10 +209,10 @@ static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStan
             spi_instance[device_master_id]->ser = 0x00;
             spi_instance[device_master_id]->ssienr = 0x00;
 
-    transfer_done:
+        transfer_done:
-        if (tx_buff != NULL) {
+            if (tx_buff != NULL && spi_datacfg->length > WRITE_BUF_SIZE) {
-            x_free(tx_buff);
+                x_free(tx_buff);
-        }
+            }
         }
 
         if (spi_datacfg->spi_cs_release) {
@@ -219,6 +227,9 @@ static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStan
 
 static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
 {
+#define READ_BUF_SIZE 1600
+    static uint32_t read_buf[4 * READ_BUF_SIZE] = { 0 };
+
     SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
 
     uint32 spi_read_length = 0;;
@@ -251,12 +262,15 @@ static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStand
                 dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), &dummy, DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
                             DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
             } else {
-                rx_buff = x_calloc(spi_datacfg->length * 4, 1);
+                if (spi_datacfg->length > READ_BUF_SIZE) {
-                if(!rx_buff)
+                    rx_buff = x_calloc(spi_datacfg->length * 4, 1);
-                {
+                    if (!rx_buff) {
-                    goto transfer_done;
+                        goto transfer_done;
+                    }
+                } else {
+                    rx_buff = read_buf;
                 }
-                
+
                 dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
                             DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
             }
@@ -273,8 +287,8 @@ static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStand
                 }
             }
 
-    transfer_done:
+        transfer_done:
-            if (rx_buff) {
+            if (rx_buff && spi_datacfg->length > READ_BUF_SIZE) {
                 x_free(rx_buff);
             }
         }

Ubiquitous/XiZi_IIoT/board/imxrt1176-sbc/third_party_driver/ethernet/eth_netdev.c

@@ -76,6 +76,7 @@ static int lwip_netdev_set_addr_info(struct netdev* netdev, ip_addr_t* ip_addr,
             netif_set_gw((struct netif*)netdev->user_data, ip_2_ip4(gw));
         }
     }
+    return 0;
 }
 
 #ifdef LWIP_DNS
@@ -92,7 +93,7 @@ static int lwip_netdev_set_dns_server(struct netdev* netdev, uint8_t dns_num, ip
 }
 #endif
 
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
 static int lwip_netdev_set_dhcp(struct netdev* netdev, bool is_enabled)
 {
     netdev_low_level_set_dhcp_status(netdev, is_enabled);
@@ -120,7 +121,7 @@ static const struct netdev_ops lwip_netdev_ops = {
 #ifdef LWIP_DNS
     .set_dns_server = lwip_netdev_set_dns_server,
 #endif
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
     .set_dhcp = lwip_netdev_set_dhcp,
 #endif
     .set_default = lwip_netdev_set_default,
@@ -180,9 +181,9 @@ int lwip_netdev_add(struct netif* lwip_netif)
     netdev->ops = &lwip_netdev_ops;
     netdev->hwaddr_len = lwip_netif->hwaddr_len;
     memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
-    netdev->ip_addr = lwip_netif->ip_addr;
+    netdev->ip_addr = &lwip_netif->ip_addr;
-    netdev->gw = lwip_netif->gw;
+    netdev->gw = &lwip_netif->gw;
-    netdev->netmask = lwip_netif->netmask;
+    netdev->netmask = &lwip_netif->netmask;
 
     return result;
 }

Ubiquitous/XiZi_IIoT/board/ok1052-c/third_party_driver/ethernet/eth_netdev.c

@@ -76,6 +76,7 @@ static int lwip_netdev_set_addr_info(struct netdev* netdev, ip_addr_t* ip_addr,
             netif_set_gw((struct netif*)netdev->user_data, ip_2_ip4(gw));
         }
     }
+    return 0;
 }
 
 #ifdef LWIP_DNS
@@ -92,7 +93,7 @@ static int lwip_netdev_set_dns_server(struct netdev* netdev, uint8_t dns_num, ip
 }
 #endif
 
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
 static int lwip_netdev_set_dhcp(struct netdev* netdev, bool is_enabled)
 {
     netdev_low_level_set_dhcp_status(netdev, is_enabled);
@@ -120,7 +121,7 @@ static const struct netdev_ops lwip_netdev_ops = {
 #ifdef LWIP_DNS
     .set_dns_server = lwip_netdev_set_dns_server,
 #endif
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
     .set_dhcp = lwip_netdev_set_dhcp,
 #endif
     .set_default = lwip_netdev_set_default,
@@ -180,9 +181,9 @@ int lwip_netdev_add(struct netif* lwip_netif)
     netdev->ops = &lwip_netdev_ops;
     netdev->hwaddr_len = lwip_netif->hwaddr_len;
     memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
-    netdev->ip_addr = lwip_netif->ip_addr;
+    netdev->ip_addr = &lwip_netif->ip_addr;
-    netdev->gw = lwip_netif->gw;
+    netdev->gw = &lwip_netif->gw;
-    netdev->netmask = lwip_netif->netmask;
+    netdev->netmask = &lwip_netif->netmask;
 
     return result;
 }

Ubiquitous/XiZi_IIoT/board/xidatong-arm32/config.mk

@@ -30,7 +30,7 @@ export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -
 export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
 
 
-export DEFINES := -DHAVE_CCONFIG_H  -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS
+export DEFINES := -DHAVE_CCONFIG_H  -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS -DCHECKSUM_BY_HARDWARE
 
 ifeq ($(CONFIG_MCUBOOT_BOOTLOADER),y)
 export DEFINES += -D__BOOTLOADER

Ubiquitous/XiZi_IIoT/board/xidatong-arm32/third_party_driver/ethernet/eth_netdev.c

@@ -76,6 +76,7 @@ static int lwip_netdev_set_addr_info(struct netdev* netdev, ip_addr_t* ip_addr,
             netif_set_gw((struct netif*)netdev->user_data, ip_2_ip4(gw));
         }
     }
+    return 0;
 }
 
 #ifdef LWIP_DNS
@@ -92,7 +93,7 @@ static int lwip_netdev_set_dns_server(struct netdev* netdev, uint8_t dns_num, ip
 }
 #endif
 
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
 static int lwip_netdev_set_dhcp(struct netdev* netdev, bool is_enabled)
 {
     netdev_low_level_set_dhcp_status(netdev, is_enabled);
@@ -120,7 +121,7 @@ static const struct netdev_ops lwip_netdev_ops = {
 #ifdef LWIP_DNS
     .set_dns_server = lwip_netdev_set_dns_server,
 #endif
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
     .set_dhcp = lwip_netdev_set_dhcp,
 #endif
     .set_default = lwip_netdev_set_default,
@@ -180,9 +181,9 @@ int lwip_netdev_add(struct netif* lwip_netif)
     netdev->ops = &lwip_netdev_ops;
     netdev->hwaddr_len = lwip_netif->hwaddr_len;
     memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
-    netdev->ip_addr = lwip_netif->ip_addr;
+    netdev->ip_addr = &lwip_netif->ip_addr;
-    netdev->gw = lwip_netif->gw;
+    netdev->gw = &lwip_netif->gw;
-    netdev->netmask = lwip_netif->netmask;
+    netdev->netmask = &lwip_netif->netmask;
 
     return result;
 }

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/.defconfig

@@ -0,0 +1,261 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# XiZi_IIoT Project Configuration
+#
+CONFIG_BOARD_EDU_ARM32_EVB=y
+CONFIG_ARCH_ARM=y
+
+#
+# hc32f4a0 feature
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART3=y
+CONFIG_SERIAL_BUS_NAME_3="usart3"
+CONFIG_SERIAL_DRV_NAME_3="usart3_drv"
+CONFIG_SERIAL_3_DEVICE_NAME_0="usart3_dev3"
+CONFIG_BSP_USING_UART6=y
+CONFIG_SERIAL_BUS_NAME_6="usart6"
+CONFIG_SERIAL_DRV_NAME_6="usart6_drv"
+CONFIG_SERIAL_6_DEVICE_NAME_0="usart6_dev6"
+
+#
+# config default board resources
+#
+
+#
+# config board app name
+#
+CONFIG_BOARD_APP_NAME="/XiUOS_edu_arm32_app.bin"
+
+#
+# Hardware feature
+#
+CONFIG_RESOURCES_SERIAL=y
+CONFIG_SERIAL_USING_DMA=y
+CONFIG_SERIAL_RB_BUFSZ=128
+
+#
+# Kernel feature
+#
+
+#
+# separate compile(choose none for compile once)
+#
+# CONFIG_SEPARATE_COMPILE is not set
+# CONFIG_COMPILER_APP is not set
+# CONFIG_APP_STARTUP_FROM_SDCARD is not set
+CONFIG_APP_STARTUP_FROM_FLASH=y
+# CONFIG_COMPILER_KERNEL is not set
+
+#
+# Memory Management
+#
+# CONFIG_KERNEL_MEMBLOCK is not set
+CONFIG_MEM_ALIGN_SIZE=8
+# CONFIG_MEM_EXTERN_SRAM is not set
+CONFIG_MM_PAGE_SIZE=4096
+
+#
+# Using small memory allocator
+#
+CONFIG_KERNEL_SMALL_MEM_ALLOC=y
+CONFIG_SMALL_NUMBER_32B=64
+CONFIG_SMALL_NUMBER_64B=32
+
+#
+# Task feature
+#
+CONFIG_USER_APPLICATION=y
+# CONFIG_TASK_ISOLATION is not set
+
+#
+# Inter-Task communication
+#
+CONFIG_KERNEL_SEMAPHORE=y
+CONFIG_KERNEL_MUTEX=y
+CONFIG_KERNEL_EVENT=y
+CONFIG_KERNEL_MESSAGEQUEUE=y
+CONFIG_KERNEL_SOFTTIMER=y
+CONFIG_SCHED_POLICY_RR_REMAINSLICE=y
+# CONFIG_SCHED_POLICY_RR is not set
+# CONFIG_SCHED_POLICY_FIFO is not set
+# CONFIG_KTASK_PRIORITY_8 is not set
+CONFIG_KTASK_PRIORITY_32=y
+# CONFIG_KTASK_PRIORITY_256 is not set
+CONFIG_KTASK_PRIORITY_MAX=32
+CONFIG_TICK_PER_SECOND=1000
+CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y
+CONFIG_IDLE_KTASK_STACKSIZE=1024
+CONFIG_ZOMBIE_KTASK_STACKSIZE=2048
+
+#
+# Kernel Console
+#
+CONFIG_KERNEL_CONSOLE=y
+CONFIG_KERNEL_BANNER=y
+CONFIG_KERNEL_CONSOLEBUF_SIZE=128
+
+#
+# Kernel Hook
+#
+# CONFIG_KERNEL_HOOK is not set
+
+#
+# Command shell
+#
+CONFIG_TOOL_SHELL=y
+CONFIG_SHELL_ENTER_CR=y
+CONFIG_SHELL_ENTER_LF=y
+CONFIG_SHELL_ENTER_CR_AND_LF=y
+# CONFIG_SHELL_ENTER_CRLF is not set
+
+#
+# Set shell user control
+#
+CONFIG_SHELL_DEFAULT_USER="letter"
+CONFIG_SHELL_DEFAULT_USER_PASSWORD=""
+CONFIG_SHELL_LOCK_TIMEOUT=10000
+
+#
+# Set shell config param
+#
+CONFIG_SHELL_TASK_STACK_SIZE=4096
+CONFIG_SHELL_TASK_PRIORITY=20
+CONFIG_SHELL_MAX_NUMBER=5
+CONFIG_SHELL_PARAMETER_MAX_NUMBER=8
+CONFIG_SHELL_HISTORY_MAX_NUMBER=5
+CONFIG_SHELL_PRINT_BUFFER=128
+CONFIG_SHELL_HELP_SHOW_PERMISSION=y
+# CONFIG_SHELL_HELP_LIST_USER is not set
+CONFIG_SHELL_HELP_LIST_VAR=y
+# CONFIG_SHELL_HELP_LIST_KEY is not set
+
+#
+# Kernel data structure Manage
+#
+CONFIG_KERNEL_QUEUEMANAGE=y
+CONFIG_KERNEL_WORKQUEUE=y
+CONFIG_WORKQUEUE_KTASK_STACKSIZE=2048
+CONFIG_WORKQUEUE_KTASK_PRIORITY=23
+CONFIG_QUEUE_MAX=16
+CONFIG_KERNEL_WAITQUEUE=y
+CONFIG_KERNEL_DATAQUEUE=y
+# CONFIG_KERNEL_CIRCULAR_AREA is not set
+# CONFIG_KERNEL_AVL_TREE is not set
+
+#
+# Kernel components init
+#
+CONFIG_KERNEL_COMPONENTS_INIT=y
+CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048
+CONFIG_KERNEL_USER_MAIN=y
+CONFIG_NAME_NUM_MAX=32
+# CONFIG_KERNEL_DEBUG is not set
+# CONFIG_ARCH_SMP is not set
+
+#
+# hash table config
+#
+CONFIG_ID_HTABLE_SIZE=16
+CONFIG_ID_NUM_MAX=128
+# CONFIG_KERNEL_TEST is not set
+
+#
+# Lib
+#
+CONFIG_LIB=y
+CONFIG_LIB_POSIX=y
+CONFIG_LIB_NEWLIB=y
+# CONFIG_LIB_MUSLLIB is not set
+
+#
+# C++ features
+#
+# CONFIG_LIB_CPLUSPLUS is not set
+
+#
+# File system
+#
+CONFIG_FS_VFS=y
+CONFIG_VFS_USING_WORKDIR=y
+CONFIG_FS_VFS_DEVFS=y
+CONFIG_FS_VFS_FATFS=y
+# CONFIG_FS_CH376 is not set
+# CONFIG_FS_LWEXT4 is not set
+
+#
+# APP_Framework
+#
+
+#
+# Framework
+#
+CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
+CONFIG_ADD_XIZI_FEATURES=y
+# CONFIG_ADD_NUTTX_FEATURES is not set
+# CONFIG_ADD_RTTHREAD_FEATURES is not set
+# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
+# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
+# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
+# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
+
+#
+# Security
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Applications
+#
+
+#
+# config stack size and priority of main task
+#
+CONFIG_MAIN_KTASK_STACK_SIZE=1024
+CONFIG_MAIN_KTASK_PRIORITY=16
+
+#
+# ota app 
+#
+# CONFIG_APPLICATION_OTA is not set
+
+#
+# test app
+#
+# CONFIG_USER_TEST is not set
+
+#
+# connection app
+#
+# CONFIG_APPLICATION_CONNECTION is not set
+
+#
+# control app
+#
+
+#
+# knowing app
+#
+# CONFIG_APPLICATION_KNOWING is not set
+
+#
+# sensor app
+#
+# CONFIG_APPLICATION_SENSOR is not set
+# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
+# CONFIG_APP_USING_WEBNET is not set
+
+#
+# lib
+#
+CONFIG_APP_SELECT_NEWLIB=y
+# CONFIG_APP_SELECT_OTHER_LIB is not set
+# CONFIG_LIB_USING_CJSON is not set
+# CONFIG_LIB_USING_QUEUE is not set
+# CONFIG_LIB_LV is not set
+
+#
+# LVGL configuration
+#
+# CONFIG_LV_CONF_MINIMAL is not set
+# CONFIG_USING_EMBEDDED_DATABASE is not set

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/config.mk

@@ -15,4 +15,8 @@ ifeq ($(CONFIG_RESOURCES_LWIP), y)
 export LINK_LWIP := $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
 endif
 
+ifeq ($(CONFIG_USE_MONGOOSE), y)
+export LINK_MONGOOSE := $(KERNEL_ROOT)/../../APP_Framework/Applications/mongoose/mongoose.a
+endif
+
 export ARCH = arm

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/adc/Kconfig

@@ -0,0 +1,13 @@
+if BSP_USING_ADC
+    config ADC1_BUS_NAME
+        string "adc 1 bus name"
+        default "adc1"
+
+    config ADC1_DRIVER_NAME
+        string "adc 1 driver name"
+        default "adc1_drv"
+
+    config ADC1_DEVICE_NAME
+        string "adc 1 bus device name"
+        default "adc1_dev"
+endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/adc/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_adc.c 
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/adc/connect_adc.c

@@ -0,0 +1,370 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_adc.c
+* @brief support to register ADC pointer and function
+* @version 1.1
+* @author AIIT XUOS Lab
+* @date 2023-02-09
+*/
+
+#include <connect_adc.h>
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/* The clock source of ADC. */
+#define ADC_CLK_SYS_CLK                 (1U)
+#define ADC_CLK_PLLH                    (2U)
+#define ADC_CLK_PLLA                    (3U)
+
+/*
+ * Selects a clock source according to the application requirements.
+ * PCLK4 is the clock for digital interface.
+ * PCLK2 is the clock for analog circuit.
+ * PCLK4 and PCLK2 are synchronous when the clock source is PLL.
+ * PCLK4 : PCLK2 = 1:1, 2:1, 4:1, 8:1, 1:2, 1:4.
+ * PCLK2 is in range [1MHz, 60MHz].
+ * If the system clock is selected as the ADC clock, macro 'ADC_ADC_CLK' can only be defined as 'CLK_PERIPHCLK_PCLK'.
+ * If PLLH is selected as the ADC clock, macro 'ADC_ADC_CLK' can be defined as 'CLK_PERIPHCLK_PLLx'(x=Q, R).
+ * If PLLA is selected as the ADC clock, macro 'ADC_ADC_CLK' can be defined as 'CLK_PERIPHCLK_PLLXx'(x=P, Q, R).
+ */
+#define ADC_CLK_SEL                     (ADC_CLK_SYS_CLK)
+
+#if (ADC_CLK_SEL == ADC_CLK_SYS_CLK)
+#define ADC_CLK                         (CLK_PERIPHCLK_PCLK)
+
+#elif (ADC_CLK_SEL == ADC_CLK_PLLH)
+#define ADC_CLK                         (CLK_PERIPHCLK_PLLQ)
+
+#elif (ADC_CLK_SEL == ADC_CLK_PLLA)
+#define ADC_CLK                         (CLK_PERIPHCLK_PLLXP)
+
+#else
+#error "The clock source your selected does not exist!!!"
+#endif
+
+/* ADC unit instance for this example. */
+#define ADC_UNIT                        (CM_ADC1)
+#define ADC_PERIPH_CLK                  (FCG3_PERIPH_ADC1)
+
+/* Selects ADC channels that needed. */
+#define ADC_CH_POTENTIOMETER            (ADC_CH3)
+#define ADC_CH                          (ADC_CH_POTENTIOMETER)
+#define ADC_CH_PORT                     (GPIO_PORT_A)
+#define ADC_CH_PIN                      (GPIO_PIN_03)
+
+/* ADC sequence to be used. */
+#define ADC_SEQ                         (ADC_SEQ_A)
+/* Flag of conversion end. */
+#define ADC_EOC_FLAG                    (ADC_FLAG_EOCA)
+
+/* ADC reference voltage. The voltage of pin VREFH. */
+#define ADC_VREF                        (3.3F)
+
+/* ADC accuracy(according to the resolution of ADC). */
+#define ADC_ACCURACY                    (1UL << 12U)
+
+/* Calculate the voltage(mV). */
+#define ADC_CAL_VOL(adcVal)             (uint16_t)((((float32_t)(adcVal) * ADC_VREF) / ((float32_t)ADC_ACCURACY)) * 1000.F)
+
+/* Timeout value. */
+#define ADC_TIMEOUT_VAL                 (1000U)
+
+/**
+ * @brief  Set specified ADC pin to analog mode.
+ * @param  None
+ * @retval None
+ */
+static void AdcSetPinAnalogMode(void)
+{
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    (void)GPIO_Init(ADC_CH_PORT, ADC_CH_PIN, &stcGpioInit);
+}
+
+/**
+ * @brief  Configures ADC clock.
+ * @param  None
+ * @retval None
+ */
+static void AdcClockConfig(void)
+{
+#if (ADC_CLK_SEL == ADC_CLK_SYS_CLK)
+    /*
+     * 1. Configures the clock divider of PCLK2 and PCLK4 here or in the function of configuring the system clock.
+     *    In this example, the system clock is MRC@8MHz.
+     *    PCLK4 is the digital interface clock, and PCLK2 is the analog circuit clock.
+     *    Make sure that PCLK2 and PCLK4 meet the following conditions:
+     *      PCLK4 : PCLK2 = 1:1, 2:1, 4:1, 8:1, 1:2, 1:4.
+     *      PCLK2 is in range [1MHz, 60MHz].
+     */
+    CLK_SetClockDiv((CLK_BUS_PCLK2 | CLK_BUS_PCLK4), (CLK_PCLK2_DIV8 | CLK_PCLK4_DIV2));
+
+#elif (ADC_CLK_SEL == ADC_CLK_PLLH)
+    /*
+     * 1. Configures PLLH and the divider of PLLHx(x=Q, R).
+     *    PLLHx(x=Q, R) is used as both the digital interface clock and the analog circuit clock.
+     *    PLLHx(x=Q, R) must be in range [1MHz, 60MHz] for ADC use.
+     *    The input source of PLLH is XTAL(8MHz).
+     */
+    stc_clock_pll_init_t stcPLLHInit;
+    stc_clock_xtal_init_t stcXtalInit;
+
+    /* Configures XTAL. PLLH input source is XTAL. */
+    (void)CLK_XtalStructInit(&stcXtalInit);
+    stcXtalInit.u8State      = CLK_XTAL_ON;
+    stcXtalInit.u8Drv        = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8Mode       = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8StableTime = CLK_XTAL_STB_499US;
+    (void)CLK_XtalInit(&stcXtalInit);
+
+    (void)CLK_PLLStructInit(&stcPLLHInit);
+    /*
+     * PLLHx(x=Q, R) = ((PLL_source / PLLM) * PLLN) / PLLx
+     * PLLHQ = (8 / 1) * 80 /16 = 40MHz
+     * PLLHR = (8 / 1) * 80 /16 = 40MHz
+     */
+    stcPLLHInit.u8PLLState = CLK_PLL_ON;
+    stcPLLHInit.PLLCFGR = 0UL;
+    stcPLLHInit.PLLCFGR_f.PLLM = (1UL  - 1UL);
+    stcPLLHInit.PLLCFGR_f.PLLN = (80UL - 1UL);
+    stcPLLHInit.PLLCFGR_f.PLLP = (4UL  - 1UL);
+    stcPLLHInit.PLLCFGR_f.PLLQ = (16UL - 1UL);
+    stcPLLHInit.PLLCFGR_f.PLLR = (16UL - 1UL);
+    /* stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; */
+    (void)CLK_PLLInit(&stcPLLHInit);
+
+#elif (ADC_CLK_SEL == ADC_CLK_PLLA)
+    /*
+     * 1. Configures PLLA and the divider of PLLAx(x=P, Q, R).
+     *    PLLAx(x=P, Q, R) is used as both the digital interface clock and the analog circuit clock.
+     *    PLLAx(x=P, Q, R) must be in range [1MHz, 60MHz] for ADC use.
+     *    The input source of PLLA is HRC(16MHz).
+     */
+    stc_clock_pllx_init_t stcPLLAInit;
+
+    /* Enable HRC(16MHz) for PLLA. */
+    CLK_HrcCmd(ENABLE);
+
+    /* Specify the input source of PLLA. NOTE!!! PLLA and PLLH use the same input source. */
+    CLK_SetPLLSrc(CLK_PLL_SRC_HRC);
+    /* PLLA configuration */
+    (void)CLK_PLLxStructInit(&stcPLLAInit);
+    /*
+     * PLLAx(x=P, Q, R) = ((PLL_source / PLLM) * PLLN) / PLLx
+     * PLLAP = (16 / 2) * 40 / 8  = 40MHz
+     * PLLAQ = (16 / 2) * 40 / 10 = 32MHz
+     * PLLAR = (16 / 2) * 40 / 16 = 20MHz
+     */
+    stcPLLAInit.u8PLLState = CLK_PLLX_ON;
+    stcPLLAInit.PLLCFGR = 0UL;
+    stcPLLAInit.PLLCFGR_f.PLLM = (2UL  - 1UL);
+    stcPLLAInit.PLLCFGR_f.PLLN = (40UL - 1UL);
+    stcPLLAInit.PLLCFGR_f.PLLR = (8UL  - 1UL);
+    stcPLLAInit.PLLCFGR_f.PLLQ = (10UL - 1UL);
+    stcPLLAInit.PLLCFGR_f.PLLP = (16UL - 1UL);
+    (void)CLK_PLLxInit(&stcPLLAInit);
+#endif
+    /* 2. Specifies the clock source of ADC. */
+    CLK_SetPeriClockSrc(ADC_CLK);
+}
+
+/**
+ * @brief  Initializes ADC.
+ * @param  None
+ * @retval None
+ */
+static void AdcInitConfig(void)
+{
+    stc_adc_init_t stcAdcInit;
+
+    /* 1. Enable ADC peripheral clock. */
+    FCG_Fcg3PeriphClockCmd(ADC_PERIPH_CLK, ENABLE);
+
+    /* 2. Modify the default value depends on the application. Not needed here. */
+    (void)ADC_StructInit(&stcAdcInit);
+
+    /* 3. Initializes ADC. */
+    (void)ADC_Init(ADC_UNIT, &stcAdcInit);
+
+    /* 4. ADC channel configuration. */
+    /* 4.1 Set the ADC pin to analog input mode. */
+    AdcSetPinAnalogMode();
+    /* 4.2 Enable ADC channels. Call ADC_ChCmd() again to enable more channels if needed. */
+    ADC_ChCmd(ADC_UNIT, ADC_SEQ, ADC_CH, ENABLE);
+
+    /* 5. Conversion data average calculation function, if needed.
+          Call ADC_ConvDataAverageChCmd() again to enable more average channels if needed. */
+    ADC_ConvDataAverageConfig(ADC_UNIT, ADC_AVG_CNT8);
+    ADC_ConvDataAverageChCmd(ADC_UNIT, ADC_CH, ENABLE);
+}
+
+/**
+ * @brief  Use ADC in polling mode.
+ * @param  None
+ * @retval uint16_t u16AdcValue
+ */
+static uint16_t AdcPolling(void)
+{
+    uint16_t u16AdcValue = 0;
+    int32_t iRet = LL_ERR;
+    __IO uint32_t u32TimeCount = 0UL;
+
+    /* Can ONLY start sequence A conversion.
+       Sequence B needs hardware trigger to start conversion. */
+    ADC_Start(ADC_UNIT);
+    do {
+        if (ADC_GetStatus(ADC_UNIT, ADC_EOC_FLAG) == SET) {
+            ADC_ClearStatus(ADC_UNIT, ADC_EOC_FLAG);
+            iRet = LL_OK;
+            break;
+        }
+    } while (u32TimeCount++ < ADC_TIMEOUT_VAL);
+
+    if (iRet == LL_OK) {
+        /* Get any ADC value of sequence A channel that needed. */
+        u16AdcValue = ADC_GetValue(ADC_UNIT, ADC_CH);
+        KPrintf("The ADC value of potentiometer is %u, voltage is %u mV\r\n",
+            u16AdcValue, ADC_CAL_VOL(u16AdcValue));
+    } else {
+        ADC_Stop(ADC_UNIT);
+        KPrintf("ADC exception.\r\n");
+    }
+
+    return ADC_CAL_VOL(u16AdcValue);
+}
+
+static uint32 AdcOpen(void *dev)
+{
+    x_err_t ret = EOK;
+    struct AdcHardwareDevice* adc_dev = (struct AdcHardwareDevice*)dev;
+
+    AdcClockConfig();
+    AdcInitConfig();
+
+    return ret;
+}
+
+static uint32 AdcClose(void *dev)
+{
+    struct AdcHardwareDevice* adc_dev = (struct AdcHardwareDevice*)dev;
+    CM_ADC_TypeDef *ADCx= (CM_ADC_TypeDef *)adc_dev->private_data;
+
+    ADC_Stop(ADC_UNIT);
+    ADC_DeInit(ADCx);
+    
+    return EOK;
+}
+
+static uint32 AdcRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    *(uint16 *)read_param->buffer = AdcPolling();
+    read_param->read_length = 2;
+
+   return EOK;
+}
+
+static uint32 AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    uint8 adc_channel;
+
+    struct AdcDriver *adc_drv = (struct AdcDriver *)drv;
+    struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev;
+    struct HwAdc *adc_cfg = (struct HwAdc *)adc_dev->haldev.private_data;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_CFG:
+            adc_cfg->adc_channel = *(uint8 *)configure_info->private_data;
+            if (adc_cfg->adc_channel != 1) {
+                KPrintf("AdcDrvConfigure set adc channel(1) %u error!", adc_cfg->adc_channel);
+                adc_cfg->adc_channel = 1;
+                ret = ERROR;
+            }
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct AdcDevDone dev_done =
+{
+    AdcOpen,
+    AdcClose,
+    NONE,
+    AdcRead,
+};
+
+int HwAdcInit(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_ADC
+    static struct AdcBus adc1_bus;
+    static struct AdcDriver adc1_drv;
+    static struct AdcHardwareDevice adc1_dev;
+    static struct HwAdc adc1_cfg;
+
+    adc1_drv.configure = AdcDrvConfigure;
+
+    ret = AdcBusInit(&adc1_bus, ADC1_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = AdcDriverInit(&adc1_drv, ADC1_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDriverAttachToBus(ADC1_DRIVER_NAME, ADC1_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    adc1_dev.adc_dev_done = &dev_done;
+    adc1_cfg.ADCx = CM_ADC1;
+    adc1_cfg.adc_channel = 1;
+
+    ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC1_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 device register error %d\n", ret);
+        return ERROR;
+    }
+#endif 
+
+    return ret;
+
+}
+
+
+
+
+

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/can/Kconfig

@@ -0,0 +1,15 @@
+config CAN_BUS_NAME_2
+    string "can bus name"
+    default "can2"
+
+config CAN_DRIVER_NAME_2
+    string "can driver name"
+    default "can2_drv"
+
+config CAN_2_DEVICE_NAME_1
+    string "can bus 1 device 1 name"
+    default "can2_dev1"
+
+config CAN_USING_INTERRUPT
+    bool "can interrupt open"
+    default n

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/can/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_can.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/can/connect_can.c

@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) Guangzhou Xingyi Electronic  Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date               Author       Notes
+ * 2014-7-4      alientek   first version
+ */
+
+/**
+* @file connect_can.c
+* @brief support hc32f4a0 can function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2023-02-20
+*/
+
+/*************************************************
+File name: connect_can.c
+Description: support can configure and spi bus register function for hc32f4a0
+Others: connect_can.c for references
+*************************************************/
+
+#include "connect_can.h"
+
+#define CAN_X (CM_CAN2)
+
+#define CAN_TX_PORT (GPIO_PORT_D)
+#define CAN_TX_PIN  (GPIO_PIN_07)
+#define CAN_RX_PORT (GPIO_PORT_D)
+#define CAN_RX_PIN  (GPIO_PIN_06)
+#define CAN_TX_PIN_FUNC (GPIO_FUNC_62)
+#define CAN_RX_PIN_FUNC (GPIO_FUNC_63)
+
+#define INTSEL_REG              ((uint32_t)(&CM_INTC->SEL0))
+#define CANX_IRQ_SRC            INT_SRC_CAN2_HOST
+#define CANX_IRQ_NUM               17
+#define IRQ_NUM_OFFSET             16
+
+#define CAN_AF1_ID (0x123UL)
+#define CAN_AF1_ID_MSK (0xFFFUL)
+#define CAN_AF1_MSK_TYPE CAN_ID_STD
+#define CAN_AF2_ID (0x005UL)
+#define CAN_AF2_ID_MSK (0x00FUL)
+#define CAN_AF2_MSK_TYPE CAN_ID_STD
+#define CAN_AF3_ID (0x23UL)
+#define CAN_AF3_ID_MSK (0xFFUL)
+#define CAN_AF3_MSK_TYPE CAN_ID_STD
+
+#ifdef CAN_USING_INTERRUPT
+void CanIrqHandler(int vector, void *param)
+{
+    stc_can_error_info_t err_info;
+    uint32_t status = CAN_GetStatusValue(CAN_X);
+    uint32_t error = CAN_GetErrorInfo(CAN_X,&err_info);
+    
+    KPrintf("Irq entered\n");    
+
+    CAN_ClearStatus(CAN_X, status);
+}
+
+static void CanIrqConfig(void)
+{
+    // register IRQ src in IRQn
+    __IO uint32_t *INTC_SELx = (__IO uint32_t *)(INTSEL_REG+ 4U * (uint32_t)(CANX_IRQ_NUM));
+    WRITE_REG32(*INTC_SELx, CANX_IRQ_SRC);
+    isrManager.done->registerIrq(CANX_IRQ_NUM+IRQ_NUM_OFFSET,CanIrqHandler,NULL);
+    isrManager.done->enableIrq(CANX_IRQ_NUM);
+}
+#endif
+
+static void CanInit(struct CanDriverConfigure *can_drv_config)
+{
+    stc_can_init_t stcInit;
+    stc_can_filter_config_t astcAFCfg[] = { \
+        {CAN_AF1_ID, CAN_AF1_ID_MSK, CAN_AF1_MSK_TYPE}, \
+        {CAN_AF2_ID, CAN_AF2_ID_MSK, CAN_AF2_MSK_TYPE}, \
+        {CAN_AF3_ID, CAN_AF3_ID_MSK, CAN_AF3_MSK_TYPE}, \
+    };
+
+    CLK_SetCANClockSrc(CLK_CAN2,CLK_CANCLK_SYSCLK_DIV4);
+
+    /* Set the function of CAN pins. */
+    GPIO_SetFunc(CAN_TX_PORT, CAN_TX_PIN, CAN_TX_PIN_FUNC);
+    GPIO_SetFunc(CAN_RX_PORT, CAN_RX_PIN, CAN_RX_PIN_FUNC);
+
+    /* Initializes CAN. */
+    (void)CAN_StructInit(&stcInit);
+    stcInit.pstcFilter = astcAFCfg;
+    stcInit.u16FilterSelect  = (CAN_FILTER1 | CAN_FILTER2 | CAN_FILTER3);
+
+    // Driver's config
+    stcInit.stcBitCfg.u32SJW = can_drv_config->tsjw;    
+    stcInit.stcBitCfg.u32Prescaler = can_drv_config->brp;
+    stcInit.stcBitCfg.u32TimeSeg1 = can_drv_config->tbs1;
+    stcInit.stcBitCfg.u32TimeSeg2 = can_drv_config->tbs2;
+    stcInit.u8WorkMode = can_drv_config->mode;
+
+#ifdef CAN_USING_FD
+    stcInit.stcFDCfg.u8TDCSSP = 16U;
+    stcInit.stcFDCfg.u8CANFDMode = CAN_FD_MODE_ISO_11898;
+    stcInit.stcFDCfg.stcFBT.u32SEG1 = 16U;
+    stcInit.stcFDCfg.stcFBT.u32SEG2 = 4U;
+    stcInit.stcFDCfg.stcFBT.u32SJW  = 4U;
+    stcInit.stcFDCfg.stcFBT.u32Prescaler = 1U;
+    (void)CAN_FD_Init(APP_CAN_UNIT, &stcInit);
+#else
+    FCG_Fcg1PeriphClockCmd(PWC_FCG1_CAN2, ENABLE);
+    (void)CAN_Init(CAN_X, &stcInit);
+#endif
+    CAN_ClearStatus(CAN_X, 0xFFFFFFFFU);
+
+#ifdef CAN_USING_INTERRUPT
+    /* Configures the interrupts if needed. */
+    CAN_IntCmd(CAN_X, CAN_INT_RX, ENABLE);
+    CanIrqConfig();
+#endif    
+}
+
+static uint32 CanConfig(void *can_drv_config)
+{
+    x_err_t ret = EOK;
+    return ret;        
+}
+
+static uint32 CanDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    x_err_t ret = EOK;
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+    struct CanDriverConfigure *can_drv_config;
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT: // can basic init
+            can_drv_config = (struct CanDriverConfigure *)configure_info->private_data;
+            CanInit(can_drv_config);
+            break;
+        case OPE_CFG: 
+            CanConfig(configure_info->private_data);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+
+static uint32 CanWriteData(void * dev , struct BusBlockWriteParam *write_param)
+{
+    x_err_t ret=EOK;
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(write_param);
+    struct CanSendConfigure *p_can_config = (struct CanSendConfigure*)write_param->buffer;
+    stc_can_tx_frame_t can_frame_obj;
+    memset(&can_frame_obj,0,sizeof(stc_can_tx_frame_t));
+
+    // configure CAN's flag bit
+    can_frame_obj.IDE = p_can_config->ide;
+    if(1==p_can_config->ide){
+        can_frame_obj.u32ID = p_can_config->exdid;
+    }else{
+        can_frame_obj.u32ID = p_can_config->stdid;
+    } 
+    can_frame_obj.RTR = p_can_config->rtr;
+    
+    memcpy(can_frame_obj.au8Data,p_can_config->data,p_can_config->data_lenth);
+    can_frame_obj.DLC = p_can_config->data_lenth;
+
+    //put frame_buffer in message queue    
+    if(can_frame_obj.DLC){
+        ret = CAN_FillTxFrame(CAN_X,CAN_TX_BUF_STB,&can_frame_obj);
+        if(EOK != ret){
+            KPrintf("CAN fill tx frame failed(CODE:%d)!\n",ret);
+            return ERROR;            
+        }
+        CAN_StartTx(CAN_X,CAN_TX_REQ_STB_ONE);
+    }
+    return ret;
+}
+
+static uint32 CanReadData(void *dev , struct BusBlockReadParam *databuf)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(databuf);
+    x_err_t ret=EOK;
+    stc_can_rx_frame_t frame_received;
+    struct CanSendConfigure *p_can_config = (struct CanSendConfigure*)databuf->buffer;
+    memset(&frame_received,0,sizeof(stc_can_rx_frame_t));
+
+    ret = CAN_GetRxFrame(CAN_X, &frame_received);
+    if(EOK != ret){
+        // KPrintf("CAN recv frame failed(CODE:%d)!\n",ret);
+        p_can_config->data_lenth = 0;
+        return ERROR;            
+    }
+
+    //put message in frame_buffer
+    p_can_config->ide = frame_received.IDE;
+    p_can_config->rtr = frame_received.RTR;
+    if(p_can_config->ide==1){
+        p_can_config->exdid = frame_received.u32ID ;
+    }else{
+        p_can_config->stdid = frame_received.u32ID;
+        p_can_config->exdid = frame_received.u32ID ;
+    }
+    p_can_config->data_lenth = frame_received.DLC;
+    for(int i=0;i<p_can_config->data_lenth;i++){
+        p_can_config->data[i] = frame_received.au8Data[i];
+    }
+    
+    return frame_received.DLC;
+}
+
+static struct CanDevDone can_dev_done = 
+{
+    .open  = NONE,
+    .close  = NONE,
+    .write  = CanWriteData,
+    .read   = CanReadData
+};
+
+static int BoardCanBusInit(struct CanBus *can_bus, struct CanDriver *can_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the can bus */
+    ret = CanBusInit(can_bus, CAN_BUS_NAME_2);
+    if (EOK != ret) {
+        KPrintf("Board_can_init canBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the can driver*/
+    ret = CanDriverInit(can_driver, CAN_DRIVER_NAME_2);
+    if (EOK != ret) {
+        KPrintf("Board_can_init canDriverInit error %d\n", ret);
+        return ERROR;
+    }
+    /*Attach the can driver to the can bus*/
+    ret = CanDriverAttachToBus(CAN_DRIVER_NAME_2, CAN_BUS_NAME_2);
+    if (EOK != ret) {
+        KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/* Attach the can device to the can bus*/
+static int BoardCanDevBend(void)
+{
+    x_err_t ret = EOK;
+    static struct CanHardwareDevice can_device0;
+    memset(&can_device0, 0, sizeof(struct CanHardwareDevice));
+
+    can_device0.dev_done = &can_dev_done;
+
+    ret = CanDeviceRegister(&can_device0, NONE, CAN_2_DEVICE_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_can_init CanDeviceInit device %s error %d\n", CAN_2_DEVICE_NAME_1, ret);
+        return ERROR;
+    }  
+
+    ret = CanDeviceAttachToBus(CAN_2_DEVICE_NAME_1, CAN_BUS_NAME_2);
+    if (EOK != ret) {
+        KPrintf("board_can_init CanDeviceAttachToBus device %s error %d\n", CAN_2_DEVICE_NAME_1, ret);
+        return ERROR;
+    }  
+
+    return ret;
+}
+
+int HwCanInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct CanBus can_bus;
+    memset(&can_bus, 0, sizeof(struct CanBus));
+
+    static struct CanDriver can_driver;
+    memset(&can_driver, 0, sizeof(struct CanDriver));
+
+    can_driver.configure = &(CanDrvConfigure);
+    
+    ret = BoardCanBusInit(&can_bus, &can_driver);
+    if (EOK != ret) {
+      KPrintf(" can_bus_init %s error ret %u\n", CAN_BUS_NAME_2, ret);
+      return ERROR;
+    }
+
+    ret = BoardCanDevBend();
+    if (EOK != ret) {
+        KPrintf("board_can_init error ret %u\n", ret);
+        return ERROR;
+    }
+    return EOK;
+}

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/dac/Kconfig

@@ -0,0 +1,17 @@
+if BSP_USING_DAC
+    config DAC_BUS_NAME
+        string "dac bus name"
+        default "dac"
+
+    config DAC_DRIVER_NAME
+        string "dac driver name"
+        default "dac_drv"
+
+    config DAC_DEVICE_NAME
+        string "dac bus device name"
+        default "dac_dev"
+
+    config DAC_GPIO_NUM
+        int "dac gpio pin num(only support 4 or 5)"
+        default "4"
+endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/dac/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_dac.c 
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/dac/connect_dac.c

@@ -0,0 +1,398 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_dac.c
+* @brief support to register DAC pointer and function
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2023-02-09
+*/
+
+#include <connect_dac.h>
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define DAC_UNIT1_PORT                               (GPIO_PORT_A)
+#define DAC_UNIT1_CHN1_PIN                           (GPIO_PIN_04)
+
+#define VREFH                                        (3.3F)
+#define DAC_CHN1                                     (0U)
+#define DAC_CHN2                                     (1U)
+#define DAC_DATA_ALIGN_12b_R                         (0U)
+#define DAC_DATA_ALIGN_12b_L                         (1U)
+
+#define SUPPORT_AMP
+#define SUPPORT_ADP
+#define SINGLE_WAVE_DAC_CHN                          (DAC_CHN1)
+#define DAC_DATA_ALIGN                               (DAC_DATA_ALIGN_12b_L)
+
+#define SINE_DOT_NUMBER                              (4096U)
+#define SINE_NEGATIVE_TO_POSITVE                     (1.0F)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+typedef enum {
+    DAC_Unit1,
+    DAC_Unit2,
+    DAC_Unit_Max,
+}en_dac_unit_t;
+
+typedef enum {
+    E_Dac_Single,
+    E_Dac_Dual,
+}en_dac_cvt_t;
+
+typedef struct {
+    CM_DAC_TypeDef *pUnit;
+    en_dac_cvt_t enCvtType;
+    uint16_t u16Ch;
+} stc_dac_handle_t;
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+static stc_dac_handle_t m_stcDACHandle[DAC_Unit_Max] = {0};
+static uint32_t gu32SinTable[SINE_DOT_NUMBER];
+static stc_dac_handle_t *pSingleDac;
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @brief   MAU Initialization
+ * @param   None
+ * @retval  None
+ */
+static void MauInit(void)
+{
+    /* Enable MAU peripheral clock. */
+    FCG_Fcg0PeriphClockCmd(PWC_FCG0_MAU, ENABLE);
+}
+
+/**
+ * @brief   MAU De-Initialization
+ * @param   None
+ * @retval  None
+ */
+static void MauDeinit(void)
+{
+    /* Enable MAU peripheral clock. */
+    FCG_Fcg0PeriphClockCmd(PWC_FCG0_MAU, DISABLE);
+}
+
+/**
+ * @brief    Sin table Initialization
+ * @param    [in] pSinTable  sin table
+ * @param    [in] u32count   number of pSinTable items
+ * @retval   None
+ */
+static void SinTableInit(uint32_t pSinTable[], uint32_t u32count)
+{
+    uint32_t i;
+    uint32_t u32AngAvg = (uint32_t)(float32_t)((float32_t)((float32_t)MAU_SIN_ANGIDX_TOTAL / (float32_t)u32count) + 0.5);
+    float32_t fSin;
+    for (i = 0U; i < u32count; i++) {
+        fSin = (((float32_t)MAU_Sin(CM_MAU, (uint16_t)(u32AngAvg * i))
+                 / (float32_t)MAU_SIN_Q15_SCALAR + SINE_NEGATIVE_TO_POSITVE) / VREFH) *
+               (float32_t)DAC_DATAREG_VALUE_MAX + 0.5F;
+
+#if (DAC_DATA_ALIGN == DAC_DATA_ALIGN_12b_L)
+        {
+            pSinTable[i] = (uint32_t)fSin << 4;
+        }
+#else
+        {
+            pSinTable[i] = (uint32_t)fSin;
+        }
+#endif
+    }
+}
+
+/**
+ * @brief    Enable DAC peripheral clock
+ * @param    [in] enUnit  The selected DAC unit
+ * @retval   None
+ */
+static void DacPClkEnable(en_dac_unit_t enUnit)
+{
+    uint32_t u32PClk;
+    switch (enUnit) {
+        case DAC_Unit1:
+            u32PClk = PWC_FCG3_DAC1;
+            break;
+        case DAC_Unit2:
+            u32PClk = PWC_FCG3_DAC2;
+            break;
+        default:
+            u32PClk = PWC_FCG3_DAC1 | PWC_FCG3_DAC2;
+            break;
+    }
+    /* Enable DAC peripheral clock. */
+    FCG_Fcg3PeriphClockCmd(u32PClk, ENABLE);
+}
+
+/**
+ * @brief    Init DAC single channel
+ * @param    [in] enUnit  The selected DAC unit
+ * @retval   A pointer of DAC handler
+ */
+static stc_dac_handle_t *DacSingleConversionInit(en_dac_unit_t enUnit)
+{
+    uint8_t u8Port;
+    uint16_t u16Pin;
+    stc_dac_handle_t *pDac;
+
+    if (enUnit == DAC_Unit1) {
+        pDac = &m_stcDACHandle[DAC_Unit1];
+        pDac->pUnit = CM_DAC1;
+    } else {
+        pDac = &m_stcDACHandle[DAC_Unit2];
+        pDac->pUnit = CM_DAC2;
+    }
+    DacPClkEnable(enUnit);
+
+    pDac->enCvtType = E_Dac_Single;
+#if (SINGLE_WAVE_DAC_CHN == DAC_CHN1)
+    pDac->u16Ch = DAC_CH1;
+#else
+    pDac->u16Ch = DAC_CH2;
+#endif
+
+    /* Init DAC by default value: source from data register and output enabled*/
+    DAC_DeInit(pDac->pUnit);
+    stc_dac_init_t stInit;
+    (void)DAC_StructInit(&stInit);
+    (void)DAC_Init(pDac->pUnit, pDac->u16Ch, &stInit);
+#if (DAC_DATA_ALIGN == DAC_DATA_ALIGN_12b_L)
+    DAC_DataRegAlignConfig(pDac->pUnit, DAC_DATA_ALIGN_L);
+#else
+    DAC_DataRegAlignConfig(pDac->pUnit, DAC_DATA_ALIGN_R);
+#endif
+
+    /* Set DAC pin attribute to analog */
+    if (enUnit == DAC_Unit1) {
+        u8Port = DAC_UNIT1_PORT;
+#if (SINGLE_WAVE_DAC_CHN == DAC_CHN1)
+        u16Pin = DAC_UNIT1_CHN1_PIN;
+#endif
+    }
+    stc_gpio_init_t stcGpioInit;
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    (void)GPIO_Init(u8Port, u16Pin, &stcGpioInit);
+
+#ifdef SUPPORT_ADP
+    /* Set ADC first */
+    /* Enable ADC peripheral clock. */
+    FCG_Fcg3PeriphClockCmd(PWC_FCG3_ADC1 | PWC_FCG3_ADC2 | PWC_FCG3_ADC3, ENABLE);
+    if (CM_ADC1->STR == 0U) {
+        if (CM_ADC2->STR == 0U) {
+            if (CM_ADC3->STR == 0U) {
+                DAC_ADCPrioConfig(pDac->pUnit, DAC_ADP_SELECT_ALL, ENABLE);
+                DAC_ADCPrioCmd(pDac->pUnit, ENABLE);
+            }
+        }
+    }
+#endif
+    return pDac;
+}
+
+/**
+ * @brief    Start single DAC conversions
+ * @param    [in] pDac       A pointer of DAC handler
+ * @retval   None
+ */
+static void DacStartSingleConversion(const stc_dac_handle_t *pDac)
+{
+    /* Enalbe AMP */
+#ifdef SUPPORT_AMP
+    (void)DAC_AMPCmd(pDac->pUnit, pDac->u16Ch, ENABLE);
+#endif
+
+    (void)DAC_Start(pDac->pUnit, pDac->u16Ch);
+
+#ifdef SUPPORT_AMP
+    /* delay 3us before setting data*/
+    DDL_DelayMS(1U);
+#endif
+}
+
+/**
+ * @brief    Convert data by single DAC channel
+ * @param    [in] pDac       A pointer of DAC handler
+ * @param    [in] pDataTable The data table to be converted
+ * @param    [in] u32count   Number of data table items
+ * @retval   None
+ */
+__STATIC_INLINE void DacSetSingleConversionData(const stc_dac_handle_t *pDac, uint32_t const pDataTable[], uint32_t u32count)
+{
+    uint32_t i = 0U;
+
+    for (i = 0U; i < u32count; i++) {
+#ifdef SUPPORT_ADP
+        uint32_t u32TryCount = 100U;
+        while (u32TryCount != 0U) {
+            u32TryCount--;
+            if (SET != DAC_GetChConvertState(pDac->pUnit, pDac->u16Ch)) {
+                break;
+            }
+        }
+#endif
+        DAC_SetChData(pDac->pUnit, pDac->u16Ch, (uint16_t)pDataTable[i]);
+    }
+}
+
+/**
+ * @brief    stop DAC conversion
+ * @param    [in] pDac A pointer of DAC handler
+ * @retval   None
+ */
+static void DAC_StopConversion(const stc_dac_handle_t *pDac)
+{
+    if (NULL == pDac) {
+        DAC_DeInit(CM_DAC1);
+        DAC_DeInit(CM_DAC2);
+    } else if (pDac->enCvtType != E_Dac_Dual) {
+        (void)DAC_Stop(pDac->pUnit, pDac->u16Ch);
+    } else {
+        DAC_StopDualCh(pDac->pUnit);
+    }
+}
+
+static uint32 DacOpen(void *dev)
+{
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev;
+
+    /* Init MAU for generating sine data*/
+    MauInit();
+    /* Init sine data table */
+    SinTableInit(gu32SinTable, SINE_DOT_NUMBER);
+
+    /* Init single DAC */
+    pSingleDac = DacSingleConversionInit(DAC_Unit1);
+
+    return EOK;
+}
+
+static uint32 DacClose(void *dev)
+{
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev;
+    CM_DAC_TypeDef *DACx  = (CM_DAC_TypeDef *)dac_dev->private_data;
+    
+    DAC_StopConversion(pSingleDac);
+    
+    DAC_DeInit(DACx);
+
+    MauDeinit();
+
+    memset(gu32SinTable, 0 , sizeof(gu32SinTable));
+    
+    return EOK;
+}
+
+static uint32 DacWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev;
+    struct HwDac *dac_cfg = (struct HwDac *)dac_dev->haldev.private_data;
+
+    for (int i = 0; i < dac_cfg->digital_data; i ++) {
+        DacStartSingleConversion(pSingleDac);
+        DacSetSingleConversionData(pSingleDac, &gu32SinTable[i], 1U);
+        if (i > SINE_DOT_NUMBER) {
+            i = 0;
+        }
+    }
+
+    return EOK;
+}
+
+static uint32 DacDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+
+    struct DacDriver *dac_drv = (struct DacDriver *)drv;
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dac_drv->driver.owner_bus->owner_haldev;
+    struct HwDac *dac_cfg = (struct HwDac *)dac_dev->haldev.private_data;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_CFG:
+            dac_cfg->digital_data = *(uint16 *)configure_info->private_data;
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct DacDevDone dev_done =
+{
+    DacOpen,
+    DacClose,
+    DacWrite,
+    NONE,
+};
+
+int HwDacInit(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_DAC
+    static struct DacBus dac_bus;
+    static struct DacDriver dac_drv;
+    static struct DacHardwareDevice dac_dev;
+    static struct HwDac dac_cfg;
+
+    dac_drv.configure = DacDrvConfigure;
+
+    ret = DacBusInit(&dac_bus, DAC_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = DacDriverInit(&dac_drv, DAC_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = DacDriverAttachToBus(DAC_DRIVER_NAME, DAC_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    dac_dev.dac_dev_done = &dev_done;
+    dac_cfg.DACx = CM_DAC1;
+    dac_cfg.digital_data = 0;
+
+    ret = DacDeviceRegister(&dac_dev, (void *)&dac_cfg, DAC_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = DacDeviceAttachToBus(DAC_DEVICE_NAME, DAC_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC device register error %d\n", ret);
+        return ERROR;
+    }
+#endif 
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/ethernet/eth_driver.c

@@ -277,10 +277,7 @@ struct pbuf* low_level_input(struct netif* netif)
     return p;
 }
 
-extern void LwipSetIPTest(int argc, char* argv[]);
 int HwEthInit(void)
 {
-    // lwip_config_tcp(0, lwip_ipaddr, lwip_netmask, lwip_gwaddr);
-    LwipSetIPTest(1, NULL);
     return EOK;
 }

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/ethernet/eth_netdev.c

@@ -76,6 +76,7 @@ static int lwip_netdev_set_addr_info(struct netdev* netdev, ip_addr_t* ip_addr,
             netif_set_gw((struct netif*)netdev->user_data, ip_2_ip4(gw));
         }
     }
+    return 0;
 }
 
 #ifdef LWIP_DNS
@@ -92,7 +93,7 @@ static int lwip_netdev_set_dns_server(struct netdev* netdev, uint8_t dns_num, ip
 }
 #endif
 
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
 static int lwip_netdev_set_dhcp(struct netdev* netdev, bool is_enabled)
 {
     netdev_low_level_set_dhcp_status(netdev, is_enabled);
@@ -120,7 +121,7 @@ static const struct netdev_ops lwip_netdev_ops = {
 #ifdef LWIP_DNS
     .set_dns_server = lwip_netdev_set_dns_server,
 #endif
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
     .set_dhcp = lwip_netdev_set_dhcp,
 #endif
     .set_default = lwip_netdev_set_default,
@@ -183,9 +184,9 @@ int lwip_netdev_add(struct netif* lwip_netif)
     netdev->ops = &lwip_netdev_ops;
     netdev->hwaddr_len = lwip_netif->hwaddr_len;
     memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
-    netdev->ip_addr = lwip_netif->ip_addr;
+    netdev->ip_addr = &lwip_netif->ip_addr;
-    netdev->gw = lwip_netif->gw;
+    netdev->gw = &lwip_netif->gw;
-    netdev->netmask = lwip_netif->netmask;
+    netdev->netmask = &lwip_netif->netmask;
 
     return result;
 }

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/ethernet/ethernetif.c

@@ -204,7 +204,6 @@ void ethernetif_input(void* netif_arg)
     /* Move received packet into a new pbuf */
     while (1) {
         sys_arch_sem_wait(get_eth_recv_sem(), WAITING_FOREVER);
-        KPrintf("%s -->\n", netif->name);
         while (1) {
             p = low_level_input(netif);
 #ifndef ETHERNET_LOOPBACK_TEST

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/ethernet_wiz/Kconfig

@@ -1,9 +1,5 @@
 # Kconfig file
 
-config BSP_WIZ_RST_PIN
-    int 
-    default 13
-
 config BSP_WIZ_INT_PIN
     int 
-    default 14
+    default 106

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/ethernet_wiz/w5x00_lwip.c

@@ -113,7 +113,6 @@ void ethernetif_input2(void* netif_arg)
     struct pbuf* p = NULL;
     for (;;) {
         sys_arch_sem_wait(get_eth_recv_sem2(), WAITING_FOREVER);
-        KPrintf("%s -->\n", netif->name);
         sys_mutex_lock(&wiz_trans_mtx);
         while (1) {
 

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/i2c/Kconfig

@@ -0,0 +1,22 @@
+config I2C_BUS_NAME_1
+    string "i2c 1 bus name"
+    default "i2c1"
+config I2C_DRV_NAME_1
+    string "i2c bus 1 driver name"
+    default "i2c1_drv"
+config I2C_1_DEVICE_NAME_0
+    string "i2c bus 1 device 0 name"
+    default "i2c1_dev0"
+config I2C_DEVICE_MODE
+    bool "choose i2c device mode as master or slave"
+    default y
+    choice
+        prompt "choose i2c mode"
+        default I2C_DEVICE_MASTER
+
+        config I2C_DEVICE_MASTER
+            bool "set i2c master"
+        
+        config I2C_DEVICE_SLAVE
+            bool "set i2c slave"
+    endchoice

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/i2c/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_i2c.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/i2c/connect_i2c.c

@@ -0,0 +1,491 @@
+/*
+ *******************************************************************************
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/**
+* @file connect_i2c.c
+* @brief support edu-arm32-board i2c function and register to bus framework
+* @version 3.0 
+* @author AIIT XUOS Lab
+* @date 2022-12-05
+*/
+
+/*************************************************
+File name: connect_i2c.c
+Description: support edu-arm32-board i2c configure and i2c bus register function
+Others: take projects/ev_hc32f4a0_lqfp176/examples/i2c/i2c_master_polling/source/main.c for references
+History: 
+1. Date: 2022-12-05
+Author: AIIT XUOS Lab
+Modification: 
+1. support edu-arm32-board i2c configure, write and read
+2. support edu-arm32-board i2c bus device and driver register
+*************************************************/
+
+#include <connect_i2c.h>
+
+#define I2C_UNIT                        (CM_I2C1)
+#define I2C_FCG_USE                     (FCG1_PERIPH_I2C1)
+
+#define I2C_TIMEOUT                     (0x40000UL)
+#define I2C_BAUDRATE                    (400000UL)
+
+/* Define port and pin for SDA and SCL */
+#define I2C_SCL_PORT                    (GPIO_PORT_D)
+#define I2C_SCL_PIN                     (GPIO_PIN_03)
+#define I2C_SDA_PORT                    (GPIO_PORT_F)
+#define I2C_SDA_PIN                     (GPIO_PIN_10)
+#define I2C_GPIO_SCL_FUNC               (GPIO_FUNC_49)
+#define I2C_GPIO_SDA_FUNC               (GPIO_FUNC_48)
+
+static x_err_t I2cGpioInit(void)
+{
+    GPIO_SetFunc(I2C_SDA_PORT, I2C_SDA_PIN, I2C_GPIO_SDA_FUNC);
+    GPIO_SetFunc(I2C_SCL_PORT, I2C_SCL_PIN, I2C_GPIO_SCL_FUNC);
+
+    return EOK;
+}
+
+static uint32 I2cInit(struct I2cDriver *i2c_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(i2c_drv);
+
+    struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)i2c_drv->driver.owner_bus->owner_haldev; 
+
+    stc_i2c_init_t i2c_init;
+    (void)I2C_StructInit(&i2c_init);
+    i2c_init.u32Baudrate = I2C_BAUDRATE;
+    i2c_init.u32SclTime = 3UL;
+    i2c_init.u32ClockDiv = I2C_CLK_DIV4;
+
+    if (configure_info->private_data) {
+        i2c_dev->i2c_dev_addr = *((uint16 *)configure_info->private_data);
+    } else {
+        KPrintf("I2cInit need set i2c dev addr\n");
+        return ERROR;
+    }
+
+    /* Configure I2C */
+    float32_t f32Error;
+    int32_t i32Ret = LL_ERR;
+    I2C_DeInit(I2C_UNIT);
+    i32Ret = I2C_Init(I2C_UNIT, &i2c_init, &f32Error);
+
+#ifdef I2C_DEVICE_SLAVE
+    if (LL_OK == i32Ret) {
+        /* Set slave address */
+        I2C_SlaveAddrConfig(I2C_UNIT, I2C_ADDR0, I2C_ADDR_7BIT, i2c_dev->i2c_dev_addr);
+    }   
+#endif
+
+    if(i32Ret != LL_OK) {
+        return ERROR;
+    }
+
+    I2C_BusWaitCmd(I2C_UNIT, ENABLE);
+
+    return EOK;
+}
+
+static uint32 I2cDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct I2cDriver *i2c_drv = (struct I2cDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = I2cInit(i2c_drv, configure_info);
+            break;
+        default:
+            break;
+    } 
+
+    return ret;
+}
+
+static uint32 I2cMasterWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
+{
+    if (msg->len == 0) {
+            return EOK;
+    }
+    uint32 i32Ret;
+
+    I2C_Cmd(I2C_UNIT, ENABLE);
+    DDL_DelayMS(20UL);
+    I2C_SWResetCmd(I2C_UNIT, ENABLE);
+    I2C_SWResetCmd(I2C_UNIT, DISABLE);
+    DDL_DelayMS(20UL);
+    i32Ret = I2C_Start(I2C_UNIT, I2C_TIMEOUT);
+    if (LL_OK == i32Ret) {
+        i32Ret = I2C_TransAddr(I2C_UNIT, i2c_dev->i2c_dev_addr, I2C_DIR_TX, I2C_TIMEOUT);
+
+        if (i32Ret == LL_OK) {
+            i32Ret = I2C_TransData(I2C_UNIT, msg->buf, msg->len, I2C_TIMEOUT);
+            KPrintf("Master Send Success!\n");
+        }
+    }
+
+    (void)I2C_Stop(I2C_UNIT, I2C_TIMEOUT);
+    I2C_Cmd(I2C_UNIT, DISABLE);
+
+    return i32Ret;
+}
+
+static uint32 I2cMasterReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
+{
+    uint32 i32Ret;
+
+    I2C_Cmd(I2C_UNIT, ENABLE);
+    I2C_SWResetCmd(I2C_UNIT, ENABLE);
+    I2C_SWResetCmd(I2C_UNIT, DISABLE);
+    i32Ret = I2C_Start(I2C_UNIT, I2C_TIMEOUT);
+    if (LL_OK == i32Ret) {
+        if (msg->len == 1U) {
+            I2C_AckConfig(I2C_UNIT, I2C_NACK);
+        }
+
+        i32Ret = I2C_TransAddr(I2C_UNIT, i2c_dev->i2c_dev_addr, I2C_DIR_RX, I2C_TIMEOUT);
+
+        if (LL_OK == i32Ret) {
+            i32Ret = I2C_MasterReceiveDataAndStop(I2C_UNIT, msg->buf, msg->len, I2C_TIMEOUT);
+            KPrintf("Master Receive Success!\n");
+        }
+
+        I2C_AckConfig(I2C_UNIT, I2C_ACK);
+    }
+
+    if (LL_OK != i32Ret) {
+        (void)I2C_Stop(I2C_UNIT, I2C_TIMEOUT);
+    }
+    I2C_Cmd(I2C_UNIT, DISABLE);
+    return i32Ret;
+}
+
+static uint32 I2cSlaveWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg) {
+    if (msg->len == 0) {
+        return EOK;
+    }
+    uint32 i32Ret;
+
+    I2C_Cmd(I2C_UNIT, ENABLE);
+
+    /* Clear status */
+    I2C_ClearStatus(I2C_UNIT, I2C_CLR_STOPFCLR | I2C_CLR_NACKFCLR);
+
+    /* Wait slave address matched */
+    while (RESET == I2C_GetStatus(I2C_UNIT, I2C_FLAG_MATCH_ADDR0)) {
+        ;
+    }
+
+    I2C_ClearStatus(I2C_UNIT, I2C_CLR_SLADDR0FCLR);
+
+    if (RESET == I2C_GetStatus(I2C_UNIT, I2C_FLAG_TRA)) {
+        i32Ret = LL_ERR;
+    } else {
+        i32Ret = I2C_TransData(I2C_UNIT, msg->buf, msg->len, I2C_TIMEOUT);
+		KPrintf("Slave send success!\r\n");
+
+        if ((LL_OK == i32Ret) || (LL_ERR_TIMEOUT == i32Ret)) {
+            /* Release SCL pin */
+            (void)I2C_ReadData(I2C_UNIT);
+
+            /* Wait stop condition */
+            i32Ret = I2C_WaitStatus(I2C_UNIT, I2C_FLAG_STOP, SET, I2C_TIMEOUT);
+        }
+    }
+
+    I2C_Cmd(I2C_UNIT, DISABLE);
+    return i32Ret;
+}
+
+static uint32 I2cSlaveReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg) {
+    uint32 i32Ret;
+
+    I2C_Cmd(I2C_UNIT, ENABLE);
+
+    /* Clear status */
+    I2C_ClearStatus(I2C_UNIT, I2C_CLR_STOPFCLR | I2C_CLR_NACKFCLR);
+
+    /* Wait slave address matched */
+    while (RESET == I2C_GetStatus(I2C_UNIT, I2C_FLAG_MATCH_ADDR0)) {
+        ;
+    }
+
+    I2C_ClearStatus(I2C_UNIT, I2C_CLR_SLADDR0FCLR);
+
+    if (RESET == I2C_GetStatus(I2C_UNIT, I2C_FLAG_TRA)) {
+        /* Slave receive data*/
+        i32Ret = I2C_ReceiveData(I2C_UNIT, msg->buf, msg->len, I2C_TIMEOUT);
+        KPrintf("Slave receive success!\r\n");
+
+        if ((LL_OK == i32Ret) || (LL_ERR_TIMEOUT == i32Ret)) {
+            /* Wait stop condition */
+            i32Ret = I2C_WaitStatus(I2C_UNIT, I2C_FLAG_STOP, SET, I2C_TIMEOUT);
+        }
+    } else {
+        i32Ret = LL_ERR;
+    }
+
+    I2C_Cmd(I2C_UNIT, DISABLE);
+    return i32Ret;
+}
+
+
+/* manage the i2c device operations*/
+static const struct I2cDevDone i2c_dev_done =
+{
+    .dev_open = NONE,
+    .dev_close = NONE,
+#ifdef I2C_DEVICE_SLAVE
+    .dev_write = I2cSlaveWriteData,
+    .dev_read = I2cSlaveReadData,
+#else
+    .dev_write = I2cMasterWriteData,
+    .dev_read = I2cMasterReadData,
+#endif
+};
+
+/* Init i2c bus */
+static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver)
+{
+    x_err_t ret = EOK;
+
+    /* Init the i2c bus */
+    ret = I2cBusInit(i2c_bus, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /* Init the i2c driver*/
+    ret = I2cDriverInit(i2c_driver, I2C_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /* Attach the i2c driver to the i2c bus*/
+    ret = I2cDriverAttachToBus(I2C_DRV_NAME_1, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+/* Attach the i2c device to the i2c bus*/
+static int BoardI2cDevBend(void)
+{
+    x_err_t ret = EOK;
+    static struct I2cHardwareDevice i2c_device0;
+    memset(&i2c_device0, 0, sizeof(struct I2cHardwareDevice));
+
+    i2c_device0.i2c_dev_done = &i2c_dev_done;
+
+    ret = I2cDeviceRegister(&i2c_device0, NONE, I2C_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDeviceInit device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    ret = I2cDeviceAttachToBus(I2C_1_DEVICE_NAME_0, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDeviceAttachToBus device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    return ret;
+}
+
+/* EDU-ARM32 BOARD I2C INIT*/
+int HwI2cInit(void)
+{
+    x_err_t ret = EOK;
+    static struct I2cBus i2c_bus;
+    memset(&i2c_bus, 0, sizeof(struct I2cBus));
+
+    static struct I2cDriver i2c_driver;
+    memset(&i2c_driver, 0, sizeof(struct I2cDriver));
+
+    I2cGpioInit();
+
+    /* Enable I2C Peripheral*/
+    FCG_Fcg1PeriphClockCmd(I2C_FCG_USE, ENABLE);
+
+    i2c_driver.configure = I2cDrvConfigure;
+
+    ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);
+    if (ret != EOK) {
+        KPrintf("board_i2c_init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardI2cDevBend();
+    if (EOK != ret) {
+        KPrintf("board_i2c_init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+// #define I2C_TEST
+#ifdef I2C_TEST
+
+#define USER_KEY_PORT                  (GPIO_PORT_I)
+#define USER_KEY_PIN                   (GPIO_PIN_07)
+
+#define DEVICE_ADDR                    (0x06U)
+
+static struct Bus *bus1;
+static struct I2cDriver *i2c_drv1;
+
+void I2cInitTest(void)
+{
+    x_err_t ret = EOK;
+
+    stc_gpio_init_t stcGpioInit;
+
+    /* KEY initialize */
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinState = PIN_STAT_RST;
+    stcGpioInit.u16PinDir = PIN_DIR_IN;
+    (void)GPIO_Init(USER_KEY_PORT, USER_KEY_PIN, &stcGpioInit);
+
+    bus1 = BusFind(I2C_BUS_NAME_1);
+    bus1->owner_driver = BusFindDriver(bus1, I2C_DRV_NAME_1);
+    bus1->owner_haldev = BusFindDevice(bus1, I2C_1_DEVICE_NAME_0);
+
+    struct BusConfigureInfo configure_info;
+    configure_info.configure_cmd = OPE_INT;
+    configure_info.private_data = (void *)DEVICE_ADDR;
+
+    ret = I2cDrvConfigure(bus1->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("initialize %s failed!\n", I2C_UNIT);
+        return;
+    }
+
+    i2c_drv1 = (struct I2cDriver *)bus1->owner_driver;
+
+    return;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+I2cInitTest, I2cInitTest,  i2c init);
+
+void I2cMasterTest(void)
+{
+    x_err_t ret = EOK;
+
+    struct I2cHardwareDevice *i2c_dev1 = (struct I2cHardwareDevice *)i2c_drv1->driver.owner_bus->owner_haldev;
+
+    struct I2cDataStandard msg;
+    uint8 u8TxBuf[256U] = {1, 2, 3, 4, 5};
+    uint8 u8RxBuf[256U];
+
+    (void)memset(u8RxBuf, 0, 256U);
+
+    msg.len = 5;
+    msg.buf = u8TxBuf;
+
+    while (SET == GPIO_ReadInputPins(USER_KEY_PORT, USER_KEY_PIN)) {
+        ;
+    }
+
+    KPrintf("I2C send data\n");
+
+    ret = I2cMasterWriteData(i2c_dev1, &msg);
+    if (EOK != ret) {
+        KPrintf("I2C send failed! ret %d\n", ret);
+        return;
+    }
+    
+    KPrintf("Master send data: ");
+    
+    for (uint16 i = 0; i < msg.len; i++) {
+        KPrintf("%d ", (msg.buf)[i]);
+    }
+
+    KPrintf("\n");
+
+    /* 50mS delay for device*/
+    DDL_DelayMS(50UL);
+
+    msg.buf = u8RxBuf;
+		
+    (void)I2cMasterReadData(i2c_dev1, &msg);
+
+    KPrintf("Master receive data: ");
+    
+    for (uint16 i = 0; i < msg.len; i++) {
+        KPrintf("%d ", (msg.buf)[i]);
+    }
+
+    KPrintf("\n");
+
+    return;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+I2cMasterTest, I2cMasterTest,  i2c master send and receive data);
+
+void I2cSlaveTest(void)
+{
+    x_err_t ret = EOK;
+
+    struct I2cHardwareDevice *i2c_dev1 = (struct I2cHardwareDevice *)i2c_drv1->driver.owner_bus->owner_haldev;
+
+    struct I2cDataStandard msg;
+    uint8 u8RxBuf[256U];
+
+    (void)memset(u8RxBuf, 0, 256U);
+
+    msg.len = 5;
+    msg.buf = u8RxBuf;
+
+    KPrintf("I2C receive data\n");
+
+    for (;;) {
+        ret = I2cSlaveReadData(i2c_dev1, &msg);
+        if (ret != EOK) {
+            KPrintf("I2C receive failed!\n");
+            break;
+        } else {
+            KPrintf("Slave receive data: ");
+            for (uint16 i = 0; i < msg.len; i++) {
+                KPrintf("%d ", (msg.buf)[i]);
+            }
+            KPrintf("\n");
+        }
+        
+        ret = I2cSlaveWriteData(i2c_dev1, &msg);
+        if (ret != EOK) {
+            KPrintf("I2C send failed!\n");
+            break;
+        } else {
+            KPrintf("Slave send data: ");
+            for (uint16 i = 0; i < msg.len; i++) {
+                KPrintf("%d ", (msg.buf)[i]);
+            }
+            KPrintf("\n");
+        }
+    }
+
+    return;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+I2cSlaveTest, I2cSlaveTest,  i2c slave receive and send data);
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_adc.h

@@ -0,0 +1,42 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_uart.h
+* @brief define edu-arm32-board usart function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2023-02-09
+*/
+
+#include <device.h>
+#include <hardware_irq.h>
+#include <hc32_ll_adc.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct HwAdc 
+{
+    CM_ADC_TypeDef *ADCx;
+    uint8 adc_channel;
+};
+
+int HwAdcInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_can.h

@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2021 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_can.h
+* @brief define edu-arm32-board can function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2023-02-21
+*/
+
+#ifndef CONNECT_CAN_H
+#define CONNECT_CAN_H
+
+#include <device.h>
+#include <hc32_ll_can.h>
+#include <hc32_ll_clk.h>
+#include <hc32_ll_gpio.h>
+#include <hardware_irq.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+int HwCanInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_dac.h

@@ -0,0 +1,43 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_uart.h
+* @brief define edu-arm32-board usart function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2023-02-09
+*/
+
+#include <device.h>
+#include <hardware_irq.h>
+#include <hc32_ll_fcg.h>
+#include <hc32_ll_dac.h>
+#include <hc32_ll_gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct HwDac 
+{
+    CM_DAC_TypeDef *DACx;
+    uint16 digital_data;
+};
+
+int HwDacInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_flash.h

@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_flash.h
+* @brief define edu-arm32-board qspi-flash function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2022-10-17
+*/
+
+#ifndef CONNECT_FLASH_H
+#define CONNECT_FLASH_H
+
+#include <device.h>
+#include <hardware_irq.h>
+#include <flash_spi.h>
+#include <hc32_ll_qspi.h>
+#include <hc32_ll_gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int FlashW25qxxSpiDeviceInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_hwtimer.h

@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_hwtimer.h
+* @brief define edu-arm32-board hwtimer function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2023-02-16
+*/
+
+#ifndef CONNECT_HWTIMER_H
+#define CONNECT_HWTIMER_H
+
+#include <device.h>
+#include <hc32f4a0.h>
+#include <hardware_irq.h>
+#include <hc32_ll_tmr0.h>
+#include <hc32_ll_gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwTimerInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_i2c.h

@@ -0,0 +1,42 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_i2c.h
+* @brief define edu-arm32-board i2c function and struct
+* @version 3.0
+* @author AIIT XUOS Lab
+* @date 2022-12-05
+*/
+
+#ifndef CONNECT_I2C_H
+#define CONNECT_I2C_H
+
+#include <device.h>
+#include <hc32_ll.h>
+#include <hc32_ll_i2c.h>
+#include <hc32_ll_utility.h>
+#include <hc32_ll_fcg.h>
+#include <hc32_ll_gpio.h>
+#include <hc32_ll_def.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwI2cInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_rtc.h

@@ -0,0 +1,37 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_rtc.h
+* @brief define edu-arm32-board rtc function and struct
+* @version 3.0
+* @author AIIT XUOS Lab
+* @date 2023-02-02
+*/
+
+#ifndef CONNECT_RTC_H
+#define CONNECT_RTC_H
+
+#include <device.h>
+#include <hc32_ll_rtc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwRtcInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_spi_lora.h

@@ -0,0 +1,61 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_spi_lora.h
+* @brief define spi lora dev function and struct using bus driver framework
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-10-31
+*/
+
+#ifndef CONNECT_SPI_LORA_H
+#define CONNECT_SPI_LORA_H
+
+#include <device.h>
+#include <hc32_ll_utility.h>
+#include <connect_spi.h>
+#include <radio.h>
+#include <spi_lora_sx12xx.h>
+#include <sx1276.h>
+#include <sx1276-Hal.h>
+#include <sx1276-LoRa.h>
+#include <sx1276-LoRaMisc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//#define SPI_LORA_FREQUENCY 10000000
+#define SPI_LORA_BUFFER_SIZE 256
+
+typedef struct SpiLoraDevice *SpiLoraDeviceType;
+
+struct LoraDevDone
+{
+    uint32 (*open) (void *dev);
+    uint32 (*close) (void *dev);
+    uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param);
+    uint32 (*read) (void *dev, struct BusBlockReadParam *read_param);
+};
+
+struct SpiLoraDevice
+{
+    struct SpiHardwareDevice *spi_dev;
+    struct SpiHardwareDevice lora_dev;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_usb.h

@@ -0,0 +1,54 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_usb.h
+* @brief define edu-arm32-board usb function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2022-11-07
+*/
+
+#ifndef CONNECT_USB_H
+#define CONNECT_USB_H
+
+#include <device.h>
+#include <hc32_ll_utility.h>
+#include <hc32_ll_gpio.h>
+#include <usb_lib.h>
+#include <usb_host_user.h>
+#include <usb_host_driver.h>
+#include <usb_host_core.h>
+#include <usb_host_msc_class.h>
+#include <usb_host_msc_scsi.h>
+#include <usb_host_msc_bot.h>
+#include <usb_host_int.h>
+
+#if defined(FS_VFS)
+#include <iot-vfs.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_HOST_STACK_SIZE 4096
+
+#define USB_SINGLE_BLOCK_SIZE 512
+
+int HwUsbHostInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/include/connect_wdt.h

@@ -0,0 +1,37 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_wdt.h
+* @brief define edu-arm32-board watchdog function and struct
+* @version 3.0
+* @author AIIT XUOS Lab
+* @date 2023-02-02
+*/
+
+#ifndef CONNECT_WDT_H
+#define CONNECT_WDT_H
+
+#include <device.h>
+#include <hc32_ll_wdt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwWdtInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/rtc/Kconfig

@@ -0,0 +1,11 @@
+if BSP_USING_RTC
+    config RTC_BUS_NAME
+        string "rtc bus name"
+        default "rtc"
+    config RTC_DRV_NAME
+        string "rtc bus driver name"
+        default "rtc_drv"
+    config RTC_DEVICE_NAME
+            string "rtc bus device name"
+            default "rtc_dev"     
+endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/rtc/Makefile

@@ -0,0 +1,2 @@
+SRC_FILES := connect_rtc.c
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/rtc/connect_rtc.c

@@ -0,0 +1,185 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_rtc.c
+* @brief support aiit-edu-arm32-board rtc function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2023-02-02
+*/
+
+#include <connect_rtc.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <time.h>
+
+static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+
+    struct RtcDriver *rtc_drv = (struct RtcDriver *)drv;
+    struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data;
+
+    int cmd = drv_param->rtc_operation_cmd;
+    time_t *time = drv_param->time;
+
+    switch (cmd)
+    {
+        case OPER_RTC_GET_TIME:
+        {
+            struct tm ct;
+            stc_rtc_date_t rtc_date;
+            stc_rtc_time_t rtc_time;
+
+            // rtc_timer_get(&year, &month, &day, &hour, &minute, &second);
+            RTC_GetDate(RTC_DATA_FMT_DEC, &rtc_date);
+            RTC_GetTime(RTC_DATA_FMT_DEC, &rtc_time);
+
+            ct.tm_year = rtc_date.u8Year ;
+            ct.tm_mon = rtc_date.u8Month ;
+            ct.tm_mday = rtc_date.u8Day;
+            ct.tm_wday = rtc_date.u8Weekday;
+
+            ct.tm_hour = rtc_time.u8Hour;
+            ct.tm_min = rtc_time.u8Minute;
+            ct.tm_sec = rtc_time.u8Second;
+
+            *time = mktime(&ct);
+        }
+        break;
+        case OPER_RTC_SET_TIME:
+        {
+            struct tm *ct;
+            stc_rtc_date_t rtc_date;
+            stc_rtc_time_t rtc_time;
+            x_base lock;
+
+            lock = CriticalAreaLock();
+            ct = localtime(time);
+            rtc_date.u8Year = ct->tm_year ;
+            rtc_date.u8Month = ct->tm_mon ;
+            rtc_date.u8Day = ct->tm_mday;
+            rtc_date.u8Weekday = ct->tm_wday;
+            rtc_time.u8Hour = ct->tm_hour;
+            rtc_time.u8Minute = ct->tm_min;
+            rtc_time.u8Second = ct->tm_sec;
+            CriticalAreaUnLock(lock);
+
+            RTC_SetDate(RTC_DATA_FMT_DEC, &rtc_date);
+            RTC_SetTime(RTC_DATA_FMT_DEC, &rtc_time);
+        }
+        break;
+    }
+    return EOK;
+}
+
+/*manage the rtc device operations*/
+static const struct RtcDevDone dev_done =
+{
+    .open = NONE,
+    .close = NONE,
+    .write = NONE,
+    .read = NONE,
+};
+
+static int BoardRtcBusInit(struct RtcBus *rtc_bus, struct RtcDriver *rtc_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the rtc bus */
+    ret = RtcBusInit(rtc_bus, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the rtc driver*/
+    ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the rtc driver to the rtc bus*/
+    ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the rtc device to the rtc bus*/
+static int BoardRtcDevBend(void)
+{
+    x_err_t ret = EOK;
+
+    static struct RtcHardwareDevice rtc_device;
+    memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice));
+
+    rtc_device.dev_done = &(dev_done);
+
+    ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret);
+        return ERROR;
+    }  
+
+    ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+
+int HwRtcInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct RtcBus rtc_bus;
+    memset(&rtc_bus, 0, sizeof(struct RtcBus));
+
+    static struct RtcDriver rtc_driver;
+    memset(&rtc_driver, 0, sizeof(struct RtcDriver));
+    
+    rtc_driver.configure = &(RtcConfigure);
+
+    ret = BoardRtcBusInit(&rtc_bus, &rtc_driver);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardRtcDevBend();
+    if (EOK != ret) {
+        KPrintf("HwRtcInit error ret %u\n", ret);
+    }
+    
+    stc_rtc_init_t stcRtcInit;
+    /* Configure structure initialization */
+    (void)RTC_StructInit(&stcRtcInit);
+
+    /* Configuration RTC structure */
+    stcRtcInit.u8ClockSrc  = RTC_CLK_SRC_XTAL32;
+    stcRtcInit.u8HourFormat= RTC_HOUR_FMT_24H;
+    stcRtcInit.u8IntPeriod = RTC_INT_PERIOD_PER_SEC;
+    (void)RTC_Init(&stcRtcInit);
+
+    RTC_Cmd(LL_RTC_ENABLE);
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/connect_flash.c

@@ -0,0 +1,260 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_flash.c
+* @brief support edu-arm32-board qspi-flash function and register to bus framework
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2023-02-16
+*/
+#include <connect_flash.h>
+
+#define QSPI_DEVICE_SLAVE_ID_0 (0)
+#define QSPI_UNIT    (CM_QSPI)
+
+#define QSPI_CS_PORT (GPIO_PORT_C)
+#define QSPI_SCK_PORT (GPIO_PORT_C)
+#define QSPI_IO0_PORT (GPIO_PORT_D)
+#define QSPI_IO1_PORT (GPIO_PORT_D)
+#define QSPI_IO2_PORT (GPIO_PORT_D)
+#define QSPI_IO3_PORT (GPIO_PORT_D)
+
+#define QSPI_CS_PIN (GPIO_PIN_07)
+#define QSPI_SCK_PIN (GPIO_PIN_06)
+#define QSPI_IO0_PIN (GPIO_PIN_08)
+#define QSPI_IO1_PIN (GPIO_PIN_09)
+#define QSPI_IO2_PIN (GPIO_PIN_10)
+#define QSPI_IO3_PIN (GPIO_PIN_11)
+
+#define QSPI_PIN_FUNC (GPIO_FUNC_18)
+
+static uint32 QSpiSdkInit(struct SpiDriver *spi_drv)
+{
+    stc_qspi_init_t stcInit;
+
+    FCG_Fcg1PeriphClockCmd(PWC_FCG1_QSPI, ENABLE);
+
+    (void)QSPI_StructInit(&stcInit);
+    stcInit.u32ClockDiv      = QSPI_CLK_DIV3;
+    stcInit.u32SpiMode       = QSPI_SPI_MD0;
+    stcInit.u32ReadMode      = QSPI_RD_MD_STD_RD;
+    stcInit.u32DummyCycle   = QSPI_DUMMY_CYCLE8;        
+    stcInit.u32AddrWidth     = QSPI_ADDR_WIDTH_24BIT;
+    return QSPI_Init(&stcInit);
+    
+}
+
+static void QspiPinConfig(void)
+{
+    stc_gpio_init_t stcGpioInit;
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinState = PIN_STAT_RST;
+    stcGpioInit.u16PinDir = PIN_DIR_OUT;
+    (void)GPIO_Init(QSPI_CS_PORT, QSPI_CS_PIN|QSPI_SCK_PIN, &stcGpioInit);
+    stcGpioInit.u16PinState = PIN_STAT_SET;
+    (void)GPIO_Init(QSPI_IO0_PORT, QSPI_IO1_PIN|QSPI_IO2_PIN|QSPI_IO3_PIN, &stcGpioInit);
+    stcGpioInit.u16PinDir = PIN_DIR_IN;
+    (void)GPIO_Init(QSPI_IO0_PORT, QSPI_IO0_PIN, &stcGpioInit);
+
+    GPIO_ResetPins(QSPI_CS_PORT, QSPI_CS_PIN);
+    GPIO_SetPins(QSPI_IO0_PORT, QSPI_IO2_PIN|QSPI_IO3_PIN);
+
+    GPIO_SetFunc(QSPI_CS_PORT, QSPI_CS_PIN, QSPI_PIN_FUNC);
+    GPIO_SetFunc(QSPI_SCK_PORT, QSPI_SCK_PIN, QSPI_PIN_FUNC);
+    GPIO_SetFunc(QSPI_IO0_PORT, QSPI_IO0_PIN, QSPI_PIN_FUNC);
+    GPIO_SetFunc(QSPI_IO1_PORT, QSPI_IO1_PIN, QSPI_PIN_FUNC);
+    GPIO_SetFunc(QSPI_IO2_PORT, QSPI_IO2_PIN, QSPI_PIN_FUNC);
+    GPIO_SetFunc(QSPI_IO3_PORT, QSPI_IO3_PIN, QSPI_PIN_FUNC);
+}
+
+static uint32 QSpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
+{
+    SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
+    uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
+    uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
+    CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data; 
+    x_err_t ret = EOK;
+    if (spi_datacfg->spi_chip_select) {
+        // GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
+        QSPI_EnterDirectCommMode();
+    }
+    if(spi_datacfg->length > 0U && spi_datacfg->tx_buff!=NULL){
+        for(int i=0;i<spi_datacfg->length;i++){
+            QSPI_WriteDirectCommValue(spi_datacfg->tx_buff[i]);           
+        }
+    }
+    if (spi_datacfg->spi_cs_release) {
+        // GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
+        QSPI_ExitDirectCommMode();   
+    }
+    return ret;
+}
+
+static uint32 QSpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
+{
+    SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
+    uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
+    uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
+    CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data; 
+    x_err_t ret = EOK;
+    uint8_t *read_buffer = spi_datacfg->rx_buff;
+
+    if (spi_datacfg->spi_chip_select) {
+        // GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
+        QSPI_EnterDirectCommMode();
+    }
+    if(spi_datacfg->length > 0U && spi_datacfg->rx_buff!=NULL){
+        for(int i=0;i<spi_datacfg->length;i++){
+            read_buffer[i] = (uint8_t)QSPI_ReadDirectCommValue();            
+        }
+    }
+    if (spi_datacfg->spi_cs_release) {
+        // GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
+        QSPI_ExitDirectCommMode(); 
+    }
+    return ret;
+}
+
+static uint32 QSpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct SpiDriver *spi_drv = (struct SpiDriver *)drv;
+    struct SpiMasterParam *spi_param;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            QSpiSdkInit(spi_drv);
+            QspiPinConfig();
+            break;
+        case OPE_CFG:
+            spi_param = (struct SpiMasterParam *)configure_info->private_data;
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+/*manage the qspi device operations*/
+static const struct SpiDevDone qspi_dev_done =
+{
+    .dev_open = NONE,
+    .dev_close = NONE,
+    .dev_write = QSpiWriteData,
+    .dev_read = QSpiReadData,
+};
+
+static int BoardQSpiDevBend(void)
+{
+    x_err_t ret = EOK;
+
+    static struct SpiHardwareDevice qspi_device0;
+    memset(&qspi_device0, 0, sizeof(struct SpiHardwareDevice));
+
+    static struct SpiSlaveParam qspi_slaveparam0;
+    memset(&qspi_slaveparam0, 0, sizeof(struct SpiSlaveParam));
+
+    qspi_slaveparam0.spi_slave_id = QSPI_DEVICE_SLAVE_ID_0;
+    qspi_slaveparam0.spi_cs_gpio_pin = QSPI_CS_PIN;
+    qspi_slaveparam0.spi_cs_gpio_port = QSPI_CS_PORT;
+
+    qspi_device0.spi_param.spi_slave_param = &qspi_slaveparam0;
+    qspi_device0.spi_dev_done = &(qspi_dev_done);
+
+    ret = SpiDeviceRegister(&qspi_device0, (void *)(&qspi_device0.spi_param), QSPI_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("BoardSpiDevBend SpiDeviceRegister device %s error %d\n", QSPI_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    ret = SpiDeviceAttachToBus(QSPI_DEVICE_NAME_0, QSPI_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("BoardSpiDevBend SpiDeviceAttachToBus device %s error %d\n", QSPI_DEVICE_NAME_0, ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+static int BoardSpiBusInit(struct SpiBus *spi_bus, struct SpiDriver *spi_driver, const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the spi bus */
+    ret = SpiBusInit(spi_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the spi driver*/
+    ret = SpiDriverInit(spi_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the spi driver to the spi bus*/
+    ret = SpiDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+
+int HwQSpiInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct SpiBus qspi_bus;
+    memset(&qspi_bus, 0, sizeof(struct SpiBus));
+
+    static struct SpiDriver qspi_driver;
+    memset(&qspi_driver, 0, sizeof(struct SpiDriver));
+
+    qspi_bus.private_data = QSPI_UNIT;
+    qspi_driver.configure = QSpiDrvConfigure;
+
+    ret = BoardSpiBusInit(&qspi_bus, &qspi_driver, QSPI_BUS_NAME, QSPI_DRV_NAME);
+    if (EOK != ret) {
+        KPrintf("BoardSpiBusInit error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardQSpiDevBend();
+    if (EOK != ret) {
+        KPrintf("BoardSpiDevBend error ret %u\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+int FlashW25qxxSpiDeviceInit(void)
+{
+    HwQSpiInit();
+    QSpiSdkInit(NULL);
+    QspiPinConfig();
+    if (NONE == SpiFlashInit(QSPI_BUS_NAME, QSPI_DEVICE_NAME_0, QSPI_DRV_NAME, QSPI_FLASH_DEV_NAME)) {
+        return ERROR;
+    }
+    return EOK;
+}

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/connect_lora_spi.c

@@ -0,0 +1,457 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_lora_spi.c
+* @brief support to register spi lora pointer and function
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-10-31
+*/
+
+#include <connect_spi_lora.h>
+
+/* RST = PI02 */
+#define LORA_RST_PORT                     (GPIO_PORT_I)
+#define LORA_RST_PIN                      (GPIO_PIN_02)
+
+static struct HardwareDev *g_spi_lora_dev;
+static tRadioDriver *Radio = NONE;
+
+void SX1276InitIo(void)
+{
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinState = PIN_STAT_RST;
+    stcGpioInit.u16PinDir = PIN_DIR_OUT;
+    (void)GPIO_Init(LORA_RST_PORT, LORA_RST_PIN, &stcGpioInit);
+}
+
+inline void SX1276WriteRxTx(uint8_t txEnable)
+{
+    if (txEnable != 0) {
+        /*to do*/
+    } else {
+        /*to do*/
+    }
+}
+
+void SX1276SetReset(uint8_t state)
+{
+    if (state == RADIO_RESET_ON) {
+        GPIO_ResetPins(LORA_RST_PORT, LORA_RST_PIN);
+    } else {
+        stc_gpio_init_t stcGpioInit;
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDir = PIN_DIR_IN;
+        (void)GPIO_Init(LORA_RST_PORT, LORA_RST_PIN, &stcGpioInit);
+    }
+}
+
+//Not-necessary Function
+uint8_t SX1276ReadDio0(void)
+{
+    return 1;
+}
+
+uint8_t SX1276ReadDio1(void)
+{
+    return 1;
+}
+
+uint8_t SX1276ReadDio2(void)
+{
+    return 1;
+}
+
+uint8_t SX1276ReadDio3(void)
+{
+    return 1;
+}
+
+uint8_t SX1276ReadDio4(void)
+{
+    return 1;
+}
+
+uint8_t SX1276ReadDio5(void)
+{
+    return 1;
+}
+
+void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+    struct BusBlockWriteParam write_param;
+    uint8 write_addr = addr | 0x80;
+
+    BusDevOpen(g_spi_lora_dev);
+
+    write_param.buffer = (void *)&write_addr;
+    write_param.size = 1;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    write_param.buffer = (void *)buffer;
+    write_param.size = size;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    BusDevClose(g_spi_lora_dev);
+}
+
+void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+    struct BusBlockWriteParam write_param;
+    struct BusBlockReadParam read_param;
+
+    uint8 write_addr = addr & 0x7F;
+
+    BusDevOpen(g_spi_lora_dev);
+
+    write_param.buffer = (void *)&write_addr;
+    write_param.size = 1;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    read_param.buffer = (void *)buffer;
+    read_param.size = size;
+    BusDevReadData(g_spi_lora_dev, &read_param);
+
+    BusDevClose(g_spi_lora_dev);
+}
+
+void SX1276WriteFifo(uint8_t *buffer, uint8_t size)
+{
+    SX1276WriteBuffer(0, buffer, size);
+}
+
+void SX1276ReadFifo(uint8_t *buffer, uint8_t size)
+{
+    SX1276ReadBuffer(0, buffer, size);
+}
+
+void SX1276Write(uint8_t addr, uint8_t data)
+{
+    SX1276WriteBuffer(addr, &data, 1);
+}
+
+void SX1276Read(uint8_t addr, uint8_t *data)
+{
+    SX1276ReadBuffer(addr, data, 1);
+}
+
+uint8_t Sx1276SpiCheck(void)
+{
+    uint8_t test = 0;
+
+	tLoRaSettings settings;
+	SX1276Read(REG_LR_VERSION, &test);
+	KPrintf("version code of the chip is 0x%x\n", test);
+
+	settings.RFFrequency = SX1276LoRaGetRFFrequency();
+	KPrintf("SX1278 Lora parameters are :\nRFFrequency is %d\n", settings.RFFrequency);
+
+	settings.Power = SX1276LoRaGetRFPower();
+	KPrintf("RFPower is %d\n",settings.Power);
+
+    settings.SignalBw = SX1276LoRaGetSignalBandwidth();	  
+	KPrintf("SignalBw is %d\n",settings.SignalBw);
+
+	settings.SpreadingFactor = SX1276LoRaGetSpreadingFactor();
+	KPrintf("SpreadingFactor is %d\n",settings.SpreadingFactor);
+
+    /*SPI confirm*/
+    SX1276Write(REG_LR_HOPPERIOD, 0x91);  
+    SX1276Read(REG_LR_HOPPERIOD, &test);
+    if (test != 0x91) {
+        return 0;
+    }		
+    return test;
+}
+
+/**
+ * This function supports to write data to the lora.
+ *
+ * @param dev lora dev descriptor
+ * @param write_param lora dev write datacfg param
+ */
+static uint32 SpiLoraWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(write_param);
+
+    if (write_param->size > 256) {
+        KPrintf("SpiLoraWrite ERROR:The message is too long!\n");
+        return ERROR;
+    } else {
+        SX1276SetTx(write_param->buffer, write_param->size);    
+
+        KPrintf("SpiLoraWrite success!\n");
+    }
+
+    return EOK;
+}
+
+/**
+ * This function supports to read data from the lora.
+ *
+ * @param dev lora dev descriptor
+ * @param read_param lora dev read datacfg param
+ */
+static uint32 SpiLoraRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(read_param);
+
+    KPrintf("SpiLoraRead Ready!\n");
+
+    int ret = SX1276GetRx(read_param->buffer, (uint16 *)&read_param->read_length);
+
+    if (ret < 0) {
+        return 0;
+    }
+
+    return read_param->read_length;
+}
+
+static uint32 SpiLoraOpen(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    KPrintf("SpiLoraOpen start\n");
+
+    x_err_t ret = EOK;
+    static x_bool lora_init_status = RET_FALSE;
+
+    if (RET_TRUE == lora_init_status) {
+        return EOK;
+    }
+
+    struct HardwareDev *haldev = (struct HardwareDev *)dev;
+
+    struct SpiHardwareDevice *lora_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev);
+    NULL_PARAM_CHECK(lora_dev);
+
+    SpiLoraDeviceType spi_lora_dev = CONTAINER_OF(lora_dev, struct SpiLoraDevice, lora_dev);    
+    NULL_PARAM_CHECK(spi_lora_dev);
+
+    struct Driver *spi_drv = spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver;
+
+    struct BusConfigureInfo configure_info;
+    struct SpiMasterParam spi_master_param;
+    spi_master_param.spi_data_bit_width = 8;
+    spi_master_param.spi_work_mode = SPI_MODE_0 | SPI_MSB;
+
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&spi_master_param;
+    ret = BusDrvConfigure(spi_drv, &configure_info);
+    if (ret) {
+        KPrintf("spi drv OPE_CFG error drv %8p cfg %8p\n", spi_drv, &spi_master_param);
+        return ERROR;
+    }
+
+    configure_info.configure_cmd = OPE_INT;
+    ret = BusDrvConfigure(spi_drv, &configure_info);
+    if (ret) {
+        KPrintf("spi drv OPE_INT error drv %8p\n", spi_drv);
+        return ERROR;
+    }
+
+    SX1276Init();
+
+    if (0x91 != Sx1276SpiCheck()) {
+        KPrintf("LoRa check failed!\n!");
+    } else {
+        Radio = RadioDriverInit();
+        KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 256 characters\n");
+    }
+
+    lora_init_status = RET_TRUE;
+    
+    return ret;
+}
+
+static uint32 SpiLoraClose(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    return EOK;
+}
+
+static const struct LoraDevDone lora_done =
+{
+    .open = SpiLoraOpen,
+    .close = SpiLoraClose,
+    .write = SpiLoraWrite,
+    .read = SpiLoraRead,
+};
+
+/**
+ * This function supports to init spi_lora_dev
+ *
+ * @param bus_name spi bus name
+ * @param dev_name spi dev name
+ * @param drv_name spi drv name
+ * @param lora_name lora dev name
+ */
+SpiLoraDeviceType SpiLoraInit(char *bus_name, char *dev_name, char *drv_name, char *lora_name)
+{
+    NULL_PARAM_CHECK(dev_name);
+    NULL_PARAM_CHECK(drv_name);
+    NULL_PARAM_CHECK(lora_name);
+    NULL_PARAM_CHECK(bus_name);
+
+    x_err_t ret;
+    static HardwareDevType haldev;
+
+    haldev = SpiDeviceFind(dev_name, TYPE_SPI_DEV);
+    if (NONE == haldev) {
+        KPrintf("SpiLoraInit find spi haldev %s error! \n", dev_name);
+        return NONE;
+    }
+
+    SpiLoraDeviceType spi_lora_dev = (SpiLoraDeviceType)malloc(sizeof(struct SpiLoraDevice));
+    if (NONE == spi_lora_dev) {
+        KPrintf("SpiLoraInit malloc spi_lora_dev failed\n");
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    memset(spi_lora_dev, 0, sizeof(struct SpiLoraDevice));
+
+    spi_lora_dev->spi_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev);
+
+    spi_lora_dev->lora_dev.spi_dev_flag = RET_TRUE;
+    spi_lora_dev->lora_dev.haldev.dev_done = (struct HalDevDone *)&lora_done;
+
+    struct Driver *spi_driver = SpiDriverFind(drv_name, TYPE_SPI_DRV);
+    if (NONE == spi_driver) {
+        KPrintf("SpiLoraInit find spi driver %s error! \n", drv_name);
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    //spi drv get spi dev param (SpiDeviceParam)
+    spi_driver->private_data = spi_lora_dev->spi_dev->haldev.private_data;
+    spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver = spi_driver;
+
+    ret = SpiDeviceRegister(&spi_lora_dev->lora_dev, spi_lora_dev->spi_dev->haldev.private_data, lora_name);
+    if (EOK != ret) {
+        KPrintf("SpiLoraInit SpiDeviceRegister device %s error %d\n", lora_name, ret);
+        free(spi_lora_dev);   
+        return NONE;
+    }
+
+    ret = SpiDeviceAttachToBus(lora_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("SpiLoraInit SpiDeviceAttachToBus device %s error %d\n", lora_name, ret);
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    g_spi_lora_dev = &spi_lora_dev->spi_dev->haldev;
+
+    return spi_lora_dev;
+}
+
+/**
+ * This function supports to release spi_lora_dev
+ *
+ * @param spi_lora_dev spi lora descriptor
+ */
+uint32 SpiLoraRelease(SpiLoraDeviceType spi_lora_dev)
+{
+    NULL_PARAM_CHECK(spi_lora_dev);
+
+    x_err_t ret;
+
+    DeviceDeleteFromBus(spi_lora_dev->lora_dev.haldev.owner_bus, &spi_lora_dev->lora_dev.haldev);
+
+    free(spi_lora_dev);
+
+    return EOK;
+}
+
+int LoraSx12xxSpiDeviceInit(void)
+{
+#ifdef BSP_USING_SPI1
+    if (NONE == SpiLoraInit(SPI_BUS_NAME_1, SPI_1_DEVICE_NAME_0, SPI_1_DRV_NAME, SX12XX_DEVICE_NAME)) {
+        return ERROR;
+    }
+#endif
+
+    return EOK;
+}
+
+#define LORA_TEST
+#ifdef LORA_TEST
+/*Just for lora test*/
+static struct Bus *bus;
+static struct HardwareDev *dev;
+
+void LoraOpen(void)
+{
+    x_err_t ret = EOK;
+
+    bus = BusFind(SPI_BUS_NAME_1);
+    dev = BusFindDevice(bus, SX12XX_DEVICE_NAME);
+
+    ret = SpiLoraOpen(dev);
+    if (EOK != ret) {
+        KPrintf("LoRa init failed\n");
+        return;
+    }
+
+    KPrintf("LoRa init succeed\n");
+
+    return;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+                                                LoraOpen, LoraOpen, open lora device and read parameters );
+
+static void LoraReceive(void)
+{
+    uint32 read_length = 0;
+    struct BusBlockReadParam read_param;
+    memset(&read_param, 0, sizeof(struct BusBlockReadParam));
+
+    read_param.buffer = malloc(SPI_LORA_BUFFER_SIZE);
+
+    read_length = SpiLoraRead(dev, &read_param);
+
+    KPrintf("LoraReceive length %d\n", read_length);
+    for (int i = 0; i < read_length; i ++) {
+        KPrintf("i %d data 0x%x\n", i, ((uint8 *)read_param.buffer)[i]);
+    }
+
+    free(read_param.buffer);
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
+LoraReceive, LoraReceive,  lora wait message );
+
+static void LoraSend(int argc, char *argv[])
+{
+    char Msg[SPI_LORA_BUFFER_SIZE] = {0};
+    struct BusBlockWriteParam write_param;
+    memset(&write_param, 0, sizeof(struct BusBlockWriteParam));
+
+    if (argc == 2) {
+        strncpy(Msg, argv[1], SPI_LORA_BUFFER_SIZE);
+        write_param.buffer = Msg;
+        write_param.size = strlen(Msg);
+
+        KPrintf("LoraSend data %s length %d\n", Msg, strlen(Msg));
+
+        SpiLoraWrite(dev, &write_param);
+    }
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+LoraSend, LoraSend,  lora send message );
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/Makefile

@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_RESOURCES_SPI_LORA),y)
+	SRC_DIR := sx12xx
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/Makefile

@@ -0,0 +1,3 @@
+SRC_DIR := src
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/inc/spi_lora_sx12xx.h

@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file spi_lora_sx12xx.h
+* @brief define spi lora driver function
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-10-31
+*/
+
+#ifndef SPI_LORA_SX12XX_H
+#define SPI_LORA_SX12XX_H
+
+#include <connect_spi_lora.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint8_t SX1276ReadDio0(void);
+uint8_t SX1276ReadDio1(void);
+uint8_t SX1276ReadDio2(void);
+uint8_t SX1276ReadDio3(void);
+uint8_t SX1276ReadDio4(void);
+uint8_t SX1276ReadDio5(void);
+
+void SX1276Write(uint8_t addr, uint8_t data);
+void SX1276Read(uint8_t addr, uint8_t *data);
+void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+void SX1276WriteFifo(uint8_t *buffer, uint8_t size);
+void SX1276ReadFifo(uint8_t *buffer, uint8_t size);
+void SX1276SetReset(uint8_t state);
+uint8_t Sx1276SpiCheck(void);
+void SX1276WriteRxTx(uint8_t txEnable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/Makefile

@@ -0,0 +1,3 @@
+SRC_DIR := radio
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := radio.c sx1276-Fsk.c sx1276-FskMisc.c sx1276-LoRa.c sx1276-LoRaMisc.c sx1276.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/platform.h

@@ -0,0 +1,96 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       platform.h
+ * \brief        
+ *
+ * \version    1.0
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ */
+/*************************************************
+File name: platform.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+#ifndef __GNUC__
+#define inline
+#endif
+
+/*!
+ * Platform definition
+ */
+#define Bleeper                                     3
+#define SX1243ska                                   2
+#define SX12xxEiger                                 1
+#define SX12000DVK                                  0
+
+/*!
+ * Platform choice. Please uncoment the PLATFORM define and choose your platform
+ * or add/change the PLATFORM definition on the compiler Defines option
+ */
+#define PLATFORM                                    SX12xxEiger
+
+#if( PLATFORM == SX12xxEiger )
+/*!
+ * Radio choice. Please uncomment the wanted radio and comment the others
+ * or add/change wanted radio definition on the compiler Defines option
+ */
+//#define USE_SX1232_RADIO
+//#define USE_SX1272_RADIO
+#define USE_SX1276_RADIO
+//#define USE_SX1243_RADIO
+
+/*!
+ * Module choice. There are three existing module with the SX1276.
+ * Please set the connected module to the value 1 and set the others to 0
+ */
+#ifdef USE_SX1276_RADIO
+#define MODULE_SX1276RF1IAS                         0
+#define MODULE_SX1276RF1JAS                         0
+#define MODULE_SX1276RF1KAS                         1
+#endif
+
+#include <spi_lora_sx12xx.h>
+#define USE_UART                                0
+
+#elif( PLATFORM == SX12000DVK )
+/*!
+ * Radio choice. Please uncomment the wanted radio and comment the others
+ * or add/change wanted radio definition on the compiler Defines option
+ */
+//#define USE_SX1232_RADIO
+#define USE_SX1272_RADIO
+//#define USE_SX1276_RADIO
+//#define USE_SX1243_RADIO
+
+    #include "sx1200dvk/sx1200dvk.h"
+
+#elif( PLATFORM == SX1243ska )
+
+#elif( PLATFORM == Bleeper )
+    #define USE_SX1272_RADIO
+    
+    #include "bleeper/bleeper.h"
+    #define USE_UART                                0
+
+#else
+    #error "Missing define: Platform (ie. SX12xxEiger)"
+#endif
+
+#endif // __PLATFORM_H__

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/radio.c

@@ -0,0 +1,75 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       radio.c
+ * \brief      Generic radio driver ( radio abstraction )
+ *
+ * \version    2.0.0 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Gregory Cristian on Apr 25 2013
+ */
+/*************************************************
+File name: radio.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#include <stdint.h>
+#include "platform.h"
+#include "radio.h"
+
+#if defined( USE_SX1232_RADIO )
+    #include "sx1232.h"
+#elif defined( USE_SX1272_RADIO )
+    #include "sx1272.h"
+#elif defined( USE_SX1276_RADIO )
+    #include "sx1276.h"
+#else
+    #error "Missing define: USE_XXXXXX_RADIO (ie. USE_SX1272_RADIO)"
+#endif    
+
+tRadioDriver RadioDriver;
+
+tRadioDriver* RadioDriverInit( void )
+{
+#if defined( USE_SX1232_RADIO )
+    RadioDriver.Init = SX1232Init;
+    RadioDriver.Reset = SX1232Reset;
+    RadioDriver.StartRx = SX1232StartRx;
+    RadioDriver.GetRxPacket = SX1232GetRxPacket;
+    RadioDriver.SetTxPacket = SX1232SetTxPacket;
+    RadioDriver.Process = SX1232Process;
+#elif defined( USE_SX1272_RADIO )
+    RadioDriver.Init = SX1272Init;
+    RadioDriver.Reset = SX1272Reset;
+    RadioDriver.StartRx = SX1272StartRx;
+    RadioDriver.GetRxPacket = SX1272GetRxPacket;
+    RadioDriver.SetTxPacket = SX1272SetTxPacket;
+    RadioDriver.Process = SX1272Process;
+#elif defined( USE_SX1276_RADIO )
+    RadioDriver.Init = SX1276Init;
+    RadioDriver.Reset = SX1276Reset;
+    RadioDriver.StartRx = SX1276StartRx;
+    RadioDriver.GetRxPacket = SX1276GetRxPacket;
+    RadioDriver.SetTxPacket = SX1276SetTxPacket;
+    RadioDriver.Process = SX1276Process;
+    RadioDriver.ChannelEmpty = SX1276ChannelEmpty;
+#else
+    #error "Missing define: USE_XXXXXX_RADIO (ie. USE_SX1272_RADIO)"
+#endif    
+
+    return &RadioDriver;
+}

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/radio.h

@@ -0,0 +1,77 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       radio.h
+ * \brief      Generic radio driver ( radio abstraction )
+ *
+ * \version    2.0.B2 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Gregory Cristian on Apr 25 2013
+ */
+/*************************************************
+File name: radio.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __RADIO_H__
+#define __RADIO_H__
+
+/*!
+ * SX1272 and SX1276 General parameters definition
+ */
+#define LORA                                        1         // [0: OFF, 1: ON]
+
+/*!
+ * RF process function return codes
+ */
+typedef enum
+{
+    RF_IDLE,
+    RF_BUSY,
+    RF_RX_DONE,
+    RF_RX_TIMEOUT,
+    RF_TX_DONE,
+    RF_TX_TIMEOUT,
+    RF_LEN_ERROR,
+    RF_CHANNEL_EMPTY,
+    RF_CHANNEL_ACTIVITY_DETECTED,
+}tRFProcessReturnCodes;
+
+/*!
+ * Radio driver structure defining the different function pointers
+ */
+typedef struct sRadioDriver
+{
+    void ( *Init )( void );
+    void ( *Reset )( void );
+    void ( *StartRx )( void );
+    void ( *GetRxPacket )( void *buffer, uint16_t *size );
+    void ( *SetTxPacket )( const void *buffer, uint16_t size );
+    uint32_t ( *Process )( void );
+    uint32_t ( *ChannelEmpty )(void );
+}tRadioDriver;
+
+/*!
+ * \brief Initializes the RadioDriver structure with specific radio
+ *        functions.
+ *
+ * \retval radioDriver Pointer to the radio driver variable
+ */
+tRadioDriver* RadioDriverInit( void );
+
+#endif // __RADIO_H__

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-Fsk.c

@@ -0,0 +1,616 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276.c
+ * \brief      SX1276 RF chip driver
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-Fsk.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include <string.h>
+#include <math.h>
+
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+
+#include "radio.h"
+
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+
+#include "sx1276-FskMisc.h"
+#include "sx1276-Fsk.h"
+
+// Default settings
+tFskSettings FskSettings = 
+{
+    870000000,      // RFFrequency
+    9600,           // Bitrate
+    50000,          // Fdev
+    20,             // Power
+    100000,         // RxBw
+    150000,         // RxBwAfc
+    true,           // CrcOn
+    true,           // AfcOn    
+    255             // PayloadLength (set payload size to the maximum for variable mode, else set the exact payload length)
+};
+
+/*!
+ * SX1276 FSK registers variable
+ */
+tSX1276* SX1276;
+
+/*!
+ * Local RF buffer for communication support
+ */
+static uint8_t RFBuffer[RF_BUFFER_SIZE];
+
+/*!
+ * Chunk size of data write in buffer 
+ */
+static uint8_t DataChunkSize = 32;
+
+
+/*!
+ * RF state machine variable
+ */
+static uint8_t RFState = RF_STATE_IDLE;
+
+/*!
+ * Rx management support variables
+ */
+
+/*!
+ * PacketTimeout holds the RF packet timeout
+ * SyncSize = [0..8]
+ * VariableSize = [0;1]
+ * AddressSize = [0;1]
+ * PayloadSize = [0..RF_BUFFER_SIZE]
+ * CrcSize = [0;2]
+ * PacketTimeout = ( ( 8 * ( VariableSize + AddressSize + PayloadSize + CrcSize ) / BR ) * 1000.0 ) + 1
+ * Computed timeout is in miliseconds
+ */
+static uint32_t PacketTimeout;
+
+/*!
+ * Preamble2SyncTimeout
+ * Preamble2SyncTimeout = ( ( 8 * ( PremableSize + SyncSize ) / RFBitrate ) * 1000.0 ) + 1
+ * Computed timeout is in miliseconds
+ */
+static uint32_t Preamble2SyncTimeout;
+
+static bool PreambleDetected = false;
+static bool SyncWordDetected = false;
+static bool PacketDetected = false;
+static uint16_t RxPacketSize = 0;
+static uint8_t RxBytesRead = 0;
+static uint8_t TxBytesSent = 0;
+static double RxPacketRssiValue;
+static uint32_t RxPacketAfcValue;
+static uint8_t RxGain = 1;
+static uint32_t RxTimeoutTimer = 0;
+static uint32_t Preamble2SyncTimer = 0;
+
+/*!
+ * Tx management support variables
+ */
+static uint16_t TxPacketSize = 0;
+static uint32_t TxTimeoutTimer = 0;
+
+void SX1276FskInit( void )
+{
+    RFState = RF_STATE_IDLE;
+
+    SX1276FskSetDefaults( );
+    
+    SX1276ReadBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 );
+
+    // Set the device in FSK mode and Sleep Mode
+    SX1276->RegOpMode = RF_OPMODE_MODULATIONTYPE_FSK | RF_OPMODE_SLEEP;
+    SX1276Write( REG_OPMODE, SX1276->RegOpMode );
+
+    SX1276->RegPaRamp = RF_PARAMP_MODULATIONSHAPING_01;
+    SX1276Write( REG_PARAMP, SX1276->RegPaRamp );
+
+    SX1276->RegLna = RF_LNA_GAIN_G1;
+    SX1276Write( REG_LNA, SX1276->RegLna );
+
+    if( FskSettings.AfcOn == true )
+    {
+        SX1276->RegRxConfig = RF_RXCONFIG_RESTARTRXONCOLLISION_OFF | RF_RXCONFIG_AFCAUTO_ON |
+                              RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT;
+    }
+    else
+    {
+        SX1276->RegRxConfig = RF_RXCONFIG_RESTARTRXONCOLLISION_OFF | RF_RXCONFIG_AFCAUTO_OFF |
+                              RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT;
+    }
+
+    SX1276->RegPreambleLsb = 8;
+    
+    SX1276->RegPreambleDetect = RF_PREAMBLEDETECT_DETECTOR_ON | RF_PREAMBLEDETECT_DETECTORSIZE_2 |
+                                RF_PREAMBLEDETECT_DETECTORTOL_10;
+
+    SX1276->RegRssiThresh = 0xFF;
+
+    SX1276->RegSyncConfig = RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON | RF_SYNCCONFIG_PREAMBLEPOLARITY_AA |
+                            RF_SYNCCONFIG_SYNC_ON |
+                            RF_SYNCCONFIG_SYNCSIZE_4;
+
+    SX1276->RegSyncValue1 = 0x69;
+    SX1276->RegSyncValue2 = 0x81;
+    SX1276->RegSyncValue3 = 0x7E;
+    SX1276->RegSyncValue4 = 0x96;
+
+    SX1276->RegPacketConfig1 = RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE | RF_PACKETCONFIG1_DCFREE_OFF |
+                               ( FskSettings.CrcOn << 4 ) | RF_PACKETCONFIG1_CRCAUTOCLEAR_ON |
+                               RF_PACKETCONFIG1_ADDRSFILTERING_OFF | RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT;
+    SX1276FskGetPacketCrcOn( ); // Update CrcOn on FskSettings
+
+    SX1276->RegPayloadLength = FskSettings.PayloadLength;
+
+    // we can now update the registers with our configuration
+    SX1276WriteBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 );
+
+    // then we need to set the RF settings 
+    SX1276FskSetRFFrequency( FskSettings.RFFrequency );
+    SX1276FskSetBitrate( FskSettings.Bitrate );
+    SX1276FskSetFdev( FskSettings.Fdev );
+
+    SX1276FskSetDccBw( &SX1276->RegRxBw, 0, FskSettings.RxBw );
+    SX1276FskSetDccBw( &SX1276->RegAfcBw, 0, FskSettings.RxBwAfc );
+    SX1276FskSetRssiOffset( 0 );
+
+#if( ( MODULE_SX1276RF1IAS == 1 ) || ( MODULE_SX1276RF1KAS == 1 ) )
+    if( FskSettings.RFFrequency > 860000000 )
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_RFO );
+        SX1276FskSetPa20dBm( false );
+        FskSettings.Power = 14;
+        SX1276FskSetRFPower( FskSettings.Power );
+    }
+    else
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_PABOOST );
+        SX1276FskSetPa20dBm( true );
+        FskSettings.Power = 20;
+        SX1276FskSetRFPower( FskSettings.Power );
+    } 
+#elif( MODULE_SX1276RF1JAS == 1 )
+    if( FskSettings.RFFrequency > 860000000 )
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_PABOOST );
+        SX1276FskSetPa20dBm( true );
+        FskSettings.Power = 20;
+        SX1276FskSetRFPower( FskSettings.Power );
+    }
+    else
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_RFO );
+        SX1276FskSetPa20dBm( false );
+        FskSettings.Power = 14;
+        SX1276FskSetRFPower( FskSettings.Power );
+    } 
+#endif
+
+    SX1276FskSetOpMode( RF_OPMODE_STANDBY );
+
+    // Calibrate the HF
+    SX1276FskRxCalibrate( );
+}
+
+void SX1276FskSetDefaults( void )
+{
+    // REMARK: See SX1276 datasheet for modified default values.
+
+    SX1276Read( REG_VERSION, &SX1276->RegVersion );
+}
+
+void SX1276FskSetOpMode( uint8_t opMode )
+{
+    static uint8_t opModePrev = RF_OPMODE_STANDBY;
+    static bool antennaSwitchTxOnPrev = true;
+    bool antennaSwitchTxOn = false;
+
+    opModePrev = SX1276->RegOpMode & ~RF_OPMODE_MASK;
+
+    if( opMode != opModePrev )
+    {
+        if( opMode == RF_OPMODE_TRANSMITTER )
+        {
+            antennaSwitchTxOn = true;
+        }
+        else
+        {
+            antennaSwitchTxOn = false;
+        }
+        if( antennaSwitchTxOn != antennaSwitchTxOnPrev )
+        {
+            antennaSwitchTxOnPrev = antennaSwitchTxOn;
+            RXTX( antennaSwitchTxOn ); // Antenna switch control
+        }
+        SX1276->RegOpMode = ( SX1276->RegOpMode & RF_OPMODE_MASK ) | opMode;
+
+        SX1276Write( REG_OPMODE, SX1276->RegOpMode );        
+    }
+}
+
+uint8_t SX1276FskGetOpMode( void )
+{
+    SX1276Read( REG_OPMODE, &SX1276->RegOpMode );
+    
+    return SX1276->RegOpMode & ~RF_OPMODE_MASK;
+}
+
+int32_t SX1276FskReadFei( void )
+{
+    SX1276ReadBuffer( REG_FEIMSB, &SX1276->RegFeiMsb, 2 );                          // Reads the FEI value
+
+    return ( int32_t )( double )( ( ( uint16_t )SX1276->RegFeiMsb << 8 ) | ( uint16_t )SX1276->RegFeiLsb ) * ( double )FREQ_STEP;
+}
+
+int32_t SX1276FskReadAfc( void )
+{
+    SX1276ReadBuffer( REG_AFCMSB, &SX1276->RegAfcMsb, 2 );                            // Reads the AFC value
+    return ( int32_t )( double )( ( ( uint16_t )SX1276->RegAfcMsb << 8 ) | ( uint16_t )SX1276->RegAfcLsb ) * ( double )FREQ_STEP;
+}
+
+uint8_t SX1276FskReadRxGain( void )
+{
+    SX1276Read( REG_LNA, &SX1276->RegLna );
+    return( SX1276->RegLna >> 5 ) & 0x07;
+}
+
+double SX1276FskReadRssi( void )
+{
+    SX1276Read( REG_RSSIVALUE, &SX1276->RegRssiValue );                               // Reads the RSSI value
+
+    return -( double )( ( double )SX1276->RegRssiValue / 2.0 );
+}
+
+uint8_t SX1276FskGetPacketRxGain( void )
+{
+    return RxGain;
+}
+
+double SX1276FskGetPacketRssi( void )
+{
+    return RxPacketRssiValue;
+}
+
+uint32_t SX1276FskGetPacketAfc( void )
+{
+    return RxPacketAfcValue;
+}
+
+void SX1276FskStartRx( void )
+{
+    SX1276FskSetRFState( RF_STATE_RX_INIT );
+}
+
+void SX1276FskGetRxPacket( void *buffer, uint16_t *size )
+{
+    *size = RxPacketSize;
+    RxPacketSize = 0;
+    memcpy( ( void * )buffer, ( void * )RFBuffer, ( size_t )*size );
+}
+
+void SX1276FskSetTxPacket( const void *buffer, uint16_t size )
+{
+    TxPacketSize = size;
+    memcpy( ( void * )RFBuffer, buffer, ( size_t )TxPacketSize ); 
+
+    RFState = RF_STATE_TX_INIT;
+}
+
+// Remark: SX1276 must be fully initialized before calling this function
+uint16_t SX1276FskGetPacketPayloadSize( void )
+{
+    uint16_t syncSize;
+    uint16_t variableSize;
+    uint16_t addressSize;
+    uint16_t payloadSize;
+    uint16_t crcSize;
+
+    syncSize = ( SX1276->RegSyncConfig & 0x07 ) + 1;
+    variableSize = ( ( SX1276->RegPacketConfig1 & 0x80 ) == 0x80 ) ? 1 : 0;
+    addressSize = ( ( SX1276->RegPacketConfig1 & 0x06 ) != 0x00 ) ? 1 : 0;
+    payloadSize = SX1276->RegPayloadLength;
+    crcSize = ( ( SX1276->RegPacketConfig1 & 0x10 ) == 0x10 ) ? 2 : 0;
+    
+    return syncSize + variableSize + addressSize + payloadSize + crcSize;
+}
+
+// Remark: SX1276 must be fully initialized before calling this function
+uint16_t SX1276FskGetPacketHeaderSize( void )
+{
+    uint16_t preambleSize;
+    uint16_t syncSize;
+
+    preambleSize = ( ( uint16_t )SX1276->RegPreambleMsb << 8 ) | ( uint16_t )SX1276->RegPreambleLsb;
+    syncSize = ( SX1276->RegSyncConfig & 0x07 ) + 1;
+    
+    return preambleSize + syncSize;
+}
+
+uint8_t SX1276FskGetRFState( void )
+{
+    return RFState;
+}
+
+void SX1276FskSetRFState( uint8_t state )
+{
+    RFState = state;
+}
+
+uint32_t SX1276FskProcess( void )
+{
+    uint32_t result = RF_BUSY;
+
+    switch( RFState )
+    {
+    case RF_STATE_IDLE:
+        break;
+    // Rx management
+    case RF_STATE_RX_INIT:
+        // DIO mapping setup
+        if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_ON ) == RF_PACKETCONFIG1_CRC_ON )
+        {
+            //                           CrcOk,                   FifoLevel,               SyncAddr,               FifoEmpty
+            SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_01 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 | RF_DIOMAPPING1_DIO3_00;
+        }
+        else
+        {
+            //                           PayloadReady,            FifoLevel,               SyncAddr,               FifoEmpty
+            SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_00 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 | RF_DIOMAPPING1_DIO3_00;
+        }
+        //                          Preamble,                   Data
+        SX1276->RegDioMapping2 = RF_DIOMAPPING2_DIO4_11 | RF_DIOMAPPING2_DIO5_10 | RF_DIOMAPPING2_MAP_PREAMBLEDETECT;
+        SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 );
+
+        SX1276FskSetOpMode( RF_OPMODE_RECEIVER );
+    
+        memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE );
+
+        PacketTimeout = ( uint16_t )( round( ( 8.0 * ( ( double )SX1276FskGetPacketPayloadSize( ) ) / ( double )FskSettings.Bitrate ) * 1000.0 ) + 1.0 );
+        PacketTimeout = PacketTimeout + ( PacketTimeout >> 1 ); // Set the Packet timeout as 1.5 times the full payload transmission time
+
+        Preamble2SyncTimeout = PacketTimeout;
+
+        Preamble2SyncTimer = RxTimeoutTimer = GET_TICK_COUNT( );
+
+        SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | 0x20; // 32 bytes of data
+        SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh );
+
+        PreambleDetected = false;
+        SyncWordDetected = false;
+        PacketDetected = false;
+        RxBytesRead = 0;
+        RxPacketSize = 0;
+        RFState = RF_STATE_RX_SYNC;
+        break;
+    case RF_STATE_RX_SYNC:
+        if( ( DIO4 == 1 ) && ( PreambleDetected == false ) )// Preamble
+        {
+            PreambleDetected = true;
+            Preamble2SyncTimer = GET_TICK_COUNT( );
+        }
+        if( ( DIO2 == 1 ) && ( PreambleDetected == true ) && ( SyncWordDetected == false ) ) // SyncAddr
+        {
+            SyncWordDetected = true;
+        
+            RxPacketRssiValue = SX1276FskReadRssi( );
+
+            RxPacketAfcValue = SX1276FskReadAfc( );
+            RxGain = SX1276FskReadRxGain( );
+        
+            Preamble2SyncTimer = RxTimeoutTimer = GET_TICK_COUNT( );
+
+            RFState = RF_STATE_RX_RUNNING;
+        }
+
+        // Preamble 2 SyncAddr timeout
+        if( ( SyncWordDetected == false ) && ( PreambleDetected == true ) && ( ( GET_TICK_COUNT( ) - Preamble2SyncTimer ) > Preamble2SyncTimeout ) )
+        {
+            RFState = RF_STATE_RX_INIT;
+            SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK );
+        }
+        if( ( SyncWordDetected == false ) &&
+            ( PreambleDetected == false ) &&
+            ( PacketDetected == false ) &&
+            ( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) )
+        {
+            RFState = RF_STATE_RX_TIMEOUT;
+        }
+        break;
+    case RF_STATE_RX_RUNNING:
+        if( RxPacketSize > RF_BUFFER_SIZE_MAX )
+        {
+            RFState = RF_STATE_RX_LEN_ERROR;
+            break;
+        }
+#if 1
+        if( DIO1 == 1 ) // FifoLevel
+        {
+            if( ( RxPacketSize == 0 ) && ( RxBytesRead == 0 ) ) // Read received packet size
+            {
+                if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE )
+                {
+                    SX1276ReadFifo( ( uint8_t* )&RxPacketSize, 1 );
+                }
+                else
+                {
+                    RxPacketSize = SX1276->RegPayloadLength;
+                }
+            }
+
+            if( ( RxPacketSize - RxBytesRead ) > ( SX1276->RegFifoThresh & 0x3F ) )
+            {
+                SX1276ReadFifo( ( RFBuffer + RxBytesRead ), ( SX1276->RegFifoThresh & 0x3F ) );
+                RxBytesRead += ( SX1276->RegFifoThresh & 0x3F );
+            }
+            else
+            {
+                SX1276ReadFifo( ( RFBuffer + RxBytesRead ), RxPacketSize - RxBytesRead );
+                RxBytesRead += ( RxPacketSize - RxBytesRead );
+            }
+        }
+#endif
+        if( DIO0 == 1 ) // PayloadReady/CrcOk
+        {
+            RxTimeoutTimer = GET_TICK_COUNT( );
+            if( ( RxPacketSize == 0 ) && ( RxBytesRead == 0 ) ) // Read received packet size
+            {
+                if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE )
+                {
+                    SX1276ReadFifo( ( uint8_t* )&RxPacketSize, 1 );
+                }
+                else
+                {
+                    RxPacketSize = SX1276->RegPayloadLength;
+                }
+                SX1276ReadFifo( RFBuffer + RxBytesRead, RxPacketSize - RxBytesRead );
+                RxBytesRead += ( RxPacketSize - RxBytesRead );
+                PacketDetected = true;
+                RFState = RF_STATE_RX_DONE;
+            }
+            else
+            {
+                SX1276ReadFifo( RFBuffer + RxBytesRead, RxPacketSize - RxBytesRead );
+                RxBytesRead += ( RxPacketSize - RxBytesRead );
+                PacketDetected = true;
+                RFState = RF_STATE_RX_DONE;
+            }
+        }
+        
+        // Packet timeout
+        if( ( PacketDetected == false ) && ( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) )
+        {
+            RFState = RF_STATE_RX_TIMEOUT;
+        }
+        break;
+    case RF_STATE_RX_DONE:
+        RxBytesRead = 0;
+        RFState = RF_STATE_RX_INIT;
+        result = RF_RX_DONE;
+        break;
+    case RF_STATE_RX_TIMEOUT:
+        RxBytesRead = 0;
+        RxPacketSize = 0;
+        SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK );
+        RFState = RF_STATE_RX_INIT;
+        result = RF_RX_TIMEOUT;
+        break;
+    case RF_STATE_RX_LEN_ERROR:
+        RxBytesRead = 0;
+        RxPacketSize = 0;
+        SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK );
+        RFState = RF_STATE_RX_INIT;
+        result = RF_LEN_ERROR;
+        break;
+    // Tx management
+    case RF_STATE_TX_INIT:
+        // Packet DIO mapping setup
+        //                           PacketSent,               FifoLevel,              FifoFull,               TxReady
+        SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_00 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_00 | RF_DIOMAPPING1_DIO3_01;
+        //                           LowBat,                   Data
+        SX1276->RegDioMapping2 = RF_DIOMAPPING2_DIO4_00 | RF_DIOMAPPING2_DIO5_10;
+        SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 );
+
+        SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | 0x18; // 24 bytes of data
+        SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh );
+
+        SX1276FskSetOpMode( RF_OPMODE_TRANSMITTER );
+        RFState = RF_STATE_TX_READY_WAIT;
+        TxBytesSent = 0;
+        break;
+    case RF_STATE_TX_READY_WAIT:
+        if( DIO3 == 1 )    // TxReady
+        {
+            if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE )
+            {
+                SX1276WriteFifo( ( uint8_t* )&TxPacketSize, 1 );
+            }
+            
+            if( ( TxPacketSize > 0 ) && ( TxPacketSize <= 64 ) )
+            {
+                DataChunkSize = TxPacketSize;
+            }
+            else
+            {
+                DataChunkSize = 32;
+            }
+            
+            SX1276WriteFifo( RFBuffer, DataChunkSize );
+            TxBytesSent += DataChunkSize;
+            TxTimeoutTimer = GET_TICK_COUNT( );
+            RFState = RF_STATE_TX_RUNNING;
+        }
+        break;
+
+    case RF_STATE_TX_RUNNING:
+        if( DIO1 == 0 )    // FifoLevel below thresold
+        {  
+            if( ( TxPacketSize - TxBytesSent ) > DataChunkSize )
+            {
+                SX1276WriteFifo( ( RFBuffer + TxBytesSent ), DataChunkSize );
+                TxBytesSent += DataChunkSize;
+            }
+            else 
+            {
+                // we write the last chunk of data
+                SX1276WriteFifo( RFBuffer + TxBytesSent, TxPacketSize - TxBytesSent );
+                TxBytesSent += TxPacketSize - TxBytesSent;
+            }
+        }
+
+        if( DIO0 == 1 ) // PacketSent
+        {
+            TxTimeoutTimer = GET_TICK_COUNT( );
+            RFState = RF_STATE_TX_DONE;
+            SX1276FskSetOpMode( RF_OPMODE_STANDBY );
+        }
+         
+        // Packet timeout
+        if( ( GET_TICK_COUNT( ) - TxTimeoutTimer ) > TICK_RATE_MS( 1000 ) )
+        {
+            RFState = RF_STATE_TX_TIMEOUT;
+        }
+        break;
+    case RF_STATE_TX_DONE:
+        RFState = RF_STATE_IDLE;
+        result = RF_TX_DONE;
+        break;
+    case RF_STATE_TX_TIMEOUT:
+        RFState = RF_STATE_IDLE;
+        result = RF_TX_TIMEOUT;
+        break;
+    default:
+        break;
+    }
+    return result;
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-FskMisc.c

@@ -0,0 +1,532 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-FskMisc.c
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-FskMisc.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include <math.h>
+
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+
+#include "sx1276-Fsk.h"
+#include "sx1276-FskMisc.h"
+
+extern tFskSettings FskSettings;
+
+void SX1276FskSetRFFrequency( uint32_t freq )
+{
+    FskSettings.RFFrequency = freq;
+
+    freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
+    SX1276->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF );
+    SX1276->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF );
+    SX1276->RegFrfLsb = ( uint8_t )( freq & 0xFF );
+    SX1276WriteBuffer( REG_FRFMSB, &SX1276->RegFrfMsb, 3 );
+}
+
+uint32_t SX1276FskGetRFFrequency( void )
+{
+    SX1276ReadBuffer( REG_FRFMSB, &SX1276->RegFrfMsb, 3 );
+    FskSettings.RFFrequency = ( ( uint32_t )SX1276->RegFrfMsb << 16 ) | ( ( uint32_t )SX1276->RegFrfMid << 8 ) | ( ( uint32_t )SX1276->RegFrfLsb );
+    FskSettings.RFFrequency = ( uint32_t )( ( double )FskSettings.RFFrequency * ( double )FREQ_STEP );
+
+    return FskSettings.RFFrequency;
+}
+
+void SX1276FskRxCalibrate( void )
+{
+    // the function RadioRxCalibrate is called just after the reset so all register are at their default values
+    uint8_t regPaConfigInitVal;
+    uint32_t initialFreq;
+
+    // save register values;
+    SX1276Read( REG_PACONFIG, &regPaConfigInitVal );
+    initialFreq = SX1276FskGetRFFrequency( );
+
+    // Cut the PA just in case
+    SX1276->RegPaConfig = 0x00; // RFO output, power = -1 dBm
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+
+    // Set Frequency in HF band
+    SX1276FskSetRFFrequency( 860000000 );
+
+    // Rx chain re-calibration workaround
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );    
+    SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START;
+    SX1276Write( REG_IMAGECAL, SX1276->RegImageCal );
+
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    // rx_cal_run goes low when calibration in finished
+    while( ( SX1276->RegImageCal & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
+    {
+        SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    }
+
+    // reload saved values into the registers
+    SX1276->RegPaConfig = regPaConfigInitVal;
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+
+    SX1276FskSetRFFrequency( initialFreq );
+
+}
+
+void SX1276FskSetBitrate( uint32_t bitrate )
+{
+    FskSettings.Bitrate = bitrate;
+    
+    bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )bitrate );
+    SX1276->RegBitrateMsb    = ( uint8_t )( bitrate >> 8 );
+    SX1276->RegBitrateLsb    = ( uint8_t )( bitrate & 0xFF );
+    SX1276WriteBuffer( REG_BITRATEMSB, &SX1276->RegBitrateMsb, 2 );    
+}
+
+uint32_t SX1276FskGetBitrate( void )
+{
+    SX1276ReadBuffer( REG_BITRATEMSB, &SX1276->RegBitrateMsb, 2 );
+    FskSettings.Bitrate = ( ( ( uint32_t )SX1276->RegBitrateMsb << 8 ) | ( ( uint32_t )SX1276->RegBitrateLsb ) );
+    FskSettings.Bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )FskSettings.Bitrate );
+
+    return FskSettings.Bitrate;
+}
+
+void SX1276FskSetFdev( uint32_t fdev )
+{
+    FskSettings.Fdev = fdev;
+
+    SX1276Read( REG_FDEVMSB, &SX1276->RegFdevMsb ); 
+
+    fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
+    SX1276->RegFdevMsb    = ( ( SX1276->RegFdevMsb & RF_FDEVMSB_FDEV_MASK ) | ( ( ( uint8_t )( fdev >> 8 ) ) & ~RF_FDEVMSB_FDEV_MASK ) );
+    SX1276->RegFdevLsb    = ( uint8_t )( fdev & 0xFF );
+    SX1276WriteBuffer( REG_FDEVMSB, &SX1276->RegFdevMsb, 2 );    
+}
+
+uint32_t SX1276FskGetFdev( void )
+{
+    SX1276ReadBuffer( REG_FDEVMSB, &SX1276->RegFdevMsb, 2 );
+    FskSettings.Fdev = ( ( ( uint32_t )( ( SX1276->RegFdevMsb << 8 ) & ~RF_FDEVMSB_FDEV_MASK ) ) | ( ( uint32_t )SX1276->RegFdevLsb ) );
+    FskSettings.Fdev = ( uint16_t )( ( double )FskSettings.Fdev * ( double )FREQ_STEP );
+
+    return FskSettings.Fdev;
+}
+
+void SX1276FskSetRFPower( int8_t power )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+    
+    if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276->RegPaDac & 0x87 ) == 0x87 )
+        {
+            if( power < 5 )
+            {
+                power = 5;
+            }
+            if( power > 20 )
+            {
+                power = 20;
+            }
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
+        }
+        else
+        {
+            if( power < 2 )
+            {
+                power = 2;
+            }
+            if( power > 17 )
+            {
+                power = 17;
+            }
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
+        }
+    }
+    else
+    {
+        if( power < -1 )
+        {
+            power = -1;
+        }
+        if( power > 14 )
+        {
+            power = 14;
+        }
+        SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
+        SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
+    }
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+    FskSettings.Power = power;
+}
+
+int8_t SX1276FskGetRFPower( void )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+
+    if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276->RegPaDac & 0x07 ) == 0x07 )
+        {
+            FskSettings.Power = 5 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK );
+        }
+        else
+        {
+            FskSettings.Power = 2 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK );
+        }
+    }
+    else
+    {
+        FskSettings.Power = -1 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK );
+    }
+    return FskSettings.Power;
+}
+
+/*!
+ * \brief Computes the Rx bandwidth with the mantisse and exponent
+ *
+ * \param [IN] mantisse Mantisse of the bandwidth value
+ * \param [IN] exponent Exponent of the bandwidth value
+ * \retval bandwidth Computed bandwidth
+ */
+static uint32_t SX1276FskComputeRxBw( uint8_t mantisse, uint8_t exponent )
+{
+    // rxBw
+    if( ( SX1276->RegOpMode & RF_OPMODE_MODULATIONTYPE_FSK ) == RF_OPMODE_MODULATIONTYPE_FSK )
+    {
+        return ( uint32_t )( ( double )XTAL_FREQ / ( mantisse * ( double )pow( 2, exponent + 2 ) ) );
+    }
+    else
+    {
+        return ( uint32_t )( ( double )XTAL_FREQ / ( mantisse * ( double )pow( 2, exponent + 3 ) ) );
+    }
+}
+
+/*!
+ * \brief Computes the mantisse and exponent from the bandwitdh value
+ *
+ * \param [IN] rxBwValue Bandwidth value
+ * \param [OUT] mantisse Mantisse of the bandwidth value
+ * \param [OUT] exponent Exponent of the bandwidth value
+ */
+static void SX1276FskComputeRxBwMantExp( uint32_t rxBwValue, uint8_t* mantisse, uint8_t* exponent )
+{
+    uint8_t tmpExp = 0;
+    uint8_t tmpMant = 0;
+
+    double tmpRxBw = 0;
+    double rxBwMin = 10e6;
+
+    for( tmpExp = 0; tmpExp < 8; tmpExp++ )
+    {
+        for( tmpMant = 16; tmpMant <= 24; tmpMant += 4 )
+        {
+            if( ( SX1276->RegOpMode & RF_OPMODE_MODULATIONTYPE_FSK ) == RF_OPMODE_MODULATIONTYPE_FSK )
+            {
+                tmpRxBw = ( double )XTAL_FREQ / ( tmpMant * ( double )pow( 2, tmpExp + 2 ) );
+            }
+            else
+            {
+                tmpRxBw = ( double )XTAL_FREQ / ( tmpMant * ( double )pow( 2, tmpExp + 3 ) );
+            }
+            if( fabs( tmpRxBw - rxBwValue ) < rxBwMin )
+            {
+                rxBwMin = fabs( tmpRxBw - rxBwValue );
+                *mantisse = tmpMant;
+                *exponent = tmpExp;
+            }
+        }
+    }
+}
+
+void SX1276FskSetDccBw( uint8_t* reg, uint32_t dccValue, uint32_t rxBwValue )
+{
+    uint8_t mantisse = 0;
+    uint8_t exponent = 0;
+    
+    if( reg == &SX1276->RegRxBw )
+    {
+        *reg = ( uint8_t )dccValue & 0x60;
+    }
+    else
+    {
+        *reg = 0;
+    }
+
+    SX1276FskComputeRxBwMantExp( rxBwValue, &mantisse, &exponent );
+
+    switch( mantisse )
+    {
+        case 16:
+            *reg |= ( uint8_t )( 0x00 | ( exponent & 0x07 ) );
+            break;
+        case 20:
+            *reg |= ( uint8_t )( 0x08 | ( exponent & 0x07 ) );
+            break;
+        case 24:
+            *reg |= ( uint8_t )( 0x10 | ( exponent & 0x07 ) );
+            break;
+        default:
+            // Something went terribely wrong
+            break;
+    }
+
+    if( reg == &SX1276->RegRxBw )
+    {
+        SX1276Write( REG_RXBW, *reg );
+        FskSettings.RxBw = rxBwValue;
+    }
+    else
+    {
+        SX1276Write( REG_AFCBW, *reg );
+        FskSettings.RxBwAfc = rxBwValue;
+    }
+}
+
+uint32_t SX1276FskGetBw( uint8_t* reg )
+{
+    uint32_t rxBwValue = 0;
+    uint8_t mantisse = 0;
+    switch( ( *reg & 0x18 ) >> 3 )
+    {
+        case 0:
+            mantisse = 16;
+            break;
+        case 1:
+            mantisse = 20;
+            break;
+        case 2:
+            mantisse = 24;
+            break;
+        default:
+            break;
+    }
+    rxBwValue = SX1276FskComputeRxBw( mantisse, ( uint8_t )*reg & 0x07 );
+    if( reg == &SX1276->RegRxBw )
+    {
+        return FskSettings.RxBw = rxBwValue;
+    }
+    else
+    {
+        return FskSettings.RxBwAfc = rxBwValue;
+    }
+}
+
+void SX1276FskSetPacketCrcOn( bool enable )
+{
+    SX1276Read( REG_PACKETCONFIG1, &SX1276->RegPacketConfig1 );
+    SX1276->RegPacketConfig1 = ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_MASK ) | ( enable << 4 );
+    SX1276Write( REG_PACKETCONFIG1, SX1276->RegPacketConfig1 );
+    FskSettings.CrcOn = enable;
+}
+
+bool SX1276FskGetPacketCrcOn( void )
+{
+    SX1276Read( REG_PACKETCONFIG1, &SX1276->RegPacketConfig1 );
+    FskSettings.CrcOn = ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_ON ) >> 4;
+    return FskSettings.CrcOn;
+}
+
+void SX1276FskSetAfcOn( bool enable )
+{
+    SX1276Read( REG_RXCONFIG, &SX1276->RegRxConfig );
+    SX1276->RegRxConfig = ( SX1276->RegRxConfig & RF_RXCONFIG_AFCAUTO_MASK ) | ( enable << 4 );
+    SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig );
+    FskSettings.AfcOn = enable;
+}
+
+bool SX1276FskGetAfcOn( void )
+{
+    SX1276Read( REG_RXCONFIG, &SX1276->RegRxConfig );
+    FskSettings.AfcOn = ( SX1276->RegRxConfig & RF_RXCONFIG_AFCAUTO_ON ) >> 4;
+    return FskSettings.AfcOn;
+}
+
+void SX1276FskSetPayloadLength( uint8_t value )
+{
+    SX1276->RegPayloadLength = value;
+    SX1276Write( REG_PAYLOADLENGTH, SX1276->RegPayloadLength );
+    FskSettings.PayloadLength = value;
+}
+
+uint8_t SX1276FskGetPayloadLength( void )
+{
+    SX1276Read( REG_PAYLOADLENGTH, &SX1276->RegPayloadLength );
+    FskSettings.PayloadLength = SX1276->RegPayloadLength;
+    return FskSettings.PayloadLength;
+}
+
+void SX1276FskSetPa20dBm( bool enale )
+{
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+
+    if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {    
+        if( enale == true )
+        {
+            SX1276->RegPaDac = 0x87;
+        }
+    }
+    else
+    {
+        SX1276->RegPaDac = 0x84;
+    }
+    SX1276Write( REG_PADAC, SX1276->RegPaDac );
+}
+
+bool SX1276FskGetPa20dBm( void )
+{
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+    
+    return ( ( SX1276->RegPaDac & 0x07 ) == 0x07 ) ? true : false;
+}
+
+void SX1276FskSetPAOutput( uint8_t outputPin )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    SX1276->RegPaConfig = (SX1276->RegPaConfig & RF_PACONFIG_PASELECT_MASK ) | outputPin;
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+}
+
+uint8_t SX1276FskGetPAOutput( void )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    return SX1276->RegPaConfig & ~RF_PACONFIG_PASELECT_MASK;
+}
+
+
+void SX1276FskSetPaRamp( uint8_t value )
+{
+    SX1276Read( REG_PARAMP, &SX1276->RegPaRamp );
+    SX1276->RegPaRamp = ( SX1276->RegPaRamp & RF_PARAMP_MASK ) | ( value & ~RF_PARAMP_MASK );
+    SX1276Write( REG_PARAMP, SX1276->RegPaRamp );
+}
+
+uint8_t SX1276FskGetPaRamp( void )
+{
+    SX1276Read( REG_PARAMP, &SX1276->RegPaRamp );
+    return SX1276->RegPaRamp & ~RF_PARAMP_MASK;
+}
+
+void SX1276FskSetRssiOffset( int8_t offset )
+{
+    SX1276Read( REG_RSSICONFIG, &SX1276->RegRssiConfig );
+    if( offset < 0 )
+    {
+        offset = ( ~offset & 0x1F );
+        offset += 1;
+        offset = -offset;
+    }
+    SX1276->RegRssiConfig |= ( uint8_t )( ( offset & 0x1F ) << 3 );
+    SX1276Write( REG_RSSICONFIG, SX1276->RegRssiConfig );
+}
+
+int8_t SX1276FskGetRssiOffset( void )
+{
+    int8_t offset;
+		SX1276Read( REG_RSSICONFIG, &SX1276->RegRssiConfig );
+    offset = SX1276->RegRssiConfig >> 3;
+    if( ( offset & 0x10 ) == 0x10 )
+    {
+        offset = ( ~offset & 0x1F );
+        offset += 1;
+        offset = -offset;
+    }
+    return offset;
+}
+
+int8_t SX1276FskGetRawTemp( void )
+{
+    int8_t temp = 0;
+    uint8_t previousOpMode;
+    uint32_t startTick;
+    
+    // Enable Temperature reading
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_TEMPMONITOR_MASK ) | RF_IMAGECAL_TEMPMONITOR_ON;
+    SX1276Write( REG_IMAGECAL, SX1276->RegImageCal );
+
+    // save current Op Mode
+    SX1276Read( REG_OPMODE, &SX1276->RegOpMode );
+    previousOpMode = SX1276->RegOpMode;
+
+    // put device in FSK RxSynth
+    SX1276->RegOpMode = RF_OPMODE_SYNTHESIZER_RX;
+    SX1276Write( REG_OPMODE, SX1276->RegOpMode );
+
+    // Wait 1ms
+    startTick = GET_TICK_COUNT( );
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) );  
+
+    // Disable Temperature reading
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_TEMPMONITOR_MASK ) | RF_IMAGECAL_TEMPMONITOR_OFF;
+    SX1276Write( REG_IMAGECAL, SX1276->RegImageCal );
+
+    // Read temperature
+    SX1276Read( REG_TEMP, &SX1276->RegTemp );
+    
+    temp = SX1276->RegTemp & 0x7F;
+    
+    if( ( SX1276->RegTemp & 0x80 ) == 0x80 )
+    {
+        temp *= -1;
+    }
+
+    // Reload previous Op Mode
+    SX1276Write( REG_OPMODE, previousOpMode );
+
+    return temp;
+}
+
+int8_t SX1276FskCalibreateTemp( int8_t actualTemp )
+{
+    return actualTemp - SX1276FskGetRawTemp( );
+}
+
+int8_t SX1276FskGetTemp( int8_t compensationFactor )
+{
+    return SX1276FskGetRawTemp( ) + compensationFactor;
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-FskMisc.h

@@ -0,0 +1,251 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-FskMisc.h
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.B2 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-FskMisc.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __SX1276_FSK_MISC_H__
+#define __SX1276_FSK_MISC_H__
+
+/*!
+ * \brief Writes the new RF frequency value
+ *
+ * \param [IN] freq New RF frequency value in [Hz]
+ */
+void SX1276FskSetRFFrequency( uint32_t freq );
+
+/*!
+ * \brief Reads the current RF frequency value
+ *
+ * \retval freq Current RF frequency value in [Hz]
+ */
+uint32_t SX1276FskGetRFFrequency( void );
+
+/*!
+ * \brief Calibrate RSSI and I/Q mismatch for HF 
+ *
+ * \retval none
+ */
+void SX1276FskRxCalibrate( void );
+
+/*!
+ * \brief Writes the new bitrate value
+ *
+ * \param [IN] bitrate New bitrate value in [bps]
+ */
+void SX1276FskSetBitrate( uint32_t bitrate );
+
+/*!
+ * \brief Reads the current bitrate value
+ *
+ * \retval bitrate Current bitrate value in [bps]
+ */
+uint32_t SX1276FskGetBitrate( void );
+
+/*!
+ * \brief Writes the new frequency deviation value
+ *
+ * \param [IN] fdev New frequency deviation value in [Hz]
+ */
+void SX1276FskSetFdev( uint32_t fdev );
+
+/*!
+ * \brief Reads the current frequency deviation value
+ *
+ * \retval fdev Current frequency deviation value in [Hz]
+ */
+uint32_t SX1276FskGetFdev( void );
+
+/*!
+ * \brief Writes the new RF output power value
+ *
+ * \param [IN] power New output power value in [dBm]
+ */
+void SX1276FskSetRFPower( int8_t power );
+
+/*!
+ * \brief Reads the current RF output power value
+ *
+ * \retval power Current output power value in [dBm]
+ */
+int8_t SX1276FskGetRFPower( void );
+
+/*!
+ * \brief Writes the DC offset canceller and Rx bandwidth values
+ *
+ * \remark For SX1276 there is no DCC setting. dccValue should be 0
+ *         ie: SX1276SetDccBw( &SX1276.RegRxBw, 0, 62500 );
+ *
+ * \param [IN] reg Register pointer to either SX1231.RegRxBw or SX1231.RegAfcBw
+ * \param [IN] dccValue New DC offset canceller value in [Hz] ( SX1231 only )
+ * \param [IN] rxBwValue New Rx bandwidth value in [Hz]
+ */
+void SX1276FskSetDccBw( uint8_t* reg, uint32_t dccValue, uint32_t rxBwValue );
+
+/*!
+ * \brief Reads the current bandwidth setting
+ *
+ * \param [IN] reg Register pointer to either SX1231.RegRxBw or SX1231.RegAfcBw
+ *
+ * \retval bandwidth Bandwidth value
+ */
+uint32_t SX1276FskGetBw( uint8_t* reg );
+
+/*!
+ * \brief Enables/Disables CRC
+ *
+ * \param [IN] enable CRC enable/disable
+ */
+void SX1276FskSetPacketCrcOn( bool enable );
+
+/*!
+ * \brief Reads the current CRC Enable/Disbale value
+ *
+ * \retval enable Current CRC Enable/Disbale value
+ */
+bool SX1276FskGetPacketCrcOn( void );
+
+/*!
+ * \brief Enables/Disables AFC
+ *
+ * \param [IN] enable AFC enable/disable
+ */
+void SX1276FskSetAfcOn( bool enable );
+
+/*!
+ * \brief Reads the current AFC Enable/Disbale value
+ *
+ * \retval enable Current AFC Enable/Disbale value
+ */
+bool SX1276FskGetAfcOn( void );
+
+/*!
+ * \brief Writes the new payload length value
+ *
+ * \param [IN] value New payload length value
+ */
+void SX1276FskSetPayloadLength( uint8_t value );
+
+/*!
+ * \brief Reads the current payload length value
+ *
+ * \retval value Current payload length value
+ */
+uint8_t SX1276FskGetPayloadLength( void );
+
+/*!
+ * \brief Enables/Disables the 20 dBm PA
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276FskSetPa20dBm( bool enale );
+
+/*!
+ * \brief Gets the current 20 dBm PA status
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276FskGetPa20dBm( void );
+
+/*!
+ * \brief Set the RF Output pin 
+ *
+ * \param [IN] RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+void SX1276FskSetPAOutput( uint8_t outputPin );
+
+/*!
+ * \brief Gets the used RF Ouptu pin
+ *
+ * \retval RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+uint8_t SX1276FskGetPAOutput( void );
+
+/*!
+ * \brief Writes the new PA rise/fall time of ramp up/down value
+ *
+ * \param [IN] value New PaRamp value
+ */
+void SX1276FskSetPaRamp( uint8_t value );
+
+/*!
+ * \brief Reads the current PA rise/fall time of ramp up/down value
+ *
+ * \retval value Current PaRamp value
+ */
+uint8_t SX1276FskGetPaRamp( void );
+
+/*!
+ * \brief Applies an offset to the RSSI. Compensates board components
+ *
+ * \param [IN] offset Offset to be applied (+/-)
+ */
+void SX1276FskSetRssiOffset( int8_t offset );
+
+/*!
+ * \brief Gets the current RSSI offset.
+ *
+ * \retval offset Current offset (+/-)
+ */
+int8_t SX1276FskGetRssiOffset( void );
+
+/*!
+ * \brief Writes the new value for the preamble size
+ *
+ * \param [IN] size New value of pramble size
+ */
+void SX1276FskSetPreambleSize( uint16_t size );
+
+/*!
+ * Reads the raw temperature
+ * \retval temperature New raw temperature reading in 2's complement format
+ */
+int8_t SX1276FskGetRawTemp( void );
+
+/*!
+ * Computes the temperature compensation factor
+ * \param [IN] actualTemp Actual temperature measured by an external device
+ * \retval compensationFactor Computed compensation factor
+ */
+int8_t SX1276FskCalibreateTemp( int8_t actualTemp );
+
+/*!
+ * Gets the actual compensated temperature
+ * \param [IN] compensationFactor Return value of the calibration function
+ * \retval New compensated temperature value
+ */
+int8_t SX1276FskGetTemp( int8_t compensationFactor );
+
+#endif //__SX1276_FSK_MISC_H__

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-Hal.h

@@ -0,0 +1,170 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-Hal.h
+ * \brief      SX1276 Hardware Abstraction Layer
+ *
+ * \version    2.0.B2 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-Hal.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __SX1276_HAL_H__
+#define __SX1276_HAL_H__
+#include "platform.h"
+
+/*!
+ * DIO state read functions mapping
+ */
+#define DIO0                                        SX1276ReadDio0( )
+#define DIO1                                        SX1276ReadDio1( )
+#define DIO2                                        SX1276ReadDio2( )
+#define DIO3                                        SX1276ReadDio3( )
+#define DIO4                                        SX1276ReadDio4( )
+#define DIO5                                        SX1276ReadDio5( )
+
+// RXTX pin control see errata note
+#define RXTX( txEnable )                            SX1276WriteRxTx( txEnable );
+
+#define GET_TICK_COUNT( )                           CurrentTicksGain()
+#define TICK_RATE_MS( ms )                          ( ms )
+
+typedef enum
+{
+    RADIO_RESET_OFF,
+    RADIO_RESET_ON,
+}tRadioResetState;
+
+/*!
+ * \brief Initializes the radio interface I/Os
+ */
+void SX1276InitIo( void );
+
+/*!
+ * \brief Set the radio reset pin state
+ * 
+ * \param state New reset pin state
+ */
+void SX1276SetReset( uint8_t state );
+
+/*!
+ * \brief Writes the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [IN]: data New register value
+ */
+void SX1276Write( uint8_t addr, uint8_t data );
+
+/*!
+ * \brief Reads the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [OUT]: data Register value
+ */
+void SX1276Read( uint8_t addr, uint8_t *data );
+
+/*!
+ * \brief Writes multiple radio registers starting at address
+ *
+ * \param [IN] addr   First Radio register address
+ * \param [IN] buffer Buffer containing the new register's values
+ * \param [IN] size   Number of registers to be written
+ */
+void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads multiple radio registers starting at address
+ *
+ * \param [IN] addr First Radio register address
+ * \param [OUT] buffer Buffer where to copy the registers data
+ * \param [IN] size Number of registers to be read
+ */
+void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Writes the buffer contents to the radio FIFO
+ *
+ * \param [IN] buffer Buffer containing data to be put on the FIFO.
+ * \param [IN] size Number of bytes to be written to the FIFO
+ */
+void SX1276WriteFifo( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads the contents of the radio FIFO
+ *
+ * \param [OUT] buffer Buffer where to copy the FIFO read data.
+ * \param [IN] size Number of bytes to be read from the FIFO
+ */
+void SX1276ReadFifo( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Gets the SX1276 DIO0 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio0( void );
+
+/*!
+ * \brief Ge// USE_SX1276_RADIOts the SX1276 DIO1 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio1( void );
+
+/*!
+ * \brief Gets the SX1276 DIO2 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio2( void );
+
+/*!
+ * \brief Gets the SX1276 DIO3 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio3( void );
+
+/*!
+ * \brief Gets the SX1276 DIO4 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio4( void );
+
+/*!
+ * \brief Gets the SX1276 DIO5 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio5( void );
+
+/*!
+ * \brief Writes the external RxTx pin value
+ *
+ * \remark see errata note
+ *
+ * \param [IN] txEnable [1: Tx, 0: Rx]
+ */
+inline void SX1276WriteRxTx( uint8_t txEnable );
+
+#endif //__SX1276_HAL_H__

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-LoRa.c

@@ -0,0 +1,723 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Original Copyright (C) SEMTECH S.A.
+ * Modified Copyright (C) 2020 AIIT XUOS Lab
+ */
+/*! 
+ * \file       sx1276-LoRa.c
+ * \brief      SX1276 RF chip driver mode LoRa
+ *
+ * \version    2.0.0 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRa.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include <string.h>
+
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+#include "radio.h"
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+#include "sx1276-LoRaMisc.h"
+#include "sx1276-LoRa.h"
+
+#define LoRa_FREQENCY                              433000000
+
+#define RSSI_OFFSET_LF                              -155.0
+#define RSSI_OFFSET_HF                              -150.0
+
+#define NOISE_ABSOLUTE_ZERO                         -174.0
+#define NOISE_FIGURE_LF                                4.0
+#define NOISE_FIGURE_HF                                6.0 
+
+volatile uint32 TickCounter = 0; 
+
+uint32 Tx_Time_Start,Tx_Time_End;   
+uint32 Rx_Time_Start,Rx_Time_End;
+//Signal bandwidth, used to calculate RSSI
+const double SignalBwLog[] =
+{
+    3.8927900303521316335038277369285,  // 7.8 kHz
+    4.0177301567005500940384239336392,  // 10.4 kHz
+    4.193820026016112828717566631653,   // 15.6 kHz
+    4.31875866931372901183597627752391, // 20.8 kHz
+    4.4948500216800940239313055263775,  // 31.2 kHz
+    4.6197891057238405255051280399961,  // 41.6 kHz
+    4.795880017344075219145044421102,   // 62.5 kHz
+    5.0969100130080564143587833158265,  // 125 kHz
+    5.397940008672037609572522210551,   // 250 kHz
+    5.6989700043360188047862611052755   // 500 kHz
+};
+
+//These values need testing
+const double RssiOffsetLF[] =
+{   
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+};
+
+//These values need testing
+const double RssiOffsetHF[] =
+{  
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+};
+
+/*!
+ * Frequency hopping frequencies table
+ */
+const int32_t HoppingFrequencies[] =
+{
+    916500000,
+    923500000,
+    906500000,
+    917500000,
+    917500000,
+    909000000,
+    903000000,
+    916000000,
+    912500000,
+    926000000,
+    925000000,
+    909500000,
+    913000000,
+    918500000,
+    918500000,
+    902500000,
+    911500000,
+    926500000,
+    902500000,
+    922000000,
+    924000000,
+    903500000,
+    913000000,
+    922000000,
+    926000000,
+    910000000,
+    920000000,
+    922500000,
+    911000000,
+    922000000,
+    909500000,
+    926000000,
+    922000000,
+    918000000,
+    925500000,
+    908000000,
+    917500000,
+    926500000,
+    908500000,
+    916000000,
+    905500000,
+    916000000,
+    903000000,
+    905000000,
+    915000000,
+    913000000,
+    907000000,
+    910000000,
+    926500000,
+    925500000,
+    911000000,
+};
+
+// Default settings
+tLoRaSettings LoRaSettings =
+{
+    LoRa_FREQENCY ,   // RFFrequency
+    20,               // Power
+    9,                // SignalBw [0: 125 kHz, 1: 250 kHz, 2: 500 kHz, 3: Reserved] 
+    12,                // SpreadingFactor [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096  chips]
+    2,                // ErrorCoding [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+    true,             // CrcOn [0: OFF, 1: ON]
+    false,            // ImplicitHeaderOn [0: OFF, 1: ON]
+    0,                // RxSingleOn [0: Continuous, 1 Single]
+    0,                // FreqHopOn [0: OFF, 1: ON]
+    4,                // HopPeriod Hops every frequency hopping period symbols
+    1000,             // TxPacketTimeout
+    1000,             // RxPacketTimeout
+    128,              // PayloadLength (used for implicit header mode)
+};
+
+/*!
+ * SX1276 LoRa registers variable
+ */
+tSX1276LR* SX1276LR;
+
+/*!
+ * Local RF buffer for communication support
+ */
+static uint8_t RFBuffer[RF_BUFFER_SIZE];
+static uint8_t TFBuffer[RF_BUFFER_SIZE];
+
+/*!
+ * RF state machine variable
+ */
+static uint8_t RFLRState = RFLR_STATE_IDLE;
+
+/*!
+ * Rx management support variables
+ */
+static uint16_t RxPacketSize = 0;     
+static int8_t RxPacketSnrEstimate;    
+static double RxPacketRssiValue;      
+static uint8_t RxGain = 1;            
+static uint32_t RxTimeoutTimer = 0;  
+
+/*!
+ * PacketTimeout Stores the Rx window time value for packet reception
+ */ 
+static uint32_t PacketTimeout;  
+
+/*!
+ * Tx management support variables
+ */
+static uint16_t TxPacketSize = 0;     
+
+
+void SX1276LoRaInit( void )
+{
+	RFLRState = RFLR_STATE_IDLE;                                     
+
+	SX1276LoRaSetDefaults();                                         
+	
+	SX1276ReadBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 );     
+    
+    //SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP );
+	
+    SX1276LR->RegLna = RFLR_LNA_GAIN_G1;                             
+    SX1276WriteBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 );    
+	
+    // set the RF settings 
+    SX1276LoRaSetRFFrequency( LoRaSettings.RFFrequency );            
+    SX1276LoRaSetSpreadingFactor( LoRaSettings.SpreadingFactor );    
+    SX1276LoRaSetErrorCoding( LoRaSettings.ErrorCoding );            
+    SX1276LoRaSetPacketCrcOn( LoRaSettings.CrcOn );                  
+    SX1276LoRaSetSignalBandwidth( LoRaSettings.SignalBw );           
+    SX1276LoRaSetImplicitHeaderOn( LoRaSettings.ImplicitHeaderOn );  
+	
+    SX1276LoRaSetSymbTimeout(0x3FF);                                 
+    SX1276LoRaSetPayloadLength( LoRaSettings.PayloadLength );        
+    SX1276LoRaSetLowDatarateOptimize( true );                        
+
+    #if( ( MODULE_SX1276RF1IAS == 1 ) || ( MODULE_SX1276RF1KAS == 1 ) )
+        if( LoRaSettings.RFFrequency > 860000000 )                   
+        {
+            SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_RFO );     
+            SX1276LoRaSetPa20dBm( false );                           
+            LoRaSettings.Power = 14;                                 
+            SX1276LoRaSetRFPower( LoRaSettings.Power );              
+        }
+        else                                                         
+        {
+			//SX1276Write( REG_LR_OCP, 0x3f );
+            SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_PABOOST ); 
+            SX1276LoRaSetPa20dBm( true );                            
+            LoRaSettings.Power = 20;                                 
+            SX1276LoRaSetRFPower( LoRaSettings.Power );                     
+        } 
+    #elif( MODULE_SX1276RF1JAS == 1 )	
+		if( LoRaSettings.RFFrequency > 380000000 )                   
+		{
+			SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_PABOOST ); 
+			SX1276LoRaSetPa20dBm( true );                            
+			LoRaSettings.Power = 20;                                 
+			SX1276LoRaSetRFPower( LoRaSettings.Power );                
+		}
+		else
+		{
+			SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_RFO );
+			SX1276LoRaSetPa20dBm( false );
+			LoRaSettings.Power = 14;
+			SX1276LoRaSetRFPower( LoRaSettings.Power );
+		} 
+	#endif
+    SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );	
+
+	SX1276ReadBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 );                         
+}
+
+void SX1276LoRaSetDefaults( void )
+{
+    // REMARK: See SX1276 datasheet for modified default values.
+
+    // Sets IF frequency selection manual
+    SX1276Read( REG_LR_VERSION, &SX1276LR->RegVersion );
+}
+
+void SX1276LoRaReset( void )
+{
+    uint32_t startTick;
+	
+	SX1276SetReset( RADIO_RESET_ON );
+    
+	// Wait 1ms
+    startTick = GET_TICK_COUNT( );                                    
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) );    
+
+    SX1276SetReset( RADIO_RESET_OFF );
+    
+	// Wait 6ms
+    startTick = GET_TICK_COUNT( );                                    
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 6 ) );    
+}
+
+void SX1276LoRaSetOpMode( uint8_t opMode )
+{
+    static uint8_t opModePrev = RFLR_OPMODE_STANDBY;
+    static bool antennaSwitchTxOnPrev = true;
+    bool antennaSwitchTxOn = false;                                  
+    opModePrev = SX1276LR->RegOpMode & ~RFLR_OPMODE_MASK;
+    if( opMode != opModePrev )                                       
+    {
+        if( opMode == RFLR_OPMODE_TRANSMITTER )                      
+		{
+			antennaSwitchTxOn = true;
+		}
+		else
+		{
+			antennaSwitchTxOn = false;
+		}
+		if( antennaSwitchTxOn != antennaSwitchTxOnPrev )
+		{
+			antennaSwitchTxOnPrev = antennaSwitchTxOn;	// Antenna switch control
+			RXTX( antennaSwitchTxOn );                                
+		}
+		SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_MASK ) | opMode | RFLR_OPMODE_FREQMODE_ACCESS_LF;
+		
+		SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode );        
+	}
+}
+
+uint8_t SX1276LoRaGetOpMode( void )                       
+{
+    SX1276Read( REG_LR_OPMODE, &SX1276LR->RegOpMode );
+    
+    return SX1276LR->RegOpMode & ~RFLR_OPMODE_MASK;
+}
+
+uint8_t SX1276LoRaReadRxGain( void )                    
+{
+	
+	SX1276Read( REG_LR_LNA, &SX1276LR->RegLna );
+	return( SX1276LR->RegLna >> 5 ) & 0x07;
+}
+
+double SX1276LoRaReadRssi( void )
+{  
+	// Reads the RSSI value
+    SX1276Read( REG_LR_RSSIVALUE, &SX1276LR->RegRssiValue );
+
+    if( LoRaSettings.RFFrequency < 860000000 )  
+    {
+        return RssiOffsetLF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegRssiValue;
+    }
+    else
+    {
+        return RssiOffsetHF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegRssiValue;
+    }
+}
+
+uint8_t SX1276LoRaGetPacketRxGain( void )
+{
+    return RxGain;
+}
+
+int8_t SX1276LoRaGetPacketSnr( void )
+{
+    return RxPacketSnrEstimate;
+}
+
+double SX1276LoRaGetPacketRssi( void )
+{
+    return RxPacketRssiValue;
+}
+
+void SX1276LoRaStartRx( void )
+{
+    SX1276LoRaSetRFState( RFLR_STATE_RX_INIT );
+}
+
+void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size )
+{
+	*size = RxPacketSize;
+	RxPacketSize = 0;
+	memcpy( (void*)buffer, (void*)RFBuffer, (size_t)*size );
+}
+
+void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size )
+{
+    if( LoRaSettings.FreqHopOn == false )    
+    {
+        TxPacketSize = size;
+    }
+    else
+    {
+        TxPacketSize = 255;
+    }
+    memcpy( ( void * )TFBuffer, buffer, ( size_t )TxPacketSize );  
+
+    RFLRState = RFLR_STATE_TX_INIT;                                
+}
+
+uint8_t SX1276LoRaGetRFState( void )
+{
+    return RFLRState;
+}
+
+void SX1276LoRaSetRFState( uint8_t state )
+{
+    RFLRState = state;
+}
+
+/*!
+ * \brief Process the LoRa modem Rx and Tx state machines depending on the
+ *        SX1276 operating mode.
+ *
+ * \retval rfState Current RF state [RF_IDLE, RF_BUSY, 
+ *                                   RF_RX_DONE, RF_RX_TIMEOUT,
+ *                                   RF_TX_DONE, RF_TX_TIMEOUT]
+ */
+uint32_t SX1276LoRaProcess( void )
+{
+    uint32_t result = RF_BUSY;
+    uint8_t regValue = 0;
+
+    switch( RFLRState )
+    {
+		case RFLR_STATE_IDLE:                                                 
+            break;
+        case RFLR_STATE_RX_INIT:                                               
+			SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);                         
+		    SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT          |  
+										//RFLR_IRQFLAGS_RXDONE             |  
+									    RFLR_IRQFLAGS_PAYLOADCRCERROR    |    
+									    RFLR_IRQFLAGS_VALIDHEADER        |
+									    RFLR_IRQFLAGS_TXDONE             |
+									    RFLR_IRQFLAGS_CADDONE            |
+                                        RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |    
+									    RFLR_IRQFLAGS_CADDETECTED;
+		    SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask );    
+
+		    if(LoRaSettings.FreqHopOn == true )                               
+		    {
+		        SX1276LR->RegHopPeriod = LoRaSettings.HopPeriod;              
+		       
+                SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );    
+			    SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+		    }
+		    else    
+		    { 
+                SX1276LR->RegHopPeriod = 255;
+		    } 
+		     
+		    SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod );  
+			
+		    if( LoRaSettings.RxSingleOn == true )        // Rx single mode                       
+		    {
+			    SX1276LoRaSetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
+		    }
+	        else                        // Rx continuous mode                                        
+		    {
+			    SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxBaseAddr;
+			     
+			    SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );    
+			    SX1276LoRaSetOpMode( RFLR_OPMODE_RECEIVER ); 
+		    }   
+		    memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE );                    
+            Rx_Time_Start=TickCounter;
+		    PacketTimeout = LoRaSettings.RxPacketTimeout;                       
+		    RxTimeoutTimer = GET_TICK_COUNT( );
+		    RFLRState = RFLR_STATE_RX_RUNNING;
+		    break;
+		case RFLR_STATE_RX_RUNNING:                                              
+			SX1276Read(0x12, &regValue);                                         
+            // RxDone
+			if(regValue & (1<<6))                                               
+            {
+		        RxTimeoutTimer = GET_TICK_COUNT( );
+                if( LoRaSettings.FreqHopOn == true )                             
+                { 
+				    SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+					SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+				}
+				// Clear Irq
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE  );           
+				RFLRState = RFLR_STATE_RX_DONE;
+			}
+			// FHSS Changed Channel
+			if(regValue & (1<<1))                                               
+			{
+			    RxTimeoutTimer = GET_TICK_COUNT( );
+			    if( LoRaSettings.FreqHopOn == true )
+				{
+					SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+					SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+				}
+				// Clear Irq
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 
+				//RxGain = SX1276LoRaReadRxGain( );
+			}
+			if( LoRaSettings.RxSingleOn == true )    // Rx single mode                             
+			{
+			    if( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout )       
+				{
+				    RFLRState = RFLR_STATE_RX_TIMEOUT;                            
+				}
+			}
+            break;
+		case RFLR_STATE_RX_DONE:                                                    	                                                                    																	
+		    SX1276Read( REG_LR_IRQFLAGS, &SX1276LR->RegIrqFlags );
+			if( ( SX1276LR->RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )   
+			{      
+				// Clear Irq
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );     
+				if( LoRaSettings.RxSingleOn == true ) // Rx single mode                             
+				{
+					RFLRState = RFLR_STATE_RX_INIT;                                
+				}
+				else
+				{ 
+					RFLRState = RFLR_STATE_RX_RUNNING;
+				}
+				break;
+		    }
+		     
+			if( LoRaSettings.RxSingleOn == true )     // Rx single mode                                
+			{
+			    SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxBaseAddr;       
+				SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );          
+			    if( LoRaSettings.ImplicitHeaderOn == true )                           
+				{
+				    RxPacketSize = SX1276LR->RegPayloadLength;
+				    SX1276ReadFifo( RFBuffer, SX1276LR->RegPayloadLength );           
+				}
+				else	
+				{
+				    SX1276Read( REG_LR_NBRXBYTES, &SX1276LR->RegNbRxBytes );
+					RxPacketSize = SX1276LR->RegNbRxBytes;
+				    SX1276ReadFifo( RFBuffer, SX1276LR->RegNbRxBytes );
+			    }
+			}
+			else     // Rx continuous mode                                                                
+			{
+				SX1276Read( REG_LR_FIFORXCURRENTADDR, &SX1276LR->RegFifoRxCurrentAddr );
+				if( LoRaSettings.ImplicitHeaderOn == true )
+				{
+					RxPacketSize = SX1276LR->RegPayloadLength;
+					SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxCurrentAddr;
+					SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );
+				    SX1276ReadFifo( RFBuffer, SX1276LR->RegPayloadLength );
+				}
+				else
+				{
+					SX1276Read( REG_LR_NBRXBYTES, &SX1276LR->RegNbRxBytes );
+					RxPacketSize = SX1276LR->RegNbRxBytes;
+					SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxCurrentAddr;
+					SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );
+					SX1276ReadFifo( RFBuffer, SX1276LR->RegNbRxBytes );
+				}
+			}  
+			if( LoRaSettings.RxSingleOn == true )   // Rx single mode                                  
+			{ 
+				RFLRState = RFLR_STATE_RX_INIT;
+			}
+			else  // Rx continuous mode                                                                    
+			{ 
+				RFLRState = RFLR_STATE_RX_RUNNING;
+			}
+			Rx_Time_End=TickCounter;
+			result = RF_RX_DONE;
+			break;
+		case RFLR_STATE_RX_TIMEOUT:                                                   
+		    RFLRState = RFLR_STATE_RX_INIT;                                          
+		    result = RF_RX_TIMEOUT;
+		    break;
+		case RFLR_STATE_TX_INIT:                                                      																	  
+		    Tx_Time_Start = TickCounter;
+			                            
+			// Initializes the payload size
+			SX1276LR->RegPayloadLength = TxPacketSize;                              
+			SX1276Write( REG_LR_PAYLOADLENGTH, SX1276LR->RegPayloadLength );
+			
+			SX1276LR->RegFifoTxBaseAddr = 0x00;  // Full buffer used for Tx                                   
+			SX1276Write( REG_LR_FIFOTXBASEADDR, SX1276LR->RegFifoTxBaseAddr );
+
+			SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoTxBaseAddr;
+			SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );
+
+			SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );   
+
+			// Write payload buffer to LORA modem
+			SX1276WriteFifo( TFBuffer, SX1276LR->RegPayloadLength );  
+
+			if( LoRaSettings.FreqHopOn == true )                                     
+			{
+				SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT          |
+											RFLR_IRQFLAGS_RXDONE             |
+											RFLR_IRQFLAGS_PAYLOADCRCERROR    |
+											RFLR_IRQFLAGS_VALIDHEADER        |
+										    //RFLR_IRQFLAGS_TXDONE             |
+											RFLR_IRQFLAGS_CADDONE            |
+										    RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+											RFLR_IRQFLAGS_CADDETECTED;
+				SX1276LR->RegHopPeriod = LoRaSettings.HopPeriod;
+				SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+				SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+			 }
+			 else
+			 {
+				SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT          |
+									        RFLR_IRQFLAGS_RXDONE             |
+											RFLR_IRQFLAGS_PAYLOADCRCERROR    |
+											RFLR_IRQFLAGS_VALIDHEADER        |
+										   	//RFLR_IRQFLAGS_TXDONE             |
+											RFLR_IRQFLAGS_CADDONE            |
+											RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+											RFLR_IRQFLAGS_CADDETECTED;             
+				SX1276LR->RegHopPeriod = 0;
+			}
+			SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod );                
+			SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask );  
+
+			SX1276Write( REG_LR_DIOMAPPING1, ( regValue & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );//DIO0设置为TXdone中断              
+
+			SX1276LoRaSetOpMode( RFLR_OPMODE_TRANSMITTER );
+
+			RFLRState = RFLR_STATE_TX_RUNNING;
+			break;
+		case RFLR_STATE_TX_RUNNING:                                            
+			SX1276Read(0x12, &regValue);
+			if(regValue & (1<<3))
+			{
+		        // Clear Irq
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );          
+				RFLRState = RFLR_STATE_TX_DONE;   
+			}	
+			// FHSS Changed Channel
+			if(regValue & (1<<3))
+			{
+				if( LoRaSettings.FreqHopOn == true )
+				{
+					SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+					SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+				}		
+				// Clear Irq		
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 
+			}
+			break;
+		case RFLR_STATE_TX_DONE:                                                
+            Tx_Time_End=TickCounter;			
+			SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );                         
+			RFLRState = RFLR_STATE_IDLE;
+			result = RF_TX_DONE;
+			break;
+		case RFLR_STATE_CAD_INIT:
+		// optimize the power consumption by switching off the transmitter as soon as the packet has been sent                                               
+			SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );
+			SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT           |
+										RFLR_IRQFLAGS_RXDONE              |
+										RFLR_IRQFLAGS_PAYLOADCRCERROR     |
+										RFLR_IRQFLAGS_VALIDHEADER         |
+										RFLR_IRQFLAGS_TXDONE              |
+									    //RFLR_IRQFLAGS_CADDONE             |
+										RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL;
+									    //RFLR_IRQFLAGS_CADDETECTED;
+			SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask );
+
+			SX1276LoRaSetOpMode( RFLR_OPMODE_CAD );
+			RFLRState = RFLR_STATE_CAD_RUNNING;
+
+			break;
+		case RFLR_STATE_CAD_RUNNING:
+			SX1276Read(0x12,&regValue);                                         
+			int cad_done = regValue & (1<<2);
+			int cad_detected = regValue & (1<<0);
+
+			if( cad_done  ) //CAD Done interrupt
+			{ 
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE  );
+				if( cad_detected  ) // CAD Detected interrupt
+				{
+					SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED  );
+					//CAD detected, we have a LoRa preamble
+					RFLRState = RFLR_STATE_RX_INIT;
+					result = RF_CHANNEL_ACTIVITY_DETECTED;
+                } 
+				else
+				{    
+					// The device goes in Standby Mode automatically    
+					RFLRState = RFLR_STATE_IDLE;
+					result = RF_CHANNEL_EMPTY;
+				}
+			}   
+			break;			
+        default:
+            break;
+    } 
+    return result;
+}
+
+uint32_t SX1276LoraChannelEmpty( void )
+{
+	uint32_t result = 0;
+	RFLRState = RFLR_STATE_CAD_INIT;
+	SX1276LoRaProcess();
+    while(RFLRState == RFLR_STATE_CAD_RUNNING)
+	{
+		//KPrintf("\nLora--SX1276LoRaProcess()");
+		result = SX1276LoRaProcess();
+	}
+
+	if(result == RF_CHANNEL_EMPTY)
+	{
+		KPrintf("\nLora--RF_CHANNEL_EMPTY\n");
+		return 0;
+	}
+	else if(result == RF_CHANNEL_ACTIVITY_DETECTED)
+	{
+		KPrintf("\nLora--RF_CHANNEL_ACTIVITY_DETECTED\n");
+		return 1;
+	}
+	else
+	{
+		return 2;
+	}
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-LoRa.h

@@ -0,0 +1,820 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Original Copyright (C) SEMTECH S.A.
+ * Modified Copyright (C) 2020 AIIT XUOS Lab
+ */
+/*! 
+ * \file       sx1276-LoRa.h
+ * \brief      SX1276 RF chip driver mode LoRa
+ *
+ * \version    2.0.0 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRa.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __SX1276_LORA_H__
+#define __SX1276_LORA_H__
+
+#include "stdint.h"
+#include "stdbool.h"
+
+
+//SX1276一些配置参数设置
+typedef struct sLoRaSettings
+{
+    uint32_t RFFrequency;			    //无线通信频率
+    int8_t Power;                       //功率
+    uint8_t SignalBw;                   //LORA 带宽[0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz,
+                                        //5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved]  
+    uint8_t SpreadingFactor;            //扩频因子 LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096  chips]
+    uint8_t ErrorCoding;                //LORA 纠错码 [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+    bool CrcOn;                         //CRC效验开关 [0: OFF, 1: ON]
+    bool ImplicitHeaderOn;              //隐藏头部信息开关 [0: OFF, 1: ON]
+    bool RxSingleOn;                    //接收单次模式\连续模式配置[0: Continuous, 1 Single]
+    bool FreqHopOn;                     //跳频模式开关 [0: OFF, 1: ON]
+    uint8_t HopPeriod;                  //跳频之间的周期长度 Hops every frequency hopping period symbols
+    uint32_t TxPacketTimeout;           //最大发送时间
+    uint32_t RxPacketTimeout;           //最大接收时间
+    uint8_t PayloadLength;              //数据长度
+}tLoRaSettings;
+
+//RF数据包大小(模块配备了256Byte的RAM缓存，该缓存仅能通过LoRa模式访问)
+#define RF_BUFFER_SIZE_MAX                          256
+#define RF_BUFFER_SIZE                              256
+
+
+//LoRa的返回值
+typedef enum
+{
+    RFLR_STATE_IDLE,
+    RFLR_STATE_RX_INIT,
+    RFLR_STATE_RX_RUNNING,
+    RFLR_STATE_RX_DONE,
+    RFLR_STATE_RX_TIMEOUT,
+    RFLR_STATE_TX_INIT,
+    RFLR_STATE_TX_RUNNING,
+    RFLR_STATE_TX_DONE,
+    RFLR_STATE_TX_TIMEOUT,
+    RFLR_STATE_CAD_INIT,
+    RFLR_STATE_CAD_RUNNING,
+}tRFLRStates;
+
+
+//SX1276 definitions
+#define XTAL_FREQ                                   32000000
+#define FREQ_STEP                                   61.03515625
+
+/*LoRa模式寄存器映射*/
+//SX1276内部寄存器地址
+#define REG_LR_FIFO                                 0x00    //FIFO 数据输入/输出。当器件处于睡眠模式时，FIFO被清零，无法访问。
+
+//通用寄存器
+#define REG_LR_OPMODE                               0x01    //关于模式选择相关的寄存器  
+#define REG_LR_BANDSETTING                          0x04    
+#define REG_LR_FRFMSB                               0x06    //RF 载波频率最高有效位
+#define REG_LR_FRFMID                               0x07    //RF 载波频率中间有效位
+#define REG_LR_FRFLSB                               0x08    //RF 载波频率最低有效位
+
+//RF模块寄存器
+#define REG_LR_PACONFIG                             0x09    
+#define REG_LR_PARAMP                               0x0A    
+#define REG_LR_OCP                                  0x0B 
+#define REG_LR_LNA                                  0x0C 
+
+//LoRa页面寄存器
+#define REG_LR_FIFOADDRPTR                          0x0D 
+#define REG_LR_FIFOTXBASEADDR                       0x0E 
+#define REG_LR_FIFORXBASEADDR                       0x0F 
+#define REG_LR_FIFORXCURRENTADDR                    0x10 
+#define REG_LR_IRQFLAGSMASK                         0x11  //IAQ标志屏蔽 
+#define REG_LR_IRQFLAGS                             0x12 
+#define REG_LR_NBRXBYTES                            0x13 
+#define REG_LR_RXHEADERCNTVALUEMSB                  0x14 
+#define REG_LR_RXHEADERCNTVALUELSB                  0x15 
+#define REG_LR_RXPACKETCNTVALUEMSB                  0x16 
+#define REG_LR_RXPACKETCNTVALUELSB                  0x17 
+#define REG_LR_MODEMSTAT                            0x18 
+#define REG_LR_PKTSNRVALUE                          0x19 
+#define REG_LR_PKTRSSIVALUE                         0x1A 
+#define REG_LR_RSSIVALUE                            0x1B 
+#define REG_LR_HOPCHANNEL                           0x1C 
+#define REG_LR_MODEMCONFIG1                         0x1D 
+#define REG_LR_MODEMCONFIG2                         0x1E 
+#define REG_LR_SYMBTIMEOUTLSB                       0x1F 
+#define REG_LR_PREAMBLEMSB                          0x20 
+#define REG_LR_PREAMBLELSB                          0x21 
+#define REG_LR_PAYLOADLENGTH                        0x22 
+#define REG_LR_PAYLOADMAXLENGTH                     0x23 
+#define REG_LR_HOPPERIOD                            0x24 
+#define REG_LR_FIFORXBYTEADDR                       0x25
+#define REG_LR_MODEMCONFIG3                         0x26
+/*以上是LoRa模式寄存器映射*/
+
+//IO控制寄存器（关于DI00-DI05的映射设置）
+#define REG_LR_DIOMAPPING1                          0x40
+#define REG_LR_DIOMAPPING2                          0x41
+
+//版本寄存器
+#define REG_LR_VERSION                              0x42
+
+//附加寄存器
+#define REG_LR_PLLHOP                               0x44
+#define REG_LR_TCXO                                 0x4B
+#define REG_LR_PADAC                                0x4D
+#define REG_LR_FORMERTEMP                           0x5B
+#define REG_LR_BITRATEFRAC                          0x5D
+#define REG_LR_AGCREF                               0x61
+#define REG_LR_AGCTHRESH1                           0x62
+#define REG_LR_AGCTHRESH2                           0x63
+#define REG_LR_AGCTHRESH3                           0x64
+
+//与模式选择相关的宏定义 RegOpMode(寄存器地址0X01)
+#define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F 
+#define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default
+#define RFLR_OPMODE_LONGRANGEMODE_ON                0x80 
+
+#define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF 
+#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40 
+#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default
+
+#define RFLR_OPMODE_FREQMODE_ACCESS_MASK            0xF7
+#define RFLR_OPMODE_FREQMODE_ACCESS_LF              0x08 // Default
+#define RFLR_OPMODE_FREQMODE_ACCESS_HF              0x00 
+
+#define RFLR_OPMODE_MASK                            0xF8 
+#define RFLR_OPMODE_SLEEP                           0x00 //睡眠模式
+#define RFLR_OPMODE_STANDBY                         0x01 //待机模式
+#define RFLR_OPMODE_SYNTHESIZER_TX                  0x02 //频率合成器转换至Tx频率
+#define RFLR_OPMODE_TRANSMITTER                     0x03 //发送模式
+#define RFLR_OPMODE_SYNTHESIZER_RX                  0x04 //频率合成器转换至Rx频率
+#define RFLR_OPMODE_RECEIVER                        0x05 //接收模式
+
+#define RFLR_OPMODE_RECEIVER_SINGLE                 0x06 //单次接收模式   
+#define RFLR_OPMODE_CAD                             0x07 //CAD模式 
+
+//与位带操作相关的宏定义
+#define RFLR_BANDSETTING_MASK                       0x3F 
+#define RFLR_BANDSETTING_AUTO                       0x00 // Default
+#define RFLR_BANDSETTING_DIV_BY_1                   0x40
+#define RFLR_BANDSETTING_DIV_BY_2                   0x80
+#define RFLR_BANDSETTING_DIV_BY_6                   0xC0
+
+//射频载波频率设置相关宏定义 RegFrf (MHz)(寄存器地址0x06，0x07,0x08)
+#define RFLR_FRFMSB_434_MHZ                         0x6C // Default
+#define RFLR_FRFMID_434_MHZ                         0x80 // Default
+#define RFLR_FRFLSB_434_MHZ                         0x00 // Default
+
+#define RFLR_FRFMSB_470_MHZ                         0x73 // Default
+#define RFLR_FRFMID_470_MHZ                         0xBB // Default
+#define RFLR_FRFLSB_470_MHZ                         0xBB // Default
+
+#define RFLR_FRFMSB_863_MHZ                         0xD7
+#define RFLR_FRFMID_863_MHZ                         0xC0
+#define RFLR_FRFLSB_863_MHZ                         0x00
+#define RFLR_FRFMSB_864_MHZ                         0xD8
+#define RFLR_FRFMID_864_MHZ                         0x00
+#define RFLR_FRFLSB_864_MHZ                         0x00
+#define RFLR_FRFMSB_865_MHZ                         0xD8
+#define RFLR_FRFMID_865_MHZ                         0x40
+#define RFLR_FRFLSB_865_MHZ                         0x00
+#define RFLR_FRFMSB_866_MHZ                         0xD8
+#define RFLR_FRFMID_866_MHZ                         0x80
+#define RFLR_FRFLSB_866_MHZ                         0x00
+#define RFLR_FRFMSB_867_MHZ                         0xD8
+#define RFLR_FRFMID_867_MHZ                         0xC0
+#define RFLR_FRFLSB_867_MHZ                         0x00
+#define RFLR_FRFMSB_868_MHZ                         0xD9
+#define RFLR_FRFMID_868_MHZ                         0x00
+#define RFLR_FRFLSB_868_MHZ                         0x00
+#define RFLR_FRFMSB_869_MHZ                         0xD9
+#define RFLR_FRFMID_869_MHZ                         0x40
+#define RFLR_FRFLSB_869_MHZ                         0x00
+#define RFLR_FRFMSB_870_MHZ                         0xD9
+#define RFLR_FRFMID_870_MHZ                         0x80
+#define RFLR_FRFLSB_870_MHZ                         0x00
+
+#define RFLR_FRFMSB_902_MHZ                         0xE1
+#define RFLR_FRFMID_902_MHZ                         0x80
+#define RFLR_FRFLSB_902_MHZ                         0x00
+#define RFLR_FRFMSB_903_MHZ                         0xE1
+#define RFLR_FRFMID_903_MHZ                         0xC0
+#define RFLR_FRFLSB_903_MHZ                         0x00
+#define RFLR_FRFMSB_904_MHZ                         0xE2
+#define RFLR_FRFMID_904_MHZ                         0x00
+#define RFLR_FRFLSB_904_MHZ                         0x00
+#define RFLR_FRFMSB_905_MHZ                         0xE2
+#define RFLR_FRFMID_905_MHZ                         0x40
+#define RFLR_FRFLSB_905_MHZ                         0x00
+#define RFLR_FRFMSB_906_MHZ                         0xE2
+#define RFLR_FRFMID_906_MHZ                         0x80
+#define RFLR_FRFLSB_906_MHZ                         0x00
+#define RFLR_FRFMSB_907_MHZ                         0xE2
+#define RFLR_FRFMID_907_MHZ                         0xC0
+#define RFLR_FRFLSB_907_MHZ                         0x00
+#define RFLR_FRFMSB_908_MHZ                         0xE3
+#define RFLR_FRFMID_908_MHZ                         0x00
+#define RFLR_FRFLSB_908_MHZ                         0x00
+#define RFLR_FRFMSB_909_MHZ                         0xE3
+#define RFLR_FRFMID_909_MHZ                         0x40
+#define RFLR_FRFLSB_909_MHZ                         0x00
+#define RFLR_FRFMSB_910_MHZ                         0xE3
+#define RFLR_FRFMID_910_MHZ                         0x80
+#define RFLR_FRFLSB_910_MHZ                         0x00
+#define RFLR_FRFMSB_911_MHZ                         0xE3
+#define RFLR_FRFMID_911_MHZ                         0xC0
+#define RFLR_FRFLSB_911_MHZ                         0x00
+#define RFLR_FRFMSB_912_MHZ                         0xE4
+#define RFLR_FRFMID_912_MHZ                         0x00
+#define RFLR_FRFLSB_912_MHZ                         0x00
+#define RFLR_FRFMSB_913_MHZ                         0xE4
+#define RFLR_FRFMID_913_MHZ                         0x40
+#define RFLR_FRFLSB_913_MHZ                         0x00
+#define RFLR_FRFMSB_914_MHZ                         0xE4
+#define RFLR_FRFMID_914_MHZ                         0x80
+#define RFLR_FRFLSB_914_MHZ                         0x00
+#define RFLR_FRFMSB_915_MHZ                         0xE4  // Default
+#define RFLR_FRFMID_915_MHZ                         0xC0  // Default
+#define RFLR_FRFLSB_915_MHZ                         0x00  // Default
+#define RFLR_FRFMSB_916_MHZ                         0xE5
+#define RFLR_FRFMID_916_MHZ                         0x00
+#define RFLR_FRFLSB_916_MHZ                         0x00
+#define RFLR_FRFMSB_917_MHZ                         0xE5
+#define RFLR_FRFMID_917_MHZ                         0x40
+#define RFLR_FRFLSB_917_MHZ                         0x00
+#define RFLR_FRFMSB_918_MHZ                         0xE5
+#define RFLR_FRFMID_918_MHZ                         0x80
+#define RFLR_FRFLSB_918_MHZ                         0x00
+#define RFLR_FRFMSB_919_MHZ                         0xE5
+#define RFLR_FRFMID_919_MHZ                         0xC0
+#define RFLR_FRFLSB_919_MHZ                         0x00
+#define RFLR_FRFMSB_920_MHZ                         0xE6
+#define RFLR_FRFMID_920_MHZ                         0x00
+#define RFLR_FRFLSB_920_MHZ                         0x00
+#define RFLR_FRFMSB_921_MHZ                         0xE6
+#define RFLR_FRFMID_921_MHZ                         0x40
+#define RFLR_FRFLSB_921_MHZ                         0x00
+#define RFLR_FRFMSB_922_MHZ                         0xE6
+#define RFLR_FRFMID_922_MHZ                         0x80
+#define RFLR_FRFLSB_922_MHZ                         0x00
+#define RFLR_FRFMSB_923_MHZ                         0xE6
+#define RFLR_FRFMID_923_MHZ                         0xC0
+#define RFLR_FRFLSB_923_MHZ                         0x00
+#define RFLR_FRFMSB_924_MHZ                         0xE7
+#define RFLR_FRFMID_924_MHZ                         0x00
+#define RFLR_FRFLSB_924_MHZ                         0x00
+#define RFLR_FRFMSB_925_MHZ                         0xE7
+#define RFLR_FRFMID_925_MHZ                         0x40
+#define RFLR_FRFLSB_925_MHZ                         0x00
+#define RFLR_FRFMSB_926_MHZ                         0xE7
+#define RFLR_FRFMID_926_MHZ                         0x80
+#define RFLR_FRFLSB_926_MHZ                         0x00
+#define RFLR_FRFMSB_927_MHZ                         0xE7
+#define RFLR_FRFMID_927_MHZ                         0xC0
+#define RFLR_FRFLSB_927_MHZ                         0x00
+#define RFLR_FRFMSB_928_MHZ                         0xE8
+#define RFLR_FRFMID_928_MHZ                         0x00
+#define RFLR_FRFLSB_928_MHZ                         0x00
+
+//PA（功率放大器） 选择和输出功率控制设置相关宏定义 RegPaConfig（寄存器地址0X09）
+#define RFLR_PACONFIG_PASELECT_MASK                 0x7F 
+#define RFLR_PACONFIG_PASELECT_PABOOST              0x80 
+#define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default
+
+#define RFLR_PACONFIG_MAX_POWER_MASK                0x8F
+
+#define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0 
+ 
+//PA（功率放大器） 斜升/斜降时间和低相噪设置相关定义 RegPaRamp（寄存器地址0X0A）
+#define RFLR_PARAMP_TXBANDFORCE_MASK                0xEF 
+#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL            0x10 
+#define RFLR_PARAMP_TXBANDFORCE_AUTO                0x00 // Default
+
+#define RFLR_PARAMP_MASK                            0xF0 
+#define RFLR_PARAMP_3400_US                         0x00 
+#define RFLR_PARAMP_2000_US                         0x01 
+#define RFLR_PARAMP_1000_US                         0x02
+#define RFLR_PARAMP_0500_US                         0x03 
+#define RFLR_PARAMP_0250_US                         0x04 
+#define RFLR_PARAMP_0125_US                         0x05 
+#define RFLR_PARAMP_0100_US                         0x06 
+#define RFLR_PARAMP_0062_US                         0x07 
+#define RFLR_PARAMP_0050_US                         0x08 
+#define RFLR_PARAMP_0040_US                         0x09 // Default
+#define RFLR_PARAMP_0031_US                         0x0A 
+#define RFLR_PARAMP_0025_US                         0x0B 
+#define RFLR_PARAMP_0020_US                         0x0C 
+#define RFLR_PARAMP_0015_US                         0x0D 
+#define RFLR_PARAMP_0012_US                         0x0E 
+#define RFLR_PARAMP_0010_US                         0x0F 
+
+//过流保护控制设置相关宏定义 RegOcp（寄存器地址0X0B）
+#define RFLR_OCP_MASK                               0xDF 
+#define RFLR_OCP_ON                                 0x20 // Default
+#define RFLR_OCP_OFF                                0x00   
+
+#define RFLR_OCP_TRIM_MASK                          0xE0
+#define RFLR_OCP_TRIM_045_MA                        0x00
+#define RFLR_OCP_TRIM_050_MA                        0x01   
+#define RFLR_OCP_TRIM_055_MA                        0x02 
+#define RFLR_OCP_TRIM_060_MA                        0x03 
+#define RFLR_OCP_TRIM_065_MA                        0x04 
+#define RFLR_OCP_TRIM_070_MA                        0x05 
+#define RFLR_OCP_TRIM_075_MA                        0x06 
+#define RFLR_OCP_TRIM_080_MA                        0x07  
+#define RFLR_OCP_TRIM_085_MA                        0x08
+#define RFLR_OCP_TRIM_090_MA                        0x09 
+#define RFLR_OCP_TRIM_095_MA                        0x0A 
+#define RFLR_OCP_TRIM_100_MA                        0x0B  // Default
+#define RFLR_OCP_TRIM_105_MA                        0x0C 
+#define RFLR_OCP_TRIM_110_MA                        0x0D 
+#define RFLR_OCP_TRIM_115_MA                        0x0E 
+#define RFLR_OCP_TRIM_120_MA                        0x0F 
+#define RFLR_OCP_TRIM_130_MA                        0x10
+#define RFLR_OCP_TRIM_140_MA                        0x11   
+#define RFLR_OCP_TRIM_150_MA                        0x12 
+#define RFLR_OCP_TRIM_160_MA                        0x13 
+#define RFLR_OCP_TRIM_170_MA                        0x14 
+#define RFLR_OCP_TRIM_180_MA                        0x15 
+#define RFLR_OCP_TRIM_190_MA                        0x16 
+#define RFLR_OCP_TRIM_200_MA                        0x17  
+#define RFLR_OCP_TRIM_210_MA                        0x18
+#define RFLR_OCP_TRIM_220_MA                        0x19 
+#define RFLR_OCP_TRIM_230_MA                        0x1A 
+#define RFLR_OCP_TRIM_240_MA                        0x1B
+
+//LNA（低噪声放大器 ）设置相关宏定义 RegLna（寄存器地址0X0C）
+#define RFLR_LNA_GAIN_MASK                          0x1F 
+#define RFLR_LNA_GAIN_G1                            0x20 // Default
+#define RFLR_LNA_GAIN_G2                            0x40 
+#define RFLR_LNA_GAIN_G3                            0x60 
+#define RFLR_LNA_GAIN_G4                            0x80 
+#define RFLR_LNA_GAIN_G5                            0xA0 
+#define RFLR_LNA_GAIN_G6                            0xC0 
+
+#define RFLR_LNA_BOOST_LF_MASK                      0xE7 
+#define RFLR_LNA_BOOST_LF_DEFAULT                   0x00 // Default
+#define RFLR_LNA_BOOST_LF_GAIN                      0x08 
+#define RFLR_LNA_BOOST_LF_IP3                       0x10 
+#define RFLR_LNA_BOOST_LF_BOOST                     0x18 
+
+#define RFLR_LNA_RXBANDFORCE_MASK                   0xFB 
+#define RFLR_LNA_RXBANDFORCE_BAND_SEL               0x04
+#define RFLR_LNA_RXBANDFORCE_AUTO                   0x00 // Default
+
+#define RFLR_LNA_BOOST_HF_MASK                      0xFC 
+#define RFLR_LNA_BOOST_HF_OFF                       0x00 // Default
+#define RFLR_LNA_BOOST_HF_ON                        0x03 
+
+
+//FIFO 数据缓冲区中 SPI 接口地址指针（寄存器地址0X0D）
+#define RFLR_FIFOADDRPTR                            0x00 // Default
+
+//发送信息的起始位置
+#define RFLR_FIFOTXBASEADDR                         0x80 // Default
+
+//接收信息的起始位置
+#define RFLR_FIFORXBASEADDR                         0x00 // Default
+
+/*!
+ * RegFifoRxCurrentAddr (Read Only)
+ */
+
+//关于中断屏蔽相关的宏定义
+#define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80 
+#define RFLR_IRQFLAGS_RXDONE_MASK                   0x40 
+#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20 
+#define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10 
+#define RFLR_IRQFLAGS_TXDONE_MASK                   0x08 
+#define RFLR_IRQFLAGS_CADDONE_MASK                  0x04 
+#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02 
+#define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01 
+
+//关于中断打开相关的宏定义
+#define RFLR_IRQFLAGS_RXTIMEOUT                     0x80 
+#define RFLR_IRQFLAGS_RXDONE                        0x40 
+#define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20 
+#define RFLR_IRQFLAGS_VALIDHEADER                   0x10 
+#define RFLR_IRQFLAGS_TXDONE                        0x08 
+#define RFLR_IRQFLAGS_CADDONE                       0x04 
+#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02 
+#define RFLR_IRQFLAGS_CADDETECTED                   0x01 
+
+
+
+/*!
+ * RegFifoRxNbBytes (Read Only)    //
+ */
+
+ 
+ /*!
+ * RegRxHeaderCntValueMsb (Read Only)    //
+ */
+ 
+ 
+  /*!
+ * RegRxHeaderCntValueLsb (Read Only)    //
+ */
+ 
+ 
+/*!
+ * RegRxPacketCntValueMsb (Read Only)    //
+ */
+ 
+ 
+ /*!
+ * RegRxPacketCntValueLsb (Read Only)    //
+ */
+ 
+ 
+ /*!
+ * RegModemStat (Read Only)    //
+ */
+#define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F 
+#define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0 
+ 
+/*!
+ * RegPktSnrValue (Read Only)    //
+ */
+
+ 
+ /*!
+ * RegPktRssiValue (Read Only)    //
+ */
+ 
+ 
+/*!
+ * RegRssiValue (Read Only)    //
+ */
+
+ 
+//与信号宽度，纠错编码率，是否显示报头有关宏定义（寄存器位置0X1D）
+#define RFLR_MODEMCONFIG1_BW_MASK                   0x0F 
+
+#define RFLR_MODEMCONFIG1_BW_7_81_KHZ               0x00 
+#define RFLR_MODEMCONFIG1_BW_10_41_KHZ              0x10 
+#define RFLR_MODEMCONFIG1_BW_15_62_KHZ              0x20 
+#define RFLR_MODEMCONFIG1_BW_20_83_KHZ              0x30 
+#define RFLR_MODEMCONFIG1_BW_31_25_KHZ              0x40 
+#define RFLR_MODEMCONFIG1_BW_41_66_KHZ              0x50 
+#define RFLR_MODEMCONFIG1_BW_62_50_KHZ              0x60 
+#define RFLR_MODEMCONFIG1_BW_125_KHZ                0x70 // Default
+#define RFLR_MODEMCONFIG1_BW_250_KHZ                0x80 
+#define RFLR_MODEMCONFIG1_BW_500_KHZ                0x90 
+                                                    
+#define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xF1 
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x02
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x04 // Default
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x06 
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x08 
+                                                    
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFE 
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x01 
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default
+
+//与扩频因子，接收模式，发送CRC开启，RX超时相关宏定义
+#define RFLR_MODEMCONFIG2_SF_MASK                   0x0F 
+#define RFLR_MODEMCONFIG2_SF_6                      0x60 
+#define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default
+#define RFLR_MODEMCONFIG2_SF_8                      0x80 
+#define RFLR_MODEMCONFIG2_SF_9                      0x90 
+#define RFLR_MODEMCONFIG2_SF_10                     0xA0 
+#define RFLR_MODEMCONFIG2_SF_11                     0xB0 
+#define RFLR_MODEMCONFIG2_SF_12                     0xC0 
+
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7 
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08 
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00 
+
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK         0xFB 
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON           0x04 
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF          0x00 // Default
+ 
+#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC 
+#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default
+                                                    
+                                                    
+/*!                                                 
+ * RegHopChannel (Read Only)                        
+ */                                                 
+#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F 
+#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80 
+#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default
+                                                    
+#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK          0xBF
+#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON            0x40
+#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF           0x00 // Default
+
+#define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F 
+
+
+/*!
+ * RegSymbTimeoutLsb
+ */
+#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default
+
+/*!
+ * RegPreambleLengthMsb
+ */
+#define RFLR_PREAMBLELENGTHMSB                      0x00 // Default
+
+/*!
+ * RegPreambleLengthLsb
+ */
+#define RFLR_PREAMBLELENGTHLSB                      0x08 // Default
+
+/*!
+ * RegPayloadLength
+ */
+#define RFLR_PAYLOADLENGTH                          0x0E // Default
+
+/*!
+ * RegPayloadMaxLength
+ */
+#define RFLR_PAYLOADMAXLENGTH                       0xFF // Default
+
+/*!
+ * RegHopPeriod
+ */
+#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default
+
+
+/*!
+ * RegDioMapping1
+ */
+#define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F
+#define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO0_01                    0x40
+#define RFLR_DIOMAPPING1_DIO0_10                    0x80
+#define RFLR_DIOMAPPING1_DIO0_11                    0xC0
+
+#define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF
+#define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO1_01                    0x10
+#define RFLR_DIOMAPPING1_DIO1_10                    0x20
+#define RFLR_DIOMAPPING1_DIO1_11                    0x30
+
+#define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3
+#define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO2_01                    0x04
+#define RFLR_DIOMAPPING1_DIO2_10                    0x08
+#define RFLR_DIOMAPPING1_DIO2_11                    0x0C
+
+#define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC
+#define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO3_01                    0x01
+#define RFLR_DIOMAPPING1_DIO3_10                    0x02
+#define RFLR_DIOMAPPING1_DIO3_11                    0x03
+
+/*!
+ * RegDioMapping2
+ */
+#define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F
+#define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default
+#define RFLR_DIOMAPPING2_DIO4_01                    0x40
+#define RFLR_DIOMAPPING2_DIO4_10                    0x80
+#define RFLR_DIOMAPPING2_DIO4_11                    0xC0
+
+#define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF
+#define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default
+#define RFLR_DIOMAPPING2_DIO5_01                    0x10
+#define RFLR_DIOMAPPING2_DIO5_10                    0x20
+#define RFLR_DIOMAPPING2_DIO5_11                    0x30
+
+#define RFLR_DIOMAPPING2_MAP_MASK                   0xFE
+#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01
+#define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default
+
+/*!
+ * RegVersion (Read Only)
+ */
+
+/*!
+ * RegAgcRef
+ */
+
+/*!
+ * RegAgcThresh1
+ */
+
+/*!
+ * RegAgcThresh2
+ */
+
+/*!
+ * RegAgcThresh3
+ */
+ 
+/*!
+ * RegFifoRxByteAddr (Read Only)
+ */
+ 
+/*!
+ * RegPllHop
+ */
+#define RFLR_PLLHOP_FASTHOP_MASK                    0x7F
+#define RFLR_PLLHOP_FASTHOP_ON                      0x80
+#define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default
+
+/*!
+ * RegTcxo
+ */
+#define RFLR_TCXO_TCXOINPUT_MASK                    0xEF
+#define RFLR_TCXO_TCXOINPUT_ON                      0x10
+#define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default
+
+/*!
+ * RegPaDac
+ */
+#define RFLR_PADAC_20DBM_MASK                       0xF8
+#define RFLR_PADAC_20DBM_ON                         0x07
+#define RFLR_PADAC_20DBM_OFF                        0x04  // Default
+
+/*!
+ * RegPll
+ */
+#define RFLR_PLL_BANDWIDTH_MASK                     0x3F
+#define RFLR_PLL_BANDWIDTH_75                       0x00
+#define RFLR_PLL_BANDWIDTH_150                      0x40
+#define RFLR_PLL_BANDWIDTH_225                      0x80
+#define RFLR_PLL_BANDWIDTH_300                      0xC0  // Default
+
+/*!
+ * RegPllLowPn
+ */
+#define RFLR_PLLLOWPN_BANDWIDTH_MASK                0x3F
+#define RFLR_PLLLOWPN_BANDWIDTH_75                  0x00
+#define RFLR_PLLLOWPN_BANDWIDTH_150                 0x40
+#define RFLR_PLLLOWPN_BANDWIDTH_225                 0x80
+#define RFLR_PLLLOWPN_BANDWIDTH_300                 0xC0  // Default
+
+/*!
+ * RegModemConfig3
+ */
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK  0xF7 
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON    0x08 
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF   0x00 // Default
+
+#define RFLR_MODEMCONFIG3_AGCAUTO_MASK              0xFB 
+#define RFLR_MODEMCONFIG3_AGCAUTO_ON                0x04 // Default 
+#define RFLR_MODEMCONFIG3_AGCAUTO_OFF               0x00 
+
+/*!
+ * RegFormerTemp
+ */
+
+typedef struct sSX1276LR
+{
+    uint8_t RegFifo;                                // 0x00 
+    // Common settings
+    uint8_t RegOpMode;                              // 0x01 
+    uint8_t RegRes02;                               // 0x02 
+    uint8_t RegRes03;                               // 0x03 
+    uint8_t RegBandSetting;                         // 0x04 
+    uint8_t RegRes05;                               // 0x05 
+    uint8_t RegFrfMsb;                              // 0x06 
+    uint8_t RegFrfMid;                              // 0x07 
+    uint8_t RegFrfLsb;                              // 0x08 
+    // Tx settings
+    uint8_t RegPaConfig;                            // 0x09 
+    uint8_t RegPaRamp;                              // 0x0A 
+    uint8_t RegOcp;                                 // 0x0B 
+    // Rx settings
+    uint8_t RegLna;                                 // 0x0C 
+    // LoRa registers
+    uint8_t RegFifoAddrPtr;                         // 0x0D 
+    uint8_t RegFifoTxBaseAddr;                      // 0x0E 
+    uint8_t RegFifoRxBaseAddr;                      // 0x0F 
+    uint8_t RegFifoRxCurrentAddr;                   // 0x10 
+    uint8_t RegIrqFlagsMask;                        // 0x11 
+    uint8_t RegIrqFlags;                            // 0x12 
+    uint8_t RegNbRxBytes;                           // 0x13 
+    uint8_t RegRxHeaderCntValueMsb;                 // 0x14 
+    uint8_t RegRxHeaderCntValueLsb;                 // 0x15 
+    uint8_t RegRxPacketCntValueMsb;                 // 0x16 
+    uint8_t RegRxPacketCntValueLsb;                 // 0x17 
+    uint8_t RegModemStat;                           // 0x18 
+    uint8_t RegPktSnrValue;                         // 0x19 
+    uint8_t RegPktRssiValue;                        // 0x1A 
+    uint8_t RegRssiValue;                           // 0x1B 
+    uint8_t RegHopChannel;                          // 0x1C 
+    uint8_t RegModemConfig1;                        // 0x1D 
+    uint8_t RegModemConfig2;                        // 0x1E 
+    uint8_t RegSymbTimeoutLsb;                      // 0x1F 
+    uint8_t RegPreambleMsb;                         // 0x20 
+    uint8_t RegPreambleLsb;                         // 0x21 
+    uint8_t RegPayloadLength;                       // 0x22 
+    uint8_t RegMaxPayloadLength;                    // 0x23 
+    uint8_t RegHopPeriod;                           // 0x24 跳频周期
+    uint8_t RegFifoRxByteAddr;                      // 0x25
+    uint8_t RegModemConfig3;                        // 0x26
+    uint8_t RegTestReserved27[0x30 - 0x27];         // 0x27-0x30
+    uint8_t RegTestReserved31;                      // 0x31
+    uint8_t RegTestReserved32[0x40 - 0x32];         // 0x32-0x40
+    // I/O settings                
+    uint8_t RegDioMapping1;                         // 0x40 
+    uint8_t RegDioMapping2;                         // 0x41 
+    // Version
+    uint8_t RegVersion;                             // 0x42
+    // Additional settings
+    uint8_t RegAgcRef;                              // 0x43
+    uint8_t RegAgcThresh1;                          // 0x44
+    uint8_t RegAgcThresh2;                          // 0x45
+    uint8_t RegAgcThresh3;                          // 0x46
+    // Test
+    uint8_t RegTestReserved47[0x4B - 0x47];         // 0x47-0x4A
+    // Additional settings
+    uint8_t RegPllHop;                              // 0x4B
+    uint8_t RegTestReserved4C;                      // 0x4C
+    uint8_t RegPaDac;                               // 0x4D
+    // Test
+    uint8_t RegTestReserved4E[0x58-0x4E];           // 0x4E-0x57
+    // Additional settings
+    uint8_t RegTcxo;                                // 0x58
+    // Test
+    uint8_t RegTestReserved59;                      // 0x59
+    // Test
+    uint8_t RegTestReserved5B;                      // 0x5B
+    // Additional settings
+    uint8_t RegPll;                                 // 0x5C
+    // Test
+    uint8_t RegTestReserved5D;                      // 0x5D
+    // Additional settings
+    uint8_t RegPllLowPn;                            // 0x5E
+    // Test
+    uint8_t RegTestReserved5F[0x6C - 0x5F];         // 0x5F-0x6B
+    // Additional settings
+    uint8_t RegFormerTemp;                          // 0x6C
+    // Test
+    uint8_t RegTestReserved6D[0x71 - 0x6D];         // 0x6D-0x70
+}tSX1276LR;
+
+extern tSX1276LR* SX1276LR;
+
+//初始化SX1276LoRa模式
+void SX1276LoRaInit( void );
+
+//读SX1276的版本号
+void SX1276LoRaSetDefaults( void );
+
+//启用/禁用LoRa模式
+void SX1276LoRaSetLoRaOn( bool enable );
+
+//设置SX1276操作模式
+void SX1276LoRaSetOpMode( uint8_t opMode );
+
+//获取SX1276操作模式
+uint8_t SX1276LoRaGetOpMode( void );
+
+//读取SX1276低噪声放大器（信号放大）的增益， 
+uint8_t SX1276LoRaReadRxGain( void );
+
+//读取lora模式下无线信号强度
+double SX1276LoRaReadRssi( void );
+
+//获取数据时的增益值
+uint8_t SX1276LoRaGetPacketRxGain( void );
+
+//获取数据时的信噪比值，信号和噪声的比值，信噪比越高，说明信号干扰越小。
+int8_t SX1276LoRaGetPacketSnr( void );
+
+//获取数据时的无线信号强度
+double SX1276LoRaGetPacketRssi( void );
+
+//开始接收
+void SX1276LoRaStartRx( void );
+
+//接收数据
+void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size );
+
+//发送数据
+void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size );
+
+//得到RFLRState状态
+uint8_t SX1276LoRaGetRFState( void );
+
+//设置RFLRState状态，RFLRState的值决定了下面的函数处理哪一步的代码
+void SX1276LoRaSetRFState( uint8_t state );
+
+//SX1276模块接发收数据的处理函数
+uint32_t SX1276LoRaProcess( void );
+
+uint32_t SX1276LoraChannelEmpty( void );
+
+#endif 

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-LoRaMisc.c

@@ -0,0 +1,420 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-LoRaMisc.c
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRaMisc.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+
+#include "sx1276-LoRa.h"
+#include "sx1276-LoRaMisc.h"
+
+/*!
+ * SX1276 definitions
+ */
+#define XTAL_FREQ                                   32000000
+#define FREQ_STEP                                   61.03515625
+
+extern tLoRaSettings LoRaSettings;
+
+void SX1276LoRaSetRFFrequency( uint32_t freq )
+{
+    LoRaSettings.RFFrequency = freq;
+
+    freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
+    SX1276LR->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF );
+    SX1276LR->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF );
+    SX1276LR->RegFrfLsb = ( uint8_t )( freq & 0xFF );
+    SX1276WriteBuffer( REG_LR_FRFMSB, &SX1276LR->RegFrfMsb, 3 );
+}
+
+uint32_t SX1276LoRaGetRFFrequency( void )
+{
+    SX1276ReadBuffer( REG_LR_FRFMSB, &SX1276LR->RegFrfMsb, 3 );
+    LoRaSettings.RFFrequency = ( ( uint32_t )SX1276LR->RegFrfMsb << 16 ) | ( ( uint32_t )SX1276LR->RegFrfMid << 8 ) | ( ( uint32_t )SX1276LR->RegFrfLsb );
+    LoRaSettings.RFFrequency = ( uint32_t )( ( double )LoRaSettings.RFFrequency * ( double )FREQ_STEP );
+
+    return LoRaSettings.RFFrequency;
+}
+
+void SX1276LoRaSetRFPower( int8_t power )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+    
+    if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276LR->RegPaDac & 0x87 ) == 0x87 )
+        {
+            if( power < 5 )
+            {
+                power = 5;
+            }
+            if( power > 20 )
+            {
+                power = 20;
+            }
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
+        }
+        else
+        {
+            if( power < 2 )
+            {
+                power = 2;
+            }
+            if( power > 17 )
+            {
+                power = 17;
+            }
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
+        }
+    }
+    else
+    {
+        if( power < -1 )
+        {
+            power = -1;
+        }
+        if( power > 14 )
+        {
+            power = 14;
+        }
+        SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
+        SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
+    }
+    SX1276Write( REG_LR_PACONFIG, SX1276LR->RegPaConfig );
+    LoRaSettings.Power = power;
+}
+
+int8_t SX1276LoRaGetRFPower( void )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+
+    if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276LR->RegPaDac & 0x07 ) == 0x07 )
+        {
+            LoRaSettings.Power = 5 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK );
+        }
+        else
+        {
+            LoRaSettings.Power = 2 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK );
+        }
+    }
+    else
+    {
+        LoRaSettings.Power = -1 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK );
+    }
+    return LoRaSettings.Power;
+}
+
+void SX1276LoRaSetSignalBandwidth( uint8_t bw )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | ( bw << 4 );
+    SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 );
+    LoRaSettings.SignalBw = bw;
+}
+
+uint8_t SX1276LoRaGetSignalBandwidth( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    LoRaSettings.SignalBw = ( SX1276LR->RegModemConfig1 & ~RFLR_MODEMCONFIG1_BW_MASK ) >> 4;
+    return LoRaSettings.SignalBw;
+}
+
+void SX1276LoRaSetSpreadingFactor( uint8_t factor )
+{
+
+    if( factor > 12 )
+    {
+        factor = 12;
+    }
+    else if( factor < 6 )
+    {
+        factor = 6;
+    }
+
+    if( factor == 6 )
+    {
+        SX1276LoRaSetNbTrigPeaks( 5 );
+    }
+    else
+    {
+        SX1276LoRaSetNbTrigPeaks( 3 );
+    }
+
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );    
+    SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | ( factor << 4 );
+    SX1276Write( REG_LR_MODEMCONFIG2, SX1276LR->RegModemConfig2 );    
+    LoRaSettings.SpreadingFactor = factor;
+}
+
+uint8_t SX1276LoRaGetSpreadingFactor( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );
+    LoRaSettings.SpreadingFactor = ( SX1276LR->RegModemConfig2 & ~RFLR_MODEMCONFIG2_SF_MASK ) >> 4;
+    return LoRaSettings.SpreadingFactor;
+}
+
+void SX1276LoRaSetErrorCoding( uint8_t value )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | ( value << 1 );
+    SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 );
+    LoRaSettings.ErrorCoding = value;
+}
+
+uint8_t SX1276LoRaGetErrorCoding( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    LoRaSettings.ErrorCoding = ( SX1276LR->RegModemConfig1 & ~RFLR_MODEMCONFIG1_CODINGRATE_MASK ) >> 1;
+    return LoRaSettings.ErrorCoding;
+}
+
+void SX1276LoRaSetPacketCrcOn( bool enable )
+{
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );
+    SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | ( enable << 2 );
+    SX1276Write( REG_LR_MODEMCONFIG2, SX1276LR->RegModemConfig2 );
+    LoRaSettings.CrcOn = enable;
+}
+
+void SX1276LoRaSetPreambleLength( uint16_t value )
+{
+    SX1276ReadBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 );
+
+    SX1276LR->RegPreambleMsb = ( value >> 8 ) & 0x00FF;
+    SX1276LR->RegPreambleLsb = value & 0xFF;
+    SX1276WriteBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 );
+}
+
+uint16_t SX1276LoRaGetPreambleLength( void )
+{
+    SX1276ReadBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 );
+    return ( ( SX1276LR->RegPreambleMsb & 0x00FF ) << 8 ) | SX1276LR->RegPreambleLsb;
+}
+
+bool SX1276LoRaGetPacketCrcOn( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );
+    LoRaSettings.CrcOn = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON ) >> 1;
+    return LoRaSettings.CrcOn;
+}
+
+void SX1276LoRaSetImplicitHeaderOn( bool enable )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | ( enable );
+    SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 );
+    LoRaSettings.ImplicitHeaderOn = enable;
+}
+
+bool SX1276LoRaGetImplicitHeaderOn( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    LoRaSettings.ImplicitHeaderOn = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_IMPLICITHEADER_ON );
+    return LoRaSettings.ImplicitHeaderOn;
+}
+
+void SX1276LoRaSetRxSingleOn( bool enable )
+{
+    LoRaSettings.RxSingleOn = enable;
+}
+
+bool SX1276LoRaGetRxSingleOn( void )
+{
+    return LoRaSettings.RxSingleOn;
+}
+
+void SX1276LoRaSetFreqHopOn( bool enable )
+{
+    LoRaSettings.FreqHopOn = enable;
+}
+
+bool SX1276LoRaGetFreqHopOn( void )
+{
+    return LoRaSettings.FreqHopOn;
+}
+
+void SX1276LoRaSetHopPeriod( uint8_t value )
+{
+    SX1276LR->RegHopPeriod = value;
+    SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod );
+    LoRaSettings.HopPeriod = value;
+}
+
+uint8_t SX1276LoRaGetHopPeriod( void )
+{
+    SX1276Read( REG_LR_HOPPERIOD, &SX1276LR->RegHopPeriod );
+    LoRaSettings.HopPeriod = SX1276LR->RegHopPeriod;
+    return LoRaSettings.HopPeriod;
+}
+
+void SX1276LoRaSetTxPacketTimeout( uint32_t value )
+{
+    LoRaSettings.TxPacketTimeout = value;
+}
+
+uint32_t SX1276LoRaGetTxPacketTimeout( void )
+{
+    return LoRaSettings.TxPacketTimeout;
+}
+
+void SX1276LoRaSetRxPacketTimeout( uint32_t value )
+{
+    LoRaSettings.RxPacketTimeout = value;
+}
+
+uint32_t SX1276LoRaGetRxPacketTimeout( void )
+{
+    return LoRaSettings.RxPacketTimeout;
+}
+
+void SX1276LoRaSetPayloadLength( uint8_t value )
+{
+    SX1276LR->RegPayloadLength = value;
+    SX1276Write( REG_LR_PAYLOADLENGTH, SX1276LR->RegPayloadLength );
+    LoRaSettings.PayloadLength = value;
+}
+
+uint8_t SX1276LoRaGetPayloadLength( void )
+{
+    SX1276Read( REG_LR_PAYLOADLENGTH, &SX1276LR->RegPayloadLength );
+    LoRaSettings.PayloadLength = SX1276LR->RegPayloadLength;
+    return LoRaSettings.PayloadLength;
+}
+
+void SX1276LoRaSetPa20dBm( bool enale )
+{
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+
+    if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST )
+    {    
+        if( enale == true )
+        {
+            SX1276LR->RegPaDac = 0x87;
+        }
+    }
+    else
+    {
+        SX1276LR->RegPaDac = 0x84;
+    }
+    SX1276Write( REG_LR_PADAC, SX1276LR->RegPaDac );
+}
+
+bool SX1276LoRaGetPa20dBm( void )
+{
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+    
+    return ( ( SX1276LR->RegPaDac & 0x07 ) == 0x07 ) ? true : false;
+}
+
+void SX1276LoRaSetPAOutput( uint8_t outputPin )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    SX1276LR->RegPaConfig = (SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | outputPin;
+    SX1276Write( REG_LR_PACONFIG, SX1276LR->RegPaConfig );
+}
+
+uint8_t SX1276LoRaGetPAOutput( void )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    return SX1276LR->RegPaConfig & ~RFLR_PACONFIG_PASELECT_MASK;
+}
+
+void SX1276LoRaSetPaRamp( uint8_t value )
+{
+    SX1276Read( REG_LR_PARAMP, &SX1276LR->RegPaRamp );
+    SX1276LR->RegPaRamp = ( SX1276LR->RegPaRamp & RFLR_PARAMP_MASK ) | ( value & ~RFLR_PARAMP_MASK );
+    SX1276Write( REG_LR_PARAMP, SX1276LR->RegPaRamp );
+}
+
+uint8_t SX1276LoRaGetPaRamp( void )
+{
+    SX1276Read( REG_LR_PARAMP, &SX1276LR->RegPaRamp );
+    return SX1276LR->RegPaRamp & ~RFLR_PARAMP_MASK;
+}
+
+void SX1276LoRaSetSymbTimeout( uint16_t value )
+{
+    SX1276ReadBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 );
+
+    SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | ( ( value >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK );
+    SX1276LR->RegSymbTimeoutLsb = value & 0xFF;
+    SX1276WriteBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 );
+}
+
+uint16_t SX1276LoRaGetSymbTimeout( void )
+{
+    SX1276ReadBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 );
+    return ( ( SX1276LR->RegModemConfig2 & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) << 8 ) | SX1276LR->RegSymbTimeoutLsb;
+}
+
+void SX1276LoRaSetLowDatarateOptimize( bool enable )
+{
+    SX1276Read( REG_LR_MODEMCONFIG3, &SX1276LR->RegModemConfig3 );
+    SX1276LR->RegModemConfig3 = ( SX1276LR->RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( enable << 3 );
+    SX1276Write( REG_LR_MODEMCONFIG3, SX1276LR->RegModemConfig3 );
+}
+
+bool SX1276LoRaGetLowDatarateOptimize( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG3, &SX1276LR->RegModemConfig3 );
+    return ( ( SX1276LR->RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON ) >> 3 );
+}
+
+void SX1276LoRaSetNbTrigPeaks( uint8_t value )
+{
+    SX1276Read( 0x31, &SX1276LR->RegTestReserved31 );
+    SX1276LR->RegTestReserved31 = ( SX1276LR->RegTestReserved31 & 0xF8 ) | value;//数据包长度最高有效位 0x31 bit2 1 0
+    SX1276Write( 0x31, SX1276LR->RegTestReserved31 );
+}
+
+uint8_t SX1276LoRaGetNbTrigPeaks( void )
+{
+    SX1276Read( 0x31, &SX1276LR->RegTestReserved31 );
+    return ( SX1276LR->RegTestReserved31 & 0x07 );
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276-LoRaMisc.h

@@ -0,0 +1,324 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-LoRaMisc.h
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRaMisc.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#ifndef __SX1276_LORA_MISC_H__
+#define __SX1276_LORA_MISC_H__
+#include "stdint.h"
+#include "stdbool.h"
+/*!
+ * \brief Writes the new RF frequency value
+ *
+ * \param [IN] freq New RF frequency value in [Hz]
+ */
+void SX1276LoRaSetRFFrequency( uint32_t freq );
+
+/*!
+ * \brief Reads the current RF frequency value
+ *
+ * \retval freq Current RF frequency value in [Hz]
+ */
+uint32_t SX1276LoRaGetRFFrequency( void );
+
+/*!
+ * \brief Writes the new RF output power value
+ *
+ * \param [IN] power New output power value in [dBm]
+ */
+void SX1276LoRaSetRFPower( int8_t power );
+
+/*!
+ * \brief Reads the current RF output power value
+ *
+ * \retval power Current output power value in [dBm]
+ */
+int8_t SX1276LoRaGetRFPower( void );
+
+/*!
+ * \brief Writes the new Signal Bandwidth value
+ *
+ * \remark This function sets the IF frequency according to the datasheet
+ *
+ * \param [IN] factor New Signal Bandwidth value [0: 125 kHz, 1: 250 kHz, 2: 500 kHz]
+ */
+void SX1276LoRaSetSignalBandwidth( uint8_t bw );
+
+/*!
+ * \brief Reads the current Signal Bandwidth value
+ *
+ * \retval factor Current Signal Bandwidth value [0: 125 kHz, 1: 250 kHz, 2: 500 kHz] 
+ */
+uint8_t SX1276LoRaGetSignalBandwidth( void );
+
+/*!
+ * \brief Writes the new Spreading Factor value
+ *
+ * \param [IN] factor New Spreading Factor value [7, 8, 9, 10, 11, 12]
+ */
+void SX1276LoRaSetSpreadingFactor( uint8_t factor );
+
+/*!
+ * \brief Reads the current Spreading Factor value
+ *
+ * \retval factor Current Spreading Factor value [7, 8, 9, 10, 11, 12] 
+ */
+uint8_t SX1276LoRaGetSpreadingFactor( void );
+
+/*!
+ * \brief Writes the new Error Coding value
+ *
+ * \param [IN] value New Error Coding value [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ */
+void SX1276LoRaSetErrorCoding( uint8_t value );
+
+/*!
+ * \brief Reads the current Error Coding value
+ *
+ * \retval value Current Error Coding value [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ */
+uint8_t SX1276LoRaGetErrorCoding( void );
+
+/*!
+ * \brief Enables/Disables the packet CRC generation
+ *
+ * \param [IN] enaable [true, false]
+ */
+void SX1276LoRaSetPacketCrcOn( bool enable );
+
+/*!
+ * \brief Reads the current packet CRC generation status
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetPacketCrcOn( void );
+
+/*!
+ * \brief Enables/Disables the Implicit Header mode in LoRa
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276LoRaSetImplicitHeaderOn( bool enable );
+
+/*!
+ * \brief Check if implicit header mode in LoRa in enabled or disabled
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetImplicitHeaderOn( void );
+
+/*!
+ * \brief Enables/Disables Rx single instead of Rx continuous
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276LoRaSetRxSingleOn( bool enable );
+
+/*!
+ * \brief Check if LoRa is in Rx Single mode
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetRxSingleOn( void );
+
+/*!
+ * \brief Enables/Disables the frequency hopping 
+ *
+ * \param [IN] enable [true, false]
+ */
+ 
+void SX1276LoRaSetFreqHopOn( bool enable );
+
+/*!
+ * \brief Get the frequency hopping status 
+ *
+ * \param [IN] enable [true, false]
+ */
+bool SX1276LoRaGetFreqHopOn( void );
+
+/*!
+ * \brief Set symbol period between frequency hops
+ *
+ * \param [IN] value
+ */
+void SX1276LoRaSetHopPeriod( uint8_t value );
+
+/*!
+ * \brief Get symbol period between frequency hops
+ *
+ * \retval value symbol period between frequency hops
+ */
+uint8_t SX1276LoRaGetHopPeriod( void );
+
+/*!
+ * \brief Set timeout Tx packet (based on MCU timer, timeout between Tx Mode entry Tx Done IRQ)
+ *
+ * \param [IN] value timeout (ms)
+ */
+void SX1276LoRaSetTxPacketTimeout( uint32_t value );
+
+/*!
+ * \brief Get timeout between Tx packet (based on MCU timer, timeout between Tx Mode entry Tx Done IRQ)
+ *
+ * \retval value timeout (ms)
+ */
+uint32_t SX1276LoRaGetTxPacketTimeout( void );
+
+/*!
+ * \brief Set timeout Rx packet (based on MCU timer, timeout between Rx Mode entry and Rx Done IRQ)
+ *
+ * \param [IN] value timeout (ms)
+ */
+void SX1276LoRaSetRxPacketTimeout( uint32_t value );
+
+/*!
+ * \brief Get timeout Rx packet (based on MCU timer, timeout between Rx Mode entry and Rx Done IRQ)
+ *
+ * \retval value timeout (ms)
+ */
+uint32_t SX1276LoRaGetRxPacketTimeout( void );
+
+/*!
+ * \brief Set payload length
+ *
+ * \param [IN] value payload length
+ */
+void SX1276LoRaSetPayloadLength( uint8_t value );
+
+/*!
+ * \brief Get payload length
+ *
+ * \retval value payload length
+ */
+uint8_t SX1276LoRaGetPayloadLength( void );
+
+/*!
+ * \brief Enables/Disables the 20 dBm PA
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276LoRaSetPa20dBm( bool enale );
+
+/*!
+ * \brief Gets the current 20 dBm PA status
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetPa20dBm( void );
+
+/*!
+ * \brief Set the RF Output pin 
+ *
+ * \param [IN] RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+void SX1276LoRaSetPAOutput( uint8_t outputPin );
+
+/*!
+ * \brief Gets the used RF Ouptut pin
+ *
+ * \retval RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+uint8_t SX1276LoRaGetPAOutput( void );
+
+/*!
+ * \brief Writes the new PA rise/fall time of ramp up/down value
+ *
+ * \param [IN] value New PaRamp value
+ */
+void SX1276LoRaSetPaRamp( uint8_t value );
+
+/*!
+ * \brief Reads the current PA rise/fall time of ramp up/down value
+ *
+ * \retval freq Current PaRamp value
+ */
+uint8_t SX1276LoRaGetPaRamp( void );
+
+/*!
+ * \brief Set Symbol Timeout based on symbol length
+ *
+ * \param [IN] value number of symbol
+ */
+void SX1276LoRaSetSymbTimeout( uint16_t value );
+
+/*!
+ * \brief  Get Symbol Timeout based on symbol length
+ *
+ * \retval value number of symbol
+ */
+uint16_t SX1276LoRaGetSymbTimeout( void );
+
+/*!
+ * \brief  Configure the device to optimize low datarate transfers
+ *
+ * \param [IN] enable Enables/Disables the low datarate optimization
+ */
+void SX1276LoRaSetLowDatarateOptimize( bool enable );
+
+/*!
+ * \brief  Get the status of optimize low datarate transfers
+ *
+ * \retval LowDatarateOptimize enable or disable
+ */
+bool SX1276LoRaGetLowDatarateOptimize( void );
+
+/*!
+ * \brief Get the preamble length
+ *
+ * \retval value preamble length
+ */
+uint16_t SX1276LoRaGetPreambleLength( void );
+
+/*!
+ * \brief Set the preamble length
+ *
+ * \param [IN] value preamble length
+ */
+void SX1276LoRaSetPreambleLength( uint16_t value );
+
+/*!
+ * \brief Set the number or rolling preamble symbol needed for detection
+ *
+ * \param [IN] value number of preamble symbol
+ */
+void SX1276LoRaSetNbTrigPeaks( uint8_t value );
+
+/*!
+ * \brief Get the number or rolling preamble symbol needed for detection
+ *
+ * \retval value number of preamble symbol
+ */
+uint8_t SX1276LoRaGetNbTrigPeaks( void );
+#endif 

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276.c

@@ -0,0 +1,327 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276.c
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include "platform.h"
+#include "radio.h"
+
+#if defined(USE_SX1276_RADIO)
+#include "sx1276.h"
+#include "sx1276-Hal.h"
+#include "sx1276-Fsk.h"
+#include "sx1276-LoRa.h"
+
+uint8_t SX1276Regs[0x70];        
+
+static bool LoRaOn = true;       
+static bool LoRaOnState = false; 
+
+static int sx1276_tx_sem, sx1276_rx_sem;
+static int sx1276_radio_task;
+
+void SX1276Reset(void)
+{
+	uint32_t startTick;  
+
+	SX1276SetReset(RADIO_RESET_ON);
+    
+    DDL_DelayMS(1);
+
+    SX1276SetReset(RADIO_RESET_OFF);
+    
+    DDL_DelayMS(6);   
+}
+
+void SX1276_SetLoRaOn(bool enable)
+{
+    if(LoRaOnState == enable) {
+        return;
+    }
+
+    LoRaOnState = enable;
+    LoRaOn = enable;
+
+    if(LoRaOn == true) {
+        SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);   
+		
+        SX1276LR->RegOpMode = (SX1276LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK) | RFLR_OPMODE_LONGRANGEMODE_ON;
+        SX1276Write(REG_LR_OPMODE, SX1276LR->RegOpMode);
+        
+        SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);  
+		
+                                        // RxDone               RxTimeout                   FhssChangeChannel           CadDone
+        SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00;
+                                        // CadDetected          ModeReady
+        SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
+        SX1276WriteBuffer(REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2);
+        
+        SX1276ReadBuffer(REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1);  
+    } else {
+        SX1276LoRaSetOpMode(RFLR_OPMODE_SLEEP);
+        
+        SX1276LR->RegOpMode = (SX1276LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK) | RFLR_OPMODE_LONGRANGEMODE_OFF;
+        SX1276Write(REG_LR_OPMODE, SX1276LR->RegOpMode);
+        
+        SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);
+        
+        SX1276ReadBuffer(REG_OPMODE, SX1276Regs + 1, 0x70 - 1);
+    }
+}
+
+bool SX1276_GetLoRaOn(void)
+{
+    return LoRaOn;
+}
+
+void SX1276SetOpMode(uint8_t opMode)
+{
+    if(LoRaOn == false) {
+        SX1276FskSetOpMode(opMode);
+    } else {
+        SX1276LoRaSetOpMode(opMode);
+    }
+}
+
+uint8_t SX1276_GetOpMode(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskGetOpMode();
+    } else {
+        return SX1276LoRaGetOpMode();
+    }
+}
+
+double SX1276ReadRssi(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskReadRssi();
+    } else {
+        return SX1276LoRaReadRssi();
+    }
+}
+
+uint8_t SX1276_ReadRxGain(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskReadRxGain();
+    } else {
+        return SX1276LoRaReadRxGain();
+    }
+}
+
+uint8_t SX1276_GetPacketRxGain(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskGetPacketRxGain();
+    } else {
+        return SX1276LoRaGetPacketRxGain();
+    }
+}
+
+int8_t SX1276_GetPacketSnr(void)
+{
+    if(LoRaOn == false) {
+        while(1) {
+            // Useless in FSK mode
+            // Block program here
+        }
+    } else {
+        return SX1276LoRaGetPacketSnr();
+    }
+}
+
+double SX1276_GetPacketRssi(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskGetPacketRssi();
+    } else {
+        return SX1276LoRaGetPacketRssi();
+    }
+}
+
+uint32_t SX1276GetPacketAfc(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskGetPacketAfc();
+    } else {
+        while(1) {
+            // Useless in LoRa mode
+            // Block program here
+        }
+    }
+}
+
+void SX1276StartRx(void)
+{
+    if(LoRaOn == false) {
+        SX1276FskSetRFState(RF_STATE_RX_INIT);
+    } else {
+        SX1276LoRaSetRFState(RFLR_STATE_RX_INIT);    
+    }
+}
+
+void SX1276GetRxPacket(void *buffer, uint16_t *size)
+{
+    if(LoRaOn == false) {
+        SX1276FskGetRxPacket(buffer, size);
+    } else {
+        SX1276LoRaGetRxPacket(buffer, size);
+    }
+}
+
+int SX1276GetRx(void *buffer, uint16_t *size)
+{
+    int ret = -1;
+    SX1276StartRx();
+
+    //receive timeout 10s
+    ret = KSemaphoreObtain(sx1276_rx_sem, 10000);
+    if (0 == ret) {
+        SX1276LoRaSetRFState(RFLR_STATE_IDLE);
+        SX1276GetRxPacket(buffer, size);
+    }
+    return ret;
+}
+
+void SX1276SetTxPacket(const void *buffer, uint16_t size)
+{
+    if(LoRaOn == false) {
+        SX1276FskSetTxPacket(buffer, size);
+    } else {
+        SX1276LoRaSetTxPacket(buffer, size);
+    }
+}
+
+void SX1276SetTx(const void *buffer, uint16_t size)
+{
+    SX1276SetTxPacket(buffer, size);
+
+    KSemaphoreObtain(sx1276_tx_sem, WAITING_FOREVER);
+    SX1276StartRx();
+}
+
+uint8_t SX1276GetRFState(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskGetRFState();
+    } else {
+        return SX1276LoRaGetRFState();
+    }
+}
+
+void SX1276SetRFState(uint8_t state)
+{
+    if(LoRaOn == false) {
+        SX1276FskSetRFState(state);
+    } else {
+        SX1276LoRaSetRFState(state);
+    }
+}
+
+uint32_t SX1276Process(void)
+{
+    if(LoRaOn == false) {
+        return SX1276FskProcess();
+    } else {
+        return SX1276LoRaProcess();
+    }
+}
+
+static void Sx1276RadioEntry(void *parameter)  
+{
+    uint32_t result;
+    while(1) {
+        result = SX1276Process();
+        if (RF_RX_DONE == result) {
+            KSemaphoreAbandon(sx1276_rx_sem);
+        }
+        if (RF_TX_DONE == result) {
+            KSemaphoreAbandon(sx1276_tx_sem);
+        }
+    }
+}
+
+uint32_t SX1276ChannelEmpty(void)
+{
+    if(LoRaOn == false) {
+        return true;
+    } else {
+        SX1276LoraChannelEmpty();
+    }
+}
+
+void SX1276Init(void)
+{
+	uint8_t TempReg;
+	
+    SX1276 = (tSX1276 *)SX1276Regs;    
+    SX1276LR = (tSX1276LR *)SX1276Regs;
+
+    SX1276InitIo();            
+
+    SX1276Reset();               
+
+	SX1276Read(0x06, &TempReg);
+
+	if(TempReg != 0x6C) {
+		KPrintf("Hard SPI Err!\r\n");
+	}
+
+	SX1276Read(0x42, &TempReg);
+
+	if(TempReg != 0x12) {
+		KPrintf("Hard SPI Err! version 0x%x\r\n", TempReg);
+	}
+    
+    #if (LORA == 0)               
+		LoRaOn = false;
+		SX1276_SetLoRaOn(LoRaOn);
+		SX1276FskInit();
+	#else
+		LoRaOn = true;               
+		SX1276_SetLoRaOn(LoRaOn);
+		SX1276LoRaInit();       
+	#endif
+
+    sx1276_rx_sem = KSemaphoreCreate(0);
+    sx1276_tx_sem = KSemaphoreCreate(0);
+
+    sx1276_radio_task = KTaskCreate("radio", Sx1276RadioEntry , NONE, 2048, 20);
+    StartupKTask(sx1276_radio_task);
+}
+
+#endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/spi/third_party_spi_lora/sx12xx/src/radio/sx1276.h

@@ -0,0 +1,97 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276.h
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+
+#ifndef __SX1276_H__
+#define __SX1276_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+extern uint8_t SX1276Regs[0x70];     						 //SX1276寄存器数组
+
+void SX1276Init( void );									 //初始化SX1276
+
+void SX1276Reset( void );									 //重置SX1276
+
+/*以下函数都没有被使用到，因为在sx1276-LoRa.h里面又定义了一系列与下面作用相同的函数*/
+void SX1276_SetLoRaOn( bool enable ); 						 //启用LoRa调制解调器或FSK调制解调器
+
+bool SX1276_GetLoRaOn( void );								 //获取LoRa调制解调器状态
+
+void SX1276SetOpMode( uint8_t opMode );  					 //设置SX1276操作模式
+
+uint8_t SX1276_GetOpMode( void );     						 //获取SX1276操作模式
+
+uint8_t SX1276_ReadRxGain( void );   						 //读取当前Rx增益设置
+
+double SX1276ReadRssi( void );       						 //读取无线信号强度
+
+uint8_t SX1276_GetPacketRxGain( void );                      //获取数据时的增益值
+
+int8_t SX1276_GetPacketSnr( void );							 //获取数据时的信噪比值，信号和噪声的比值，信噪比越高，说明信号干扰越小。
+
+double SX1276_GetPacketRssi( void );  					     //获取数据是的无线信号强度
+
+/*!
+ * \brief Gets the AFC value measured while receiving the packet
+ *
+ * \retval afcValue Current AFC value in [Hz]
+ */
+uint32_t SX1276GetPacketAfc( void );                          //此函数不知道作用
+
+
+void SX1276StartRx( void );                                   //开始接收
+
+void SX1276GetRxPacket( void *buffer, uint16_t *size );       //得到接收的数据
+
+int SX1276GetRx(void *buffer, uint16_t *size);                //应用接收数据，无数据时阻塞
+
+void SX1276SetTxPacket( const void *buffer, uint16_t size );  //发送数据
+
+void SX1276SetTx( const void *buffer, uint16_t size );        //应用发送数据
+
+uint8_t SX1276GetRFState( void );       				      //得到RFLRState状态
+
+void SX1276SetRFState( uint8_t state );						  //设置RFLRState状态，RFLRState的值决定了下面的函数处理哪一步的代码
+
+uint32_t SX1276Process( void );         			          //SX1276模块接发收数据的处理函数
+
+uint32_t SX1276ChannelEmpty( void );
+
+#endif 

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/timer/Kconfig

@@ -0,0 +1,16 @@
+menuconfig BSP_USING_HWTIMER
+    bool "Using hwtimer"
+    default y
+    select RESOURCES_HWTIMER
+
+if BSP_USING_HWTIMER
+    config HWTIMER_BUS_NAME_0
+        string "timer 0 bus 0 name"
+        default "timer0"
+    config HWTIMER_0_DEVICE_NAME_0
+        string "timer 0 bus 0 device 0 name"
+        default "timer0_dev0" 
+    config HWTIMER_DRIVER_NAME_0
+        string "timer 0 bus 0 driver name"
+        default "timer0_drv"
+endif

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/timer/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_hwtimer.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/timer/connect_hwtimer.c

@@ -0,0 +1,189 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_hwtimer.c
+* @brief support edu-arm32-board hwtimer function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <connect_hwtimer.h>
+
+#define TMR0_CMP_VAL 1000
+#define TMR0x                          ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE)
+#define TMR0_CH_x                      (TMR0_CH_A)
+#define INTSEL_REG                     ((uint32_t)(&CM_INTC->SEL0))
+#define TIMER0_IRQn                    (18)
+
+
+void (*callback_function)(void *) ;
+
+static void Timer0Callback(int vector, void *param)
+{
+    TMR0_SetCountValue(TMR0x, TMR0_CH_x, 0);
+    if (callback_function) {
+        callback_function(param);
+    }
+
+}
+
+static uint32 HwtimerOpen(void *dev)
+{
+    struct HwtimerHardwareDevice *hwtimer_dev = dev;
+    stc_tmr0_init_t stcTmr0Init;
+    /* Enable timer0 peripheral clock */
+    FCG_Fcg2PeriphClockCmd(PWC_FCG2_TMR0_1, ENABLE);
+
+    /* TIMER0 basetimer function initialize */
+    (void)TMR0_StructInit(&stcTmr0Init);
+    stcTmr0Init.u32ClockDiv = TMR0_CLK_DIV128;        /* Config clock division */
+    stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK;          /* Chose clock source */
+    stcTmr0Init.u32Func = TMR0_FUNC_CMP;            /* Timer0 compare mode */
+    stcTmr0Init.u16CompareValue = TMR0_CMP_VAL;             /* Set compare register data */
+    (void)TMR0_Init(TMR0x, TMR0_CH_x, &stcTmr0Init);
+
+    // DelayKTask(1);
+    // /* Set internal hardware capture source */
+    // TMR0_SetTriggerSrc(EVT_PORT_EIRQ0);
+
+    // DelayKTask(1);
+
+    return EOK;
+}
+
+static uint32 HwtimerClose(void *dev)
+{
+    /* Timer0 interrupt function Disable */
+    TMR0_IntCmd(TMR0x, TMR0_INT_CMP_A, DISABLE);
+    return EOK;
+}
+
+/*manage the hwtimer device operations*/
+static const struct HwtimerDevDone dev_done =
+{
+    .open = HwtimerOpen,
+    .close = HwtimerClose,
+    .write = NONE,
+    .read = NONE,
+};
+
+static uint32 HwtimerDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    __IO uint32_t *INTC_SELx;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            INTC_SELx = (__IO uint32_t *)(INTSEL_REG+ 4U * (uint32_t)(TIMER0_IRQn));
+            WRITE_REG32(*INTC_SELx, EVT_SRC_TMR0_1_CMP_A);
+            callback_function = (void (*)(void *param))configure_info->private_data;
+            isrManager.done->registerIrq(TIMER0_IRQn+16,Timer0Callback,NULL);   
+            isrManager.done->enableIrq(TIMER0_IRQn);
+            TMR0_IntCmd(TMR0x, TMR0_INT_CMP_A, ENABLE);
+            break;
+        case OPE_CFG:
+            TMR0_ClearStatus(TMR0x, TMR0_FLAG_CMP_A);
+            TMR0_SetCompareValue(TMR0x, TMR0_CH_x, *((int *)configure_info->private_data) );
+            /* Timer0 interrupt function Enable */
+            TMR0_SetCountValue(TMR0x, TMR0_CH_x, 0x0000); 
+            TMR0_Start(TMR0x, TMR0_CH_x);
+            break;
+        default:
+            break;
+    }
+    return ret;
+}
+
+/*Init hwtimer bus*/
+static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the hwtimer bus */
+    ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_0);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the hwtimer driver*/
+    hwtimer_driver->configure = &(HwtimerDrvConfigure);
+    ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_0);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the hwtimer driver to the hwtimer bus*/
+    ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_0, HWTIMER_BUS_NAME_0);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+/*Attach the hwtimer device to the hwtimer bus*/
+static int BoardHwtimerDevBend(void)
+{
+    x_err_t ret = EOK;
+    static struct HwtimerHardwareDevice hwtimer_device_0;
+    memset(&hwtimer_device_0, 0, sizeof(struct HwtimerHardwareDevice));
+
+    hwtimer_device_0.dev_done = &dev_done;
+
+    ret = HwtimerDeviceRegister(&hwtimer_device_0, NONE, HWTIMER_0_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("BoardHwtimerDevBend HwtimerDeviceRegister device %s error %d\n", HWTIMER_0_DEVICE_NAME_0, ret);
+        return ERROR;
+    }
+
+    ret = HwtimerDeviceAttachToBus(HWTIMER_0_DEVICE_NAME_0, HWTIMER_BUS_NAME_0);
+    if (EOK != ret) {
+        KPrintf("BoardHwtimerDevBend HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_0_DEVICE_NAME_0, ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+/*EDU-ARM32 BOARD HWTIMER INIT*/
+int HwTimerInit(void)
+{
+    x_err_t ret = EOK;
+    static struct HwtimerBus hwtimer_bus;
+    memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus));
+
+    static struct HwtimerDriver hwtimer_driver;
+    memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver));
+
+    ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardHwtimerDevBend();
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/watchdog/Kconfig

@@ -0,0 +1,15 @@
+if BSP_USING_WDT
+    config WDT_BUS_NAME_0
+        string "watchdog bus 0 name"
+        default "wdt0"
+
+    config WDT_DRIVER_NAME_0
+        string "watchdog driver 0 name"
+        default "wdt0_drv"
+
+    config WDT_0_DEVICE_NAME_0
+        string "watchdog device 0 name"
+        default "wdt0_dev0"
+endif
+
+

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/watchdog/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_wdt.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/xishutong-arm32/third_party_driver/watchdog/connect_wdt.c

@@ -0,0 +1,145 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_wdt.c
+* @brief support edu-arm32-board watchdog function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2023-02-02
+*/
+
+#include <connect_wdt.h>
+
+#define WDT_COUNT_CYCLE 65536U
+
+static uint32 WdtOpen(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    stc_wdt_init_t stcWdtInit;
+    stcWdtInit.u32CountPeriod   = WDT_CNT_PERIOD65536;
+    stcWdtInit.u32ClockDiv      = WDT_CLK_DIV1024;
+    stcWdtInit.u32RefreshRange  = WDT_RANGE_0TO25PCT;
+    stcWdtInit.u32LPMCount      = WDT_LPM_CNT_STOP;
+    stcWdtInit.u32ExceptionType = WDT_EXP_TYPE_RST;
+    (void)WDT_Init(&stcWdtInit);
+    return EOK;
+}
+
+static uint32 WdtConfigure(void *drv, struct BusConfigureInfo *args)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(args);
+
+    stc_wdt_init_t stcWdtInit;
+
+    int period_option = *((int*)args->private_data);
+    if(period_option<=256){
+        period_option = WDT_CNT_PERIOD256;
+    }else if(period_option<=4096){
+        period_option = WDT_CNT_PERIOD4096;
+    }else if(period_option<=16384){
+        period_option = WDT_CNT_PERIOD16384;
+    }else{
+        period_option = WDT_CNT_PERIOD65536;
+    }
+
+    switch (args->configure_cmd)
+    {
+        case OPER_WDT_SET_TIMEOUT:
+        stcWdtInit.u32CountPeriod    = period_option;
+        stcWdtInit.u32ClockDiv       = WDT_CLK_DIV1024;
+        stcWdtInit.u32RefreshRange   = WDT_RANGE_0TO25PCT;
+        stcWdtInit.u32LPMCount       = WDT_LPM_CNT_STOP;
+        stcWdtInit.u32ExceptionType  = WDT_EXP_TYPE_RST;
+        if (WDT_Init(&stcWdtInit) != 0) {
+            return ERROR;
+        }
+        /* the chip SDK's feature:to start up watchdog counter, feed dog first after initialization*/
+        WDT_FeedDog();
+        break;
+        case OPER_WDT_KEEPALIVE:
+            /* must wait for count lower than 25%(division by 4) for a feed as RefreshRange is set as 0TO25PCT*/
+            if (WDT_GetCountValue() < WDT_COUNT_CYCLE/4){  
+                WDT_FeedDog();
+            }
+            break;
+        default:
+            return ERROR;
+    }
+    return EOK;
+}
+
+static const struct WdtDevDone dev_done =
+{
+    WdtOpen,
+    NONE,
+    NONE,
+    NONE,
+};
+
+/**
+ * @description: Watchdog function
+ * @return success: EOK, failure: other
+ */
+int StartWatchdog(void)
+{
+    //add feed watchdog task function
+
+    return EOK;
+}
+
+int HwWdtInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct WdtBus wdt0;
+
+    ret = WdtBusInit(&wdt0, WDT_BUS_NAME_0);
+    if (ret != EOK) {
+        KPrintf("Watchdog bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct WdtDriver drv0;
+    drv0.configure = WdtConfigure;
+    
+    ret = WdtDriverInit(&drv0, WDT_DRIVER_NAME_0);
+    if (ret != EOK) {
+        KPrintf("Watchdog driver init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = WdtDriverAttachToBus(WDT_DRIVER_NAME_0, WDT_BUS_NAME_0);
+    if (ret != EOK) {
+        KPrintf("Watchdog driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct WdtHardwareDevice dev0;
+    dev0.dev_done = &dev_done;
+
+    ret = WdtDeviceRegister(&dev0, WDT_0_DEVICE_NAME_0);
+    if (ret != EOK) {
+        KPrintf("Watchdog device register error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = WdtDeviceAttachToBus(WDT_0_DEVICE_NAME_0, WDT_BUS_NAME_0);
+    if (ret != EOK) {
+        KPrintf("Watchdog device register error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/xiwangtong-arm32/third_party_driver/ethernet/eth_netdev.c

@@ -76,6 +76,7 @@ static int lwip_netdev_set_addr_info(struct netdev* netdev, ip_addr_t* ip_addr,
             netif_set_gw((struct netif*)netdev->user_data, ip_2_ip4(gw));
         }
     }
+    return 0;
 }
 
 #ifdef LWIP_DNS
@@ -92,7 +93,7 @@ static int lwip_netdev_set_dns_server(struct netdev* netdev, uint8_t dns_num, ip
 }
 #endif
 
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
 static int lwip_netdev_set_dhcp(struct netdev* netdev, bool is_enabled)
 {
     netdev_low_level_set_dhcp_status(netdev, is_enabled);
@@ -120,7 +121,7 @@ static const struct netdev_ops lwip_netdev_ops = {
 #ifdef LWIP_DNS
     .set_dns_server = lwip_netdev_set_dns_server,
 #endif
-#ifdef LWIP_DHCP
+#if LWIP_DHCP
     .set_dhcp = lwip_netdev_set_dhcp,
 #endif
     .set_default = lwip_netdev_set_default,
@@ -180,9 +181,9 @@ int lwip_netdev_add(struct netif* lwip_netif)
     netdev->ops = &lwip_netdev_ops;
     netdev->hwaddr_len = lwip_netif->hwaddr_len;
     memcpy(netdev->hwaddr, lwip_netif->hwaddr, lwip_netif->hwaddr_len);
-    netdev->ip_addr = lwip_netif->ip_addr;
+    netdev->ip_addr = &lwip_netif->ip_addr;
-    netdev->gw = lwip_netif->gw;
+    netdev->gw = &lwip_netif->gw;
-    netdev->netmask = lwip_netif->netmask;
+    netdev->netmask = &lwip_netif->netmask;
 
     return result;
 }

Ubiquitous/XiZi_IIoT/compiler.mk

@@ -2,6 +2,8 @@ ifeq ($(COMPILE_TYPE), COMPILE_MUSL)
 SRC_DIR_TEMP := $(MUSL_DIR)
 else ifeq ($(COMPILE_TYPE), COMPILE_LWIP) 
 SRC_DIR_TEMP := $(LWIP_DIR)
+else ifeq ($(COMPILE_TYPE), COMPILE_MONGOOSE)
+SRC_DIR_TEMP := $(MONGOOSE_DIR)
 else
 SRC_DIR_TEMP := $(SRC_DIR) 
 endif
@@ -9,6 +11,7 @@ endif
 SRC_DIR :=
 MUSL_DIR :=
 LWIP_DIR :=
+MONGOOSE_DIR :=
 
 ifeq ($(USE_APP_INCLUDEPATH), y)
 	include $(KERNEL_ROOT)/path_app.mk

Ubiquitous/XiZi_IIoT/fs/shared/include/iot-vfs_posix.h

@@ -15,7 +15,8 @@
 
 #include <iot-vfs.h>
 
-typedef void DIR;
+#include <ff.h>
+// typedef void void;
 
 #if defined(LIB_NEWLIB) && defined(_EXFUN)
 _READ_WRITE_RETURN_TYPE _EXFUN(read, (int __fd, void *__buf, size_t __nbyte));
@@ -39,15 +40,15 @@ int fsync(int fd);
 int ftruncate(int fd, off_t length);
 
 int mkdir(const char *path, mode_t mode);
-DIR *opendir(const char *path);
+void* opendir(const char* path);
-int closedir(DIR *dirp);
+int closedir(void* dirp);
-struct dirent *readdir(DIR *dirp);
+struct dirent* readdir(void* dirp);
 int rmdir(const char *path);
 int chdir(const char *path);
 char *getcwd(char *buf, size_t size);
-long telldir(DIR *dirp);
+long telldir(void* dirp);
-void seekdir(DIR *dirp, off_t offset);
+void seekdir(void* dirp, off_t offset);
-void rewinddir(DIR *dirp);
+void rewinddir(void* dirp);
 
 int statfs(const char *path, struct statfs *buf);
 

Ubiquitous/XiZi_IIoT/fs/shared/src/iot-vfs.c

@@ -906,7 +906,7 @@ err:
     return 0;
 }
 
-DIR *opendir(const char *path)
+void* opendir(const char* path)
 {
     struct FileDescriptor *fdp;
     struct MountPoint *mp;
@@ -968,7 +968,7 @@ err:
     return fdp;
 }
 
-int closedir(DIR *dirp)
+int closedir(void* dirp)
 {
     struct FileDescriptor *fdp = dirp;
     int ret;
@@ -999,7 +999,7 @@ int closedir(DIR *dirp)
 }
 
 static struct dirent dirent;
-struct dirent *readdir(DIR *dirp)
+struct dirent* readdir(void* dirp)
 {
     struct FileDescriptor *fdp = dirp;
     int ret;
@@ -1036,7 +1036,7 @@ int rmdir(const char *path)
 int chdir(const char *path)
 {
     char *abspath;
-    DIR *dirp;
+    void* dirp;
 
     if (path == NULL) {
         SYS_ERR("%s: invalid path\n", __func__);
@@ -1074,7 +1074,7 @@ char *getcwd(char *buf, size_t size)
     return buf;
 }
 
-void seekdir(DIR *dirp, off_t offset)
+void seekdir(void* dirp, off_t offset)
 {
     struct FileDescriptor *fdp = dirp;
 
@@ -1093,7 +1093,7 @@ void seekdir(DIR *dirp, off_t offset)
     fdp->mntp->fs->seekdir(fdp, offset);
 }
 
-void rewinddir(DIR *dirp)
+void rewinddir(void* dirp)
 {
     struct FileDescriptor *fdp = dirp;
 

Ubiquitous/XiZi_IIoT/kernel/include/xs_kdbg.h

@@ -44,15 +44,16 @@ extern "C" {
 
 #define MSGQUEUE_DEBUG 0
 #define FILESYS_DEBUG 0
-#define NETDEV_DEBUG 0
+#define NETDEV_DEBUG 1
 #define WEBNET_DEBUG 0
 #define WIZNET_DEBUG 0
 
-#define SYS_KDEBUG_LOG(section, information) \
+#define SYS_KDEBUG_LOG(section, information)         \
-    do {                                     \
+    do {                                             \
-        if (section) {                       \
+        if (section) {                               \
-            KPrintf information;             \
+            KPrintf("[%s:%d] ", __func__, __LINE__); \
-        }                                    \
+            KPrintf information;                     \
+        }                                            \
     } while (0)
 
 #define KDYN_NONE 0

Ubiquitous/XiZi_IIoT/link.mk

@@ -3,7 +3,7 @@ OBJS := $(shell cat make.obj)
 $(TARGET): $(OBJS) 
 	@echo ------------------------------------------------
 	@echo link $(TARGET)
-	@$(CROSS_COMPILE)g++ -o $@ $($(LINK_FLAGS)) $(OBJS) $(LINK_LWIP) $(LINK_MUSLLIB) $(LIBCC)
+	@$(CROSS_COMPILE)g++ -o $@ $($(LINK_FLAGS)) $(OBJS) $(LINK_LWIP) $(LINK_MUSLLIB) $(LINK_MONGOOSE) $(LIBCC)
 	@echo ------------------------------------------------
 	@$(CROSS_COMPILE)objcopy -O binary $@ XiZi-$(BOARD)$(COMPILE_TYPE).bin
 	@$(CROSS_COMPILE)objdump -S $@ > XiZi-$(BOARD)$(COMPILE_TYPE).asm

Ubiquitous/XiZi_IIoT/link_mongoose.mk

@@ -0,0 +1,9 @@
+OBJS := $(shell cat make.obj)
+
+$(TARGET): $(OBJS) 
+	@echo ------------------------------------------------
+	@echo link $(TARGET)
+	@$(CROSS_COMPILE)ar -r $@  $(OBJS)
+	@echo ------------------------------------------------
+	@$(CROSS_COMPILE)objcopy $@ $(TARGET)
+	@$(CROSS_COMPILE)size $@

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/api/sockets.c

@@ -640,7 +640,8 @@ lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
   LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
   sock = get_socket(s);
   if (!sock) {
-    return -1;
+      KPrintf("sock = get_socket(s);\n");
+      return -1;
   }
 
   /* wait for a new connection */
@@ -655,6 +656,7 @@ lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
       sock_set_errno(sock, err_to_errno(err));
     }
     done_socket(sock);
+    KPrintf("err = netconn_accept(sock->conn, &newconn);\n");
     return -1;
   }
   LWIP_ASSERT("newconn != NULL", newconn != NULL);
@@ -664,6 +666,7 @@ lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
     netconn_delete(newconn);
     sock_set_errno(sock, ENFILE);
     done_socket(sock);
+    KPrintf("newsock = alloc_socket(newconn, 1);\n");
     return -1;
   }
   LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET));
@@ -701,6 +704,7 @@ lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
       free_socket(nsock, 1);
       sock_set_errno(sock, err_to_errno(err));
       done_socket(sock);
+      KPrintf("err = netconn_peer(newconn, &naddr, &port);\n");
       return -1;
     }
 
@@ -1242,6 +1246,8 @@ lwip_recvfrom(int s, void *mem, size_t len, int flags,
     if (err != ERR_OK) {
       LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom[UDP/RAW](%d): buf == NULL, error is \"%s\"!\n",
                                   s, lwip_strerr(err)));
+      KPrintf("lwip_recvfrom[UDP/RAW](%d): buf == NULL, error is \"%s\"!\n",
+          s, lwip_strerr(err));
       sock_set_errno(sock, err_to_errno(err));
       done_socket(sock);
       return -1;

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h

@@ -36,6 +36,7 @@
 #ifndef LWIP_DEBUG
 #define LWIP_DEBUG 1
 // #define LWIP_SOCKET_DEBUG
+// #define LWIP_SOCKETS_DEBUG
 // #define LWIP_TCPIP_DEBUG
 // #define LWIP_MEMP_DEBUG
 // #define LWIP_PBUF_DEBUG
@@ -271,13 +272,16 @@ a lot of data that needs to be copied, this should be set high. */
 #define MEMP_NUM_PBUF 32
 /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
    per active UDP "connection". */
-#define MEMP_NUM_UDP_PCB 4
+#define MEMP_NUM_UDP_PCB 32
 /* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
    connections. */
-#define MEMP_NUM_TCP_PCB 64
+#define MEMP_NUM_TCP_PCB 32
+#define MEMP_NUM_RAW_PCB 32
+#define MEMP_NUM_REASSDATA 32
+#define MEMP_NUM_NETCONN 32
 /* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
    connections. */
-#define MEMP_NUM_TCP_PCB_LISTEN 2
+#define MEMP_NUM_TCP_PCB_LISTEN 32
 /* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
    segments. */
 #define MEMP_NUM_TCP_SEG 256
@@ -383,12 +387,6 @@ a lot of data that needs to be copied, this should be set high. */
 /* ---------- ICMP options ---------- */
 #define LWIP_ICMP 1
 
-/* ---------- DHCP options ---------- */
-/* Define LWIP_DHCP to 1 if you want DHCP configuration of
-   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
-   turning this on does currently not work. */
-#define LWIP_DHCP 1
-
 /* ---------- UDP options ---------- */
 #define LWIP_UDP 1
 #define UDP_TTL 255
@@ -412,7 +410,7 @@ The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums
  - To use this feature let the following define uncommented.
  - To disable it and process by CPU comment the  the checksum.
 */
-#define CHECKSUM_BY_HARDWARE
+// #define CHECKSUM_BY_HARDWARE
 
 #ifdef CHECKSUM_BY_HARDWARE
 /* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
@@ -520,7 +518,7 @@ The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums
 /* ---------- DHCP options ---------- */
 /* Define LWIP_DHCP to 1 if you want DHCP configuration of
    interfaces. */
-#define LWIP_DHCP 1
+#define LWIP_DHCP 0
 
 /* 1 if you want to do an ARP check on the offered address
    (recommended). */

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/sys_arch.c

@@ -76,9 +76,9 @@ char lwip_eth0_ipaddr[20] = { 192, 168, 130, 77 };
 char lwip_eth0_netmask[20] = { 255, 255, 254, 0 };
 char lwip_eth0_gwaddr[20] = { 192, 168, 130, 1 };
 
-char lwip_eth1_ipaddr[20] = { 192, 168, 130, 99 };
+char lwip_eth1_ipaddr[20] = { 192, 168, 131, 88 };
 char lwip_eth1_netmask[20] = { 255, 255, 254, 0 };
-char lwip_eth1_gwaddr[20] = { 192, 168, 130, 23 };
+char lwip_eth1_gwaddr[20] = { 192, 168, 130, 1 };
 
 char lwip_flag = 0;
 
@@ -93,6 +93,13 @@ sys_sem_t* get_eth_recv_sem()
     return &g_recv_sem;
 }
 
+struct netif gnetif2;
+sys_sem_t* get_eth_recv_sem2()
+{
+    static sys_sem_t g_recv_sem = 0;
+    return &g_recv_sem;
+}
+
 void sys_init(void)
 {
     // do nothing
@@ -332,136 +339,104 @@ ip4_addr_t ipaddr;
 ip4_addr_t netmask;
 ip4_addr_t gw;
 
-void lwip_config_input(struct netif* net)
+void lwip_config_input(int eport, struct netif* net)
 {
     sys_thread_t th_id = 0;
 
-    th_id = sys_thread_new("eth_input", ethernetif_input, net, LWIP_TASK_STACK_SIZE, 30);
+    if (eport == 0) {
-
+        th_id = sys_thread_new("eth_input", ethernetif_input, net, LWIP_TASK_STACK_SIZE, 30);
-    // if (th_id >= 0) {
+    } else if (eport == 1) {
-    //     lw_print("%s %d successfully!\n", __func__, th_id);
+#ifdef NETIF_ENET1_INIT_FUNC
-    // } else {
+        th_id = sys_thread_new("eth_input2", ethernetif_input2, net, LWIP_TASK_STACK_SIZE, 30);
-    //     lw_print("%s failed!\n", __func__);
+#endif
-    // }
+    }
 }
 
 void lwip_config_tcp(uint8_t enet_port, char* ip, char* mask, char* gw)
 {
-    static char is_init = 0;
+    static char is_init_0 = 0;
-    if (is_init != 0) {
+    static char is_init_1 = 0;
-        return;
+    if (is_init_0 == 0 && is_init_1 == 0) {
+        sys_sem_new(get_eth_recv_sem(), 0);
+        sys_sem_new(get_eth_recv_sem2(), 0);
+
+        if (chk_lwip_bit(LWIP_INIT_FLAG)) {
+            lw_print("lw: [%s] already ...\n", __func__);
+        }
+
+        set_lwip_bit(LWIP_INIT_FLAG);
+
+        tcpip_init(NULL, NULL);
     }
-    is_init = 1;
-
-    sys_sem_new(get_eth_recv_sem(), 0);
-
-    ip4_addr_t net_ipaddr, net_netmask, net_gw;
-    char* eth_cfg;
-
-    eth_cfg = ethernetif_config_enet_set(enet_port);
-
-    if (chk_lwip_bit(LWIP_INIT_FLAG)) {
-        lw_print("lw: [%s] already ...\n", __func__);
-        return;
-    }
-
-    set_lwip_bit(LWIP_INIT_FLAG);
-
-    tcpip_init(NULL, NULL);
 
     lw_print("lw: [%s] start ...\n", __func__);
 
+    char* eth_cfg = ethernetif_config_enet_set(enet_port);
+    ip4_addr_t net_ipaddr, net_netmask, net_gw;
     IP4_ADDR(&net_ipaddr, ip[0], ip[1], ip[2], ip[3]);
     IP4_ADDR(&net_netmask, mask[0], mask[1], mask[2], mask[3]);
     IP4_ADDR(&net_gw, gw[0], gw[1], gw[2], gw[3]);
 
     if (0 == enet_port) {
+        if (is_init_0 == 1) {
+            return;
+        }
+#ifndef NETIF_ENET0_INIT_FUNC
+        lw_print("Not Netif driver for Eport 0\n");
+        return;
+#endif
 #ifdef NETIF_ENET0_INIT_FUNC
+        lw_print("Add netif eport 0\n");
         netif_add(&gnetif, &net_ipaddr, &net_netmask, &net_gw, eth_cfg, NETIF_ENET0_INIT_FUNC,
             tcpip_input);
-#endif
-    } else if (1 == enet_port) {
-#ifdef NETIF_ENET1_INIT_FUNC
-        netif_add(&gnetif, &net_ipaddr, &net_netmask, &net_gw, eth_cfg, NETIF_ENET1_INIT_FUNC,
-            tcpip_input);
-#endif
-    }
 
-    netif_set_default(&gnetif);
+        netif_set_default(&gnetif);
-    netif_set_up(&gnetif);
-
-    lw_print("\r\n************************************************\r\n");
-    lw_print(" Network Configuration\r\n");
-    lw_print("************************************************\r\n");
-    lw_print(" IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&net_ipaddr)[0], ((u8_t*)&net_ipaddr)[1],
-        ((u8_t*)&net_ipaddr)[2], ((u8_t*)&net_ipaddr)[3]);
-    lw_print(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&net_netmask)[0], ((u8_t*)&net_netmask)[1],
-        ((u8_t*)&net_netmask)[2], ((u8_t*)&net_netmask)[3]);
-    lw_print(" IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&net_gw)[0], ((u8_t*)&net_gw)[1],
-        ((u8_t*)&net_gw)[2], ((u8_t*)&net_gw)[3]);
-    lw_print("************************************************\r\n");
-
-    lwip_config_input(&gnetif);
-}
-
-void lwip_config_net(uint8_t enet_port, char* ip, char* mask, char* gw)
-{
-    ip4_addr_t net_ipaddr, net_netmask, net_gw;
-    char* eth_cfg;
-
-    eth_cfg = ethernetif_config_enet_set(enet_port);
-
-    if (chk_lwip_bit(LWIP_INIT_FLAG)) {
-        lw_print("lw: [%s] already ...\n", __func__);
-
-        IP4_ADDR(&net_ipaddr, ip[0], ip[1], ip[2], ip[3]);
-        IP4_ADDR(&net_netmask, mask[0], mask[1], mask[2], mask[3]);
-        IP4_ADDR(&net_gw, gw[0], gw[1], gw[2], gw[3]);
-
-        // update ip addr
-        netif_set_down(&gnetif);
-        netif_set_gw(&gnetif, &net_gw);
-        netif_set_netmask(&gnetif, &net_netmask);
-        netif_set_ipaddr(&gnetif, &net_ipaddr);
         netif_set_up(&gnetif);
-        return;
-    }
-    set_lwip_bit(LWIP_INIT_FLAG);
 
-    lw_print("lw: [%s] start ...\n", __func__);
+        lw_print("\r\n************************************************\r\n");
-
+        lw_print(" Network Configuration\r\n");
-    IP4_ADDR(&net_ipaddr, ip[0], ip[1], ip[2], ip[3]);
+        lw_print("************************************************\r\n");
-    IP4_ADDR(&net_netmask, mask[0], mask[1], mask[2], mask[3]);
+        lw_print(" IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&net_ipaddr)[0], ((u8_t*)&net_ipaddr)[1],
-    IP4_ADDR(&net_gw, gw[0], gw[1], gw[2], gw[3]);
-
-    lwip_init();
-
-    if (0 == enet_port) {
-#ifdef NETIF_ENET0_INIT_FUNC
-        netif_add(&gnetif, &net_ipaddr, &net_netmask, &net_gw, eth_cfg, NETIF_ENET0_INIT_FUNC,
-            ethernet_input);
-#endif
-    } else if (1 == enet_port) {
-#ifdef NETIF_ENET1_INIT_FUNC
-        netif_add(&gnetif, &net_ipaddr, &net_netmask, &net_gw, eth_cfg, NETIF_ENET1_INIT_FUNC,
-            ethernet_input);
-#endif
-    }
-
-    netif_set_default(&gnetif);
-    netif_set_up(&gnetif);
-
-    if (chk_lwip_bit(LWIP_PRINT_FLAG)) {
-        lw_notice("\r\n************************************************\r\n");
-        lw_notice(" Network Configuration\r\n");
-        lw_notice("************************************************\r\n");
-        lw_notice(" IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&net_ipaddr)[0], ((u8_t*)&net_ipaddr)[1],
             ((u8_t*)&net_ipaddr)[2], ((u8_t*)&net_ipaddr)[3]);
-        lw_notice(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&net_netmask)[0], ((u8_t*)&net_netmask)[1],
+        lw_print(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&net_netmask)[0], ((u8_t*)&net_netmask)[1],
             ((u8_t*)&net_netmask)[2], ((u8_t*)&net_netmask)[3]);
-        lw_notice(" IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&net_gw)[0], ((u8_t*)&net_gw)[1],
+        lw_print(" IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&net_gw)[0], ((u8_t*)&net_gw)[1],
             ((u8_t*)&net_gw)[2], ((u8_t*)&net_gw)[3]);
-        lw_notice("************************************************\r\n");
+        lw_print("************************************************\r\n");
+
+        lwip_config_input(enet_port, &gnetif);
+        is_init_0 = 1;
+#endif
+
+    } else if (1 == enet_port) {
+        if (is_init_1 == 1) {
+            return;
+        }
+#ifndef NETIF_ENET1_INIT_FUNC
+        lw_print("Not Netif driver for Eport 1\n");
+        return;
+#endif
+#ifdef NETIF_ENET1_INIT_FUNC
+        lw_print("Add netif eport 1\n");
+        netif_add(&gnetif2, &net_ipaddr, &net_netmask, &net_gw, eth_cfg, NETIF_ENET1_INIT_FUNC,
+            tcpip_input);
+
+        // netif_set_default(&gnetif2);
+        netif_set_up(&gnetif2);
+
+        lw_print("\r\n************************************************\r\n");
+        lw_print(" Network Configuration\r\n");
+        lw_print("************************************************\r\n");
+        lw_print(" IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&net_ipaddr)[0], ((u8_t*)&net_ipaddr)[1],
+            ((u8_t*)&net_ipaddr)[2], ((u8_t*)&net_ipaddr)[3]);
+        lw_print(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&net_netmask)[0], ((u8_t*)&net_netmask)[1],
+            ((u8_t*)&net_netmask)[2], ((u8_t*)&net_netmask)[3]);
+        lw_print(" IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&net_gw)[0], ((u8_t*)&net_gw)[1],
+            ((u8_t*)&net_gw)[2], ((u8_t*)&net_gw)[3]);
+        lw_print("************************************************\r\n");
+
+        lwip_config_input(enet_port, &gnetif2);
+        is_init_1 = 1;
+#endif
     }
-    lwip_config_input(&gnetif);
+}
-}

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/sys_arch.h

@@ -101,6 +101,8 @@ extern char lwip_eth1_gwaddr[];
 
 extern struct netif gnetif;
 extern sys_sem_t* get_eth_recv_sem();
+extern struct netif gnetif2;
+extern sys_sem_t* get_eth_recv_sem2();
 
 void lwip_tcp_init(void);
 void lwip_config_net(uint8_t enet_port, char *ip, char *mask, char *gw);

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/core/ipv4/ip4.c

@@ -228,6 +228,95 @@ ip4_route(const ip4_addr_t *dest)
   return netif_default;
 }
 
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ *
+ * @param dest the destination IP address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif*
+ip4_route2(const ip4_addr_t* src, const ip4_addr_t* dest)
+{
+#if !LWIP_SINGLE_NETIF
+    struct netif* netif;
+    LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_MULTICAST_TX_OPTIONS
+    /* Use administratively selected interface for multicast by default */
+    if (ip4_addr_ismulticast(dest) && ip4_default_multicast_netif) {
+        return ip4_default_multicast_netif;
+    }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+    /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
+    LWIP_UNUSED_ARG(dest);
+
+    /* iterate through netifs */
+    NETIF_FOREACH(netif)
+    {
+        /* is the netif up, does it have a link and a valid address? */
+        if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+
+            /* network mask matches? */
+            // if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
+            if (ip4_addr_cmp(src, netif_ip4_addr(netif))) {
+                /* return netif on which to forward IP packet */
+                return netif;
+            }
+            /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
+            if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
+                /* return netif on which to forward IP packet */
+                return netif;
+            }
+        }
+    }
+
+#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF
+    /* loopif is disabled, looopback traffic is passed through any netif */
+    if (ip4_addr_isloopback(dest)) {
+        /* don't check for link on loopback traffic */
+        if (netif_default != NULL && netif_is_up(netif_default)) {
+            return netif_default;
+        }
+        /* default netif is not up, just use any netif for loopback traffic */
+        NETIF_FOREACH(netif)
+        {
+            if (netif_is_up(netif)) {
+                return netif;
+            }
+        }
+        return NULL;
+    }
+#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
+
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+    netif = LWIP_HOOK_IP4_ROUTE_SRC(NULL, dest);
+    if (netif != NULL) {
+        return netif;
+    }
+#elif defined(LWIP_HOOK_IP4_ROUTE)
+    netif = LWIP_HOOK_IP4_ROUTE(dest);
+    if (netif != NULL) {
+        return netif;
+    }
+#endif
+#endif /* !LWIP_SINGLE_NETIF */
+
+    if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
+        /* No matching netif found and default netif is not usable.
+           If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %" U16_F ".%" U16_F ".%" U16_F ".%" U16_F "\n", ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+        IP_STATS_INC(ip.rterr);
+        MIB2_STATS_INC(mib2.ipoutnoroutes);
+        return NULL;
+    }
+
+    return netif_default;
+}
+
 #if IP_FORWARD
 /**
  * Determine whether an IP address is in a reserved set of addresses

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/ip4.h

@@ -63,39 +63,41 @@ extern "C" {
 
 #define ip_init() /* Compatibility define, no init needed. */
 struct netif *ip4_route(const ip4_addr_t *dest);
+struct netif* ip4_route2(const ip4_addr_t* src, const ip4_addr_t* dest);
 #if LWIP_IPV4_SRC_ROUTING
-struct netif *ip4_route_src(const ip4_addr_t *src, const ip4_addr_t *dest);
+struct netif* ip4_route_src(const ip4_addr_t* src, const ip4_addr_t* dest);
 #else /* LWIP_IPV4_SRC_ROUTING */
-#define ip4_route_src(src, dest) ip4_route(dest)
+// #define ip4_route_src(src, dest) ip4_route(dest)
+#define ip4_route_src(src, dest) ip4_route2(src, dest)
 #endif /* LWIP_IPV4_SRC_ROUTING */
-err_t ip4_input(struct pbuf *p, struct netif *inp);
+err_t ip4_input(struct pbuf* p, struct netif* inp);
-err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+err_t ip4_output(struct pbuf* p, const ip4_addr_t* src, const ip4_addr_t* dest,
-       u8_t ttl, u8_t tos, u8_t proto);
+    u8_t ttl, u8_t tos, u8_t proto);
-err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+err_t ip4_output_if(struct pbuf* p, const ip4_addr_t* src, const ip4_addr_t* dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+    u8_t ttl, u8_t tos, u8_t proto, struct netif* netif);
-err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+err_t ip4_output_if_src(struct pbuf* p, const ip4_addr_t* src, const ip4_addr_t* dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+    u8_t ttl, u8_t tos, u8_t proto, struct netif* netif);
 #if LWIP_NETIF_USE_HINTS
-err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+    err_t ip4_output_hinted(struct pbuf* p, const ip4_addr_t* src, const ip4_addr_t* dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif_hint *netif_hint);
+        u8_t ttl, u8_t tos, u8_t proto, struct netif_hint* netif_hint);
 #endif /* LWIP_NETIF_USE_HINTS */
 #if IP_OPTIONS_SEND
-err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+    err_t ip4_output_if_opt(struct pbuf* p, const ip4_addr_t* src, const ip4_addr_t* dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+        u8_t ttl, u8_t tos, u8_t proto, struct netif* netif, void* ip_options,
-       u16_t optlen);
+        u16_t optlen);
-err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+    err_t ip4_output_if_opt_src(struct pbuf* p, const ip4_addr_t* src, const ip4_addr_t* dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+        u8_t ttl, u8_t tos, u8_t proto, struct netif* netif, void* ip_options,
-       u16_t optlen);
+        u16_t optlen);
 #endif /* IP_OPTIONS_SEND */
 
 #if LWIP_MULTICAST_TX_OPTIONS
-void  ip4_set_default_multicast_netif(struct netif* default_multicast_netif);
+    void ip4_set_default_multicast_netif(struct netif* default_multicast_netif);
 #endif /* LWIP_MULTICAST_TX_OPTIONS */
 
 #define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL)
 
 #if IP_DEBUG
-void ip4_debug_print(struct pbuf *p);
+    void ip4_debug_print(struct pbuf* p);
 #else
 #define ip4_debug_print(p)
 #endif /* IP_DEBUG */

Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/opt.h

@@ -521,7 +521,7 @@
  * (only needed if you use the sequential API, like api_lib.c)
  */
 #if !defined MEMP_NUM_NETBUF || defined __DOXYGEN__
-#define MEMP_NUM_NETBUF                 2
+#define MEMP_NUM_NETBUF 8
 #endif
 
 /**
@@ -529,7 +529,7 @@
  * (only needed if you use the sequential API, like api_lib.c)
  */
 #if !defined MEMP_NUM_NETCONN || defined __DOXYGEN__
-#define MEMP_NUM_NETCONN                4
+#define MEMP_NUM_NETCONN 8
 #endif
 
 /**
@@ -538,7 +538,7 @@
  * In that case, you need one per thread calling lwip_select.)
  */
 #if !defined MEMP_NUM_SELECT_CB || defined __DOXYGEN__
-#define MEMP_NUM_SELECT_CB              4
+#define MEMP_NUM_SELECT_CB 4
 #endif
 
 /**
@@ -547,7 +547,7 @@
  * (only needed if you use tcpip.c)
  */
 #if !defined MEMP_NUM_TCPIP_MSG_API || defined __DOXYGEN__
-#define MEMP_NUM_TCPIP_MSG_API          8
+#define MEMP_NUM_TCPIP_MSG_API 8
 #endif
 
 /**
@@ -556,7 +556,7 @@
  * (only needed if you use tcpip.c)
  */
 #if !defined MEMP_NUM_TCPIP_MSG_INPKT || defined __DOXYGEN__
-#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#define MEMP_NUM_TCPIP_MSG_INPKT 8
 #endif
 
 /**
@@ -564,7 +564,7 @@
  * (before freeing the corresponding memory using lwip_freeaddrinfo()).
  */
 #if !defined MEMP_NUM_NETDB || defined __DOXYGEN__
-#define MEMP_NUM_NETDB                  1
+#define MEMP_NUM_NETDB 2
 #endif
 
 /**
@@ -572,7 +572,7 @@
  * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
  */
 #if !defined MEMP_NUM_LOCALHOSTLIST || defined __DOXYGEN__
-#define MEMP_NUM_LOCALHOSTLIST          1
+#define MEMP_NUM_LOCALHOSTLIST 2
 #endif
 
 /**

Ubiquitous/XiZi_IIoT/resources/ethernet/cmd_lwip/Makefile

@@ -1,4 +1,4 @@
 # SRC_FILES := ping.c lwip_ping_demo.c lwip_config_demo.c lwip_dhcp_demo.c iperf.c http_test.c
-SRC_FILES := ping.c lwip_ping_demo.c lwip_udp_demo.c tcpecho_raw.c lwip_config_demo.c lwip_dhcp_demo.c
+SRC_FILES := ping.c lwip_ping_demo.c tcpecho_raw.c lwip_config_demo.c 
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/resources/ethernet/cmd_lwip/lwip_config_demo.c

@@ -25,104 +25,145 @@
 #include <sys_arch.h>
 #include <xs_kdbg.h>
 
-#include <netdev.h>
+#include "argparse.h"
+
+#include "inet.h"
+#include "netdev.h"
 
 /******************************************************************************/
-uint8_t enet_id = 0;
+enum NETWORK_ACTIVE_E {
-static void LwipSetIPTask(void* param)
+    LWIP_ACTIVE = 'e',
-{
+    LWIP_ACTIVE_ALL = 'a',
-    uint8_t enet_port = *(uint8_t*)param; ///< test enet port
+};
-    printf("lw: [%s] config netport id[%d]\n", __func__, enet_port);
-    // lwip_config_net(enet_port, lwip_ipaddr, lwip_netmask, lwip_gwaddr);
-    lwip_config_tcp(enet_port, lwip_ipaddr, lwip_netmask, lwip_gwaddr);
-}
 
-void LwipSetIPTest(int argc, char* argv[])
+void LwipNetworkActive(int argc, char* argv[])
 {
-    if (argc >= 4) {
+    static char usage_info[] = "select a eport to start.";
-        printf("lw: [%s] ip %s mask %s gw %s netport %s\n", __func__, argv[1], argv[2], argv[3], argv[4]);
+    static char program_info[] = "Active lwip network function.";
-        sscanf(argv[1], "%hhd.%hhd.%hhd.%hhd", &lwip_ipaddr[0], &lwip_ipaddr[1], &lwip_ipaddr[2], &lwip_ipaddr[3]);
+    static const char* const net_active_usages[] = {
-        sscanf(argv[2], "%hhd.%hhd.%hhd.%hhd", &lwip_netmask[0], &lwip_netmask[1], &lwip_netmask[2], &lwip_netmask[3]);
+        "LwipNetworkActive -e 0",
-        sscanf(argv[3], "%hhd.%hhd.%hhd.%hhd", &lwip_gwaddr[0], &lwip_gwaddr[1], &lwip_gwaddr[2], &lwip_gwaddr[3]);
+        "LwipNetworkActive -e 1",
-        sscanf(argv[4], "%hhd", &enet_id);
+        "LwipNetworkActive -a",
+    };
 
-        if (0 == enet_id) {
+    int eport = -1;
-            printf("save eth0 info\n");
+    bool all = false;
-            memcpy(lwip_eth0_ipaddr, lwip_ipaddr, 20);
+    bool is_help = false;
-            memcpy(lwip_eth0_netmask, lwip_netmask, 20);
+    struct argparse_option options[] = {
-            memcpy(lwip_eth0_gwaddr, lwip_gwaddr, 20);
+        OPT_HELP(&is_help),
-        } else if (1 == enet_id) {
+        OPT_INTEGER(LWIP_ACTIVE, "eport", &eport, "eport to start network.", NULL, 0, 0),
-            printf("save eth1 info\n");
+        OPT_BIT(LWIP_ACTIVE_ALL, "all", &all, "start network at both eport 0 and 1.", NULL, true, 0),
-            memcpy(lwip_eth1_ipaddr, lwip_ipaddr, 20);
+        OPT_END(),
-            memcpy(lwip_eth1_netmask, lwip_netmask, 20);
+    };
-            memcpy(lwip_eth1_gwaddr, lwip_gwaddr, 20);
+
-        }
+    struct argparse argparse;
-    } else if (argc == 2) {
+    argparse_init(&argparse, options, net_active_usages, 0);
-        printf("lw: [%s] set eth0 ipaddr %s \n", __func__, argv[1]);
+    argparse_describe(&argparse, usage_info, program_info);
-        sscanf(argv[1], "%hhd.%hhd.%hhd.%hhd", &lwip_ipaddr[0], &lwip_ipaddr[1], &lwip_ipaddr[2], &lwip_ipaddr[3]);
+    argc = argparse_parse(&argparse, argc, (const char**)argv);
-        memcpy(lwip_eth0_ipaddr, lwip_ipaddr, strlen(lwip_ipaddr));
+    if (is_help) {
+        return;
     }
-    // sys_thread_new("SET ip address", LwipSetIPTask, &enet_id, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
-    LwipSetIPTask(&enet_id);
-}
 
+    if (all) {
+        lwip_config_tcp(0, lwip_eth0_ipaddr, lwip_eth0_netmask, lwip_eth0_gwaddr);
+        lwip_config_tcp(1, lwip_eth1_ipaddr, lwip_eth1_netmask, lwip_eth1_gwaddr);
+        return;
+    }
+
+    if (eport != 0 && eport != 1) {
+        printf("[%s] Err: Support only eport 0 and eport 1.\n", __func__);
+    }
+
+    if (eport == 0) {
+        lwip_config_tcp(0, lwip_eth0_ipaddr, lwip_eth0_netmask, lwip_eth0_gwaddr);
+    } else if (eport == 1) {
+        lwip_config_tcp(1, lwip_eth1_ipaddr, lwip_eth1_netmask, lwip_eth1_gwaddr);
+    }
+}
 SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(5),
-    setip, LwipSetIPTest, setip[IP][Netmask][Gateway][port]);
+    LwipNetworkActive, LwipNetworkActive, start lwip);
 
-void LwipShowIPTask(int argc, char* argv[])
+enum NETWORK_CONFIG_E {
+    NETWORK_DEV = 'd',
+    NETWORK_IP = 'i',
+    NETWORK_NM = 'n',
+    NETWORK_GW = 'g',
+};
+
+void LwipSetNetwork(int argc, char* argv[])
 {
-#ifdef configMAC_ADDR
+    static char usage_info[] = "config network information.";
-    char mac_addr0[] = configMAC_ADDR;
+    static char program_info[] = "set network ip, netmask, gateway";
-#endif
+    static const char* const net_set_usages[] = {
+        "LwipSetNetwork -d [dev] -i [ip]",
+        "LwipSetNetwork -d [dev] -n [netmask]",
+        "LwipSetNetwork -d [dev] -g [gw]",
+        "LwipSetNetwork -d [dev] -i [ip] -n [netmask] -g [gw]",
+    };
 
-    // find default netdev
+    char* dev_ptr = NULL;
-    struct netdev* netdev = netdev_get_by_name("en\0");
+    char* ip_ptr = NULL;
+    char* nm_ptr = NULL;
+    char* gw_ptr = NULL;
+    bool is_help = false;
+    struct argparse_option options[] = {
+        OPT_HELP(&is_help),
+        OPT_GROUP("Param Options"),
+        OPT_STRING(NETWORK_DEV, "dev", &dev_ptr, "netdev", NULL, 0, 0),
+        OPT_STRING(NETWORK_IP, "ip", &ip_ptr, "change ip", NULL, 0, 0),
+        OPT_STRING(NETWORK_NM, "nm", &nm_ptr, "change netmask", NULL, 0, 0),
+        OPT_STRING(NETWORK_GW, "gw", &gw_ptr, "change gateway", NULL, 0, 0),
+        OPT_END(),
+    };
+
+    struct argparse argparse;
+    argparse_init(&argparse, options, net_set_usages, 0);
+    argparse_describe(&argparse, usage_info, program_info);
+    argc = argparse_parse(&argparse, argc, (const char**)argv);
+    /* help task */
+    if (is_help) {
+        return;
+    }
+
+    if (dev_ptr == NULL) {
+        printf("[%s] Err: must given a netdev name.\n", __func__);
+        return;
+    }
+    struct netdev* netdev = netdev_get_by_name(dev_ptr);
     if (netdev == NULL) {
-        lw_notice("[%s] Netdev not found by name en\n");
+        printf("[%s] Err: Netdev not found by name: %s\n", __func__, dev_ptr);
-        struct netdev* default_netdev = NETDEV_DEFAULT;
+        return;
     }
 
-    lw_notice("\r\n************************************************\r\n");
+    ip_addr_t ipaddr, maskaddr, gwaddr;
-    lw_notice(" Network Configuration\r\n");
+    if (ip_ptr != NULL) {
-    lw_notice("************************************************\r\n");
+        inet_aton(ip_ptr, &ipaddr);
-    //     lw_notice(" ETH0 IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth0_ipaddr)[0], ((u8_t*)&lwip_eth0_ipaddr)[1],
+        if (0 != netdev_set_ipaddr(netdev, &ipaddr)) {
-    //         ((u8_t*)&lwip_eth0_ipaddr)[2], ((u8_t*)&lwip_eth0_ipaddr)[3]);
+            printf("[%s] Err: set ip: %s failed.\n", __func__, ip_ptr);
-    //     lw_notice(" ETH0 IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth0_netmask)[0], ((u8_t*)&lwip_eth0_netmask)[1],
+        }
-    //         ((u8_t*)&lwip_eth0_netmask)[2], ((u8_t*)&lwip_eth0_netmask)[3]);
-    //     lw_notice(" ETH0 IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_gwaddr)[0], ((u8_t*)&lwip_eth0_gwaddr)[1],
-    //         ((u8_t*)&lwip_eth0_gwaddr)[2], ((u8_t*)&lwip_eth0_gwaddr)[3]);
-    // #ifdef configMAC_ADDR
-    //     lw_notice(" ETH0 MAC Address    : %x:%x:%x:%x:%x:%x\r\n", mac_addr0[0], mac_addr0[1], mac_addr0[2],
-    //         mac_addr0[3], mac_addr0[4], mac_addr0[5]);
-    // #endif
-
-    lw_notice(" ETH0 IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth0_ipaddr)[0], ((u8_t*)&lwip_eth0_ipaddr)[1],
-        ((u8_t*)&lwip_eth0_ipaddr)[2], ((u8_t*)&lwip_eth0_ipaddr)[3]);
-    lw_notice(" ETH0 IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth0_netmask)[0], ((u8_t*)&lwip_eth0_netmask)[1],
-        ((u8_t*)&lwip_eth0_netmask)[2], ((u8_t*)&lwip_eth0_netmask)[3]);
-    lw_notice(" ETH0 IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_gwaddr)[0], ((u8_t*)&lwip_eth0_gwaddr)[1],
-        ((u8_t*)&lwip_eth0_gwaddr)[2], ((u8_t*)&lwip_eth0_gwaddr)[3]);
-#ifdef configMAC_ADDR
-    lw_notice(" ETH0 MAC Address    : %x:%x:%x:%x:%x:%x\r\n", mac_addr0[0], mac_addr0[1], mac_addr0[2],
-        mac_addr0[3], mac_addr0[4], mac_addr0[5]);
-#endif
-
-#ifdef BOARD_NET_COUNT
-    if (BOARD_NET_COUNT > 1) {
-        char mac_addr1[] = configMAC_ADDR_ETH1;
-        lw_notice("\r\n");
-        lw_notice(" ETH1 IPv4 Address   : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth1_ipaddr)[0], ((u8_t*)&lwip_eth1_ipaddr)[1],
-            ((u8_t*)&lwip_eth1_ipaddr)[2], ((u8_t*)&lwip_eth1_ipaddr)[3]);
-        lw_notice(" ETH1 IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth1_netmask)[0], ((u8_t*)&lwip_eth1_netmask)[1],
-            ((u8_t*)&lwip_eth1_netmask)[2], ((u8_t*)&lwip_eth1_netmask)[3]);
-        lw_notice(" ETH1 IPv4 Gateway   : %u.%u.%u.%u\r\n", ((u8_t*)&lwip_eth1_gwaddr)[0], ((u8_t*)&lwip_eth1_gwaddr)[1],
-            ((u8_t*)&lwip_eth1_gwaddr)[2], ((u8_t*)&lwip_eth1_gwaddr)[3]);
-        lw_notice(" ETH1 MAC Address    : %x:%x:%x:%x:%x:%x\r\n", mac_addr1[0], mac_addr1[1], mac_addr1[2],
-            mac_addr1[3], mac_addr1[4], mac_addr1[5]);
     }
-#endif
+    if (nm_ptr != NULL) {
-    lw_notice("************************************************\r\n");
+        inet_aton(nm_ptr, &maskaddr);
+        if (0 != netdev_set_netmask(netdev, &maskaddr)) {
+            printf("[%s] Err: set netmask: %s failed.\n", __func__, nm_ptr);
+        }
+    }
+    if (gw_ptr != NULL) {
+        inet_aton(gw_ptr, &gwaddr);
+        if (0 != netdev_set_gw(netdev, &gwaddr)) {
+            printf("[%s] Err: set gateway: %s failed.\n", __func__, gw_ptr);
+        }
+    }
+}
+
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(11),
+    LwipSetNetwork, LwipSetNetwork, config lwip);
+
+void LwipShowNetwork(int argc, char* argv[])
+{
+    extern void netdev_list_dev();
+    netdev_list_dev();
 }
 
 SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
-    showip, LwipShowIPTask, GetIp[IP][Netmask][Gateway]);
+    LwipShowNetwork, LwipShowNetwork, show lwip network configuration);

Ubiquitous/XiZi_IIoT/resources/ethernet/netdev/netdev_lowlevel.c

@@ -43,8 +43,8 @@ void netdev_low_level_set_ipaddr(struct netdev* netdev, const ip_addr_t* ip_addr
 {
     CHECK(ip_addr);
 
-    if (netdev && ip_addr_cmp(&(netdev->ip_addr), ip_addr) == 0) {
+    if (netdev && ip_addr_cmp((netdev->ip_addr), ip_addr) == 0) {
-        ip_addr_copy(netdev->ip_addr, *ip_addr);
+        ip_addr_copy(*netdev->ip_addr, *ip_addr);
 
         /* execute IP address change callback function */
         if (netdev->addr_callback) {
@@ -64,8 +64,8 @@ void netdev_low_level_set_netmask(struct netdev* netdev, const ip_addr_t* netmas
 {
     CHECK(netmask);
 
-    if (netdev && ip_addr_cmp(&(netdev->netmask), netmask) == 0) {
+    if (netdev && ip_addr_cmp((netdev->netmask), netmask) == 0) {
-        ip_addr_copy(netdev->netmask, *netmask);
+        ip_addr_copy(*netdev->netmask, *netmask);
 
         /* execute netmask address change callback function */
         if (netdev->addr_callback) {
@@ -85,8 +85,8 @@ void netdev_low_level_set_gw(struct netdev* netdev, const ip_addr_t* gw)
 {
     CHECK(gw);
 
-    if (netdev && ip_addr_cmp(&(netdev->gw), gw) == 0) {
+    if (netdev && ip_addr_cmp((netdev->gw), gw) == 0) {
-        ip_addr_copy(netdev->gw, *gw);
+        ip_addr_copy(*netdev->gw, *gw);
 
         /* execute gateway address change callback function */
         if (netdev->addr_callback) {