fit XiUOS to ch32v307. fix i2c for xidatong-arm32. add new interface for sensor information from Tu_yuyang

it is OK

APP_Framework/Applications/lv_app/Makefile

@@ -1,3 +1,4 @@
 SRC_FILES := lv_init.c lv_demo.c lv_demo_calendar.c 
+SRC_FILES += lv_sensor_info.c lv_sensor_update_info.c lv_sensor_info_update_demo.c
 
 include $(KERNEL_ROOT)/compiler.mk

APP_Framework/Applications/lv_app/README.md

@@ -0,0 +1,31 @@
+## lv_sensor_update_info
+用于在触摸屏上显示传感器的各项数据
+
+更新显示数据可在线程中使用`bool sensor_update_val(double val, enum sensor_type st)`（保障线程安全）  
+    - `val`: 传感器数值；  
+    - `st`：检测值类型（如氧气、臭氧）；  
+        - `st`类型为`enum sensor_type`，该枚举类型在lv_sensor_info.h中给出；   
+    - 该函数的使用方法可参考lv_sensor_info_update_demo.c；   
+    - 请勿直接修改lvgl table；  
+``` C
+enum sensor_type {
+    O3 = 0, // 臭氧
+    CO2,  // 二氧化碳
+    SO2,  // 二氧化硫
+    NO2,  // 二氧化氮
+    N2,  // 氨气
+    TVOC,  
+    FORMALDEHYDE,  // 甲醛
+    ALCOHOL,  // 乙醇
+    METHANE,  // 甲烷
+    O2,  // 氧气
+    AQS,
+    PM,  // PM1.0/2.5
+    TEMPERATURE,  // 温度
+    HUMIDITY,  // 湿度 
+    WIND_SPEED,  // 风速
+    WIND_DIRECTION,  //风向
+    PRESURE,  // 压力
+    NOISE  // 噪音
+};
+```

APP_Framework/Applications/lv_app/lv_demo.c

@@ -3,19 +3,20 @@
 #include "lv_demo_calendar.h"
 #include <transform.h>
 
-extern void lv_example_chart_2(void);
+// extern void lv_example_chart_2(void);
-extern void lv_example_img_1(void);
+// extern void lv_example_img_1(void);
-extern void lv_example_img_2(void);
+// extern void lv_example_img_2(void);
-extern void lv_example_img_3(void);
+// extern void lv_example_img_3(void);
-extern void lv_example_img_4(void);
+// extern void lv_example_img_4(void);
-extern void lv_example_line_1(void);
+// extern void lv_example_line_1(void);
-extern void lv_example_aoteman(void);
+// extern void lv_example_aoteman(void);
 void* lvgl_thread(void *parameter)
 {
     /* display demo; you may replace with your LVGL application at here */
     lv_demo_calendar();
     // lv_example_img_1();
     // lv_example_chart_2();
+    // lv_example_table_1();
     // lv_example_line_1();
     // lv_example_aoteman();
     /* handle the tasks of LVGL */

APP_Framework/Applications/lv_app/lv_sensor_info.c

@@ -0,0 +1,127 @@
+#include "lv_sensor_info.h"
+
+static void draw_part_event_cb(lv_event_t* e) {
+    lv_obj_t* obj = lv_event_get_target(e);
+    lv_obj_draw_part_dsc_t* dsc = lv_event_get_param(e);
+    /*If the cells are drawn...*/
+    if(dsc->part == LV_PART_ITEMS) {
+        uint32_t row = dsc->id /  lv_table_get_col_cnt(obj);
+        uint32_t col = dsc->id - row * lv_table_get_col_cnt(obj);
+        /*Make the texts in the first cell center aligned*/
+        if(row == 0) {
+            dsc->label_dsc->align = LV_TEXT_ALIGN_CENTER;
+            dsc->rect_dsc->bg_color = lv_color_mix(lv_palette_main(LV_PALETTE_BLUE), dsc->rect_dsc->bg_color, LV_OPA_20);
+            dsc->rect_dsc->bg_opa = LV_OPA_COVER;
+        }
+        /*In the first column align the texts to the right*/
+        else if(col == 0) {
+            dsc->label_dsc->flag = LV_TEXT_ALIGN_CENTER;
+        }
+        /*Make every 2nd row grayish*/
+        if((row != 0 && row % 2) == 0) {
+            dsc->rect_dsc->bg_color = lv_color_mix(lv_palette_main(LV_PALETTE_GREY), dsc->rect_dsc->bg_color, LV_OPA_10);
+            dsc->rect_dsc->bg_opa = LV_OPA_COVER;
+        }
+    }
+}
+
+char* Double2Str(char* buf, double value) {
+	sprintf(buf,"%.8f",value);//保留8位小数，不够补0
+	int index = 0;
+	int len = strlen(buf);
+	for(int i = len-1;i>0;i--)
+	{
+		if(buf[i] == '0')
+			continue;
+        else {
+            if (buf[i] == '.') index = i;
+            else index = i + 1;
+            break;
+        }
+	}
+    buf[index] = '\0';
+    return buf;
+}
+
+lv_obj_t* lv_ssr_tb;
+
+void lv_sensor_info(void) {
+    lv_ssr_tb = lv_table_create(lv_scr_act());
+    // lv_obj_remove_style(lv_ssr_tb, NULL, LV_PART_ITEMS | LV_STATE_PRESSED);
+
+    for (uint32_t i = 0; i < NR_VAL_PERLINE; ++i) {
+        lv_table_set_cell_value(lv_ssr_tb, 0, 2 * i, "检测量");
+        lv_table_set_cell_value(lv_ssr_tb, 0, 2 * i + 1, "数值");
+    }
+
+    // fill name
+    uint32_t filled_pos = 0;
+    uint32_t cur_line_tmp = 0;
+    LV_FONT_DECLARE(lvgl_font_chinese);
+    while (filled_pos < nr_sensors) {
+        cur_line_tmp = 1 + (filled_pos / NR_VAL_PERLINE);
+        for (uint32_t i = 0; i < NR_VAL_PERLINE; ++i) {
+            if (filled_pos >= nr_sensors) { break; }
+            lv_table_set_cell_value(lv_ssr_tb, cur_line_tmp, 2 * i, sensor_names[filled_pos++]);
+        }
+    }
+    lv_obj_set_style_text_font(lv_ssr_tb, &lvgl_font_chinese, 0);
+
+    // set width of cells in table
+    for (uint32_t i = 0; i < 2 * NR_VAL_PERLINE; ++i) {
+        if (i % 2 == 0) {
+            lv_table_set_col_width(lv_ssr_tb, i, 75);
+        }
+        else {
+            lv_table_set_col_width(lv_ssr_tb, i, 85);
+        }
+    }
+
+    // fill val
+    filled_pos = 0;
+    // init val
+    for (uint32_t i = 0; i < nr_sensors; ++i) { lv_sensor_vals[i] = 0; }
+    char buf[10];
+    snprintf(buf, 9, "%.1f", 0);
+    while (filled_pos < nr_sensors) {
+        for (uint32_t i = 0; i < NR_VAL_PERLINE; ++i) {
+            if (filled_pos >= nr_sensors) { break; }
+            lv_table_set_cell_value_fmt(lv_ssr_tb, 1 + (filled_pos / NR_VAL_PERLINE),
+                1 + 2 * i, "%s %s", buf, seneor_denominations[filled_pos++]);
+        }
+    }
+
+    lv_obj_set_size(lv_ssr_tb, 480, 272);
+    
+    lv_obj_set_height(lv_ssr_tb, 272);
+    lv_obj_center(lv_ssr_tb);
+
+    /*Add an event callback to to apply some custom drawing*/
+    lv_obj_add_event_cb(lv_ssr_tb, draw_part_event_cb, LV_EVENT_DRAW_PART_BEGIN, NULL);
+}
+
+void* lvgl_thd_show_sensor_info(void *parameter)
+{
+    lv_sensor_info();
+    PrivMutexCreate(&ssr_val_lock, 0);
+    while (1)
+    {
+        lv_task_handler();
+
+        sensor_update_table();
+    }
+}
+
+pthread_t lvgl_task;
+static int lvgl_show_sensor_info(void)
+{
+    pthread_attr_t attr;
+    attr.schedparam.sched_priority = 25;
+    attr.stacksize = 4096;
+
+    PrivTaskCreate(&lvgl_task, &attr, lvgl_thd_show_sensor_info, NULL);
+
+    return 0;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),lvgl_show_sensor_info, lvgl_show_sensor_info, lvgl_show_sensor_info );
+

APP_Framework/Applications/lv_app/lv_sensor_info.h

@@ -0,0 +1,56 @@
+#ifndef __LVGL_SENSOR_INFO_H__
+#define __LVGL_SENSOR_INFO_H__
+
+#include <lvgl.h>
+#include <string.h>
+
+#define nr_sensors 18
+extern lv_obj_t* lv_ssr_tb;
+pthread_mutex_t ssr_val_lock;
+
+// number of sensor values showed in one line
+#define NR_VAL_PERLINE 3
+
+static char* sensor_names[nr_sensors] = {
+    "臭氧", "二氧化碳", "二氧化硫", "二氧化氮", "氨气",
+    "TVOC", "甲醛", "乙醇", "甲烷", "氧气", "AQS", "PM1.0/2.5/10",
+    "温度", "湿度",
+    "风速", "风向", "气压", "噪音"
+};
+
+static char* seneor_denominations[nr_sensors] = {
+    "ppb", "ppm", "ppb", "ppb", "ppm",
+    "ppm", "ppm", "ppm", "%VOL", "%VOL", "ug/m³", "ug/m³",
+    "°C", "%RH",
+    "m/s", "m/s", "mbar", "dB(A)"
+};
+
+static double lv_sensor_vals[nr_sensors];
+
+enum sensor_type {
+    O3 = 0, // 臭氧
+    CO2,  // 二氧化碳
+    SO2,  // 二氧化硫
+    NO2,  // 二氧化氮
+    N2,  // 氨气
+    TVOC,  
+    FORMALDEHYDE,  // 甲醛
+    ALCOHOL,  // 乙醇
+    METHANE,  // 甲烷
+    O2,  // 氧气
+    AQS,
+    PM,  // PM1.0/2.5
+    TEMPERATURE,  // 温度
+    HUMIDITY,  // 湿度 
+    WIND_SPEED,  // 风速
+    WIND_DIRECTION,  //风向
+    PRESURE,  // 压力
+    NOISE  // 噪音
+};
+
+void lv_sensor_info(void);
+bool sensor_update_val(double, enum sensor_type);
+char* Double2Str(char* buf, double value);
+void sensor_update_table();
+
+#endif

APP_Framework/Applications/lv_app/lv_sensor_info_update_demo.c

@@ -0,0 +1,32 @@
+#include "lv_sensor_info.h"
+
+void* lvgl_thd_sensor_info_update_demo(void *parameter)
+{
+    double val = 0;
+    while (1)
+    {
+        sensor_update_val(val + 0.1, O3);
+        sensor_update_val(val, CO2);
+        sensor_update_val(val + 0.2, NO2);
+        sensor_update_val(val - 0.1, SO2);
+        sensor_update_val(val + 0.3, AQS);
+        sensor_update_val(val - 0.3, O2);
+        sensor_update_val(val + 0.3, TEMPERATURE);
+        val += 0.3;
+        PrivTaskDelay(10);
+    }
+}
+
+pthread_t lvgl_task;
+static int lvgl_sensor_info_update_demo(void)
+{
+    pthread_attr_t attr;
+    attr.schedparam.sched_priority = 25;
+    attr.stacksize = 4096;
+
+    PrivTaskCreate(&lvgl_task, &attr, lvgl_thd_sensor_info_update_demo, NULL);
+
+    return 0;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),lvgl_sensor_info_update_demo, lvgl_sensor_info_update_demo, lvgl_sensor_info_update_demo );
+

APP_Framework/Applications/lv_app/lv_sensor_update_info.c

@@ -0,0 +1,57 @@
+#include "lv_sensor_info.h"
+
+uint32_t lv_ssr_map_idx(enum sensor_type st) {
+    uint32_t idx;
+    switch (st) {
+    case O3: {idx = 0; break;}
+    case CO2: {idx = 1; break;}
+    case SO2: {idx = 2; break;}
+    case NO2: {idx = 3; break;}
+    case N2: {idx = 4; break;}
+    case TVOC: {idx = 5; break;}
+    case FORMALDEHYDE: {idx = 6; break;}
+    case ALCOHOL: {idx = 7; break;}
+    case METHANE: {idx = 8; break;}
+    case O2: {idx = 9; break;}
+    case AQS: {idx = 10; break;}
+    case PM: {idx = 11; break;}
+    case TEMPERATURE: {idx = 12; break;}
+    case HUMIDITY: {idx = 13; break;}
+    case WIND_SPEED: {idx = 14; break;}
+    case WIND_DIRECTION: {idx = 15; break;}
+    case PRESURE: {idx = 16; break;}
+    case NOISE: {idx = 17; break;}
+    default: {idx = -1; break;}
+    }
+    return idx;
+}
+
+bool sensor_update_val(double val, enum sensor_type st) {
+    uint32_t idx = lv_ssr_map_idx(st);
+    if (idx >= nr_sensors || lv_ssr_tb == NULL) { return false; }
+    PrivMutexObtain(&ssr_val_lock);
+    lv_sensor_vals[idx] = val;
+    PrivMutexAbandon(&ssr_val_lock);
+    return true;
+}
+
+/**
+ *@brief update cell vals in lv_ssr_tb, 
+ *       note that this function can only be called in lv_ssr_tb control thread 
+ *
+ */
+void sensor_update_table() {
+    uint32_t filled_pos = 0;
+    char buf[10] = { 0 };
+    PrivMutexObtain(&ssr_val_lock);
+    while (filled_pos < nr_sensors) {
+        for (uint32_t i = 0; i < NR_VAL_PERLINE; ++i) {
+            if (filled_pos >= nr_sensors) { break; }
+            snprintf(buf, 9, "%.1f", lv_sensor_vals[filled_pos]);
+            lv_table_set_cell_value_fmt(lv_ssr_tb, 1 + (filled_pos / NR_VAL_PERLINE),
+                1 + 2 * i, "%s %s", buf, seneor_denominations[filled_pos++]);
+        }
+    }
+    PrivMutexAbandon(&ssr_val_lock);
+}
+

APP_Framework/Applications/main.c

@@ -15,6 +15,8 @@
 // #include <user_api.h>
 #include <transform.h>
 
+
+
 extern int FrameworkInit();
 extern void ApplicationOtaTaskInit(void);
 int main(void)

APP_Framework/lib/lvgl/lv_conf.h

@@ -46,10 +46,10 @@
  *=========================*/
 
 /*1: use custom malloc/free, 0: use the built-in `lv_mem_alloc()` and `lv_mem_free()`*/
-#define LV_MEM_CUSTOM 1
+#define LV_MEM_CUSTOM 0
 #if LV_MEM_CUSTOM == 0
 /*Size of the memory available for `lv_mem_alloc()` in bytes (>= 2kB)*/
-#  define LV_MEM_SIZE (32U * 1024U)          /*[bytes]*/
+#  define LV_MEM_SIZE (64U * 1024U)          /*[bytes]*/
 
 /*Set an address for the memory pool instead of allocating it as a normal array. Can be in external SRAM too.*/
 #  define LV_MEM_ADR 0     /*0: unused*/
@@ -78,10 +78,10 @@
  *====================*/
 
 /*Default display refresh period. LVG will redraw changed areas with this period time*/
-#define LV_DISP_DEF_REFR_PERIOD 100      /*[ms]*/
+#define LV_DISP_DEF_REFR_PERIOD 1      /*[ms]*/
 
 /*Input device read period in milliseconds*/
-#define LV_INDEV_DEF_READ_PERIOD 30     /*[ms]*/
+#define LV_INDEV_DEF_READ_PERIOD 1     /*[ms]*/
 
 /*Use a custom tick source that tells the elapsed time in milliseconds.
  *It removes the need to manually update the tick with `lv_tick_inc()`)*/
@@ -187,7 +187,7 @@ e.g. "stm32f769xx.h" or "stm32f429xx.h"*/
 
 /*1: Print the log with 'printf';
  *0: User need to register a callback with `lv_log_register_print_cb()`*/
-#  define LV_LOG_PRINTF 0
+#  define LV_LOG_PRINTF 1
 
 /*Enable/disable LV_LOG_TRACE in modules that produces a huge number of logs*/
 #  define LV_LOG_TRACE_MEM        1
@@ -229,7 +229,7 @@ e.g. "stm32f769xx.h" or "stm32f429xx.h"*/
 
 /*1: Show the used memory and the memory fragmentation in the left bottom corner
  * Requires LV_MEM_CUSTOM = 0*/
-#define LV_USE_MEM_MONITOR 0
+#define LV_USE_MEM_MONITOR 1
 #if LV_USE_PERF_MONITOR
 #define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT
 #endif

APP_Framework/lib/lvgl/lvgl.mk

@@ -1,4 +1,5 @@
-include $(LVGL_DIR)/$(LVGL_DIR_NAME)/examples/examples.mk
+# include $(LVGL_DIR)/$(LVGL_DIR_NAME)/examples/examples.mk
+include $(LVGL_DIR)/$(LVGL_DIR_NAME)/porting/porting.mk
 include $(LVGL_DIR)/$(LVGL_DIR_NAME)/src/extra/extra.mk
 include $(LVGL_DIR)/$(LVGL_DIR_NAME)/src/core/lv_core.mk
 include $(LVGL_DIR)/$(LVGL_DIR_NAME)/src/draw/lv_draw.mk

APP_Framework/lib/lvgl/porting/lv_port_disp_template.c

@@ -0,0 +1,199 @@
+/**
+ * @file lv_port_disp_templ.c
+ *
+ */
+
+ /*Copy this file as "lv_port_disp.c" and set this value to "1" to enable content*/
+#if 1
+
+/*********************
+ *      INCLUDES
+ *********************/
+#include "lv_port_disp_template.h"
+#include "../lvgl.h"
+
+static int lcd_fd = 0;
+/*********************
+ *      DEFINES
+ *********************/
+
+/**********************
+ *      TYPEDEFS
+ **********************/
+
+/**********************
+ *  STATIC PROTOTYPES
+ **********************/
+static void disp_init(void);
+
+static void disp_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p);
+//static void gpu_fill(lv_disp_drv_t * disp_drv, lv_color_t * dest_buf, lv_coord_t dest_width,
+//        const lv_area_t * fill_area, lv_color_t color);
+
+/**********************
+ *  STATIC VARIABLES
+ **********************/
+
+/**********************
+ *      MACROS
+ **********************/
+
+/**********************
+ *   GLOBAL FUNCTIONS
+ **********************/
+
+void lv_port_disp_init(void)
+{
+    /*-------------------------
+     * Initialize your display
+     * -----------------------*/
+    disp_init();
+
+    /*-----------------------------
+     * Create a buffer for drawing
+     *----------------------------*/
+
+    /**
+     * LVGL requires a buffer where it internally draws the widgets.
+     * Later this buffer will passed to your display driver's `flush_cb` to copy its content to your display.
+     * The buffer has to be greater than 1 display row
+     *
+     * There are 3 buffering configurations:
+     * 1. Create ONE buffer:
+     *      LVGL will draw the display's content here and writes it to your display
+     *
+     * 2. Create TWO buffer:
+     *      LVGL will draw the display's content to a buffer and writes it your display.
+     *      You should use DMA to write the buffer's content to the display.
+     *      It will enable LVGL to draw the next part of the screen to the other buffer while
+     *      the data is being sent form the first buffer. It makes rendering and flushing parallel.
+     *
+     * 3. Double buffering
+     *      Set 2 screens sized buffers and set disp_drv.full_refresh = 1.
+     *      This way LVGL will always provide the whole rendered screen in `flush_cb`
+     *      and you only need to change the frame buffer's address.
+     */
+
+    /* Example for 1) */
+    // static lv_disp_draw_buf_t draw_buf_dsc_1;
+    // static lv_color_t buf_1[MY_DISP_HOR_RES * 1];                          /*A buffer for 10 rows*/
+    // lv_disp_draw_buf_init(&draw_buf_dsc_1, buf_1, NULL, MY_DISP_HOR_RES * 1);   /*Initialize the display buffer*/
+
+    /* Example for 2) */
+    static lv_disp_draw_buf_t draw_buf_dsc_2;
+    static lv_color_t buf_2_1[MY_DISP_HOR_RES *10];                       /*A buffer for 10 rows*/
+    static lv_color_t buf_2_2[MY_DISP_HOR_RES * 10];                        /*An other buffer for 10 rows*/
+    lv_disp_draw_buf_init(&draw_buf_dsc_2, buf_2_1, buf_2_2, MY_DISP_HOR_RES * 10);   /*Initialize the display buffer*/
+
+    /* Example for 3) also set disp_drv.full_refresh = 1 below*/
+    // static lv_disp_draw_buf_t draw_buf_dsc_3;
+    // static lv_color_t buf_3_1[MY_DISP_HOR_RES * MY_DISP_VER_RES];            /*A screen sized buffer*/
+    // static lv_color_t buf_3_2[MY_DISP_HOR_RES * MY_DISP_VER_RES];            /*An other screen sized buffer*/
+    // lv_disp_draw_buf_init(&draw_buf_dsc_3, buf_3_1, buf_3_2, MY_DISP_VER_RES * LV_VER_RES_MAX);   /*Initialize the display buffer*/
+
+    /*-----------------------------------
+     * Register the display in LVGL
+     *----------------------------------*/
+
+    static lv_disp_drv_t disp_drv;                         /*Descriptor of a display driver*/
+    lv_disp_drv_init(&disp_drv);                    /*Basic initialization*/
+
+    /*Set up the functions to access to your display*/
+
+    /*Set the resolution of the display*/
+    disp_drv.hor_res = MY_DISP_HOR_RES;
+    disp_drv.ver_res = MY_DISP_VER_RES;
+
+    /*Used to copy the buffer's content to the display*/
+    disp_drv.flush_cb = disp_flush;
+
+    /*Set a display buffer*/
+    disp_drv.draw_buf = &draw_buf_dsc_2;
+
+    /*Required for Example 3)*/
+    //disp_drv.full_refresh = 1
+
+    /* Fill a memory array with a color if you have GPU.
+     * Note that, in lv_conf.h you can enable GPUs that has built-in support in LVGL.
+     * But if you have a different GPU you can use with this callback.*/
+    //disp_drv.gpu_fill_cb = gpu_fill;
+
+    /*Finally register the driver*/
+    lv_disp_drv_register(&disp_drv);
+}
+
+/**********************
+ *   STATIC FUNCTIONS
+ **********************/
+
+/*Initialize your display and the required peripherals.*/
+static void disp_init(void)
+{
+    lcd_fd = PrivOpen(PRIV_LCD_DEV,O_RDWR);
+    printf("lcd fd = %d\n",lcd_fd);
+    /*You code here*/
+}
+
+/*Flush the content of the internal buffer the specific area on the display
+ *You can use DMA or any hardware acceleration to do this operation in the background but
+ *'lv_disp_flush_ready()' has to be called when finished.*/
+static void disp_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p)
+{
+    /*The most simple case (but also the slowest) to put all pixels to the screen one-by-one*/
+    LcdWriteParam   disp_info;
+    /*Put a pixel to the display. For example:*/
+            
+    memset(&disp_info,0,sizeof(LcdWriteParam));
+    if(area && color_p)
+    {
+        disp_info.type = 1;
+        // printf("wwg debug\n");
+        disp_info.pixel_info.x_startpos =  area->x1;
+        disp_info.pixel_info.x_endpos =  area->x2;
+        disp_info.pixel_info.y_startpos = area->y1;
+        disp_info.pixel_info.y_endpos = area->y2;
+        disp_info.pixel_info.pixel_color = color_p;
+        // printf("x1:%d  x2:%d y1 %d y2 %d\n",disp_info.pixel_info.x_startpos,disp_info.pixel_info.x_endpos,disp_info.pixel_info.y_startpos,disp_info.pixel_info.y_endpos);
+        PrivWrite(lcd_fd, &disp_info, sizeof(LcdWriteParam));
+    }
+    
+
+    // int32_t x;
+    // int32_t y;
+    // for(y = area->y1; y <= area->y2; y++) {
+    //     for(x = area->x1; x <= area->x2; x++) {
+    //         /*Put a pixel to the display. For example:*/
+    //         /*put_px(x, y, *color_p)*/
+    //         color_p++;
+    //     }
+    // }
+
+    /*IMPORTANT!!!
+     *Inform the graphics library that you are ready with the flushing*/
+    lv_disp_flush_ready(disp_drv);
+}
+
+/*OPTIONAL: GPU INTERFACE*/
+
+/*If your MCU has hardware accelerator (GPU) then you can use it to fill a memory with a color*/
+//static void gpu_fill(lv_disp_drv_t * disp_drv, lv_color_t * dest_buf, lv_coord_t dest_width,
+//                    const lv_area_t * fill_area, lv_color_t color)
+//{
+//    /*It's an example code which should be done by your GPU*/
+//    int32_t x, y;
+//    dest_buf += dest_width * fill_area->y1; /*Go to the first line*/
+//
+//    for(y = fill_area->y1; y <= fill_area->y2; y++) {
+//        for(x = fill_area->x1; x <= fill_area->x2; x++) {
+//            dest_buf[x] = color;
+//        }
+//        dest_buf+=dest_width;    /*Go to the next line*/
+//    }
+//}
+
+
+#else /*Enable this file at the top*/
+
+/*This dummy typedef exists purely to silence -Wpedantic.*/
+typedef int keep_pedantic_happy;
+#endif

APP_Framework/lib/lvgl/porting/lv_port_disp_template.h

@@ -0,0 +1,43 @@
+/**
+ * @file lv_port_disp_templ.h
+ *
+ */
+
+ /*Copy this file as "lv_port_disp.h" and set this value to "1" to enable content*/
+#if 0
+
+#ifndef LV_PORT_DISP_TEMPL_H
+#define LV_PORT_DISP_TEMPL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*********************
+ *      INCLUDES
+ *********************/
+#include "lvgl/lvgl.h"
+
+/*********************
+ *      DEFINES
+ *********************/
+
+/**********************
+ *      TYPEDEFS
+ **********************/
+
+/**********************
+ * GLOBAL PROTOTYPES
+ **********************/
+
+/**********************
+ *      MACROS
+ **********************/
+
+#ifdef __cplusplus
+} /*extern "C"*/
+#endif
+
+#endif /*LV_PORT_DISP_TEMPL_H*/
+
+#endif /*Disable/Enable content*/

APP_Framework/lib/lvgl/porting/lv_port_fs_template.c

@@ -0,0 +1,264 @@
+/**
+ * @file lv_port_fs_templ.c
+ *
+ */
+
+ /*Copy this file as "lv_port_fs.c" and set this value to "1" to enable content*/
+#if 0
+
+/*********************
+ *      INCLUDES
+ *********************/
+#include "lv_port_fs_template.h"
+#include "../../lvgl.h"
+
+/*********************
+ *      DEFINES
+ *********************/
+
+/**********************
+ *      TYPEDEFS
+ **********************/
+
+/**********************
+ *  STATIC PROTOTYPES
+ **********************/
+static void fs_init(void);
+
+static void * fs_open(lv_fs_drv_t * drv, void * file_p, const char * path, lv_fs_mode_t mode);
+static lv_fs_res_t fs_close(lv_fs_drv_t * drv, void * file_p);
+static lv_fs_res_t fs_read(lv_fs_drv_t * drv, void * file_p, void * buf, uint32_t btr, uint32_t * br);
+static lv_fs_res_t fs_write(lv_fs_drv_t * drv, void * file_p, const void * buf, uint32_t btw, uint32_t * bw);
+static lv_fs_res_t fs_seek(lv_fs_drv_t * drv, void * file_p, uint32_t pos, lv_fs_whence_t whence);
+static lv_fs_res_t fs_size(lv_fs_drv_t * drv, void * file_p, uint32_t * size_p);
+static lv_fs_res_t fs_tell(lv_fs_drv_t * drv, void * file_p, uint32_t * pos_p);
+
+static void * fs_dir_open(lv_fs_drv_t * drv, const char *path);
+static lv_fs_res_t fs_dir_read(lv_fs_drv_t * drv, void * rddir_p, char * fn);
+static lv_fs_res_t fs_dir_close(lv_fs_drv_t * drv, void * rddir_p);
+
+/**********************
+ *  STATIC VARIABLES
+ **********************/
+
+/**********************
+ * GLOBAL PROTOTYPES
+ **********************/
+
+/**********************
+ *      MACROS
+ **********************/
+
+/**********************
+ *   GLOBAL FUNCTIONS
+ **********************/
+
+void lv_port_fs_init(void)
+{
+    /*----------------------------------------------------
+     * Initialize your storage device and File System
+     * -------------------------------------------------*/
+    fs_init();
+
+    /*---------------------------------------------------
+     * Register the file system interface in LVGL
+     *--------------------------------------------------*/
+
+    /*Add a simple drive to open images*/
+    static lv_fs_drv_t fs_drv;
+    lv_fs_drv_init(&fs_drv);
+
+    /*Set up fields...*/
+    fs_drv.letter = 'P';
+    fs_drv.open_cb = fs_open;
+    fs_drv.close_cb = fs_close;
+    fs_drv.read_cb = fs_read;
+    fs_drv.write_cb = fs_write;
+    fs_drv.seek_cb = fs_seek;
+    fs_drv.tell_cb = fs_tell;
+
+    fs_drv.dir_close_cb = fs_dir_close;
+    fs_drv.dir_open_cb = fs_dir_open;
+    fs_drv.dir_read_cb = fs_dir_read;
+
+    lv_fs_drv_register(&fs_drv);
+}
+
+/**********************
+ *   STATIC FUNCTIONS
+ **********************/
+
+/*Initialize your Storage device and File system.*/
+static void fs_init(void)
+{
+    /*E.g. for FatFS initialize the SD card and FatFS itself*/
+
+    /*You code here*/
+}
+
+/**
+ * Open a file
+ * @param drv       pointer to a driver where this function belongs
+ * @param path      path to the file beginning with the driver letter (e.g. S:/folder/file.txt)
+ * @param mode      read: FS_MODE_RD, write: FS_MODE_WR, both: FS_MODE_RD | FS_MODE_WR
+ * @return          a file descriptor or NULL on error
+ */
+static void * fs_open(lv_fs_drv_t * drv, const char * path, lv_fs_mode_t mode)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    void * f = NULL;
+
+    if(mode == LV_FS_MODE_WR)
+    {
+        /*Open a file for write*/
+        f = ...         /*Add your code here*/
+    }
+    else if(mode == LV_FS_MODE_RD)
+    {
+        /*Open a file for read*/
+        f = ...         /*Add your code here*/
+    }
+    else if(mode == (LV_FS_MODE_WR | LV_FS_MODE_RD))
+    {
+        /*Open a file for read and write*/
+        f = ...         /*Add your code here*/
+    }
+
+    return file;
+}
+
+/**
+ * Close an opened file
+ * @param drv       pointer to a driver where this function belongs
+ * @param file_p    pointer to a file_t variable. (opened with fs_open)
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_close(lv_fs_drv_t * drv, void * file_p)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+
+/**
+ * Read data from an opened file
+ * @param drv       pointer to a driver where this function belongs
+ * @param file_p    pointer to a file_t variable.
+ * @param buf       pointer to a memory block where to store the read data
+ * @param btr       number of Bytes To Read
+ * @param br        the real number of read bytes (Byte Read)
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_read(lv_fs_drv_t * drv, void * file_p, void * buf, uint32_t btr, uint32_t * br)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+
+/**
+ * Write into a file
+ * @param drv       pointer to a driver where this function belongs
+ * @param file_p    pointer to a file_t variable
+ * @param buf       pointer to a buffer with the bytes to write
+ * @param btr       Bytes To Write
+ * @param br        the number of real written bytes (Bytes Written). NULL if unused.
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_write(lv_fs_drv_t * drv, void * file_p, const void * buf, uint32_t btw, uint32_t * bw)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+
+/**
+ * Set the read write pointer. Also expand the file size if necessary.
+ * @param drv       pointer to a driver where this function belongs
+ * @param file_p    pointer to a file_t variable. (opened with fs_open )
+ * @param pos       the new position of read write pointer
+ * @param whence    tells from where to interpret the `pos`. See @lv_fs_whence_t
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_seek(lv_fs_drv_t * drv, void * file_p, uint32_t pos, lv_fs_whence_t whence)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+/**
+ * Give the position of the read write pointer
+ * @param drv       pointer to a driver where this function belongs
+ * @param file_p    pointer to a file_t variable.
+ * @param pos_p     pointer to to store the result
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_tell(lv_fs_drv_t * drv, void * file_p, uint32_t * pos_p)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+
+/**
+ * Initialize a 'lv_fs_dir_t' variable for directory reading
+ * @param drv       pointer to a driver where this function belongs
+ * @param path      path to a directory
+ * @return          pointer to the directory read descriptor or NULL on error
+ */
+static void * fs_dir_open(lv_fs_drv_t * drv, const char *path)
+{
+    void * dir = NULL;
+    /*Add your code here*/
+    dir = ...           /*Add your code here*/
+    return dir;
+}
+
+/**
+ * Read the next filename form a directory.
+ * The name of the directories will begin with '/'
+ * @param drv       pointer to a driver where this function belongs
+ * @param rddir_p   pointer to an initialized 'lv_fs_dir_t' variable
+ * @param fn        pointer to a buffer to store the filename
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_dir_read(lv_fs_drv_t * drv, void * rddir_p, char *fn)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+
+/**
+ * Close the directory reading
+ * @param drv       pointer to a driver where this function belongs
+ * @param rddir_p   pointer to an initialized 'lv_fs_dir_t' variable
+ * @return          LV_FS_RES_OK: no error or  any error from @lv_fs_res_t enum
+ */
+static lv_fs_res_t fs_dir_close(lv_fs_drv_t * drv, void * rddir_p)
+{
+    lv_fs_res_t res = LV_FS_RES_NOT_IMP;
+
+    /*Add your code here*/
+
+    return res;
+}
+
+#else /*Enable this file at the top*/
+
+/*This dummy typedef exists purely to silence -Wpedantic.*/
+typedef int keep_pedantic_happy;
+#endif

APP_Framework/lib/lvgl/porting/lv_port_fs_template.h

@@ -0,0 +1,43 @@
+/**
+ * @file lv_port_fs_templ.h
+ *
+ */
+
+ /*Copy this file as "lv_port_fs.h" and set this value to "1" to enable content*/
+#if 0
+
+#ifndef LV_PORT_FS_TEMPL_H
+#define LV_PORT_FS_TEMPL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*********************
+ *      INCLUDES
+ *********************/
+#include "lvgl/lvgl.h"
+
+/*********************
+ *      DEFINES
+ *********************/
+
+/**********************
+ *      TYPEDEFS
+ **********************/
+
+/**********************
+ * GLOBAL PROTOTYPES
+ **********************/
+
+/**********************
+ *      MACROS
+ **********************/
+
+#ifdef __cplusplus
+} /*extern "C"*/
+#endif
+
+#endif /*LV_PORT_FS_TEMPL_H*/
+
+#endif /*Disable/Enable content*/

APP_Framework/lib/lvgl/porting/lv_port_indev_template.c

@@ -0,0 +1,521 @@
+/**
+ * @file lv_port_indev_templ.c
+ *
+ */
+
+ /*Copy this file as "lv_port_indev.c" and set this value to "1" to enable content*/
+#if 1
+
+/*********************
+ *      INCLUDES
+ *********************/
+#include "lv_port_indev_template.h"
+#include "../lvgl.h"
+
+#include <dev_touch.h>
+
+static int touch_fd = 0;
+/*********************
+ *      DEFINES
+ *********************/
+#define LV_USE_INDEV_TOUCHPAD 0x1u
+#define LV_USE_INDEV_MOUSE    0x2u
+#define LV_USE_INDEV_KEYPAD   0x4u
+#define LV_USE_INDEV_ENCODER  0x8u
+#define LV_USE_INDEV_BUTTUN   0x10u
+
+#define PRESS_FAILED_LIMIT    15
+#define LV_USE_INDEV  LV_USE_INDEV_TOUCHPAD  ///< modify this DEFINE to enable the indev device. e.g #define LV_USE_INDEV  LV_USE_INDEV_TOUCHPAD | LV_USE_INDEV_KEYPAD
+
+/**********************
+ *      TYPEDEFS
+ **********************/
+
+/**********************
+ *  STATIC PROTOTYPES
+ **********************/
+#if (LV_USE_INDEV & LV_USE_INDEV_TOUCHPAD) == LV_USE_INDEV_TOUCHPAD
+static void touchpad_init(void);
+static void touchpad_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data);
+// static bool touchpad_is_pressed(void);
+// static void touchpad_get_xy(lv_coord_t * x, lv_coord_t * y);
+static bool touchpad_is_pressed(struct TouchDataStandard* touch_data_ptr);
+static void touchpad_get_xy(struct TouchDataStandard* touch_data_ptr,
+    lv_coord_t* x, lv_coord_t* y);
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_MOUSE) == LV_USE_INDEV_MOUSE
+static void mouse_init(void);
+static void mouse_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data);
+static bool mouse_is_pressed(void);
+static void mouse_get_xy(lv_coord_t * x, lv_coord_t * y);
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_KEYPAD) == LV_USE_INDEV_KEYPAD
+static void keypad_init(void);
+static void keypad_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data);
+static uint32_t keypad_get_key(void);
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_ENCODER) == LV_USE_INDEV_ENCODER
+static void encoder_init(void);
+static void encoder_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data);
+static void encoder_handler(void);
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_BUTTUN) == LV_USE_INDEV_BUTTUN
+static void button_init(void);
+static void button_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data);
+static int8_t button_get_pressed_id(void);
+static bool button_is_pressed(uint8_t id);
+#endif
+
+/**********************
+ *  STATIC VARIABLES
+ **********************/
+#if (LV_USE_INDEV & LV_USE_INDEV_TOUCHPAD) == LV_USE_INDEV_TOUCHPAD
+lv_indev_t * indev_touchpad;
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_MOUSE) == LV_USE_INDEV_MOUSE
+lv_indev_t * indev_mouse;
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_KEYPAD) == LV_USE_INDEV_KEYPAD
+lv_indev_t * indev_keypad;
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_ENCODER) == LV_USE_INDEV_ENCODER
+lv_indev_t * indev_encoder;
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_BUTTUN) == LV_USE_INDEV_BUTTUN
+lv_indev_t * indev_button;
+#endif
+
+static int32_t encoder_diff;
+static lv_indev_state_t encoder_state;
+
+/**********************
+ *      MACROS
+ **********************/
+
+/**********************
+ *   GLOBAL FUNCTIONS
+ **********************/
+
+void lv_port_indev_init(void)
+{
+    /**
+     * Here you will find example implementation of input devices supported by LittelvGL:
+     *  - Touchpad
+     *  - Mouse (with cursor support)
+     *  - Keypad (supports GUI usage only with key)
+     *  - Encoder (supports GUI usage only with: left, right, push)
+     *  - Button (external buttons to press points on the screen)
+     *
+     *  The `..._read()` function are only examples.
+     *  You should shape them according to your hardware
+     */
+
+    static lv_indev_drv_t indev_drv;
+#if (LV_USE_INDEV & LV_USE_INDEV_TOUCHPAD) == LV_USE_INDEV_TOUCHPAD
+    /*------------------
+     * Touchpad
+     * -----------------*/
+
+    /*Initialize your touchpad if you have*/
+    touchpad_init();
+
+    /*Register a touchpad input device*/
+    lv_indev_drv_init(&indev_drv);
+    indev_drv.type = LV_INDEV_TYPE_POINTER;
+    indev_drv.read_cb = touchpad_read;
+    indev_touchpad = lv_indev_drv_register(&indev_drv);
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_MOUSE) == LV_USE_INDEV_MOUSE
+    /*------------------
+     * Mouse
+     * -----------------*/
+
+    /*Initialize your touchpad if you have*/
+    mouse_init();
+
+    /*Register a mouse input device*/
+    lv_indev_drv_init(&indev_drv);
+    indev_drv.type = LV_INDEV_TYPE_POINTER;
+    indev_drv.read_cb = mouse_read;
+    indev_mouse = lv_indev_drv_register(&indev_drv);
+
+    /*Set cursor. For simplicity set a HOME symbol now.*/
+    lv_obj_t * mouse_cursor = lv_img_create(lv_scr_act());
+    lv_img_set_src(mouse_cursor, LV_SYMBOL_HOME);
+    lv_indev_set_cursor(indev_mouse, mouse_cursor);
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_KEYPAD) == LV_USE_INDEV_KEYPAD
+    /*------------------
+     * Keypad
+     * -----------------*/
+
+    /*Initialize your keypad or keyboard if you have*/
+    keypad_init();
+
+    /*Register a keypad input device*/
+    lv_indev_drv_init(&indev_drv);
+    indev_drv.type = LV_INDEV_TYPE_KEYPAD;
+    indev_drv.read_cb = keypad_read;
+    indev_keypad = lv_indev_drv_register(&indev_drv);
+
+    /*Later you should create group(s) with `lv_group_t * group = lv_group_create()`,
+     *add objects to the group with `lv_group_add_obj(group, obj)`
+     *and assign this input device to group to navigate in it:
+     *`lv_indev_set_group(indev_keypad, group);`*/
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_ENCODER) == LV_USE_INDEV_ENCODER
+    /*------------------
+     * Encoder
+     * -----------------*/
+
+    /*Initialize your encoder if you have*/
+    encoder_init();
+
+    /*Register a encoder input device*/
+    lv_indev_drv_init(&indev_drv);
+    indev_drv.type = LV_INDEV_TYPE_ENCODER;
+    indev_drv.read_cb = encoder_read;
+    indev_encoder = lv_indev_drv_register(&indev_drv);
+
+    /*Later you should create group(s) with `lv_group_t * group = lv_group_create()`,
+     *add objects to the group with `lv_group_add_obj(group, obj)`
+     *and assign this input device to group to navigate in it:
+     *`lv_indev_set_group(indev_encoder, group);`*/
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_BUTTUN) == LV_USE_INDEV_BUTTUN
+    /*------------------
+     * Button
+     * -----------------*/
+
+    /*Initialize your button if you have*/
+    button_init();
+
+    /*Register a button input device*/
+    lv_indev_drv_init(&indev_drv);
+    indev_drv.type = LV_INDEV_TYPE_BUTTON;
+    indev_drv.read_cb = button_read;
+    indev_button = lv_indev_drv_register(&indev_drv);
+
+    /*Assign buttons to points on the screen*/
+    static const lv_point_t btn_points[2] = {
+            {10, 10},   /*Button 0 -> x:10; y:10*/
+            {40, 100},  /*Button 1 -> x:40; y:100*/
+    };
+    lv_indev_set_button_points(indev_button, btn_points);
+#endif
+}
+
+/**********************
+ *   STATIC FUNCTIONS
+ **********************/
+#if (LV_USE_INDEV & LV_USE_INDEV_TOUCHPAD) == LV_USE_INDEV_TOUCHPAD
+/*------------------
+ * Touchpad
+ * -----------------*/
+
+/*Initialize your touchpad*/
+static void touchpad_init(void)
+{
+    touch_fd = PrivOpen(PRIV_TOUCH_DEV,O_RDWR);
+    if(touch_fd >= 0) {
+        // printf("touch fd = %d\n",touch_fd);
+    } else {
+        printf("open %s touch fd = %d failed.\n",PRIV_TOUCH_DEV,touch_fd);
+    }
+        
+    /*Your code comes here*/
+}
+
+// static struct TouchDataStandard touch_data;
+
+/*Will be called by the library to read the touchpad*/
+static void touchpad_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data)
+{
+    static lv_coord_t last_x = 0;
+    static lv_coord_t last_y = 0;
+
+    static struct TouchDataStandard touch_data;
+
+    /*Save the pressed coordinates and the state*/
+    if (touchpad_is_pressed(&touch_data)) {
+        touchpad_get_xy(&touch_data, &last_x, &last_y);
+        data->state = LV_INDEV_STATE_PR;
+    } else {
+        data->state = LV_INDEV_STATE_REL;
+    }
+
+    /*Set the last pressed coordinates*/
+    data->point.x = last_x;
+    data->point.y = last_y;
+}
+
+/*Return true is the touchpad is pressed*/
+// static bool touchpad_is_pressed(void)
+// {
+//     int ret;
+//     /*Your code comes here*/
+//     // memset(&touch_data, 0 ,sizeof(TouchDataParam));
+//     memset(&touch_data, 0 ,sizeof(struct TouchDataStandard));
+//     ret = PrivRead(touch_fd, &touch_data, 1);
+//     if (ret && touch_data.x >= 0 && touch_data.x < MY_INDEV_X
+//         && touch_data.y >= 0 && touch_data.y < MY_INDEV_Y)
+//     {
+//         // printf("touch x %d touch y %d\n",touch_data.x,touch_data.y);
+//         return true;
+//     }
+    
+//     return false;
+// }
+
+uint32_t press_failed_cnt = 0;
+static bool touchpad_is_pressed(struct TouchDataStandard* touch_data_ptr)
+{
+    int ret;
+    /*Your code comes here*/
+    memset(touch_data_ptr, 0 ,sizeof(struct TouchDataStandard));
+    ret = PrivRead(touch_fd, touch_data_ptr, 1);
+    if (ret && touch_data_ptr->x > 0 && touch_data_ptr->x < MY_INDEV_X
+        && touch_data_ptr->y > 0 && touch_data_ptr->y < MY_INDEV_Y)
+    {
+        press_failed_cnt = 0;
+        return true;
+    }
+
+    press_failed_cnt++;
+    if (press_failed_cnt >= PRESS_FAILED_LIMIT) {
+        PrivClose(touch_fd);
+        touchpad_init();
+        press_failed_cnt = 0;
+    }
+    
+    return false;
+}
+
+/*Get the x and y coordinates if the touchpad is pressed*/
+static void touchpad_get_xy(struct TouchDataStandard* touch_data_ptr,
+    lv_coord_t* x, lv_coord_t* y) {
+    /*Your code comes here*/
+
+    (*x) = touch_data_ptr->x;
+    (*y) = touch_data_ptr->y;
+}
+
+// static void touchpad_get_xy(lv_coord_t * x, lv_coord_t * y)
+// {
+//     /*Your code comes here*/
+
+//     (*x) = touch_data.x;
+//     (*y) = touch_data.y;
+// }
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_MOUSE) == LV_USE_INDEV_MOUSE
+/*------------------
+ * Mouse
+ * -----------------*/
+
+/*Initialize your mouse*/
+static void mouse_init(void)
+{
+    /*Your code comes here*/
+}
+
+/*Will be called by the library to read the mouse*/
+static void mouse_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data)
+{
+    /*Get the current x and y coordinates*/
+    mouse_get_xy(&data->point.x, &data->point.y);
+
+    /*Get whether the mouse button is pressed or released*/
+    if(mouse_is_pressed()) {
+        data->state = LV_INDEV_STATE_PR;
+    } else {
+        data->state = LV_INDEV_STATE_REL;
+    }
+}
+
+/*Return true is the mouse button is pressed*/
+static bool mouse_is_pressed(void)
+{
+    /*Your code comes here*/
+
+    return false;
+}
+
+/*Get the x and y coordinates if the mouse is pressed*/
+static void mouse_get_xy(lv_coord_t * x, lv_coord_t * y)
+{
+    /*Your code comes here*/
+
+    (*x) = 0;
+    (*y) = 0;
+}
+#endif
+
+
+
+#if (LV_USE_INDEV & LV_USE_INDEV_KEYPAD) == LV_USE_INDEV_KEYPAD
+/*------------------
+ * Keypad
+ * -----------------*/
+
+/*Initialize your keypad*/
+static void keypad_init(void)
+{
+    /*Your code comes here*/
+}
+
+/*Will be called by the library to read the mouse*/
+static void keypad_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data)
+{
+    static uint32_t last_key = 0;
+
+    /*Get the current x and y coordinates*/
+    mouse_get_xy(&data->point.x, &data->point.y);
+
+    /*Get whether the a key is pressed and save the pressed key*/
+    uint32_t act_key = keypad_get_key();
+    if(act_key != 0) {
+        data->state = LV_INDEV_STATE_PR;
+
+        /*Translate the keys to LVGL control characters according to your key definitions*/
+        switch(act_key) {
+        case 1:
+            act_key = LV_KEY_NEXT;
+            break;
+        case 2:
+            act_key = LV_KEY_PREV;
+            break;
+        case 3:
+            act_key = LV_KEY_LEFT;
+            break;
+        case 4:
+            act_key = LV_KEY_RIGHT;
+            break;
+        case 5:
+            act_key = LV_KEY_ENTER;
+            break;
+        }
+
+        last_key = act_key;
+    } else {
+        data->state = LV_INDEV_STATE_REL;
+    }
+
+    data->key = last_key;
+}
+
+/*Get the currently being pressed key.  0 if no key is pressed*/
+static uint32_t keypad_get_key(void)
+{
+    /*Your code comes here*/
+
+    return 0;
+}
+#endif
+
+
+
+#if (LV_USE_INDEV & LV_USE_INDEV_ENCODER) == LV_USE_INDEV_ENCODER
+/*------------------
+ * Encoder
+ * -----------------*/
+
+/*Initialize your keypad*/
+static void encoder_init(void)
+{
+    /*Your code comes here*/
+}
+
+/*Will be called by the library to read the encoder*/
+static void encoder_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data)
+{
+
+    data->enc_diff = encoder_diff;
+    data->state = encoder_state;
+}
+
+/*Call this function in an interrupt to process encoder events (turn, press)*/
+static void encoder_handler(void)
+{
+    /*Your code comes here*/
+
+    encoder_diff += 0;
+    encoder_state = LV_INDEV_STATE_REL;
+}
+#endif
+
+#if (LV_USE_INDEV & LV_USE_INDEV_BUTTUN) == LV_USE_INDEV_BUTTUN
+/*------------------
+ * Button
+ * -----------------*/
+
+/*Initialize your buttons*/
+static void button_init(void)
+{
+    /*Your code comes here*/
+}
+
+/*Will be called by the library to read the button*/
+static void button_read(lv_indev_drv_t * indev_drv, lv_indev_data_t * data)
+{
+
+    static uint8_t last_btn = 0;
+
+    /*Get the pressed button's ID*/
+    int8_t btn_act = button_get_pressed_id();
+
+    if(btn_act >= 0) {
+        data->state = LV_INDEV_STATE_PR;
+        last_btn = btn_act;
+    } else {
+        data->state = LV_INDEV_STATE_REL;
+    }
+
+    /*Save the last pressed button's ID*/
+    data->btn_id = last_btn;
+}
+
+/*Get ID  (0, 1, 2 ..) of the pressed button*/
+static int8_t button_get_pressed_id(void)
+{
+    uint8_t i;
+
+    /*Check to buttons see which is being pressed (assume there are 2 buttons)*/
+    for(i = 0; i < 2; i++) {
+        /*Return the pressed button's ID*/
+        if(button_is_pressed(i)) {
+            return i;
+        }
+    }
+
+    /*No button pressed*/
+    return -1;
+}
+
+/*Test if `id` button is pressed or not*/
+static bool button_is_pressed(uint8_t id)
+{
+
+    /*Your code comes here*/
+
+    return false;
+}
+#endif
+#else /*Enable this file at the top*/
+
+/*This dummy typedef exists purely to silence -Wpedantic.*/
+typedef int keep_pedantic_happy;
+#endif

APP_Framework/lib/lvgl/porting/lv_port_indev_template.h

@@ -0,0 +1,44 @@
+
+/**
+ * @file lv_port_indev_templ.h
+ *
+ */
+
+ /*Copy this file as "lv_port_indev.h" and set this value to "1" to enable content*/
+#if 0
+
+#ifndef LV_PORT_INDEV_TEMPL_H
+#define LV_PORT_INDEV_TEMPL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*********************
+ *      INCLUDES
+ *********************/
+#include "lvgl/lvgl.h"
+
+/*********************
+ *      DEFINES
+ *********************/
+
+/**********************
+ *      TYPEDEFS
+ **********************/
+
+/**********************
+ * GLOBAL PROTOTYPES
+ **********************/
+
+/**********************
+ *      MACROS
+ **********************/
+
+#ifdef __cplusplus
+} /*extern "C"*/
+#endif
+
+#endif /*LV_PORT_INDEV_TEMPL_H*/
+
+#endif /*Disable/Enable content*/

APP_Framework/lib/lvgl/porting/porting.mk

@@ -0,0 +1 @@
+SRC_FILES := $(shell find -L $(LVGL_DIR)/$(LVGL_DIR_NAME)/porting -name \*.c)

APP_Framework/lib/lvgl/src/misc/lv_timer.c

@@ -101,7 +101,7 @@ LV_ATTRIBUTE_TIMER_HANDLER uint32_t lv_timer_handler(void)
         timer_deleted = false;
         timer_created = false;
         LV_GC_ROOT(_lv_timer_act) = _lv_ll_get_head(&LV_GC_ROOT(_lv_timer_ll));
-        while(LV_GC_ROOT(_lv_timer_act)) {
+        while (LV_GC_ROOT(_lv_timer_act)) {
             /*The timer might be deleted if it runs only once ('repeat_count = 1')
              *So get next element until the current is surely valid*/
             next = _lv_ll_get_next(&LV_GC_ROOT(_lv_timer_ll), LV_GC_ROOT(_lv_timer_act));
@@ -113,11 +113,11 @@ LV_ATTRIBUTE_TIMER_HANDLER uint32_t lv_timer_handler(void)
                     break;
                 }
             }
-
             LV_GC_ROOT(_lv_timer_act) = next; /*Load the next timer*/
         }
     } while(LV_GC_ROOT(_lv_timer_act));
 
+    
     uint32_t time_till_next = LV_NO_TIMER_READY;
     next = _lv_ll_get_head(&LV_GC_ROOT(_lv_timer_ll));
     while(next) {
@@ -310,8 +310,8 @@ static bool lv_timer_exec(lv_timer_t * timer)
         if(timer->repeat_count > 0) timer->repeat_count--;
         timer->last_run = lv_tick_get();
         TIMER_TRACE("calling timer callback: %p", *((void **)&timer->timer_cb));
-        if(timer->timer_cb && original_repeat_count != 0) timer->timer_cb(timer);
+        if (timer->timer_cb && original_repeat_count != 0) timer->timer_cb(timer);
-        TIMER_TRACE("timer callback %p finished", *((void **)&timer->timer_cb));
+        TIMER_TRACE("timer callback %p finished", *((void**)&timer->timer_cb));
         LV_ASSERT_MEM_INTEGRITY();
         exec = true;
     }

APP_Framework/lib/lvgl/src/widgets/lv_table.c

@@ -116,7 +116,7 @@ void lv_table_set_cell_value_fmt(lv_obj_t * obj, uint16_t row, uint16_t col, con
     LV_ASSERT_OBJ(obj, MY_CLASS);
     LV_ASSERT_NULL(fmt);
 
-    lv_table_t * table = (lv_table_t *)obj;
+    lv_table_t* table = (lv_table_t*)obj;
     if(col >= table->col_cnt) {
         LV_LOG_WARN("lv_table_set_cell_value: invalid column");
         return;
@@ -183,8 +183,10 @@ void lv_table_set_cell_value_fmt(lv_obj_t * obj, uint16_t row, uint16_t col, con
     /*Refresh the row height*/
     lv_coord_t cell_left = lv_obj_get_style_pad_left(obj, LV_PART_ITEMS);
     lv_coord_t cell_right = lv_obj_get_style_pad_right(obj, LV_PART_ITEMS);
-    lv_coord_t cell_top = lv_obj_get_style_pad_top(obj, LV_PART_ITEMS);
+    // lv_coord_t cell_top = lv_obj_get_style_pad_top(obj, LV_PART_ITEMS);
-    lv_coord_t cell_bottom = lv_obj_get_style_pad_bottom(obj, LV_PART_ITEMS);
+    lv_coord_t cell_top = 3;
+    // lv_coord_t cell_bottom = lv_obj_get_style_pad_bottom(obj, LV_PART_ITEMS);
+    lv_coord_t cell_bottom = 3;
     
     lv_coord_t letter_space = lv_obj_get_style_text_letter_space(obj, LV_PART_ITEMS);
     lv_coord_t line_space = lv_obj_get_style_text_line_space(obj, LV_PART_ITEMS);

Ubiquitous/XiZi/arch/risc-v/Makefile

@@ -1,4 +1,6 @@
+ifeq ($(CONFIG_BOARD_CH32V307VCT6), )
 SRC_DIR :=  shared
+endif
 
 ifeq ($(CONFIG_BOARD_FE310_EVB),y)
 SRC_DIR +=fe310
@@ -28,6 +30,10 @@ ifeq ($(CONFIG_BOARD_GD32VF103RVSTAR),y)
 SRC_DIR +=gd32vf103-rvstar
 endif
 
+ifeq ($(CONFIG_BOARD_CH32V307VCT6), y)
+SRC_DIR +=ch32v307vct6
+endif 
+
 ifeq ($(CONFIG_BOARD_RV32M1_VEGA),y)
 SRC_DIR +=rv32m1-vega
 endif

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Core/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := core_riscv.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Core/core_riscv.c

@@ -0,0 +1,558 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Source File
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/*********************************************************************
+ * @fn      __get_FFLAGS
+ *
+ * @brief   Return the Floating-Point Accrued Exceptions
+ *
+ * @return  fflags value
+ */
+uint32_t __get_FFLAGS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FFLAGS
+ *
+ * @brief   Set the Floating-Point Accrued Exceptions
+ *
+ * @param   value  - set FFLAGS value
+ *
+ * @return  none
+ */
+void __set_FFLAGS(uint32_t value)
+{
+  __ASM volatile ("csrw fflags, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_FRM
+ *
+ * @brief   Return the Floating-Point Dynamic Rounding Mode
+ *
+ * @return  frm value
+ */
+uint32_t __get_FRM(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "frm" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FRM
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set frm value
+ *
+ * @return  none
+ */
+void __set_FRM(uint32_t value)
+{
+  __ASM volatile ("csrw frm, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_FCSR
+ *
+ * @brief   Return the Floating-Point Control and Status Register
+ *
+ * @return  fcsr value
+ */
+uint32_t __get_FCSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FCSR
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set fcsr value
+ *
+ * @return  none
+ */
+void __set_FCSR(uint32_t value)
+{
+  __ASM volatile ("csrw fcsr, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MSTATUS
+ *
+ * @brief   Return the Machine Status Register
+ *
+ * @return  mstatus value
+ */
+uint32_t __get_MSTATUS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MSTATUS
+ *
+ * @brief   Set the Machine Status Register
+ *
+ * @param   value  - set mstatus value
+ *
+ * @return  none
+ */
+void __set_MSTATUS(uint32_t value)
+{
+  __ASM volatile ("csrw mstatus, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MISA
+ *
+ * @brief   Return the Machine ISA Register
+ *
+ * @return  misa value
+ */
+uint32_t __get_MISA(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "misa" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set misa value
+ *
+ * @return  none
+ */
+void __set_MISA(uint32_t value)
+{
+  __ASM volatile ("csrw misa, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MIE
+ *
+ * @brief   Return the Machine Interrupt Enable Register
+ *
+ * @return  mie value
+ */
+uint32_t __get_MIE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mie" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set mie value
+ *
+ * @return  none
+ */
+void __set_MIE(uint32_t value)
+{
+  __ASM volatile ("csrw mie, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Trap-Vector Base-Address Register
+ *
+ * @return  mtvec value
+ */
+uint32_t __get_MTVEC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Trap-Vector Base-Address Register
+ *
+ * @param   value  - set mtvec value
+ *
+ * @return  none
+ */
+void __set_MTVEC(uint32_t value)
+{
+  __ASM volatile ("csrw mtvec, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Seratch Register
+ *
+ * @return  mscratch value
+ */
+uint32_t __get_MSCRATCH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Seratch Register
+ *
+ * @param   value  - set mscratch value
+ *
+ * @return  none
+ */
+void __set_MSCRATCH(uint32_t value)
+{
+  __ASM volatile ("csrw mscratch, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MEPC
+ *
+ * @brief   Return the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+uint32_t __get_MEPC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+void __set_MEPC(uint32_t value)
+{
+  __ASM volatile ("csrw mepc, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCAUSE
+ *
+ * @brief   Return the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MCAUSE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+void __set_MCAUSE(uint32_t value)
+{
+  __ASM volatile ("csrw mcause, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVAL
+ *
+ * @brief   Return the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+uint32_t __get_MTVAL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVAL
+ *
+ * @brief   Set the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+void __set_MTVAL(uint32_t value)
+{
+  __ASM volatile ("csrw mtval, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MIP
+ *
+ * @brief   Return the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+uint32_t __get_MIP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mip" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MIP
+ *
+ * @brief   Set the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+void __set_MIP(uint32_t value)
+{
+  __ASM volatile ("csrw mip, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLE
+ *
+ * @brief   Return Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+uint32_t __get_MCYCLE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLE
+ *
+ * @brief   Set Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+void __set_MCYCLE(uint32_t value)
+{
+  __ASM volatile ("csrw mcycle, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLEH
+ *
+ * @brief   Return Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+uint32_t __get_MCYCLEH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLEH
+ *
+ * @brief   Set Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+void __set_MCYCLEH(uint32_t value)
+{
+  __ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRET
+ *
+ * @brief   Return Lower 32 bits of Instructions-retired counter
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MINSTRET(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRET
+ *
+ * @brief   Set Lower 32 bits of Instructions-retired counter
+ *
+ * @return  minstret value
+ */
+void __set_MINSTRET(uint32_t value)
+{
+  __ASM volatile ("csrw minstret, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRETH
+ *
+ * @brief   Return Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+uint32_t __get_MINSTRETH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRETH
+ *
+ * @brief   Set Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+void __set_MINSTRETH(uint32_t value)
+{
+  __ASM volatile ("csrw minstreth, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MVENDORID
+ *
+ * @brief   Return Vendor ID Register
+ *
+ * @return  mvendorid value
+ */
+uint32_t __get_MVENDORID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MARCHID
+ *
+ * @brief   Return Machine Architecture ID Register
+ *
+ * @return  marchid value
+ */
+uint32_t __get_MARCHID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MIMPID
+ *
+ * @brief   Return Machine Implementation ID Register
+ *
+ * @return  mimpid value
+ */
+uint32_t __get_MIMPID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MHARTID
+ *
+ * @brief   Return Hart ID Register
+ *
+ * @return  mhartid value
+ */
+uint32_t __get_MHARTID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_SP
+ *
+ * @brief   none
+ *
+ * @return  Return SP Register
+ */
+uint32_t __get_SP(void)
+{
+  uint32_t result;
+
+  asm volatile (
+   "mv %0," "sp"
+   : "=r"(result)
+   :
+ );
+  return (result);
+}
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Core/core_riscv.h

@@ -0,0 +1,375 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Header File for CH32V30x
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CORE_RISCV_H__
+#define __CORE_RISCV_H__
+
+/* IO definitions */
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions     */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+/* Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef __I uint64_t vuc64;  /* Read Only */
+typedef __I uint32_t vuc32;  /* Read Only */
+typedef __I uint16_t vuc16;  /* Read Only */
+typedef __I uint8_t vuc8;   /* Read Only */
+
+typedef const uint64_t uc64;  /* Read Only */
+typedef const uint32_t uc32;  /* Read Only */
+typedef const uint16_t uc16;  /* Read Only */
+typedef const uint8_t uc8;   /* Read Only */
+
+typedef __I int64_t vsc64;  /* Read Only */
+typedef __I int32_t vsc32;  /* Read Only */
+typedef __I int16_t vsc16;  /* Read Only */
+typedef __I int8_t vsc8;   /* Read Only */
+
+typedef const int64_t sc64;  /* Read Only */
+typedef const int32_t sc32;  /* Read Only */
+typedef const int16_t sc16;  /* Read Only */
+typedef const int8_t sc8;   /* Read Only */
+
+typedef __IO uint64_t  vu64;
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef uint64_t  u64;
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef __IO int64_t  vs64;
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef int64_t  s64;
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef enum {StatERROR = 0, SUCCESS = !StatERROR} ErrorStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+#define   RV_STATIC_INLINE  static  inline
+
+/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
+typedef struct{
+  __I  uint32_t ISR[8];
+  __I  uint32_t IPR[8];
+  __IO uint32_t ITHRESDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t CFGR;
+  __I  uint32_t GISR;
+  uint8_t VTFIDR[4];
+  uint8_t RESERVED0[12];
+  __IO uint32_t VTFADDR[4];
+  uint8_t RESERVED1[0x90];
+  __O  uint32_t IENR[8];
+  uint8_t RESERVED2[0x60];
+  __O  uint32_t IRER[8];
+  uint8_t RESERVED3[0x60];
+  __O  uint32_t IPSR[8];
+  uint8_t RESERVED4[0x60];
+  __O  uint32_t IPRR[8];
+  uint8_t RESERVED5[0x60];
+  __IO uint32_t IACTR[8];
+  uint8_t RESERVED6[0xE0];
+  __IO uint8_t IPRIOR[256];
+  uint8_t RESERVED7[0x810];
+  __IO uint32_t SCTLR;
+}PFIC_Type;
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+    __IO u32 CTLR;
+    __IO u32 SR;
+    __IO u64 CNT;
+    __IO u64 CMP;
+}SysTick_Type;
+
+
+#define PFIC            ((PFIC_Type *) 0xE000E000 )
+#define NVIC            PFIC
+#define NVIC_KEY1       ((uint32_t)0xFA050000)
+#define NVIC_KEY2               ((uint32_t)0xBCAF0000)
+#define NVIC_KEY3               ((uint32_t)0xBEEF0000)
+
+#define SysTick         ((SysTick_Type *) 0xE000F000)
+
+/*********************************************************************
+ * @fn      __enable_irq
+ *
+ * @brief   Enable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __enable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); }
+
+/*********************************************************************
+ * @fn      __disable_irq
+ *
+ * @brief   Disable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __disable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); }
+
+/*********************************************************************
+ * @fn      __NOP
+ *
+ * @brief   nop
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __NOP() { __asm volatile ("nop"); }
+
+/*********************************************************************
+ * @fn      NVIC_EnableIRQ
+ *
+ * @brief   Enable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
+  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_DisableIRQ
+ *
+ * @brief   Disable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetStatusIRQ
+ *
+ * @brief   Get Interrupt Enable State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Enable
+ *          0 - Interrupt Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetPendingIRQ
+ *
+ * @brief   Get Interrupt Pending State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Pending Enable
+ *          0 - Interrupt Pending Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPendingIRQ
+ *
+ * @brief   Set Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_ClearPendingIRQ
+ *
+ * @brief   Clear Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetActive
+ *
+ * @brief   Get Interrupt Active State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Active
+ *          0 - Interrupt No Active
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPriority
+ *
+ * @brief   Set Interrupt Priority
+ *
+ * @param   IRQn - Interrupt Numbers
+ *          priority -
+ *              bit7 - pre-emption priority
+ *              bit6~bit4 - subpriority
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
+{
+  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
+}
+
+/*********************************************************************
+ * @fn      __WFI
+ *
+ * @brief   Wait for Interrupt
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
+{
+  NVIC->SCTLR &= ~(1<<3);   // wfi
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      __WFE
+ *
+ * @brief   Wait for Events
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
+{
+  uint32_t t;
+
+  t = NVIC->SCTLR;
+  NVIC->SCTLR |= (1<<3)|(1<<5);     // (wfi->wfe)+(__sev)
+  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
+  asm volatile ("wfi");
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      SetVTFIRQ
+ *
+ * @brief   Set VTF Interrupt
+ *
+ * @param   add - VTF interrupt service function base address.
+ *          IRQn -Interrupt Numbers
+ *          num - VTF Interrupt Numbers
+ *          NewState - DISABLE or ENABLE
+ * @return  None
+ */
+RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
+  if(num > 3)  return ;
+
+  if (NewState != DISABLE)
+  {
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)|0x1);
+  }
+  else{
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)&(~0x1));
+  }
+}
+
+/*********************************************************************
+ * @fn      NVIC_SystemReset
+ *
+ * @brief   Initiate a system reset request
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SystemReset(void)
+{
+  NVIC->CFGR = NVIC_KEY3|(1<<7);
+}
+
+
+
+/* Core_Exported_Functions */  
+extern uint32_t __get_FFLAGS(void);
+extern void __set_FFLAGS(uint32_t value);
+extern uint32_t __get_FRM(void);
+extern void __set_FRM(uint32_t value);
+extern uint32_t __get_FCSR(void);
+extern void __set_FCSR(uint32_t value);
+extern uint32_t __get_MSTATUS(void);
+extern void __set_MSTATUS(uint32_t value);
+extern uint32_t __get_MISA(void);
+extern void __set_MISA(uint32_t value);
+extern uint32_t __get_MIE(void);
+extern void __set_MIE(uint32_t value);
+extern uint32_t __get_MTVEC(void);
+extern void __set_MTVEC(uint32_t value);
+extern uint32_t __get_MSCRATCH(void);
+extern void __set_MSCRATCH(uint32_t value);
+extern uint32_t __get_MEPC(void);
+extern void __set_MEPC(uint32_t value);
+extern uint32_t __get_MCAUSE(void);
+extern void __set_MCAUSE(uint32_t value);
+extern uint32_t __get_MTVAL(void);
+extern void __set_MTVAL(uint32_t value);
+extern uint32_t __get_MIP(void);
+extern void __set_MIP(uint32_t value);
+extern uint32_t __get_MCYCLE(void);
+extern void __set_MCYCLE(uint32_t value);
+extern uint32_t __get_MCYCLEH(void);
+extern void __set_MCYCLEH(uint32_t value);
+extern uint32_t __get_MINSTRET(void);
+extern void __set_MINSTRET(uint32_t value);
+extern uint32_t __get_MINSTRETH(void);
+extern void __set_MINSTRETH(uint32_t value);
+extern uint32_t __get_MVENDORID(void);
+extern uint32_t __get_MARCHID(void);
+extern uint32_t __get_MIMPID(void);
+extern uint32_t __get_MHARTID(void);
+extern uint32_t __get_SP(void);
+
+
+
+#endif
+
+
+
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Debug/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := debug.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Debug/debug.c

@@ -0,0 +1,201 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+/*************************************************
+File name: debug.c
+Description: support some basic functions for ch32v30x 
+History: 
+1. Date: 2022-08-09
+Author: AIIT XUOS Lab
+Modification:  
+*************************************************/
+#include "debug.h"
+
+static uint8_t  p_us = 0;
+static uint16_t p_ms = 0;
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */
+void Delay_Init(void)
+{
+    p_us = SystemCoreClock / 8000000;
+    p_ms = (uint16_t)p_us * 1000;
+}
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_us;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_ms;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      USART_Printf_Init
+ *
+ * @brief   Initializes the USARTx peripheral.
+ *
+ * @param   baudrate - USART communication baud rate.
+ *
+ * @return  None
+ */
+void USART_Printf_Init(uint32_t baudrate)
+{
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+
+#if(DEBUG == DEBUG_UART1)
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART2)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART3)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#endif
+
+    USART_InitStructure.USART_BaudRate = baudrate;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+#if(DEBUG == DEBUG_UART1)
+    USART_Init(USART1, &USART_InitStructure);
+    USART_Cmd(USART1, ENABLE);
+
+#elif(DEBUG == DEBUG_UART2)
+    USART_Init(USART2, &USART_InitStructure);
+    USART_Cmd(USART2, ENABLE);
+
+#elif(DEBUG == DEBUG_UART3)
+    USART_Init(USART3, &USART_InitStructure);
+    USART_Cmd(USART3, ENABLE);
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      _write
+ *
+ * @brief   Support Printf Function
+ *
+ * @param   *buf - UART send Data.
+ *          size - Data length
+ *
+ * @return  size: Data length
+ */
+__attribute__((used)) int _write(int fd, char *buf, int size)
+{
+    int i;
+
+    for(i = 0; i < size; i++)
+    {
+#if(DEBUG == DEBUG_UART1)
+        while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+        USART_SendData(USART1, *buf++);
+#elif(DEBUG == DEBUG_UART2)
+        while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
+        USART_SendData(USART2, *buf++);
+#elif(DEBUG == DEBUG_UART3)
+        while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
+        USART_SendData(USART3, *buf++);
+#endif
+    }
+
+    return size;
+}
+
+/*********************************************************************
+ * @fn      _sbrk
+ *
+ * @brief   Change the spatial position of data segment.
+ *
+ * @return  size: Data length
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+    extern char _end[];
+    extern char _heap_end[];
+    static char *curbrk = _end;
+
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+    curbrk += incr;
+    return curbrk - incr;
+}
+
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Debug/debug.h

@@ -0,0 +1,45 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+/*************************************************
+File name: debug.h
+Description: support some basic functions for ch32v30x 
+History: 
+1. Date: 2022-08-09
+Author: AIIT XUOS Lab
+Modification:  
+*************************************************/
+
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#include "stdio.h"
+#include "ch32v30x.h"
+
+/* UART Printf Definition */
+#define DEBUG_UART1    1
+#define DEBUG_UART2    2
+#define DEBUG_UART3    3
+
+/* DEBUG UATR Definition */
+#define DEBUG   DEBUG_UART1
+//#define DEBUG   DEBUG_UART2
+//#define DEBUG   DEBUG_UART3
+
+
+void Delay_Init(void);
+void Delay_Us (uint32_t n);
+void Delay_Ms (uint32_t n);
+void USART_Printf_Init(uint32_t baudrate);
+
+#endif 
+
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := boot.S interrupt.c tick.c switch.S prepare_rhwstack.c interrupt_switch.S
+SRC_DIR := Core User Debug
+# interrupt_switch.S
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/User/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := ch32v30x_it.c system_ch32v30x.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/User/ch32v30x_conf.h

@@ -0,0 +1,51 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_conf.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Library configuration file.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+/*************************************************
+File name: ch32v30x_conf.h
+Description: include peripheral supports for ch32v30x 
+History: 
+1. Date: 2022-08-09
+Author: AIIT XUOS Lab
+Modification:  
+*************************************************/
+#ifndef __CH32V30x_CONF_H
+#define __CH32V30x_CONF_H
+
+#include "ch32v30x_adc.h"
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_can.h"
+#include "ch32v30x_crc.h"
+#include "ch32v30x_dac.h"
+#include "ch32v30x_dbgmcu.h"
+#include "ch32v30x_dma.h"
+#include "ch32v30x_exti.h"
+#include "ch32v30x_flash.h"
+#include "ch32v30x_fsmc.h"
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_i2c.h"
+#include "ch32v30x_iwdg.h"
+#include "ch32v30x_pwr.h"
+#include "ch32v30x_rcc.h"
+#include "ch32v30x_rtc.h"
+#include "ch32v30x_sdio.h"
+#include "ch32v30x_spi.h"
+#include "ch32v30x_tim.h"
+#include "ch32v30x_usart.h"
+#include "ch32v30x_wwdg.h"
+#include "ch32v30x_it.h"
+#include "ch32v30x_misc.h"
+
+
+#endif /* __CH32V30x_CONF_H */
+
+
+	
+	
+	

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/User/ch32v30x_it.c

@@ -0,0 +1,61 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v10x_it.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2020/04/30
+* Description        : Main Interrupt Service Routines.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+/*************************************************
+File name: ch32v30x_it.c
+Description: include peripheral supports for ch32v30x 
+History: 
+1. Date: 2022-08-09
+Author: AIIT XUOS Lab
+Modification:
+1. add HardFault interrupt implementation.
+*************************************************/
+#include "ch32v30x_it.h"
+#include "board.h"
+#include <xs_isr.h>
+
+
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+    GET_INT_SP();
+    isrManager.done->incCounter();
+    KPrintf("NMI_Handler.\n");
+    isrManager.done->decCounter();
+    FREE_INT_SP();
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+    GET_INT_SP();
+    isrManager.done->incCounter();
+    KPrintf("HardFault_Handler.\n");
+    isrManager.done->decCounter();
+    FREE_INT_SP();
+}
+
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/User/ch32v30x_it.h

@@ -0,0 +1,21 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains the headers of the interrupt handlers.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_IT_H
+#define __CH32V30x_IT_H
+
+#include "debug.h"
+
+#define GET_INT_SP()   asm("csrrw sp,mscratch,sp")
+#define FREE_INT_SP()  asm("csrrw sp,mscratch,sp")
+
+
+#endif /* __CH32V30x_IT_H */
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/User/system_ch32v30x.c

@@ -0,0 +1,776 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Source File.
+*                      For HSE = 8Mhz
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+/* #define SYSCLK_FREQ_24MHz  24000000  */ 
+//#define SYSCLK_FREQ_48MHz  48000000
+/* #define SYSCLK_FREQ_56MHz  56000000  */  
+//#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+//#define SYSCLK_FREQ_120MHz  120000000
+#define SYSCLK_FREQ_144MHz  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+
+#elif defined SYSCLK_FREQ_96MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
+
+#else /* HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#elif defined SYSCLK_FREQ_120MHz
+  static void SetSysClockTo120(void);
+#elif defined SYSCLK_FREQ_144MHz
+  static void SetSysClockTo144(void);
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+
+#ifdef CH32V30x_D8C
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+#endif 
+
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+
+#ifdef CH32V30x_D8C
+  RCC->CTLR &= (uint32_t)0xEBFFFFFF;
+  RCC->INTR = 0x00FF0000;
+  RCC->CFGR2 = 0x00000000;
+#else
+  RCC->INTR = 0x009F0000;   
+#endif   
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08: 
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC; 
+      pllmull = ( pllmull >> 18) + 2;
+
+#ifdef CH32V30x_D8
+          if(pllmull == 17) pllmull = 18;
+#else
+          if(pllmull == 2) pllmull = 18;
+          if(pllmull == 15){
+              pllmull = 13;  /* *6.5 */
+              Pll_6_5 = 1;
+          }
+          if(pllmull == 16) pllmull = 15;
+          if(pllmull == 17) pllmull = 16;
+#endif
+
+      if (pllsource == 0x00)
+      {
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {    
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+ 
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;  
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+  SetSysClockTo96();
+#elif defined SYSCLK_FREQ_120MHz
+  SetSysClockTo120();
+#elif defined SYSCLK_FREQ_144MHz
+  SetSysClockTo144();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
+#endif
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo96
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo120
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo144
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#endif

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/User/system_ch32v30x.h

@@ -0,0 +1,31 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Header File.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V30x_H 
+#define __SYSTEM_CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#include<stdint.h>
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V30x_SYSTEM_H */
+
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/arch_interrupt.h

@@ -0,0 +1,13 @@
+#ifndef ARCH_INTERRUPT_H__
+#define ARCH_INTERRUPT_H__
+
+#include "ch32v30x.h"
+#include "core_riscv.h"
+
+#define   ARCH_MAX_IRQ_NUM   128
+#define ARCH_IRQ_NUM_OFFSET 0
+
+int ArchEnableHwIrq(uint32_t irq_num);
+int ArchDisableHwIrq(uint32_t irq_num);
+
+#endif 

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/boot.S

@@ -0,0 +1,389 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : boot.S
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x vector table for eclipse toolchain.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00100073
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .word   TIM8_BRK_IRQHandler        /* TIM8 Break */
+    .word   TIM8_UP_IRQHandler         /* TIM8 Update */
+    .word   TIM8_TRG_COM_IRQHandler    /* TIM8 Trigger and Commutation */
+    .word   TIM8_CC_IRQHandler         /* TIM8 Capture Compare */
+    .word   RNG_IRQHandler             /* RNG */
+    .word   FSMC_IRQHandler            /* FSMC */
+    .word   SDIO_IRQHandler            /* SDIO */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   SPI3_IRQHandler            /* SPI3 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   UART5_IRQHandler           /* UART5 */
+    .word   TIM6_IRQHandler            /* TIM6 */
+    .word   TIM7_IRQHandler            /* TIM7 */
+    .word   DMA2_Channel1_IRQHandler   /* DMA2 Channel 1 */
+    .word   DMA2_Channel2_IRQHandler   /* DMA2 Channel 2 */
+    .word   DMA2_Channel3_IRQHandler   /* DMA2 Channel 3 */
+    .word   DMA2_Channel4_IRQHandler   /* DMA2 Channel 4 */
+    .word   DMA2_Channel5_IRQHandler   /* DMA2 Channel 5 */
+    .word   ETH_IRQHandler             /* ETH */
+    .word   ETH_WKUP_IRQHandler        /* ETH WakeUp */
+    .word   CAN2_TX_IRQHandler         /* CAN2 TX */
+    .word   CAN2_RX0_IRQHandler        /* CAN2 RX0 */
+    .word   CAN2_RX1_IRQHandler        /* CAN2 RX1 */
+    .word   CAN2_SCE_IRQHandler        /* CAN2 SCE */
+    .word   OTG_FS_IRQHandler          /* OTGFS */
+    .word   USBHSWakeup_IRQHandler     /* USBHS Wakeup */
+    .word   USBHS_IRQHandler           /* USBHS */
+    .word   DVP_IRQHandler             /* DVP */
+    .word   UART6_IRQHandler           /* UART6 */
+    .word   UART7_IRQHandler           /* UART7 */
+    .word   UART8_IRQHandler           /* UART8 */
+    .word   TIM9_BRK_IRQHandler        /* TIM9 Break */
+    .word   TIM9_UP_IRQHandler         /* TIM9 Update */
+    .word   TIM9_TRG_COM_IRQHandler    /* TIM9 Trigger and Commutation */
+    .word   TIM9_CC_IRQHandler         /* TIM9 Capture Compare */
+    .word   TIM10_BRK_IRQHandler       /* TIM10 Break */
+    .word   TIM10_UP_IRQHandler        /* TIM10 Update */
+    .word   TIM10_TRG_COM_IRQHandler   /* TIM10 Trigger and Commutation */
+    .word   TIM10_CC_IRQHandler        /* TIM10 Capture Compare */
+    .word   DMA2_Channel6_IRQHandler   /* DMA2 Channel 6 */
+    .word   DMA2_Channel7_IRQHandler   /* DMA2 Channel 7 */
+    .word   DMA2_Channel8_IRQHandler   /* DMA2 Channel 8 */
+    .word   DMA2_Channel9_IRQHandler   /* DMA2 Channel 9 */
+    .word   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
+    .word   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
+
+    .option rvc;
+
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   TIM8_BRK_IRQHandler        /* TIM8 Break */
+    .weak   TIM8_UP_IRQHandler         /* TIM8 Update */
+    .weak   TIM8_TRG_COM_IRQHandler    /* TIM8 Trigger and Commutation */
+    .weak   TIM8_CC_IRQHandler         /* TIM8 Capture Compare */
+    .weak   RNG_IRQHandler             /* RNG */
+    .weak   FSMC_IRQHandler            /* FSMC */
+    .weak   SDIO_IRQHandler            /* SDIO */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   SPI3_IRQHandler            /* SPI3 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   UART5_IRQHandler           /* UART5 */
+    .weak   TIM6_IRQHandler            /* TIM6 */
+    .weak   TIM7_IRQHandler            /* TIM7 */
+    .weak   DMA2_Channel1_IRQHandler   /* DMA2 Channel 1 */
+    .weak   DMA2_Channel2_IRQHandler   /* DMA2 Channel 2 */
+    .weak   DMA2_Channel3_IRQHandler   /* DMA2 Channel 3 */
+    .weak   DMA2_Channel4_IRQHandler   /* DMA2 Channel 4 */
+    .weak   DMA2_Channel5_IRQHandler   /* DMA2 Channel 5 */
+    .weak   ETH_IRQHandler             /* ETH */
+    .weak   ETH_WKUP_IRQHandler        /* ETH WakeUp */
+    .weak   CAN2_TX_IRQHandler         /* CAN2 TX */
+    .weak   CAN2_RX0_IRQHandler        /* CAN2 RX0 */
+    .weak   CAN2_RX1_IRQHandler        /* CAN2 RX1 */
+    .weak   CAN2_SCE_IRQHandler        /* CAN2 SCE */
+    .weak   OTG_FS_IRQHandler          /* OTGFS */
+    .weak   USBHSWakeup_IRQHandler     /* USBHS Wakeup */
+    .weak   USBHS_IRQHandler           /* USBHS */
+    .weak   DVP_IRQHandler             /* DVP */
+    .weak   UART6_IRQHandler           /* UART6 */
+    .weak   UART7_IRQHandler           /* UART7 */
+    .weak   UART8_IRQHandler           /* UART8 */
+    .weak   TIM9_BRK_IRQHandler        /* TIM9 Break */
+    .weak   TIM9_UP_IRQHandler         /* TIM9 Update */
+    .weak   TIM9_TRG_COM_IRQHandler    /* TIM9 Trigger and Commutation */
+    .weak   TIM9_CC_IRQHandler         /* TIM9 Capture Compare */
+    .weak   TIM10_BRK_IRQHandler       /* TIM10 Break */
+    .weak   TIM10_UP_IRQHandler        /* TIM10 Update */
+    .weak   TIM10_TRG_COM_IRQHandler   /* TIM10 Trigger and Commutation */
+    .weak   TIM10_CC_IRQHandler        /* TIM10 Capture Compare */
+    .weak   DMA2_Channel6_IRQHandler   /* DMA2 Channel 6 */
+    .weak   DMA2_Channel7_IRQHandler   /* DMA2 Channel 7 */
+    .weak   DMA2_Channel8_IRQHandler   /* DMA2 Channel 8 */
+    .weak   DMA2_Channel9_IRQHandler   /* DMA2 Channel 9 */
+    .weak   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
+    .weak   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
+
+NMI_Handler:  1:  j 1b
+HardFault_Handler:  1:  j 1b
+Ecall_M_Mode_Handler:  1:  j 1b
+Ecall_U_Mode_Handler:  1:  j 1b
+Break_Point_Handler:  1:  j 1b
+SysTick_Handler:  1:  j 1b
+SW_handler:  1:  j 1b
+WWDG_IRQHandler:  1:  j 1b
+PVD_IRQHandler:  1:  j 1b
+TAMPER_IRQHandler:  1:  j 1b
+RTC_IRQHandler:  1:  j 1b
+FLASH_IRQHandler:  1:  j 1b
+RCC_IRQHandler:  1:  j 1b
+EXTI0_IRQHandler:  1:  j 1b
+EXTI1_IRQHandler:  1:  j 1b
+EXTI2_IRQHandler:  1:  j 1b
+EXTI3_IRQHandler:  1:  j 1b
+EXTI4_IRQHandler:  1:  j 1b
+DMA1_Channel1_IRQHandler:  1:  j 1b
+DMA1_Channel2_IRQHandler:  1:  j 1b
+DMA1_Channel3_IRQHandler:  1:  j 1b
+DMA1_Channel4_IRQHandler:  1:  j 1b
+DMA1_Channel5_IRQHandler:  1:  j 1b
+DMA1_Channel6_IRQHandler:  1:  j 1b
+DMA1_Channel7_IRQHandler:  1:  j 1b
+ADC1_2_IRQHandler:  1:  j 1b
+USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
+USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
+CAN1_RX1_IRQHandler:  1:  j 1b
+CAN1_SCE_IRQHandler:  1:  j 1b
+EXTI9_5_IRQHandler:  1:  j 1b
+TIM1_BRK_IRQHandler:  1:  j 1b
+TIM1_UP_IRQHandler:  1:  j 1b
+TIM1_TRG_COM_IRQHandler:  1:  j 1b
+TIM1_CC_IRQHandler:  1:  j 1b
+TIM2_IRQHandler:  1:  j 1b
+TIM3_IRQHandler:  1:  j 1b
+TIM4_IRQHandler:  1:  j 1b
+I2C1_EV_IRQHandler:  1:  j 1b
+I2C1_ER_IRQHandler:  1:  j 1b
+I2C2_EV_IRQHandler:  1:  j 1b
+I2C2_ER_IRQHandler:  1:  j 1b
+SPI1_IRQHandler:  1:  j 1b
+SPI2_IRQHandler:  1:  j 1b
+USART1_IRQHandler:  1:  j 1b
+USART2_IRQHandler:  1:  j 1b
+USART3_IRQHandler:  1:  j 1b
+EXTI15_10_IRQHandler:  1:  j 1b
+RTCAlarm_IRQHandler:  1:  j 1b
+USBWakeUp_IRQHandler:  1:  j 1b
+TIM8_BRK_IRQHandler:  1:  j 1b
+TIM8_UP_IRQHandler:  1:  j 1b
+TIM8_TRG_COM_IRQHandler:  1:  j 1b
+TIM8_CC_IRQHandler:  1:  j 1b
+RNG_IRQHandler:  1:  j 1b
+FSMC_IRQHandler:  1:  j 1b
+SDIO_IRQHandler:  1:  j 1b
+TIM5_IRQHandler:  1:  j 1b
+SPI3_IRQHandler:  1:  j 1b
+UART4_IRQHandler:  1:  j 1b
+UART5_IRQHandler:  1:  j 1b
+TIM6_IRQHandler:  1:  j 1b
+TIM7_IRQHandler:  1:  j 1b
+DMA2_Channel1_IRQHandler:  1:  j 1b
+DMA2_Channel2_IRQHandler:  1:  j 1b
+DMA2_Channel3_IRQHandler:  1:  j 1b
+DMA2_Channel4_IRQHandler:  1:  j 1b
+DMA2_Channel5_IRQHandler:  1:  j 1b
+ETH_IRQHandler:  1:  j 1b
+ETH_WKUP_IRQHandler:  1:  j 1b
+CAN2_TX_IRQHandler:  1:  j 1b
+CAN2_RX0_IRQHandler:  1:  j 1b
+CAN2_RX1_IRQHandler:  1:  j 1b
+CAN2_SCE_IRQHandler:  1:  j 1b
+OTG_FS_IRQHandler:  1:  j 1b
+USBHSWakeup_IRQHandler:  1:  j 1b
+USBHS_IRQHandler:  1:  j 1b
+DVP_IRQHandler:  1:  j 1b
+UART6_IRQHandler:  1:  j 1b
+UART7_IRQHandler:  1:  j 1b
+UART8_IRQHandler:  1:  j 1b
+TIM9_BRK_IRQHandler:  1:  j 1b
+TIM9_UP_IRQHandler:  1:  j 1b
+TIM9_TRG_COM_IRQHandler:  1:  j 1b
+TIM9_CC_IRQHandler:  1:  j 1b
+TIM10_BRK_IRQHandler:  1:  j 1b
+TIM10_UP_IRQHandler:  1:  j 1b
+TIM10_TRG_COM_IRQHandler:  1:  j 1b
+TIM10_CC_IRQHandler:  1:  j 1b
+DMA2_Channel6_IRQHandler:  1:  j 1b
+DMA2_Channel7_IRQHandler:  1:  j 1b
+DMA2_Channel8_IRQHandler:  1:  j 1b
+DMA2_Channel9_IRQHandler:  1:  j 1b
+DMA2_Channel10_IRQHandler:  1:  j 1b
+DMA2_Channel11_IRQHandler:  1:  j 1b
+
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+    csrw mepc, t0
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+	/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+	/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+    li t0, 0x1f
+    csrw 0xbc0, t0
+
+    /* Enable nested and hardware stack */
+	li t0, 0x1f
+	csrw 0x804, t0
+#	csrw 0x804, zero
+
+    /* Enable floating point and interrupt */
+   	li t0, 0x7800
+   	csrs mstatus, t0
+
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, entry
+	csrw mepc, t0
+	mret
+
+

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/cpuport.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ */
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+#ifndef CPUPORT_H__
+#define CPUPORT_H__
+
+/* bytes of register width  */
+//#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+
+#ifdef ARCH_CPU_64BIT
+#define STORE                   sd
+#define LOAD                    ld
+#define StoreDS                 "sd"
+#define LoadDS                  "ld"
+#define REGBYTES                8
+#define RegLength               8
+#define RegLengthS              "8"
+#else
+#define STORE                   sw
+#define LOAD                    lw
+#define StoreDS                 "sw"
+#define LoadDS                  "lw"
+#define RegLength               4
+#define REGBYTES                4
+#define RegLengthS              "4"
+#endif
+
+/* FPU */
+#ifdef ARCH_RISCV_FPU
+#ifdef ARCH_RISCV_FPU_D
+#define FSTORE                  fsd
+#define FLOAD                   fld
+#define FREGBYTES               8
+#endif
+#ifdef ARCH_RISCV_FPU_S
+#define FSTORE                  fsw
+#define FLOAD                   flw
+#define FREGBYTES               4
+#endif
+#endif
+
+#endif

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/interrupt.c

@@ -0,0 +1,142 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+#include <xs_assign.h>
+#include <xs_base.h>
+#include <xs_isr.h>
+#include <xs_ktask.h>
+#include "ch32v30x.h"
+#include "cpuport.h"
+#include "core_riscv.h"
+#ifdef  TASK_ISOLATION
+#include <xs_service.h>
+#endif
+
+extern x_ubase interrupt_from_sp;
+extern x_ubase interrupt_to_sp;
+extern x_ubase interrupt_new_task;
+
+void sw_setpend(void)
+{
+    SysTick->CTLR |= (1<<31);
+}
+
+/*
+ * clear soft interrupt
+ */
+void sw_clearpend(void)
+{
+    SysTick->CTLR &= ~(1<<31);
+}
+
+x_base DisableLocalInterrupt()
+{
+    x_base level;
+    asm volatile ("csrrci %0, mstatus, 8" : "=r"(level));
+    return level;
+}
+
+void EnableLocalInterrupt(x_base level)
+{
+    asm volatile ("csrw mstatus, %0" :: "r"(level));
+}
+
+int ArchEnableHwIrq(uint32_t irq_num)
+{
+    NVIC_SetPriority(irq_num, 1);
+    NVIC_EnableIRQ(irq_num);
+}
+
+int ArchDisableHwIrq(uint32_t irq_num)
+{
+    NVIC_DisableIRQ(irq_num);
+}
+
+struct ExceptionStackFrame
+{
+    uint64_t x1;
+    uint64_t x2;
+    uint64_t x3;
+    uint64_t x4;
+    uint64_t x5;
+    uint64_t x6;
+    uint64_t x7;
+    uint64_t x8;
+    uint64_t x9;
+    uint64_t x10;
+    uint64_t x11;
+    uint64_t x12;
+    uint64_t x13;
+    uint64_t x14;
+    uint64_t x15;
+    uint64_t x16;
+    uint64_t x17;
+    uint64_t x18;
+    uint64_t x19;
+    uint64_t x20;
+    uint64_t x21;
+    uint64_t x22;
+    uint64_t x23;
+    uint64_t x24;
+    uint64_t x25;
+    uint64_t x26;
+    uint64_t x27;
+    uint64_t x28;
+    uint64_t x29;
+    uint64_t x30;
+    uint64_t x31;
+};
+
+void PrintStackFrame(uintptr_t * sp)
+{
+    struct ExceptionStackFrame * esf = (struct ExceptionStackFrame *)(sp+1);
+
+    KPrintf("\n=================================================================\n");
+    KPrintf("x1 (ra   : Return address                ) ==> 0x%08x%08x\n", esf->x1 >> 32  , esf->x1 & UINT32_MAX);
+    KPrintf("x2 (sp   : Stack pointer                 ) ==> 0x%08x%08x\n", esf->x2 >> 32  , esf->x2 & UINT32_MAX);
+    KPrintf("x3 (gp   : Global pointer                ) ==> 0x%08x%08x\n", esf->x3 >> 32  , esf->x3 & UINT32_MAX);
+    KPrintf("x4 (tp   : Task pointer                  ) ==> 0x%08x%08x\n", esf->x4 >> 32  , esf->x4 & UINT32_MAX);
+    KPrintf("x5 (t0   : Temporary                     ) ==> 0x%08x%08x\n", esf->x5 >> 32  , esf->x5 & UINT32_MAX);
+    KPrintf("x6 (t1   : Temporary                     ) ==> 0x%08x%08x\n", esf->x6 >> 32  , esf->x6 & UINT32_MAX);
+    KPrintf("x7 (t2   : Temporary                     ) ==> 0x%08x%08x\n", esf->x7 >> 32  , esf->x7 & UINT32_MAX);
+    KPrintf("x8 (s0/fp: Save register,frame pointer   ) ==> 0x%08x%08x\n", esf->x8 >> 32  , esf->x8 & UINT32_MAX);
+    KPrintf("x9 (s1   : Save register                 ) ==> 0x%08x%08x\n", esf->x9 >> 32  , esf->x9 & UINT32_MAX);
+    KPrintf("x10(a0   : Function argument,return value) ==> 0x%08x%08x\n", esf->x10 >> 32 , esf->x10 & UINT32_MAX);
+    KPrintf("x11(a1   : Function argument,return value) ==> 0x%08x%08x\n", esf->x11 >> 32 , esf->x11 & UINT32_MAX);
+    KPrintf("x12(a2   : Function argument             ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MAX);
+    KPrintf("x13(a3   : Function argument             ) ==> 0x%08x%08x\n", esf->x13 >> 32 , esf->x13 & UINT32_MAX);
+    KPrintf("x14(a4   : Function argument             ) ==> 0x%08x%08x\n", esf->x14 >> 32 , esf->x14 & UINT32_MAX);
+    KPrintf("x15(a5   : Function argument             ) ==> 0x%08x%08x\n", esf->x15 >> 32 , esf->x15 & UINT32_MAX);
+    KPrintf("x16(a6   : Function argument             ) ==> 0x%08x%08x\n", esf->x16 >> 32 , esf->x16 & UINT32_MAX);
+    KPrintf("x17(a7   : Function argument             ) ==> 0x%08x%08x\n", esf->x17 >> 32 , esf->x17 & UINT32_MAX);
+    KPrintf("x18(s2   : Save register                 ) ==> 0x%08x%08x\n", esf->x18 >> 32 , esf->x18 & UINT32_MAX);
+    KPrintf("x19(s3   : Save register                 ) ==> 0x%08x%08x\n", esf->x19 >> 32 , esf->x19 & UINT32_MAX);
+    KPrintf("x20(s4   : Save register                 ) ==> 0x%08x%08x\n", esf->x20 >> 32 , esf->x20 & UINT32_MAX);
+    KPrintf("x21(s5   : Save register                 ) ==> 0x%08x%08x\n", esf->x21 >> 32 , esf->x21 & UINT32_MAX);
+    KPrintf("x22(s6   : Save register                 ) ==> 0x%08x%08x\n", esf->x22 >> 32 , esf->x22 & UINT32_MAX);
+    KPrintf("x23(s7   : Save register                 ) ==> 0x%08x%08x\n", esf->x23 >> 32 , esf->x23 & UINT32_MAX);
+    KPrintf("x24(s8   : Save register                 ) ==> 0x%08x%08x\n", esf->x24 >> 32 , esf->x24 & UINT32_MAX);
+    KPrintf("x25(s9   : Save register                 ) ==> 0x%08x%08x\n", esf->x25 >> 32 , esf->x25 & UINT32_MAX);
+    KPrintf("x26(s10  : Save register                 ) ==> 0x%08x%08x\n", esf->x26 >> 32 , esf->x26 & UINT32_MAX);
+    KPrintf("x27(s11  : Save register                 ) ==> 0x%08x%08x\n", esf->x27 >> 32 , esf->x27 & UINT32_MAX);
+    KPrintf("x28(t3   : Temporary                     ) ==> 0x%08x%08x\n", esf->x28 >> 32 , esf->x28 & UINT32_MAX);
+    KPrintf("x29(t4   : Temporary                     ) ==> 0x%08x%08x\n", esf->x29 >> 32 , esf->x29 & UINT32_MAX);
+    KPrintf("x30(t5   : Temporary                     ) ==> 0x%08x%08x\n", esf->x30 >> 32 , esf->x30 & UINT32_MAX);
+    KPrintf("x31(t6   : Temporary                     ) ==> 0x%08x%08x\n", esf->x31 >> 32 , esf->x31 & UINT32_MAX);
+    KPrintf("=================================================================\n");
+}
+
+void HwInterruptcontextSwitch(x_ubase from_sp, x_ubase to_sp, struct TaskDescriptor* new_task, void* context) {
+    interrupt_from_sp = (x_ubase)from_sp;
+    interrupt_to_sp = (x_ubase)to_sp;
+    interrupt_new_task = (x_ubase)new_task;
+    sw_setpend();
+}

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/interrupt_switch.S

@@ -0,0 +1,115 @@
+#include "cpuport.h"
+
+.global SW_handler
+.align 2
+SW_handler:
+    /* save all from thread context */
+#ifdef ARCH_RISCV_FPU
+    addi    sp, sp, -32 * FREGBYTES
+    FSTORE  f0, 0 * FREGBYTES(sp)
+    FSTORE  f1, 1 * FREGBYTES(sp)
+    FSTORE  f2, 2 * FREGBYTES(sp)
+    FSTORE  f3, 3 * FREGBYTES(sp)
+    FSTORE  f4, 4 * FREGBYTES(sp)
+    FSTORE  f5, 5 * FREGBYTES(sp)
+    FSTORE  f6, 6 * FREGBYTES(sp)
+    FSTORE  f7, 7 * FREGBYTES(sp)
+    FSTORE  f8, 8 * FREGBYTES(sp)
+    FSTORE  f9, 9 * FREGBYTES(sp)
+    FSTORE  f10, 10 * FREGBYTES(sp)
+    FSTORE  f11, 11 * FREGBYTES(sp)
+    FSTORE  f12, 12 * FREGBYTES(sp)
+    FSTORE  f13, 13 * FREGBYTES(sp)
+    FSTORE  f14, 14 * FREGBYTES(sp)
+    FSTORE  f15, 15 * FREGBYTES(sp)
+    FSTORE  f16, 16 * FREGBYTES(sp)
+    FSTORE  f17, 17 * FREGBYTES(sp)
+    FSTORE  f18, 18 * FREGBYTES(sp)
+    FSTORE  f19, 19 * FREGBYTES(sp)
+    FSTORE  f20, 20 * FREGBYTES(sp)
+    FSTORE  f21, 21 * FREGBYTES(sp)
+    FSTORE  f22, 22 * FREGBYTES(sp)
+    FSTORE  f23, 23 * FREGBYTES(sp)
+    FSTORE  f24, 24 * FREGBYTES(sp)
+    FSTORE  f25, 25 * FREGBYTES(sp)
+    FSTORE  f26, 26 * FREGBYTES(sp)
+    FSTORE  f27, 27 * FREGBYTES(sp)
+    FSTORE  f28, 28 * FREGBYTES(sp)
+    FSTORE  f29, 29 * FREGBYTES(sp)
+    FSTORE  f30, 30 * FREGBYTES(sp)
+    FSTORE  f31, 31 * FREGBYTES(sp)
+#endif
+
+    addi sp, sp, -32 * REGBYTES
+    STORE x5,   5 * REGBYTES(sp)
+
+    /* saved MPIE */
+ 	li    t0,   0x80
+    STORE t0,   2 * REGBYTES(sp)
+
+	/* Temporarily disable HPE  */
+	li   t0,    0x20
+	csrs 0x804, t0
+
+    STORE x1,   1 * REGBYTES(sp)
+    STORE x4,   4 * REGBYTES(sp)
+    STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+    csrr  a0, mepc
+    STORE a0, 0 * REGBYTES(sp)
+
+    /* switch to interrupt stack */
+	csrrw sp,mscratch,sp
+    /* clear interrupt */
+    jal   sw_clearpend
+    /* switch to from thread stack */
+	csrrw sp,mscratch,sp
+
+    csrr  a0, mepc
+    STORE a0, 0 * REGBYTES(sp)
+
+    la    s0, interrupt_from_sp
+    LOAD  s1, 0(s0) 
+    STORE sp, 0(s1)
+
+    la    s0, interrupt_to_sp
+    LOAD  s1, 0(s0) 
+    LOAD  sp, 0(s1)
+
+
+    LOAD  a0,  0 * REGBYTES(sp)
+    csrw  mepc, a0
+
+    LOAD  x1,  1 * REGBYTES(sp)
+
+	li t0,0x7800
+	csrs mstatus, t0
+	LOAD t0, 2*REGBYTES(sp)
+	csrs mstatus, t0
+
+	j  SwitchKTaskContextExit

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/prepare_rhwstack.c

@@ -0,0 +1,151 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+#include "cpuport.h"
+#include <board.h>
+#include <xs_base.h>
+#include <xs_ktask.h>
+#include <xs_isr.h>
+#ifdef  TASK_ISOLATION
+#include "encoding.h"
+#include <stdint.h>
+#include <xs_isolation.h>
+#endif
+
+volatile x_ubase interrupt_from_sp = 0;
+volatile x_ubase interrupt_to_sp = 0;
+volatile x_ubase interrupt_new_task = 0;
+
+struct StackRegisterContext
+{
+    x_ubase epc;        
+    x_ubase ra;         
+    x_ubase mstatus;    
+    x_ubase gp;         
+    x_ubase tp;         
+    x_ubase t0;         
+    x_ubase t1;         
+    x_ubase t2;         
+    x_ubase s0_fp;      
+    x_ubase s1;         
+    x_ubase a0;         
+    x_ubase a1;       
+    x_ubase a2;         
+    x_ubase a3;         
+    x_ubase a4;         
+    x_ubase a5;         
+    x_ubase a6;         
+    x_ubase a7;         
+    x_ubase s2;         
+    x_ubase s3;        
+    x_ubase s4;         
+    x_ubase s5;         
+    x_ubase s6;         
+    x_ubase s7;       
+    x_ubase s8;        
+    x_ubase s9;       
+    x_ubase s10;      
+    x_ubase s11;        
+    x_ubase t3;       
+    x_ubase t4;     
+    x_ubase t5;         
+    x_ubase t6;
+
+/* float register */
+#ifdef ARCH_RISCV_FPU
+    x_ubase f0;      /* f0  */
+    x_ubase f1;      /* f1  */
+    x_ubase f2;      /* f2  */
+    x_ubase f3;      /* f3  */
+    x_ubase f4;      /* f4  */
+    x_ubase f5;      /* f5  */
+    x_ubase f6;      /* f6  */
+    x_ubase f7;      /* f7  */
+    x_ubase f8;      /* f8  */
+    x_ubase f9;      /* f9  */
+    x_ubase f10;     /* f10 */
+    x_ubase f11;     /* f11 */
+    x_ubase f12;     /* f12 */
+    x_ubase f13;     /* f13 */
+    x_ubase f14;     /* f14 */
+    x_ubase f15;     /* f15 */
+    x_ubase f16;     /* f16 */
+    x_ubase f17;     /* f17 */
+    x_ubase f18;     /* f18 */
+    x_ubase f19;     /* f19 */
+    x_ubase f20;     /* f20 */
+    x_ubase f21;     /* f21 */
+    x_ubase f22;     /* f22 */
+    x_ubase f23;     /* f23 */
+    x_ubase f24;     /* f24 */
+    x_ubase f25;     /* f25 */
+    x_ubase f26;     /* f26 */
+    x_ubase f27;     /* f27 */
+    x_ubase f28;     /* f28 */
+    x_ubase f29;     /* f29 */
+    x_ubase f30;     /* f30 */
+    x_ubase f31;     /* f31 */
+#endif
+};
+
+uint8 KTaskStackSetup(struct TaskDescriptor *task)
+{
+    struct StackRegisterContext *stack_contex;
+    int  i;
+
+    task->stack_point  = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), RegLength);
+    task->stack_point -= sizeof(struct StackRegisterContext);
+    stack_contex = (struct StackRegisterContext *)task->stack_point;
+
+    for (i = 0; i < sizeof(struct StackRegisterContext) / sizeof(x_ubase); i++)
+        ((x_ubase *)stack_contex)[i] = 0xfadeface;
+
+#ifdef  SEPARATE_COMPILE
+    if (task->task_dync_sched_member.isolation_flag == 1) {
+        stack_contex->ra      = (unsigned long)USERSPACE->us_taskquit;
+    } else {
+         stack_contex->ra      = (x_ubase)KTaskQuit;
+    }
+        
+#else
+    stack_contex->ra      = (x_ubase)KTaskQuit;
+#endif
+
+    stack_contex->a0      = (x_ubase)task->task_base_info.func_param;
+    stack_contex->epc     = (x_ubase)task->task_base_info.func_entry;
+
+#ifdef  TASK_ISOLATION
+    stack_contex->tp     = (x_ubase)task;
+    if(task->task_dync_sched_member.isolation_flag == 1)
+        stack_contex->mstatus = 0x00006080;
+    else
+#endif
+        stack_contex->mstatus = 0x00007880;
+
+    return EOK;
+}
+
+#ifdef  TASK_ISOLATION
+void RestoreMstatus(uintptr_t *sp)
+{
+    struct TaskDescriptor *tid;
+    tid = (struct TaskDescriptor *)(sp[4]);
+    if(tid->task_dync_sched_member.isolation_flag == 1 && tid->task_dync_sched_member.isolation_status == 0){
+        CLEAR_CSR(mstatus, (MSTATUS_MPP));
+#ifdef MOMERY_PROTECT_ENABLE
+        mem_access.Load(tid->task_dync_sched_member.isolation);
+#endif
+    }else{
+        SET_CSR(mstatus, MSTATUS_MPP);
+    }
+}
+#endif

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/switch.S

@@ -0,0 +1,200 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+#include "cpuport.h"
+
+    .global SwitchKTaskContextExit
+SwitchKTaskContextExit:
+    /* resw ra to mepc */
+    LOAD a0,   0 * REGBYTES(sp)
+    csrw mepc, a0
+
+    LOAD ra,   1 * REGBYTES(sp)
+
+	/* keep machine mode */
+	li    a0,      0x7800
+	csrw  mstatus, a0
+	/* resume MPIE */
+	LOAD  a0,      2*REGBYTES(sp)
+    csrs  mstatus, a0
+
+    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x5,   5 * REGBYTES(sp)
+    LOAD x6,   6 * REGBYTES(sp)
+    LOAD x7,   7 * REGBYTES(sp)
+    LOAD x8,   8 * REGBYTES(sp)
+    LOAD x9,   9 * REGBYTES(sp)
+    LOAD x10, 10 * REGBYTES(sp)
+    LOAD x11, 11 * REGBYTES(sp)
+    LOAD x12, 12 * REGBYTES(sp)
+    LOAD x13, 13 * REGBYTES(sp)
+    LOAD x14, 14 * REGBYTES(sp)
+    LOAD x15, 15 * REGBYTES(sp)
+    LOAD x16, 16 * REGBYTES(sp)
+    LOAD x17, 17 * REGBYTES(sp)
+    LOAD x18, 18 * REGBYTES(sp)
+    LOAD x19, 19 * REGBYTES(sp)
+    LOAD x20, 20 * REGBYTES(sp)
+    LOAD x21, 21 * REGBYTES(sp)
+    LOAD x22, 22 * REGBYTES(sp)
+    LOAD x23, 23 * REGBYTES(sp)
+    LOAD x24, 24 * REGBYTES(sp)
+    LOAD x25, 25 * REGBYTES(sp)
+    LOAD x26, 26 * REGBYTES(sp)
+    LOAD x27, 27 * REGBYTES(sp)
+    LOAD x28, 28 * REGBYTES(sp)
+    LOAD x29, 29 * REGBYTES(sp)
+    LOAD x30, 30 * REGBYTES(sp)
+    LOAD x31, 31 * REGBYTES(sp)
+    addi sp,  sp, 32 * REGBYTES
+
+ /* load float reg */
+#ifdef ARCH_RISCV_FPU
+
+    FLOAD   f0, 0 * FREGBYTES(sp)
+    FLOAD   f1, 1 * FREGBYTES(sp)
+    FLOAD   f2, 2 * FREGBYTES(sp)
+    FLOAD   f3, 3 * FREGBYTES(sp)
+    FLOAD   f4, 4 * FREGBYTES(sp)
+    FLOAD   f5, 5 * FREGBYTES(sp)
+    FLOAD   f6, 6 * FREGBYTES(sp)
+    FLOAD   f7, 7 * FREGBYTES(sp)
+    FLOAD   f8, 8 * FREGBYTES(sp)
+    FLOAD   f9, 9 * FREGBYTES(sp)
+    FLOAD   f10, 10 * FREGBYTES(sp)
+    FLOAD   f11, 11 * FREGBYTES(sp)
+    FLOAD   f12, 12 * FREGBYTES(sp)
+    FLOAD   f13, 13 * FREGBYTES(sp)
+    FLOAD   f14, 14 * FREGBYTES(sp)
+    FLOAD   f15, 15 * FREGBYTES(sp)
+    FLOAD   f16, 16 * FREGBYTES(sp)
+    FLOAD   f17, 17 * FREGBYTES(sp)
+    FLOAD   f18, 18 * FREGBYTES(sp)
+    FLOAD   f19, 19 * FREGBYTES(sp)
+    FLOAD   f20, 20 * FREGBYTES(sp)
+    FLOAD   f21, 21 * FREGBYTES(sp)
+    FLOAD   f22, 22 * FREGBYTES(sp)
+    FLOAD   f23, 23 * FREGBYTES(sp)
+    FLOAD   f24, 24 * FREGBYTES(sp)
+    FLOAD   f25, 25 * FREGBYTES(sp)
+    FLOAD   f26, 26 * FREGBYTES(sp)
+    FLOAD   f27, 27 * FREGBYTES(sp)
+    FLOAD   f28, 28 * FREGBYTES(sp)
+    FLOAD   f29, 29 * FREGBYTES(sp)
+    FLOAD   f30, 30 * FREGBYTES(sp)
+    FLOAD   f31, 31 * FREGBYTES(sp)
+    addi    sp, sp, 32 * FREGBYTES
+#endif
+    mret
+
+    .global SwitchKtaskContextTo
+SwitchKtaskContextTo:
+    /* first save interrupt stack */
+	la t0, _eusrstack
+	addi t0, t0, -512
+    csrw mscratch,t0
+
+    LOAD sp, (a0)
+    MOVE a0, a1
+    jal  RestoreCpusLockStatus
+    LOAD a0, 2 * REGBYTES(sp)
+    csrw mstatus, a0
+    j    SwitchKTaskContextExit
+
+    .global SwitchKtaskContext
+SwitchKtaskContext:
+    /* switch in thread */
+#ifdef ARCH_RISCV_FPU
+	addi sp, sp, -32*FREGBYTES
+
+    FSTORE  f0, 0 * FREGBYTES(sp)
+    FSTORE  f1, 1 * FREGBYTES(sp)
+    FSTORE  f2, 2 * FREGBYTES(sp)
+    FSTORE  f3, 3 * FREGBYTES(sp)
+    FSTORE  f4, 4 * FREGBYTES(sp)
+    FSTORE  f5, 5 * FREGBYTES(sp)
+    FSTORE  f6, 6 * FREGBYTES(sp)
+    FSTORE  f7, 7 * FREGBYTES(sp)
+    FSTORE  f8, 8 * FREGBYTES(sp)
+    FSTORE  f9, 9 * FREGBYTES(sp)
+    FSTORE  f10, 10 * FREGBYTES(sp)
+    FSTORE  f11, 11 * FREGBYTES(sp)
+    FSTORE  f12, 12 * FREGBYTES(sp)
+    FSTORE  f13, 13 * FREGBYTES(sp)
+    FSTORE  f14, 14 * FREGBYTES(sp)
+    FSTORE  f15, 15 * FREGBYTES(sp)
+    FSTORE  f16, 16 * FREGBYTES(sp)
+    FSTORE  f17, 17 * FREGBYTES(sp)
+    FSTORE  f18, 18 * FREGBYTES(sp)
+    FSTORE  f19, 19 * FREGBYTES(sp)
+    FSTORE  f20, 20 * FREGBYTES(sp)
+    FSTORE  f21, 21 * FREGBYTES(sp)
+    FSTORE  f22, 22 * FREGBYTES(sp)
+    FSTORE  f23, 23 * FREGBYTES(sp)
+    FSTORE  f24, 24 * FREGBYTES(sp)
+    FSTORE  f25, 25 * FREGBYTES(sp)
+    FSTORE  f26, 26 * FREGBYTES(sp)
+    FSTORE  f27, 27 * FREGBYTES(sp)
+    FSTORE  f28, 28 * FREGBYTES(sp)
+    FSTORE  f29, 29 * FREGBYTES(sp)
+    FSTORE  f30, 30 * FREGBYTES(sp)
+    FSTORE  f31, 31 * FREGBYTES(sp)
+#endif
+
+	addi sp, sp, -32 * REGBYTES
+	/* save from sp */
+	STORE sp,   0(a0)
+	/* save ra to epc */
+	STORE x1,   0 * REGBYTES(sp)
+	STORE x1,   1 * REGBYTES(sp)
+	STORE x5,   5 * REGBYTES(sp) 
+
+	csrr  t0,  mstatus
+	andi  t0, t0, 8
+	/* if MIE be enabled,set MPIE */
+	beqz  t0, 1f
+	li    t0, 0x80
+
+1:  STORE t0,   2 * REGBYTES(sp)
+	STORE x4,   4 * REGBYTES(sp)
+    
+	STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+	/* get "to" thread sp */
+	LOAD  sp,  (a1)
+    /*MOVE  a0,  a2
+    jal  RestoreCpusLockStatus*/
+	j  SwitchKTaskContextExit

Ubiquitous/XiZi/arch/risc-v/ch32v307vct6/tick.c

@@ -0,0 +1,39 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+#include <xs_ktick.h>
+#include <xs_isr.h>
+#include <xs_assign.h>
+#include "ch32v30x.h"
+#include "ch32v30x_it.h"
+#include "core_riscv.h"
+
+extern void KTaskOsAssignAfterIrq(void *);
+
+void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void SysTick_Handler(void)
+{
+    GET_INT_SP();
+    /* enter interrupt */
+    x_base level;
+    level = DisableLocalInterrupt();
+    isrManager.done->incCounter();
+    EnableLocalInterrupt(level);
+    SysTick->SR = 0;
+    TickAndTaskTimesliceUpdate();
+    KTaskOsAssignAfterIrq(NONE);
+    /* leave interrupt */
+    level = DisableLocalInterrupt();
+    isrManager.done->decCounter();
+    EnableLocalInterrupt(level);
+    FREE_INT_SP();
+}

Ubiquitous/XiZi/arch/risc-v/k210/interrupt.c

@@ -115,7 +115,7 @@ void InitHwinterrupt(void)
     SET_CSR(mie, MIP_MEIP);
 }
 
-void InitHwScondaryInterrupt(void)
+void InitHwSecondaryInterrupt(void)
 {
     int idx;
     int cpuid;

Ubiquitous/XiZi/arch/risc-v/k210/smp_support.c

@@ -65,14 +65,14 @@ void StartupSecondaryCpu(void)
     cpu2_boot_flag = 0x2018050420191010;
 }
 
-extern void InitHwScondaryInterrupt(void);
+extern void InitHwSecondaryInterrupt(void);
 extern int InitHwTick(void);
 extern int EnableHwclintIpi(void);
 
 void SecondaryCpuCStart(void)
 {
     HwLockSpinlock(&AssignSpinLock);
-    InitHwScondaryInterrupt();
+    InitHwSecondaryInterrupt();
 
     InitHwTick();
 

Ubiquitous/XiZi/arch/risc-v/shared/prepare_rhwstack.c

@@ -55,6 +55,42 @@ struct StackRegisterContext
     x_ubase t4;     
     x_ubase t5;         
     x_ubase t6;
+
+/* float register */
+#ifdef ARCH_RISCV_FPU
+    x_ubase f0;      /* f0  */
+    x_ubase f1;      /* f1  */
+    x_ubase f2;      /* f2  */
+    x_ubase f3;      /* f3  */
+    x_ubase f4;      /* f4  */
+    x_ubase f5;      /* f5  */
+    x_ubase f6;      /* f6  */
+    x_ubase f7;      /* f7  */
+    x_ubase f8;      /* f8  */
+    x_ubase f9;      /* f9  */
+    x_ubase f10;     /* f10 */
+    x_ubase f11;     /* f11 */
+    x_ubase f12;     /* f12 */
+    x_ubase f13;     /* f13 */
+    x_ubase f14;     /* f14 */
+    x_ubase f15;     /* f15 */
+    x_ubase f16;     /* f16 */
+    x_ubase f17;     /* f17 */
+    x_ubase f18;     /* f18 */
+    x_ubase f19;     /* f19 */
+    x_ubase f20;     /* f20 */
+    x_ubase f21;     /* f21 */
+    x_ubase f22;     /* f22 */
+    x_ubase f23;     /* f23 */
+    x_ubase f24;     /* f24 */
+    x_ubase f25;     /* f25 */
+    x_ubase f26;     /* f26 */
+    x_ubase f27;     /* f27 */
+    x_ubase f28;     /* f28 */
+    x_ubase f29;     /* f29 */
+    x_ubase f30;     /* f30 */
+    x_ubase f31;     /* f31 */
+#endif
 };
 
 uint8 KTaskStackSetup(struct TaskDescriptor *task)

Ubiquitous/XiZi/arch/risc-v/shared/riscv64_switch.c

@@ -59,11 +59,86 @@ void __attribute__((naked)) SwitchKTaskContextExit()
     asm volatile (LoadDS " t5,  30 * " RegLengthS "(sp)");
     asm volatile (LoadDS " t6,  31 * " RegLengthS "(sp)");
     asm volatile ("addi sp,  sp, 32 * " RegLengthS "");
+
+#ifdef ARCH_RISCV_FPU
+    asm volatile (FLOAD  " f0, 0 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f1, 1 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f2, 2 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f3, 3 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f4, 4 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f5, 5 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f6, 6 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f7, 7 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f8, 8 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f9, 9 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f10, 10 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f11, 11 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f12, 12 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f13, 13 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f14, 14 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f15, 15 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f16, 16 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f17, 17 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f18, 18 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f19, 19 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f20, 20 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f21, 21 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f22, 22 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f23, 23 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f24, 24 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f25, 25 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f26, 26 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f27, 27 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f28, 28 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f29, 29 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f30, 30 *" FREGBYTES "(sp)");
+    asm volatile (FLOAD  " f31, 31 *" FREGBYTES "(sp)");
+    asm volatile ("addi sp, sp, 32 *" FREGBYTES);
+#endif
+
     asm volatile ("mret");
 }
 
 void __attribute__((naked)) SaveMpie()
 {
+    
+#ifdef ARCH_RISCV_FPV
+    asm volatile ("addi sp, sp, -32 *" FREGBYTES);
+
+    asm volatile (FSTORE  " f0, 0 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f1, 1 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f2, 2 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f3, 3 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f4, 4 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f5, 5 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f6, 6 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f7, 7 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f8, 8 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f9, 9 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f10, 10 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f11, 11 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f12, 12 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f13, 13 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f14, 14 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f15, 15 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f16, 16 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f17, 17 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f18, 18 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f19, 19 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f20, 20 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f21, 21 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f22, 22 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f23, 23 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f24, 24 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f25, 25 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f26, 26 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f27, 27 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f28, 28 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f29, 29 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f30, 30 *" FREGBYTES "(sp)");
+    asm volatile (FSTORE  " f31, 31 *" FREGBYTES "(sp)");
+#endif
+
     asm volatile (StoreDS " a0,   2 * " RegLengthS "(sp)");
     asm volatile (StoreDS " tp,   4 * " RegLengthS "(sp)");
     asm volatile (StoreDS " t0,   5 * " RegLengthS "(sp)");

Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/i2c/connect_i2c.c

@@ -42,7 +42,7 @@ Modification:
 
 static I2cBusParam i2c_bus_param =
 {
-    I2C_SDA_FUNC_GPIO,
+    _FUNC_GPIO,
     I2C_SCL_FUNC_GPIO,
 };
 static BusType pin;

Ubiquitous/XiZi/board/ch32v307vct6/Kconfig

@@ -0,0 +1,31 @@
+mainmenu "XiZi Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CH32V307VCT6
+    bool
+    select ARCH_RISCV
+    default y  
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "ch32v307vct6 feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+endmenu
+
+
+menu "Hardware feature"
+    source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"
+
+

Ubiquitous/XiZi/board/ch32v307vct6/Makefile

@@ -0,0 +1,6 @@
+SRC_FILES := board.c
+
+SRC_DIR := third_party_driver 
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/ch32v307vct6/README.md

@@ -0,0 +1,58 @@
+# CH32V307VCT6-board README
+
+## 1. 简介
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| ch32v307 |
+|CPU| 单核RV32GC |
+|主频| 144MHz |
+|片内SRAM| 可配最大128KB |
+| 外设 |  |
+| | GPIO、UART|
+
+## 2. 编译说明
+
+编译环境：Ubuntu18.04
+
+编译工具链：riscv-none-embed-gcc ( xPack GNU RISC-V Embedded GCC)  
+**xPack RISC-V Embedded GCC** 工具链可以使用[xpm](https://www.npmjs.com/package/xpm)工具进行安装:
+
+```console
+$ xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@8.2.0-3.1.1
+```
+
+编译步骤：
+
+>1.将编译工具链的路径添加到board/ch32v307vct6/config.mk文件当中，例如将xpack-riscv-none-elf-gcc解压到/opt/下时添加：
+```
+export CROSS_COMPILE ?=/opt/riscv-embedded-gcc/bin/riscv-none-embed-
+```
+>2.在代码根目录下执行以下命令，生成配置文件
+```
+cd ./Ubiquitous/XiZi
+make BOARD=ch32v307vct6 distclean
+make BOARD=ch32v307vct6 menuconfig
+```
+>3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出
+>4.继续执行以下命令，进行编译
+```
+make BOARD=ch32v307vct6
+```
+>5.如果编译正确无误，会产生XiZi-ch32v307vct6.elf、XiZi-ch32v307vct6.bin文件。其中XiZi-ch32v307vct6.bin需要烧写到设备中进行运行。
+>注：最后可以执行以下命令，清除配置文件和编译生成的文件
+```
+make BOARD=ch32v307vct6 distclean
+```
+
+## 3. 烧写及执行
+
+开发板可使用数据线通过USB接口与电脑连接，将开发板的Boot0接口通电（连接VCC）后按动ReSet按钮，即可使用烧录工具[WCHISPTool](https://www.wch.cn/download/WCHISPTool_Setup_exe.html)进行烧录。![board_settng](img/board.jpg)烧录工具的配置如下图所示。![WCHISPTool配置](img/WCHIPSTool_setting.PNG)
+
+烧录完成后可通过串口连接PC电脑与开发版，TX(PA9)接串口RX、RX(PA10)接串口TX。![](img/serial.jpg)
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，将开发板BOOT引脚与VCC引脚断开后重新上电或将RESET引脚短接一下，将会在串口终端上看到信息打印输出。
+
+![terminal](img/terminal.PNG)

Ubiquitous/XiZi/board/ch32v307vct6/board.c

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-07-24     Tanek        the first version
+ * 2018-11-12     Ernest Chen  modify copyright
+ */
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support ch32v307 init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2022-08-08
+*/
+#include <board.h>
+#include <xizi.h>
+#include <stdint.h>
+#include <device.h>
+#include "connect_uart.h"
+#include "xsconfig.h"
+#include "ch32v30x.h"
+#include "core_riscv.h"
+ // #include <system_ch32v30x.h>
+
+ // core clock.
+extern uint32_t SystemCoreClock;
+
+static uint32_t _SysTick_Config(uint32_t ticks)
+{
+    NVIC_SetPriority(SysTicK_IRQn,0xf0);
+    NVIC_SetPriority(Software_IRQn,0xf0);
+    NVIC_EnableIRQ(SysTicK_IRQn);
+    NVIC_EnableIRQ(Software_IRQn);
+    SysTick->CTLR=0;
+    SysTick->SR=0;
+    SysTick->CNT=0;
+    SysTick->CMP=ticks-1;
+    SysTick->CTLR=0xF;
+    return 0;
+}
+
+/**
+ * This function will initial your board.
+ */
+void InitBoardHardware()
+{
+    USART_Printf_Init(115200);
+    /* System Tick Configuration */
+    _SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
+    /* initialize memory system */
+    InitBoardMemory(MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+    InitHwUart();
+    InstallConsole("uart1", "uart1_drv", "uart1_dev1");
+
+    KPrintf("consle init completed.\n");
+    KPrintf("board initialization......\n");
+    // KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, gd32vf103_SRAM_SIZE);
+    /* initialize memory system */
+	
+    KPrintf("board init done.\n");
+	KPrintf("start okernel...\n");
+}
+

Ubiquitous/XiZi/board/ch32v307vct6/board.h

@@ -0,0 +1,49 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define ch32v307 init configure and start-up function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-09-02
+*/
+
+/*************************************************
+File name: board.h
+Description: define ch32v307 vct6 init configure and start-up function
+Others: 
+History: 
+1. Date: 2022-08-08
+Author: AIIT XUOS Lab
+Modification: 
+1. define ch32v307 vct6 InitBoardHardware
+*************************************************/
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "ch32v30x.h"
+#include <xsconfig.h>
+
+#define CH32V30X_PIN_NUMBERS   100
+/* board configuration */
+#define SRAM_SIZE  64
+#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
+
+extern int _ebss;
+extern int __stack_size;
+#define MEMORY_START_ADDRESS    ((void *)&_ebss)
+#define MEMORY_END_ADDRESS      (SRAM_END-__stack_size)
+
+void InitBoardHardware(void);
+
+#endif /* __BOARD_H__ */

Ubiquitous/XiZi/board/ch32v307vct6/config.mk

@@ -0,0 +1,22 @@
+
+export CFLAGS :=  -march=rv32imac -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -g
+export AFLAGS :=  -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb
+export LFLAGS :=  -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi-ch32v307vct6.map,-cref,-u,_start -T $(BSP_ROOT)/link.ld
+
+# export CFLAGS :=  -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -g -std=gnu99
+# export AFLAGS :=  -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb
+# export LFLAGS :=  -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -g -T $(BSP_ROOT)/link.ld -nostartfiles -Xlinker --gc-sections -Wl,-Map,"XiZi-ch32v307vct6.map" --specs=nano.specs --specs=nosys.specs
+
+export APPLFLAGS :=  -nostartfiles -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+export CXXFLAGS :=  -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common # -std=gnu99
+
+export CROSS_COMPILE ?=/opt/riscv-embedded-gcc/bin/riscv-none-embed-
+
+export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO
+
+export ARCH = risc-v
+export MCU =  GH32V307
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/link.ld

@@ -0,0 +1,194 @@
+ENTRY( _start)
+
+__stack_size = 3072;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.gnu.linkonce.t.*)
+
+	/* section information for  shell */
+        . = ALIGN(4);
+		_shell_command_start = .;
+		KEEP (*(shellCommand))
+		_shell_command_end = .;
+		. = ALIGN(4);
+
+		PROVIDE(__ctors_start__ = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE(__ctors_end__ = .);
+
+		. = ALIGN(4);
+		__isrtbl_idx_start = .;
+		KEEP(*(.isrtbl.idx))
+		__isrtbl_start = .;
+		KEEP(*(.isrtbl))
+		__isrtbl_end = .;
+		. = ALIGN(4);
+
+		PROVIDE(g_service_table_start = ABSOLUTE(.));
+		KEEP(*(.g_service_table))
+		PROVIDE(g_service_table_end = ABSOLUTE(.));
+
+		*(.gnu.linkonce.t.*)
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );    
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM 
+
+}
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Kconfig

@@ -0,0 +1,18 @@
+
+menuconfig BSP_USING_UART
+    bool "Using UART device"
+    default y
+    select RESOURCES_SERIAL
+    if BSP_USING_UART
+        source "$BSP_DIR/third_party_driver/uart/Kconfig"
+    endif
+
+menuconfig BSP_USING_GPIO
+    bool "Using GPIO"
+    default y
+    select RESOURCES_SERIAL
+    if BSP_USING_GPIO
+        source "$BSP_DIR/third_party_driver/gpio/Kconfig"
+    endif
+ 
+    

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Makefile

@@ -0,0 +1,12 @@
+SRC_FILES := 
+SRC_DIR := Peripheral
+
+ifeq ($(CONFIG_BSP_USING_UART),y)
+  SRC_DIR += uart
+endif
+
+ifeq ($(CONFIG_BSP_USING_GPIO),y)
+  SRC_DIR += gpio
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/Makefile

@@ -0,0 +1,3 @@
+SRC_DIR := src
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_adc.h

@@ -0,0 +1,228 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_adc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      ADC firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_ADC_H
+#define __CH32V30x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+/* ADC Init structure definition */
+typedef struct
+{
+  uint32_t ADC_Mode;                      /* Configures the ADC to operate in independent or
+                                             dual mode. 
+                                             This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /* Specifies whether the conversion is performed in
+                                             Scan (multichannels) or Single (one channel) mode.
+                                             This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
+                                             Continuous or Single mode.
+                                             This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /* Defines the external trigger used to start the analog
+                                             to digital conversion of regular channels. This parameter
+                                             can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /* Specifies whether the ADC data alignment is left or right.
+                                             This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /* Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+
+  uint32_t  ADC_OutputBuffer;             /* Specifies whether the ADC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref ADC_OutputBuffer */
+
+  uint32_t ADC_Pga;                       /* Specifies the PGA gain multiple.
+                                               This parameter can be a value of @ref ADC_Pga */
+}ADC_InitTypeDef;
+
+/* ADC_mode */
+#define ADC_Mode_Independent                        ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                     ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig                ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl             ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl             ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                        ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                          ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                         ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                         ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                          ((uint32_t)0x00090000)
+
+/* ADC_external_trigger_sources_for_regular_channels_conversion */
+#define ADC_ExternalTrigConv_T1_CC1                 ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigConv_T1_CC2                 ((uint32_t)0x00020000) 
+#define ADC_ExternalTrigConv_T2_CC2                 ((uint32_t)0x00060000) 
+#define ADC_ExternalTrigConv_T3_TRGO                ((uint32_t)0x00080000) 
+#define ADC_ExternalTrigConv_T4_CC4                 ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO     ((uint32_t)0x000C0000) 
+
+#define ADC_ExternalTrigConv_T1_CC3                 ((uint32_t)0x00040000) 
+#define ADC_ExternalTrigConv_None                   ((uint32_t)0x000E0000) 
+
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) 
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) 
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000)
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) 
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) 
+
+
+/* ADC_data_align */
+#define ADC_DataAlign_Right                         ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                          ((uint32_t)0x00000800)
+
+/* ADC_channels */
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+/*ADC_output_buffer*/
+#define ADC_OutputBuffer_Enable                     ((uint32_t)0x04000000)
+#define ADC_OutputBuffer_Disable                    ((uint32_t)0x00000000)
+
+/*ADC_pga*/
+#define ADC_Pga_1                                   ((uint32_t)0x00000000)
+#define ADC_Pga_4                                   ((uint32_t)0x08000000)
+#define ADC_Pga_16                                  ((uint32_t)0x10000000)
+#define ADC_Pga_64                                  ((uint32_t)0x18000000)
+
+/* ADC_sampling_time */
+#define ADC_SampleTime_1Cycles5                     ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                     ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                    ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                    ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                    ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                    ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                    ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                   ((uint8_t)0x07)
+
+/* ADC_external_trigger_sources_for_injected_channels_conversion */
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) 
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) 
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) 
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) 
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) 
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) 
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) 
+
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) 
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) 
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) 
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000)
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) 
+
+
+/* ADC_injected_channel_selection */
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+
+/* ADC_analog_watchdog_selection */
+#define ADC_AnalogWatchdog_SingleRegEnable          ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable        ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable   ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable             ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable           ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable     ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                     ((uint32_t)0x00000000)
+
+/* ADC_interrupts_definition */
+#define ADC_IT_EOC                                  ((uint16_t)0x0220)
+#define ADC_IT_AWD                                  ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                 ((uint16_t)0x0480)
+
+/* ADC_flags_definition */
+#define ADC_FLAG_AWD                                ((uint8_t)0x01)
+#define ADC_FLAG_EOC                                ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                               ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                              ((uint8_t)0x08)
+#define ADC_FLAG_STRT                               ((uint8_t)0x10)
+
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+s32 TempSensor_Volt_To_Temper(s32 Value);
+void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+int16_t Get_CalibrationValue(ADC_TypeDef* ADCx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_bkp.h

@@ -0,0 +1,97 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_bkp.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      BKP firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_BKP_H
+#define __CH32V30x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* Tamper_Pin_active_level */
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+
+/* RTC_output_source_to_output_on_the_Tamper_pin */
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+	 
+/* Data_Backup_Register */
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_can.h

@@ -0,0 +1,366 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_can.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      CAN firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_CAN_H
+#define __CH32V30x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* CAN init structure definition */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /* Specifies the length of a time quantum. 
+                               It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /* Specifies the CAN operating mode.
+                               This parameter can be a value of 
+                              @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /* Specifies the maximum number of time quanta 
+                               the CAN hardware is allowed to lengthen or 
+                               shorten a bit to perform resynchronization.
+                               This parameter can be a value of 
+                               @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /* Specifies the number of time quanta in Bit 
+                               Segment 1. This parameter can be a value of 
+                               @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /* Specifies the number of time quanta in Bit 
+                               Segment 2.
+                               This parameter can be a value of 
+                               @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /* Enable or disable the time triggered 
+                               communication mode. This parameter can be set 
+                               either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /* Enable or disable the automatic bus-off 
+                                management. This parameter can be set either 
+                                to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /* Enable or disable the automatic wake-up mode. 
+                                This parameter can be set either to ENABLE or 
+                                DISABLE. */
+
+  FunctionalState CAN_NART;  /* Enable or disable the no-automatic 
+                                retransmission mode. This parameter can be 
+                                set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /* Enable or disable the Receive FIFO Locked mode.
+                                This parameter can be set either to ENABLE 
+                                or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /* Enable or disable the transmit FIFO priority.
+                                This parameter can be set either to ENABLE 
+                                or DISABLE. */
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /* Specifies the filter identification number (MSBs for a 32-bit
+                                            configuration, first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /* Specifies the filter identification number (LSBs for a 32-bit
+                                            configuration, second one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /* Specifies the filter mask number or identification number,
+                                            according to the mode (MSBs for a 32-bit configuration,
+                                            first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /* Specifies the filter mask number or identification number,
+                                            according to the mode (LSBs for a 32-bit configuration,
+                                            second one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                            This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /* Specifies the filter mode to be initialized.
+                                            This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /* Specifies the filter scale.
+                                            This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
+                                            This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+  uint32_t StdId;  /* Specifies the standard identifier.
+                      This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /* Specifies the extended identifier.
+                      This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /* Specifies the type of identifier for the message that 
+                      will be transmitted. This parameter can be a value 
+                      of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /* Specifies the type of frame for the message that will 
+                      be transmitted. This parameter can be a value of 
+                      @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /* Specifies the length of the frame that will be 
+                      transmitted. This parameter can be a value between 
+                      0 to 8 */
+
+  uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 
+                       to 0xFF. */
+} CanTxMsg;
+
+/* CAN Rx message structure definition  */
+typedef struct
+{
+  uint32_t StdId;  /* Specifies the standard identifier.
+                      This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /* Specifies the extended identifier.
+                      This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /* Specifies the type of identifier for the message that 
+                      will be received. This parameter can be a value of 
+                      @ref CAN_identifier_type */
+
+  uint8_t RTR;     /* Specifies the type of frame for the received message.
+                      This parameter can be a value of 
+                      @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /* Specifies the length of the frame that will be received.
+                      This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to 
+                      0xFF. */
+
+  uint8_t FMI;     /* Specifies the index of the filter the message stored in 
+                      the mailbox passes through. This parameter can be a 
+                      value between 0 to 0xFF */
+} CanRxMsg;
+
+/* CAN_sleep_constants */
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /* CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /* CAN initialization OK */
+
+/* CAN_Mode */
+#define CAN_Mode_Normal                    ((uint8_t)0x00)  /* normal mode */
+#define CAN_Mode_LoopBack                  ((uint8_t)0x01)  /* loopback mode */
+#define CAN_Mode_Silent                    ((uint8_t)0x02)  /* silent mode */
+#define CAN_Mode_Silent_LoopBack           ((uint8_t)0x03)  /* loopback combined with silent mode */
+
+/* CAN_Operating_Mode */
+#define CAN_OperatingMode_Initialization   ((uint8_t)0x00) /* Initialization mode */
+#define CAN_OperatingMode_Normal           ((uint8_t)0x01) /* Normal mode */
+#define CAN_OperatingMode_Sleep            ((uint8_t)0x02) /* sleep mode */
+
+/* CAN_Mode_Status */
+#define CAN_ModeStatus_Failed              ((uint8_t)0x00)                /* CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success             ((uint8_t)!CAN_ModeStatus_Failed)   /* CAN entering the specific mode Succeed */
+
+/* CAN_synchronisation_jump_width */
+#define CAN_SJW_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_SJW_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_SJW_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_SJW_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_1 */
+#define CAN_BS1_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_BS1_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_BS1_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_BS1_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+#define CAN_BS1_5tq                        ((uint8_t)0x04)  /* 5 time quantum */
+#define CAN_BS1_6tq                        ((uint8_t)0x05)  /* 6 time quantum */
+#define CAN_BS1_7tq                        ((uint8_t)0x06)  /* 7 time quantum */
+#define CAN_BS1_8tq                        ((uint8_t)0x07)  /* 8 time quantum */
+#define CAN_BS1_9tq                        ((uint8_t)0x08)  /* 9 time quantum */
+#define CAN_BS1_10tq                       ((uint8_t)0x09)  /* 10 time quantum */
+#define CAN_BS1_11tq                       ((uint8_t)0x0A)  /* 11 time quantum */
+#define CAN_BS1_12tq                       ((uint8_t)0x0B)  /* 12 time quantum */
+#define CAN_BS1_13tq                       ((uint8_t)0x0C)  /* 13 time quantum */
+#define CAN_BS1_14tq                       ((uint8_t)0x0D)  /* 14 time quantum */
+#define CAN_BS1_15tq                       ((uint8_t)0x0E)  /* 15 time quantum */
+#define CAN_BS1_16tq                       ((uint8_t)0x0F)  /* 16 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_2 */
+#define CAN_BS2_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_BS2_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_BS2_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_BS2_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+#define CAN_BS2_5tq                        ((uint8_t)0x04)  /* 5 time quantum */
+#define CAN_BS2_6tq                        ((uint8_t)0x05)  /* 6 time quantum */
+#define CAN_BS2_7tq                        ((uint8_t)0x06)  /* 7 time quantum */
+#define CAN_BS2_8tq                        ((uint8_t)0x07)  /* 8 time quantum */
+
+/* CAN_filter_mode */
+#define CAN_FilterMode_IdMask              ((uint8_t)0x00)  /* identifier/mask mode */
+#define CAN_FilterMode_IdList              ((uint8_t)0x01)  /* identifier list mode */
+
+/* CAN_filter_scale */
+#define CAN_FilterScale_16bit              ((uint8_t)0x00) /* Two 16-bit filters */
+#define CAN_FilterScale_32bit              ((uint8_t)0x01) /* One 32-bit filter */
+
+/* CAN_filter_FIFO */
+#define CAN_Filter_FIFO0                   ((uint8_t)0x00)  /* Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1                   ((uint8_t)0x01)  /* Filter FIFO 1 assignment for filter x */
+
+/* CAN_identifier_type */
+#define CAN_Id_Standard                    ((uint32_t)0x00000000)  /* Standard Id */
+#define CAN_Id_Extended                    ((uint32_t)0x00000004)  /* Extended Id */
+
+/* CAN_remote_transmission_request */
+#define CAN_RTR_Data                       ((uint32_t)0x00000000)  /* Data frame */
+#define CAN_RTR_Remote                     ((uint32_t)0x00000002)  /* Remote frame */
+
+/* CAN_transmit_constants */
+#define CAN_TxStatus_Failed                ((uint8_t)0x00)/* CAN transmission failed */
+#define CAN_TxStatus_Ok                    ((uint8_t)0x01) /* CAN transmission succeeded */
+#define CAN_TxStatus_Pending               ((uint8_t)0x02) /* CAN transmission pending */
+#define CAN_TxStatus_NoMailBox             ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN_receive_FIFO_number_constants */
+#define CAN_FIFO0                          ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
+#define CAN_FIFO1                          ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
+
+/* CAN_sleep_constants */
+#define CAN_Sleep_Failed                   ((uint8_t)0x00) /* CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok                       ((uint8_t)0x01) /* CAN entered the sleep mode */
+
+/* CAN_wake_up_constants */
+#define CAN_WakeUp_Failed                  ((uint8_t)0x00) /* CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok                      ((uint8_t)0x01) /* CAN leaved the sleep mode */
+ 
+/* CAN_Error_Code_constants */                                                               
+#define CAN_ErrorCode_NoErr                ((uint8_t)0x00) /* No Error */ 
+#define	CAN_ErrorCode_StuffErr             ((uint8_t)0x10) /* Stuff Error */ 
+#define	CAN_ErrorCode_FormErr              ((uint8_t)0x20) /* Form Error */ 
+#define	CAN_ErrorCode_ACKErr               ((uint8_t)0x30) /* Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr      ((uint8_t)0x40) /* Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr       ((uint8_t)0x50) /* Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr               ((uint8_t)0x60) /* CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr       ((uint8_t)0x70) /* Software Set Error */ 
+
+
+/* CAN_flags */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0                     ((uint32_t)0x38000001) /* Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1                     ((uint32_t)0x38000100) /* Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2                     ((uint32_t)0x38010000) /* Request MailBox2 Flag */
+
+/* Receive Flags */ 
+#define CAN_FLAG_FMP0                      ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0                       ((uint32_t)0x32000008) /* FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0                      ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1                      ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1                       ((uint32_t)0x34000008) /* FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1                      ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU                       ((uint32_t)0x31000008) /* Wake up Flag */
+#define CAN_FLAG_SLAK                      ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
+
+/* Error Flags */
+#define CAN_FLAG_EWG                       ((uint32_t)0x10F00001) /* Error Warning Flag   */
+#define CAN_FLAG_EPV                       ((uint32_t)0x10F00002) /* Error Passive Flag   */
+#define CAN_FLAG_BOF                       ((uint32_t)0x10F00004) /* Bus-Off Flag         */
+#define CAN_FLAG_LEC                       ((uint32_t)0x30F00070) /* Last error code Flag */
+
+
+/* CAN_interrupts */
+#define CAN_IT_TME                         ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                        ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                         ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                        ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                        ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                         ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                        ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                         ((uint32_t)0x00010000) /* Wake-up Interrupt*/
+#define CAN_IT_SLK                         ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                         ((uint32_t)0x00000100) /* Error warning Interrupt*/
+#define CAN_IT_EPV                         ((uint32_t)0x00000200) /* Error passive Interrupt*/
+#define CAN_IT_BOF                         ((uint32_t)0x00000400) /* Bus-off Interrupt*/
+#define CAN_IT_LEC                         ((uint32_t)0x00000800) /* Last error code Interrupt*/
+#define CAN_IT_ERR                         ((uint32_t)0x00008000) /* Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0    CAN_IT_TME
+#define CAN_IT_RQCP1    CAN_IT_TME
+#define CAN_IT_RQCP2    CAN_IT_TME
+
+/* CAN_Legacy */
+#define CANINITFAILED               CAN_InitStatus_Failed
+#define CANINITOK                   CAN_InitStatus_Success
+#define CAN_FilterFIFO0             CAN_Filter_FIFO0
+#define CAN_FilterFIFO1             CAN_Filter_FIFO1
+#define CAN_ID_STD                  CAN_Id_Standard           
+#define CAN_ID_EXT                  CAN_Id_Extended
+#define CAN_RTR_DATA                CAN_RTR_Data         
+#define CAN_RTR_REMOTE              CAN_RTR_Remote
+#define CANTXFAILE                  CAN_TxStatus_Failed
+#define CANTXOK                     CAN_TxStatus_Ok
+#define CANTXPENDING                CAN_TxStatus_Pending
+#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED              CAN_Sleep_Failed
+#define CANSLEEPOK                  CAN_Sleep_Ok
+#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
+#define CANWAKEUPOK                 CAN_WakeUp_Ok        
+
+
+void CAN_DeInit(CAN_TypeDef* CANx); 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_crc.h

@@ -0,0 +1,37 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_crc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      CRC firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_CRC_H
+#define __CH32V30x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+	 
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_dac.h

@@ -0,0 +1,120 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dac.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DAC firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_DAC_H
+#define __CH32V30x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* DAC Init structure definition */
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /* Specifies the external trigger for the selected DAC channel.
+                                                This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /* Specifies whether DAC channel noise waves or triangle waves
+                                                are generated, or whether no wave is generated.
+                                                This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or
+                                                the maximum amplitude triangle generation for the DAC channel. 
+                                                This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /* Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+
+/* DAC_trigger_selection */
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                     has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                     only in High-density devices*/
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */
+
+/* DAC_wave_generation */
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+
+
+/* DAC_lfsrunmask_triangleamplitude */
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */
+
+/* DAC_output_buffer */
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+
+/* DAC_Channel_selection */
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+																 
+/* DAC_data_alignment */
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+
+/* DAC_wave_generation */
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_dbgmcu.h

@@ -0,0 +1,35 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dbgmcu.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DBGMCU firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_DBGMCU_H
+#define __CH32V30x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_dma.h

@@ -0,0 +1,268 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dma.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DMA firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/  
+#ifndef __CH32V30x_DMA_H
+#define __CH32V30x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+ 
+/* DMA Init structure definition */
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
+
+  uint32_t DMA_MemoryBaseAddr;     /* Specifies the memory base address for DMAy Channelx. */
+
+  uint32_t DMA_DIR;                /* Specifies if the peripheral is the source or destination.
+                                      This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /* Specifies the buffer size, in data unit, of the specified Channel. 
+                                      The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                      or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /* Specifies whether the Peripheral address register is incremented or not.
+                                      This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /* Specifies whether the memory address register is incremented or not.
+                                      This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /* Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /* Specifies the operation mode of the DMAy Channelx.
+                                      This parameter can be a value of @ref DMA_circular_normal_mode.
+                                      @note: The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /* Specifies the software priority for the DMAy Channelx.
+                                      This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_M2M;                /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                      This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* DMA_data_transfer_direction */
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_incremented_mode */
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+											
+/* DMA_memory_incremented_mode */
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+										
+/* DMA_peripheral_data_size */
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+
+/* DMA_memory_data_size */
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+
+/* DMA_circular_normal_mode */
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+
+/* DMA_priority_level */
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+/* DMA_memory_to_memory */
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+
+/* DMA_interrupts_definition */
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+#define DMA2_IT_GL6                        ((uint32_t)0x10100000)
+#define DMA2_IT_TC6                        ((uint32_t)0x10200000)
+#define DMA2_IT_HT6                        ((uint32_t)0x10400000)
+#define DMA2_IT_TE6                        ((uint32_t)0x10800000)
+#define DMA2_IT_GL7                        ((uint32_t)0x11000000)
+#define DMA2_IT_TC7                        ((uint32_t)0x12000000)
+#define DMA2_IT_HT7                        ((uint32_t)0x14000000)
+#define DMA2_IT_TE7                        ((uint32_t)0x18000000)
+
+#define DMA2_IT_GL8                        ((uint32_t)0x20000001)
+#define DMA2_IT_TC8                        ((uint32_t)0x20000002)
+#define DMA2_IT_HT8                        ((uint32_t)0x20000004)
+#define DMA2_IT_TE8                        ((uint32_t)0x20000008)
+#define DMA2_IT_GL9                        ((uint32_t)0x20000010)
+#define DMA2_IT_TC9                        ((uint32_t)0x20000020)
+#define DMA2_IT_HT9                        ((uint32_t)0x20000040)
+#define DMA2_IT_TE9                        ((uint32_t)0x20000080)
+#define DMA2_IT_GL10                       ((uint32_t)0x20000100)
+#define DMA2_IT_TC10                       ((uint32_t)0x20000200)
+#define DMA2_IT_HT10                       ((uint32_t)0x20000400)
+#define DMA2_IT_TE10                       ((uint32_t)0x20000800)
+#define DMA2_IT_GL11                       ((uint32_t)0x20001000)
+#define DMA2_IT_TC11                       ((uint32_t)0x20002000)
+#define DMA2_IT_HT11                       ((uint32_t)0x20004000)
+#define DMA2_IT_TE11                       ((uint32_t)0x20008000)
+
+/* DMA_flags_definition */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+#define DMA2_FLAG_GL6                      ((uint32_t)0x10100000)
+#define DMA2_FLAG_TC6                      ((uint32_t)0x10200000)
+#define DMA2_FLAG_HT6                      ((uint32_t)0x10400000)
+#define DMA2_FLAG_TE6                      ((uint32_t)0x10800000)
+#define DMA2_FLAG_GL7                      ((uint32_t)0x11000000)
+#define DMA2_FLAG_TC7                      ((uint32_t)0x12000000)
+#define DMA2_FLAG_HT7                      ((uint32_t)0x14000000)
+#define DMA2_FLAG_TE7                      ((uint32_t)0x18000000)
+
+#define DMA2_FLAG_GL8                      ((uint32_t)0x20000001)
+#define DMA2_FLAG_TC8                      ((uint32_t)0x20000002)
+#define DMA2_FLAG_HT8                      ((uint32_t)0x20000004)
+#define DMA2_FLAG_TE8                      ((uint32_t)0x20000008)
+#define DMA2_FLAG_GL9                      ((uint32_t)0x20000010)
+#define DMA2_FLAG_TC9                      ((uint32_t)0x20000020)
+#define DMA2_FLAG_HT9                      ((uint32_t)0x20000040)
+#define DMA2_FLAG_TE9                      ((uint32_t)0x20000080)
+#define DMA2_FLAG_GL10                     ((uint32_t)0x20000100)
+#define DMA2_FLAG_TC10                     ((uint32_t)0x20000200)
+#define DMA2_FLAG_HT10                     ((uint32_t)0x20000400)
+#define DMA2_FLAG_TE10                     ((uint32_t)0x20000800)
+#define DMA2_FLAG_GL11                     ((uint32_t)0x20001000)
+#define DMA2_FLAG_TC11                     ((uint32_t)0x20002000)
+#define DMA2_FLAG_HT11                     ((uint32_t)0x20004000)
+#define DMA2_FLAG_TE11                     ((uint32_t)0x20008000)
+
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_dvp.h

@@ -0,0 +1,67 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dvp.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DVP firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_DVP_H
+#define __CH32V30x_DVP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* DVP Data Mode */
+typedef enum
+{
+ Video_Mode = 0,
+ JPEG_Mode,
+}DVP_Data_ModeTypeDef;
+
+
+/* DVP DMA */
+typedef enum
+{
+ DVP_DMA_Disable = 0,
+ DVP_DMA_Enable,
+}DVP_DMATypeDef;
+
+/* DVP FLAG and FIFO Reset */
+typedef enum
+{
+ DVP_FLAG_FIFO_RESET_Disable = 0,
+ DVP_FLAG_FIFO_RESET_Enable,
+}DVP_FLAG_FIFO_RESETTypeDef;
+
+/* DVP RX Reset */
+typedef enum
+{
+ DVP_RX_RESET_Disable = 0,
+ DVP_RX_RESET_Enable,
+}DVP_RX_RESETTypeDef;
+
+
+
+void DVP_INTCfg( uint8_t s,  uint8_t i );
+void DVP_Mode( uint8_t s,  DVP_Data_ModeTypeDef i);
+void DVP_Cfg( DVP_DMATypeDef s,  DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_exti.h

@@ -0,0 +1,90 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_exti.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      EXTI firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_EXTI_H
+#define __CH32V30x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* EXTI mode enumeration */
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+/* EXTI Trigger enumeration */
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+/* EXTI Init Structure definition */
+typedef struct
+{
+  uint32_t EXTI_Line;               /* Specifies the EXTI lines to be enabled or disabled.
+                                       This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /* Specifies the mode for the EXTI lines.
+                                       This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
+                                       This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /* Specifies the new state of the selected EXTI lines.
+                                       This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+
+/* EXTI_Lines */
+#define EXTI_Line0       ((uint32_t)0x00001)  /* External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /* External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /* External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /* External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /* External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /* External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /* External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /* External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /* External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /* External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /* External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /* External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /* External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /* External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /* External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /* External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /* External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /* External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /* External interrupt line 18 Connected to the USBD/USBFS OTG
+                                                 Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)  /* External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20      ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_flash.h

@@ -0,0 +1,143 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_flash.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the FLASH  
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_FLASH_H
+#define __CH32V30x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* FLASH Status */
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+
+/* Write Protect */
+#define FLASH_WRProt_Sectors0        ((uint32_t)0x00000001) /* Write protection of setor 0  */
+#define FLASH_WRProt_Sectors1        ((uint32_t)0x00000002) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors2        ((uint32_t)0x00000004) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors3        ((uint32_t)0x00000008) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors4        ((uint32_t)0x00000010) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors5        ((uint32_t)0x00000020) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors6        ((uint32_t)0x00000040) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors7        ((uint32_t)0x00000080) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors8        ((uint32_t)0x00000100) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors9        ((uint32_t)0x00000200) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors10       ((uint32_t)0x00000400) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors11       ((uint32_t)0x00000800) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors12       ((uint32_t)0x00001000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors13       ((uint32_t)0x00002000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors14       ((uint32_t)0x00004000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors15       ((uint32_t)0x00008000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors16       ((uint32_t)0x00010000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors17       ((uint32_t)0x00020000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors18       ((uint32_t)0x00040000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors19       ((uint32_t)0x00080000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors20       ((uint32_t)0x00100000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors21       ((uint32_t)0x00200000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors22       ((uint32_t)0x00400000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors23       ((uint32_t)0x00800000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors24       ((uint32_t)0x01000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors25       ((uint32_t)0x02000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors26       ((uint32_t)0x04000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors27       ((uint32_t)0x08000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors28       ((uint32_t)0x10000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors29       ((uint32_t)0x20000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors30       ((uint32_t)0x40000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors31to127  ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllSectors      ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
+
+/* Option_Bytes_IWatchdog */
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /* Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /* Hardware IWDG selected */
+
+/* Option_Bytes_nRST_STOP */
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+
+/* Option_Bytes_nRST_STDBY  */
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+
+/* FLASH_Interrupts */	
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /* FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /* End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /* FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /* End of FLASH BANK1 Operation Interrupt source */
+
+/* FLASH_Flags */	
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /* FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /* FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /* FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /* FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /* FLASH BANK1 Write protected error flag */
+
+/* FLASH_Enhance_CLK */
+#define FLASH_Enhance_SYSTEM_HALF      ((uint32_t)0x00000000)   /* FLASH Enhance Clock = SYSTEM */
+#define FLASH_Enhance_SYSTEM           ((uint32_t)0x02000000)   /* Enhance_CLK = SYSTEM/2 */ 
+ 
+ 
+/*Functions used for all devices*/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+void FLASH_Unlock_Fast(void);
+void FLASH_Lock_Fast(void);
+void FLASH_ErasePage_Fast(uint32_t Page_Address);
+void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
+void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
+void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf);
+void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState);
+
+/* New function used for all devices */
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_fsmc.h

@@ -0,0 +1,287 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_fsmc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the FSMC
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_FSMC_H
+#define __CH32V30x_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#include "ch32v30x.h"
+
+
+/* FSMC Init structure definition */
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /* Defines the number of HCLK cycles to configure
+                                           the duration of the address setup time.
+                                           This parameter can be a value between 0 and 0xF.
+                                           @note: It is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /* Defines the number of HCLK cycles to configure
+                                           the duration of the address hold time.
+                                           This parameter can be a value between 0 and 0xF.
+                                           @note: It is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /* Defines the number of HCLK cycles to configure
+                                           the duration of the data setup time.
+                                           This parameter can be a value between 0 and 0xFF.
+                                           @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /* Defines the number of HCLK cycles to configure
+                                           the duration of the bus turnaround.
+                                           This parameter can be a value between 0 and 0xF.
+                                           @note: It is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                           This parameter can be a value between 1 and 0xF.
+                                           @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /* Defines the number of memory clock cycles to issue
+                                           to the memory before getting the first data.
+                                           The value of this parameter depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /* Specifies the asynchronous access mode.
+                                            This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+
+typedef struct
+{
+  uint32_t FSMC_Bank;                /* Specifies the NOR/SRAM memory bank that will be used.
+                                        This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /* Specifies whether the address and data values are
+                                        multiplexed on the databus or not.
+                                        This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /* Specifies the type of external memory attached to
+                                        the corresponding memory bank.
+                                        This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /* Specifies the external memory device width.
+                                        This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /* Enables or disables the burst access mode for Flash memory,
+                                        valid only with synchronous burst Flash memories.
+                                        This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+                                       
+  uint32_t FSMC_AsynchronousWait;    /* Enables or disables wait signal during asynchronous transfers,
+                                        valid only with asynchronous Flash memories.
+                                        This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+  uint32_t FSMC_WaitSignalPolarity;  /* Specifies the wait signal polarity, valid only when accessing
+                                        the Flash memory in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /* Enables or disables the Wrapped burst access mode for Flash
+                                        memory, valid only when accessing Flash memories in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /* Specifies if the wait signal is asserted by the memory one
+                                        clock cycle before the wait state or during the wait state,
+                                        valid only when accessing memories in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /* Enables or disables the write operation in the selected bank by the FSMC.
+                                        This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /* Enables or disables the wait-state insertion via wait
+                                        signal, valid for Flash memory access in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /* Enables or disables the extended mode.
+                                        This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /* Enables or disables the write burst operation.
+                                        This parameter can be a value of @ref FSMC_Write_Burst */
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the  ExtendedMode is not used*/
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /* Timing Parameters for write access if the  ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+
+typedef struct
+{
+  uint32_t FSMC_SetupTime;      /* Defines the number of HCLK cycles to setup address before
+                                   the command assertion for NAND-Flash read or write access
+                                   to common/Attribute or I/O memory space (depending on
+                                   the memory space timing to be configured).
+                                   This parameter can be a value between 0 and 0xFF.*/
+
+  uint32_t FSMC_WaitSetupTime;  /* Defines the minimum number of HCLK cycles to assert the
+                                   command for NAND-Flash read or write access to
+                                   common/Attribute or I/O memory space (depending on the
+                                   memory space timing to be configured).
+                                   This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HoldSetupTime;  /* Defines the number of HCLK clock cycles to hold address
+                                   (and data for write access) after the command deassertion
+                                   for NAND-Flash read or write access to common/Attribute
+                                   or I/O memory space (depending on the memory space timing
+                                   to be configured).
+                                   This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HiZSetupTime;   /* Defines the number of HCLK clock cycles during which the
+                                   databus is kept in HiZ after the start of a NAND-Flash
+                                   write access to common/Attribute or I/O memory space (depending
+                                   on the memory space timing to be configured).
+                                   This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+
+typedef struct
+{
+  uint32_t FSMC_Bank;             /* Specifies the NAND memory bank that will be used.
+                                     This parameter can be a value of @ref FSMC_NAND_Bank */
+
+  uint32_t FSMC_Waitfeature;      /* Enables or disables the Wait feature for the NAND Memory Bank.
+                                     This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_MemoryDataWidth;  /* Specifies the external memory device width.
+                                     This parameter can be any value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_ECC;              /* Enables or disables the ECC computation.
+                                     This parameter can be any value of @ref FSMC_ECC */
+
+  uint32_t FSMC_ECCPageSize;      /* Defines the page size for the extended ECC.
+                                     This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+  uint32_t FSMC_TCLRSetupTime;    /* Defines the number of HCLK cycles to configure the
+                                     delay between CLE low and RE low.
+                                     This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;     /* Defines the number of HCLK cycles to configure the
+                                     delay between ALE low and RE low.
+                                     This parameter can be a number between 0x0 and 0xFF */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /* FSMC Common Space Timing */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+
+/* FSMC_NORSRAM_Bank */
+#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
+
+/* FSMC_NAND_Bank */
+#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
+
+/* FSMC_Data_Address_Bus_Multiplexing */
+#define FSMC_DataAddressMux_Disable                     ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                      ((uint32_t)0x00000002)
+
+/* FSMC_Memory_Type */
+#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
+
+/* FSMC_Data_Width */
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
+
+/* FSMC_Burst_Access_Mode */
+#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
+
+/* FSMC_AsynchronousWait */
+#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
+
+/* FSMC_Wait_Signal_Polarity */
+#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
+
+/* FSMC_Wrap_Mode */
+#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
+
+/* FSMC_Wait_Timing */
+#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
+
+/* FSMC_Write_Operation */
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+
+/* FSMC_Wait_Signal */
+#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
+
+/* FSMC_Extended_Mode */
+#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
+
+/* FSMC_Write_Burst */
+#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
+
+/* FSMC_Access_Mode */
+#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
+
+/* FSMC_Wait_feature */
+#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
+
+/* FSMC_ECC */
+#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
+
+/* FSMC_ECC_Page_Size */
+#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
+
+/* FSMC_Interrupt_sources */
+#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
+#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
+
+/* FSMC_Flags */
+#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
+
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_gpio.h

@@ -0,0 +1,197 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_gpio.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      GPIO firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_GPIO_H
+#define __CH32V30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+                                 
+/* Output Maximum frequency selection */
+typedef enum
+{ 
+  GPIO_Speed_10MHz = 1,
+  GPIO_Speed_2MHz, 
+  GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+/* Configuration Mode enumeration */
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IPD = 0x28,
+  GPIO_Mode_IPU = 0x48,
+  GPIO_Mode_Out_OD = 0x14,
+  GPIO_Mode_Out_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+/* GPIO Init structure definition */
+typedef struct
+{
+  uint16_t GPIO_Pin;             /* Specifies the GPIO pins to be configured.
+                                    This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOSpeed_TypeDef GPIO_Speed;  /* Specifies the speed for the selected pins.
+                                    This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOMode_TypeDef GPIO_Mode;    /* Specifies the operating mode for the selected pins.
+                                    This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+	Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0                  ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                  ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                  ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                  ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                  ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                  ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                  ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                  ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                  ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                  ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                 ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                 ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                 ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                 ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                 ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                 ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All                ((uint16_t)0xFFFF)  /* All pins selected */
+
+/* GPIO_Remap_define */
+/* PCFR1 */
+#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /* USART1 Alternate Function mapping low bit */
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /* PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /* LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /* ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /* ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /* Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /* CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_MII_RMII_SEL     ((uint32_t)0x00200080)  /* MII or RMII selection */
+#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3             ((uint32_t)0x00201000)  /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+                                                               to TIM2 Internal Trigger 1 for calibration
+                                                               (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+/* PCFR2 */
+#define GPIO_Remap_TIM8             ((uint32_t)0x80000004)  /* TIM8 Alternate Function mapping */
+#define GPIO_PartialRemap_TIM9      ((uint32_t)0x80130008)  /* TIM9 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM9         ((uint32_t)0x80130010)  /* TIM9 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM10     ((uint32_t)0x80150020)  /* TIM10 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM10        ((uint32_t)0x80150040)  /* TIM10 Full Alternate Function mapping */
+#define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /* FSMC_NADV Alternate Function mapping */
+#define GPIO_PartialRemap_USART4    ((uint32_t)0x80300001)  /* USART4 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART4       ((uint32_t)0x80300002)  /* USART4 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART5    ((uint32_t)0x80320004)  /* USART5 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART5       ((uint32_t)0x80320008)  /* USART5 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART6    ((uint32_t)0x80340010)  /* USART6 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART6       ((uint32_t)0x80340020)  /* USART6 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART7    ((uint32_t)0x80360040)  /* USART7 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART7       ((uint32_t)0x80360080)  /* USART7 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART8    ((uint32_t)0x80380100)  /* USART8 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART8       ((uint32_t)0x80380200)  /* USART8 Full Alternate Function mapping */
+#define GPIO_Remap_USART1_HighBit   ((uint32_t)0x80200400)  /* USART1 Alternate Function mapping high bit */
+
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA        ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB        ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC        ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD        ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE        ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF        ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG        ((uint8_t)0x06)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0             ((uint8_t)0x00)
+#define GPIO_PinSource1             ((uint8_t)0x01)
+#define GPIO_PinSource2             ((uint8_t)0x02)
+#define GPIO_PinSource3             ((uint8_t)0x03)
+#define GPIO_PinSource4             ((uint8_t)0x04)
+#define GPIO_PinSource5             ((uint8_t)0x05)
+#define GPIO_PinSource6             ((uint8_t)0x06)
+#define GPIO_PinSource7             ((uint8_t)0x07)
+#define GPIO_PinSource8             ((uint8_t)0x08)
+#define GPIO_PinSource9             ((uint8_t)0x09)
+#define GPIO_PinSource10            ((uint8_t)0x0A)
+#define GPIO_PinSource11            ((uint8_t)0x0B)
+#define GPIO_PinSource12            ((uint8_t)0x0C)
+#define GPIO_PinSource13            ((uint8_t)0x0D)
+#define GPIO_PinSource14            ((uint8_t)0x0E)
+#define GPIO_PinSource15            ((uint8_t)0x0F)
+
+/* Ethernet_Media_Interface */
+#define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)
+
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_i2c.h

@@ -0,0 +1,211 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_i2c.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      I2C firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_I2C_H
+#define __CH32V30x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* I2C Init structure definition  */
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /* Specifies the clock frequency.
+                                       This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /* Specifies the I2C mode.
+                                       This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /* Specifies the I2C fast mode duty cycle.
+                                       This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /* Specifies the first device own address.
+                                       This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /* Enables or disables the acknowledgement.
+                                       This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
+                                       This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* I2C_mode */
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+
+/* I2C_duty_cycle_in_fast_mode */
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
+
+/* I2C_acknowledgement */
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+
+/* I2C_transfer_direction */
+#define I2C_Direction_Transmitter       ((uint8_t)0x00)
+#define I2C_Direction_Receiver          ((uint8_t)0x01)
+
+/* I2C_acknowledged_address */
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+
+/* I2C_registers */
+#define I2C_Register_CTLR1              ((uint8_t)0x00)
+#define I2C_Register_CTLR2              ((uint8_t)0x04)
+#define I2C_Register_OADDR1             ((uint8_t)0x08)
+#define I2C_Register_OADDR2             ((uint8_t)0x0C)
+#define I2C_Register_DATAR              ((uint8_t)0x10)
+#define I2C_Register_STAR1              ((uint8_t)0x14)
+#define I2C_Register_STAR2              ((uint8_t)0x18)
+#define I2C_Register_CKCFGR             ((uint8_t)0x1C)
+#define I2C_Register_RTR                ((uint8_t)0x20)
+
+/* I2C_SMBus_alert_pin_level */
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+
+/* I2C_PEC_position */
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+
+/* I2C_NACK_position */
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+/* SR2 register flags  */
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/* SR1 register flags */
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+
+/****************I2C Master Events (Events grouped in order of communication)********************/
+
+#define I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                ((uint32_t)0x00070080)  /* TRA, BUSY, MSL, TXE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/******************I2C Slave Events (Events grouped in order of communication)******************/
+
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002)  /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082)  /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+#define I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+
+/****************************************************************************************
+*                         I2C State Monitoring Functions                     
+****************************************************************************************/
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_iwdg.h

@@ -0,0 +1,56 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_iwdg.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the  
+*                      IWDG firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_IWDG_H
+#define __CH32V30x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* IWDG_WriteAccess */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+
+/* IWDG_prescaler */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+
+/* IWDG_Flag */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_misc.h

@@ -0,0 +1,46 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_misc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      miscellaneous firmware library functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/   
+#ifndef __CH32V30X_MISC_H
+#define __CH32V30X_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* NVIC Init Structure definition */	 
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;
+  uint8_t NVIC_IRQChannelPreemptionPriority;
+  uint8_t NVIC_IRQChannelSubPriority;
+  FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+ 
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0           ((uint32_t)0x00)
+#define NVIC_PriorityGroup_1           ((uint32_t)0x01)
+#define NVIC_PriorityGroup_2           ((uint32_t)0x02)
+#define NVIC_PriorityGroup_3           ((uint32_t)0x03)
+#define NVIC_PriorityGroup_4           ((uint32_t)0x04)
+
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_opa.h

@@ -0,0 +1,75 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_opa.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      OPA firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_OPA_H
+#define __CH32V30x_OPA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+#define OPA_PSEL_OFFSET 3
+#define OPA_NSEL_OFFSET 2
+#define OPA_MODE_OFFSET 1
+
+
+/* OPA member enumeration */
+typedef enum
+{
+   OPA1=0,
+   OPA2,
+   OPA3,
+   OPA4
+}OPA_Num_TypeDef;
+
+/* OPA PSEL enumeration */
+typedef enum
+{
+   CHP0=0,
+   CHP1
+}OPA_PSEL_TypeDef;
+
+/* OPA NSEL enumeration */
+typedef enum
+{
+   CHN0=0,
+   CHN1
+}OPA_NSEL_TypeDef;
+
+/* OPA Mode enumeration */
+typedef enum
+{
+   OUT_IO_ADC=0,
+   OUT_IO
+}OPA_Mode_TypeDef;
+
+/* OPA Init Structure definition */
+typedef struct
+{
+  OPA_Num_TypeDef   OPA_NUM;      /* Specifies the members of OPA */
+  OPA_PSEL_TypeDef  PSEL;         /* Specifies the positive channel of OPA */
+  OPA_NSEL_TypeDef  NSEL;         /* Specifies the negative channel of OPA */
+  OPA_Mode_TypeDef  Mode;         /* Specifies the mode of OPA */
+}OPA_InitTypeDef;
+
+
+void OPA_DeInit(void);
+void OPA_Init(OPA_InitTypeDef* OPA_InitStruct);
+void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct);
+void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_pwr.h

@@ -0,0 +1,64 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_pwr.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the PWR  
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_PWR_H
+#define __CH32V30x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* PVD_detection_level  */
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+	 
+/* Regulator_state_is_STOP_mode */
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+
+/* STOP_mode_entry */
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+ 
+/* PWR_Flag */
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_EnterSTANDBYMode_RAM(void);
+void PWR_EnterSTANDBYMode_RAM_LV(void);
+void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
+void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_rcc.h

@@ -0,0 +1,456 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rcc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RCC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_RCC_H
+#define __CH32V30x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* RCC_Exported_Types */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;  /* returns SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;    /* returns HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;   /* returns PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;   /* returns PCLK2 clock frequency expressed in Hz */
+  uint32_t ADCCLK_Frequency;  /* returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* HSE_configuration */
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+
+#ifdef CH32V30x_D8
+#define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+#define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+
+#else
+#define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
+
+#endif
+
+/* PLL_multiplication_factor */
+#ifdef CH32V30x_D8
+#define RCC_PLLMul_2                     ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                     ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                     ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                     ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                     ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                     ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                    ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                    ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                    ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                    ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                    ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                    ((uint32_t)0x00380000)
+#define RCC_PLLMul_18                    ((uint32_t)0x003C0000)
+
+#else
+#define RCC_PLLMul_18_EXTEN              ((uint32_t)0x00000000)
+#define RCC_PLLMul_3_EXTEN               ((uint32_t)0x00040000)
+#define RCC_PLLMul_4_EXTEN               ((uint32_t)0x00080000)
+#define RCC_PLLMul_5_EXTEN               ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6_EXTEN               ((uint32_t)0x00100000)
+#define RCC_PLLMul_7_EXTEN               ((uint32_t)0x00140000)
+#define RCC_PLLMul_8_EXTEN               ((uint32_t)0x00180000)
+#define RCC_PLLMul_9_EXTEN               ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10_EXTEN              ((uint32_t)0x00200000)
+#define RCC_PLLMul_11_EXTEN              ((uint32_t)0x00240000)
+#define RCC_PLLMul_12_EXTEN              ((uint32_t)0x00280000)
+#define RCC_PLLMul_13_EXTEN              ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14_EXTEN              ((uint32_t)0x00300000)
+#define RCC_PLLMul_6_5_EXTEN             ((uint32_t)0x00340000)
+#define RCC_PLLMul_15_EXTEN              ((uint32_t)0x00380000)
+#define RCC_PLLMul_16_EXTEN              ((uint32_t)0x003C0000)
+
+#endif
+
+/* PREDIV1_division_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PREDIV1_Div1                 ((uint32_t)0x00000000)
+#define RCC_PREDIV1_Div2                 ((uint32_t)0x00000001)
+#define RCC_PREDIV1_Div3                 ((uint32_t)0x00000002)
+#define RCC_PREDIV1_Div4                 ((uint32_t)0x00000003)
+#define RCC_PREDIV1_Div5                 ((uint32_t)0x00000004)
+#define RCC_PREDIV1_Div6                 ((uint32_t)0x00000005)
+#define RCC_PREDIV1_Div7                 ((uint32_t)0x00000006)
+#define RCC_PREDIV1_Div8                 ((uint32_t)0x00000007)
+#define RCC_PREDIV1_Div9                 ((uint32_t)0x00000008)
+#define RCC_PREDIV1_Div10                ((uint32_t)0x00000009)
+#define RCC_PREDIV1_Div11                ((uint32_t)0x0000000A)
+#define RCC_PREDIV1_Div12                ((uint32_t)0x0000000B)
+#define RCC_PREDIV1_Div13                ((uint32_t)0x0000000C)
+#define RCC_PREDIV1_Div14                ((uint32_t)0x0000000D)
+#define RCC_PREDIV1_Div15                ((uint32_t)0x0000000E)
+#define RCC_PREDIV1_Div16                ((uint32_t)0x0000000F)
+
+#endif
+
+/* PREDIV1_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_PREDIV1_Source_HSE           ((uint32_t)0x00000000)
+#define RCC_PREDIV1_Source_PLL2          ((uint32_t)0x00010000)
+
+#endif
+
+/* PREDIV2_division_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PREDIV2_Div1                 ((uint32_t)0x00000000)
+#define RCC_PREDIV2_Div2                 ((uint32_t)0x00000010)
+#define RCC_PREDIV2_Div3                 ((uint32_t)0x00000020)
+#define RCC_PREDIV2_Div4                 ((uint32_t)0x00000030)
+#define RCC_PREDIV2_Div5                 ((uint32_t)0x00000040)
+#define RCC_PREDIV2_Div6                 ((uint32_t)0x00000050)
+#define RCC_PREDIV2_Div7                 ((uint32_t)0x00000060)
+#define RCC_PREDIV2_Div8                 ((uint32_t)0x00000070)
+#define RCC_PREDIV2_Div9                 ((uint32_t)0x00000080)
+#define RCC_PREDIV2_Div10                ((uint32_t)0x00000090)
+#define RCC_PREDIV2_Div11                ((uint32_t)0x000000A0)
+#define RCC_PREDIV2_Div12                ((uint32_t)0x000000B0)
+#define RCC_PREDIV2_Div13                ((uint32_t)0x000000C0)
+#define RCC_PREDIV2_Div14                ((uint32_t)0x000000D0)
+#define RCC_PREDIV2_Div15                ((uint32_t)0x000000E0)
+#define RCC_PREDIV2_Div16                ((uint32_t)0x000000F0)
+
+#endif
+
+/* PLL2_multiplication_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PLL2Mul_2_5                  ((uint32_t)0x00000000)
+#define RCC_PLL2Mul_12_5                 ((uint32_t)0x00000100)
+#define RCC_PLL2Mul_4                    ((uint32_t)0x00000200)
+#define RCC_PLL2Mul_5                    ((uint32_t)0x00000300)
+#define RCC_PLL2Mul_6                    ((uint32_t)0x00000400)
+#define RCC_PLL2Mul_7                    ((uint32_t)0x00000500)
+#define RCC_PLL2Mul_8                    ((uint32_t)0x00000600)
+#define RCC_PLL2Mul_9                    ((uint32_t)0x00000700)
+#define RCC_PLL2Mul_10                   ((uint32_t)0x00000800)
+#define RCC_PLL2Mul_11                   ((uint32_t)0x00000900)
+#define RCC_PLL2Mul_12                   ((uint32_t)0x00000A00)
+#define RCC_PLL2Mul_13                   ((uint32_t)0x00000B00)
+#define RCC_PLL2Mul_14                   ((uint32_t)0x00000C00)
+#define RCC_PLL2Mul_15                   ((uint32_t)0x00000D00)
+#define RCC_PLL2Mul_16                   ((uint32_t)0x00000E00)
+#define RCC_PLL2Mul_20                   ((uint32_t)0x00000F00)
+
+#endif
+
+/* PLL3_multiplication_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PLL3Mul_2_5                  ((uint32_t)0x00000000)
+#define RCC_PLL3Mul_12_5                 ((uint32_t)0x00001000)
+#define RCC_PLL3Mul_4                    ((uint32_t)0x00002000)
+#define RCC_PLL3Mul_5                    ((uint32_t)0x00003000)
+#define RCC_PLL3Mul_6                    ((uint32_t)0x00004000)
+#define RCC_PLL3Mul_7                    ((uint32_t)0x00005000)
+#define RCC_PLL3Mul_8                    ((uint32_t)0x00006000)
+#define RCC_PLL3Mul_9                    ((uint32_t)0x00007000)
+#define RCC_PLL3Mul_10                   ((uint32_t)0x00008000)
+#define RCC_PLL3Mul_11                   ((uint32_t)0x00009000)
+#define RCC_PLL3Mul_12                   ((uint32_t)0x0000A000)
+#define RCC_PLL3Mul_13                   ((uint32_t)0x0000B000)
+#define RCC_PLL3Mul_14                   ((uint32_t)0x0000C000)
+#define RCC_PLL3Mul_15                   ((uint32_t)0x0000D000)
+#define RCC_PLL3Mul_16                   ((uint32_t)0x0000E000)
+#define RCC_PLL3Mul_20                   ((uint32_t)0x0000F000)
+
+#endif
+
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+
+/* APB1_APB2_clock_source */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#ifdef CH32V30x_D8C
+#define RCC_IT_PLL2RDY                   ((uint8_t)0x20)
+#define RCC_IT_PLL3RDY                   ((uint8_t)0x40)
+
+#endif
+
+/* USB_OTG_FS_clock_source */
+#define RCC_OTGFSCLKSource_PLLCLK_Div1   ((uint8_t)0x00)
+#define RCC_OTGFSCLKSource_PLLCLK_Div2   ((uint8_t)0x01)
+#define RCC_OTGFSCLKSource_PLLCLK_Div3   ((uint8_t)0x02)
+
+/* I2S2_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_I2S2CLKSource_SYSCLK         ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_PLL3_VCO       ((uint8_t)0x01)
+
+#endif
+
+/* I2S3_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_I2S3CLKSource_SYSCLK         ((uint8_t)0x00)
+#define RCC_I2S3CLKSource_PLL3_VCO       ((uint8_t)0x01)
+
+#endif
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+
+/* LSE_configuration */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+
+/* RTC_clock_source */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_RNG                ((uint32_t)0x00000200)
+#define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
+#define RCC_AHBPeriph_USBHS              ((uint32_t)0x00000800)
+#define RCC_AHBPeriph_OTG_FS             ((uint32_t)0x00001000)
+#define RCC_AHBPeriph_DVP                ((uint32_t)0x00002000)
+#define RCC_AHBPeriph_ETH_MAC            ((uint32_t)0x00004000)
+#define RCC_AHBPeriph_ETH_MAC_Tx         ((uint32_t)0x00008000)
+#define RCC_AHBPeriph_ETH_MAC_Rx         ((uint32_t)0x00010000)
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_UART6             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_UART7             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_UART8             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+
+#ifdef CH32V30x_D8C
+#define RCC_MCO_PLL2CLK                  ((uint8_t)0x08)
+#define RCC_MCO_PLL3CLK_Div2             ((uint8_t)0x09)
+#define RCC_MCO_XT1                      ((uint8_t)0x0A)
+#define RCC_MCO_PLL3CLK                  ((uint8_t)0x0B)
+
+#endif
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+#ifdef CH32V30x_D8C
+#define RCC_FLAG_PLL2RDY                 ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY                 ((uint8_t)0x3D)
+
+#endif
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8      ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK           ((uint32_t)0x00000004)
+
+/* RNG_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_RNGCLKSource_SYSCLK          ((uint32_t)0x00)
+#define RCC_RNGCLKSource_PLL3_VCO        ((uint32_t)0x01)
+
+#endif
+
+/* ETH1G_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_ETH1GCLKSource_PLL2_VCO      ((uint32_t)0x00)
+#define RCC_ETH1GCLKSource_PLL3_VCO      ((uint32_t)0x01)
+#define RCC_ETH1GCLKSource_PB1_IN        ((uint32_t)0x02)
+
+#endif
+
+/* USBFS_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_USBPLL_Div1                  ((uint32_t)0x00)
+#define RCC_USBPLL_Div2                  ((uint32_t)0x01)
+#define RCC_USBPLL_Div3                  ((uint32_t)0x02)
+#define RCC_USBPLL_Div4                  ((uint32_t)0x03)
+#define RCC_USBPLL_Div5                  ((uint32_t)0x04)
+#define RCC_USBPLL_Div6                  ((uint32_t)0x05)
+#define RCC_USBPLL_Div7                  ((uint32_t)0x06)
+#define RCC_USBPLL_Div8                  ((uint32_t)0x07)
+
+#endif
+
+/* USBHSPLL_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_HSBHSPLLCLKSource_HSE        ((uint32_t)0x00)
+#define RCC_HSBHSPLLCLKSource_HSI        ((uint32_t)0x01)
+
+#endif
+
+/* USBHSPLLCKREF_clock_select */
+#ifdef CH32V30x_D8C
+#define RCC_USBHSPLLCKREFCLK_3M          ((uint32_t)0x00)
+#define RCC_USBHSPLLCKREFCLK_4M          ((uint32_t)0x01)
+#define RCC_USBHSPLLCKREFCLK_8M          ((uint32_t)0x02)
+#define RCC_USBHSPLLCKREFCLK_5M          ((uint32_t)0x03)
+
+#endif
+
+/* OTGUSBCLK48M_clock_source */
+#define RCC_USBCLK48MCLKSource_PLLCLK    ((uint32_t)0x00)
+#define RCC_USBCLK48MCLKSource_USBPHY    ((uint32_t)0x01)
+
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+void RCC_ADCCLKADJcmd(FunctionalState NewState);
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
+
+#ifdef CH32V30x_D8C
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+void RCC_PLL2Cmd(FunctionalState NewState);
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+void RCC_PLL3Cmd(FunctionalState NewState);
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
+void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
+void RCC_ETH1G_125Mcmd(FunctionalState NewState);
+void RCC_USBHSConfig(uint32_t RCC_USBHS);
+void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
+void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
+void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_rng.h

@@ -0,0 +1,41 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rng.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the
+*                      RNG firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_RNG_H
+#define __CH32V30x_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#include "ch32v30x.h"
+
+ /* RNG_flags_definition*/
+#define RNG_FLAG_DRDY               ((uint8_t)0x0001) /* Data ready */
+#define RNG_FLAG_CECS               ((uint8_t)0x0002) /* Clock error current status */
+#define RNG_FLAG_SECS               ((uint8_t)0x0004) /* Seed error current status */
+
+/* RNG_interrupts_definition */
+#define RNG_IT_CEI                  ((uint8_t)0x20) /* Clock error interrupt */
+#define RNG_IT_SEI                  ((uint8_t)0x40) /* Seed error interrupt */
+
+
+void RNG_Cmd(FunctionalState NewState);
+uint32_t RNG_GetRandomNumber(void);
+void RNG_ITConfig(FunctionalState NewState);
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
+void RNG_ClearFlag(uint8_t RNG_FLAG);
+ITStatus RNG_GetITStatus(uint8_t RNG_IT);
+void RNG_ClearITPendingBit(uint8_t RNG_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_rtc.h

@@ -0,0 +1,54 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rtc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the RTC  
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_RTC_H
+#define __CH32V30x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+/* RTC_interrupts_define */
+#define RTC_IT_OW            ((uint16_t)0x0004)  /* Overflow interrupt */
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /* Alarm interrupt */
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /* Second interrupt */
+
+/* RTC_interrupts_flags */
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /* Registers Synchronized flag */
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /* Overflow flag */
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /* Alarm flag */
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /* Second flag */
+	 
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_sdio.h

@@ -0,0 +1,254 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_sdio.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the SDIO
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_SDIO_H
+#define __CH32V30x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* SDIO Init structure definition */
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /* Specifies the clock transition on which the bit capture is made.
+                                         This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /* Specifies whether the SDIO Clock divider bypass is
+                                         enabled or disabled.
+                                         This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /* Specifies whether SDIO Clock output is enabled or
+                                         disabled when the bus is idle.
+                                         This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /* Specifies the SDIO bus width.
+                                         This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /* Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                         This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /* Specifies the clock frequency of the SDIO controller.
+                                         This parameter can be a value between 0x00 and 0xFF. */
+                                           
+} SDIO_InitTypeDef;
+
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /* Specifies the SDIO command argument which is sent
+                              to a card as part of a command message. If a command
+                              contains an argument, it must be loaded into this register
+                              before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /* Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /* Specifies the SDIO response type.
+                              This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                              This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /* Specifies whether SDIO Command path state machine (CPSM)
+                              is enabled or disabled.
+                              This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /* Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /* Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /* Specifies the data block size for block transfer.
+                                   This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /* Specifies the data transfer direction, whether the transfer
+                                   is a read or write.
+                                   This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /* Specifies whether data transfer is in stream or block mode.
+                                   This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /* Specifies whether SDIO Data path state machine (DPSM)
+                                   is enabled or disabled.
+                                   This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+
+/* SDIO_Clock_Edge */
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+
+/* SDIO_Clock_Bypass */
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+
+/* SDIO_Clock_Power_Save */
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+
+/* SDIO_Bus_Wide */
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+
+/* SDIO_Hardware_Flow_Control */
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+
+/* SDIO_Power_State */
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+
+/* SDIO_Interrupt_sources */
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+
+/* SDIO_Response_Type */
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+
+/* SDIO_Wait_Interrupt_State */
+#define SDIO_Wait_No                        ((uint32_t)0x00000000)
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100)
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200)
+
+/* SDIO_CPSM_State */
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+
+/* SDIO_Response_Registers */
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+
+/* SDIO_Data_Block_Size */
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+
+/* SDIO_Transfer_Direction */
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+
+/* SDIO_Transfer_Type */
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+
+/* SDIO_DPSM_State */
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+
+/* SDIO_Flags */
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+
+/* SDIO_Read_Wait_Mode */
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_spi.h

@@ -0,0 +1,229 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_spi.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the  
+*                      SPI firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_SPI_H
+#define __CH32V30x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* SPI Init structure definition */
+typedef struct
+{
+  uint16_t SPI_Direction;           /* Specifies the SPI unidirectional or bidirectional data mode.
+                                       This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /* Specifies the SPI operating mode.
+                                       This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /* Specifies the SPI data size.
+                                       This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /* Specifies the serial clock steady state.
+                                       This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /* Specifies the clock active edge for the bit capture.
+                                       This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /* Specifies whether the NSS signal is managed by
+                                       hardware (NSS pin) or by software using the SSI bit.
+                                       This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /* Specifies the Baud Rate prescaler value which will be
+                                       used to configure the transmit and receive SCK clock.
+                                       This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                       @note The communication clock is derived from the master
+                                             clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /* Specifies whether data transfers start from MSB or LSB bit.
+                                       This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /* Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/* I2S Init structure definition */
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /* Specifies the I2S operating mode.
+                                This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /* Specifies the standard used for the I2S communication.
+                                This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /* Specifies the data format for the I2S communication.
+                                This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /* Specifies whether the I2S MCLK output is enabled or not.
+                                This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /* Specifies the frequency selected for the I2S communication.
+                                This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /* Specifies the idle state of the I2S clock.
+                                This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* SPI_data_direction */  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+
+/* SPI_mode */
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+
+/* SPI_data_size */
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+
+/* SPI_Clock_Polarity */
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+
+/* SPI_Clock_Phase */
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+
+/* SPI_Slave_Select_management */
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+
+/* SPI_BaudRate_Prescaler */
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+
+/* SPI_MSB_LSB_transmission */
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+
+/* I2S_Mode */
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+
+/* I2S_Standard */
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+
+/* I2S_Data_Format */
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+
+/* I2S_MCLK_Output */
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+
+/* I2S_Audio_Frequency */
+#define I2S_AudioFreq_192k              ((uint32_t)192000)
+#define I2S_AudioFreq_96k               ((uint32_t)96000)
+#define I2S_AudioFreq_48k               ((uint32_t)48000)
+#define I2S_AudioFreq_44k               ((uint32_t)44100)
+#define I2S_AudioFreq_32k               ((uint32_t)32000)
+#define I2S_AudioFreq_22k               ((uint32_t)22050)
+#define I2S_AudioFreq_16k               ((uint32_t)16000)
+#define I2S_AudioFreq_11k               ((uint32_t)11025)
+#define I2S_AudioFreq_8k                ((uint32_t)8000)
+#define I2S_AudioFreq_Default           ((uint32_t)2)
+
+/* I2S_Clock_Polarity */
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+
+/* SPI_I2S_DMA_transfer_requests */
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+
+/* SPI_NSS_internal_software_management */
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+
+/* SPI_CRC_Transmit_Receive */
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+
+/* SPI_direction_transmit_receive */
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+
+/* SPI_I2S_interrupts_definition */
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+
+/* SPI_I2S_flags_definition */
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_tim.h

@@ -0,0 +1,515 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_tim.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the  
+*                      TIM firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_TIM_H
+#define __CH32V30x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* TIM Time Base Init structure definition */
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /* Specifies the prescaler value used to divide the TIM clock.
+                                     This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /* Specifies the counter mode.
+                                     This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint16_t TIM_Period;            /* Specifies the period value to be loaded into the active
+                                     Auto-Reload Register at the next update event.
+                                     This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /* Specifies the clock division.
+                                    This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /* Specifies the repetition counter value. Each time the RCR downcounter
+                                     reaches zero, an update event is generated and counting restarts
+                                     from the RCR value (N).
+                                     This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     This parameter must be a number between 0x00 and 0xFF. 
+                                     @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;       
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+  uint16_t TIM_OCMode;        /* Specifies the TIM mode.
+                                 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /* Specifies the TIM Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /* Specifies the TIM complementary Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_Pulse;         /* Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                 This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_OCPolarity;    /* Specifies the output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /* Specifies the complementary output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCIdleState;   /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCNIdleState;  /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+  uint16_t TIM_Channel;      /* Specifies the TIM channel.
+                                This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /* Specifies the active edge of the input signal.
+                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /* Specifies the input.
+                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /* Specifies the Input Capture Prescaler.
+                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /* Specifies the input capture filter.
+                                This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+  uint16_t TIM_OSSRState;        /* Specifies the Off-State selection used in Run mode.
+                                    This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /* Specifies the Off-State used in Idle state.
+                                    This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /* Specifies the LOCK level parameters.
+                                    This parameter can be a value of @ref Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /* Specifies the delay time between the switching-off and the
+                                    switching-on of the outputs.
+                                    This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /* Specifies whether the TIM Break input is enabled or not. 
+                                    This parameter can be a value of @ref Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /* Specifies the TIM Break Input pin polarity.
+                                    This parameter can be a value of @ref Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /* Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                    This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* TIM_Output_Compare_and_PWM_modes */
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+
+/* TIM_One_Pulse_Mode */
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+
+/* TIM_Channel */
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+/* TIM_Clock_Division_CKD */
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+
+/* TIM_Counter_Mode */
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+
+/* TIM_Output_Compare_Polarity */
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+
+/* TIM_Output_Compare_N_Polarity */  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+
+/* TIM_Output_Compare_state */
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+
+/* TIM_Output_Compare_N_state */
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+
+/* TIM_Capture_Compare_state */
+#define TIM_CCx_Enable                     ((uint16_t)0x0001)
+#define TIM_CCx_Disable                    ((uint16_t)0x0000)
+
+/* TIM_Capture_Compare_N_state */
+#define TIM_CCxN_Enable                    ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                   ((uint16_t)0x0000)
+
+/* Break_Input_enable_disable */
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+
+/* Break_Polarity */
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+
+/* TIM_AOE_Bit_Set_Reset */
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+
+/* Lock_level */
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+
+/* OSSI_Off_State_Selection_for_Idle_mode_state */
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+
+/* OSSR_Off_State_Selection_for_Run_mode_state */
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Idle_State */
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_N_Idle_State */
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+
+/* TIM_Input_Capture_Polarity */
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+                                     
+/* TIM_Input_Capture_Selection */
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                 connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be
+                                                                 connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+
+/* TIM_Input_Capture_Prescaler */
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /* Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /* Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /* Capture performed once every 8 events. */
+
+/* TIM_interrupt_sources */
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+
+/* TIM_DMA_Base_address */
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+
+/* TIM_DMA_Burst_Length */
+#define TIM_DMABurstLength_1Transfer       ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers      ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers      ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers      ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers      ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers      ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers      ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers      ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers      ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers     ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers     ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers     ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers     ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers     ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers     ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers     ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers     ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers     ((uint16_t)0x1100)
+
+/* TIM_DMA_sources */
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+
+/* TIM_External_Trigger_Prescaler */
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+
+/* TIM_Internal_Trigger_Selection */
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+
+/* TIM_TIx_External_Clock_Source */
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/* TIM_External_Trigger_Polarity */
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+
+/* TIM_Prescaler_Reload_Mode */
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+
+/* TIM_Forced_Action */
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+
+/* TIM_Encoder_Mode */
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+
+/* TIM_Event_Source */
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+
+/* TIM_Update_Source */
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow
+                                                                 or the setting of UG bit, or an update generation
+                                                                 through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
+
+/* TIM_Output_Compare_Preload_State */
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Fast_State */
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Clear_State */
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+
+/* TIM_Trigger_Output_Source */
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+
+/* TIM_Slave_Mode */
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+
+/* TIM_Master_Slave_Mode */
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+
+/* TIM_Flags */
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+
+/* TIM_Legacy */
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_usart.h

@@ -0,0 +1,195 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_usart.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      USART firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_USART_H
+#define __CH32V30x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+ 
+
+/* USART Init Structure definition */  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /* This member configures the USART communication baud rate.
+                                         The baud rate is computed using the following formula:
+                                          - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                          - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+  uint16_t USART_WordLength;          /* Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /* Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /* Specifies the parity mode.
+                                         This parameter can be a value of @ref USART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /* Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /* Specifies whether the USART clock is enabled or disabled.
+                             This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /* Specifies the steady state value of the serial clock.
+                             This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /* Specifies the clock transition on which the bit capture is made.
+                             This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
+                             data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                             This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* USART_Word_Length */ 
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+/* USART_Stop_Bits */  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+
+/* USART_Parity */  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+
+/* USART_Mode */ 
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+#define USART_IT_ORE                          USART_IT_ORE_ER
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b       ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b       ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/inc/ch32v30x_wwdg.h

@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_wwdg.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the WWDG 
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_WWDG_H
+#define __CH32V30x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+/* WWDG_Prescaler */  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+
+  
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/Makefile

@@ -0,0 +1,18 @@
+SRC_FILES := ch32v30x_adc.c \
+	ch32v30x_bkp.c \
+	ch32v30x_can.c \
+	ch32v30x_dac.c ch32v30x_dbgmcu.c ch32v30x_dma.c ch32v30x_dvp.c \
+	ch32v30x_eth.c ch32v30x_exti.c \
+	ch32v30x_flash.c ch32v30x_fsmc.c \
+	ch32v30x_gpio.c \
+	ch32v30x_i2c.c ch32v30x_iwdg.c \
+	ch32v30x_misc.c \
+	ch32v30x_opa.c \
+	ch32v30x_pwr.c \
+	ch32v30x_rcc.c ch32v30x_rng.c ch32v30x_rtc.c \
+	ch32v30x_sdio.c ch32v30x_spi.c \
+	ch32v30x_tim.c \
+	ch32v30x_usart.c \
+	ch32v30x_wwdg.c 
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_bkp.c

@@ -0,0 +1,242 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_bkp.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the BKP firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_rcc.h"
+
+/* BKP registers bit mask */
+
+/* OCTLR register bit mask */
+#define OCTLR_CAL_MASK    ((uint16_t)0xFF80)
+#define OCTLR_MASK        ((uint16_t)0xFC7F)
+
+/*********************************************************************
+ * @fn      BKP_DeInit
+ *
+ * @brief   Deinitializes the BKP peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinLevelConfig
+ *
+ * @brief   Configures the Tamper Pin active level.
+ *
+ * @param   BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ *            BKP_TamperPinLevel_High - Tamper pin active on high level.
+ *            BKP_TamperPinLevel_Low - Tamper pin active on low level.
+ *
+ * @return  none
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+    if(BKP_TamperPinLevel)
+    {
+        BKP->TPCTLR |= (1 << 1);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 1);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinCmd
+ *
+ * @brief   Enables or disables the Tamper Pin activation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCTLR |= (1 << 0);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ITConfig
+ *
+ * @brief   Enables or disables the Tamper Pin Interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCSR |= (1 << 2);
+    }
+    else
+    {
+        BKP->TPCSR &= ~(1 << 2);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_RTCOutputConfig
+ *
+ * @brief   Select the RTC output source to output on the Tamper pin.
+ *
+ * @param   BKP_RTCOutputSource - specifies the RTC output source.
+ *            BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
+ *            BKP_RTCOutputSource_CalibClock - output the RTC clock with
+ *        frequency divided by 64 on the Tamper pin.
+ *            BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
+ *        on the Tamper pin.
+ *            BKP_RTCOutputSource_Second - output the RTC Second pulse
+ *        signal on the Tamper pin.
+ *
+ * @return  none
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_MASK;
+    tmpreg |= BKP_RTCOutputSource;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_SetRTCCalibrationValue
+ *
+ * @brief   Sets RTC Clock Calibration value.
+ *
+ * @param   CalibrationValue - specifies the RTC Clock Calibration value.
+ *            This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_CAL_MASK;
+    tmpreg |= CalibrationValue;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_WriteBackupRegister
+ *
+ * @brief   Writes user data to the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *          Data - data to write.
+ *
+ * @return  none
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      BKP_ReadBackupRegister
+ *
+ * @brief   Reads data from the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *            This parameter can be BKP_DRx where x=[1, 42].
+ *
+ * @return  none
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      BKP_GetFlagStatus
+ *
+ * @brief   Checks whether the Tamper Pin Event flag is set or not.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+    if(BKP->TPCSR & (1 << 8))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearFlag
+ *
+ * @brief   Clears Tamper Pin Event pending flag.
+ *
+ * @return  none
+ */
+void BKP_ClearFlag(void)
+{
+    BKP->TPCSR |= BKP_CTE;
+}
+
+/*********************************************************************
+ * @fn      BKP_GetITStatus
+ *
+ * @brief   Checks whether the Tamper Pin Interrupt has occurred or not.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus BKP_GetITStatus(void)
+{
+    if(BKP->TPCSR & (1 << 9))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearITPendingBit
+ *
+ * @brief   Clears Tamper Pin Interrupt pending bit.
+ *
+ * @return  none
+ */
+void BKP_ClearITPendingBit(void)
+{
+    BKP->TPCSR |= BKP_CTI;
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_crc.c

@@ -0,0 +1,98 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_crc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the CRC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_crc.h"
+
+/*********************************************************************
+ * @fn      CRC_ResetDR
+ *
+ * @brief   Resets the CRC Data register (DR).
+ *
+ * @return  none
+ */
+void CRC_ResetDR(void)
+{
+    CRC->CTLR = CRC_CTLR_RESET;
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given data word(32-bit).
+ *
+ * @param   Data - data word(32-bit) to compute its CRC.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+    CRC->DATAR = Data;
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcBlockCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ *
+ * @param   pBuffer - pointer to the buffer containing the data to be computed.
+ *          BufferLength - length of the buffer to be computed.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    for(index = 0; index < BufferLength; index++)
+    {
+        CRC->DATAR = pBuffer[index];
+    }
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_GetCRC
+ *
+ * @brief   Returns the current CRC value.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_GetCRC(void)
+{
+    return (CRC->IDATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_SetIDRegister
+ *
+ * @brief   Stores a 8-bit data in the Independent Data(ID) register.
+ *
+ * @param   IDValue - 8-bit value to be stored in the ID register.
+ *
+ * @return  none
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+    CRC->IDATAR = IDValue;
+}
+
+/*********************************************************************
+ * @fn      CRC_GetIDRegister
+ *
+ * @brief   Returns the 8-bit data stored in the Independent Data(ID) register.
+ *
+ * @return  8-bit value of the ID register.
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+    return (CRC->IDATAR);
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_dac.c

@@ -0,0 +1,302 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dac.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DAC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+****************************************************************************************/
+#include "ch32v30x_dac.h"
+#include "ch32v30x_rcc.h"
+
+/* CTLR register Mask */
+#define CTLR_CLEAR_MASK    ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTR masks */
+#define DUAL_SWTR_SET      ((uint32_t)0x00000003)
+#define DUAL_SWTR_RESET    ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET     ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET     ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET     ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET         ((uint32_t)0x0000002C)
+
+/*********************************************************************
+ * @fn      DAC_DeInit
+ *
+ * @brief   Deinitializes the DAC peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void DAC_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      DAC_Init
+ *
+ * @brief   Initializes the DAC peripheral according to the specified parameters in
+ *        the DAC_InitStruct.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          DAC_InitStruct - pointer to a DAC_InitTypeDef structure.
+ *
+ * @return  none
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+    tmpreg1 = DAC->CTLR;
+    tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel);
+    tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+               DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+    tmpreg1 |= tmpreg2 << DAC_Channel;
+    DAC->CTLR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      DAC_StructInit
+ *
+ * @brief   Fills each DAC_InitStruct member with its default value.
+ *
+ * @param   DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized.
+ *
+ * @return  none
+ */
+void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
+{
+    DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+    DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+    DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+    DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/*********************************************************************
+ * @fn      DAC_Cmd
+ *
+ * @brief   Enables or disables the specified DAC channel.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTLR |= (DAC_EN1 << DAC_Channel);
+    }
+    else
+    {
+        DAC->CTLR &= ~(DAC_EN1 << DAC_Channel);
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_DMACmd
+ *
+ * @brief   Enables or disables the specified DAC channel DMA request.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel);
+    }
+    else
+    {
+        DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel);
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_SoftwareTriggerCmd
+ *
+ * @brief   Enables or disables the selected DAC channel software trigger.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4);
+    }
+    else
+    {
+        DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4));
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_DualSoftwareTriggerCmd
+ *
+ * @brief   Enables or disables the two DAC channel software trigger.
+ *
+ * @param   NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->SWTR |= DUAL_SWTR_SET;
+    }
+    else
+    {
+        DAC->SWTR &= DUAL_SWTR_RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_WaveGenerationCmd
+ *
+ * @brief   Enables or disables the selected DAC channel wave generation.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          DAC_Wave - Specifies the wave type to enable or disable.
+ *            DAC_Wave_Noise - noise wave generation
+ *            DAC_Wave_Triangle - triangle wave generation
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTLR |= DAC_Wave << DAC_Channel;
+    }
+    else
+    {
+        DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_SetChannel1Data
+ *
+ * @brief   Set the specified data holding register value for DAC channel1.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *          Data - Data to be loaded in the selected data holding register.
+ *
+ * @return  none
+ */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DHR12R1_OFFSET + DAC_Align;
+
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      DAC_SetChannel2Data
+ *
+ * @brief   Set the specified data holding register value for DAC channel2.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *            Data - Data to be loaded in the selected data holding register.
+ *
+ * @return  none
+ */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DHR12R2_OFFSET + DAC_Align;
+
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      DAC_SetDualChannelData
+ *
+ * @brief   Set the specified data holding register value for two DAC.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *            Data - Data to be loaded in the selected data holding register.
+ *          Data1 - Data for DAC Channel1.
+ *          Data2 - Data for DAC Channel2
+ *
+ * @return  none
+ */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+    uint32_t data = 0, tmp = 0;
+
+    if(DAC_Align == DAC_Align_8b_R)
+    {
+        data = ((uint32_t)Data2 << 8) | Data1;
+    }
+    else
+    {
+        data = ((uint32_t)Data2 << 16) | Data1;
+    }
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DHR12RD_OFFSET + DAC_Align;
+
+    *(__IO uint32_t *)tmp = data;
+}
+
+/*********************************************************************
+ * @fn      DAC_GetDataOutputValue
+ *
+ * @brief   Returns the last data output value of the selected DAC channel.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *
+ * @return  none
+ */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+    return (uint16_t)(*(__IO uint32_t *)tmp);
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_dbgmcu.c

@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dbgmcu.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DBGMCU firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+****************************************************************************************/
+#include "ch32v30x_dbgmcu.h"
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/*********************************************************************
+ * @fn      DBGMCU_GetREVID
+ *
+ * @brief   Returns the device revision identifier.
+ *
+ * @return  Revision identifier.
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+    return ((*(uint32_t *)0x1FFFF704) >> 16);
+}
+
+/*********************************************************************
+ * @fn      DBGMCU_GetDEVID
+ *
+ * @brief   Returns the device identifier.
+ *
+ * @return  Device identifier.
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+    return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_dma.c

@@ -0,0 +1,690 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dma.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DMA firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_dma.h"
+#include "ch32v30x_rcc.h"
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask     ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA1_Channel2_IT_Mask     ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA1_Channel3_IT_Mask     ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA1_Channel4_IT_Mask     ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA1_Channel5_IT_Mask     ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA1_Channel6_IT_Mask     ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA1_Channel7_IT_Mask     ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask     ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA2_Channel2_IT_Mask     ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA2_Channel3_IT_Mask     ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA2_Channel4_IT_Mask     ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA2_Channel5_IT_Mask     ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA2_Channel6_IT_Mask     ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA2_Channel7_IT_Mask     ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+#define DMA2_Channel8_IT_Mask     ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
+#define DMA2_Channel9_IT_Mask     ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9))
+#define DMA2_Channel10_IT_Mask    ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10))
+#define DMA2_Channel11_IT_Mask    ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                 ((uint32_t)0x10000000)
+#define DMA2_EXTEN_FLAG_Mask      ((uint32_t)0x20000000)
+
+/* DMA registers Masks */
+#define CFGR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
+
+/*********************************************************************
+ * @fn      DMA_DeInit
+ *
+ * @brief   Deinitializes the DMAy Channelx registers to their default
+ *        reset values.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    DMAy_Channelx->CFGR = 0;
+    DMAy_Channelx->CNTR = 0;
+    DMAy_Channelx->PADDR = 0;
+    DMAy_Channelx->MADDR = 0;
+    if(DMAy_Channelx == DMA1_Channel1)
+    {
+        DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel2)
+    {
+        DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel3)
+    {
+        DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel4)
+    {
+        DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel5)
+    {
+        DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel6)
+    {
+        DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel7)
+    {
+        DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel1)
+    {
+        DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel2)
+    {
+        DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel3)
+    {
+        DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel4)
+    {
+        DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel5)
+    {
+        DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel6)
+    {
+        DMA2->INTFCR |= DMA2_Channel6_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel7)
+    {
+        DMA2->INTFCR |= DMA2_Channel7_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel8)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel9)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel10)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel11)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_Init
+ *
+ * @brief   Initializes the DMAy Channelx according to the specified
+ *        parameters in the DMA_InitStruct.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = DMAy_Channelx->CFGR;
+    tmpreg &= CFGR_CLEAR_Mask;
+    tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+              DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+              DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+              DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+    DMAy_Channelx->CFGR = tmpreg;
+    DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
+    DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+    DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*********************************************************************
+ * @fn      DMA_StructInit
+ *
+ * @brief   Fills each DMA_InitStruct member with its default value.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
+{
+    DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+    DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+    DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+    DMA_InitStruct->DMA_BufferSize = 0;
+    DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+    DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+    DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/*********************************************************************
+ * @fn      DMA_Cmd
+ *
+ * @brief   Enables or disables the specified DMAy Channelx.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_ITConfig
+ *
+ * @brief   Enables or disables the specified DMAy Channelx interrupts.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_IT - specifies the DMA interrupts sources to be enabled
+ *        or disabled.
+ *           DMA_IT_TC - Transfer complete interrupt mask
+ *           DMA_IT_HT - Half transfer interrupt mask
+ *           DMA_IT_TE -  Transfer error interrupt mask
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_IT;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= ~DMA_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_SetCurrDataCounter
+ *
+ * @brief   Sets the number of data units in the current DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DataNumber - The number of data units in the current DMAy Channelx
+ *        transfer.
+ *
+ * @return  none
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
+{
+    DMAy_Channelx->CNTR = DataNumber;
+}
+
+/*********************************************************************
+ * @fn      DMA_GetCurrDataCounter
+ *
+ * @brief   Returns the number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *
+ * @return  DataNumber - The number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    return ((uint16_t)(DMAy_Channelx->CNTR));
+}
+
+/*********************************************************************
+ * @fn      DMA_GetFlagStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx flag is set or not.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t   tmpreg = 0;
+
+    if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        tmpreg = DMA2_EXTEN->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearFlag
+ *
+ * @brief   Clears the DMAy Channelx's pending flags.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+    if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
+    {
+        DMA2->INTFCR = DMAy_FLAG;
+    }
+    else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        DMA2_EXTEN->INTFCR = DMAy_FLAG;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_FLAG;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_GetITStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx interrupt has
+ *        occurred or not.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_IT_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_IT_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_IT_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_IT_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_IT_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_IT_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+
+    if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        tmpreg = DMA2_EXTEN->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if((tmpreg & DMAy_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearITPendingBit
+ *
+ * @brief   Clears the DMAy Channelx's interrupt pending bits.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_IT_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_IT_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_IT_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_IT_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_IT_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_IT_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+    if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
+    {
+        DMA2->INTFCR = DMAy_IT;
+    }
+    else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        DMA2_EXTEN->INTFCR = DMAy_IT;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_IT;
+    }
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_dvp.c

@@ -0,0 +1,133 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dvp.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DVP firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_dvp.h"
+
+/*********************************************************************
+ * @fn      DVP_INTCfg
+ *
+ * @brief   DVP interrupt configuration
+ *
+ * @param   s - interrupt enable
+ *             ENABLE
+ *             DISABLE
+ *          i - interrupt type
+ *             RB_DVP_IE_STP_FRM
+ *             RB_DVP_IE_FIFO_OV
+ *             RB_DVP_IE_FRM_DONE
+ *             RB_DVP_IE_ROW_DONE
+ *             RB_DVP_IE_STR_FRM
+ *
+ * @return  none
+ */
+void DVP_INTCfg(uint8_t s, uint8_t i)
+{
+    if(s)
+    {
+        DVP->IER |= i;
+    }
+    else
+    {
+        DVP->IER &= ~i;
+    }
+}
+
+/*********************************************************************
+ * @fn      DVP_Mode
+ *
+ * @brief   DVP mode
+ *
+ * @param   s - data bit width
+ *             RB_DVP_D8_MOD
+ *             RB_DVP_D10_MOD
+ *             RB_DVP_D12_MOD
+ *          i - interrupt type
+ *             Video_Mode
+ *             JPEG_Mode
+ *
+ * @return  none
+ */
+void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i)
+{
+    DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD;
+
+    if(s)
+    {
+        DVP->CR0 |= s;
+    }
+    else
+    {
+        DVP->CR0 &= ~(3 << 4);
+    }
+
+    if(i)
+    {
+        DVP->CR0 |= RB_DVP_JPEG;
+    }
+    else
+    {
+        DVP->CR0 &= ~RB_DVP_JPEG;
+    }
+}
+
+/*********************************************************************
+ * @fn      DVP_Cfg
+ *
+ * @brief   DVP configuration
+ *
+ * @param   s - DMA enable control
+ *            DVP_DMA_Enable
+ *            DVP_DMA_Disable
+ *          i - DVP all clear
+ *            DVP_FLAG_FIFO_RESET_Enable
+ *            DVP_FLAG_FIFO_RESET_Disable
+ *          j - receive reset enable
+ *            DVP_RX_RESET_Enable
+ *            DVP_RX_RESET_Disable
+ *
+ * @return  none
+ */
+void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j)
+{
+    switch(s)
+    {
+        case DVP_DMA_Enable:
+            DVP->CR1 |= RB_DVP_DMA_EN;
+            break;
+        case DVP_DMA_Disable:
+            DVP->CR1 &= ~RB_DVP_DMA_EN;
+            break;
+        default:
+            break;
+    }
+
+    switch(i)
+    {
+        case DVP_RX_RESET_Enable:
+            DVP->CR1 |= RB_DVP_ALL_CLR;
+            break;
+        case DVP_RX_RESET_Disable:
+            DVP->CR1 &= ~RB_DVP_ALL_CLR;
+            break;
+        default:
+            break;
+    }
+
+    switch(j)
+    {
+        case DVP_RX_RESET_Enable:
+            DVP->CR1 |= RB_DVP_RCV_CLR;
+            break;
+        case DVP_RX_RESET_Disable:
+            DVP->CR1 &= ~RB_DVP_RCV_CLR;
+            break;
+        default:
+            break;
+    }
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_exti.c

@@ -0,0 +1,180 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_exti.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the EXTI firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+***************************************************************************************/
+#include "ch32v30x_exti.h"
+
+/* No interrupt selected */
+#define EXTI_LINENONE    ((uint32_t)0x00000)
+
+/*********************************************************************
+ * @fn      EXTI_DeInit
+ *
+ * @brief   Deinitializes the EXTI peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none.
+ */
+void EXTI_DeInit(void)
+{
+    EXTI->INTENR = 0x00000000;
+    EXTI->EVENR = 0x00000000;
+    EXTI->RTENR = 0x00000000;
+    EXTI->FTENR = 0x00000000;
+    EXTI->INTFR = 0x000FFFFF;
+}
+
+/*********************************************************************
+ * @fn      EXTI_Init
+ *
+ * @brief   Initializes the EXTI peripheral according to the specified
+ *        parameters in the EXTI_InitStruct.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    uint32_t tmp = 0;
+
+    tmp = (uint32_t)EXTI_BASE;
+    if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+    {
+        EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
+        if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+        {
+            EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            tmp = (uint32_t)EXTI_BASE;
+            tmp += EXTI_InitStruct->EXTI_Trigger;
+            *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/*********************************************************************
+ * @fn      EXTI_StructInit
+ *
+ * @brief   Fills each EXTI_InitStruct member with its reset value.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+    EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GenerateSWInterrupt
+ *
+ * @brief   Generates a Software interrupt.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none.
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+    EXTI->SWIEVR |= EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetFlagStatus
+ *
+ * @brief   Checks whether the specified EXTI line flag is set or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+    FlagStatus bitstatus = RESET;
+    if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearFlag
+ *
+ * @brief   Clears the EXTI's line pending flags.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetITStatus
+ *
+ * @brief   Checks whether the specified EXTI line is asserted or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = EXTI->INTENR & EXTI_Line;
+    if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearITPendingBit
+ *
+ * @brief   Clears the EXTI's line pending bits.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}

Ubiquitous/XiZi/board/ch32v307vct6/third_party_driver/Peripheral/src/ch32v30x_flash.c

@@ -0,0 +1,968 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_flash.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the FLASH firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+***************************************************************************************/
+#include "ch32v30x_flash.h"
+
+/* Flash Control Register bits */
+#define CR_PG_Set                  ((uint32_t)0x00000001)
+#define CR_PG_Reset                ((uint32_t)0x00001FFE)
+#define CR_PER_Set                 ((uint32_t)0x00000002)
+#define CR_PER_Reset               ((uint32_t)0x00001FFD)
+#define CR_MER_Set                 ((uint32_t)0x00000004)
+#define CR_MER_Reset               ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set               ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset             ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set               ((uint32_t)0x00000020)
+#define CR_OPTER_Reset             ((uint32_t)0x00001FDF)
+#define CR_STRT_Set                ((uint32_t)0x00000040)
+#define CR_LOCK_Set                ((uint32_t)0x00000080)
+#define CR_FAST_LOCK_Set           ((uint32_t)0x00008000)
+#define CR_PAGE_PG                 ((uint32_t)0x00010000)
+#define CR_PAGE_ER                 ((uint32_t)0x00020000)
+#define CR_BER32                   ((uint32_t)0x00040000)
+#define CR_BER64                   ((uint32_t)0x00080000)
+#define CR_PG_STRT                 ((uint32_t)0x00200000)
+
+/* FLASH Status Register bits */
+#define SR_BSY                     ((uint32_t)0x00000001)
+#define SR_WR_BSY                  ((uint32_t)0x00000002)
+#define SR_WRPRTERR                ((uint32_t)0x00000010)
+#define SR_EOP                     ((uint32_t)0x00000020)
+
+/* FLASH Mask */
+#define RDPRT_Mask                 ((uint32_t)0x00000002)
+#define WRP0_Mask                  ((uint32_t)0x000000FF)
+#define WRP1_Mask                  ((uint32_t)0x0000FF00)
+#define WRP2_Mask                  ((uint32_t)0x00FF0000)
+#define WRP3_Mask                  ((uint32_t)0xFF000000)
+#define OB_USER_BFB2               ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key                    ((uint16_t)0x00A5)
+#define FLASH_KEY1                 ((uint32_t)0x45670123)
+#define FLASH_KEY2                 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS    ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout               ((uint32_t)0x000B0000)
+#define ProgramTimeout             ((uint32_t)0x00005000)
+
+/*********************************************************************
+ * @fn      FLASH_Unlock
+ *
+ * @brief   Unlocks the FLASH Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_Unlock(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UnlockBank1
+ *
+ * @brief   Unlocks the FLASH Bank1 Program Erase Controller.
+ *          equivalent to FLASH_Unlock function.
+ *
+ * @return  none
+ */
+void FLASH_UnlockBank1(void)
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock
+ *
+ * @brief   Locks the FLASH Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_Lock(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_LockBank1
+ *
+ * @brief   Locks the FLASH Bank1 Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_LockBank1(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage
+ *
+ * @brief   Erases a specified FLASH page(page size 4KB).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PER_Set;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_PER_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseAllPages
+ *
+ * @brief   Erases all FLASH pages.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseAllBank1Pages
+ *
+ * @brief   Erases all Bank1 FLASH pages.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseOptionBytes
+ *
+ * @brief   Erases the FLASH option bytes.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+    uint16_t     rdptmp = RDP_Key;
+    uint32_t     Address = 0x1FFFF800;
+    __IO uint8_t i;
+
+    FLASH_Status status = FLASH_COMPLETE;
+    if(FLASH_GetReadOutProtectionStatus() != RESET)
+    {
+        rdptmp = 0x00;
+    }
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            OB->RDPR = (uint16_t)rdptmp;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+
+        /* Write 0xFF */
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Address + 2 * i) = 0x00FF;
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramWord
+ *
+ * @brief   Programs a word at a specified address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+    FLASH_Status  status = FLASH_COMPLETE;
+    __IO uint32_t tmp = 0;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+
+        *(__IO uint16_t *)Address = (uint16_t)Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            tmp = Address + 2;
+            *(__IO uint16_t *)tmp = Data >> 16;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+        else
+        {
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramHalfWord
+ *
+ * @brief   Programs a half word at a specified address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+        *(__IO uint16_t *)Address = Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        FLASH->CTLR &= CR_PG_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramOptionByteData
+ *
+ * @brief   Programs a half word at a specified Option Byte Data address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data));
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EnableWriteProtection
+ *
+ * @brief   Write protects the desired sectors
+ *
+ * @param   FLASH_Sectors - specifies the address of the pages to be write protected.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors)
+{
+    uint16_t     WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    FLASH_Sectors = (uint32_t)(~FLASH_Sectors);
+    WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask);
+    WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8);
+    WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16);
+    WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24);
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[4] = WRP0_Data;
+        pbuf[5] = WRP1_Data;
+        pbuf[6] = WRP2_Data;
+        pbuf[7] = WRP3_Data;
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ReadOutProtection
+ *
+ * @brief   Enables or disables the read out protection.
+ *
+ * @param   Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        if(NewState == DISABLE)
+            pbuf[0] = 0x5AA5;
+        else
+            pbuf[0] = 0x00FF;
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UserOptionByteConfig
+ *
+ * @brief   Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY.
+ *
+ * @param   OB_IWDG - Selects the IWDG mode
+ *            OB_IWDG_SW - Software IWDG selected
+ *            OB_IWDG_HW - Hardware IWDG selected
+ *          OB_STOP - Reset event when entering STOP mode.
+ *            OB_STOP_NoRST - No reset generated when entering in STOP
+ *            OB_STOP_RST - Reset generated when entering in STOP
+ *          OB_STDBY - Reset event when entering Standby mode.
+ *            OB_STDBY_NoRST - No reset generated when entering in STANDBY
+ *            OB_STDBY_RST - Reset generated when entering in STANDBY
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    FLASH->OBKEYR = FLASH_KEY1;
+    FLASH->OBKEYR = FLASH_KEY2;
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetUserOptionByte
+ *
+ * @brief   Returns the FLASH User Option Bytes values.
+ *
+ * @return  The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ *        and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+    return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetWriteProtectionOptionByte
+ *
+ * @brief   Returns the FLASH Write Protection Option Bytes Register value.
+ *
+ * @return  The FLASH Write Protection Option Bytes Register value.
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+    return (uint32_t)(FLASH->WPR);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetReadOutProtectionStatus
+ *
+ * @brief   Checks whether the FLASH Read Out Protection Status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ITConfig
+ *
+ * @brief   Enables or disables the specified FLASH interrupts.
+ *
+ * @param   FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled.
+ *            FLASH_IT_ERROR - FLASH Error Interrupt
+ *            FLASH_IT_EOP - FLASH end of operation Interrupt
+ *          NewState - new state of the specified Flash interrupts(ENABLE or DISABLE).
+ *
+ * @return  FLASH Prefetch Buffer Status (SET or RESET).
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        FLASH->CTLR |= FLASH_IT;
+    }
+    else
+    {
+        FLASH->CTLR &= ~(uint32_t)FLASH_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetFlagStatus
+ *
+ * @brief   Checks whether the specified FLASH flag is set or not.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flag to check.
+ *            FLASH_FLAG_BSY - FLASH Busy flag
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *            FLASH_FLAG_OPTERR - FLASH Option Byte error flag
+ *
+ * @return  The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+    {
+        if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ClearFlag
+ *
+ * @brief   Clears the FLASH's pending flags.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flags to clear.
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *
+ * @return  none
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+    FLASH->STATR = FLASH_FLAG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetStatus
+ *
+ * @brief   Returns the FLASH Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetBank1Status
+ *
+ * @brief   Returns the FLASH Bank1 Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastOperation
+ *
+ * @brief   Waits for a Flash operation to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_BUSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastBank1Operation
+ *
+ * @brief   Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Unlock_Fast(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast program mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock_Fast
+ *
+ * @brief   Locks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Lock_Fast(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage_Fast
+ *
+ * @brief   Erases a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_ErasePage_Fast(uint32_t Page_Address)
+{
+    Page_Address &= 0xFFFFFF00;
+
+    FLASH->CTLR |= CR_PAGE_ER;
+    FLASH->ADDR = Page_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_PAGE_ER;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseBlock_32K_Fast
+ *
+ * @brief   Erases a specified FLASH Block (1Block = 32KByte).
+ *
+ * @param   Block_Address - The block address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
+{
+    Block_Address &= 0xFFFF8000;
+
+    FLASH->CTLR |= CR_BER32;
+    FLASH->ADDR = Block_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_BER32;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseBlock_64K_Fast
+ *
+ * @brief   Erases a specified FLASH Block (1Block = 64KByte).
+ *
+ * @param   Block_Address - The block address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address)
+{
+    Block_Address &= 0xFFFF0000;
+
+    FLASH->CTLR |= CR_BER64;
+    FLASH->ADDR = Block_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_BER64;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramPage_Fast
+ *
+ * @brief   Program a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be programed.
+ *
+ * @return  none
+ */
+void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf)
+{
+    uint8_t size = 64;
+
+    Page_Address &= 0xFFFFFF00;
+
+    FLASH->CTLR |= CR_PAGE_PG;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    while(FLASH->STATR & SR_WR_BSY)
+        ;
+
+    while(size)
+    {
+        *(uint32_t *)Page_Address = *(uint32_t *)pbuf;
+        Page_Address += 4;
+        pbuf += 1;
+        size -= 1;
+        while(FLASH->STATR & SR_WR_BSY)
+            ;
+    }
+
+    FLASH->CTLR |= CR_PG_STRT;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_PAGE_PG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Enhance_Mode
+ *
+ * @brief   Read FLASH Enhance Mode
+ *
+ * @param   FLASH_Enhance_CLK -
+ *            FLASH_Enhance_SYSTEM_HALF - System clock/2
+ *            FLASH_Enhance_SYSTEM - System clock
+ *          Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState)
+{
+    FLASH->CTLR &= ~(1 << 25);
+    FLASH->CTLR |= FLASH_Enhance_CLK;
+
+    if(NewState)
+    {
+        FLASH->CTLR |= (1 << 24);
+    }
+    else
+    {
+        FLASH->CTLR &= ~(1 << 24);
+        FLASH->CTLR |= (1 << 22);
+    }
+}