modify XiUOS DIR : (1.add plc_demo in APP_Framework/control_app; 2.add industrial_network、industrial_fieldbus and industrial_wlan; 3.add XiZi_AIoT and modify XiZi as XiZi_IIoT.)

2022-09-27 20:39:52 +08:00
parent dbca22a1a6
commit e14fa6ff8e
5009 changed files with 1019 additions and 3084 deletions
@@ -0,0 +1,5 @@
+SRC_DIR := NuClockConfig NuPinConfig
+
+SRC_FILES := nu_clk.c nu_gpio.c nu_sys.c nu_uart.c system_M2354.c
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,3 @@
+SRC_FILES := nutool_modclkcfg.c
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,27 @@
+/****************************************************************************
+ * @file     nutool_clkcfg.h
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32
+ * @brief    NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_CLKCFG_H__
+#define __NUTOOL_CLKCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#undef  __HXT
+#define __HXT         (12000000UL)  /*!< High Speed External Crystal Clock Frequency */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_CLKCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
@@ -0,0 +1,35 @@
+/****************************************************************************
+ * @file     nutool_modclkcfg.cfg
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32 
+ * @brief    NuMicro clock config file
+ *
+ * @note Please do not modify this file.
+ *       Otherwise, it may not be loaded successfully.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+MCU:M2354KJFAE(LQFP128)
+Reg:CLKDIV0 = 0x00000010
+Reg:CLKDIV1 = 0x00000000
+Reg:CLKDIV4 = 0x00000000
+Reg:PCLKDIV = 0x00000000
+Reg:CLKSEL0 = 0x0020011A
+Reg:CLKSEL1 = 0xB000009D
+Reg:CLKSEL2 = 0x00002BAB
+Reg:CLKSEL3 = 0x00020000
+Reg:PWRCTL = 0x00240007
+Reg:AHBCLK = 0xFFFFFFFF
+Reg:APBCLK0 = 0xFFFFFFFF
+Reg:APBCLK1 = 0xFFFFFFFF
+Reg:PLLCTL = 0x00000206
+Reg:CLKOCTL = 0x00000000
+Reg:SYST_CTRL = 0x00000005
+Reg:RTC_LXTCTL = 0x0000000E
+LXT:32768
+HXT:12000000
+PLL:96000000
+Step:4
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * @file     nutool_modclkcfg.h
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32
+ * @brief    NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_MODCLKCFG_H__
+#define __NUTOOL_MODCLKCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+void nutool_modclkcfg_init_acmp01(void);
+void nutool_modclkcfg_deinit_acmp01(void);
+void nutool_modclkcfg_init_bpwm0(void);
+void nutool_modclkcfg_deinit_bpwm0(void);
+void nutool_modclkcfg_init_bpwm1(void);
+void nutool_modclkcfg_deinit_bpwm1(void);
+void nutool_modclkcfg_init_can0(void);
+void nutool_modclkcfg_deinit_can0(void);
+void nutool_modclkcfg_init_crc(void);
+void nutool_modclkcfg_deinit_crc(void);
+void nutool_modclkcfg_init_crpt(void);
+void nutool_modclkcfg_deinit_crpt(void);
+void nutool_modclkcfg_init_dac(void);
+void nutool_modclkcfg_deinit_dac(void);
+void nutool_modclkcfg_init_eadc(void);
+void nutool_modclkcfg_deinit_eadc(void);
+void nutool_modclkcfg_init_ebi(void);
+void nutool_modclkcfg_deinit_ebi(void);
+void nutool_modclkcfg_init_ecap0(void);
+void nutool_modclkcfg_deinit_ecap0(void);
+void nutool_modclkcfg_init_ecap1(void);
+void nutool_modclkcfg_deinit_ecap1(void);
+void nutool_modclkcfg_init_epwm0(void);
+void nutool_modclkcfg_deinit_epwm0(void);
+void nutool_modclkcfg_init_epwm1(void);
+void nutool_modclkcfg_deinit_epwm1(void);
+void nutool_modclkcfg_init_ewdt(void);
+void nutool_modclkcfg_deinit_ewdt(void);
+void nutool_modclkcfg_init_ewwdt(void);
+void nutool_modclkcfg_deinit_ewwdt(void);
+void nutool_modclkcfg_init_exst(void);
+void nutool_modclkcfg_deinit_exst(void);
+void nutool_modclkcfg_init_fmcidle(void);
+void nutool_modclkcfg_deinit_fmcidle(void);
+void nutool_modclkcfg_init_gpa(void);
+void nutool_modclkcfg_deinit_gpa(void);
+void nutool_modclkcfg_init_gpb(void);
+void nutool_modclkcfg_deinit_gpb(void);
+void nutool_modclkcfg_init_gpc(void);
+void nutool_modclkcfg_deinit_gpc(void);
+void nutool_modclkcfg_init_gpd(void);
+void nutool_modclkcfg_deinit_gpd(void);
+void nutool_modclkcfg_init_gpe(void);
+void nutool_modclkcfg_deinit_gpe(void);
+void nutool_modclkcfg_init_gpf(void);
+void nutool_modclkcfg_deinit_gpf(void);
+void nutool_modclkcfg_init_gpg(void);
+void nutool_modclkcfg_deinit_gpg(void);
+void nutool_modclkcfg_init_gph(void);
+void nutool_modclkcfg_deinit_gph(void);
+void nutool_modclkcfg_init_i2c0(void);
+void nutool_modclkcfg_deinit_i2c0(void);
+void nutool_modclkcfg_init_i2c1(void);
+void nutool_modclkcfg_deinit_i2c1(void);
+void nutool_modclkcfg_init_i2c2(void);
+void nutool_modclkcfg_deinit_i2c2(void);
+void nutool_modclkcfg_init_i2s0(void);
+void nutool_modclkcfg_deinit_i2s0(void);
+void nutool_modclkcfg_init_isp(void);
+void nutool_modclkcfg_deinit_isp(void);
+void nutool_modclkcfg_init_ks(void);
+void nutool_modclkcfg_deinit_ks(void);
+void nutool_modclkcfg_init_lcd(void);
+void nutool_modclkcfg_deinit_lcd(void);
+void nutool_modclkcfg_init_lcdcp(void);
+void nutool_modclkcfg_deinit_lcdcp(void);
+void nutool_modclkcfg_init_otg(void);
+void nutool_modclkcfg_deinit_otg(void);
+void nutool_modclkcfg_init_pdma0(void);
+void nutool_modclkcfg_deinit_pdma0(void);
+void nutool_modclkcfg_init_pdma1(void);
+void nutool_modclkcfg_deinit_pdma1(void);
+void nutool_modclkcfg_init_qei0(void);
+void nutool_modclkcfg_deinit_qei0(void);
+void nutool_modclkcfg_init_qei1(void);
+void nutool_modclkcfg_deinit_qei1(void);
+void nutool_modclkcfg_init_qspi0(void);
+void nutool_modclkcfg_deinit_qspi0(void);
+void nutool_modclkcfg_init_rtc(void);
+void nutool_modclkcfg_deinit_rtc(void);
+void nutool_modclkcfg_init_sc0(void);
+void nutool_modclkcfg_deinit_sc0(void);
+void nutool_modclkcfg_init_sc1(void);
+void nutool_modclkcfg_deinit_sc1(void);
+void nutool_modclkcfg_init_sc2(void);
+void nutool_modclkcfg_deinit_sc2(void);
+void nutool_modclkcfg_init_sdh0(void);
+void nutool_modclkcfg_deinit_sdh0(void);
+void nutool_modclkcfg_init_spi0(void);
+void nutool_modclkcfg_deinit_spi0(void);
+void nutool_modclkcfg_init_spi1(void);
+void nutool_modclkcfg_deinit_spi1(void);
+void nutool_modclkcfg_init_spi2(void);
+void nutool_modclkcfg_deinit_spi2(void);
+void nutool_modclkcfg_init_spi3(void);
+void nutool_modclkcfg_deinit_spi3(void);
+void nutool_modclkcfg_init_sram0(void);
+void nutool_modclkcfg_deinit_sram0(void);
+void nutool_modclkcfg_init_sram1(void);
+void nutool_modclkcfg_deinit_sram1(void);
+void nutool_modclkcfg_init_sram2(void);
+void nutool_modclkcfg_deinit_sram2(void);
+void nutool_modclkcfg_init_systick(void);
+void nutool_modclkcfg_deinit_systick(void);
+void nutool_modclkcfg_init_tamper(void);
+void nutool_modclkcfg_deinit_tamper(void);
+void nutool_modclkcfg_init_tmr0(void);
+void nutool_modclkcfg_deinit_tmr0(void);
+void nutool_modclkcfg_init_tmr1(void);
+void nutool_modclkcfg_deinit_tmr1(void);
+void nutool_modclkcfg_init_tmr2(void);
+void nutool_modclkcfg_deinit_tmr2(void);
+void nutool_modclkcfg_init_tmr3(void);
+void nutool_modclkcfg_deinit_tmr3(void);
+void nutool_modclkcfg_init_tmr4(void);
+void nutool_modclkcfg_deinit_tmr4(void);
+void nutool_modclkcfg_init_tmr5(void);
+void nutool_modclkcfg_deinit_tmr5(void);
+void nutool_modclkcfg_init_trace(void);
+void nutool_modclkcfg_deinit_trace(void);
+void nutool_modclkcfg_init_trng(void);
+void nutool_modclkcfg_deinit_trng(void);
+void nutool_modclkcfg_init_uart0(void);
+void nutool_modclkcfg_deinit_uart0(void);
+void nutool_modclkcfg_init_uart1(void);
+void nutool_modclkcfg_deinit_uart1(void);
+void nutool_modclkcfg_init_uart2(void);
+void nutool_modclkcfg_deinit_uart2(void);
+void nutool_modclkcfg_init_uart3(void);
+void nutool_modclkcfg_deinit_uart3(void);
+void nutool_modclkcfg_init_uart4(void);
+void nutool_modclkcfg_deinit_uart4(void);
+void nutool_modclkcfg_init_uart5(void);
+void nutool_modclkcfg_deinit_uart5(void);
+void nutool_modclkcfg_init_usbd(void);
+void nutool_modclkcfg_deinit_usbd(void);
+void nutool_modclkcfg_init_usbh(void);
+void nutool_modclkcfg_deinit_usbh(void);
+void nutool_modclkcfg_init_usci0(void);
+void nutool_modclkcfg_deinit_usci0(void);
+void nutool_modclkcfg_init_usci1(void);
+void nutool_modclkcfg_deinit_usci1(void);
+void nutool_modclkcfg_init_wdt(void);
+void nutool_modclkcfg_deinit_wdt(void);
+void nutool_modclkcfg_init_wwdt(void);
+void nutool_modclkcfg_deinit_wwdt(void);
+void nutool_modclkcfg_init_base(void);
+void nutool_modclkcfg_init(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_MODCLKCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
@@ -0,0 +1,3 @@
+SRC_FILES := nutool_pincfg.c
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,434 @@
+/****************************************************************************
+ * @file     nutool_pincfg.c
+ * @version  V1.21
+ * @Date     2020/11/11-12:06:36
+ * @brief    NuMicro generated code file
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+/********************
+MCU:M2354KJFAE(LQFP128)
+Pin Configuration:
+Pin1:SD0_DAT3
+Pin2:SD0_DAT2
+Pin3:SD0_DAT1
+Pin4:SD0_DAT0
+Pin5:EPWM1_CH0
+Pin6:EPWM1_CH1
+Pin7:EPWM1_CH2
+Pin8:EPWM1_CH3
+Pin9:SD0_CLK
+Pin10:SD0_CMD
+Pin15:UART1_TXD
+Pin16:UART1_RXD
+Pin21:I2C1_SCL
+Pin22:I2C1_SDA
+Pin25:I2S0_BCLK
+Pin26:I2S0_MCLK
+Pin27:I2S0_DI
+Pin28:I2S0_DO
+Pin29:I2S0_LRCK
+Pin48:UART4_TXD
+Pin49:UART4_RXD
+Pin50:UART0_TXD
+Pin51:UART0_RXD
+Pin57:SPI0_SS
+Pin58:SPI0_CLK
+Pin59:SPI0_MISO
+Pin60:SPI0_MOSI
+Pin65:ICE_DAT
+Pin66:ICE_CLK
+Pin73:EPWM1_CH4
+Pin74:EPWM1_CH5
+Pin93:USB_VBUS
+Pin94:USB_D-
+Pin95:USB_D+
+Pin96:USB_OTG_ID
+Pin97:EPWM0_CH0
+Pin98:EPWM0_CH1
+Pin105:SPI1_MISO
+Pin106:SPI1_MOSI
+Pin107:SPI1_CLK
+Pin108:SPI1_SS
+Pin109:PH.10
+Pin116:USB_VBUS_EN
+Pin117:USB_VBUS_ST
+Pin119:SD0_nCD
+Pin123:EADC0_CH11
+Pin124:EADC0_CH10
+Pin125:EADC0_CH9
+Pin126:EADC0_CH8
+Pin127:EADC0_CH7
+Pin128:EADC0_CH6
+********************/
+
+#include "M2354.h"
+
+void nutool_pincfg_init_eadc0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk);
+    SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB11MFP_EADC0_CH11 | SYS_GPB_MFPH_PB10MFP_EADC0_CH10 | SYS_GPB_MFPH_PB9MFP_EADC0_CH9 | SYS_GPB_MFPH_PB8MFP_EADC0_CH8);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk);
+    SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB7MFP_EADC0_CH7 | SYS_GPB_MFPL_PB6MFP_EADC0_CH6);
+
+    /* Disable digital path on these EADC pins */
+    GPIO_DISABLE_DIGITAL_PATH(PB, BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11);
+
+    return;
+}
+
+void nutool_pincfg_deinit_eadc0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk);
+
+    /* Enable digital path on these EADC pins */
+    GPIO_ENABLE_DIGITAL_PATH(PB, BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11);
+
+    return;
+}
+
+void nutool_pincfg_init_epwm0(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk);
+    SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 | SYS_GPE_MFPL_PE6MFP_EPWM0_CH1);
+
+    return;
+}
+
+void nutool_pincfg_deinit_epwm0(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_epwm1(void)
+{
+    SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk);
+#if !defined(BOARD_USING_LCD_ILI9341)
+    SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 | SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 | SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 | SYS_GPC_MFPH_PC9MFP_EPWM1_CH3);
+#else
+    SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 | SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 | SYS_GPC_MFPH_PC9MFP_EPWM1_CH3);
+#endif
+
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk);
+    SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 | SYS_GPC_MFPL_PC0MFP_EPWM1_CH5);
+
+    return;
+}
+
+void nutool_pincfg_deinit_epwm1(void)
+{
+    SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk);
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_i2c1(void)
+{
+    SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk);
+    SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG3MFP_I2C1_SDA | SYS_GPG_MFPL_PG2MFP_I2C1_SCL);
+
+    return;
+}
+
+void nutool_pincfg_deinit_i2c1(void)
+{
+    SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_i2s0(void)
+{
+    SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk);
+    SYS->GPF_MFPH |= (SYS_GPF_MFPH_PF10MFP_I2S0_BCLK | SYS_GPF_MFPH_PF9MFP_I2S0_MCLK | SYS_GPF_MFPH_PF8MFP_I2S0_DI);
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk);
+    SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF7MFP_I2S0_DO | SYS_GPF_MFPL_PF6MFP_I2S0_LRCK);
+
+    return;
+}
+
+void nutool_pincfg_deinit_i2s0(void)
+{
+    SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk);
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_ice(void)
+{
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk);
+    SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF1MFP_ICE_CLK | SYS_GPF_MFPL_PF0MFP_ICE_DAT);
+
+    return;
+}
+
+void nutool_pincfg_deinit_ice(void)
+{
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_ph(void)
+{
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH10MFP_Msk);
+    SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH10MFP_GPIO);
+
+    return;
+}
+
+void nutool_pincfg_deinit_ph(void)
+{
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH10MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_sd0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk);
+    SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB12MFP_SD0_nCD);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk);
+    SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB5MFP_SD0_DAT3 | SYS_GPB_MFPL_PB4MFP_SD0_DAT2 | SYS_GPB_MFPL_PB3MFP_SD0_DAT1 | SYS_GPB_MFPL_PB2MFP_SD0_DAT0 | SYS_GPB_MFPL_PB1MFP_SD0_CLK | SYS_GPB_MFPL_PB0MFP_SD0_CMD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_sd0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_spi0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk);
+    SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_SPI0_SS | SYS_GPA_MFPL_PA2MFP_SPI0_CLK | SYS_GPA_MFPL_PA1MFP_SPI0_MISO | SYS_GPA_MFPL_PA0MFP_SPI0_MOSI);
+
+    return;
+}
+
+void nutool_pincfg_deinit_spi0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_spi1(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk);
+    SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE1MFP_SPI1_MISO | SYS_GPE_MFPL_PE0MFP_SPI1_MOSI);
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk);
+    SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH9MFP_SPI1_SS | SYS_GPH_MFPH_PH8MFP_SPI1_CLK);
+
+    return;
+}
+
+void nutool_pincfg_deinit_spi1(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk);
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_uart0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk);
+    SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA7MFP_UART0_TXD | SYS_GPA_MFPL_PA6MFP_UART0_RXD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_uart0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_uart1(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk);
+    SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA9MFP_UART1_TXD | SYS_GPA_MFPH_PA8MFP_UART1_RXD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_uart1(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_uart4(void)
+{
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk);
+    SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC7MFP_UART4_TXD | SYS_GPC_MFPL_PC6MFP_UART4_RXD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_uart4(void)
+{
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_usb(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk);
+    SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA15MFP_USB_OTG_ID | SYS_GPA_MFPH_PA14MFP_USB_D_P | SYS_GPA_MFPH_PA13MFP_USB_D_N | SYS_GPA_MFPH_PA12MFP_USB_VBUS);
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk);
+    SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN | SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST);
+
+    return;
+}
+
+void nutool_pincfg_deinit_usb(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk);
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk);
+
+    return;
+}
+
+
+void pincfg_init_slcd(void)
+{
+    /*
+        Summary of LCD pin usage:
+            COM 0~5   : PC.0, PC.1, PC.2, PC.3, PC.4, PC.5
+            COM 6~7   : PD.8, PD.9
+            SEG 0     : PD.14
+            SEG 1~4   : PH.11, PH.10, PH.9, PH.8
+            SEG 5~12  : PE.0, PE.1, PE.2, PE.3, PE.4, PE.5, PE.6, PE.7
+            SEG 13~14 : PD.6, PD.7
+            SEG 15~21 : PG.15, PG.14, PG.13, PG.12, PG.11, PG.10, PG.9
+            SEG 22~23 : PE.15, PE.14
+            SEG 24~29 : PA.0, PA.1, PA.2, PA.3, PA.4, PA.5
+            SEG 30~32 : PE.10, PE.9, PE.8
+            SEG 33~36 : PH.7, PH.6, PH.5, PH.4
+            SEG 37~39 : PG.4, PG.3, PG.2
+    */
+
+    /* COM 0~5 */
+    SYS->GPC_MFPL = (SYS->GPC_MFPL &
+                     ~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk |
+                       SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC5MFP_Msk)) |
+                    (LCD_COM0_PC0 | LCD_COM1_PC1 | LCD_COM2_PC2 | LCD_COM3_PC3 | LCD_COM4_PC4 | LCD_COM5_PC5);
+    /* COM 6~7 */
+    SYS->GPD_MFPH = (SYS->GPD_MFPH & ~(SYS_GPD_MFPH_PD8MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk)) |
+                    (LCD_COM6_PD8 | LCD_COM7_PD9);
+
+    /* SEG 0 */
+    SYS->GPD_MFPH = (SYS->GPD_MFPH & ~SYS_GPD_MFPH_PD14MFP_Msk) | LCD_SEG0_PD14;
+    /* SEG 1~4 */
+    SYS->GPH_MFPH = (SYS->GPH_MFPH & ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk | SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk)) |
+                    (LCD_SEG1_PH11 | LCD_SEG2_PH10 | LCD_SEG3_PH9 | LCD_SEG4_PH8);
+    /* SEG 5~12 */
+    SYS->GPE_MFPL = (SYS->GPE_MFPL &
+                     ~(SYS_GPE_MFPL_PE0MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk |
+                       SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE7MFP_Msk)) |
+                    (LCD_SEG5_PE0 | LCD_SEG6_PE1 | LCD_SEG7_PE2 | LCD_SEG8_PE3 |
+                     LCD_SEG9_PE4 | LCD_SEG10_PE5 | LCD_SEG11_PE6 | LCD_SEG12_PE7);
+    /* SEG 13~14 */
+    SYS->GPD_MFPL = (SYS->GPD_MFPL & ~(SYS_GPD_MFPL_PD6MFP_Msk | SYS_GPD_MFPL_PD7MFP_Msk)) | (LCD_SEG13_PD6 | LCD_SEG14_PD7);
+    /* SEG 15~21 */
+    SYS->GPG_MFPH = (SYS->GPG_MFPH &
+                     ~(SYS_GPG_MFPH_PG15MFP_Msk | SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk |
+                       SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk)) |
+                    (LCD_SEG15_PG15 | LCD_SEG16_PG14 | LCD_SEG17_PG13 | LCD_SEG18_PG12 |
+                     LCD_SEG19_PG11 | LCD_SEG20_PG10 | LCD_SEG21_PG9);
+    /* SEG 22~23 */
+    SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk)) | (LCD_SEG22_PE15 | LCD_SEG23_PE14);
+    /* SEG 24~29 */
+    SYS->GPA_MFPL = (SYS->GPA_MFPL &
+                     ~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk |
+                       SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk)) |
+                    (LCD_SEG24_PA0 | LCD_SEG25_PA1 | LCD_SEG26_PA2 | LCD_SEG27_PA3 | LCD_SEG28_PA4 | LCD_SEG29_PA5);
+    /* SEG 30~32 */
+    SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk)) |
+                    (LCD_SEG30_PE10 | LCD_SEG31_PE9 | LCD_SEG32_PE8);
+    /* SEG 33~36 */
+    SYS->GPH_MFPL = (SYS->GPH_MFPL & ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk)) |
+                    (LCD_SEG33_PH7 | LCD_SEG34_PH6 | LCD_SEG35_PH5 | LCD_SEG36_PH4);
+    /* SEG 37~39 */
+    SYS->GPG_MFPL = (SYS->GPG_MFPL & ~(SYS_GPG_MFPL_PG4MFP_Msk | SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk)) |
+                    (LCD_SEG37_PG4 | LCD_SEG38_PG3 | LCD_SEG39_PG2);
+}
+
+
+void nutool_pincfg_init(void)
+{
+    //SYS->GPA_MFPH = 0xEEEE0077;
+    //SYS->GPA_MFPL = 0x77004444;
+    //SYS->GPB_MFPH = 0xEF091111;
+    //SYS->GPB_MFPL = 0x11333333;
+    //SYS->GPC_MFPH = 0x000CCCC0;
+    //SYS->GPC_MFPL = 0x550000CC;
+    //SYS->GPD_MFPH = 0x00000000;
+    //SYS->GPD_MFPL = 0x00000000;
+    //SYS->GPE_MFPH = 0x00000000;
+    //SYS->GPE_MFPL = 0xCC000066;
+    //SYS->GPF_MFPH = 0x00000444;
+    //SYS->GPF_MFPL = 0x440000EE;
+    //SYS->GPG_MFPH = 0x00000000;
+    //SYS->GPG_MFPL = 0x00005500;
+    //SYS->GPH_MFPH = 0x00000066;
+    //SYS->GPH_MFPL = 0x00000000;
+
+    nutool_pincfg_init_eadc0();
+    nutool_pincfg_init_epwm0();
+    nutool_pincfg_init_epwm1();
+    nutool_pincfg_init_i2c1();
+    nutool_pincfg_init_i2s0();
+    nutool_pincfg_init_ice();
+    nutool_pincfg_init_ph();
+    nutool_pincfg_init_sd0();
+    nutool_pincfg_init_spi0();
+    nutool_pincfg_init_spi1();
+    nutool_pincfg_init_uart0();
+#if !defined(BOARD_USING_LCD_ILI9341)
+    nutool_pincfg_init_uart1();
+#endif
+    nutool_pincfg_init_uart4();
+    nutool_pincfg_init_usb();
+
+#if defined(BSP_USING_SLCD)
+    pincfg_init_slcd();
+#endif
+    return;
+}
+
+void nutool_pincfg_deinit(void)
+{
+    nutool_pincfg_deinit_eadc0();
+    nutool_pincfg_deinit_epwm0();
+    nutool_pincfg_deinit_epwm1();
+    nutool_pincfg_deinit_i2c1();
+    nutool_pincfg_deinit_i2s0();
+    nutool_pincfg_deinit_ice();
+    nutool_pincfg_deinit_ph();
+    nutool_pincfg_deinit_sd0();
+    nutool_pincfg_deinit_spi0();
+    nutool_pincfg_deinit_spi1();
+    nutool_pincfg_deinit_uart0();
+    nutool_pincfg_deinit_uart1();
+    nutool_pincfg_deinit_uart4();
+    nutool_pincfg_deinit_usb();
+
+    return;
+}
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * @file     nutool_pincfg.cfg
+ * @version  V1.21
+ * @Date     2020/11/11-12:06:37 
+ * @brief    NuMicro config file
+ *
+ * @note Please do not modify this file.
+ *       Otherwise, it may not be loaded successfully.
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+MCU:M2354KJFAE(LQFP128)
+Pin1:SD0_DAT3
+Pin2:SD0_DAT2
+Pin3:SD0_DAT1
+Pin4:SD0_DAT0
+Pin5:EPWM1_CH0
+Pin6:EPWM1_CH1
+Pin7:EPWM1_CH2
+Pin8:EPWM1_CH3
+Pin9:SD0_CLK
+Pin10:SD0_CMD
+Pin11:VSS
+Pin12:VDD
+Pin13:PA.11
+Pin14:PA.10
+Pin15:UART1_TXD
+Pin16:UART1_RXD
+Pin17:PC.13
+Pin18:PD.12
+Pin19:PD.11
+Pin20:PD.10
+Pin21:I2C1_SCL
+Pin22:I2C1_SDA
+Pin23:PG.4
+Pin24:PF.11
+Pin25:I2S0_BCLK
+Pin26:I2S0_MCLK
+Pin27:I2S0_DI
+Pin28:I2S0_DO
+Pin29:I2S0_LRCK
+Pin30:VBAT
+Pin31:PF.5
+Pin32:PF.4
+Pin33:PH.4
+Pin34:PH.5
+Pin35:PH.6
+Pin36:PH.7
+Pin37:PF.3
+Pin38:PF.2
+Pin39:VSS
+Pin40:VDD
+Pin41:PE.8
+Pin42:PE.9
+Pin43:PE.10
+Pin44:PE.11
+Pin45:PE.12
+Pin46:PE.13
+Pin47:PC.8
+Pin48:UART4_TXD
+Pin49:UART4_RXD
+Pin50:UART0_TXD
+Pin51:UART0_RXD
+Pin52:VSS
+Pin53:VDD
+Pin54:LDO_CAP
+Pin55:PA.5
+Pin56:PA.4
+Pin57:SPI0_SS
+Pin58:SPI0_CLK
+Pin59:SPI0_MISO
+Pin60:SPI0_MOSI
+Pin61:VDDIO
+Pin62:PE.14
+Pin63:PE.15
+Pin64:nRESET
+Pin65:ICE_DAT
+Pin66:ICE_CLK
+Pin67:PD.9
+Pin68:PD.8
+Pin69:PC.5
+Pin70:PC.4
+Pin71:PC.3
+Pin72:PC.2
+Pin73:EPWM1_CH4
+Pin74:EPWM1_CH5
+Pin75:VSS
+Pin76:VDD
+Pin77:PG.9
+Pin78:PG.10
+Pin79:PG.11
+Pin80:PG.12
+Pin81:PG.13
+Pin82:PG.14
+Pin83:PG.15
+Pin84:PD.7
+Pin85:PD.6
+Pin86:PD.5
+Pin87:PD.4
+Pin88:PD.3
+Pin89:PD.2
+Pin90:PD.1
+Pin91:PD.0
+Pin92:VLCD
+Pin93:USB_VBUS
+Pin94:USB_D-
+Pin95:USB_D+
+Pin96:USB_OTG_ID
+Pin97:EPWM0_CH0
+Pin98:EPWM0_CH1
+Pin99:PE.5
+Pin100:PE.4
+Pin101:PE.3
+Pin102:PE.2
+Pin103:VSS
+Pin104:VDD
+Pin105:SPI1_MISO
+Pin106:SPI1_MOSI
+Pin107:SPI1_CLK
+Pin108:SPI1_SS
+Pin109:PH.10
+Pin110:PH.11
+Pin111:PD.14
+Pin112:VSS
+Pin113:Vsw
+Pin114:VDD
+Pin115:LDO_CAP
+Pin116:USB_VBUS_EN
+Pin117:USB_VBUS_ST
+Pin118:PB.13
+Pin119:SD0_nCD
+Pin120:AVDD
+Pin121:VREF
+Pin122:AVSS
+Pin123:EADC0_CH11
+Pin124:EADC0_CH10
+Pin125:EADC0_CH9
+Pin126:EADC0_CH8
+Pin127:EADC0_CH7
+Pin128:EADC0_CH6
+GPIOpin:108
+SYS->GPA_MFPH = 0xEEEE0077
+SYS->GPA_MFPL = 0x77004444
+SYS->GPB_MFPH = 0xEF091111
+SYS->GPB_MFPL = 0x11333333
+SYS->GPC_MFPH = 0x000CCCC0
+SYS->GPC_MFPL = 0x550000CC
+SYS->GPD_MFPH = 0x00000000
+SYS->GPD_MFPL = 0x00000000
+SYS->GPE_MFPH = 0x00000000
+SYS->GPE_MFPL = 0xCC000066
+SYS->GPF_MFPH = 0x00000444
+SYS->GPF_MFPL = 0x440000EE
+SYS->GPG_MFPH = 0x00000000
+SYS->GPG_MFPL = 0x00005500
+SYS->GPH_MFPH = 0x00000066
+SYS->GPH_MFPL = 0x00000000
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * @file     nutool_pincfg.h
+ * @version  V1.21
+ * @Date     2020/11/11-12:06:36
+ * @brief    NuMicro generated code file
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_PINCFG_H__
+#define __NUTOOL_PINCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+void nutool_pincfg_init_eadc0(void);
+void nutool_pincfg_deinit_eadc0(void);
+void nutool_pincfg_init_epwm0(void);
+void nutool_pincfg_deinit_epwm0(void);
+void nutool_pincfg_init_epwm1(void);
+void nutool_pincfg_deinit_epwm1(void);
+void nutool_pincfg_init_i2c1(void);
+void nutool_pincfg_deinit_i2c1(void);
+void nutool_pincfg_init_i2s0(void);
+void nutool_pincfg_deinit_i2s0(void);
+void nutool_pincfg_init_ice(void);
+void nutool_pincfg_deinit_ice(void);
+void nutool_pincfg_init_ph(void);
+void nutool_pincfg_deinit_ph(void);
+void nutool_pincfg_init_sd0(void);
+void nutool_pincfg_deinit_sd0(void);
+void nutool_pincfg_init_spi0(void);
+void nutool_pincfg_deinit_spi0(void);
+void nutool_pincfg_init_spi1(void);
+void nutool_pincfg_deinit_spi1(void);
+void nutool_pincfg_init_uart0(void);
+void nutool_pincfg_deinit_uart0(void);
+void nutool_pincfg_init_uart1(void);
+void nutool_pincfg_deinit_uart1(void);
+void nutool_pincfg_init_uart4(void);
+void nutool_pincfg_deinit_uart4(void);
+void nutool_pincfg_init_usb(void);
+void nutool_pincfg_deinit_usb(void);
+void nutool_pincfg_init(void);
+void nutool_pincfg_deinit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_PINCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
@@ -0,0 +1,189 @@
+/**************************************************************************//**
+ * @file     gpio.c
+ * @version  V3.00
+ * @brief    M2354 series General Purpose I/O (GPIO) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Set GPIO operation mode
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @param[in]   u32Mode     Operation mode. It could be
+ *                          - \ref GPIO_MODE_INPUT
+ *                          - \ref GPIO_MODE_OUTPUT
+ *                          - \ref GPIO_MODE_OPEN_DRAIN
+ *                          - \ref GPIO_MODE_QUASI
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t u32Idx;
+
+    for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+    {
+        if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx))
+        {
+            port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Enable GPIO interrupt
+ *
+ * @param[in]   port            GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin          The pin of specified GPIO port. \n
+ *                              It could be 0 ~ 15 for PA, PB and PE. \n
+ *                              It could be 0 ~ 13 for PC GPIO port. \n
+ *                              It could be 0 ~ 12, 14 for PD GPIO port. \n
+ *                              It could be 0 ~ 11 for PF GPIO port. \n
+ *                              It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ *                              It could be 4 ~ 11 for PH GPIO port.
+ * @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be
+ *                              - \ref GPIO_INT_RISING
+ *                              - \ref GPIO_INT_FALLING
+ *                              - \ref GPIO_INT_BOTH_EDGE
+ *                              - \ref GPIO_INT_HIGH
+ *                              - \ref GPIO_INT_LOW
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+    /* Configure interrupt mode of specified pin */
+    port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+
+    /* Enable interrupt function of specified pin */
+    port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief       Disable GPIO interrupt
+ *
+
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port. \n
+ *                          It could be 0 ~ 15 for PA, PB and PE. \n
+ *                          It could be 0 ~ 13 for PC GPIO port. \n
+ *                          It could be 0 ~ 12, 14 for PD GPIO port. \n
+ *                          It could be 0 ~ 11 for PF GPIO port. \n
+ *                          It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ *                          It could be 4 ~ 11 for PH GPIO port.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+    /* Configure interrupt mode of specified pin */
+    port->INTTYPE &= ~(1UL << u32Pin);
+
+    /* Disable interrupt function of specified pin */
+    port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+/**
+ * @brief       Set GPIO slew rate control
+ *
+
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @param[in]   u32Mode     Slew rate mode. It could be
+ *                          - \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
+ *                          - \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
+ *                          - \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t u32Idx;
+
+    for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+    {
+        if(u32PinMask & (1ul << u32Idx))
+        {
+            port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Set GPIO Pull-up and Pull-down control
+ *
+
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @param[in]   u32Mode     The pin mode of specified GPIO pin. It could be
+ *                          - \ref GPIO_PUSEL_DISABLE
+ *                          - \ref GPIO_PUSEL_PULL_UP
+ *                          - \ref GPIO_PUSEL_PULL_DOWN
+ *
+ * @return      None
+ *
+ * @details     Set the pin mode of specified GPIO pin.
+ */
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t u32Idx;
+
+    for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+    {
+        if(u32PinMask & (1ul << u32Idx))
+        {
+            port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+        }
+    }
+}
+
+/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group GPIO_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
@@ -0,0 +1,441 @@
+/**************************************************************************//**
+ * @file     sys.c
+ * @version  V3.00
+ * @brief    M2354 series System Manager (SYS) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+  @{
+*/
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear reset source
+  * @param[in]  u32Src is system reset source. Including :
+  *             - \ref SYS_RSTSTS_CPULKRF_Msk
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  * @return     None
+  * @details    This function clear the selected system reset source.
+  */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+    SYS->RSTSTS = u32Src;
+}
+
+/**
+  * @brief      Get Brown-out detector output status
+  * @param      None
+  * @retval     0 System voltage is higher than BODVL setting or BODEN is 0.
+  * @retval     1 System voltage is lower than BODVL setting.
+  * @details    This function get Brown-out detector output status.
+  */
+uint32_t SYS_GetBODStatus(void)
+{
+    return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+  * @brief      Get reset status register value
+  * @param      None
+  * @return     Reset source
+  * @details    This function get the system reset status register value.
+  */
+uint32_t SYS_GetResetSrc(void)
+{
+    return (SYS->RSTSTS);
+}
+
+/**
+  * @brief      Check if register is locked nor not
+  * @param      None
+  * @retval     0 Write-protection function is disabled.
+  *             1 Write-protection function is enabled.
+  * @details    This function check register write-protection bit setting.
+  */
+uint32_t SYS_IsRegLocked(void)
+{
+    return SYS->REGLCTL & 1UL ? 0UL : 1UL;
+}
+
+/**
+  * @brief      Get product ID
+  * @param      None
+  * @return     Product ID
+  * @details    This function get product ID.
+  */
+uint32_t  SYS_ReadPDID(void)
+{
+    return SYS->PDID;
+}
+
+/**
+  * @brief      Reset chip with chip reset
+  * @param      None
+  * @return     None
+  * @details    This function reset chip with chip reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetChip(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+  * @brief      Reset chip with CPU reset
+  * @param      None
+  * @return     None
+  * @details    This function reset CPU with CPU reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetCPU(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+  * @brief      Reset selected module
+  * @param[in]  u32ModuleIndex is module index. Including :
+  *             - \ref PDMA0_RST
+  *             - \ref PDMA1_RST
+  *             - \ref EBI_RST
+  *             - \ref USBH_RST
+  *             - \ref SDH0_RST
+  *             - \ref CRC_RST
+  *             - \ref CRPT_RST
+  *             - \ref KS_RST
+  *             - \ref GPIO_RST
+  *             - \ref TMR0_RST
+  *             - \ref TMR1_RST
+  *             - \ref TMR2_RST
+  *             - \ref TMR3_RST
+  *             - \ref TMR4_RST
+  *             - \ref TMR5_RST
+  *             - \ref ACMP01_RST
+  *             - \ref I2C0_RST
+  *             - \ref I2C1_RST
+  *             - \ref I2C2_RST
+  *             - \ref QSPI0_RST
+  *             - \ref SPI0_RST
+  *             - \ref SPI1_RST
+  *             - \ref SPI2_RST
+  *             - \ref SPI3_RST
+  *             - \ref UART0_RST
+  *             - \ref UART1_RST
+  *             - \ref UART2_RST
+  *             - \ref UART3_RST
+  *             - \ref UART4_RST
+  *             - \ref UART5_RST
+  *             - \ref CAN0_RST
+  *             - \ref OTG_RST
+  *             - \ref USBD_RST
+  *             - \ref EADC_RST
+  *             - \ref I2S0_RST
+  *             - \ref LCD_RST
+  *             - \ref TRNG_RST
+  *             - \ref SC0_RST
+  *             - \ref SC1_RST
+  *             - \ref SC2_RST
+  *             - \ref USCI0_RST
+  *             - \ref USCI1_RST
+  *             - \ref DAC_RST
+  *             - \ref EPWM0_RST
+  *             - \ref EPWM1_RST
+  *             - \ref BPWM0_RST
+  *             - \ref BPWM1_RST
+  *             - \ref QEI0_RST
+  *             - \ref QEI1_RST
+  *             - \ref ECAP0_RST
+  *             - \ref ECAP1_RST
+  * @return     None
+  * @details    This function reset selected module.
+  */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+    uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
+
+    /* Generate reset signal to the corresponding module */
+    u32TmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL));
+    u32TmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL));
+    *(uint32_t *)u32TmpAddr |= u32TmpVal;
+
+    /* Release corresponding module from reset state */
+    u32TmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL));
+    *(uint32_t *)u32TmpAddr &= u32TmpVal;
+}
+
+/**
+  * @brief      Enable and configure Brown-out detector function
+  * @param[in]  i32Mode is reset or interrupt mode. Including :
+  *             - \ref SYS_BODCTL_BOD_RST_EN
+  *             - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+  * @param[in]  u32BODLevel is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_1_6V
+  *             - \ref SYS_BODCTL_BODVL_1_8V
+  *             - \ref SYS_BODCTL_BODVL_2_0V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  *             - \ref SYS_BODCTL_BODVL_2_4V
+  *             - \ref SYS_BODCTL_BODVL_2_6V
+  *             - \ref SYS_BODCTL_BODVL_2_8V
+  *             - \ref SYS_BODCTL_BODVL_3_0V
+  * @return     None
+  * @details    This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+    /* Enable Brown-out Detector function */
+    /* Enable Brown-out interrupt or reset function */
+    /* Select Brown-out Detector threshold voltage */
+    while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk);
+    SYS->BODCTL = (SYS->BODCTL & ~(SYS_BODCTL_BODRSTEN_Msk | SYS_BODCTL_BODVL_Msk)) |
+                  ((uint32_t)i32Mode) | (u32BODLevel) | (SYS_BODCTL_BODEN_Msk);
+}
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This function disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_DisableBOD(void)
+{
+    while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk);
+    SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+
+/**
+  * @brief      Set Power Level
+  * @param[in]  u32PowerLevel is power level setting. Including :
+  *             - \ref SYS_PLCTL_PLSEL_PL0  : Supports system clock up to 96MHz.
+  *             - \ref SYS_PLCTL_PLSEL_PL1  : Supports system clock up to 84MHz.
+  *             - \ref SYS_PLCTL_PLSEL_PL2  : Supports system clock up to 48MHz.
+  *             - \ref SYS_PLCTL_PLSEL_PL3  : Supports system clock up to 4MHz.
+  * @return     None
+  * @details    This function select power level.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetPowerLevel(uint32_t u32PowerLevel)
+{
+    /* Set power voltage level */
+    while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+    SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel);
+    while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk);
+}
+
+
+/**
+  * @brief      Set Main Voltage Regulator Type
+  * @param[in]  u32PowerRegulator is main voltage regulator type. Including :
+  *             - \ref SYS_PLCTL_MVRS_LDO
+  *             - \ref SYS_PLCTL_MVRS_DCDC
+  * @retval     0  main voltage regulator type setting is not finished
+  * @retval     1  main voltage regulator type setting is finished
+  * @details    This function set main voltage regulator type.
+  *             The main voltage regulator type setting to DCDC cannot finished if the inductor is not detected.
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator)
+{
+    int32_t i32TimeOutCnt = 400;
+    uint32_t u32Ret = 1U;
+    uint32_t u32PowerRegStatus;
+
+    /* Get main voltage regulator type status */
+    u32PowerRegStatus = SYS->PLSTS & SYS_PLSTS_CURMVR_Msk;
+
+    /* Set main voltage regulator type */
+    if((u32PowerRegulator == SYS_PLCTL_MVRS_DCDC) && (u32PowerRegStatus == SYS_PLSTS_CURMVR_LDO))
+    {
+
+        /* Set main voltage regulator type to DCDC if status is LDO */
+        while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+        SYS->PLCTL |= SYS_PLCTL_MVRS_Msk;
+
+        /* Wait inductor detection and main voltage regulator type change ready */
+        while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_DCDC)
+        {
+            if(i32TimeOutCnt-- <= 0)
+            {
+                u32Ret = 0U;    /* Main voltage regulator type change time-out */
+                break;
+            }
+        }
+
+    }
+    else if(u32PowerRegulator == SYS_PLCTL_MVRS_LDO)
+    {
+
+        /* Set main voltage regulator type to LDO if status is DCDC */
+        while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+        SYS->PLCTL &= (~SYS_PLCTL_MVRS_Msk);
+
+        /* Wait main voltage regulator type change ready */
+        while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_LDO)
+        {
+            if(i32TimeOutCnt-- <= 0)
+            {
+                u32Ret = 0U;    /* Main voltage regulator type change time-out */
+                break;
+            }
+        }
+
+    }
+
+    /* Clear main voltage regulator type change error flag */
+    if(SYS->PLSTS & SYS_PLSTS_MVRCERR_Msk)
+    {
+        SYS->PLSTS = SYS_PLSTS_MVRCERR_Msk;
+        u32Ret = 0U;
+    }
+
+    return u32Ret;
+}
+
+/**
+  * @brief      Set System SRAM Power Mode
+  * @param[in]  u32SRAMSel is SRAM region selection. Including :
+  *             - \ref SYS_SRAMPC0_SRAM0PM0_Msk     : 0x2000_0000 - 0x2000_0FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM1_Msk     : 0x2000_1000 - 0x2000_1FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM2_Msk     : 0x2000_2000 - 0x2000_3FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM3_Msk     : 0x2000_4000 - 0x2000_5FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM4_Msk     : 0x2000_6000 - 0x2000_7FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM0_Msk     : 0x2000_8000 - 0x2000_BFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM1_Msk     : 0x2000_C000 - 0x2000_FFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM2_Msk     : 0x2001_0000 - 0x2001_3FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM3_Msk     : 0x2001_4000 - 0x2001_7FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM4_Msk     : 0x2001_8000 - 0x2001_BFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM5_Msk     : 0x2001_C000 - 0x2001_FFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM6_Msk     : 0x2002_0000 - 0x2002_3FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM7_Msk     : 0x2002_4000 - 0x2002_7FFF
+  *             - \ref SYS_SRAMPC0_SRAM2PM0_Msk     : 0x2002_8000 - 0x2002_BFFF
+  *             - \ref SYS_SRAMPC0_SRAM2PM1_Msk     : 0x2002_C000 - 0x2002_FFFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM2_Msk     : 0x2003_0000 - 0x2003_3FFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM3_Msk     : 0x2003_4000 - 0x2003_7FFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM4_Msk     : 0x2003_8000 - 0x2003_BFFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM5_Msk     : 0x2003_C000 - 0x2003_FFFF
+  * @param[in]  u32PowerMode is SRAM power mode. Including :
+  *             - \ref SYS_SRAMPC0_SRAM_NORMAL
+  *             - \ref SYS_SRAMPC0_SRAM_RETENTION
+  *             - \ref SYS_SRAMPC0_SRAM_POWER_SHUT_DOWN
+  *             - \ref SYS_SRAMPC1_SRAM_NORMAL
+  *             - \ref SYS_SRAMPC1_SRAM_RETENTION
+  *             - \ref SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN
+  * @return     None
+  * @details    This function set system SRAM power mode.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode)
+{
+    uint32_t u32SRAMSelPos = 0UL;
+
+    /* Get system SRAM power mode setting position */
+    while(u32SRAMSelPos < 30UL)
+    {
+        if(u32SRAMSel & (1 << u32SRAMSelPos))
+        {
+            break;
+        }
+        else
+        {
+            u32SRAMSelPos++;
+        }
+    }
+
+    /* Set system SRAM power mode setting */
+    if(u32PowerMode & BIT31)
+    {
+        while(SYS->SRAMPC1 & SYS_SRAMPC1_PCBUSY_Msk);
+        SYS->SRAMPC1 = (SYS->SRAMPC1 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);
+    }
+    else
+    {
+        while(SYS->SRAMPC0 & SYS_SRAMPC0_PCBUSY_Msk);
+        SYS->SRAMPC0 = (SYS->SRAMPC0 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);
+
+    }
+}
+
+/**
+  * @brief      Set Peripheral SRAM Power Mode
+  * @param[in]  u32SRAMSel is SRAM region selection. Including :
+  *             - \ref SYS_SRAMPC1_CAN_Msk
+  *             - \ref SYS_SRAMPC1_USBD_Msk
+  *             - \ref SYS_SRAMPC1_PDMA0_Msk
+  *             - \ref SYS_SRAMPC1_PDMA1_Msk
+  *             - \ref SYS_SRAMPC1_FMCCACHE_Msk
+  *             - \ref SYS_SRAMPC1_RSA_Msk
+  *             - \ref SYS_SRAMPC1_KS_Msk
+  * @param[in]  u32PowerMode is SRAM power mode. Including :
+  *             - \ref SYS_SRAMPC1_SRAM_NORMAL
+  *             - \ref SYS_SRAMPC1_SRAM_RETENTION
+  *             - \ref SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN
+  * @return     None
+  * @details    This function set peripheral SRAM power mode.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode)
+{
+    uint32_t u32SRAMSelPos = 16UL;
+
+    /* Get peripheral SRAM power mode setting position */
+    while(u32SRAMSelPos < 30UL)
+    {
+        if(u32SRAMSel & (1 << u32SRAMSelPos))
+        {
+            break;
+        }
+        else
+        {
+            u32SRAMSelPos++;
+        }
+    }
+
+    /* Set peripheral SRAM power mode setting */
+    while(SYS->SRAMPC1 & SYS_SRAMPC1_PCBUSY_Msk);
+    SYS->SRAMPC1 = (SYS->SRAMPC1 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);
+}
+
+/**
+  * @brief      Set Reference Voltage
+  * @param[in]  u32VRefCTL is reference voltage setting. Including :
+  *             - \ref SYS_VREFCTL_VREF_PIN
+  *             - \ref SYS_VREFCTL_VREF_1_6V
+  *             - \ref SYS_VREFCTL_VREF_2_0V
+  *             - \ref SYS_VREFCTL_VREF_2_5V
+  *             - \ref SYS_VREFCTL_VREF_3_0V
+  *             - \ref SYS_VREFCTL_VREF_AVDD
+  * @return     None
+  * @details    This function select reference voltage.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetVRef(uint32_t u32VRefCTL)
+{
+    /* Set reference voltage */
+    SYS->VREFCTL = (SYS->VREFCTL & (~SYS_VREFCTL_VREFCTL_Msk)) | (u32VRefCTL);
+}
+
+
+/**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SYS_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
@@ -0,0 +1,687 @@
+/**************************************************************************//**
+ * @file     uart.c
+ * @version  V3.00
+ * @brief    M2354 series UART Interface Controller (UART) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include <stdio.h>
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+  @{
+*/
+
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        Clear UART specified interrupt flag
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTSTS_SWBEINT_Msk   : Single-wire Bit Error Detect Interrupt
+ *                                      - \ref UART_INTSTS_LININT_Msk    : LIN Bus interrupt
+ *                                      - \ref UART_INTSTS_WKINT_Msk     : Wake-up interrupt
+ *                                      - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ *                                      - \ref UART_INTSTS_MODEMINT_Msk  : MODEM Status Interrupt
+ *                                      - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to clear UART specified interrupt flag.
+ */
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)
+{
+    if(u32InterruptFlag & UART_INTSTS_SWBEINT_Msk)      /* Clear Bit Error Detection Interrupt */
+    {
+        uart->FIFOSTS = UART_INTSTS_SWBEIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk)       /* Clear Receive Line Status Interrupt */
+    {
+        uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_ADDRDETF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk)     /* Clear MODEM Status Interrupt */
+    {
+        uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk)    /* Clear Buffer Error Interrupt */
+    {
+        uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_WKINT_Msk)        /* Clear Wake-up Interrupt */
+    {
+        uart->WKSTS = UART_WKSTS_CTSWKF_Msk  | UART_WKSTS_DATWKF_Msk   |
+                      UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |
+                      UART_WKSTS_TOUTWKF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_LININT_Msk)       /* Clear LIN Bus Interrupt */
+    {
+        uart->INTSTS = UART_INTSTS_LINIF_Msk;
+        uart->LINSTS = UART_LINSTS_BITEF_Msk    | UART_LINSTS_BRKDETF_Msk  |
+                       UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+                       UART_LINSTS_SLVHEF_Msk   | UART_LINSTS_SLVHDETF_Msk ;
+    }
+
+}
+
+
+/**
+ *  @brief      Disable UART interrupt
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T* uart)
+{
+    uart->INTEN = 0ul;
+}
+
+
+/**
+ *  @brief      Disable UART auto flow control function
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+    uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ *    @brief        Disable UART specified interrupt
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTEN_TXENDIEN_Msk   : Transmitter Empty Interrupt
+ *                                      - \ref UART_INTEN_SWBEIEN_Msk    : Single-wire Bit Error Detect Interrupt
+ *                                      - \ref UART_INTEN_ABRIEN_Msk     : Auto-baud Rate Interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin Bus interrupt
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx Time-out Interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : MODEM Status Interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line Status Interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Transmit Holding Register Empty Interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Receive Data Available Interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+    /* Disable UART specified interrupt */
+    UART_DISABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ *    @brief        Enable UART auto flow control function
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to Enable UART auto flow control.
+ */
+/**
+ *    @brief        Enable UART auto flow control function
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+    /* Set RTS pin output is low level active */
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+
+    /* Set CTS pin input is low level active */
+    uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+
+    /* Set RTS and CTS auto flow control enable */
+    uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ *    @brief        Enable UART specified interrupt
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module:
+ *                                      - \ref UART_INTEN_TXENDIEN_Msk   : Transmitter Empty Interrupt
+ *                                      - \ref UART_INTEN_ABRIEN_Msk     : Auto-baud Rate Interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin Bus interrupt
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx Time-out Interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : MODEM Status Interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line Status Interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Transmit Holding Register Empty Interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Receive Data Available Interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+
+    /* Enable UART specified interrupt */
+    UART_ENABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ *    @brief        Open and set UART function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The baudrate of UART module.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+    uint32_t u32UartClkSrcSel, u32UartClkDivNum;
+    uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul};
+    uint32_t u32BaudDiv = 0ul;
+
+    /* Get UART clock source selection and UART clock divider number */
+    switch((uint32_t)uart)
+    {
+        case UART0_BASE:
+        case UART0_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART1_BASE:
+        case UART1_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART2_BASE:
+        case UART2_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART3_BASE:
+        case UART3_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART4_BASE:
+        case UART4_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART5_BASE:
+        case UART5_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        default:
+            return;
+    }
+
+    /* Select UART function */
+    uart->FUNCSEL = UART_FUNCSEL_UART;
+
+    /* Set UART line configuration */
+    uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+    /* Set UART Rx and RTS trigger level */
+    uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul)
+    {
+        au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0ul)
+    {
+        u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if(u32BaudDiv > 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        }
+        else
+        {
+            uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv);
+        }
+    }
+}
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8RxBuf        The buffer to receive the data of receive FIFO.
+ *    @param[in]    u32ReadBytes    The the read bytes number of data.
+ *
+ *    @return       u32Count Receive byte count
+ *
+ *    @details      The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t  u32Count, u32delayno;
+    uint32_t  u32Exit = 0ul;
+
+    for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
+    {
+        u32delayno = 0ul;
+
+        while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)   /* Check RX empty => failed */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul)
+            {
+                u32Exit = 1ul;
+                break;
+            }
+            else
+            {
+            }
+        }
+
+        if(u32Exit == 1ul)
+        {
+            break;
+        }
+        else
+        {
+            pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX  */
+        }
+    }
+
+    return u32Count;
+}
+
+
+/**
+ *    @brief        Set UART line configuration
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The register value of baudrate of UART module.
+ *                                  If u32baudrate = 0, UART baudrate will not change.
+ *    @param[in]    u32data_width   The data length of UART module.
+ *                                  - \ref UART_WORD_LEN_5
+ *                                  - \ref UART_WORD_LEN_6
+ *                                  - \ref UART_WORD_LEN_7
+ *                                  - \ref UART_WORD_LEN_8
+ *    @param[in]    u32parity       The parity setting (none/odd/even/mark/space) of UART module.
+ *                                  - \ref UART_PARITY_NONE
+ *                                  - \ref UART_PARITY_ODD
+ *                                  - \ref UART_PARITY_EVEN
+ *                                  - \ref UART_PARITY_MARK
+ *                                  - \ref UART_PARITY_SPACE
+ *    @param[in]    u32stop_bits    The stop bit length (1/1.5/2 bit) of UART module.
+ *                                  - \ref UART_STOP_BIT_1
+ *                                  - \ref UART_STOP_BIT_1_5
+ *                                  - \ref UART_STOP_BIT_2
+ *
+ *    @return       None
+ *
+ *    @details      This function use to config UART line setting.
+ */
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits)
+{
+    uint32_t u32UartClkSrcSel, u32UartClkDivNum;
+    uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul};
+    uint32_t u32BaudDiv = 0ul;
+
+    /* Get UART clock source selection and UART clock divider number */
+    switch((uint32_t)uart)
+    {
+        case UART0_BASE:
+        case UART0_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART1_BASE:
+        case UART1_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART2_BASE:
+        case UART2_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART3_BASE:
+        case UART3_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART4_BASE:
+        case UART4_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART5_BASE:
+        case UART5_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        default:
+            return;
+    }
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul)
+    {
+        au32ClkTbl[1] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0ul)
+    {
+        u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if(u32BaudDiv > 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        }
+        else
+        {
+            uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv);
+        }
+    }
+
+    /* Set UART line configuration */
+    uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ *    @brief        Set Rx timeout count
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *    @param[in]    u32TOC  Rx timeout counter.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+    /* Set time-out interrupt comparator */
+    uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+
+    /* Set time-out counter enable */
+    uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ *    @brief        Select and configure IrDA function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Buadrate     The baudrate of UART module.
+ *    @param[in]    u32Direction    The direction of UART module in IrDA mode:
+ *                                  - \ref UART_IRDA_TXEN
+ *                                  - \ref UART_IRDA_RXEN
+ *
+ *    @return       None
+  *
+ *    @details      The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+    uint32_t u32UartClkSrcSel = 0UL, u32UartClkDivNum = 1UL;
+    uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul};
+    uint32_t u32BaudDiv;
+
+    /* Select IrDA function mode */
+    uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+    /* Get UART clock source selection and UART clock divider number */
+    switch((uint32_t)uart)
+    {
+        case UART0_BASE:
+        case UART0_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART1_BASE:
+        case UART1_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART2_BASE:
+        case UART2_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART3_BASE:
+        case UART3_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART4_BASE:
+        case UART4_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART5_BASE:
+        case UART5_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        default:
+            return;
+    }
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul)
+    {
+        au32ClkTbl[1] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART IrDA baud rate in mode 0 */
+    if(u32Buadrate != 0ul)
+    {
+        u32BaudDiv = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
+
+        if(u32BaudDiv < 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | u32BaudDiv);
+        }
+    }
+
+    /* Configure IrDA relative settings */
+    if(u32Direction == UART_IRDA_RXEN)
+    {
+        uart->IRDA |= UART_IRDA_RXINV_Msk;     /* Rx signal is inverse */
+        uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+    }
+    else
+    {
+        uart->IRDA &= ~UART_IRDA_TXINV_Msk;    /* Tx signal is not inverse */
+        uart->IRDA |= UART_IRDA_TXEN_Msk;
+    }
+
+}
+
+
+/**
+ *    @brief        Select and configure RS485 function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module.
+ *    @param[in]    u32Mode     The operation mode(NMM/AUD/AAD).
+ *                              - \ref UART_ALTCTL_RS485NMM_Msk
+ *                              - \ref UART_ALTCTL_RS485AUD_Msk
+ *                              - \ref UART_ALTCTL_RS485AAD_Msk
+ *    @param[in]    u32Addr     The RS485 address.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+    /* Select UART RS485 function mode */
+    uart->FUNCSEL = UART_FUNCSEL_RS485;
+
+    /* Set RS585 configuration */
+    uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+    uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ *    @brief        Select and configure LIN function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Mode         The LIN direction :
+ *                                  - \ref UART_ALTCTL_LINTXEN_Msk
+ *                                  - \ref UART_ALTCTL_LINRXEN_Msk
+ *    @param[in]    u32BreakLength  The breakfield length.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+    /* Select LIN function mode */
+    uart->FUNCSEL = UART_FUNCSEL_LIN;
+
+    /* Select LIN function setting : Tx enable, Rx enable and break field length */
+    uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+    uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8TxBuf        The buffer to send the data to UART transmission FIFO.
+ *    @param[out]   u32WriteBytes   The byte number of data.
+ *
+ *    @return       u32Count transfer byte count
+ *
+ *    @details      The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t  u32Count, u32delayno;
+    uint32_t  u32Exit = 0ul;
+
+    for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
+    {
+        u32delayno = 0ul;
+        while(UART_IS_TX_FULL(uart))     /* Wait Tx not full and Time-out manner */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul)
+            {
+                u32Exit = 1ul;
+                break;
+            }
+            else
+            {
+            }
+        }
+
+        if(u32Exit == 1ul)
+        {
+            break;
+        }
+        else
+        {
+            uart->DAT = pu8TxBuf[u32Count];    /* Send UART Data from buffer */
+        }
+    }
+
+    return u32Count;
+}
+
+/**
+ *    @brief        Select Single Wire mode function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to select Single Wire mode.
+ */
+void UART_SelectSingleWireMode(UART_T *uart)
+{
+    /* Select UART SingleWire function mode */
+    uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE);
+}
+
+
+/**@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group UART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
@@ -0,0 +1,564 @@
+/**************************************************************************//**
+ * @file     system_M2354.c
+ * @version  V2.00
+ * @brief    System Setting Source File
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)       /* ARM Compiler 6 */
+#include <arm_cmse.h>
+#endif
+
+#include <stdio.h>
+#include <stdint.h>
+#include "NuMicro.h"
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+#include "partition_M2354.h"
+#endif
+extern void *InterruptVectors;                   /* see startup file */
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock  = __HSI;              /*!< System Clock Frequency (Core Clock) */
+uint32_t CyclesPerUs      = (__HSI / 1000000UL);/*!< Cycles per micro second             */
+uint32_t PllClock         = __HSI;              /*!< PLL Output Clock Frequency          */
+
+void FMC_NSBA_Setup(void);
+void SCU_Setup(void);
+void NSC_Init(void);
+void TZ_SAU_Setup(void);
+
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+extern void SCU_IRQHandler(void);
+#else
+extern void SCU_IRQHandler(void)__attribute__((noreturn));
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ * @brief    Setup Non-secure boundary
+ *
+ * @details  This function is used to set Non-secure boundary according to
+ *           the configuration of partition header file
+ */
+void FMC_NSBA_Setup(void)
+{
+    /* Skip NSBA Setupt according config */
+    if(FMC_INIT_NSBA == 0)
+        return;
+
+    /* Check if NSBA value with current active NSBA */
+    if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
+    {
+        /* Unlock Protected Register */
+        SYS_UnlockReg();
+
+        /* Enable ISP and config update */
+        FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
+
+        /* Config Base of NSBA */
+        FMC->ISPADDR = FMC_NSCBA_BASE ;
+
+        /* Read Non-secure base address config */
+        FMC->ISPCMD = FMC_ISPCMD_READ;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC->ISPTRG);
+
+        //while(PA0);
+
+        /* Setting NSBA when it is empty */
+        if(FMC->ISPDAT != 0xfffffffful)
+        {
+            /* Erase old setting */
+            FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+            FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+            while(FMC->ISPTRG);
+        }
+
+        /* Set new base */
+        FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC->ISPTRG);
+
+        /* Force Chip Reset to valid new setting */
+        SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
+
+
+    }
+
+}
+
+
+/**
+  \brief   Setup SCU Configuration Unit
+  \details
+
+ */
+void SCU_Setup(void)
+{
+    int32_t i;
+
+    SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
+    SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
+    SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
+    SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
+    SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
+    SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
+    SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
+
+
+    SCU->IONSSET[0] = SCU_INIT_IONSSET0_VAL;
+    SCU->IONSSET[1] = SCU_INIT_IONSSET1_VAL;
+    SCU->IONSSET[2] = SCU_INIT_IONSSET2_VAL;
+    SCU->IONSSET[3] = SCU_INIT_IONSSET3_VAL;
+    SCU->IONSSET[4] = SCU_INIT_IONSSET4_VAL;
+    SCU->IONSSET[5] = SCU_INIT_IONSSET5_VAL;
+    SCU->IONSSET[6] = SCU_INIT_IONSSET6_VAL;
+    SCU->IONSSET[7] = SCU_INIT_IONSSET7_VAL;
+
+    /* Set Non-secure SRAM */
+    for(i = 15; i >= SCU_SECURE_SRAM_SIZE / 16384; i--)
+    {
+        SCU->SRAMNSSET |= (1U << i);
+    }
+
+    /* Set interrupt to non-secure according to PNNSET settings */
+    if(SCU_INIT_PNSSET0_VAL & BIT9) NVIC->ITNS[1] |= BIT22;  /* Int of USBH_INT     */
+    if(SCU_INIT_PNSSET0_VAL & BIT13) NVIC->ITNS[2] |= BIT0 ; /* Int of SDHOST0_INT  */
+    if(SCU_INIT_PNSSET0_VAL & BIT24) NVIC->ITNS[3] |= BIT2 ; /* Int of PDMA1_INT    */
+    if(SCU_INIT_PNSSET1_VAL & BIT18) NVIC->ITNS[2] |= BIT7 ; /* Int of CRYPTO       */
+    if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT15;  /* Int of EWDT_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT16;  /* Int of EWWDT_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT10;  /* Int of EADC0_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT11;  /* Int of EADC1_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT14;  /* Int of EADC2_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT15;  /* Int of EADC3_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT5) NVIC->ITNS[1] |= BIT12;  /* Int of ACMP01_INT   */
+    if(SCU_INIT_PNSSET2_VAL & BIT7) NVIC->ITNS[1] |= BIT9 ;  /* Int of DAC_INT      */
+    if(SCU_INIT_PNSSET2_VAL & BIT8) NVIC->ITNS[2] |= BIT4 ;  /* Int of I2S0_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT13) NVIC->ITNS[1] |= BIT23; /* Int of USBOTG_INT   */
+    if(SCU_INIT_PNSSET2_VAL & BIT17) NVIC->ITNS[1] |= BIT2 ; /* Int of TMR2_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT17) NVIC->ITNS[1] |= BIT3 ; /* Int of TMR3_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT18) NVIC->ITNS[3] |= BIT18; /* Int of TMR4_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT18) NVIC->ITNS[3] |= BIT19; /* Int of TMR5_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT25; /* Int of EPWM0_P0_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT26; /* Int of EPWM0_P1_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT27; /* Int of EPWM0_P2_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT29; /* Int of EPWM1_P0_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT30; /* Int of EPWM1_P1_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT31; /* Int of EPWM1_P2_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT26) NVIC->ITNS[2] |= BIT14; /* Int of BPWM0_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT27) NVIC->ITNS[2] |= BIT15; /* Int of BPWM1_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT0) NVIC->ITNS[0] |= BIT22;  /* Int of QSPI0_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT1) NVIC->ITNS[0] |= BIT23;  /* Int of SPI0_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT2) NVIC->ITNS[1] |= BIT19;  /* Int of SPI1_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT3) NVIC->ITNS[1] |= BIT20;  /* Int of SPI2_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT4) NVIC->ITNS[1] |= BIT30;  /* Int of SPI3_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT16) NVIC->ITNS[1] |= BIT4 ; /* Int of UART0_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT17) NVIC->ITNS[1] |= BIT5 ; /* Int of UART1_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT18) NVIC->ITNS[1] |= BIT16; /* Int of UART2_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT19) NVIC->ITNS[1] |= BIT17; /* Int of UART3_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT20) NVIC->ITNS[2] |= BIT10; /* Int of UART4_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT21) NVIC->ITNS[2] |= BIT11; /* Int of UART5_INT    */
+    if(SCU_INIT_PNSSET4_VAL & BIT0) NVIC->ITNS[1] |= BIT6 ;  /* Int of I2C0_INT     */
+    if(SCU_INIT_PNSSET4_VAL & BIT1) NVIC->ITNS[1] |= BIT7 ;  /* Int of I2C1_INT     */
+    if(SCU_INIT_PNSSET4_VAL & BIT2) NVIC->ITNS[2] |= BIT18;  /* Int of I2C2_INT     */
+    if(SCU_INIT_PNSSET4_VAL & BIT16) NVIC->ITNS[1] |= BIT26; /* Int of SC0_INT      */
+    if(SCU_INIT_PNSSET4_VAL & BIT17) NVIC->ITNS[1] |= BIT27; /* Int of SC1_INT      */
+    if(SCU_INIT_PNSSET4_VAL & BIT18) NVIC->ITNS[1] |= BIT28; /* Int of SC2_INT      */
+    if(SCU_INIT_PNSSET5_VAL & BIT0) NVIC->ITNS[1] |= BIT24;  /* Int of CAN0_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT16) NVIC->ITNS[2] |= BIT20; /* Int of QEI0_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT17) NVIC->ITNS[2] |= BIT21; /* Int of QEI1_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT20) NVIC->ITNS[2] |= BIT22; /* Int of ECAP0_INT    */
+    if(SCU_INIT_PNSSET5_VAL & BIT21) NVIC->ITNS[2] |= BIT23; /* Int of ECAP1_INT    */
+    if(SCU_INIT_PNSSET5_VAL & BIT25) NVIC->ITNS[3] |= BIT5 ; /* Int of TRNG_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT27) NVIC->ITNS[3] |= BIT4 ; /* Int of LCD_INT      */
+    if(SCU_INIT_PNSSET6_VAL & BIT0) NVIC->ITNS[1] |= BIT21;  /* Int of USBD_INT     */
+    if(SCU_INIT_PNSSET6_VAL & BIT16) NVIC->ITNS[2] |= BIT12; /* Int of USCI0_INT    */
+    if(SCU_INIT_PNSSET6_VAL & BIT17) NVIC->ITNS[2] |= BIT13; /* Int of USCI1_INT    */
+    if(SCU_INIT_IONSSET_VAL & BIT0) NVIC->ITNS[0] |= BIT16;  /* Int of PA           */
+    if(SCU_INIT_IONSSET_VAL & BIT1) NVIC->ITNS[0] |= BIT17;  /* Int of PB           */
+    if(SCU_INIT_IONSSET_VAL & BIT2) NVIC->ITNS[0] |= BIT18;  /* Int of PC           */
+    if(SCU_INIT_IONSSET_VAL & BIT3) NVIC->ITNS[0] |= BIT19;  /* Int of PD           */
+    if(SCU_INIT_IONSSET_VAL & BIT4) NVIC->ITNS[0] |= BIT20;  /* Int of PE           */
+    if(SCU_INIT_IONSSET_VAL & BIT5) NVIC->ITNS[0] |= BIT21;  /* Int of PF           */
+    if(SCU_INIT_IONSSET_VAL & BIT6) NVIC->ITNS[2] |= BIT8 ;  /* Int of PG           */
+    if(SCU_INIT_IONSSET_VAL & BIT7) NVIC->ITNS[2] |= BIT24;  /* Int of PH           */
+    if(SCU_INIT_IONSSET_VAL & BIT8) NVIC->ITNS[0] |= BIT10;  /* Int of EINT0        */
+    if(SCU_INIT_IONSSET_VAL & BIT9) NVIC->ITNS[0] |= BIT11;  /* Int of EINT1        */
+    if(SCU_INIT_IONSSET_VAL & BIT10) NVIC->ITNS[0] |= BIT12; /* Int of EINT2        */
+    if(SCU_INIT_IONSSET_VAL & BIT11) NVIC->ITNS[0] |= BIT13; /* Int of EINT3        */
+    if(SCU_INIT_IONSSET_VAL & BIT12) NVIC->ITNS[0] |= BIT14; /* Int of EINT4        */
+    if(SCU_INIT_IONSSET_VAL & BIT13) NVIC->ITNS[0] |= BIT15; /* Int of EINT5        */
+    if(SCU_INIT_IONSSET_VAL & BIT14) NVIC->ITNS[2] |= BIT9;  /* Int of EINT6        */
+    if(SCU_INIT_IONSSET_VAL & BIT15) NVIC->ITNS[2] |= BIT25; /* Int of EINT7        */
+
+    /* Enable SCU Int status */
+    SCU->SVIOIEN = (uint32_t)(-1);
+    SCU->PVIOIEN = (uint32_t)(-1);
+    NVIC_EnableIRQ(SCU_IRQn);
+
+}
+
+
+#if defined( __ICCARM__ )
+__WEAK
+#else
+__attribute__((weak))
+#endif
+void SCU_IRQHandler(void)
+{
+    char const *master[] = {"CPU", 0, 0, "PDMA0", "SDH0", "CRPT", "USBH", 0, 0, 0, 0, "PDMA1"};
+    char const *ipname[] = {"APB0", "APB1", 0, 0, "GPIO", "EBI", "USBH", "CRC", "SDH0", 0, "PDMA0", "PDMA1"
+                            , "SRAM0", "SRAM1", "FMC", "FLASH", "SCU", "SYS", "CRPT", "KS", "SIORAM"
+                           };
+    const uint8_t info[] = {0x34, 0x3C, 0, 0, 0x44, 0x4C, 0x54, 0x5C, 0x64, 0, 0x74, 0x7C, 0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0xC4};
+    uint32_t u32Reg, u32Addr;
+    uint32_t i;
+
+    /* TrustZone access policy */
+    u32Reg = SCU->SVINTSTS;
+    if(u32Reg)
+    {
+
+        /* Get violation address and source */
+        for(i = 0; i < sizeof(ipname); i++)
+        {
+            if(u32Reg & (1 << i))
+            {
+                u32Addr = M32(SCU_BASE + info[i] + 4);
+                printf("  %s(0x%08x) Alarm! illegal access by %s\n", ipname[i], u32Addr, master[M32(SCU_BASE + info[i])]);
+                SCU->SVINTSTS = (1 << i);
+                break;
+            }
+
+        }
+    }
+
+    /* Privilege */
+    u32Reg = SCU->PVINTSTS;
+    if(u32Reg)
+    {
+        /* Get violation address and source */
+        for(i = 0; i < sizeof(ipname); i++)
+        {
+            if(u32Reg & (1 << i))
+            {
+                printf("\n%s Alarm! Caused by unprivilege access\n\n", ipname[i]);
+                SCU->PVINTSTS = (1 << i);
+                break;
+            }
+        }
+    }
+
+}
+
+
+/**
+  \brief   Setup a Nonsecure callable Region
+  \details The base and limit of Nonsecure callable region is dependent on the
+           application code size.
+ */
+void NSC_Init(void)
+{
+    uint32_t u32Region;
+    uint32_t u32Base, u32Limit;
+
+#if defined (__ICCARM__)
+# pragma section = "NSC"
+    u32Base = (uint32_t)__section_begin("NSC");
+    u32Limit = (uint32_t)__section_end("NSC");
+#elif defined(__ARMCC_VERSION)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wdollar-in-identifier-extension"
+    extern uint32_t Image$$NSC_ROM$$XO$$Base[];
+    extern uint32_t Image$$NSC_ROM$$XO$$Limit[];
+    u32Base = (uint32_t)Image$$NSC_ROM$$XO$$Base;
+    u32Limit = (uint32_t)Image$$NSC_ROM$$XO$$Limit;
+#pragma clang diagnostic pop
+#else
+    extern uint32_t __start_NSC[];
+    extern uint32_t __end_NSC[];
+    u32Base = (uint32_t)__start_NSC;
+    u32Limit = (uint32_t)__end_NSC;
+#endif
+
+    /* SAU region 3 is dedicated for NSC */
+    u32Region = 3;
+    SAU->RNR  = (u32Region & SAU_RNR_REGION_Msk);
+    SAU->RBAR = (u32Base & SAU_RBAR_BADDR_Msk);
+    SAU->RLAR = (u32Limit & SAU_RLAR_LADDR_Msk) |
+                ((1ul << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk) | 1ul;
+
+}
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+void TZ_SAU_Setup(void)
+{
+
+#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
+
+#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+#endif
+
+#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+#endif
+
+#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+#endif
+
+#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+#endif
+
+#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+#endif
+
+#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+#endif
+
+#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+#endif
+
+#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+#endif
+
+    /* repeat this for all possible SAU regions */
+
+
+#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+#endif
+
+#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
+
+#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
+                 ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (0x05FA << 16) |
+                 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                 ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk)    |
+                 ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk);
+
+
+
+#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
+    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk)) |
+                 ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);
+#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
+
+    /* repeat this for all possible ITNS elements */
+
+    /* Initial Nonsecure callable region */
+    NSC_Init();
+}
+#else
+#if defined( __ICCARM__ )
+__WEAK
+#else
+__attribute__((weak))
+#endif
+void SCU_IRQHandler(void)
+{
+    while(1);
+}
+#endif
+
+
+/**
+ * @brief    Update the Variable SystemCoreClock
+ *
+ * @details  This function is used to update the variable SystemCoreClock
+ *           and must be called whenever the core clock is changed.
+ */
+void SystemCoreClockUpdate(void)
+{
+    /* Update PLL Clock */
+    PllClock = CLK_GetPLLClockFreq();
+
+    /* Update System Core Clock */
+    SystemCoreClock = CLK_GetCPUFreq();
+
+    /* Update Cycles per micro second */
+    CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+}
+
+
+
+/**
+ * @brief    System Initialization
+ *
+ * @details  The necessary initialization of system. Global variables are forbidden here.
+ */
+void SystemInit(void)
+{
+#if 0
+    if((__PC() & NS_OFFSET) == 0)
+    {
+        /* Unlock protected registers */
+        do
+        {
+            SYS->REGLCTL = 0x59;
+            SYS->REGLCTL = 0x16;
+            SYS->REGLCTL = 0x88;
+        }
+        while(!SYS->REGLCTL);
+
+        /* Enable Crypto power switch */
+        SYS->PSWCTL = SYS_PSWCTL_CRPTPWREN_Msk;
+
+        /* Enable all GPIO, SRAM and Trace clock */
+        CLK->AHBCLK |= (0xffful << 20) | (1ul << 14);
+    }
+#endif
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    SCB->VTOR = (uint32_t) &InterruptVectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+    TZ_SAU_Setup();
+    SCU_Setup();
+    FMC_NSBA_Setup();
+#endif
+
+#ifdef INIT_SYSCLK_AT_BOOTING
+
+#endif
+
+}
+
+
+#if USE_ASSERT
+
+/**
+ * @brief      Assert Error Message
+ *
+ * @param[in]  file  the source file name
+ * @param[in]  line  line number
+ *
+ * @details    The function prints the source file name and line number where
+ *             the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
+ */
+void AssertError(uint8_t * file, uint32_t line)
+{
+
+    printf("[%s] line %d : wrong parameters.\r\n", file, line);
+
+    /* Infinite loop */
+    while(1) ;
+}
+#endif
+
+
+#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000))
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+uint32_t __TZ_get_PSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile("MRS %0, psp_ns"  : "=r"(result));
+    return(result);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack));
+}
+
+
+
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+int32_t __TZ_get_MSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile("MRS %0, msp_ns" : "=r"(result));
+    return(result);
+}
+
+
+
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack));
+}
+
+
+
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, primask_ns" : "=r"(result));
+    return(result);
+}
+
+
+
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory");
+}
+
+
+#endif
+
+
+#endif
+
+
+