diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile index 1c3991e07..d6fa521c7 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile @@ -34,6 +34,10 @@ ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += k210_leds.c endif +ifeq ($(CONFIG_K210_LCD),y) +CSRCS += k210_lcd.c lcd_demo.c +endif + ifeq ($(CONFIG_DEV_GPIO),y) CSRCS += k210_gpio.c endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c index b85c649bd..bc90e372b 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c @@ -34,6 +34,7 @@ #include #include "k210.h" +#include "k210_clockconfig.h" #include "xidatong-riscv64.h" #ifdef CONFIG_BSP_USING_CH438 @@ -75,5 +76,14 @@ int k210_bringup(void) board_ch438_initialize(); #endif +#ifdef CONFIG_K210_LCD + k210_sysctl_init(); + ret = board_lcd_initialize(); + if (ret < 0) + { + syslog(LOG_NOTICE, "board lcd initialize %d\n", ret); + } +#endif + return ret; } diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_lcd.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_lcd.c new file mode 100755 index 000000000..5eebdbb4f --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_lcd.c @@ -0,0 +1,219 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file k210_lcd.c + * @brief LCD relative driver + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2022.7.21 + */ + + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "k210_fpioa.h" +#include "k210_gpiohs.h" +#include "nuttx/arch.h" +#include "nuttx/lcd/lt768.h" +#include "nuttx/lcd/lt768_lib.h" +#include "nuttx/lcd/k210_lcd.h" +#ifdef CONFIG_LCD_LCDDRV_SPIIF +#include "nuttx/lcd/lcddrv_spiif.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void test_delay(void) +{ + volatile uint32_t i = 0; + for (i = 0; i < 200; ++i) + { + __asm("NOP"); /* delay */ + } +} + +void lcd_pin_init(void) +{ + k210_fpioa_config(BSP_LCD_NRST, HS_GPIO(FPIOA_LCD_NRST) | K210_IOFLAG_GPIOHS); + k210_fpioa_config(BSP_LCD_SCLK, HS_GPIO(FPIOA_LCD_SCLK) | K210_IOFLAG_GPIOHS); + k210_fpioa_config(BSP_LCD_MOSI, HS_GPIO(FPIOA_LCD_MOSI) | K210_IOFLAG_GPIOHS); + k210_fpioa_config(BSP_LCD_MISO, HS_GPIO(FPIOA_LCD_MISO) | K210_IOFLAG_GPIOHS); + k210_fpioa_config(BSP_LCD_NCS, HS_GPIO(FPIOA_LCD_NCS) | K210_IOFLAG_GPIOHS); + + k210_gpiohs_set_direction(FPIOA_LCD_MISO, GPIO_DM_INPUT); + k210_gpiohs_set_direction(FPIOA_LCD_NRST, GPIO_DM_OUTPUT); + k210_gpiohs_set_direction(FPIOA_LCD_SCLK, GPIO_DM_OUTPUT); + k210_gpiohs_set_direction(FPIOA_LCD_MOSI, GPIO_DM_OUTPUT); + k210_gpiohs_set_direction(FPIOA_LCD_NCS, GPIO_DM_OUTPUT); + + lcd_set_pin(FPIOA_LCD_SCLK, GPIO_PV_HIGH); + lcd_set_pin(FPIOA_LCD_NCS, GPIO_PV_HIGH); + lcd_set_pin(FPIOA_LCD_NRST, GPIO_PV_HIGH); +} + +void lcd_backlight_init(bool enable) +{ + k210_fpioa_config(BSP_LCD_BL_PIN, HS_GPIO(FPIOA_LCD_BL) | K210_IOFLAG_GPIOHS); + k210_gpiohs_set_direction(FPIOA_LCD_BL, GPIO_DM_OUTPUT); + k210_gpiohs_set_value(FPIOA_LCD_BL, enable); +} + +#ifdef CONFIG_LCD_LCDDRV_SPIIF +int spiif_backlight(FAR struct lcddrv_lcd_s *lcd, int level) +{ + lcd_backlight_init(true); + return 1; +} +#endif + +uint8_t lcd_transfer_byte(uint8_t dat) +{ + uint8_t i, rx_data = 0; + + for(i = 0; i < 8; i++) + { + CLK_H; + + // MOSI during falling edge + if((dat << i) & 0x80) + { + MOSI_H; + } + else + { + MOSI_L; + } + + CLK_L; + + // MISO during rising edge + rx_data <<= 1; + if(lcd_get_pin(FPIOA_LCD_MISO)) + rx_data ++; + } + CLK_H; + return rx_data; +} + +void LCD_CmdWrite(uint8_t cmd) +{ + NCS_L; + lcd_transfer_byte(0x00); + lcd_transfer_byte(cmd); + NCS_H; +} + +void LCD_DataWrite(uint8_t data) +{ + NCS_L; + lcd_transfer_byte(0x80); + lcd_transfer_byte(data); + NCS_H; +} + +void LCD_DataWrite_Pixel(uint8_t data) +{ + NCS_L; + lcd_transfer_byte(0x80); + lcd_transfer_byte(data); + NCS_H; + NCS_L; + lcd_transfer_byte(0x80); + lcd_transfer_byte(data >> 8); + NCS_H; +} + +uint8_t LCD_StatusRead(void) +{ + uint8_t temp = 0; + NCS_L; + lcd_transfer_byte(0x40); + temp = lcd_transfer_byte(0xff); + NCS_H; + return temp; +} + +uint8_t LCD_DataRead(void) +{ + uint8_t temp = 0; + NCS_L; + lcd_transfer_byte(0xc0); + temp = lcd_transfer_byte(0xff); + NCS_H; + return temp; +} + +/*****************************************************************************/ + +void lcd_drv_init(void) +{ + uint8_t PwmControl = 100; + + lcd_pin_init(); + lt768_init(); + Select_SFI_Dual_Mode0(); + + // PWM1 enable backlight + LT768_PWM1_Init(1, 0, 200, 100, PwmControl); + + // enable RGB output + Display_ON(); + + Main_Image_Start_Address(LCD_START_ADDR); + Main_Image_Width(LCD_XSIZE_TFT); + Main_Window_Start_XY(0, 0); + Canvas_Image_Start_address(LCD_START_ADDR); + Canvas_image_width(LCD_XSIZE_TFT); + Active_Window_XY(0, 0); + Active_Window_WH(LCD_XSIZE_TFT, LCD_YSIZE_TFT); + up_mdelay(10); + Canvas_Image_Start_address(LCD_START_ADDR); + + //fill blue background + LT768_DrawSquare_Fill(0, 0, LCD_XSIZE_TFT, LCD_YSIZE_TFT, Blue); +} + +/**************************************************************************** + * Name: k210_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ****************************************************************************/ + +void board_lcd_initialize(void) +{ + /* Configure the LCD backlight (and turn the backlight off) */ + lcd_backlight_init(true); + lcd_drv_init(); +} + +/**************************************************************************** + * Name: k210_backlight + * + * Description: + * If CONFIG_K210_LCD_BACKLIGHT is defined, then the board-specific + * logic must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_K210_LCD_BACKLIGHT +void k210_backlight(bool blon) +{ + lcd_backlight_init(blon); +} +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/lcd_demo.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/lcd_demo.c new file mode 100755 index 000000000..cebf7d69e --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/lcd_demo.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * lcd_demo.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/** +* @file lcd_demo.c +* @brief +* @version 1.0.0 +* @author AIIT XUOS Lab +* @date 2022-07-21 +*/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "nuttx/arch.h" +#include "nuttx/lcd/lt768.h" +#include "nuttx/lcd/lt768_lib.h" +#include "nuttx/lcd/k210_lcd.h" + +void LcdDemo(void) +{ +// int x1 = 0, y1 = 0, x2 = LCD_XSIZE_TFT, y2 = LCD_YSIZE_TFT; + int x1 = 100, y1 = 100, x2 = 200, y2 = 200; + + Main_Image_Start_Address(LCD_START_ADDR); + Main_Image_Width(LCD_XSIZE_TFT); + Main_Window_Start_XY(0, 0); + Canvas_Image_Start_address(LCD_START_ADDR); + Canvas_image_width(LCD_XSIZE_TFT); + Active_Window_XY(0, 0); + Active_Window_WH(LCD_XSIZE_TFT, LCD_YSIZE_TFT); + up_mdelay(10); + Canvas_Image_Start_address(LCD_START_ADDR); + + for(int i = 0; i < 3; i++) + { + syslog(LOG_NOTICE, "Disp_demo %d\n", i); + LT768_DrawSquare_Fill(x1, y1, x2, y2, Red); + up_mdelay(2000); + LT768_DrawSquare_Fill(x1, y1, x2, y2, Green); + up_mdelay(2000); + LT768_DrawSquare_Fill(x1, y1, x2, y2, Blue); + up_mdelay(2000); + } +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h index 366bab399..3e4c8f172 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h @@ -1454,6 +1454,10 @@ int nsh_foreach_var(FAR struct nsh_vtbl_s *vtbl, nsh_foreach_var_t cb, int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); #endif +#if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD) + int cmd_Lcd(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); +#endif + #if defined(CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS) && !defined(CONFIG_NSH_DISABLE_HCHO_TB600B_WQ_HCHO1OS) int cmd_Hcho1os(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv); #endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c index 34fb18629..8d2138e95 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c @@ -49,6 +49,19 @@ int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) } #endif +/**************************************************************************** + * Name: cmd_lcd + ****************************************************************************/ +#if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD) +extern void LcdDemo(void); +int cmd_Lcd(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + nsh_output(vtbl, "Hello, LCD!\n"); + LcdDemo(); + return OK; +} +#endif + /**************************************************************************** * Name: cmd_Hcho1os ****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c index 79ee7365d..d0e50455a 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c @@ -600,6 +600,10 @@ static const struct cmdmap_s g_cmdmap[] = { "ch438", cmd_Ch438, 1, 1, "[ch438 demo cmd.]" }, #endif +#if defined(CONFIG_K210_LCD) && !defined(CONFIG_NSH_DISABLE_LCD) + { "lcd", cmd_Lcd, 1, 1, "[LCD demo cmd.]" }, +#endif + #if defined(CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS) && !defined(CONFIG_NSH_DISABLE_HCHO_TB600B_WQ_HCHO1OS) { "hcho1os", cmd_Hcho1os, 1, 1, "[get the concentration of formaldehyde with sensor tb600b_wq_hcho1os.]" }, #endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig new file mode 100755 index 000000000..483c24e8d --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Kconfig @@ -0,0 +1,49 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "K210 Configuration Options" + +menu "K210 Peripheral Support" + +# These "hidden" settings determine whether a peripheral option is available +# for the selected MCU + +config K210_HAVE_UART0 + bool + default y + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +# These are the peripheral selections proper + +config K210_UART0 + bool "UART0" + default y + select ARCH_HAVE_UART0 + select ARCH_HAVE_SERIAL_TERMIOS + select K210_UART + +config K210_HAVE_LCD + bool + default n + +config K210_LCD + bool "LCD" + default y + select K210_HAVE_LCD + +config K210_LCD_BACKLIGHT + bool "LCD BACKLIGHT" + default y + +endmenu + +menu "K210 Others" + +config K210_WITH_QEMU + bool "qemu support" + default n + +endmenu diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs index 221af4901..63dbba19a 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs @@ -57,6 +57,7 @@ CHIP_CSRCS = k210_allocateheap.c k210_clockconfig.c CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c k210_systemreset.c CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c k210_gpio.c +CHIP_CSRCS += k210_sysctl.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h new file mode 100755 index 000000000..980e36f4c --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/encoding.h @@ -0,0 +1,1329 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001U +#define MSTATUS_SIE 0x00000002U +#define MSTATUS_HIE 0x00000004U +//#define MSTATUS_MIE 0x00000008U +#define MSTATUS_UPIE 0x00000010U +#define MSTATUS_SPIE 0x00000020U +#define MSTATUS_HPIE 0x00000040U +//#define MSTATUS_MPIE 0x00000080U +#define MSTATUS_SPP 0x00000100U +#define MSTATUS_HPP 0x00000600U +#define MSTATUS_MPP 0x00001800U +//#define MSTATUS_FS 0x00006000U +#define MSTATUS_XS 0x00018000U +#define MSTATUS_MPRV 0x00020000U +#define MSTATUS_PUM 0x00040000U +#define MSTATUS_MXR 0x00080000U +#define MSTATUS_VM 0x1F000000U +#define MSTATUS32_SD 0x80000000U +#define MSTATUS64_SD 0x8000000000000000U + +#define SSTATUS_UIE 0x00000001U +#define SSTATUS_SIE 0x00000002U +#define SSTATUS_UPIE 0x00000010U +#define SSTATUS_SPIE 0x00000020U +#define SSTATUS_SPP 0x00000100U +#define SSTATUS_FS 0x00006000U +#define SSTATUS_XS 0x00018000U +#define SSTATUS_PUM 0x00040000U +#define SSTATUS32_SD 0x80000000U +#define SSTATUS64_SD 0x8000000000000000U + +#define DCSR_XDEBUGVER (3U << 30) +#define DCSR_NDRESET (1U << 29) +#define DCSR_FULLRESET (1U << 28) +#define DCSR_EBREAKM (1U << 15) +#define DCSR_EBREAKH (1U << 14) +#define DCSR_EBREAKS (1U << 13) +#define DCSR_EBREAKU (1U << 12) +#define DCSR_STOPCYCLE (1U << 10) +#define DCSR_STOPTIME (1U << 9) +#define DCSR_CAUSE (7U << 6) +#define DCSR_DEBUGINT (1U << 5) +#define DCSR_HALT (1U << 3) +#define DCSR_STEP (1U << 2) +#define DCSR_PRV (3U << 0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_SELECT (1U << 19) +#define MCONTROL_TIMING (1U << 18) +#define MCONTROL_ACTION (0x3fU << 12) +#define MCONTROL_CHAIN (1U << 11) +#define MCONTROL_MATCH (0xfU << 7) +#define MCONTROL_M (1U << 6) +#define MCONTROL_H (1U << 5) +#define MCONTROL_S (1U << 4) +#define MCONTROL_U (1U << 3) +#define MCONTROL_EXECUTE (1U << 2) +#define MCONTROL_STORE (1U << 1) +#define MCONTROL_LOAD (1U << 0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1U << IRQ_S_SOFT) +#define MIP_HSIP (1U << IRQ_H_SOFT) +#define MIP_MSIP (1U << IRQ_M_SOFT) +#define MIP_STIP (1U << IRQ_S_TIMER) +#define MIP_HTIP (1U << IRQ_H_TIMER) +//#define MIP_MTIP (1U << IRQ_M_TIMER) +#define MIP_SEIP (1U << IRQ_S_EXT) +#define MIP_HEIP (1U << IRQ_H_EXT) +#define MIP_MEIP (1U << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000U +#define DEFAULT_NMIVEC 0x00001004U +#define DEFAULT_MTVEC 0x00001010U +#define CONFIG_STRING_ADDR 0x0000100CU +#define EXT_IO_BASE 0x40000000U +#define DRAM_BASE 0x80000000U + +/* page table entry (PTE) fields */ +#define PTE_V 0x001U /* Valid */ +#define PTE_R 0x002U /* Read */ +#define PTE_W 0x004U /* Write */ +#define PTE_X 0x008U /* Execute */ +#define PTE_U 0x010U /* User */ +#define PTE_G 0x020U /* Global */ +#define PTE_A 0x040U /* Accessed */ +#define PTE_D 0x080U /* Dirty */ +#define PTE_SOFT 0x300U /* Reserved for Software */ + +#define PTE_PPN_SHIFT 10 + +#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#if defined(__riscv) + +#if defined(__riscv64) +#define MSTATUS_SD MSTATUS64_SD +#define SSTATUS_SD SSTATUS64_SD +#define RISCV_PGLEVEL_BITS 9 +#else +#define MSTATUS_SD MSTATUS32_SD +#define SSTATUS_SD SSTATUS32_SD +#define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#if defined(__GNUC__) + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define read_time() read_csr(mtime) +#define read_cycle() read_csr(mcycle) +#define current_coreid() read_csr(mhartid) + +#endif + +#endif + +#endif + +#endif + +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63U +#define MASK_BEQ 0x707fU +#define MATCH_BNE 0x1063U +#define MASK_BNE 0x707fU +#define MATCH_BLT 0x4063U +#define MASK_BLT 0x707fU +#define MATCH_BGE 0x5063U +#define MASK_BGE 0x707fU +#define MATCH_BLTU 0x6063U +#define MASK_BLTU 0x707fU +#define MATCH_BGEU 0x7063U +#define MASK_BGEU 0x707fU +#define MATCH_JALR 0x67U +#define MASK_JALR 0x707fU +#define MATCH_JAL 0x6fU +#define MASK_JAL 0x7fU +#define MATCH_LUI 0x37U +#define MASK_LUI 0x7fU +#define MATCH_AUIPC 0x17U +#define MASK_AUIPC 0x7fU +#define MATCH_ADDI 0x13U +#define MASK_ADDI 0x707fU +#define MATCH_SLLI 0x1013U +#define MASK_SLLI 0xfc00707fU +#define MATCH_SLTI 0x2013U +#define MASK_SLTI 0x707fU +#define MATCH_SLTIU 0x3013U +#define MASK_SLTIU 0x707fU +#define MATCH_XORI 0x4013U +#define MASK_XORI 0x707fU +#define MATCH_SRLI 0x5013U +#define MASK_SRLI 0xfc00707fU +#define MATCH_SRAI 0x40005013U +#define MASK_SRAI 0xfc00707fU +#define MATCH_ORI 0x6013U +#define MASK_ORI 0x707fU +#define MATCH_ANDI 0x7013U +#define MASK_ANDI 0x707fU +#define MATCH_ADD 0x33U +#define MASK_ADD 0xfe00707fU +#define MATCH_SUB 0x40000033U +#define MASK_SUB 0xfe00707fU +#define MATCH_SLL 0x1033U +#define MASK_SLL 0xfe00707fU +#define MATCH_SLT 0x2033U +#define MASK_SLT 0xfe00707fU +#define MATCH_SLTU 0x3033U +#define MASK_SLTU 0xfe00707fU +#define MATCH_XOR 0x4033U +#define MASK_XOR 0xfe00707fU +#define MATCH_SRL 0x5033U +#define MASK_SRL 0xfe00707fU +#define MATCH_SRA 0x40005033U +#define MASK_SRA 0xfe00707fU +#define MATCH_OR 0x6033U +#define MASK_OR 0xfe00707fU +#define MATCH_AND 0x7033U +#define MASK_AND 0xfe00707fU +#define MATCH_ADDIW 0x1bU +#define MASK_ADDIW 0x707fU +#define MATCH_SLLIW 0x101bU +#define MASK_SLLIW 0xfe00707fU +#define MATCH_SRLIW 0x501bU +#define MASK_SRLIW 0xfe00707fU +#define MATCH_SRAIW 0x4000501bU +#define MASK_SRAIW 0xfe00707fU +#define MATCH_ADDW 0x3bU +#define MASK_ADDW 0xfe00707fU +#define MATCH_SUBW 0x4000003bU +#define MASK_SUBW 0xfe00707fU +#define MATCH_SLLW 0x103bU +#define MASK_SLLW 0xfe00707fU +#define MATCH_SRLW 0x503bU +#define MASK_SRLW 0xfe00707fU +#define MATCH_SRAW 0x4000503bU +#define MASK_SRAW 0xfe00707fU +#define MATCH_LB 0x3U +#define MASK_LB 0x707fU +#define MATCH_LH 0x1003U +#define MASK_LH 0x707fU +#define MATCH_LW 0x2003U +#define MASK_LW 0x707fU +#define MATCH_LD 0x3003U +#define MASK_LD 0x707fU +#define MATCH_LBU 0x4003U +#define MASK_LBU 0x707fU +#define MATCH_LHU 0x5003U +#define MASK_LHU 0x707fU +#define MATCH_LWU 0x6003U +#define MASK_LWU 0x707fU +#define MATCH_SB 0x23U +#define MASK_SB 0x707fU +#define MATCH_SH 0x1023U +#define MASK_SH 0x707fU +#define MATCH_SW 0x2023U +#define MASK_SW 0x707fU +#define MATCH_SD 0x3023U +#define MASK_SD 0x707fU +#define MATCH_FENCE 0xfU +#define MASK_FENCE 0x707fU +#define MATCH_FENCE_I 0x100fU +#define MASK_FENCE_I 0x707fU +#define MATCH_MUL 0x2000033U +#define MASK_MUL 0xfe00707fU +#define MATCH_MULH 0x2001033U +#define MASK_MULH 0xfe00707fU +#define MATCH_MULHSU 0x2002033U +#define MASK_MULHSU 0xfe00707fU +#define MATCH_MULHU 0x2003033U +#define MASK_MULHU 0xfe00707fU +#define MATCH_DIV 0x2004033U +#define MASK_DIV 0xfe00707fU +#define MATCH_DIVU 0x2005033U +#define MASK_DIVU 0xfe00707fU +#define MATCH_REM 0x2006033U +#define MASK_REM 0xfe00707fU +#define MATCH_REMU 0x2007033U +#define MASK_REMU 0xfe00707fU +#define MATCH_MULW 0x200003bU +#define MASK_MULW 0xfe00707fU +#define MATCH_DIVW 0x200403bU +#define MASK_DIVW 0xfe00707fU +#define MATCH_DIVUW 0x200503bU +#define MASK_DIVUW 0xfe00707fU +#define MATCH_REMW 0x200603bU +#define MASK_REMW 0xfe00707fU +#define MATCH_REMUW 0x200703bU +#define MASK_REMUW 0xfe00707fU +#define MATCH_AMOADD_W 0x202fU +#define MASK_AMOADD_W 0xf800707fU +#define MATCH_AMOXOR_W 0x2000202fU +#define MASK_AMOXOR_W 0xf800707fU +#define MATCH_AMOOR_W 0x4000202fU +#define MASK_AMOOR_W 0xf800707fU +#define MATCH_AMOAND_W 0x6000202fU +#define MASK_AMOAND_W 0xf800707fU +#define MATCH_AMOMIN_W 0x8000202fU +#define MASK_AMOMIN_W 0xf800707fU +#define MATCH_AMOMAX_W 0xa000202fU +#define MASK_AMOMAX_W 0xf800707fU +#define MATCH_AMOMINU_W 0xc000202fU +#define MASK_AMOMINU_W 0xf800707fU +#define MATCH_AMOMAXU_W 0xe000202fU +#define MASK_AMOMAXU_W 0xf800707fU +#define MATCH_AMOSWAP_W 0x800202fU +#define MASK_AMOSWAP_W 0xf800707fU +#define MATCH_LR_W 0x1000202fU +#define MASK_LR_W 0xf9f0707fU +#define MATCH_SC_W 0x1800202fU +#define MASK_SC_W 0xf800707fU +#define MATCH_AMOADD_D 0x302fU +#define MASK_AMOADD_D 0xf800707fU +#define MATCH_AMOXOR_D 0x2000302fU +#define MASK_AMOXOR_D 0xf800707fU +#define MATCH_AMOOR_D 0x4000302fU +#define MASK_AMOOR_D 0xf800707fU +#define MATCH_AMOAND_D 0x6000302fU +#define MASK_AMOAND_D 0xf800707fU +#define MATCH_AMOMIN_D 0x8000302fU +#define MASK_AMOMIN_D 0xf800707fU +#define MATCH_AMOMAX_D 0xa000302fU +#define MASK_AMOMAX_D 0xf800707fU +#define MATCH_AMOMINU_D 0xc000302fU +#define MASK_AMOMINU_D 0xf800707fU +#define MATCH_AMOMAXU_D 0xe000302fU +#define MASK_AMOMAXU_D 0xf800707fU +#define MATCH_AMOSWAP_D 0x800302fU +#define MASK_AMOSWAP_D 0xf800707fU +#define MATCH_LR_D 0x1000302fU +#define MASK_LR_D 0xf9f0707fU +#define MATCH_SC_D 0x1800302fU +#define MASK_SC_D 0xf800707fU +#define MATCH_ECALL 0x73U +#define MASK_ECALL 0xffffffffU +#define MATCH_EBREAK 0x100073U +#define MASK_EBREAK 0xffffffffU +#define MATCH_URET 0x200073U +#define MASK_URET 0xffffffffU +#define MATCH_SRET 0x10200073U +#define MASK_SRET 0xffffffffU +#define MATCH_HRET 0x20200073U +#define MASK_HRET 0xffffffffU +#define MATCH_MRET 0x30200073U +#define MASK_MRET 0xffffffffU +#define MATCH_DRET 0x7b200073U +#define MASK_DRET 0xffffffffU +#define MATCH_SFENCE_VM 0x10400073U +#define MASK_SFENCE_VM 0xfff07fffU +#define MATCH_WFI 0x10500073U +#define MASK_WFI 0xffffffffU +#define MATCH_CSRRW 0x1073U +#define MASK_CSRRW 0x707fU +#define MATCH_CSRRS 0x2073U +#define MASK_CSRRS 0x707fU +#define MATCH_CSRRC 0x3073U +#define MASK_CSRRC 0x707fU +#define MATCH_CSRRWI 0x5073U +#define MASK_CSRRWI 0x707fU +#define MATCH_CSRRSI 0x6073U +#define MASK_CSRRSI 0x707fU +#define MATCH_CSRRCI 0x7073U +#define MASK_CSRRCI 0x707fU +#define MATCH_FADD_S 0x53U +#define MASK_FADD_S 0xfe00007fU +#define MATCH_FSUB_S 0x8000053U +#define MASK_FSUB_S 0xfe00007fU +#define MATCH_FMUL_S 0x10000053U +#define MASK_FMUL_S 0xfe00007fU +#define MATCH_FDIV_S 0x18000053U +#define MASK_FDIV_S 0xfe00007fU +#define MATCH_FSGNJ_S 0x20000053U +#define MASK_FSGNJ_S 0xfe00707fU +#define MATCH_FSGNJN_S 0x20001053U +#define MASK_FSGNJN_S 0xfe00707fU +#define MATCH_FSGNJX_S 0x20002053U +#define MASK_FSGNJX_S 0xfe00707fU +#define MATCH_FMIN_S 0x28000053U +#define MASK_FMIN_S 0xfe00707fU +#define MATCH_FMAX_S 0x28001053U +#define MASK_FMAX_S 0xfe00707fU +#define MATCH_FSQRT_S 0x58000053U +#define MASK_FSQRT_S 0xfff0007fU +#define MATCH_FADD_D 0x2000053U +#define MASK_FADD_D 0xfe00007fU +#define MATCH_FSUB_D 0xa000053U +#define MASK_FSUB_D 0xfe00007fU +#define MATCH_FMUL_D 0x12000053U +#define MASK_FMUL_D 0xfe00007fU +#define MATCH_FDIV_D 0x1a000053U +#define MASK_FDIV_D 0xfe00007fU +#define MATCH_FSGNJ_D 0x22000053U +#define MASK_FSGNJ_D 0xfe00707fU +#define MATCH_FSGNJN_D 0x22001053U +#define MASK_FSGNJN_D 0xfe00707fU +#define MATCH_FSGNJX_D 0x22002053U +#define MASK_FSGNJX_D 0xfe00707fU +#define MATCH_FMIN_D 0x2a000053U +#define MASK_FMIN_D 0xfe00707fU +#define MATCH_FMAX_D 0x2a001053U +#define MASK_FMAX_D 0xfe00707fU +#define MATCH_FCVT_S_D 0x40100053U +#define MASK_FCVT_S_D 0xfff0007fU +#define MATCH_FCVT_D_S 0x42000053U +#define MASK_FCVT_D_S 0xfff0007fU +#define MATCH_FSQRT_D 0x5a000053U +#define MASK_FSQRT_D 0xfff0007fU +#define MATCH_FLE_S 0xa0000053U +#define MASK_FLE_S 0xfe00707fU +#define MATCH_FLT_S 0xa0001053U +#define MASK_FLT_S 0xfe00707fU +#define MATCH_FEQ_S 0xa0002053U +#define MASK_FEQ_S 0xfe00707fU +#define MATCH_FLE_D 0xa2000053U +#define MASK_FLE_D 0xfe00707fU +#define MATCH_FLT_D 0xa2001053U +#define MASK_FLT_D 0xfe00707fU +#define MATCH_FEQ_D 0xa2002053U +#define MASK_FEQ_D 0xfe00707fU +#define MATCH_FCVT_W_S 0xc0000053U +#define MASK_FCVT_W_S 0xfff0007fU +#define MATCH_FCVT_WU_S 0xc0100053U +#define MASK_FCVT_WU_S 0xfff0007fU +#define MATCH_FCVT_L_S 0xc0200053U +#define MASK_FCVT_L_S 0xfff0007fU +#define MATCH_FCVT_LU_S 0xc0300053U +#define MASK_FCVT_LU_S 0xfff0007fU +#define MATCH_FMV_X_S 0xe0000053U +#define MASK_FMV_X_S 0xfff0707fU +#define MATCH_FCLASS_S 0xe0001053U +#define MASK_FCLASS_S 0xfff0707fU +#define MATCH_FCVT_W_D 0xc2000053U +#define MASK_FCVT_W_D 0xfff0007fU +#define MATCH_FCVT_WU_D 0xc2100053U +#define MASK_FCVT_WU_D 0xfff0007fU +#define MATCH_FCVT_L_D 0xc2200053U +#define MASK_FCVT_L_D 0xfff0007fU +#define MATCH_FCVT_LU_D 0xc2300053U +#define MASK_FCVT_LU_D 0xfff0007fU +#define MATCH_FMV_X_D 0xe2000053U +#define MASK_FMV_X_D 0xfff0707fU +#define MATCH_FCLASS_D 0xe2001053U +#define MASK_FCLASS_D 0xfff0707fU +#define MATCH_FCVT_S_W 0xd0000053U +#define MASK_FCVT_S_W 0xfff0007fU +#define MATCH_FCVT_S_WU 0xd0100053U +#define MASK_FCVT_S_WU 0xfff0007fU +#define MATCH_FCVT_S_L 0xd0200053U +#define MASK_FCVT_S_L 0xfff0007fU +#define MATCH_FCVT_S_LU 0xd0300053U +#define MASK_FCVT_S_LU 0xfff0007fU +#define MATCH_FMV_S_X 0xf0000053U +#define MASK_FMV_S_X 0xfff0707fU +#define MATCH_FCVT_D_W 0xd2000053U +#define MASK_FCVT_D_W 0xfff0007fU +#define MATCH_FCVT_D_WU 0xd2100053U +#define MASK_FCVT_D_WU 0xfff0007fU +#define MATCH_FCVT_D_L 0xd2200053U +#define MASK_FCVT_D_L 0xfff0007fU +#define MATCH_FCVT_D_LU 0xd2300053U +#define MASK_FCVT_D_LU 0xfff0007fU +#define MATCH_FMV_D_X 0xf2000053U +#define MASK_FMV_D_X 0xfff0707fU +#define MATCH_FLW 0x2007U +#define MASK_FLW 0x707fU +#define MATCH_FLD 0x3007U +#define MASK_FLD 0x707fU +#define MATCH_FSW 0x2027U +#define MASK_FSW 0x707fU +#define MATCH_FSD 0x3027U +#define MASK_FSD 0x707fU +#define MATCH_FMADD_S 0x43U +#define MASK_FMADD_S 0x600007fU +#define MATCH_FMSUB_S 0x47U +#define MASK_FMSUB_S 0x600007fU +#define MATCH_FNMSUB_S 0x4bU +#define MASK_FNMSUB_S 0x600007fU +#define MATCH_FNMADD_S 0x4fU +#define MASK_FNMADD_S 0x600007fU +#define MATCH_FMADD_D 0x2000043U +#define MASK_FMADD_D 0x600007fU +#define MATCH_FMSUB_D 0x2000047U +#define MASK_FMSUB_D 0x600007fU +#define MATCH_FNMSUB_D 0x200004bU +#define MASK_FNMSUB_D 0x600007fU +#define MATCH_FNMADD_D 0x200004fU +#define MASK_FNMADD_D 0x600007fU +#define MATCH_C_NOP 0x1U +#define MASK_C_NOP 0xffffU +#define MATCH_C_ADDI16SP 0x6101U +#define MASK_C_ADDI16SP 0xef83U +#define MATCH_C_JR 0x8002U +#define MASK_C_JR 0xf07fU +#define MATCH_C_JALR 0x9002U +#define MASK_C_JALR 0xf07fU +#define MATCH_C_EBREAK 0x9002U +#define MASK_C_EBREAK 0xffffU +#define MATCH_C_LD 0x6000U +#define MASK_C_LD 0xe003U +#define MATCH_C_SD 0xe000U +#define MASK_C_SD 0xe003U +#define MATCH_C_ADDIW 0x2001U +#define MASK_C_ADDIW 0xe003U +#define MATCH_C_LDSP 0x6002U +#define MASK_C_LDSP 0xe003U +#define MATCH_C_SDSP 0xe002U +#define MASK_C_SDSP 0xe003U +#define MATCH_C_ADDI4SPN 0x0U +#define MASK_C_ADDI4SPN 0xe003U +#define MATCH_C_FLD 0x2000U +#define MASK_C_FLD 0xe003U +#define MATCH_C_LW 0x4000U +#define MASK_C_LW 0xe003U +#define MATCH_C_FLW 0x6000U +#define MASK_C_FLW 0xe003U +#define MATCH_C_FSD 0xa000U +#define MASK_C_FSD 0xe003U +#define MATCH_C_SW 0xc000U +#define MASK_C_SW 0xe003U +#define MATCH_C_FSW 0xe000U +#define MASK_C_FSW 0xe003U +#define MATCH_C_ADDI 0x1U +#define MASK_C_ADDI 0xe003U +#define MATCH_C_JAL 0x2001U +#define MASK_C_JAL 0xe003U +#define MATCH_C_LI 0x4001U +#define MASK_C_LI 0xe003U +#define MATCH_C_LUI 0x6001U +#define MASK_C_LUI 0xe003U +#define MATCH_C_SRLI 0x8001U +#define MASK_C_SRLI 0xec03U +#define MATCH_C_SRAI 0x8401U +#define MASK_C_SRAI 0xec03U +#define MATCH_C_ANDI 0x8801U +#define MASK_C_ANDI 0xec03U +#define MATCH_C_SUB 0x8c01U +#define MASK_C_SUB 0xfc63U +#define MATCH_C_XOR 0x8c21U +#define MASK_C_XOR 0xfc63U +#define MATCH_C_OR 0x8c41U +#define MASK_C_OR 0xfc63U +#define MATCH_C_AND 0x8c61U +#define MASK_C_AND 0xfc63U +#define MATCH_C_SUBW 0x9c01U +#define MASK_C_SUBW 0xfc63U +#define MATCH_C_ADDW 0x9c21U +#define MASK_C_ADDW 0xfc63U +#define MATCH_C_J 0xa001U +#define MASK_C_J 0xe003U +#define MATCH_C_BEQZ 0xc001U +#define MASK_C_BEQZ 0xe003U +#define MATCH_C_BNEZ 0xe001U +#define MASK_C_BNEZ 0xe003U +#define MATCH_C_SLLI 0x2U +#define MASK_C_SLLI 0xe003U +#define MATCH_C_FLDSP 0x2002U +#define MASK_C_FLDSP 0xe003U +#define MATCH_C_LWSP 0x4002U +#define MASK_C_LWSP 0xe003U +#define MATCH_C_FLWSP 0x6002U +#define MASK_C_FLWSP 0xe003U +#define MATCH_C_MV 0x8002U +#define MASK_C_MV 0xf003U +#define MATCH_C_ADD 0x9002U +#define MASK_C_ADD 0xf003U +#define MATCH_C_FSDSP 0xa002U +#define MASK_C_FSDSP 0xe003U +#define MATCH_C_SWSP 0xc002U +#define MASK_C_SWSP 0xe003U +#define MATCH_C_FSWSP 0xe002U +#define MASK_C_FSWSP 0xe003U +#define MATCH_CUSTOM0 0xbU +#define MASK_CUSTOM0 0x707fU +#define MATCH_CUSTOM0_RS1 0x200bU +#define MASK_CUSTOM0_RS1 0x707fU +#define MATCH_CUSTOM0_RS1_RS2 0x300bU +#define MASK_CUSTOM0_RS1_RS2 0x707fU +#define MATCH_CUSTOM0_RD 0x400bU +#define MASK_CUSTOM0_RD 0x707fU +#define MATCH_CUSTOM0_RD_RS1 0x600bU +#define MASK_CUSTOM0_RD_RS1 0x707fU +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700bU +#define MASK_CUSTOM0_RD_RS1_RS2 0x707fU +#define MATCH_CUSTOM1 0x2bU +#define MASK_CUSTOM1 0x707fU +#define MATCH_CUSTOM1_RS1 0x202bU +#define MASK_CUSTOM1_RS1 0x707fU +#define MATCH_CUSTOM1_RS1_RS2 0x302bU +#define MASK_CUSTOM1_RS1_RS2 0x707fU +#define MATCH_CUSTOM1_RD 0x402bU +#define MASK_CUSTOM1_RD 0x707fU +#define MATCH_CUSTOM1_RD_RS1 0x602bU +#define MASK_CUSTOM1_RD_RS1 0x707fU +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702bU +#define MASK_CUSTOM1_RD_RS1_RS2 0x707fU +#define MATCH_CUSTOM2 0x5bU +#define MASK_CUSTOM2 0x707fU +#define MATCH_CUSTOM2_RS1 0x205bU +#define MASK_CUSTOM2_RS1 0x707fU +#define MATCH_CUSTOM2_RS1_RS2 0x305bU +#define MASK_CUSTOM2_RS1_RS2 0x707fU +#define MATCH_CUSTOM2_RD 0x405bU +#define MASK_CUSTOM2_RD 0x707fU +#define MATCH_CUSTOM2_RD_RS1 0x605bU +#define MASK_CUSTOM2_RD_RS1 0x707fU +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705bU +#define MASK_CUSTOM2_RD_RS1_RS2 0x707fU +#define MATCH_CUSTOM3 0x7bU +#define MASK_CUSTOM3 0x707fU +#define MATCH_CUSTOM3_RS1 0x207bU +#define MASK_CUSTOM3_RS1 0x707fU +#define MATCH_CUSTOM3_RS1_RS2 0x307bU +#define MASK_CUSTOM3_RS1_RS2 0x707fU +#define MATCH_CUSTOM3_RD 0x407bU +#define MASK_CUSTOM3_RD 0x707fU +#define MATCH_CUSTOM3_RD_RS1 0x607bU +#define MASK_CUSTOM3_RD_RS1 0x707fU +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707bU +#define MASK_CUSTOM3_RD_RS1_RS2 0x707fU + +#if 0 +#define CSR_FFLAGS 0x1U +#define CSR_FRM 0x2U +#define CSR_FCSR 0x3U +#define CSR_CYCLE 0xc00U +#define CSR_TIME 0xc01U +#define CSR_INSTRET 0xc02U +#define CSR_HPMCOUNTER3 0xc03U +#define CSR_HPMCOUNTER4 0xc04U +#define CSR_HPMCOUNTER5 0xc05U +#define CSR_HPMCOUNTER6 0xc06U +#define CSR_HPMCOUNTER7 0xc07U +#define CSR_HPMCOUNTER8 0xc08U +#define CSR_HPMCOUNTER9 0xc09U +#define CSR_HPMCOUNTER10 0xc0aU +#define CSR_HPMCOUNTER11 0xc0bU +#define CSR_HPMCOUNTER12 0xc0cU +#define CSR_HPMCOUNTER13 0xc0dU +#define CSR_HPMCOUNTER14 0xc0eU +#define CSR_HPMCOUNTER15 0xc0fU +#define CSR_HPMCOUNTER16 0xc10U +#define CSR_HPMCOUNTER17 0xc11U +#define CSR_HPMCOUNTER18 0xc12U +#define CSR_HPMCOUNTER19 0xc13U +#define CSR_HPMCOUNTER20 0xc14U +#define CSR_HPMCOUNTER21 0xc15U +#define CSR_HPMCOUNTER22 0xc16U +#define CSR_HPMCOUNTER23 0xc17U +#define CSR_HPMCOUNTER24 0xc18U +#define CSR_HPMCOUNTER25 0xc19U +#define CSR_HPMCOUNTER26 0xc1aU +#define CSR_HPMCOUNTER27 0xc1bU +#define CSR_HPMCOUNTER28 0xc1cU +#define CSR_HPMCOUNTER29 0xc1dU +#define CSR_HPMCOUNTER30 0xc1eU +#define CSR_HPMCOUNTER31 0xc1fU +#define CSR_SSTATUS 0x100U +#define CSR_SIE 0x104U +#define CSR_STVEC 0x105U +#define CSR_SSCRATCH 0x140U +#define CSR_SEPC 0x141U +#define CSR_SCAUSE 0x142U +#define CSR_SBADADDR 0x143U +#define CSR_SIP 0x144U +#define CSR_SPTBR 0x180U +#define CSR_MSTATUS 0x300U +#define CSR_MISA 0x301U +#define CSR_MEDELEG 0x302U +#define CSR_MIDELEG 0x303U +#define CSR_MIE 0x304U +#define CSR_MTVEC 0x305U +#define CSR_MSCRATCH 0x340U +#define CSR_MEPC 0x341U +#define CSR_MCAUSE 0x342U +#define CSR_MBADADDR 0x343U +#define CSR_MIP 0x344U +#define CSR_TSELECT 0x7a0U +#define CSR_TDATA1 0x7a1U +#define CSR_TDATA2 0x7a2U +#define CSR_TDATA3 0x7a3U +#define CSR_DCSR 0x7b0U +#define CSR_DPC 0x7b1U +#define CSR_DSCRATCH 0x7b2U +#define CSR_MCYCLE 0xb00U +#define CSR_MINSTRET 0xb02U +#define CSR_MHPMCOUNTER3 0xb03U +#define CSR_MHPMCOUNTER4 0xb04U +#define CSR_MHPMCOUNTER5 0xb05U +#define CSR_MHPMCOUNTER6 0xb06U +#define CSR_MHPMCOUNTER7 0xb07U +#define CSR_MHPMCOUNTER8 0xb08U +#define CSR_MHPMCOUNTER9 0xb09U +#define CSR_MHPMCOUNTER10 0xb0aU +#define CSR_MHPMCOUNTER11 0xb0bU +#define CSR_MHPMCOUNTER12 0xb0cU +#define CSR_MHPMCOUNTER13 0xb0dU +#define CSR_MHPMCOUNTER14 0xb0eU +#define CSR_MHPMCOUNTER15 0xb0fU +#define CSR_MHPMCOUNTER16 0xb10U +#define CSR_MHPMCOUNTER17 0xb11U +#define CSR_MHPMCOUNTER18 0xb12U +#define CSR_MHPMCOUNTER19 0xb13U +#define CSR_MHPMCOUNTER20 0xb14U +#define CSR_MHPMCOUNTER21 0xb15U +#define CSR_MHPMCOUNTER22 0xb16U +#define CSR_MHPMCOUNTER23 0xb17U +#define CSR_MHPMCOUNTER24 0xb18U +#define CSR_MHPMCOUNTER25 0xb19U +#define CSR_MHPMCOUNTER26 0xb1aU +#define CSR_MHPMCOUNTER27 0xb1bU +#define CSR_MHPMCOUNTER28 0xb1cU +#define CSR_MHPMCOUNTER29 0xb1dU +#define CSR_MHPMCOUNTER30 0xb1eU +#define CSR_MHPMCOUNTER31 0xb1fU +#define CSR_MUCOUNTEREN 0x320U +#define CSR_MSCOUNTEREN 0x321U +#define CSR_MHPMEVENT3 0x323U +#define CSR_MHPMEVENT4 0x324U +#define CSR_MHPMEVENT5 0x325U +#define CSR_MHPMEVENT6 0x326U +#define CSR_MHPMEVENT7 0x327U +#define CSR_MHPMEVENT8 0x328U +#define CSR_MHPMEVENT9 0x329U +#define CSR_MHPMEVENT10 0x32aU +#define CSR_MHPMEVENT11 0x32bU +#define CSR_MHPMEVENT12 0x32cU +#define CSR_MHPMEVENT13 0x32dU +#define CSR_MHPMEVENT14 0x32eU +#define CSR_MHPMEVENT15 0x32fU +#define CSR_MHPMEVENT16 0x330U +#define CSR_MHPMEVENT17 0x331U +#define CSR_MHPMEVENT18 0x332U +#define CSR_MHPMEVENT19 0x333U +#define CSR_MHPMEVENT20 0x334U +#define CSR_MHPMEVENT21 0x335U +#define CSR_MHPMEVENT22 0x336U +#define CSR_MHPMEVENT23 0x337U +#define CSR_MHPMEVENT24 0x338U +#define CSR_MHPMEVENT25 0x339U +#define CSR_MHPMEVENT26 0x33aU +#define CSR_MHPMEVENT27 0x33bU +#define CSR_MHPMEVENT28 0x33cU +#define CSR_MHPMEVENT29 0x33dU +#define CSR_MHPMEVENT30 0x33eU +#define CSR_MHPMEVENT31 0x33fU +#define CSR_MVENDORID 0xf11U +#define CSR_MARCHID 0xf12U +#define CSR_MIMPID 0xf13U +#define CSR_MHARTID 0xf14U +#define CSR_CYCLEH 0xc80U +#define CSR_TIMEH 0xc81U +#define CSR_INSTRETH 0xc82U +#define CSR_HPMCOUNTER3H 0xc83U +#define CSR_HPMCOUNTER4H 0xc84U +#define CSR_HPMCOUNTER5H 0xc85U +#define CSR_HPMCOUNTER6H 0xc86U +#define CSR_HPMCOUNTER7H 0xc87U +#define CSR_HPMCOUNTER8H 0xc88U +#define CSR_HPMCOUNTER9H 0xc89U +#define CSR_HPMCOUNTER10H 0xc8aU +#define CSR_HPMCOUNTER11H 0xc8bU +#define CSR_HPMCOUNTER12H 0xc8cU +#define CSR_HPMCOUNTER13H 0xc8dU +#define CSR_HPMCOUNTER14H 0xc8eU +#define CSR_HPMCOUNTER15H 0xc8fU +#define CSR_HPMCOUNTER16H 0xc90U +#define CSR_HPMCOUNTER17H 0xc91U +#define CSR_HPMCOUNTER18H 0xc92U +#define CSR_HPMCOUNTER19H 0xc93U +#define CSR_HPMCOUNTER20H 0xc94U +#define CSR_HPMCOUNTER21H 0xc95U +#define CSR_HPMCOUNTER22H 0xc96U +#define CSR_HPMCOUNTER23H 0xc97U +#define CSR_HPMCOUNTER24H 0xc98U +#define CSR_HPMCOUNTER25H 0xc99U +#define CSR_HPMCOUNTER26H 0xc9aU +#define CSR_HPMCOUNTER27H 0xc9bU +#define CSR_HPMCOUNTER28H 0xc9cU +#define CSR_HPMCOUNTER29H 0xc9dU +#define CSR_HPMCOUNTER30H 0xc9eU +#define CSR_HPMCOUNTER31H 0xc9fU +#define CSR_MCYCLEH 0xb80U +#define CSR_MINSTRETH 0xb82U +#define CSR_MHPMCOUNTER3H 0xb83U +#define CSR_MHPMCOUNTER4H 0xb84U +#define CSR_MHPMCOUNTER5H 0xb85U +#define CSR_MHPMCOUNTER6H 0xb86U +#define CSR_MHPMCOUNTER7H 0xb87U +#define CSR_MHPMCOUNTER8H 0xb88U +#define CSR_MHPMCOUNTER9H 0xb89U +#define CSR_MHPMCOUNTER10H 0xb8aU +#define CSR_MHPMCOUNTER11H 0xb8bU +#define CSR_MHPMCOUNTER12H 0xb8cU +#define CSR_MHPMCOUNTER13H 0xb8dU +#define CSR_MHPMCOUNTER14H 0xb8eU +#define CSR_MHPMCOUNTER15H 0xb8fU +#define CSR_MHPMCOUNTER16H 0xb90U +#define CSR_MHPMCOUNTER17H 0xb91U +#define CSR_MHPMCOUNTER18H 0xb92U +#define CSR_MHPMCOUNTER19H 0xb93U +#define CSR_MHPMCOUNTER20H 0xb94U +#define CSR_MHPMCOUNTER21H 0xb95U +#define CSR_MHPMCOUNTER22H 0xb96U +#define CSR_MHPMCOUNTER23H 0xb97U +#define CSR_MHPMCOUNTER24H 0xb98U +#define CSR_MHPMCOUNTER25H 0xb99U +#define CSR_MHPMCOUNTER26H 0xb9aU +#define CSR_MHPMCOUNTER27H 0xb9bU +#define CSR_MHPMCOUNTER28H 0xb9cU +#define CSR_MHPMCOUNTER29H 0xb9dU +#define CSR_MHPMCOUNTER30H 0xb9eU +#define CSR_MHPMCOUNTER31H 0xb9fU +#endif + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#if defined(DECLARE_INSN) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#if defined(DECLARE_CSR) +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#if defined(DECLARE_CAUSE) +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c new file mode 100755 index 000000000..616348bf6 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/risc-v/src/k210/k210_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "k210_clockconfig.h" +#include "k210_sysctl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OSC_FREQ 26000000UL + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_cpu_clock = 390000000;//416000000; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k210_get_cpuclk + ****************************************************************************/ + +uint32_t k210_get_cpuclk(void) +{ + return g_cpu_clock; +} + +/**************************************************************************** + * Name: k210_get_pll0clk + ****************************************************************************/ + +#ifndef CONFIG_K210_WITH_QEMU +uint32_t k210_get_pll0clk(void) +{ + uint32_t pll0; + uint32_t nr; + uint32_t nf; + uint32_t od; + + pll0 = getreg32(K210_SYSCTL_PLL0); + nr = PLL_CLK_R(pll0) + 1; + nf = PLL_CLK_F(pll0) + 1; + od = PLL_CLK_OD(pll0) + 1; + + return OSC_FREQ / nr * nf / od; +} + +uint32_t k210_get_pll1clk(void) +{ + uint32_t pll1; + uint32_t nr; + uint32_t nf; + uint32_t od; + + pll1 = getreg32(K210_SYSCTL_PLL1); + nr = PLL_CLK_R(pll1) + 1; + nf = PLL_CLK_F(pll1) + 1; + od = PLL_CLK_OD(pll1) + 1; + + return OSC_FREQ / nr * nf / od; +} + +uint32_t k210_get_pll2clk(void) +{ + uint32_t pll2; + uint32_t nr; + uint32_t nf; + uint32_t od; + + pll2 = getreg32(K210_SYSCTL_PLL2); + nr = PLL_CLK_R(pll2) + 1; + nf = PLL_CLK_F(pll2) + 1; + od = PLL_CLK_OD(pll2) + 1; + + return OSC_FREQ / nr * nf / od; +} + +#endif + +/**************************************************************************** + * Name: k210_clockconfig + ****************************************************************************/ + +void k210_clockconfig(void) +{ +#ifndef CONFIG_K210_WITH_QEMU + uint32_t clksel0; + + /* Obtain clock selector for ACLK */ + clksel0 = getreg32(K210_SYSCTL_CLKSEL0); + + if (1 == CLKSEL0_ACLK_SEL(clksel0)) + { + /* PLL0 selected */ + g_cpu_clock = k210_get_pll0clk() / 2; + + syslog(LOG_NOTICE, "g_cpu clock = %d sel %#x\r\n", g_cpu_clock, clksel0); + } + else + { + /* OSC selected */ + + g_cpu_clock = OSC_FREQ; + } +#endif +} + +void k210_sysctl_init(void) +{ +// sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL); +// sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL); +// sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL); + sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2); + +// sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18); +// sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18); +// sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18); +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.h new file mode 100755 index 000000000..5c4933a0c --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_clockconfig.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/risc-v/src/k210/k210_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_K210_K210_CLOCKCONFIG_H +#define __ARCH_RISCV_SRC_K210_K210_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "k210_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +EXTERN uint32_t k210_get_cpuclk(void); +EXTERN uint32_t k210_get_pll0clk(void); +EXTERN void k210_clockconfig(void); +EXTERN void k210_sysctl_init(void); + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_K210_K210_CLOCKCONFIG_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_gpiohs.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_gpiohs.h index 43bd7eb60..11a6e63f5 100644 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_gpiohs.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_gpiohs.h @@ -38,6 +38,8 @@ #include #include "k210_gpio_common.h" +#define HS_GPIO(n) (K210_IO_FUNC_GPIOHS0 + n) + /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_memorymap.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_memorymap.h new file mode 100755 index 000000000..11f3b0634 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_memorymap.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/k210/k210_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_K210_K210_MEMORYMAP_H +#define __ARCH_RISCV_SRC_K210_K210_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "riscv_internal.h" +#include "hardware/k210_memorymap.h" +#include "hardware/k210_uart.h" +#include "hardware/k210_clint.h" +#include "hardware/k210_plic.h" +//#include "hardware/k210_sysctl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Idle thread stack starts from _ebss */ + +#ifndef __ASSEMBLY__ +#define K210_IDLESTACK_BASE (uintptr_t)&_ebss +#else +#define K210_IDLESTACK_BASE _ebss +#endif + +#define K210_IDLESTACK0_BASE (K210_IDLESTACK_BASE) +#define K210_IDLESTACK0_TOP (K210_IDLESTACK0_BASE + CONFIG_IDLETHREAD_STACKSIZE) + +#endif /* __ARCH_RISCV_SRC_K210_K210_MEMORYMAP_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_sysctl.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_sysctl.c new file mode 100755 index 000000000..509b35c0e --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_sysctl.c @@ -0,0 +1,1853 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include "k210_sysctl.h" + +#define SYSCTRL_CLOCK_FREQ_IN0 (26000000UL) + +const uint8_t get_select_pll2[] = +{ + [SYSCTL_SOURCE_IN0] = 0, + [SYSCTL_SOURCE_PLL0] = 1, + [SYSCTL_SOURCE_PLL1] = 2, +}; + +const uint8_t get_source_pll2[] = +{ + [0] = SYSCTL_SOURCE_IN0, + [1] = SYSCTL_SOURCE_PLL0, + [2] = SYSCTL_SOURCE_PLL1, +}; + +const uint8_t get_select_aclk[] = +{ + [SYSCTL_SOURCE_IN0] = 0, + [SYSCTL_SOURCE_PLL0] = 1, +}; + +const uint8_t get_source_aclk[] = +{ + [0] = SYSCTL_SOURCE_IN0, + [1] = SYSCTL_SOURCE_PLL0, +}; + +volatile sysctl_t *const sysctl = (volatile sysctl_t *)SYSCTL_BASE_ADDR; + +uint32_t sysctl_get_git_id(void) +{ + return sysctl->git_id.git_id; +} + +uint32_t sysctl_get_freq(void) +{ + return sysctl->clk_freq.clk_freq; +} + +static void sysctl_reset_ctl(sysctl_reset_t reset, uint8_t rst_value) +{ + switch(reset) + { + case SYSCTL_RESET_SOC: + sysctl->soft_reset.soft_reset = rst_value; + break; + case SYSCTL_RESET_ROM: + sysctl->peri_reset.rom_reset = rst_value; + break; + case SYSCTL_RESET_DMA: + sysctl->peri_reset.dma_reset = rst_value; + break; + case SYSCTL_RESET_AI: + sysctl->peri_reset.ai_reset = rst_value; + break; + case SYSCTL_RESET_DVP: + sysctl->peri_reset.dvp_reset = rst_value; + break; + case SYSCTL_RESET_FFT: + sysctl->peri_reset.fft_reset = rst_value; + break; + case SYSCTL_RESET_GPIO: + sysctl->peri_reset.gpio_reset = rst_value; + break; + case SYSCTL_RESET_SPI0: + sysctl->peri_reset.spi0_reset = rst_value; + break; + case SYSCTL_RESET_SPI1: + sysctl->peri_reset.spi1_reset = rst_value; + break; + case SYSCTL_RESET_SPI2: + sysctl->peri_reset.spi2_reset = rst_value; + break; + case SYSCTL_RESET_SPI3: + sysctl->peri_reset.spi3_reset = rst_value; + break; + case SYSCTL_RESET_I2S0: + sysctl->peri_reset.i2s0_reset = rst_value; + break; + case SYSCTL_RESET_I2S1: + sysctl->peri_reset.i2s1_reset = rst_value; + break; + case SYSCTL_RESET_I2S2: + sysctl->peri_reset.i2s2_reset = rst_value; + break; + case SYSCTL_RESET_I2C0: + sysctl->peri_reset.i2c0_reset = rst_value; + break; + case SYSCTL_RESET_I2C1: + sysctl->peri_reset.i2c1_reset = rst_value; + break; + case SYSCTL_RESET_I2C2: + sysctl->peri_reset.i2c2_reset = rst_value; + break; + case SYSCTL_RESET_UART1: + sysctl->peri_reset.uart1_reset = rst_value; + break; + case SYSCTL_RESET_UART2: + sysctl->peri_reset.uart2_reset = rst_value; + break; + case SYSCTL_RESET_UART3: + sysctl->peri_reset.uart3_reset = rst_value; + break; + case SYSCTL_RESET_AES: + sysctl->peri_reset.aes_reset = rst_value; + break; + case SYSCTL_RESET_FPIOA: + sysctl->peri_reset.fpioa_reset = rst_value; + break; + case SYSCTL_RESET_TIMER0: + sysctl->peri_reset.timer0_reset = rst_value; + break; + case SYSCTL_RESET_TIMER1: + sysctl->peri_reset.timer1_reset = rst_value; + break; + case SYSCTL_RESET_TIMER2: + sysctl->peri_reset.timer2_reset = rst_value; + break; + case SYSCTL_RESET_WDT0: + sysctl->peri_reset.wdt0_reset = rst_value; + break; + case SYSCTL_RESET_WDT1: + sysctl->peri_reset.wdt1_reset = rst_value; + break; + case SYSCTL_RESET_SHA: + sysctl->peri_reset.sha_reset = rst_value; + break; + case SYSCTL_RESET_RTC: + sysctl->peri_reset.rtc_reset = rst_value; + break; + + default: + break; + } +} + +void sysctl_reset(sysctl_reset_t reset) +{ + sysctl_reset_ctl(reset, 1); + usleep(10); + sysctl_reset_ctl(reset, 0); +} + +static int sysctl_clock_bus_en(sysctl_clock_t clock, uint8_t en) +{ + /* + * The timer is under APB0, to prevent apb0_clk_en1 and apb0_clk_en0 + * on same register, we split it to peripheral and central two + * registers, to protect CPU close apb0 clock accidentally. + * + * The apb0_clk_en0 and apb0_clk_en1 have same function, + * one of them set, the APB0 clock enable. + */ + + /* The APB clock should carefully disable */ + if(en) + { + switch(clock) + { + /* + * These peripheral devices are under APB0 + * GPIO, UART1, UART2, UART3, SPI_SLAVE, I2S0, I2S1, + * I2S2, I2C0, I2C1, I2C2, FPIOA, SHA256, TIMER0, + * TIMER1, TIMER2 + */ + case SYSCTL_CLOCK_GPIO: + case SYSCTL_CLOCK_SPI2: + case SYSCTL_CLOCK_I2S0: + case SYSCTL_CLOCK_I2S1: + case SYSCTL_CLOCK_I2S2: + case SYSCTL_CLOCK_I2C0: + case SYSCTL_CLOCK_I2C1: + case SYSCTL_CLOCK_I2C2: + case SYSCTL_CLOCK_UART1: + case SYSCTL_CLOCK_UART2: + case SYSCTL_CLOCK_UART3: + case SYSCTL_CLOCK_FPIOA: + case SYSCTL_CLOCK_TIMER0: + case SYSCTL_CLOCK_TIMER1: + case SYSCTL_CLOCK_TIMER2: + case SYSCTL_CLOCK_SHA: + sysctl->clk_en_cent.apb0_clk_en = en; + break; + + /* + * These peripheral devices are under APB1 + * WDT, AES, OTP, DVP, SYSCTL + */ + case SYSCTL_CLOCK_AES: + case SYSCTL_CLOCK_WDT0: + case SYSCTL_CLOCK_WDT1: + case SYSCTL_CLOCK_OTP: + case SYSCTL_CLOCK_RTC: + sysctl->clk_en_cent.apb1_clk_en = en; + break; + + /* + * These peripheral devices are under APB2 + * SPI0, SPI1 + */ + case SYSCTL_CLOCK_SPI0: + case SYSCTL_CLOCK_SPI1: + sysctl->clk_en_cent.apb2_clk_en = en; + break; + + default: + break; + } + } + + return 0; +} + +static int sysctl_clock_device_en(sysctl_clock_t clock, uint8_t en) +{ + switch(clock) + { + /* + * These devices are PLL + */ + case SYSCTL_CLOCK_PLL0: + sysctl->pll0.pll_out_en0 = en; + break; + case SYSCTL_CLOCK_PLL1: + sysctl->pll1.pll_out_en1 = en; + break; + case SYSCTL_CLOCK_PLL2: + sysctl->pll2.pll_out_en2 = en; + break; + + /* + * These devices are CPU, SRAM, APB bus, ROM, DMA, AI + */ + case SYSCTL_CLOCK_CPU: + sysctl->clk_en_cent.cpu_clk_en = en; + break; + case SYSCTL_CLOCK_SRAM0: + sysctl->clk_en_cent.sram0_clk_en = en; + break; + case SYSCTL_CLOCK_SRAM1: + sysctl->clk_en_cent.sram1_clk_en = en; + break; + case SYSCTL_CLOCK_APB0: + sysctl->clk_en_cent.apb0_clk_en = en; + break; + case SYSCTL_CLOCK_APB1: + sysctl->clk_en_cent.apb1_clk_en = en; + break; + case SYSCTL_CLOCK_APB2: + sysctl->clk_en_cent.apb2_clk_en = en; + break; + case SYSCTL_CLOCK_ROM: + sysctl->clk_en_peri.rom_clk_en = en; + break; + case SYSCTL_CLOCK_DMA: + sysctl->clk_en_peri.dma_clk_en = en; + break; + case SYSCTL_CLOCK_AI: + sysctl->clk_en_peri.ai_clk_en = en; + break; + case SYSCTL_CLOCK_DVP: + sysctl->clk_en_peri.dvp_clk_en = en; + break; + case SYSCTL_CLOCK_FFT: + sysctl->clk_en_peri.fft_clk_en = en; + break; + case SYSCTL_CLOCK_SPI3: + sysctl->clk_en_peri.spi3_clk_en = en; + break; + + /* + * These peripheral devices are under APB0 + * GPIO, UART1, UART2, UART3, SPI_SLAVE, I2S0, I2S1, + * I2S2, I2C0, I2C1, I2C2, FPIOA, SHA256, TIMER0, + * TIMER1, TIMER2 + */ + case SYSCTL_CLOCK_GPIO: + sysctl->clk_en_peri.gpio_clk_en = en; + break; + case SYSCTL_CLOCK_SPI2: + sysctl->clk_en_peri.spi2_clk_en = en; + break; + case SYSCTL_CLOCK_I2S0: + sysctl->clk_en_peri.i2s0_clk_en = en; + break; + case SYSCTL_CLOCK_I2S1: + sysctl->clk_en_peri.i2s1_clk_en = en; + break; + case SYSCTL_CLOCK_I2S2: + sysctl->clk_en_peri.i2s2_clk_en = en; + break; + case SYSCTL_CLOCK_I2C0: + sysctl->clk_en_peri.i2c0_clk_en = en; + break; + case SYSCTL_CLOCK_I2C1: + sysctl->clk_en_peri.i2c1_clk_en = en; + break; + case SYSCTL_CLOCK_I2C2: + sysctl->clk_en_peri.i2c2_clk_en = en; + break; + case SYSCTL_CLOCK_UART1: + sysctl->clk_en_peri.uart1_clk_en = en; + break; + case SYSCTL_CLOCK_UART2: + sysctl->clk_en_peri.uart2_clk_en = en; + break; + case SYSCTL_CLOCK_UART3: + sysctl->clk_en_peri.uart3_clk_en = en; + break; + case SYSCTL_CLOCK_FPIOA: + sysctl->clk_en_peri.fpioa_clk_en = en; + break; + case SYSCTL_CLOCK_TIMER0: + sysctl->clk_en_peri.timer0_clk_en = en; + break; + case SYSCTL_CLOCK_TIMER1: + sysctl->clk_en_peri.timer1_clk_en = en; + break; + case SYSCTL_CLOCK_TIMER2: + sysctl->clk_en_peri.timer2_clk_en = en; + break; + case SYSCTL_CLOCK_SHA: + sysctl->clk_en_peri.sha_clk_en = en; + break; + + /* + * These peripheral devices are under APB1 + * WDT, AES, OTP, DVP, SYSCTL + */ + case SYSCTL_CLOCK_AES: + sysctl->clk_en_peri.aes_clk_en = en; + break; + case SYSCTL_CLOCK_WDT0: + sysctl->clk_en_peri.wdt0_clk_en = en; + break; + case SYSCTL_CLOCK_WDT1: + sysctl->clk_en_peri.wdt1_clk_en = en; + break; + case SYSCTL_CLOCK_OTP: + sysctl->clk_en_peri.otp_clk_en = en; + break; + case SYSCTL_CLOCK_RTC: + sysctl->clk_en_peri.rtc_clk_en = en; + break; + + /* + * These peripheral devices are under APB2 + * SPI0, SPI1 + */ + case SYSCTL_CLOCK_SPI0: + sysctl->clk_en_peri.spi0_clk_en = en; + break; + case SYSCTL_CLOCK_SPI1: + sysctl->clk_en_peri.spi1_clk_en = en; + break; + + default: + break; + } + + return 0; +} + +int sysctl_clock_enable(sysctl_clock_t clock) +{ + if(clock >= SYSCTL_CLOCK_MAX) + return -1; + sysctl_clock_bus_en(clock, 1); + sysctl_clock_device_en(clock, 1); + return 0; +} + +int sysctl_clock_disable(sysctl_clock_t clock) +{ + if(clock >= SYSCTL_CLOCK_MAX) + return -1; + sysctl_clock_device_en(clock, 0); + return 0; +} + +int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold) +{ + int result = 0; + switch(which) + { + /* + * These threshold is 2 bit width + */ + case SYSCTL_THRESHOLD_ACLK: + sysctl->clk_sel0.aclk_divider_sel = (uint8_t)threshold & 0x03; + break; + + /* + * These threshold is 3 bit width + */ + case SYSCTL_THRESHOLD_APB0: + sysctl->clk_sel0.apb0_clk_sel = (uint8_t)threshold & 0x07; + break; + case SYSCTL_THRESHOLD_APB1: + sysctl->clk_sel0.apb1_clk_sel = (uint8_t)threshold & 0x07; + break; + case SYSCTL_THRESHOLD_APB2: + sysctl->clk_sel0.apb2_clk_sel = (uint8_t)threshold & 0x07; + break; + + /* + * These threshold is 4 bit width + */ + case SYSCTL_THRESHOLD_SRAM0: + sysctl->clk_th0.sram0_gclk_threshold = (uint8_t)threshold & 0x0F; + break; + case SYSCTL_THRESHOLD_SRAM1: + sysctl->clk_th0.sram1_gclk_threshold = (uint8_t)threshold & 0x0F; + break; + case SYSCTL_THRESHOLD_AI: + sysctl->clk_th0.ai_gclk_threshold = (uint8_t)threshold & 0x0F; + break; + case SYSCTL_THRESHOLD_DVP: + sysctl->clk_th0.dvp_gclk_threshold = (uint8_t)threshold & 0x0F; + break; + case SYSCTL_THRESHOLD_ROM: + sysctl->clk_th0.rom_gclk_threshold = (uint8_t)threshold & 0x0F; + break; + + /* + * These threshold is 8 bit width + */ + case SYSCTL_THRESHOLD_SPI0: + sysctl->clk_th1.spi0_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_SPI1: + sysctl->clk_th1.spi1_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_SPI2: + sysctl->clk_th1.spi2_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_SPI3: + sysctl->clk_th1.spi3_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_TIMER0: + sysctl->clk_th2.timer0_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_TIMER1: + sysctl->clk_th2.timer1_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_TIMER2: + sysctl->clk_th2.timer2_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_I2S0_M: + sysctl->clk_th4.i2s0_mclk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_I2S1_M: + sysctl->clk_th4.i2s1_mclk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_I2S2_M: + sysctl->clk_th5.i2s2_mclk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_I2C0: + sysctl->clk_th5.i2c0_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_I2C1: + sysctl->clk_th5.i2c1_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_I2C2: + sysctl->clk_th5.i2c2_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_WDT0: + sysctl->clk_th6.wdt0_clk_threshold = (uint8_t)threshold; + break; + case SYSCTL_THRESHOLD_WDT1: + sysctl->clk_th6.wdt1_clk_threshold = (uint8_t)threshold; + break; + + /* + * These threshold is 16 bit width + */ + case SYSCTL_THRESHOLD_I2S0: + sysctl->clk_th3.i2s0_clk_threshold = (uint16_t)threshold; + break; + case SYSCTL_THRESHOLD_I2S1: + sysctl->clk_th3.i2s1_clk_threshold = (uint16_t)threshold; + break; + case SYSCTL_THRESHOLD_I2S2: + sysctl->clk_th4.i2s2_clk_threshold = (uint16_t)threshold; + break; + + default: + result = -1; + break; + } + return result; +} + +int sysctl_clock_get_threshold(sysctl_threshold_t which) +{ + int threshold = 0; + + switch(which) + { + /* + * Select and get threshold value + */ + case SYSCTL_THRESHOLD_ACLK: + threshold = (int)sysctl->clk_sel0.aclk_divider_sel; + break; + case SYSCTL_THRESHOLD_APB0: + threshold = (int)sysctl->clk_sel0.apb0_clk_sel; + break; + case SYSCTL_THRESHOLD_APB1: + threshold = (int)sysctl->clk_sel0.apb1_clk_sel; + break; + case SYSCTL_THRESHOLD_APB2: + threshold = (int)sysctl->clk_sel0.apb2_clk_sel; + break; + case SYSCTL_THRESHOLD_SRAM0: + threshold = (int)sysctl->clk_th0.sram0_gclk_threshold; + break; + case SYSCTL_THRESHOLD_SRAM1: + threshold = (int)sysctl->clk_th0.sram1_gclk_threshold; + break; + case SYSCTL_THRESHOLD_AI: + threshold = (int)sysctl->clk_th0.ai_gclk_threshold; + break; + case SYSCTL_THRESHOLD_DVP: + threshold = (int)sysctl->clk_th0.dvp_gclk_threshold; + break; + case SYSCTL_THRESHOLD_ROM: + threshold = (int)sysctl->clk_th0.rom_gclk_threshold; + break; + case SYSCTL_THRESHOLD_SPI0: + threshold = (int)sysctl->clk_th1.spi0_clk_threshold; + break; + case SYSCTL_THRESHOLD_SPI1: + threshold = (int)sysctl->clk_th1.spi1_clk_threshold; + break; + case SYSCTL_THRESHOLD_SPI2: + threshold = (int)sysctl->clk_th1.spi2_clk_threshold; + break; + case SYSCTL_THRESHOLD_SPI3: + threshold = (int)sysctl->clk_th1.spi3_clk_threshold; + break; + case SYSCTL_THRESHOLD_TIMER0: + threshold = (int)sysctl->clk_th2.timer0_clk_threshold; + break; + case SYSCTL_THRESHOLD_TIMER1: + threshold = (int)sysctl->clk_th2.timer1_clk_threshold; + break; + case SYSCTL_THRESHOLD_TIMER2: + threshold = (int)sysctl->clk_th2.timer2_clk_threshold; + break; + case SYSCTL_THRESHOLD_I2S0: + threshold = (int)sysctl->clk_th3.i2s0_clk_threshold; + break; + case SYSCTL_THRESHOLD_I2S1: + threshold = (int)sysctl->clk_th3.i2s1_clk_threshold; + break; + case SYSCTL_THRESHOLD_I2S2: + threshold = (int)sysctl->clk_th4.i2s2_clk_threshold; + break; + case SYSCTL_THRESHOLD_I2S0_M: + threshold = (int)sysctl->clk_th4.i2s0_mclk_threshold; + break; + case SYSCTL_THRESHOLD_I2S1_M: + threshold = (int)sysctl->clk_th4.i2s1_mclk_threshold; + break; + case SYSCTL_THRESHOLD_I2S2_M: + threshold = (int)sysctl->clk_th5.i2s2_mclk_threshold; + break; + case SYSCTL_THRESHOLD_I2C0: + threshold = (int)sysctl->clk_th5.i2c0_clk_threshold; + break; + case SYSCTL_THRESHOLD_I2C1: + threshold = (int)sysctl->clk_th5.i2c1_clk_threshold; + break; + case SYSCTL_THRESHOLD_I2C2: + threshold = (int)sysctl->clk_th5.i2c2_clk_threshold; + break; + case SYSCTL_THRESHOLD_WDT0: + threshold = (int)sysctl->clk_th6.wdt0_clk_threshold; + break; + case SYSCTL_THRESHOLD_WDT1: + threshold = (int)sysctl->clk_th6.wdt1_clk_threshold; + break; + + default: + break; + } + + return threshold; +} + +int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select) +{ + int result = 0; + switch(which) + { + /* + * These clock select is 1 bit width + */ + case SYSCTL_CLOCK_SELECT_PLL0_BYPASS: + sysctl->pll0.pll_bypass0 = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_PLL1_BYPASS: + sysctl->pll1.pll_bypass1 = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_PLL2_BYPASS: + sysctl->pll2.pll_bypass2 = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_ACLK: + sysctl->clk_sel0.aclk_sel = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_SPI3: + sysctl->clk_sel0.spi3_clk_sel = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_TIMER0: + sysctl->clk_sel0.timer0_clk_sel = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_TIMER1: + sysctl->clk_sel0.timer1_clk_sel = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_TIMER2: + sysctl->clk_sel0.timer2_clk_sel = select & 0x01; + break; + case SYSCTL_CLOCK_SELECT_SPI3_SAMPLE: + sysctl->clk_sel1.spi3_sample_clk_sel = select & 0x01; + break; + + /* + * These clock select is 2 bit width + */ + case SYSCTL_CLOCK_SELECT_PLL2: + sysctl->pll2.pll_ckin_sel2 = select & 0x03; + break; + + default: + result = -1; + break; + } + + return result; +} + +int sysctl_clock_get_clock_select(sysctl_clock_select_t which) +{ + int clock_select = 0; + + switch(which) + { + /* + * Select and get clock select value + */ + case SYSCTL_CLOCK_SELECT_PLL0_BYPASS: + clock_select = (int)sysctl->pll0.pll_bypass0; + break; + case SYSCTL_CLOCK_SELECT_PLL1_BYPASS: + clock_select = (int)sysctl->pll1.pll_bypass1; + break; + case SYSCTL_CLOCK_SELECT_PLL2_BYPASS: + clock_select = (int)sysctl->pll2.pll_bypass2; + break; + case SYSCTL_CLOCK_SELECT_PLL2: + clock_select = (int)sysctl->pll2.pll_ckin_sel2; + break; + case SYSCTL_CLOCK_SELECT_ACLK: + clock_select = (int)sysctl->clk_sel0.aclk_sel; + break; + case SYSCTL_CLOCK_SELECT_SPI3: + clock_select = (int)sysctl->clk_sel0.spi3_clk_sel; + break; + case SYSCTL_CLOCK_SELECT_TIMER0: + clock_select = (int)sysctl->clk_sel0.timer0_clk_sel; + break; + case SYSCTL_CLOCK_SELECT_TIMER1: + clock_select = (int)sysctl->clk_sel0.timer1_clk_sel; + break; + case SYSCTL_CLOCK_SELECT_TIMER2: + clock_select = (int)sysctl->clk_sel0.timer2_clk_sel; + break; + case SYSCTL_CLOCK_SELECT_SPI3_SAMPLE: + clock_select = (int)sysctl->clk_sel1.spi3_sample_clk_sel; + break; + + default: + break; + } + + return clock_select; +} + +uint32_t sysctl_clock_source_get_freq(sysctl_clock_source_t input) +{ + uint32_t result; + + switch(input) + { + case SYSCTL_SOURCE_IN0: + result = SYSCTRL_CLOCK_FREQ_IN0; + break; + case SYSCTL_SOURCE_PLL0: + result = sysctl_pll_get_freq(SYSCTL_PLL0); + break; + case SYSCTL_SOURCE_PLL1: + result = sysctl_pll_get_freq(SYSCTL_PLL1); + break; + case SYSCTL_SOURCE_PLL2: + result = sysctl_pll_get_freq(SYSCTL_PLL2); + break; + case SYSCTL_SOURCE_ACLK: + result = sysctl_clock_get_freq(SYSCTL_CLOCK_ACLK); + break; + default: + result = 0; + break; + } + return result; +} + +static int sysctl_pll_is_lock(sysctl_pll_t pll) +{ + /* + * All bit enable means PLL lock + * + * struct pll_lock_t + * { + * uint8_t overflow : 1; + * uint8_t rfslip : 1; + * uint8_t fbslip : 1; + * }; + * + */ + + if(pll >= SYSCTL_PLL_MAX) + return 0; + + switch(pll) + { + case SYSCTL_PLL0: + return sysctl->pll_lock.pll_lock0 == 3; + + case SYSCTL_PLL1: + return sysctl->pll_lock.pll_lock1 & 1; + + case SYSCTL_PLL2: + return sysctl->pll_lock.pll_lock2 & 1; + + default: + break; + } + + return 0; +} + +static int sysctl_pll_clear_slip(sysctl_pll_t pll) +{ + if(pll >= SYSCTL_PLL_MAX) + return -1; + + switch(pll) + { + case SYSCTL_PLL0: + sysctl->pll_lock.pll_slip_clear0 = 1; + break; + + case SYSCTL_PLL1: + sysctl->pll_lock.pll_slip_clear1 = 1; + break; + + case SYSCTL_PLL2: + sysctl->pll_lock.pll_slip_clear2 = 1; + break; + + default: + break; + } + + return sysctl_pll_is_lock(pll) ? 0 : -1; +} + +int sysctl_pll_enable(sysctl_pll_t pll) +{ + /* + * ---+ + * PWRDN | + * +------------------------------------------------------------- + * ^ + * | + * | + * t1 + * +------------------+ + * RESET | | + * ----------+ +----------------------------------- + * ^ ^ ^ + * |<----- t_rst ---->|<---------- t_lock ---------->| + * | | | + * t2 t3 t4 + */ + + if(pll >= SYSCTL_PLL_MAX) + return -1; + + switch(pll) + { + case SYSCTL_PLL0: + /* Do not bypass PLL */ + sysctl->pll0.pll_bypass0 = 0; + /* + * Power on the PLL, negtive from PWRDN + * 0 is power off + * 1 is power on + */ + sysctl->pll0.pll_pwrd0 = 1; + /* + * Reset trigger of the PLL, connected RESET + * 0 is free + * 1 is reset + */ + sysctl->pll0.pll_reset0 = 0; + sysctl->pll0.pll_reset0 = 1; + asm volatile("nop"); + asm volatile("nop"); + sysctl->pll0.pll_reset0 = 0; + break; + + case SYSCTL_PLL1: + /* Do not bypass PLL */ + sysctl->pll1.pll_bypass1 = 0; + /* + * Power on the PLL, negtive from PWRDN + * 0 is power off + * 1 is power on + */ + sysctl->pll1.pll_pwrd1 = 1; + /* + * Reset trigger of the PLL, connected RESET + * 0 is free + * 1 is reset + */ + sysctl->pll1.pll_reset1 = 0; + sysctl->pll1.pll_reset1 = 1; + asm volatile("nop"); + asm volatile("nop"); + sysctl->pll1.pll_reset1 = 0; + break; + + case SYSCTL_PLL2: + /* Do not bypass PLL */ + sysctl->pll2.pll_bypass2 = 0; + /* + * Power on the PLL, negtive from PWRDN + * 0 is power off + * 1 is power on + */ + sysctl->pll2.pll_pwrd2 = 1; + /* + * Reset trigger of the PLL, connected RESET + * 0 is free + * 1 is reset + */ + sysctl->pll2.pll_reset2 = 0; + sysctl->pll2.pll_reset2 = 1; + asm volatile("nop"); + asm volatile("nop"); + sysctl->pll2.pll_reset2 = 0; + break; + + default: + break; + } + + return 0; +} + +int sysctl_pll_disable(sysctl_pll_t pll) +{ + if(pll >= SYSCTL_PLL_MAX) + return -1; + + switch(pll) + { + case SYSCTL_PLL0: + /* Bypass PLL */ + sysctl->pll0.pll_bypass0 = 1; + /* + * Power on the PLL, negtive from PWRDN + * 0 is power off + * 1 is power on + */ + sysctl->pll0.pll_pwrd0 = 0; + break; + + case SYSCTL_PLL1: + /* Bypass PLL */ + sysctl->pll1.pll_bypass1 = 1; + /* + * Power on the PLL, negtive from PWRDN + * 0 is power off + * 1 is power on + */ + sysctl->pll1.pll_pwrd1 = 0; + break; + + case SYSCTL_PLL2: + /* Bypass PLL */ + sysctl->pll2.pll_bypass2 = 1; + /* + * Power on the PLL, negtive from PWRDN + * 0 is power off + * 1 is power on + */ + sysctl->pll2.pll_pwrd2 = 0; + break; + + default: + break; + } + + return 0; +} + +uint32_t sysctl_pll_get_freq(sysctl_pll_t pll) +{ + uint32_t freq_in = 0, freq_out = 0; + uint32_t nr = 0, nf = 0, od = 0; + uint8_t select = 0; + + if(pll >= SYSCTL_PLL_MAX) + return 0; + + switch(pll) + { + case SYSCTL_PLL0: + freq_in = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + nr = sysctl->pll0.clkr0 + 1; + nf = sysctl->pll0.clkf0 + 1; + od = sysctl->pll0.clkod0 + 1; + break; + + case SYSCTL_PLL1: + freq_in = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + nr = sysctl->pll1.clkr1 + 1; + nf = sysctl->pll1.clkf1 + 1; + od = sysctl->pll1.clkod1 + 1; + break; + + case SYSCTL_PLL2: + /* + * Get input freq accroding select register + */ + select = sysctl->pll2.pll_ckin_sel2; + if(select < sizeof(get_source_pll2)) + freq_in = sysctl_clock_source_get_freq(get_source_pll2[select]); + else + return 0; + + nr = sysctl->pll2.clkr2 + 1; + nf = sysctl->pll2.clkf2 + 1; + od = sysctl->pll2.clkod2 + 1; + break; + + default: + break; + } + + /* + * Get final PLL output freq + * FOUT = FIN / NR * NF / OD + */ + freq_out = (double)freq_in / (double)nr * (double)nf / (double)od; + return freq_out; +} + +static uint32_t sysctl_pll_source_set_freq(sysctl_pll_t pll, sysctl_clock_source_t source, uint32_t freq) +{ + uint32_t freq_in = 0; + + if(pll >= SYSCTL_PLL_MAX) + return 0; + + if(source >= SYSCTL_SOURCE_MAX) + return 0; + + switch(pll) + { + case SYSCTL_PLL0: + case SYSCTL_PLL1: + /* + * Check input clock source + */ + if(source != SYSCTL_SOURCE_IN0) + return 0; + freq_in = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + /* + * Check input clock freq + */ + if(freq_in == 0) + return 0; + break; + + case SYSCTL_PLL2: + /* + * Check input clock source + */ + if(source < sizeof(get_select_pll2)) + freq_in = sysctl_clock_source_get_freq(source); + /* + * Check input clock freq + */ + if(freq_in == 0) + return 0; + break; + + default: + return 0; + } + + /* + * Begin calculate PLL registers' value + */ + + /* constants */ + const double vco_min = 3.5e+08; + const double vco_max = 1.75e+09; + const double ref_min = 1.36719e+07; + const double ref_max = 1.75e+09; + const int nr_min = 1; + const int nr_max = 16; + const int nf_min = 1; + const int nf_max = 64; + const int no_min = 1; + const int no_max = 16; + const int nb_min = 1; + const int nb_max = 64; + const int max_vco = 1; + const int ref_rng = 1; + + /* variables */ + int nr = 0; + int nrx = 0; + int nf = 0; + int nfi = 0; + int no = 0; + int noe = 0; + int not = 0; + int nor = 0; + int nore = 0; + int nb = 0; + int first = 0; + int firstx = 0; + int found = 0; + + long long nfx = 0; + double fin = 0, fout = 0, fvco = 0; + double val = 0, nval = 0, err = 0, merr = 0, terr = 0; + int x_nrx = 0, x_no = 0, x_nb = 0; + long long x_nfx = 0; + double x_fvco = 0, x_err = 0; + + fin = freq_in; + fout = freq; + val = fout / fin; + terr = 0.5 / ((double)(nf_max / 2)); + first = firstx = 1; + if(terr != -2) + { + first = 0; + if(terr == 0) + terr = 1e-16; + merr = fabs(terr); + } + found = 0; + for(nfi = val; nfi < nf_max; ++nfi) + { + nr = rint(((double)nfi) / val); + if(nr == 0) + continue; + if((ref_rng) && (nr < nr_min)) + continue; + if(fin / ((double)nr) > ref_max) + continue; + nrx = nr; + nf = nfx = nfi; + nval = ((double)nfx) / ((double)nr); + if(nf == 0) + nf = 1; + err = 1 - nval / val; + + if((first) || (fabs(err) < merr * (1 + 1e-6)) || (fabs(err) < 1e-16)) + { + not = floor(vco_max / fout); + for(no = (not > no_max) ? no_max : not; no > no_min; --no) + { + if((ref_rng) && ((nr / no) < nr_min)) + continue; + if((nr % no) == 0) + break; + } + if((nr % no) != 0) + continue; + nor = ((not > no_max) ? no_max : not) / no; + nore = nf_max / nf; + if(nor > nore) + nor = nore; + noe = ceil(vco_min / fout); + if(!max_vco) + { + nore = (noe - 1) / no + 1; + nor = nore; + not = 0; /* force next if to fail */ + } + if((((no * nor) < (not >> 1)) || ((no * nor) < noe)) && ((no * nor) < (nf_max / nf))) + { + no = nf_max / nf; + if(no > no_max) + no = no_max; + if(no > not) + no = not; + nfx *= no; + nf *= no; + if((no > 1) && (!firstx)) + continue; + /* wait for larger nf in later iterations */ + } else + { + nrx /= no; + nfx *= nor; + nf *= nor; + no *= nor; + if(no > no_max) + continue; + if((nor > 1) && (!firstx)) + continue; + /* wait for larger nf in later iterations */ + } + + nb = nfx; + if(nb < nb_min) + nb = nb_min; + if(nb > nb_max) + continue; + + fvco = fin / ((double)nrx) * ((double)nfx); + if(fvco < vco_min) + continue; + if(fvco > vco_max) + continue; + if(nf < nf_min) + continue; + if((ref_rng) && (fin / ((double)nrx) < ref_min)) + continue; + if((ref_rng) && (nrx > nr_max)) + continue; + if(!(((firstx) && (terr < 0)) || (fabs(err) < merr * (1 - 1e-6)) || ((max_vco) && (no > x_no)))) + continue; + if((!firstx) && (terr >= 0) && (nrx > x_nrx)) + continue; + + found = 1; + x_no = no; + x_nrx = nrx; + x_nfx = nfx; + x_nb = nb; + x_fvco = fvco; + x_err = err; + first = firstx = 0; + merr = fabs(err); + if(terr != -1) + continue; + } + } + if(!found) + { + return 0; + } + + nrx = x_nrx; + nfx = x_nfx; + no = x_no; + nb = x_nb; + fvco = x_fvco; + err = x_err; + if((terr != -2) && (fabs(err) >= terr * (1 - 1e-6))) + { + return 0; + } + + /* + * Begin write PLL registers' value, + * Using atomic write method. + */ + sysctl_pll0_t pll0; + sysctl_pll1_t pll1; + sysctl_pll2_t pll2; + + switch(pll) + { + case SYSCTL_PLL0: + /* Read register from bus */ + pll0 = sysctl->pll0; + /* Set register temporary value */ + pll0.clkr0 = nrx - 1; + pll0.clkf0 = nfx - 1; + pll0.clkod0 = no - 1; + pll0.bwadj0 = nb - 1; + /* Write register back to bus */ + sysctl->pll0 = pll0; + break; + + case SYSCTL_PLL1: + /* Read register from bus */ + pll1 = sysctl->pll1; + /* Set register temporary value */ + pll1.clkr1 = nrx - 1; + pll1.clkf1 = nfx - 1; + pll1.clkod1 = no - 1; + pll1.bwadj1 = nb - 1; + /* Write register back to bus */ + sysctl->pll1 = pll1; + break; + + case SYSCTL_PLL2: + /* Read register from bus */ + pll2 = sysctl->pll2; + /* Set register temporary value */ + if(source < sizeof(get_select_pll2)) + pll2.pll_ckin_sel2 = get_select_pll2[source]; + + pll2.clkr2 = nrx - 1; + pll2.clkf2 = nfx - 1; + pll2.clkod2 = no - 1; + pll2.bwadj2 = nb - 1; + /* Write register back to bus */ + sysctl->pll2 = pll2; + break; + + default: + return 0; + } + + return sysctl_pll_get_freq(pll); +} + +uint32_t sysctl_clock_get_freq(sysctl_clock_t clock) +{ + uint32_t source = 0; + uint32_t result = 0; + + switch(clock) + { + /* + * The clock IN0 + */ + case SYSCTL_CLOCK_IN0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + result = source; + break; + + /* + * These clock directly under PLL clock domain + * They are using gated divider. + */ + case SYSCTL_CLOCK_PLL0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source; + break; + case SYSCTL_CLOCK_PLL1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL1); + result = source; + break; + case SYSCTL_CLOCK_PLL2: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL2); + result = source; + break; + + /* + * These clock directly under ACLK clock domain + */ + case SYSCTL_CLOCK_CPU: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_ACLK)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0) / + (2ULL << sysctl_clock_get_threshold(SYSCTL_THRESHOLD_ACLK)); + break; + default: + break; + } + result = source; + break; + case SYSCTL_CLOCK_DMA: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_ACLK)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0) / + (2ULL << sysctl_clock_get_threshold(SYSCTL_THRESHOLD_ACLK)); + break; + default: + break; + } + result = source; + break; + case SYSCTL_CLOCK_FFT: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_ACLK)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0) / + (2ULL << sysctl_clock_get_threshold(SYSCTL_THRESHOLD_ACLK)); + break; + default: + break; + } + result = source; + break; + case SYSCTL_CLOCK_ACLK: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_ACLK)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0) / + (2ULL << sysctl_clock_get_threshold(SYSCTL_THRESHOLD_ACLK)); + break; + default: + break; + } + result = source; + break; + case SYSCTL_CLOCK_HCLK: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_ACLK)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0) / + (2ULL << sysctl_clock_get_threshold(SYSCTL_THRESHOLD_ACLK)); + break; + default: + break; + } + result = source; + break; + + /* + * These clock under ACLK clock domain. + * They are using gated divider. + */ + case SYSCTL_CLOCK_SRAM0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_SRAM0) + 1); + break; + case SYSCTL_CLOCK_SRAM1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_SRAM1) + 1); + break; + case SYSCTL_CLOCK_ROM: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_ROM) + 1); + break; + case SYSCTL_CLOCK_DVP: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_DVP) + 1); + break; + + /* + * These clock under ACLK clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_APB0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_APB0) + 1); + break; + case SYSCTL_CLOCK_APB1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_APB1) + 1); + break; + case SYSCTL_CLOCK_APB2: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_ACLK); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_APB2) + 1); + break; + + /* + * These clock under AI clock domain. + * They are using gated divider. + */ + case SYSCTL_CLOCK_AI: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL1); + result = source / (sysctl_clock_get_threshold(SYSCTL_THRESHOLD_AI) + 1); + break; + + /* + * These clock under I2S clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_I2S0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL2); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_I2S0) + 1) * 2); + break; + case SYSCTL_CLOCK_I2S1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL2); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_I2S1) + 1) * 2); + break; + case SYSCTL_CLOCK_I2S2: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL2); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_I2S2) + 1) * 2); + break; + + /* + * These clock under WDT clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_WDT0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_WDT0) + 1) * 2); + break; + case SYSCTL_CLOCK_WDT1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_WDT1) + 1) * 2); + break; + + /* + * These clock under PLL0 clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_SPI0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_SPI0) + 1) * 2); + break; + case SYSCTL_CLOCK_SPI1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_SPI1) + 1) * 2); + break; + case SYSCTL_CLOCK_SPI2: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_SPI2) + 1) * 2); + break; + case SYSCTL_CLOCK_I2C0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_I2C0) + 1) * 2); + break; + case SYSCTL_CLOCK_I2C1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_I2C1) + 1) * 2); + break; + case SYSCTL_CLOCK_I2C2: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_I2C2) + 1) * 2); + break; + + /* + * These clock under PLL0_SEL clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_SPI3: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_SPI3)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + break; + default: + break; + } + + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_SPI3) + 1) * 2); + break; + case SYSCTL_CLOCK_TIMER0: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_TIMER0)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + break; + default: + break; + } + + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_TIMER0) + 1) * 2); + break; + case SYSCTL_CLOCK_TIMER1: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_TIMER1)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + break; + default: + break; + } + + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_TIMER1) + 1) * 2); + break; + case SYSCTL_CLOCK_TIMER2: + switch(sysctl_clock_get_clock_select(SYSCTL_CLOCK_SELECT_TIMER2)) + { + case 0: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + break; + case 1: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_PLL0); + break; + default: + break; + } + + result = source / ((sysctl_clock_get_threshold(SYSCTL_THRESHOLD_TIMER2) + 1) * 2); + break; + + /* + * These clock under MISC clock domain. + * They are using even divider. + */ + + /* + * These clock under APB0 clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_GPIO: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + result = source; + break; + case SYSCTL_CLOCK_UART1: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + result = source; + break; + case SYSCTL_CLOCK_UART2: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + result = source; + break; + case SYSCTL_CLOCK_UART3: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + result = source; + break; + case SYSCTL_CLOCK_FPIOA: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + result = source; + break; + case SYSCTL_CLOCK_SHA: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0); + result = source; + break; + + /* + * These clock under APB1 clock domain. + * They are using even divider. + */ + case SYSCTL_CLOCK_AES: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1); + result = source; + break; + case SYSCTL_CLOCK_OTP: + source = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1); + result = source; + break; + case SYSCTL_CLOCK_RTC: + source = sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0); + result = source; + break; + + /* + * These clock under APB2 clock domain. + * They are using even divider. + */ + /* + * Do nothing. + */ + default: + break; + } + return result; +} + +int sysctl_dma_select(sysctl_dma_channel_t channel, sysctl_dma_select_t select) +{ + sysctl_dma_sel0_t dma_sel0; + sysctl_dma_sel1_t dma_sel1; + + /* Read register from bus */ + dma_sel0 = sysctl->dma_sel0; + dma_sel1 = sysctl->dma_sel1; + switch(channel) + { + case SYSCTL_DMA_CHANNEL_0: + dma_sel0.dma_sel0 = select; + break; + + case SYSCTL_DMA_CHANNEL_1: + dma_sel0.dma_sel1 = select; + break; + + case SYSCTL_DMA_CHANNEL_2: + dma_sel0.dma_sel2 = select; + break; + + case SYSCTL_DMA_CHANNEL_3: + dma_sel0.dma_sel3 = select; + break; + + case SYSCTL_DMA_CHANNEL_4: + dma_sel0.dma_sel4 = select; + break; + + case SYSCTL_DMA_CHANNEL_5: + dma_sel1.dma_sel5 = select; + break; + + default: + return -1; + } + + /* Write register back to bus */ + sysctl->dma_sel0 = dma_sel0; + sysctl->dma_sel1 = dma_sel1; + + return 0; +} + +uint32_t sysctl_pll_fast_enable_pll(void) +{ + /* + * Begin write PLL registers' value, + * Using atomic write method. + */ + sysctl_pll0_t pll0; + sysctl_pll1_t pll1; + sysctl_pll2_t pll2; + + /* Read register from bus */ + pll0 = sysctl->pll0; + pll1 = sysctl->pll1; + pll2 = sysctl->pll2; + + /* PLL VCO MAX freq: 1.8GHz */ + + /* PLL0: 26M reference clk get 793M output clock */ + pll0.clkr0 = 0; + pll0.clkf0 = 60; + pll0.clkod0 = 1; + pll0.bwadj0 = 60; + + /* PLL1: 26M reference clk get 390M output clock */ + pll1.clkr1 = 0; + pll1.clkf1 = 59; + pll1.clkod1 = 3; + pll1.bwadj1 = 59; + + /* PLL2: 26M reference clk get 390M output clock */ + pll2.clkr2 = 0; + pll2.clkf2 = 59; + pll2.clkod2 = 3; + pll2.bwadj2 = 59; + + /* Write register to bus */ + sysctl->pll0 = pll0; + sysctl->pll1 = pll1; + sysctl->pll2 = pll2; + + sysctl_pll_enable(SYSCTL_PLL0); + sysctl_pll_enable(SYSCTL_PLL1); + sysctl_pll_enable(SYSCTL_PLL2); + + while(sysctl_pll_is_lock(SYSCTL_PLL0) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL0); + while(sysctl_pll_is_lock(SYSCTL_PLL1) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL1); + while(sysctl_pll_is_lock(SYSCTL_PLL2) == 0) + sysctl_pll_clear_slip(SYSCTL_PLL2); + + sysctl_clock_enable(SYSCTL_CLOCK_PLL0); + sysctl_clock_enable(SYSCTL_CLOCK_PLL1); + sysctl_clock_enable(SYSCTL_CLOCK_PLL2); + + /* Set ACLK to PLL0 */ + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + + return 0; +} + +uint32_t sysctl_set_spi0_dvp_data(uint8_t en) +{ + sysctl->misc.spi_dvp_data_enable = en; + return 0; +} + +void sysctl_set_power_mode(sysctl_power_bank_t power_bank, sysctl_io_power_mode_t io_power_mode) +{ + if(io_power_mode) + *((uint32_t *)(&sysctl->power_sel)) |= (1 << power_bank); + else + *((uint32_t *)(&sysctl->power_sel)) &= ~(1 << power_bank); +} + +uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, uint32_t pll_freq) +{ + if(pll_freq == 0) + return 0; + + volatile sysctl_general_pll_t *v_pll_t; + switch(pll) + { + case SYSCTL_PLL0: + v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll0); + break; + case SYSCTL_PLL1: + v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll1); + break; + case SYSCTL_PLL2: + v_pll_t = (sysctl_general_pll_t *)(&sysctl->pll2); + break; + default: + return 0; + break; + } + + /* 1. Change CPU CLK to XTAL */ + if(pll == SYSCTL_PLL0) + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0); + + /* 2. Disable PLL output */ + v_pll_t->pll_out_en = 0; + + /* 3. Turn off PLL */ + v_pll_t->pll_pwrd = 0; + + /* 4. Set PLL new value */ + uint32_t result; + if(pll == SYSCTL_PLL2) + result = sysctl_pll_source_set_freq(pll, v_pll_t->pll_ckin_sel, pll_freq); + else + result = sysctl_pll_source_set_freq(pll, SYSCTL_SOURCE_IN0, pll_freq); + + /* 5. Power on PLL */ + v_pll_t->pll_pwrd = 1; + /* wait >100ns */ + usleep(1); + + /* 6. Reset PLL then Release Reset*/ + v_pll_t->pll_reset = 0; + v_pll_t->pll_reset = 1; + /* wait >100ns */ + usleep(1); + v_pll_t->pll_reset = 0; + + /* 7. Get lock status, wait PLL stable */ + while(sysctl_pll_is_lock(pll) == 0) + sysctl_pll_clear_slip(pll); + + /* 8. Enable PLL output */ + v_pll_t->pll_out_en = 1; + + /* 9. Change CPU CLK to PLL */ + if(pll == SYSCTL_PLL0) + { + sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0); + } + return result; +} + +static uint32_t cpu_freq = 390000000; + +uint32_t sysctl_cpu_get_freq(void) +{ + return cpu_freq; +} + +uint32_t sysctl_cpu_set_freq(uint32_t freq) +{ + if(freq == 0) + return 0; + + cpu_freq = sysctl_pll_set_freq(SYSCTL_PLL0, (sysctl->clk_sel0.aclk_divider_sel + 1) * 2 * freq); + return cpu_freq; +} + +void sysctl_enable_irq(void) +{ + set_csr(mie, MIP_MEIP); + set_csr(mstatus, MSTATUS_MIE); +} + +void sysctl_disable_irq(void) +{ + clear_csr(mie, MIP_MEIP); + clear_csr(mstatus, MSTATUS_MIE); +} + +uint64_t sysctl_get_time_us(void) +{ + uint64_t v_cycle = read_cycle(); + return v_cycle * 1000000 / sysctl_clock_get_freq(SYSCTL_CLOCK_CPU); +} + +sysctl_reset_enum_status_t sysctl_get_reset_status(void) +{ + static sysctl_reset_enum_status_t s_reset_status = 0; + if(s_reset_status != 0) + { + return s_reset_status; + } + + if(sysctl->reset_status.wdt0_reset_sts) + { + s_reset_status = SYSCTL_RESET_STATUS_WDT0; + } else if(sysctl->reset_status.wdt1_reset_sts) + { + s_reset_status = SYSCTL_RESET_STATUS_WDT1; + } else if(sysctl->reset_status.soft_reset_sts) + { + s_reset_status = SYSCTL_RESET_STATUS_SOFT; + } else + { + s_reset_status = SYSCTL_RESET_STATUS_HARD; + } + sysctl->reset_status.reset_sts_clr = 1; + + return s_reset_status; +} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_sysctl.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_sysctl.h new file mode 100755 index 000000000..625a3f3e3 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_sysctl.h @@ -0,0 +1,1097 @@ +/* Copyright 2018 Canaan Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _DRIVER_SYSCTL_H +#define _DRIVER_SYSCTL_H + +#include +#include "encoding.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define K210_SYSCTL_PLL0 (K210_SYSCTL_BASE + 0x08) +#define K210_SYSCTL_PLL1 (K210_SYSCTL_BASE + 0x0c) +#define K210_SYSCTL_PLL2 (K210_SYSCTL_BASE + 0x10) +#define K210_SYSCTL_LOCK (K210_SYSCTL_BASE + 0x18) +#define K210_SYSCTL_SEL0 (K210_SYSCTL_BASE + 0x20) +#define K210_SYSCTL_SEL1 (K210_SYSCTL_BASE + 0x24) +#define K210_SYSCTL_EN (K210_SYSCTL_BASE + 0x28) + +#define PLL_CLK_R(n) (n & 0x00000f) +#define PLL_CLK_F(n) ((n & 0x0003f0) >> 4) +#define PLL_CLK_OD(n) ((n & 0x003c00) >> 10) + +#define K210_SYSCTL_CLKSEL0 (K210_SYSCTL_BASE + 0x20) +#define K210_SYSCTL_CLK_EN (K210_SYSCTL_BASE + 0x2c) + +#define CLKSEL0_ACLK_SEL(n) (n & 0x00000001) + +#define SYSCTL_BASE_ADDR (0x50440000U) + +/** + * @brief System controller register + * + * @note System controller register table + * + * | Offset | Name | Description | + * |-----------|----------------|-------------------------------------| + * | 0x00 | git_id | Git short commit id | + * | 0x04 | clk_freq | System clock base frequency | + * | 0x08 | pll0 | PLL0 controller | + * | 0x0c | pll1 | PLL1 controller | + * | 0x10 | pll2 | PLL2 controller | + * | 0x14 | resv5 | Reserved | + * | 0x18 | pll_lock | PLL lock tester | + * | 0x1c | rom_error | AXI ROM detector | + * | 0x20 | clk_sel0 | Clock select controller0 | + * | 0x24 | clk_sel1 | Clock select controller1 | + * | 0x28 | clk_en_cent | Central clock enable | + * | 0x2c | clk_en_peri | Peripheral clock enable | + * | 0x30 | soft_reset | Soft reset ctrl | + * | 0x34 | peri_reset | Peripheral reset controller | + * | 0x38 | clk_th0 | Clock threshold controller 0 | + * | 0x3c | clk_th1 | Clock threshold controller 1 | + * | 0x40 | clk_th2 | Clock threshold controller 2 | + * | 0x44 | clk_th3 | Clock threshold controller 3 | + * | 0x48 | clk_th4 | Clock threshold controller 4 | + * | 0x4c | clk_th5 | Clock threshold controller 5 | + * | 0x50 | clk_th6 | Clock threshold controller 6 | + * | 0x54 | misc | Miscellaneous controller | + * | 0x58 | peri | Peripheral controller | + * | 0x5c | spi_sleep | SPI sleep controller | + * | 0x60 | reset_status | Reset source status | + * | 0x64 | dma_sel0 | DMA handshake selector | + * | 0x68 | dma_sel1 | DMA handshake selector | + * | 0x6c | power_sel | IO Power Mode Select controller | + * | 0x70 | resv28 | Reserved | + * | 0x74 | resv29 | Reserved | + * | 0x78 | resv30 | Reserved | + * | 0x7c | resv31 | Reserved | + * + */ + +typedef enum _sysctl_pll_t +{ + SYSCTL_PLL0, + SYSCTL_PLL1, + SYSCTL_PLL2, + SYSCTL_PLL_MAX +} sysctl_pll_t; + +typedef enum _sysctl_clock_source_t +{ + SYSCTL_SOURCE_IN0, + SYSCTL_SOURCE_PLL0, + SYSCTL_SOURCE_PLL1, + SYSCTL_SOURCE_PLL2, + SYSCTL_SOURCE_ACLK, + SYSCTL_SOURCE_MAX +} sysctl_clock_source_t; + +typedef enum _sysctl_dma_channel_t +{ + SYSCTL_DMA_CHANNEL_0, + SYSCTL_DMA_CHANNEL_1, + SYSCTL_DMA_CHANNEL_2, + SYSCTL_DMA_CHANNEL_3, + SYSCTL_DMA_CHANNEL_4, + SYSCTL_DMA_CHANNEL_5, + SYSCTL_DMA_CHANNEL_MAX +} sysctl_dma_channel_t; + +typedef enum _sysctl_dma_select_t +{ + SYSCTL_DMA_SELECT_SSI0_RX_REQ, + SYSCTL_DMA_SELECT_SSI0_TX_REQ, + SYSCTL_DMA_SELECT_SSI1_RX_REQ, + SYSCTL_DMA_SELECT_SSI1_TX_REQ, + SYSCTL_DMA_SELECT_SSI2_RX_REQ, + SYSCTL_DMA_SELECT_SSI2_TX_REQ, + SYSCTL_DMA_SELECT_SSI3_RX_REQ, + SYSCTL_DMA_SELECT_SSI3_TX_REQ, + SYSCTL_DMA_SELECT_I2C0_RX_REQ, + SYSCTL_DMA_SELECT_I2C0_TX_REQ, + SYSCTL_DMA_SELECT_I2C1_RX_REQ, + SYSCTL_DMA_SELECT_I2C1_TX_REQ, + SYSCTL_DMA_SELECT_I2C2_RX_REQ, + SYSCTL_DMA_SELECT_I2C2_TX_REQ, + SYSCTL_DMA_SELECT_UART1_RX_REQ, + SYSCTL_DMA_SELECT_UART1_TX_REQ, + SYSCTL_DMA_SELECT_UART2_RX_REQ, + SYSCTL_DMA_SELECT_UART2_TX_REQ, + SYSCTL_DMA_SELECT_UART3_RX_REQ, + SYSCTL_DMA_SELECT_UART3_TX_REQ, + SYSCTL_DMA_SELECT_AES_REQ, + SYSCTL_DMA_SELECT_SHA_RX_REQ, + SYSCTL_DMA_SELECT_AI_RX_REQ, + SYSCTL_DMA_SELECT_FFT_RX_REQ, + SYSCTL_DMA_SELECT_FFT_TX_REQ, + SYSCTL_DMA_SELECT_I2S0_TX_REQ, + SYSCTL_DMA_SELECT_I2S0_RX_REQ, + SYSCTL_DMA_SELECT_I2S1_TX_REQ, + SYSCTL_DMA_SELECT_I2S1_RX_REQ, + SYSCTL_DMA_SELECT_I2S2_TX_REQ, + SYSCTL_DMA_SELECT_I2S2_RX_REQ, + SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ, + SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ, + SYSCTL_DMA_SELECT_MAX +} sysctl_dma_select_t; + +/** + * @brief System controller clock id + */ +typedef enum _sysctl_clock_t +{ + SYSCTL_CLOCK_PLL0, + SYSCTL_CLOCK_PLL1, + SYSCTL_CLOCK_PLL2, + SYSCTL_CLOCK_CPU, + SYSCTL_CLOCK_SRAM0, + SYSCTL_CLOCK_SRAM1, + SYSCTL_CLOCK_APB0, + SYSCTL_CLOCK_APB1, + SYSCTL_CLOCK_APB2, + SYSCTL_CLOCK_ROM, + SYSCTL_CLOCK_DMA, + SYSCTL_CLOCK_AI, + SYSCTL_CLOCK_DVP, + SYSCTL_CLOCK_FFT, + SYSCTL_CLOCK_GPIO, + SYSCTL_CLOCK_SPI0, + SYSCTL_CLOCK_SPI1, + SYSCTL_CLOCK_SPI2, + SYSCTL_CLOCK_SPI3, + SYSCTL_CLOCK_I2S0, + SYSCTL_CLOCK_I2S1, + SYSCTL_CLOCK_I2S2, + SYSCTL_CLOCK_I2C0, + SYSCTL_CLOCK_I2C1, + SYSCTL_CLOCK_I2C2, + SYSCTL_CLOCK_UART1, + SYSCTL_CLOCK_UART2, + SYSCTL_CLOCK_UART3, + SYSCTL_CLOCK_AES, + SYSCTL_CLOCK_FPIOA, + SYSCTL_CLOCK_TIMER0, + SYSCTL_CLOCK_TIMER1, + SYSCTL_CLOCK_TIMER2, + SYSCTL_CLOCK_WDT0, + SYSCTL_CLOCK_WDT1, + SYSCTL_CLOCK_SHA, + SYSCTL_CLOCK_OTP, + SYSCTL_CLOCK_RTC, + SYSCTL_CLOCK_ACLK = 40, + SYSCTL_CLOCK_HCLK, + SYSCTL_CLOCK_IN0, + SYSCTL_CLOCK_MAX +} sysctl_clock_t; + +/** + * @brief System controller clock select id + */ +typedef enum _sysctl_clock_select_t +{ + SYSCTL_CLOCK_SELECT_PLL0_BYPASS, + SYSCTL_CLOCK_SELECT_PLL1_BYPASS, + SYSCTL_CLOCK_SELECT_PLL2_BYPASS, + SYSCTL_CLOCK_SELECT_PLL2, + SYSCTL_CLOCK_SELECT_ACLK, + SYSCTL_CLOCK_SELECT_SPI3, + SYSCTL_CLOCK_SELECT_TIMER0, + SYSCTL_CLOCK_SELECT_TIMER1, + SYSCTL_CLOCK_SELECT_TIMER2, + SYSCTL_CLOCK_SELECT_SPI3_SAMPLE, + SYSCTL_CLOCK_SELECT_MAX = 11 +} sysctl_clock_select_t; + +/** + * @brief System controller clock threshold id + */ +typedef enum _sysctl_threshold_t +{ + SYSCTL_THRESHOLD_ACLK, + SYSCTL_THRESHOLD_APB0, + SYSCTL_THRESHOLD_APB1, + SYSCTL_THRESHOLD_APB2, + SYSCTL_THRESHOLD_SRAM0, + SYSCTL_THRESHOLD_SRAM1, + SYSCTL_THRESHOLD_AI, + SYSCTL_THRESHOLD_DVP, + SYSCTL_THRESHOLD_ROM, + SYSCTL_THRESHOLD_SPI0, + SYSCTL_THRESHOLD_SPI1, + SYSCTL_THRESHOLD_SPI2, + SYSCTL_THRESHOLD_SPI3, + SYSCTL_THRESHOLD_TIMER0, + SYSCTL_THRESHOLD_TIMER1, + SYSCTL_THRESHOLD_TIMER2, + SYSCTL_THRESHOLD_I2S0, + SYSCTL_THRESHOLD_I2S1, + SYSCTL_THRESHOLD_I2S2, + SYSCTL_THRESHOLD_I2S0_M, + SYSCTL_THRESHOLD_I2S1_M, + SYSCTL_THRESHOLD_I2S2_M, + SYSCTL_THRESHOLD_I2C0, + SYSCTL_THRESHOLD_I2C1, + SYSCTL_THRESHOLD_I2C2, + SYSCTL_THRESHOLD_WDT0, + SYSCTL_THRESHOLD_WDT1, + SYSCTL_THRESHOLD_MAX = 28 +} sysctl_threshold_t; + +/** + * @brief System controller reset control id + */ +typedef enum _sysctl_reset_t +{ + SYSCTL_RESET_SOC, + SYSCTL_RESET_ROM, + SYSCTL_RESET_DMA, + SYSCTL_RESET_AI, + SYSCTL_RESET_DVP, + SYSCTL_RESET_FFT, + SYSCTL_RESET_GPIO, + SYSCTL_RESET_SPI0, + SYSCTL_RESET_SPI1, + SYSCTL_RESET_SPI2, + SYSCTL_RESET_SPI3, + SYSCTL_RESET_I2S0, + SYSCTL_RESET_I2S1, + SYSCTL_RESET_I2S2, + SYSCTL_RESET_I2C0, + SYSCTL_RESET_I2C1, + SYSCTL_RESET_I2C2, + SYSCTL_RESET_UART1, + SYSCTL_RESET_UART2, + SYSCTL_RESET_UART3, + SYSCTL_RESET_AES, + SYSCTL_RESET_FPIOA, + SYSCTL_RESET_TIMER0, + SYSCTL_RESET_TIMER1, + SYSCTL_RESET_TIMER2, + SYSCTL_RESET_WDT0, + SYSCTL_RESET_WDT1, + SYSCTL_RESET_SHA, + SYSCTL_RESET_RTC, + SYSCTL_RESET_MAX = 31 +} sysctl_reset_t; + +/** + * @brief System controller power bank id + */ +typedef enum _sysctl_power_bank +{ + SYSCTL_POWER_BANK0, + SYSCTL_POWER_BANK1, + SYSCTL_POWER_BANK2, + SYSCTL_POWER_BANK3, + SYSCTL_POWER_BANK4, + SYSCTL_POWER_BANK5, + SYSCTL_POWER_BANK6, + SYSCTL_POWER_BANK7, + SYSCTL_POWER_BANK_MAX, +} sysctl_power_bank_t; + +/** + * @brief System controller reset control id + */ +typedef enum _sysctl_io_power_mode +{ + SYSCTL_POWER_V33, + SYSCTL_POWER_V18 +} sysctl_io_power_mode_t; + +/** + * @brief System reset status + */ +typedef enum _sysctl_reset_enum_status +{ + SYSCTL_RESET_STATUS_HARD, + SYSCTL_RESET_STATUS_SOFT, + SYSCTL_RESET_STATUS_WDT0, + SYSCTL_RESET_STATUS_WDT1, + SYSCTL_RESET_STATUS_MAX, +} sysctl_reset_enum_status_t; + +/** + * @brief Git short commit id + * + * No. 0 Register (0x00) + */ +typedef struct _sysctl_git_id +{ + uint32_t git_id : 32; +} __attribute__((packed, aligned(4))) sysctl_git_id_t; + +/** + * @brief System clock base frequency + * + * No. 1 Register (0x04) + */ +typedef struct _sysctl_clk_freq +{ + uint32_t clk_freq : 32; +} __attribute__((packed, aligned(4))) sysctl_clk_freq_t; + +/** + * @brief PLL0 controller + * + * No. 2 Register (0x08) + */ +typedef struct _sysctl_pll0 +{ + uint32_t clkr0 : 4; + uint32_t clkf0 : 6; + uint32_t clkod0 : 4; + uint32_t bwadj0 : 6; + uint32_t pll_reset0 : 1; + uint32_t pll_pwrd0 : 1; + uint32_t pll_intfb0 : 1; + uint32_t pll_bypass0 : 1; + uint32_t pll_test0 : 1; + uint32_t pll_out_en0 : 1; + uint32_t pll_test_en : 1; + uint32_t reserved : 5; +} __attribute__((packed, aligned(4))) sysctl_pll0_t; + +/** + * @brief PLL1 controller + * + * No. 3 Register (0x0c) + */ +typedef struct _sysctl_pll1 +{ + uint32_t clkr1 : 4; + uint32_t clkf1 : 6; + uint32_t clkod1 : 4; + uint32_t bwadj1 : 6; + uint32_t pll_reset1 : 1; + uint32_t pll_pwrd1 : 1; + uint32_t pll_intfb1 : 1; + uint32_t pll_bypass1 : 1; + uint32_t pll_test1 : 1; + uint32_t pll_out_en1 : 1; + uint32_t reserved : 6; +} __attribute__((packed, aligned(4))) sysctl_pll1_t; + +/** + * @brief PLL2 controller + * + * No. 4 Register (0x10) + */ +typedef struct _sysctl_pll2 +{ + uint32_t clkr2 : 4; + uint32_t clkf2 : 6; + uint32_t clkod2 : 4; + uint32_t bwadj2 : 6; + uint32_t pll_reset2 : 1; + uint32_t pll_pwrd2 : 1; + uint32_t pll_intfb2 : 1; + uint32_t pll_bypass2 : 1; + uint32_t pll_test2 : 1; + uint32_t pll_out_en2 : 1; + uint32_t pll_ckin_sel2 : 2; + uint32_t reserved : 4; +} __attribute__((packed, aligned(4))) sysctl_pll2_t; + +/** + * @brief PLL lock tester + * + * No. 6 Register (0x18) + */ +typedef struct _sysctl_pll_lock +{ + uint32_t pll_lock0 : 2; + uint32_t pll_slip_clear0 : 1; + uint32_t test_clk_out0 : 1; + uint32_t reserved0 : 4; + uint32_t pll_lock1 : 2; + uint32_t pll_slip_clear1 : 1; + uint32_t test_clk_out1 : 1; + uint32_t reserved1 : 4; + uint32_t pll_lock2 : 2; + uint32_t pll_slip_clear2 : 1; + uint32_t test_clk_out2 : 1; + uint32_t reserved2 : 12; +} __attribute__((packed, aligned(4))) sysctl_pll_lock_t; + +/** + * @brief AXI ROM detector + * + * No. 7 Register (0x1c) + */ +typedef struct _sysctl_rom_error +{ + uint32_t rom_mul_error : 1; + uint32_t rom_one_error : 1; + uint32_t reserved : 30; +} __attribute__((packed, aligned(4))) sysctl_rom_error_t; + +/** + * @brief Clock select controller0 + * + * No. 8 Register (0x20) + */ +typedef struct _sysctl_clk_sel0 +{ + uint32_t aclk_sel : 1; + uint32_t aclk_divider_sel : 2; + uint32_t apb0_clk_sel : 3; + uint32_t apb1_clk_sel : 3; + uint32_t apb2_clk_sel : 3; + uint32_t spi3_clk_sel : 1; + uint32_t timer0_clk_sel : 1; + uint32_t timer1_clk_sel : 1; + uint32_t timer2_clk_sel : 1; + uint32_t reserved : 16; +} __attribute__((packed, aligned(4))) sysctl_clk_sel0_t; + +/** + * @brief Clock select controller1 + * + * No. 9 Register (0x24) + */ +typedef struct _sysctl_clk_sel1 +{ + uint32_t spi3_sample_clk_sel : 1; + uint32_t reserved0 : 30; + uint32_t reserved1 : 1; +} __attribute__((packed, aligned(4))) sysctl_clk_sel1_t; + +/** + * @brief Central clock enable + * + * No. 10 Register (0x28) + */ +typedef struct _sysctl_clk_en_cent +{ + uint32_t cpu_clk_en : 1; + uint32_t sram0_clk_en : 1; + uint32_t sram1_clk_en : 1; + uint32_t apb0_clk_en : 1; + uint32_t apb1_clk_en : 1; + uint32_t apb2_clk_en : 1; + uint32_t reserved : 26; +} __attribute__((packed, aligned(4))) sysctl_clk_en_cent_t; + +/** + * @brief Peripheral clock enable + * + * No. 11 Register (0x2c) + */ +typedef struct _sysctl_clk_en_peri +{ + uint32_t rom_clk_en : 1; + uint32_t dma_clk_en : 1; + uint32_t ai_clk_en : 1; + uint32_t dvp_clk_en : 1; + uint32_t fft_clk_en : 1; + uint32_t gpio_clk_en : 1; + uint32_t spi0_clk_en : 1; + uint32_t spi1_clk_en : 1; + uint32_t spi2_clk_en : 1; + uint32_t spi3_clk_en : 1; + uint32_t i2s0_clk_en : 1; + uint32_t i2s1_clk_en : 1; + uint32_t i2s2_clk_en : 1; + uint32_t i2c0_clk_en : 1; + uint32_t i2c1_clk_en : 1; + uint32_t i2c2_clk_en : 1; + uint32_t uart1_clk_en : 1; + uint32_t uart2_clk_en : 1; + uint32_t uart3_clk_en : 1; + uint32_t aes_clk_en : 1; + uint32_t fpioa_clk_en : 1; + uint32_t timer0_clk_en : 1; + uint32_t timer1_clk_en : 1; + uint32_t timer2_clk_en : 1; + uint32_t wdt0_clk_en : 1; + uint32_t wdt1_clk_en : 1; + uint32_t sha_clk_en : 1; + uint32_t otp_clk_en : 1; + uint32_t reserved : 1; + uint32_t rtc_clk_en : 1; + uint32_t reserved0 : 2; +} __attribute__((packed, aligned(4))) sysctl_clk_en_peri_t; + +/** + * @brief Soft reset ctrl + * + * No. 12 Register (0x30) + */ +typedef struct _sysctl_soft_reset +{ + uint32_t soft_reset : 1; + uint32_t reserved : 31; +} __attribute__((packed, aligned(4))) sysctl_soft_reset_t; + +/** + * @brief Peripheral reset controller + * + * No. 13 Register (0x34) + */ +typedef struct _sysctl_peri_reset +{ + uint32_t rom_reset : 1; + uint32_t dma_reset : 1; + uint32_t ai_reset : 1; + uint32_t dvp_reset : 1; + uint32_t fft_reset : 1; + uint32_t gpio_reset : 1; + uint32_t spi0_reset : 1; + uint32_t spi1_reset : 1; + uint32_t spi2_reset : 1; + uint32_t spi3_reset : 1; + uint32_t i2s0_reset : 1; + uint32_t i2s1_reset : 1; + uint32_t i2s2_reset : 1; + uint32_t i2c0_reset : 1; + uint32_t i2c1_reset : 1; + uint32_t i2c2_reset : 1; + uint32_t uart1_reset : 1; + uint32_t uart2_reset : 1; + uint32_t uart3_reset : 1; + uint32_t aes_reset : 1; + uint32_t fpioa_reset : 1; + uint32_t timer0_reset : 1; + uint32_t timer1_reset : 1; + uint32_t timer2_reset : 1; + uint32_t wdt0_reset : 1; + uint32_t wdt1_reset : 1; + uint32_t sha_reset : 1; + uint32_t reserved : 2; + uint32_t rtc_reset : 1; + uint32_t reserved0 : 2; +} __attribute__((packed, aligned(4))) sysctl_peri_reset_t; + +/** + * @brief Clock threshold controller 0 + * + * No. 14 Register (0x38) + */ +typedef struct _sysctl_clk_th0 +{ + uint32_t sram0_gclk_threshold : 4; + uint32_t sram1_gclk_threshold : 4; + uint32_t ai_gclk_threshold : 4; + uint32_t dvp_gclk_threshold : 4; + uint32_t rom_gclk_threshold : 4; + uint32_t reserved : 12; +} __attribute__((packed, aligned(4))) sysctl_clk_th0_t; + +/** + * @brief Clock threshold controller 1 + * + * No. 15 Register (0x3c) + */ +typedef struct _sysctl_clk_th1 +{ + uint32_t spi0_clk_threshold : 8; + uint32_t spi1_clk_threshold : 8; + uint32_t spi2_clk_threshold : 8; + uint32_t spi3_clk_threshold : 8; +} __attribute__((packed, aligned(4))) sysctl_clk_th1_t; + +/** + * @brief Clock threshold controller 2 + * + * No. 16 Register (0x40) + */ +typedef struct _sysctl_clk_th2 +{ + uint32_t timer0_clk_threshold : 8; + uint32_t timer1_clk_threshold : 8; + uint32_t timer2_clk_threshold : 8; + uint32_t reserved : 8; +} __attribute__((packed, aligned(4))) sysctl_clk_th2_t; + +/** + * @brief Clock threshold controller 3 + * + * No. 17 Register (0x44) + */ +typedef struct _sysctl_clk_th3 +{ + uint32_t i2s0_clk_threshold : 16; + uint32_t i2s1_clk_threshold : 16; +} __attribute__((packed, aligned(4))) sysctl_clk_th3_t; + +/** + * @brief Clock threshold controller 4 + * + * No. 18 Register (0x48) + */ +typedef struct _sysctl_clk_th4 +{ + uint32_t i2s2_clk_threshold : 16; + uint32_t i2s0_mclk_threshold : 8; + uint32_t i2s1_mclk_threshold : 8; +} __attribute__((packed, aligned(4))) sysctl_clk_th4_t; + +/** + * @brief Clock threshold controller 5 + * + * No. 19 Register (0x4c) + */ +typedef struct _sysctl_clk_th5 +{ + uint32_t i2s2_mclk_threshold : 8; + uint32_t i2c0_clk_threshold : 8; + uint32_t i2c1_clk_threshold : 8; + uint32_t i2c2_clk_threshold : 8; +} __attribute__((packed, aligned(4))) sysctl_clk_th5_t; + +/** + * @brief Clock threshold controller 6 + * + * No. 20 Register (0x50) + */ +typedef struct _sysctl_clk_th6 +{ + uint32_t wdt0_clk_threshold : 8; + uint32_t wdt1_clk_threshold : 8; + uint32_t reserved0 : 8; + uint32_t reserved1 : 8; +} __attribute__((packed, aligned(4))) sysctl_clk_th6_t; + +/** + * @brief Miscellaneous controller + * + * No. 21 Register (0x54) + */ +typedef struct _sysctl_misc +{ + uint32_t debug_sel : 6; + uint32_t reserved0 : 4; + uint32_t spi_dvp_data_enable : 1; + uint32_t reserved1 : 21; +} __attribute__((packed, aligned(4))) sysctl_misc_t; + +/** + * @brief Peripheral controller + * + * No. 22 Register (0x58) + */ +typedef struct _sysctl_peri +{ + uint32_t timer0_pause : 1; + uint32_t timer1_pause : 1; + uint32_t timer2_pause : 1; + uint32_t timer3_pause : 1; + uint32_t timer4_pause : 1; + uint32_t timer5_pause : 1; + uint32_t timer6_pause : 1; + uint32_t timer7_pause : 1; + uint32_t timer8_pause : 1; + uint32_t timer9_pause : 1; + uint32_t timer10_pause : 1; + uint32_t timer11_pause : 1; + uint32_t spi0_xip_en : 1; + uint32_t spi1_xip_en : 1; + uint32_t spi2_xip_en : 1; + uint32_t spi3_xip_en : 1; + uint32_t spi0_clk_bypass : 1; + uint32_t spi1_clk_bypass : 1; + uint32_t spi2_clk_bypass : 1; + uint32_t i2s0_clk_bypass : 1; + uint32_t i2s1_clk_bypass : 1; + uint32_t i2s2_clk_bypass : 1; + uint32_t jtag_clk_bypass : 1; + uint32_t dvp_clk_bypass : 1; + uint32_t debug_clk_bypass : 1; + uint32_t reserved0 : 1; + uint32_t reserved1 : 6; +} __attribute__((packed, aligned(4))) sysctl_peri_t; + +/** + * @brief SPI sleep controller + * + * No. 23 Register (0x5c) + */ +typedef struct _sysctl_spi_sleep +{ + uint32_t ssi0_sleep : 1; + uint32_t ssi1_sleep : 1; + uint32_t ssi2_sleep : 1; + uint32_t ssi3_sleep : 1; + uint32_t reserved : 28; +} __attribute__((packed, aligned(4))) sysctl_spi_sleep_t; + +/** + * @brief Reset source status + * + * No. 24 Register (0x60) + */ +typedef struct _sysctl_reset_status +{ + uint32_t reset_sts_clr : 1; + uint32_t pin_reset_sts : 1; + uint32_t wdt0_reset_sts : 1; + uint32_t wdt1_reset_sts : 1; + uint32_t soft_reset_sts : 1; + uint32_t reserved : 27; +} __attribute__((packed, aligned(4))) sysctl_reset_status_t; + +/** + * @brief DMA handshake selector + * + * No. 25 Register (0x64) + */ +typedef struct _sysctl_dma_sel0 +{ + uint32_t dma_sel0 : 6; + uint32_t dma_sel1 : 6; + uint32_t dma_sel2 : 6; + uint32_t dma_sel3 : 6; + uint32_t dma_sel4 : 6; + uint32_t reserved : 2; +} __attribute__((packed, aligned(4))) sysctl_dma_sel0_t; + +/** + * @brief DMA handshake selector + * + * No. 26 Register (0x68) + */ +typedef struct _sysctl_dma_sel1 +{ + uint32_t dma_sel5 : 6; + uint32_t reserved : 26; +} __attribute__((packed, aligned(4))) sysctl_dma_sel1_t; + +/** + * @brief IO Power Mode Select controller + * + * No. 27 Register (0x6c) + */ +typedef struct _sysctl_power_sel +{ + uint32_t power_mode_sel0 : 1; + uint32_t power_mode_sel1 : 1; + uint32_t power_mode_sel2 : 1; + uint32_t power_mode_sel3 : 1; + uint32_t power_mode_sel4 : 1; + uint32_t power_mode_sel5 : 1; + uint32_t power_mode_sel6 : 1; + uint32_t power_mode_sel7 : 1; + uint32_t reserved : 24; +} __attribute__((packed, aligned(4))) sysctl_power_sel_t; + +/** + * @brief System controller object + * + * The System controller is a peripheral device mapped in the + * internal memory map, discoverable in the Configuration String. + * It is responsible for low-level configuration of all system + * related peripheral device. It contain PLL controller, clock + * controller, reset controller, DMA handshake controller, SPI + * controller, timer controller, WDT controller and sleep + * controller. + */ +typedef struct _sysctl +{ + /* No. 0 (0x00): Git short commit id */ + sysctl_git_id_t git_id; + /* No. 1 (0x04): System clock base frequency */ + sysctl_clk_freq_t clk_freq; + /* No. 2 (0x08): PLL0 controller */ + sysctl_pll0_t pll0; + /* No. 3 (0x0c): PLL1 controller */ + sysctl_pll1_t pll1; + /* No. 4 (0x10): PLL2 controller */ + sysctl_pll2_t pll2; + /* No. 5 (0x14): Reserved */ + uint32_t resv5; + /* No. 6 (0x18): PLL lock tester */ + sysctl_pll_lock_t pll_lock; + /* No. 7 (0x1c): AXI ROM detector */ + sysctl_rom_error_t rom_error; + /* No. 8 (0x20): Clock select controller0 */ + sysctl_clk_sel0_t clk_sel0; + /* No. 9 (0x24): Clock select controller1 */ + sysctl_clk_sel1_t clk_sel1; + /* No. 10 (0x28): Central clock enable */ + sysctl_clk_en_cent_t clk_en_cent; + /* No. 11 (0x2c): Peripheral clock enable */ + sysctl_clk_en_peri_t clk_en_peri; + /* No. 12 (0x30): Soft reset ctrl */ + sysctl_soft_reset_t soft_reset; + /* No. 13 (0x34): Peripheral reset controller */ + sysctl_peri_reset_t peri_reset; + /* No. 14 (0x38): Clock threshold controller 0 */ + sysctl_clk_th0_t clk_th0; + /* No. 15 (0x3c): Clock threshold controller 1 */ + sysctl_clk_th1_t clk_th1; + /* No. 16 (0x40): Clock threshold controller 2 */ + sysctl_clk_th2_t clk_th2; + /* No. 17 (0x44): Clock threshold controller 3 */ + sysctl_clk_th3_t clk_th3; + /* No. 18 (0x48): Clock threshold controller 4 */ + sysctl_clk_th4_t clk_th4; + /* No. 19 (0x4c): Clock threshold controller 5 */ + sysctl_clk_th5_t clk_th5; + /* No. 20 (0x50): Clock threshold controller 6 */ + sysctl_clk_th6_t clk_th6; + /* No. 21 (0x54): Miscellaneous controller */ + sysctl_misc_t misc; + /* No. 22 (0x58): Peripheral controller */ + sysctl_peri_t peri; + /* No. 23 (0x5c): SPI sleep controller */ + sysctl_spi_sleep_t spi_sleep; + /* No. 24 (0x60): Reset source status */ + sysctl_reset_status_t reset_status; + /* No. 25 (0x64): DMA handshake selector */ + sysctl_dma_sel0_t dma_sel0; + /* No. 26 (0x68): DMA handshake selector */ + sysctl_dma_sel1_t dma_sel1; + /* No. 27 (0x6c): IO Power Mode Select controller */ + sysctl_power_sel_t power_sel; + /* No. 28 (0x70): Reserved */ + uint32_t resv28; + /* No. 29 (0x74): Reserved */ + uint32_t resv29; + /* No. 30 (0x78): Reserved */ + uint32_t resv30; + /* No. 31 (0x7c): Reserved */ + uint32_t resv31; +} __attribute__((packed, aligned(4))) sysctl_t; + +/** + * @brief Abstruct PLL struct + */ +typedef struct _sysctl_general_pll +{ + uint32_t clkr : 4; + uint32_t clkf : 6; + uint32_t clkod : 4; + uint32_t bwadj : 6; + uint32_t pll_reset : 1; + uint32_t pll_pwrd : 1; + uint32_t pll_intfb : 1; + uint32_t pll_bypass : 1; + uint32_t pll_test : 1; + uint32_t pll_out_en : 1; + uint32_t pll_ckin_sel : 2; + uint32_t reserved : 4; +} __attribute__((packed, aligned(4))) sysctl_general_pll_t; + +/** + * @brief System controller object instanse + */ +extern volatile sysctl_t *const sysctl; + +/** + * @brief Enable clock for peripheral + * + * @param[in] clock The clock to be enable + * + * @return result + * - 0 Success + * - Other Fail + */ +int sysctl_clock_enable(sysctl_clock_t clock); + +/** + * @brief Enable clock for peripheral + * + * @param[in] clock The clock to be disable + * + * @return result + * - 0 Success + * - Other Fail + */ +int sysctl_clock_disable(sysctl_clock_t clock); + +/** + * @brief Sysctl clock set threshold + * + * @param[in] which Which threshold to set + * @param[in] threshold The threshold value + * + * @return result + * - 0 Success + * - Other Fail + */ +int sysctl_clock_set_threshold(sysctl_threshold_t which, int threshold); + +/** + * @brief Sysctl clock get threshold + * + * @param[in] which Which threshold to get + * + * @return The threshold value + * - Other Value of threshold + * - -1 Fail + */ +int sysctl_clock_get_threshold(sysctl_threshold_t which); + +/** + * @brief Sysctl clock set clock select + * + * @param[in] which Which clock select to set + * @param[in] select The clock select value + * + * @return result + * - 0 Success + * - Other Fail + */ +int sysctl_clock_set_clock_select(sysctl_clock_select_t which, int select); + +/** + * @brief Sysctl clock get clock select + * + * @param[in] which Which clock select to get + * + * @return The clock select value + * - Other Value of clock select + * - -1 Fail + */ +int sysctl_clock_get_clock_select(sysctl_clock_select_t which); + +/** + * @brief Get PLL frequency + * + * @param[in] pll The PLL id + * + * @return The frequency of PLL + */ +uint32_t sysctl_pll_get_freq(sysctl_pll_t pll); + +/** + * @brief Get base clock frequency by clock id + * + * @param[in] clock The clock id + * + * @return The clock frequency + */ +uint32_t sysctl_clock_get_freq(sysctl_clock_t clock); + +/** + * @brief Reset device by reset controller + * + * @param[in] reset The reset signal + */ +void sysctl_reset(sysctl_reset_t reset); + +/** + * @brief Enable the PLL and power on with reset + * + * @param[in] pll The pll id + * + * @return Result + * - 0 Success + * - Other Fail + */ +int sysctl_pll_enable(sysctl_pll_t pll); + +/** + * @brief Disable the PLL and power off + * + * @param[in] pll The pll id + * + * @return Result + * - 0 Success + * - Other Fail + */ +int sysctl_pll_disable(sysctl_pll_t pll); + +/** + * @brief Select DMA channel handshake peripheral signal + * + * @param[in] channel The DMA channel + * @param[in] select The peripheral select + * + * @return Result + * - 0 Success + * - Other Fail + */ +int sysctl_dma_select(sysctl_dma_channel_t channel, sysctl_dma_select_t select); + +/** + * @brief Set SPI0_D0-D7 DVP_D0-D7 as spi and dvp data pin + * + * @param[in] en Enable or not + * + * @return Result + * - 0 Success + * - Other Fail + */ +uint32_t sysctl_set_spi0_dvp_data(uint8_t en); + +/** + * @brief Set io power mode + * + * @param[in] power_bank IO power bank + * @param[in] io_power_mode Set power mode 3.3v or 1.8 + * + * @return Result + * - 0 Success + * - Other Fail + */ +void sysctl_set_power_mode(sysctl_power_bank_t power_bank, sysctl_io_power_mode_t io_power_mode); + +/** + * @brief get the frequency of CPU + * + * @return The frequency of CPU + */ +uint32_t sysctl_cpu_get_freq(void); + +/** + * @brief Set frequency of CPU + * @param[in] freq The desired frequency in Hz + * + * @return The actual frequency of CPU after set + */ +uint32_t sysctl_cpu_set_freq(uint32_t freq); + +/** + * @brief Init PLL freqency + * @param[in] pll The PLL id + * @param[in] pll_freq The desired frequency in Hz + + */ +uint32_t sysctl_pll_set_freq(sysctl_pll_t pll, uint32_t pll_freq); + +/** + * @brief Enable interrupt + */ +void sysctl_enable_irq(void); + +/** + * @brief Disable interrupt + */ +void sysctl_disable_irq(void); + +/** + * @brief Get the time start up to now + * + * @return The time of microsecond + */ +uint64_t sysctl_get_time_us(void); + +/** + * @brief Get reset status + * + * @return The status of reset + */ +sysctl_reset_enum_status_t sysctl_get_reset_status(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_SYSCTL_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/Kconfig new file mode 100755 index 000000000..3db813e68 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/Kconfig @@ -0,0 +1,1630 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +menu "LCD Driver Support" + +menuconfig LCD + bool "Graphic LCD Driver Support" + default n + ---help--- + Drivers for parallel and serial LCD and OLED type devices. These + drivers support interfaces as defined in include/nuttx/lcd/lcd.h + + This selection is necessary to enable support for LCD drivers in + drivers/lcd as well as for board-specific LCD drivers in the boards/ + subdirectories. + +if LCD + +config LCD_PACKEDMSFIRST + bool + default n + +comment "Common Graphic LCD Settings" + +config LCD_DEV + bool "LCD character device" + default n + ---help--- + This option enables support for a character driver which exposes + LCD operations to userspace via ioctl() commands. This is useful when + not using NXGraphics but an alternative graphics library such as LVGL. + +config LCD_FRAMEBUFFER + bool "LCD framebuffer front end" + default n + select FB_UPDATE + ---help--- + Enable a "front end" that converts an sequential LCD driver into a + standard, NuttX frame buffer driver. + + NOTE: Some LCD drivers implement an internal framebuffer for + efficiency reasons but do not export a framebuffer interface. So + those LCD cannot be used as framebuffer drivers. If the option is + available, then such internal framebuffer support should be + disabled because this external common framebuffer interface will + provide the necessary buffering. + +config LCD_EXTERNINIT + bool "External LCD Initialization" + default n + depends on LCD_FRAMEBUFFER + ---help--- + Define to support external LCD initialization by platform-specific + code. If this option is defined, then the LCD framebuffer + emulation will call board_graphics_setup() to initialize the + graphics device. This option is necessary if display is used that + cannot be initialized using the standard LCD interfaces. + +menu "LCD driver selection" + +config LCD_NOGETRUN + bool "Write-only LCD" + default n + ---help--- + Many LCD hardware interfaces provide only minimal graphics capability. In + particularly, many simple LCD interfaces are write only. That is we, can + write graphics data to the LCD device memory, but we cannot read it back. + If the LCD hardware does not support reading the graphics memory, then + this option should be defined so that the NX layer can taking alternative + measures when the LCD is not readable. For example, if the LCD is not + readable, then NX will not attempt to support transparency. + + See also NX_WRITEONLY in the graphics support menu. + +config LCD_MAXCONTRAST + int "LCD maximum contrast" + default 31 if AQM_1248A + default 63 if LCD_SHARP_MEMLCD + default 255 if LCD_P14201 || LCD_LCD1602 + default 63 + range 1 255 + ---help--- + must be 63 with the Epson controller and 127 with + the Phillips controller. + +config LCD_MAXPOWER + int "LCD maximum power" + default 255 if LCD_LCD1602 + default 1 + range 1 255 + ---help--- + Maximum value of LCD power setting. This normally equates to brightness: + The brighter the screen, the high the power usage. + + On LCDs that have a backlight, this value corresponds directly to that + backlight setting. Board-specific logic may place restrictions on this + value. + +comment "Graphic LCD Devices" + +config LCD_P14201 + bool "Rit P1402 series display" + default n + ---help--- + p14201.c. Driver for RiT P14201 series display with SD1329 IC + controller. This OLED is used with older versions of the + TI/Luminary LM3S8962 Evaluation Kit. + +if LCD_P14201 +config P14201_NINTERFACES + int "Number of physical P14201 devices" + default 1 + range 1 1 + ---help--- + Specifies the number of physical P14201 + devices that will be supported. + +config P14201_SPIMODE + int "SPI mode" + default 2 + range 0 3 + ---help--- + Controls the SPI mode + +config P14201_FREQUENCY + int "SPI frequency" + default 1000000 + ---help--- + Define to use a different bus frequency,FIXME DEFAULT VALUE OK? + +config P14201_FRAMEBUFFER + bool "Enable P14201 GDDRAM cache" + default y + ---help--- + If defined, accesses will be performed + using an in-memory copy of the OLEDs GDDRAM. This cost of this + buffer is 128 * 96 / 2 = 6Kb. If this is defined, then the driver + will be fully functional. If not, then it will have the following + limitations: + + Reading graphics memory cannot be supported, and + + All pixel writes must be aligned to byte boundaries. + The latter limitation effectively reduces the 128x96 display to 64x96. + + NOTE: This option should not be used if CONFIG_LCD_FRAMBEBUFFER is + enabled. That options provides for a more generalized, external + LCD framebuffer. This internal framebuffer support should not be + enabled with CONFIG_LCD_FRAMBEBUFFER because this external common + framebuffer interface will provide the necessary buffering. +endif + +config LCD_MAX7219 + bool "Matrix of 8x8 LEDs controlled by MAX7219" + default n + ---help--- + Matrix of LEDs (8x8) controlled by MAX7219. + You can use cluster of 8x8 chained together. + +if LCD_MAX7219 + +config MAX7219_NHORIZONTALBLKS + int "Number of 8x8 LEDs matrices in the horizontal (width)!" + default 1 + ---help--- + Specifies the number of physical 8x8 LED matrices that are + connected together in the horizontal. In fact we have only + a single strip, but it can be arranged in blocks creating + physically horizontal/vertical columns/rows. + +config MAX7219_NVERTICALBLKS + int "Number of 8x8 LEDs matrices in the vertical (height)!" + default 1 + ---help--- + Specifies the number of physical 8x8 LED matrices that are + connected together in the vertical. In fact we have only + a single strip, but it can be arranged in blocks creating + physically horizontal/vertical columns/rows. + +config MAX7219_INTENSITY + int "Default LED Matrix bright intensity" + default 10 + range 0 15 + ---help--- + Specifies the default LEDs bright intensity to use. + +endif # LCD_MAX7219 + +config LCD_MIO283QT2 + bool "MIO283QT-2 TFT LCD Display Module" + default n + ---help--- + OLED Display Module, MIO283QT-2, Multi-Inno Technology, Co. + based on the Himax HX8347-D LCD controller. + +config LCD_MIO283QT9A + bool "MIO283QT-9A TFT LCD Display Module" + default n + ---help--- + Selects the driver for the MI0283QT-9A LCD from Multi-Inno + Technology Co., Ltd. This LCD is based on the Ilitek ILI9341 + LCD controller. + +config LCD_UG9664HSWAG01 + bool "UG-9664HSWAG01 OLED Display Module" + default n + depends on SPI + ---help--- + OLED Display Module, UG-9664HSWAG01, Univision Technology Inc. Used + with the LPCXpresso and Embedded Artists base board. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + +if LCD_UG9664HSWAG01 + +config UG9664HSWAG01_SPIMODE + int "UG-9664HSWAG01 SPI Mode" + default 0 + range 0 3 + ---help--- + Controls the SPI mode + +config UG9664HSWAG01_FREQUENCY + int "UG-9664HSWAG01 SPI Frequency" + default 3500000 + ---help--- + Define to use a different bus frequency + +config UG9664HSWAG01_NINTERFACES + int "Number of UG-9664HSWAG01 Devices" + default 1 + ---help--- + Specifies the number of physical UG-9664HSWAG01 devices that will be + supported. NOTE: At present, this must be undefined or defined to be 1. + +config UG9664HSWAG01_POWER + bool "Power control" + default n + ---help--- + If the hardware supports a controllable OLED a power supply, this + configuration should be defined. In this case the system must + provide an interface ug_power(). + +endif + +config LCD_SH1106_OLED_132 + bool "Generic 0.96'' OLED Display Module (SH1106/SSD1306)" + default n + select LCD_SSD1306 + ---help--- + 0.96'' OLED Display Module, featuring an SH1106, typically advertised as + SSD1306. Mostly similar to "UG2864HSWEG01" although it uses the full + 132x28 pixels. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + +config LCD_UG2864HSWEG01 + bool "UG-2864HSWEG01 OLED Display Module (SSD1306)" + default n + select LCD_SSD1306 + ---help--- + OLED Display Module, UG-2864HSWEG01, Univision Technology Inc based + on the Solomon Tech SSD1306 LCD controller. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + +config LCD_UG2832HSWEG04 + bool "UG-2832HSWEG04 OLED Display Module (SSD1306)" + default n + select LCD_SSD1306 + ---help--- + OLED Display Module, UG-UG2832HSWEG04, Univision Technology Inc + based on the Solomon Tech SSD1306 LCD controller. Used with the + Atmel SAM4L Xplained Pro board on the OLED1 module. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + +config LCD_DD12864WO4A + bool "DD-12864WO-4A OLED Display Module" + default n + select LCD_SSD1306 + select SPI_CMDDATA + ---help--- + OLED Display Module, DD-12864WO-4A, Densitron Technologies + based on the Solomon Tech SSD1309 LCD controller. Used with the + ThingseeOne board. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + +config LCD_HILETGO + bool "HiletGO 128x64 OLED" + default n + select LCD_SSD1306 + select SPI_CMDDATA + ---help--- + HiletGo 129x64 OLED Display Module, featuring an SSD1306. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + +config LCD_SSD1306 + bool + +if LCD_SSD1306 + +choice + prompt "SSD1306 Interface" + default LCD_SSD1306_SPI + +config LCD_SSD1306_SPI + bool "SSD1306 on SPI Interface" + select SPI + ---help--- + Enables support for the SPI interface. + +config LCD_SSD1306_I2C + bool "SSD1306 on I2C Interface" + select I2C + ---help--- + Enables support for the I2C interface + +endchoice # SSD1306 Interface +endif # LCD_SSD1306 + +if LCD_SSD1306_SPI + +config SSD1306_SPIMODE + int "SSD1306 SPI Mode" + default 0 if !LCD_DD12864WO4A + default 3 if LCD_DD12864WO4A + range 0 3 + ---help--- + Selects the SPI mode used with the SSD1306 device + +config SSD1306_FREQUENCY + int "SSD1306 SPI Frequency" + default 3500000 if !LCD_DD12864WO4A + default 10000000 if LCD_DD12864WO4A + ---help--- + Selects the SPI bus frequency used with the SSD1306 device + +endif # LCD_SSD1306_SPI + +if LCD_SSD1306_I2C + +config SSD1306_I2CADDR + int "SSD1306 I2C Address" + default 60 + ---help--- + 7-bit I2C Address of SSD1306. Typical addresses are 0x3c (60) or + 0x3d (61). NOTE that these correspond to the 8-bit addresses + 0x78 or 0x7a that you may see in documentation. + +config SSD1306_I2CFREQ + int "SSD1306 I2C Frequency" + default 400000 + ---help--- + I2C Frequency to communicate with SSD1306 + +endif # LCD_SSD1306_I2C + +config LCD_SSD1351 + bool "SSD1351 OLED Display Module" + default n + ---help--- + OLED Display Module, SSD1351, Solomon Systech. + +if LCD_SSD1351 + +choice + prompt "Interface" + default SSD1351_SPI4WIRE + +config SSD1351_PARALLEL8BIT + bool "8-bit Parallel Interface" + ---help--- + Enables support for the 8-bit parallel interface. + +config SSD1351_SPI3WIRE + bool "3-wire SPI Interface" + select SPI + ---help--- + Enables support for the 3-wire SPI interface. + +config SSD1351_SPI4WIRE + bool "4-wire SPI Interface" + select SPI + select SPI_CMDDATA + ---help--- + Enables support for the 4-wire SPI interface. + +endchoice + +if SSD1351_SPI3WIRE || SSD1351_SPI4WIRE + +config SSD1351_SPIMODE + int "SPI Mode" + default 0 + range 0 3 + ---help--- + Specifies the SPI mode. + +config SSD1351_SPIFREQ + int "SPI Frequency" + default 1000000 + ---help--- + Specifies the SPI frequency. + +endif + +config SSD1351_NINTERFACES + int "Number of SSD1351 Devices" + default 1 + range 1 1 + ---help--- + Specifies the number of physical SSD1351 devices that will + be supported. + +config SSD1351_XRES + int "X Resolution" + default 128 + range 1 128 + ---help--- + Specifies the X resolution of the display. + +config SSD1351_YRES + int "Y Resolution" + default 128 + range 1 128 + ---help--- + Specifies the Y resolution of the display. + +config SSD1351_MIRRORX + bool "Mirror X" + default n + ---help--- + Mirrors the display along the X axis. + +config SSD1351_MIRRORY + bool "Mirror Y" + default n + ---help--- + Mirrors the display along the Y axis. + +config SSD1351_INVERT + bool "Invert Display" + default n + ---help--- + Inverts the display. + +config SSD1351_VDDEXT + bool "External VDD" + default n + ---help--- + Specifies that VDD is external. + +config SSD1351_TRST + int "Reset Period" + default 5 + range 5 31 + ---help--- + Specifies the reset period in DCLKs. + +config SSD1351_TPRECHG1 + int "First Pre-charge Period" + default 8 + range 3 15 + ---help--- + Specifies the first pre-charge period in DCLKs. + +config SSD1351_PERFENHANCE + bool "Enhance Display Performance" + default n + ---help--- + Enhances the display performance. + +config SSD1351_CLKDIV + int "Clock Divider" + default 0 + range 0 10 + ---help--- + Specifies the clock divider. + +config SSD1351_OSCFREQ + int "Oscillator Frequency" + default 15 + range 0 15 + ---help--- + Specifies the oscillator frequency. + +config SSD1351_TPRECHG2 + int "Second Pre-charge Period" + default 8 + range 1 15 + ---help--- + Specifies the second pre-charge period in DCLKs. + +config SSD1351_VPRECHG + int "Voltage Pre-charge Level" + default 50 + range 20 60 + ---help--- + Specifies the pre-charge voltage level as a percentage of VCC. + +config SSD1351_VCOMH + int "COM Deselect Voltage Level" + default 82 + range 72 86 + ---help--- + Specifies the COM deselect voltage level as a percentage of VCC. + +config SSD1351_CONTRASTA + int "Color A Contrast" + default 138 + range 0 255 + ---help--- + Specifies the contrast of color A. + +config SSD1351_CONTRASTB + int "Color B Contrast" + default 81 + range 0 255 + ---help--- + Specifies the contrast of color B. + +config SSD1351_CONTRASTC + int "Color C Contrast" + default 138 + range 0 255 + ---help--- + Specifies the contrast of color C. + +config SSD1351_MSTRCONTRAST + int "Master Contrast Ratio" + default 16 + range 1 16 + ---help--- + Specifies the master contrast ratio in sixteenths. + +endif + +config LCD_ST7735 + bool "Sitronix ST7735 TFT Controller" + default n + +if LCD_ST7735 + choice + prompt "LCD Preset Resolutions" + optional + + config LCD_ST7735_GM11 + bool "128x160" + + config LCD_ST7735_GM00 + bool "132x162" + + config LCD_ST7735_GM01 + bool "132x132" + + endchoice + +if !LCD_ST7735_GM00 && !LCD_ST7735_GM01 && !LCD_ST7735_GM11 + + config LCD_ST7735_XRES + int "ST7735 X Resolution" + default 128 + ---help--- + Specifies the X resolution of the LCD. + + config LCD_ST7735_YRES + int "ST7735 Y Resolution" + default 160 + ---help--- + Specifies the Y resolution of the LCD. + + config LCD_ST7735_XOFFSET + int "ST7735 X Offset" + default 0 + ---help--- + Specifies the X offset of the LCD. + + config LCD_ST7735_YOFFSET + int "ST7735 Y Offset" + default 0 + ---help--- + Specifies the Y offset of the LCD. + +endif + + config LCD_ST7735_BGR + bool "Swap R & B channel" + default n + + config LCD_ST7735_BPP + int "Bit Per Pixel (12, 16 or 18)" + default 16 + + config LCD_ST7735_SPIMODE + int "SPI Mode" + default 0 + + config LCD_ST7735_FREQUENCY + int "SPI Frequency" + default 3000000 + +endif # LCD_ST7735 + +config LCD_ST7789 + bool "Sitronix ST7789 TFT Controller" + default n + +if LCD_ST7789 + config LCD_ST7789_XRES + int "ST7789 X Resolution" + default 240 + ---help--- + Specifies the X resolution of the LCD. + + config LCD_ST7789_YRES + int "ST7789 Y Resolution" + default 320 + ---help--- + Specifies the Y resolution of the LCD. + + config LCD_ST7789_XOFFSET + int "ST7789 X Offset" + default 0 + ---help--- + Specifies the X offset of the LCD. + + config LCD_ST7789_YOFFSET + int "ST7789 Y Offset" + default 0 + ---help--- + Specifies the Y offset of the LCD. + + config LCD_ST7789_BPP + int "Bit Per Pixel (12 or 16)" + default 16 + + config LCD_ST7789_SPIMODE + int "SPI Mode" + default 0 + + config LCD_ST7789_FREQUENCY + int "SPI Frequency" + default 1000000 + +endif # LCD_ST7789 + +config LCD_GC9A01 + bool "Galaxycore GC9A01 TFT Controller" + default n + +if LCD_GC9A01 + config LCD_GC9A01_XRES + int "GC9A01 X Resolution" + default 240 + ---help--- + Specifies the X resolution of the LCD. + + config LCD_GC9A01_YRES + int "GC9A01 Y Resolution" + default 240 + ---help--- + Specifies the Y resolution of the LCD. + + config LCD_GC9A01_XOFFSET + int "GC9A01 X Offset" + default 0 + ---help--- + Specifies the X offset of the LCD. + + config LCD_GC9A01_YOFFSET + int "GC9A01 Y Offset" + default 0 + ---help--- + Specifies the Y offset of the LCD. + + config LCD_GC9A01_BGR + bool "Swap R & B channel" + default n + + config LCD_GC9A01_BPP + int "Bit Per Pixel (12 or 16)" + default 16 + + config LCD_GC9A01_SPIMODE + int "SPI Mode" + default 0 + + config LCD_GC9A01_FREQUENCY + int "SPI Frequency" + default 1000000 + +endif # LCD_GC9A01 + +config LCD_PCD8544 + bool "Nokia 5110 LCD Display (Philips PCD8544)" + default n + ---help--- + LCD Display Module, PCD8544, Philips + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + +if LCD_PCD8544 + +config PCD8544_NINTERFACES + int "Number of PCD8544 Devices" + default 1 + ---help--- + Specifies the number of physical PCD8544 devices that will be + supported. NOTE: At present, this must be undefined or defined to be 1. + +config PCD8544_XRES + int "PCD8544 X Resolution" + default 84 + ---help--- + Specifies the X resolution of the LCD. + +config PCD8544_YRES + int "PCD8544 Y Resolution" + default 48 + ---help--- + Specifies the Y resolution of the LCD. + +config PCD8544_INVERSE_VIDEO + bool "PCD8544 Inverse video" + default n + ---help--- + Inverse video on LCD. + +endif # LCD_PCD8544 + +config LCD_ST7565 + bool "ST7565 LCD Display Module" + default n + ---help--- + LCD Display Module, ST7565, Univision Technology Inc. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + +if LCD_ST7565 + +choice + prompt "LCD Display Module initialization sequence" + default NHD_C12864KGZ + +config NHD_C12864KGZ + bool "like NHD C12864KGZ" + +config ERC_12864_3 + bool "like ERC12864-3" + +config AQM_1248A + bool "like AQM1248A" + +endchoice + +config ST7565_NINTERFACES + int "Number of ST7565 Devices" + default 1 + ---help--- + Specifies the number of physical ST7565 devices that will be + supported. NOTE: At present, this must be undefined or defined to be 1. + +config ST7565_XRES + int "ST7565 X Resolution" + default 128 + ---help--- + Specifies the X resolution of the LCD. + +config ST7565_YRES + int "ST7565 Y Resolution" + default 48 if AQM_1248A + default 64 + ---help--- + Specifies the Y resolution of the LCD. + +config ST7565_MIRROR_X + bool "ST7565 apply mirror on X" + default n + ---help--- + Mirror X on LCD. + +config ST7565_MIRROR_Y + bool "ST7565 apply mirror on Y" + default y if AQM_1248A + default n + ---help--- + Mirror Y on LCD. + +config ST7565_INVERSE_VIDEO + bool "ST7565 Inverse video" + default n + ---help--- + Inverse video on LCD. + +endif # LCD_ST7565 + +config LCD_ST7567 + bool "ST7567 LCD Display Module" + default n + ---help--- + LCD Display Module, ST7567, Univision Technology Inc. Used + with the LPCXpresso and Embedded Artists base board. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + +if LCD_ST7567 + +config ST7567_SPIMODE + int "ST7567 SPI Mode" + default 0 + range 0 3 + ---help--- + Controls the SPI mode + +config ST7567_FREQUENCY + int "ST7567 SPI Frequency" + default 3500000 + ---help--- + Define to use a different bus frequency + +config ST7567_NINTERFACES + int "Number of ST7567 Devices" + default 1 + ---help--- + Specifies the number of physical ST7567 devices that will be + supported. NOTE: At present, this must be undefined or defined to be 1. + +config ST7567_POWER + bool "Power control" + default n + ---help--- + If the hardware supports a controllable LCD a power supply, this + configuration should be defined. In this case the system must + provide an interface ug_power(). + +config ST7567_XRES + int "ST7567 X Resolution" + default 128 + ---help--- + Specifies the X resolution of the LCD. + +config ST7567_YRES + int "ST7567 Y Resolution" + default 64 + ---help--- + Specifies the Y resolution of the LCD. + +endif # LCD_ST7567 + +config LCD_UG2864AMBAG01 + bool "UG-2864AMBAG01 OLED Display Module" + default n + ---help--- + OLED Display Module, UG-2864AMBAG01, Univision Technology Inc. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + +if LCD_UG2864AMBAG01 + +config UG2864AMBAG01_SPIMODE + int "UG-2864AMBAG01 SPI Mode" + default 3 + range 0 3 + ---help--- + Controls the SPI mode + +config UG2864AMBAG01_FREQUENCY + int "UG-2864AMBAG01 SPI Frequency" + default 3500000 + ---help--- + Define to use a different bus frequency + +config UG2864AMBAG01_NINTERFACES + int "Number of UG-2864AMBAG01 Devices" + default 1 + ---help--- + Specifies the number of physical UG-9664HSWAG01 devices that will be + supported. NOTE: At present, this must be undefined or defined to be 1. + +endif + +config LCD_SSD1289 + bool "LCD Based on SSD1289 Controller" + default n + ---help--- + Enables generic support for any LCD based on the Solomon Systech, + Ltd, SSD1289 Controller. Use of this driver will usually require so + detailed customization of the LCD initialization code as necessary + for the specific LCD driven by the SSD1289 controller. + +if LCD_SSD1289 + +choice + prompt "SSD1289 Initialization Profile" + default SSD1289_PROFILE1 + +config SSD1289_PROFILE1 + bool "Profile 1" + +config SSD1289_PROFILE2 + bool "Profile 2" + +config SSD1289_PROFILE3 + bool "Profile 3" + +endchoice +endif + +config LCD_SHARP_MEMLCD + bool "Sharp Memory LCD Suite" + default n + ---help--- + memlcd.c. Driver for Sharp Memory LCD Suite. + +if LCD_SHARP_MEMLCD + +choice + prompt "Memory LCD Model" + default MEMLCD_LS013B7DH03 + +config MEMLCD_LS013B7DH01 + bool "LS013B7DH01" + ---help--- + Selects the LS013B7DH01 model + +config MEMLCD_LS013B7DH03 + bool "LS013B7DH03" + ---help--- + Selects the LS013B7DH03 model + +endchoice + +config MEMLCD_NINTERFACES + int "Number of physical Memory LCD devices" + default 1 + range 1 1 + ---help--- + Specifies the number of physical Memory LCD devices that will + be supported. + +config MEMLCD_EXTCOMIN_MODE_HW + bool "Use hardware mode for EXTCOMIN" + default n + ---help--- + If use hardware mode to toggle VCOM, we need to send specific + command at a constant frequency to trigger the LCD internal + hardware logic. While use software mode, we set up a timer to + toggle EXTCOMIN connected IO, basically, it is a hardware + timer to ensure a constant frequency. + +config MEMLCD_SPI_FREQUENCY + int "SPI frequency" + default 3500000 + ---help--- + Define to use a different bus frequency, FIXME DEFAULT VALUE OK? + +endif + +choice + prompt "LCD Orientation" + default LCD_LANDSCAPE + depends on LCD + ---help--- + Some LCD drivers may support displays in different orientations. + If the LCD driver supports this capability, than these are configuration + options to select that display orientation. + +config LCD_LANDSCAPE + bool "Landscape orientation" + ---help--- + Define for "landscape" orientation support. Landscape mode refers one + of two orientations where the display is wider than it is tall + (LCD_RLANDSCAPE is the other). This is the default orientation. + +config LCD_PORTRAIT + bool "Portrait orientation" + ---help--- + Define for "portrait" orientation support. Portrait mode refers one + of two orientations where the display is taller than it is wide + (LCD_RPORTAIT is the other). + +config LCD_RPORTRAIT + bool "Reverse portrait display" + ---help--- + Define for "reverse portrait" orientation support. Reverse portrait mode + refers one of two orientations where the display is taller than it is + wide (LCD_PORTAIT is the other). + +config LCD_RLANDSCAPE + bool "Reverse landscape orientation" + ---help--- + Define for "reverse landscape" orientation support. Reverse landscape mode + refers one of two orientations where the display is wider than it is + tall (LCD_LANDSCAPE is the other). + +endchoice + +config LCD_LPM013M091A + bool "JDI LPM013M091A LCD Driver" + default n + ---help--- + JDI LPM013M091A LCD Driver. + This driver doesn't support reading data. + Recommended to use DMA to transfer data or displayed image would be + broken. + +config LCD_ILI9225 + bool "ILI9225 LCD Single Chip Driver" + default n + ---help--- + LCD Single Chip Driver, ILI9225, ILI Technology Corp. + +if LCD_ILI9225 + config LCD_ILI9225_XRES + int "ILI9225 X Resolution" + default 176 + ---help--- + Specifies the X resolution of the LCD. + + config LCD_ILI9225_YRES + int "ILI9225 Y Resolution" + default 220 + ---help--- + Specifies the Y resolution of the LCD. + + config LCD_ILI9225_BPP + int "Bit Per Pixel (16)" + default 16 + + config LCD_ILI9225_SPIMODE + int "SPI Mode" + default 0 + + config LCD_ILI9225_FREQUENCY + int "SPI Frequency" + default 1000000 + +endif # LCD_ILI9225 + +config LCD_ILI9340 + bool "ILI9340 LCD Single Chip Driver" + default n + ---help--- + LCD Single Chip Driver, ILI9340, ILI Technology Corp. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + +config LCD_ILI9340_NINTERFACES + int "Number of supported display driver" + range 1 2 + default 1 + depends on LCD_ILI9340 + ---help--- + Define the number of supported displays driven by a ili9340 LCD Single + Chip Driver. + +config LCD_ILI9340_IFACE0 + bool "(1) LCD Display" + depends on LCD_ILI9340_NINTERFACES = 1 || LCD_ILI9340_NINTERFACES = 2 + ---help--- + Configure first LCD Display. + +if LCD_ILI9340_IFACE0 +choice + prompt "LCD Orientation" + default LCD_ILI9340_IFACE0_LANDSCAPE + ---help--- + Configure display orientation. + +config LCD_ILI9340_IFACE0_LANDSCAPE + bool "Landscape orientation" + ---help--- + Define for "landscape" orientation support. + +config LCD_ILI9340_IFACE0_PORTRAIT + bool "Portrait orientation" + ---help--- + Define for "portrait" orientation support. + +config LCD_ILI9340_IFACE0_RLANDSCAPE + bool "Reverse landscape orientation" + ---help--- + Define for "reverse landscape" orientation support. + +config LCD_ILI9340_IFACE0_RPORTRAIT + bool "Reverse portrait display" + ---help--- + Define for "reverse portrait" orientation support. + +endchoice + +choice + prompt "Color format" + default LCD_ILI9340_IFACE0_RGB565 + ---help--- + LCD color format. + +config LCD_ILI9340_IFACE0_RGB565 + bool "16 bpp RGB565 color format" + ---help--- + 16 bpp RGB565 color format + +endchoice +endif + +config LCD_ILI9340_IFACE1 + bool "(2) LCD Display" + depends on LCD_ILI9340_NINTERFACES = 2 + ---help--- + Configure second LCD Display. + +if LCD_ILI9340_IFACE1 +choice + prompt "LCD Orientation" + default LCD_ILI9340_IFACE1_LANDSCAPE + ---help--- + Configure display orientation. + +config LCD_ILI9340_IFACE1_LANDSCAPE + bool "Landscape orientation" + ---help--- + Define for "landscape" orientation support. + +config LCD_ILI9340_IFACE1_PORTRAIT + bool "Portrait orientation" + ---help--- + Define for "portrait" orientation support. + +config LCD_ILI9340_IFACE1_RLANDSCAPE + bool "Reverse landscape orientation" + ---help--- + Define for "reverse landscape" orientation support. + +config LCD_ILI9340_IFACE1_RPORTRAIT + bool "Reverse portrait display" + ---help--- + Define for "reverse portrait" orientation support. + +endchoice + +choice + prompt "Color format" + default LCD_ILI9340_IFACE1_RGB565 + ---help--- + LCD color format. + +config LCD_ILI9340_IFACE1_RGB565 + bool "16 bpp RGB565 color format" + ---help--- + 16 bpp RGB565 color format + +endchoice +endif + +config LCD_ILI9341 + bool "ILI9341 LCD Single Chip Driver" + default n + ---help--- + LCD Single Chip Driver, ILI9341, ILI Technology Corp. Used + with the STM32F429i Discovery Board. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + +config LCD_ILI9341_NINTERFACES + int "Number of supported display driver" + range 1 2 + default 1 + depends on LCD_ILI9341 + ---help--- + Define the number of supported displays driven by a ili9341 LCD Single + Chip Driver. + +config LCD_ILI9341_IFACE0 + bool "(1) LCD Display" + depends on LCD_ILI9341_NINTERFACES = 1 || LCD_ILI9341_NINTERFACES = 2 + ---help--- + Configure first LCD Display. + +if LCD_ILI9341_IFACE0 +choice + prompt "LCD Orientation" + default LCD_ILI9341_IFACE0_LANDSCAPE + ---help--- + Configure display orientation. + +config LCD_ILI9341_IFACE0_LANDSCAPE + bool "Landscape orientation" + ---help--- + Define for "landscape" orientation support. + +config LCD_ILI9341_IFACE0_PORTRAIT + bool "Portrait orientation" + ---help--- + Define for "portrait" orientation support. + +config LCD_ILI9341_IFACE0_RLANDSCAPE + bool "Reverse landscape orientation" + ---help--- + Define for "reverse landscape" orientation support. + +config LCD_ILI9341_IFACE0_RPORTRAIT + bool "Reverse portrait display" + ---help--- + Define for "reverse portrait" orientation support. + +endchoice + +choice + prompt "Color format" + default LCD_ILI9341_IFACE0_RGB565 + ---help--- + LCD color format. + +config LCD_ILI9341_IFACE0_RGB565 + bool "16 bpp RGB565 color format" + ---help--- + 16 bpp RGB565 color format + +endchoice +endif + +config LCD_ILI9341_IFACE1 + bool "(2) LCD Display" + depends on LCD_ILI9341_NINTERFACES = 2 + ---help--- + Configure second LCD Display. + +if LCD_ILI9341_IFACE1 +choice + prompt "LCD Orientation" + default LCD_ILI9341_IFACE1_LANDSCAPE + ---help--- + Configure display orientation. + +config LCD_ILI9341_IFACE1_LANDSCAPE + bool "Landscape orientation" + ---help--- + Define for "landscape" orientation support. + +config LCD_ILI9341_IFACE1_PORTRAIT + bool "Portrait orientation" + ---help--- + Define for "portrait" orientation support. + +config LCD_ILI9341_IFACE1_RLANDSCAPE + bool "Reverse landscape orientation" + ---help--- + Define for "reverse landscape" orientation support. + +config LCD_ILI9341_IFACE1_RPORTRAIT + bool "Reverse portrait display" + ---help--- + Define for "reverse portrait" orientation support. + +endchoice + +choice + prompt "Color format" + default LCD_ILI9341_IFACE1_RGB565 + ---help--- + LCD color format. + +config LCD_ILI9341_IFACE1_RGB565 + bool "16 bpp RGB565 color format" + ---help--- + 16 bpp RGB565 color format + +endchoice +endif + +config LCD_LCDDRV_SPIIF + bool "Generic SPI Interface Driver (for ILI9341 or others)" + default n +# depends on LCD_ILI9341 + ---help--- + SPI Interface shim to allow LCD and ePaper to be bound to + a normal SPI port. + +config LCD_LCDDRV_SPEED + int "Generic SPI Interface speed" + default 10000000 + depends on LCD_LCDDRV_SPIIF + ---help--- + SPI Interface speed. According to the specification this is generally + quite limited, but people have had success with much faster + speeds than the spec sheets say. YMMV. + +config LCD_RA8875 + bool "RA8875 LCD Display Controller" + default n + depends on ALLOW_BSD_COMPONENTS + ---help--- + LCD controller driver for RA8875 by RAiO Technologies Inc. + +if LCD_RA8875 + +choice + prompt "MCU Interface width" + default LCD_RA8875_8BIT + ---help--- + Bit-width of MCU interface (8 or 16) + +config LCD_RA8875_8BIT + bool "8 bit" + +config LCD_RA8875_16BIT + bool "16 bit" + +endchoice # MCU Interface width + +choice + prompt "Colors" + default LCD_RA8875_65K + ---help--- + Number of colors/color depth + +config LCD_RA8875_256 + bool "256 / 8 bit" + +config LCD_RA8875_65K + bool "65k / 16 bit" + +endchoice # Colors + +config LCD_RA8875_EXTENDED + bool "Extended drawing interfaces" + default n + depends on BUILD_FLAT + ---help--- + Build in some non-standard, custom drawing interfaces for the RA8875 + including the following: ra8875_drawrectangle(), ra8875_drawline(), + ra8875_drawtriangle(), and ra8875_drawcircle(). NOTE that these + will not be accessible by applications in protected or kernel build + configurations. + + NOTE: The non-standard ra8875_clear(), ra8875_drawrectangle(), + ra8875_drawline() interfaces are always built and available for use + because within the OS because these are used internally by the + driver anyway. + +endif # LCD_RA8875 + +config LCD_LT768 + bool "LT768 LCD Single Chip Driver" + default n + ---help--- + LCD Single Chip Driver, LT768, Levetop Electronics. Used + with the Xidatong-riscv64 Board. + +if LCD_LT768 + +choice + prompt "LCD LT768 part" + default LCD_LT768 + +endchoice # LCD LT768 part + +choice + prompt "LT768 Interface" + default LCD_LT768_SPI + +config LCD_LT768_SPI + bool "SPI" + select SPI + +endchoice # LT768 Interface + +choice + prompt "Display size" + default LCD_LT768_WQVGA + +config LCD_FT80X_WQVGA + bool "WQVGA 480x272" + +endchoice # Display size + +endif # LCD_LT768 + +config LCD_FT80X + bool "FTDI FT80x GUI Controller" + default n + select SCHED_HPWORK + ---help--- + Integrated LCD, Audio, Touchscreen controller driver for the FTDI + FT80x "EVE" series. + +if LCD_FT80X + +choice + prompt "FTDI FT80x part" + default LCD_FT800 + +config LCD_FT800 + bool "FT800" + +config LCD_FT801 + bool "FT801" + +endchoice # FTDI FT80x part + +choice + prompt "FTDI FT80x Interface" + default LCD_FT80X_SPI + +config LCD_FT80X_SPI + bool "SPI" + select SPI + +config LCD_FT80X_I2C + bool "I2C" + select I2C + +endchoice # FTDI FT80x Interface + +config LCD_FT801_MULTITOUCH + bool "FT801 Multi-touch" + default n + depends on LCD_FT801 + +choice + prompt "Display size" + default LCD_FT80X_WQVGA + +config LCD_FT80X_WQVGA + bool "WQVGA 480x272" + +config LCD_FT80X_QVGA + bool "QVGA 320x240" + +endchoice # Display size + +choice + prompt "Audio Shutdown Options" + default LCD_FT80X_AUDIO_NOSHUTDOWN + +config LCD_FT80X_AUDIO_NOSHUTDOWN + bool "No amplifier shutdown control" + ---help--- + There is no audio amplifier or the audio amplifier is not under + software control. + +config LCD_FT80X_AUDIO_MCUSHUTDOWN + bool "MCU controls audio shutdown" + ---help--- + The audio amplifier is controlled via an MCU GPIO output pin. + +config LCD_FT80X_AUDIO_GPIOSHUTDOWN + bool "FT80X controls audio shutdown" + ---help--- + The audio amplifier is controlled via an FT80x GPIO output pin. + +endchoice # Audio Shutdown Option + +config LCD_FT80X_AUDIO_GPIO + int "FT80x audio shutdown GPIO" + default 0 + range 0 1 + depends on LCD_FT80X_AUDIO_GPIOSHUTDOWN + ---help--- + Identifies the GPIO pin used to control the amplifier shutdown + output. + +endif # LCD_FT80X + +endmenu # LCD Driver selection +endif # LCD + +comment "Character/Segment LCD Devices" + +menuconfig SLCD + bool "Alphanumeric/Segment LCD Devices" + default n + ---help--- + Drivers for Alphanumeric and Segment LCDs (SLCDs). These + drivers support interfaces as defined in include/nuttx/lcd/slcd_ioctl.h + amd slcd_codec.h + + This selection is necessary to enable support for SLCD drivers in + drivers/lcd as well as for board-specific LCD drivers in the boards/ + subdirectories. + +if SLCD + +config SLCD_CONSOLE + bool "SLCD console output" + default n + ---help--- + It is possible to use an SLCD to provide console output. This option + enables that possibility. + + At present, only one architecture supports this option (M16C). + However, this feature could be provided by other architectures in + the future. + +config LCD_LCD1602 + bool "LCD 1602" + default n + ---help--- + Enable support for LCD1602 devices. LCD1602 is based on the Hitachi + HD44780U LCD controller. See also include/nuttx/lcd/hd4478ou.h. + + NOTE: There is no common implementation of the LCD1602 driver. + Rather, there are board-by-board implementations. + +config LCD_BACKPACK + bool "PCF8574 LCD Backpack" + default n + depends on I2C + select LIBC_SLCDCODEC + ---help--- + Enable support for PCF8574 LCD Backpack driver. This driver supports + an interface board that is based on the PCF8574 io expander and + supports the HD44780-based (or compatible) LCD modules. There are + a myriad of different vendors of such, but they are principally the + same, save wiring and minor features like jumpers for I2C addresses. + This driver supports known and unknown variants. + + See pcf8574_lcd_backpack_readme.txt + +config LCD_ST7032 + bool "ST7032 over I2C (i.e. JLX1602G-390)" + default n + depends on I2C + ---help--- + Enable support for ST7032i on I2C. This driver was tested with + JLX1602G-390 that has 10 pins: CAP1N, CAP1P, VOUT, VCC, SHLS, + SHLC, GND, SDA, SCL, XRESET. The XRESET pin is connected to a + pull-up resistor, then the module automatically executes power-on + reset when power is supplied to the module. The pin SHLS is also + connected to a pull-up resistor and the pin SHLC is connected to + the ground. So only I2C pins SDA and SCL are used by NuttX. + +config LCD_HT16K33 + bool "Holtek HT16K33 4 Digits 14-Segment Display" + default n + depends on I2C + ---help--- + Enable support for Holtek HT16K33 (and Vinka VK16K33) 4 Digits + 14-Segment module: 0.54" 14-segment LED HT16K33 Backpack. + +if LCD_HT16K33 +config LCD_HT16K33_MULT_MODULE + bool "Enable support to multiple modules as a single display" + default n + depends on I2C + ---help--- + It is possible to connect many HT16K33 modules with sequential + I2C addresses to work as a single display to support length + text strings. The device at the I2C address 0x70 will display the + 4 more significant characters, the device 0x71 will display the + previous 4 more significant characters and so on. + +config LCD_HT16K33_NUMBER_MODULES + int "Quantity of HT16K33 modules to be used as a single display" + range 1 8 + depends on LCD_HT16K33_MULT_MODULE + ---help--- + Quantity of sequential modules to be used to create a single + display. We can have up to 8 to I2C Addresses: 0x70 - 0x77. + +endif # LCD_HT16K33 + +endif # SLCD + +comment "Other LCD-related Devices" + +config LCD_OTHER + bool + default n + +config LCD_TDA19988 + bool "TDA19988 HDMI Encoder" + default n + select LCD_OTHER + depends on I2C && EXPERIMENTAL + ---help--- + Enable support for the TI TDA19988 HDMI Encoder. The TDA19988 is a + very low power and very small size High-Definition Multimedia + Interface (HDMI) 1.4a transmitter. This device is primarily + intended for mobile applications like Digital Video Camera (DVC), + Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile + Phone and Ultra-Mobile Personal Computer (UM PC), new PC tablet and + MID where size and power are key for battery autonomy. + +endmenu # LCD Driver Support diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/Make.defs new file mode 100755 index 000000000..392c7894d --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/Make.defs @@ -0,0 +1,183 @@ +############################################################################ +# drivers/lcd/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_LCD),y) + +# Support for the generic LCD framebuffer front-end + +ifeq ($(CONFIG_LCD_FRAMEBUFFER),y) + CSRCS += lcd_framebuffer.c +endif + +ifeq ($(CONFIG_LCD_DEV),y) + CSRCS += lcd_dev.c +endif + +# Include support for Graphics LCD drivers + +ifeq ($(CONFIG_LCD_FT80X),y) + CSRCS += ft80x.c +ifeq ($(CONFIG_LCD_FT80X_SPI),y) + CSRCS += ft80x_spi.c +else ifeq ($(CONFIG_LCD_FT80X_I2C),y) + CSRCS += ft80x_i2c.c +endif +endif + +ifeq ($(CONFIG_LCD_LPM013M091A),y) + CSRCS += lpm013m091a.c +endif + +ifeq ($(CONFIG_LCD_P14201),y) + CSRCS += p14201.c +endif + +ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) + CSRCS += ug-2864ambag01.c +endif + +ifeq ($(CONFIG_LCD_UG9664HSWAG01),y) + CSRCS += ug-9664hswag01.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += ssd1306_base.c +endif + +ifeq ($(CONFIG_LCD_SSD1306_SPI),y) + CSRCS += ssd1306_spi.c +endif + +ifeq ($(CONFIG_LCD_SSD1306_I2C),y) + CSRCS += ssd1306_i2c.c +endif + +ifeq ($(CONFIG_LCD_SSD1289),y) + CSRCS += ssd1289.c +endif + +ifeq ($(CONFIG_LCD_SSD1351),y) + CSRCS += ssd1351.c +endif + +ifeq ($(CONFIG_LCD_MIO283QT2),y) + CSRCS += mio283qt2.c +endif + +ifeq ($(CONFIG_LCD_MAX7219),y) + CSRCS += max7219.c +endif + +ifeq ($(CONFIG_LCD_MIO283QT9A),y) + CSRCS += mio283qt9a.c +endif + +ifeq ($(CONFIG_LCD_PCD8544),y) + CSRCS += pcd8544.c +endif + +ifeq ($(CONFIG_LCD_ST7565),y) + CSRCS += st7565.c +endif + +ifeq ($(CONFIG_LCD_ST7567),y) + CSRCS += st7567.c +endif + +ifeq ($(CONFIG_LCD_SHARP_MEMLCD),y) + CSRCS += memlcd.c +endif + +ifeq ($(CONFIG_LCD_ILI9225),y) + CSRCS += ili9225.c +endif + +ifeq ($(CONFIG_LCD_ILI9340),y) + CSRCS += ili9340.c +endif + +ifeq ($(CONFIG_LCD_ILI9341),y) + CSRCS += ili9341.c +endif + +ifeq ($(CONFIG_LCD_LT768),y) + CSRCS += lt768.c lt768_lib.c +endif + +ifeq ($(CONFIG_LCD_LCDDRV_SPIIF),y) + CSRCS += lcddrv_spiif.c +endif + +ifeq ($(CONFIG_LCD_RA8875),y) + CSRCS += ra8875.c +endif + +ifeq ($(CONFIG_LCD_ST7735),y) + CSRCS += st7735.c +endif + +ifeq ($(CONFIG_LCD_ST7789),y) + CSRCS += st7789.c +endif + +ifeq ($(CONFIG_LCD_GC9A01),y) + CSRCS += gc9a01.c +endif + +endif # CONFIG_LCD + +ifeq ($(CONFIG_SLCD),y) + +# Include support for Alphanumeric/Segment LCD drivers + +ifeq ($(CONFIG_LCD_BACKPACK),y) + CSRCS += pcf8574_lcd_backpack.c +endif + +ifeq ($(CONFIG_LCD_ST7032),y) + CSRCS += st7032.c +endif + +ifeq ($(CONFIG_LCD_HT16K33),y) + CSRCS += ht16k33_14seg.c +endif +endif # CONFIG_SLCD + +# Other LCD-related devices + +ifeq ($(CONFIG_LCD_TDA19988),y) + CSRCS += tda19988.c +endif + +# Include LCD driver build support (the nested if-then-else implements an OR) + +ifeq ($(CONFIG_LCD),y) + DEPPATH += --dep-path lcd + VPATH += :lcd + CFLAGS += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)lcd} +else ifeq ($(CONFIG_SLCD),y) + DEPPATH += --dep-path lcd + VPATH += :lcd + CFLAGS += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)lcd} +else ifeq ($(CONFIG_LCD_OTHER),y) + DEPPATH += --dep-path lcd + VPATH += :lcd + CFLAGS += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)lcd} +endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/lt768.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/lt768.c new file mode 100755 index 000000000..2d5d1bfdc --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/drivers/lcd/lt768.c @@ -0,0 +1,6371 @@ +/********************* COPYRIGHT *********************** +* File Name : LT768.c +* Author : Levetop Electronics +* Version : V1.0 +* Date : 2017-8-25 +* Description : 操作LT768的寄存器函数 + 具体操作哪个寄存器请看LT768.h文件 +*********************************************************/ + +#include +#include "nuttx/arch.h" +#include "nuttx/lcd/lt768.h" +#include "nuttx/lcd/k210_lcd.h" + +//============================================================================== +void LCD_RegisterWrite(unsigned char Cmd,unsigned char Data) +{ + LCD_CmdWrite(Cmd); + LCD_DataWrite(Data); +} + +unsigned char LCD_RegisterRead(unsigned char Cmd) +{ + unsigned char temp; + LCD_CmdWrite(Cmd); + temp=LCD_DataRead(); + return temp; +} + +/******************************************************************************/ +/*Sub program area */ +/******************************************************************************/ +void Check_Mem_WR_FIFO_not_Full(void) +{ + /* 0: Memory Write FIFO is not full. + 1: Memory Write FIFO is full. */ + do + { + } + while(LCD_StatusRead()&0x80); +} +void Check_Mem_WR_FIFO_Empty(void) +{ + /* 0: Memory Write FIFO is not empty. + 1: Memory Write FIFO is empty. */ + do + { + } + while((LCD_StatusRead()&0x40) == 0x00); +} +void Check_Mem_RD_FIFO_not_Full(void) +{ + /* 0: Memory Read FIFO is not full. + 1: Memory Read FIFO is full. */ + do + { + } + while(LCD_StatusRead()&0x20); +} +void Check_Mem_RD_FIFO_not_Empty(void) +{ + /* 0: Memory Read FIFO is not empty. + 1: Memory Read FIFO is empty. + */ + do + { + } + while(LCD_StatusRead()&0x10); +} +void Check_2D_Busy(void) +{ + do + { + } + while(LCD_StatusRead()&0x08); +} +void Check_SDRAM_Ready(void) +{ + /* 0: SDRAM is not ready for access + 1: SDRAM is ready for access */ + unsigned char temp; + + do + { + temp=LCD_StatusRead(); + } + while((temp&0x04) == 0x00); +} + +unsigned char Power_Saving_Status(void) +{ + unsigned char temp; + + if((LCD_StatusRead()&0x02)==0x02) + { + temp = 1; + } + else + { + temp = 0; + } + + return temp; +} + +void Check_Power_is_Normal(void) +{ + /* 0: Normal operation state + 1: Power saving state */ + do + { + } + while(LCD_StatusRead()&0x02); +} +void Check_Power_is_Saving(void) +{ + /* 0: Normal operation state + 1: Power saving state */ + do + { + } + while((LCD_StatusRead()&0x02) == 0x00); +} +void Check_NO_Interrupt(void) +{ + /* 0: without interrupt event + 1: interrupt event occur + */ + do + { + } + while(LCD_StatusRead()&0x01); +} +void Check_Interrupt_Occur(void) +{ + /* 0: without interrupt event + 1: interrupt event occur + */ + do + { + } + while((LCD_StatusRead()&0x01) == 0x00); +} + +void Check_Busy_Draw(void) +{ + unsigned char temp; + + do + { + temp=LCD_StatusRead(); + } + while(temp&0x08); +} + +//[00h]========================================================================= + +void LT768_SW_Reset(void)//IC Reset +{ + unsigned char temp; + LCD_CmdWrite(0x00); + temp = LCD_DataRead(); + temp |= 0x01; + LCD_DataWrite(temp); + + do + { + temp = LCD_DataRead(); + } + while(temp&0x01); +} + +//[01h][01h][01h][01h][01h][01h][01h][01h][01h][01h][01h][01h][01h][01h][01h][01h] +void Enable_PLL(void) +{ + /* 0: PLL disable; allow change PLL parameter. + 1: PLL enable; cannot change PLL parameter.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); + up_udelay(1);//PLL +} +void LT768_Sleep(void) +{ + /* 0: Normal mode. + 1: Sleep mode.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void LT768_WakeUp(void) +{ + /* 0: Normal mode. + 1: Sleep mode.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Key_Scan_Enable(void) +{ + /* 0: Disable. + 1: Enable.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Key_Scan_Disable(void) +{ + /* 0: Disable. + 1: Enable.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void TFT_24bit(void) +{ + /* 00b: 24-bits output. + 01b: 18-bits output, unused pins are set as GPIO. + 10b: 16-bits output, unused pins are set as GPIO. + 11b: LVDS, all 24-bits unused output pins are set as GPIO.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb4; + temp &= cClrb3; + LCD_DataWrite(temp); +} +void TFT_18bit(void) +{ + /* 00b: 24-bits output. + 01b: 18-bits output, unused pins are set as GPIO. + 10b: 16-bits output, unused pins are set as GPIO. + 11b: LVDS, all 24-bits unused output pins are set as GPIO.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb4; + temp |= cSetb3; + LCD_DataWrite(temp); +} +void TFT_16bit(void) +{ + /* 00b: 24-bits output. + 01b: 18-bits output, unused pins are set as GPIO. + 10b: 16-bits output, unused pins are set as GPIO. + 11b: LVDS, all 24-bits unused output pins are set as GPIO.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb4; + temp &= cClrb3; + LCD_DataWrite(temp); +} +void TFT_LVDS(void) +{ + /* 00b: 24-bits output. + 01b: 18-bits output, unused pins are set as GPIO. + 10b: 16-bits output, unused pins are set as GPIO. + 11b: LVDS, all 24-bits unused output pins are set as GPIO.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb4; + temp |= cSetb3; + LCD_DataWrite(temp); +} + +void LT768_I2CM_Enable(void) +{ + /* I2C master Interface Enable/Disable + 0: Disable + 1: Enable*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} + +void LT768_I2CM_Disable(void) +{ + /* I2C master Interface Enable/Disable + 0: Disable + 1: Enable*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} + +void Enable_SFlash_SPI(void) +{ + /* Serial Flash SPI Interface Enable/Disable + 0: Disable + 1: Enable*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} + +void Disable_SFlash_SPI(void) +{ + /* Serial Flash SPI Interface Enable/Disable + 0: Disable + 1: Enable*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Host_Bus_8bit(void) +{ + /* Parallel Host Data Bus Width Selection + 0: 8-bit Parallel Host Data Bus. + 1: 16-bit Parallel Host Data Bus.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Host_Bus_16bit(void) +{ + /* Parallel Host Data Bus Width Selection + 0: 8-bit Parallel Host Data Bus. + 1: 16-bit Parallel Host Data Bus.*/ + unsigned char temp; + LCD_CmdWrite(0x01); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} + +//[02h][02h][02h][02h][02h][02h][02h][02h][02h][02h][02h][02h][02h][02h][02h][02h] + +void RGB_8b_8bpp(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void RGB_8b_16bpp(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb7; + temp |= cSetb6; + LCD_DataWrite(temp); +} +void RGB_8b_24bpp(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} + +void RGB_16b_8bpp(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp |= cSetb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void RGB_16b_16bpp(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb7; + temp |= cSetb6; + LCD_DataWrite(temp); +} +void RGB_16b_24bpp_mode1(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void RGB_16b_24bpp_mode2(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp |= cSetb7; + temp |= cSetb6; + LCD_DataWrite(temp); +} + +void MemRead_Left_Right_Top_Down(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void MemRead_Right_Left_Top_Down(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +void MemRead_Top_Down_Left_Right(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp |= cSetb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void MemRead_Down_Top_Left_Right(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp |= cSetb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +void MemWrite_Left_Right_Top_Down(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb2; + temp &= cClrb1; + LCD_DataWrite(temp); +} +void MemWrite_Right_Left_Top_Down(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp &= cClrb2; + temp |= cSetb1; + LCD_DataWrite(temp); +} +void MemWrite_Top_Down_Left_Right(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp |= cSetb2; + temp &= cClrb1; + LCD_DataWrite(temp); +} +void MemWrite_Down_Top_Left_Right(void) +{ + unsigned char temp; + LCD_CmdWrite(0x02); + temp = LCD_DataRead(); + temp |= cSetb2; + temp |= cSetb1; + LCD_DataWrite(temp); +} +//[03h][03h][03h][03h][03h][03h][03h][03h][03h][03h][03h][03h][03h][03h][03h][03h] +void Interrupt_Active_Low(void) +{ + /* MPU Interrupt active level + 0 : active low. + 1 : active high.*/ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void Interrupt_Active_High(void) +{ + /* MPU Interrupt active level + 0 : active low. + 1 : active high.*/ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void ExtInterrupt_Debounce(void) +{ + /* External interrupt de-bounce + 0 : without de-bounce + 1 : enable de-bounce (1024 OSC clock)*/ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void ExtInterrupt_Nodebounce(void) +{ + /* External interrupt de-bounce + 0 : without de-bounce + 1 : enable de-bounce (1024 OSC clock)*/ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void ExtInterrupt_Input_Low_Level_Trigger(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void ExtInterrupt_Input_High_Level_Trigger(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void ExtInterrupt_Input_Falling_Edge_Trigger(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +void ExtInterrupt_Input_Rising_Edge_Trigger(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +void LVDS_Format1(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void LVDS_Format2(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Graphic_Mode(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Text_Mode(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Memory_Select_SDRAM(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp &= cClrb1; + temp &= cClrb0; // B + LCD_DataWrite(temp); +} +void Memory_Select_Graphic_Cursor_RAM(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Memory_Select_Color_Palette_RAM(void) +{ + unsigned char temp; + LCD_CmdWrite(0x03); + temp = LCD_DataRead(); + temp |= cSetb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} + +//[05h]========================================================================= +//[06h]========================================================================= +//[07h]========================================================================= +//[08h]========================================================================= +//[09h]========================================================================= +//[0Ah]========================================================================= +//[0Bh]========================================================================= + +void Enable_Resume_Interrupt(void) +{ + /* + Resume Interrupt Enable + 0: Disable. + 1: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Disable_Resume_Interrupt(void) +{ + /* + Resume Interrupt Enable + 0: Disable. + 1: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void Enable_ExtInterrupt_Input(void) +{ + /* + External Interrupt (PS[0] pin) Enable + 0: Disable. + 1: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Disable_ExtInterrupt_Input(void) +{ + /* + External Interrupt (PS[0] pin) Enable + 0: Disable. + 1: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Enable_I2CM_Interrupt(void) +{ + /* + I2C Master Interrupt Enable + 0: Disable. + 1: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Disable_I2CM_Interrupt(void) +{ + /* + I2C Master Interrupt Enable + 0: Disable. + 1: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void Enable_Vsync_Interrupt(void) +{ + /* + Vsync time base interrupt Enable Bit + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Disable_Vsync_Interrupt(void) +{ + /* + Vsync time base interrupt Enable Bit + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Enable_KeyScan_Interrupt(void) +{ + /* + Key Scan Interrupt Enable Bit + 0: Disable Key scan interrupt. + 1: Enable Key scan interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Disable_KeyScan_Interrupt(void) +{ + /* + Key Scan Interrupt Enable Bit + 0: Disable Key scan interrupt. + 1: Enable Key scan interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Enable_DMA_Draw_BTE_Interrupt(void) +{ + /* + Serial flash DMA Complete | Draw task finished | BTE Process + Complete etc. Interrupt Enable + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Disable_DMA_Draw_BTE_Interrupt(void) +{ + /* + Serial flash DMA Complete | Draw task finished | BTE Process + Complete etc. Interrupt Enable + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Enable_PWM1_Interrupt(void) +{ + /* + PWM timer 1 Interrupt Enable Bit + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Disable_PWM1_Interrupt(void) +{ + /* + PWM timer 1 Interrupt Enable Bit + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Enable_PWM0_Interrupt(void) +{ + /* + PWM timer 0 Interrupt Enable Bit + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Disable_PWM0_Interrupt(void) +{ + /* + PWM timer 0 Interrupt Enable Bit + 0: Disable Interrupt. + 1: Enable Interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0B); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} + +//[0Ch]========================================================================= +unsigned char Read_Interrupt_status(void) +{ + /* + [Bit7]Read Function ..Resume Interrupt Status + 0: No Resume interrupt happens. + 1: Resume interrupt happens. + [Bit6]Read Function .. PS[0] pin Interrupt Status + 0: No PS[0] pin interrupt happens. + 1: PS[0] pin interrupt happens. + [Bit5]Read Function .. I2C master Interrupt Status + 0: No I2C master interrupt happens. + 1: I2C master interrupt happens. + [Bit4]Read Function .. Vsync Interrupt Status + 0: No interrupt happens. + 1: interrupt happens. + [Bit3]Read Function ..Key Scan Interrupt Status + 0: No Key Scan interrupt happens. + 1: Key Scan interrupt happens. + [Bit2]Read Function..Interrupt Status + 0: No interrupt happens. + 1: interrupt happens. + [Bit1]Read Function..Interrupt Status + 0: No interrupt happens. + 1: interrupt happens. + [Bit0]Read Function..Interrupt Status + 0: No interrupt happens. + 1: interrupt happens. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + return temp; +} +void Clear_Resume_Interrupt_Flag(void) +{ + /* + Resume Interrupt flag + Write Function .. Resume Interrupt Clear Bit + 0: No operation. + 1: Clear Resume interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Clear_ExtInterrupt_Input_Flag(void) +{ + /* + External Interrupt (PS[0] pin) flag + Write Function .. PS[0] pin edge Interrupt Clear Bit + 0: No operation. + 1: Clear the PS[0] pin edge interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Clear_I2CM_Interrupt_Flag(void) +{ + /* + I2C master Interrupt flag + Write Function.. I2C master Interrupt Clear Bit + 0: No operation. + 1: Clear the I2C master interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Clear_Vsync_Interrupt_Flag(void) +{ + /* + Vsync Time base interrupt flag + Write Function ..Vsync Interrupt Clear Bit + 0: No operation. + 1: Clear the interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Clear_KeyScan_Interrupt_Flag(void) +{ + /* + Key Scan Interrupt flag + Write Function..Key Scan Interrupt Clear Bit + 0: No operation. + 1: Clear the Key Scan interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Clear_DMA_Draw_BTE_Interrupt_Flag(void) +{ + /* + Serial flash DMA Complete | Draw task finished | BTE + Process Complete etc. Interrupt flag + Write Function.. Interrupt Clear Bit + 0: No operation. + 1: Clear interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Clear_PWM1_Interrupt_Flag(void) +{ + /* + PWM 1 timer Interrupt flag + Write Function..Interrupt Clear Bit + 0: No operation. + 1: Clear interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Clear_PWM0_Interrupt_Flag(void) +{ + /* + PWM 0 timer Interrupt flag + Write Function..Interrupt Clear Bit + 0: No operation. + 1: Clear interrupt. + */ + unsigned char temp; + LCD_CmdWrite(0x0C); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} +//[0Dh]========================================================================= +void Mask_Resume_Interrupt_Flag(void) +{ + /* + Mask Resume Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Mask_ExtInterrupt_Input_Flag(void) +{ + /* + Mask External Interrupt (PS[0] pin) Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Mask_I2CM_Interrupt_Flag(void) +{ + /* + Mask I2C Master Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Mask_Vsync_Interrupt_Flag(void) +{ + /* + Mask Vsync time base interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Mask_KeyScan_Interrupt_Flag(void) +{ + /* + Mask Key Scan Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Mask_DMA_Draw_BTE_Interrupt_Flag(void) +{ + /* + Mask Serial flash DMA Complete | Draw task finished | BTE + Process Complete etc. Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Mask_PWM1_Interrupt_Flag(void) +{ + /* + Mask PWM timer 1 Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Mask_PWM0_Interrupt_Flag(void) +{ + /* + Mask PWM timer 0 Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} + +void Enable_Resume_Interrupt_Flag(void) +{ + /* + Mask Resume Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void Enable_ExtInterrupt_Inpur_Flag(void) +{ + /* + Mask External Interrupt (PS[0] pin) Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Enable_I2CM_Interrupt_Flag(void) +{ + /* + Mask I2C Master Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void Enable_Vsync_Interrupt_Flag(void) +{ + /* + Mask Vsync time base interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Enable_KeyScan_Interrupt_Flag(void) +{ + /* + Mask Key Scan Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Enable_DMA_Draw_BTE_Interrupt_Flag(void) +{ + /* + Mask Serial flash DMA Complete | Draw task finished | BTE + Process Complete etc. Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Enable_PWM1_Interrupt_Flag(void) +{ + /* + Mask PWM timer 1 Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Enable_PWM0_Interrupt_Flag(void) +{ + /* + Mask PWM timer 0 Interrupt Flag + 0: Enable. + 1: Mask. + */ + unsigned char temp; + LCD_CmdWrite(0x0D); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} + +//[0Eh]========================================================================= +void Enable_GPIOF_PullUp(void) +{ + /* + GPIO_F[7:0] Pull-Up Enable (XPDAT[23:19, 15:13]) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Enable_GPIOE_PullUp(void) +{ + /* + GPIO_E[7:0] Pull-Up Enable (XPDAT[12:10, 7:3]) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Enable_GPIOD_PullUp(void) +{ + /* + GPIO_D[7:0] Pull-Up Enable (XPDAT[18, 2, 17, 16, 9, 8, 1,0]) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Enable_GPIOC_PullUp(void) +{ + /* + GPIO_C[6:0] Pull-Up Enable (XSDA, XSCL, XnSFCS1, + XnSFCS0, XMISO, XMOSI , XSCK) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Enable_XDB15_8_PullUp(void) +{ + /* + XDB[15:8] Pull-Up Enable + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Enable_XDB7_0_PullUp(void) +{ + /* + XDB[7:0] Pull-Up Enable + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Disable_GPIOF_PullUp(void) +{ + /* + GPIO_F[7:0] Pull-Up Enable (XPDAT[23:19, 15:13]) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void Disable_GPIOE_PullUp(void) +{ + /* + GPIO_E[7:0] Pull-Up Enable (XPDAT[12:10, 7:3]) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Disable_GPIOD_PullUp(void) +{ + /* + GPIO_D[7:0] Pull-Up Enable (XPDAT[18, 2, 17, 16, 9, 8, 1,0]) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Disable_GPIOC_PullUp(void) +{ + /* + GPIO_C[6:0] Pull-Up Enable (XSDA, XSCL, XnSFCS1, + XnSFCS0, XMISO, XMOSI , XSCK) + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Disable_XDB15_8_PullUp(void) +{ + /* + XDB[15:8] Pull-Up Enable + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Disable_XDB7_0_PullUp(void) +{ + /* + XDB[7:0] Pull-Up Enable + 0: Pull-Up Disable + 1: Pull-Up Enable + */ + unsigned char temp; + LCD_CmdWrite(0x0E); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} +//[0Fh]========================================================================= +void XPDAT18_Set_GPIO_D7(void) +{ + /* + XPDAT[18]  not scan function select + 0: GPIO-D7 + 1: KOUT[4] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void XPDAT18_Set_KOUT4(void) +{ + /* + XPDAT[18]  not scan function select + 0: GPIO-D7 + 1: KOUT[4] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void XPDAT17_Set_GPIO_D5(void) +{ + /* + XPDAT[17]  not scan function select + 0: GPIO-D5 + 1: KOUT[2] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void XPDAT17_Set_KOUT2(void) +{ + /* + XPDAT[17]  not scan function select + 0: GPIO-D5 + 1: KOUT[2] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void XPDAT16_Set_GPIO_D4(void) +{ + /* + XPDAT[16]  not scan function select + 0: GPIO-D4 + 1: KOUT[1] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void XPDAT16_Set_KOUT1(void) +{ + /* + XPDAT[16]  not scan function select + 0: GPIO-D4 + 1: KOUT[1] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void XPDAT9_Set_GPIO_D3(void) +{ + /* + XPDAT[9]  not scan function select + 0: GPIO-D3 + 1: KOUT[3] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void XPDAT9_Set_KOUT3(void) +{ + /* + XPDAT[9]  not scan function select + 0: GPIO-D3 + 1: KOUT[3] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void XPDAT8_Set_GPIO_D2(void) +{ + /* + XPDAT[8]  not scan function select + 0: GPIO-D2 + 1: KIN[3] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void XPDAT8_Set_KIN3(void) +{ + /* + XPDAT[8]  not scan function select + 0: GPIO-D2 + 1: KIN[3] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void XPDAT2_Set_GPIO_D6(void) +{ + /* + XPDAT[2]  not scan function select + 0: GPIO-D6 + 1: KIN[4] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void XPDAT2_Set_KIN4(void) +{ + /* + XPDAT[2]  not scan function select + 0: GPIO-D6 + 1: KIN[4] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void XPDAT1_Set_GPIO_D1(void) +{ + /* + XPDAT[1]  not scan function select + 0: GPIO-D1 + 1: KIN[2] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void XPDAT1_Set_KIN2(void) +{ + /* + XPDAT[1]  not scan function select + 0: GPIO-D1 + 1: KIN[2] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void XPDAT0_Set_GPIO_D0(void) +{ + /* + XPDAT[0]  not scan function select + 0: GPIO-D0 + 1: KIN[1] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} +void XPDAT0_Set_KIN1(void) +{ + /* + XPDAT[0]  not scan function select + 0: GPIO-D0 + 1: KIN[1] + */ + unsigned char temp; + LCD_CmdWrite(0x0F); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} + +//[10h]========================================================================= +void Enable_PIP1(void) +{ + /* + PIP 1 window Enable/Disable + 0 : PIP 1 window disable. + 1 : PIP 1 window enable + PIP 1 window always on top of PIP 2 window. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Disable_PIP1(void) +{ + /* + PIP 1 window Enable/Disable + 0 : PIP 1 window disable. + 1 : PIP 1 window enable + PIP 1 window always on top of PIP 2 window. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void Enable_PIP2(void) +{ + /* + PIP 2 window Enable/Disable + 0 : PIP 2 window disable. + 1 : PIP 2 window enable + PIP 1 window always on top of PIP 2 window. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Disable_PIP2(void) +{ + /* + PIP 2 window Enable/Disable + 0 : PIP 2 window disable. + 1 : PIP 2 window enable + PIP 1 window always on top of PIP 2 window. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Select_PIP1_Parameter(void) +{ + /* + 0: To configure PIP 1ˇs parameters. + 1: To configure PIP 2ˇs parameters.. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Select_PIP2_Parameter(void) +{ + /* + 0: To configure PIP 1ˇs parameters. + 1: To configure PIP 2ˇs parameters.. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Select_Main_Window_8bpp(void) +{ + /* + Main Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp &= cClrb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Select_Main_Window_16bpp(void) +{ + /* + Main Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp &= cClrb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Select_Main_Window_24bpp(void) +{ + /* + Main Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x10); + temp = LCD_DataRead(); + temp |= cSetb3; + //temp |= cSetb2; + LCD_DataWrite(temp); +} +//[11h]========================================================================= +void Select_PIP2_Window_8bpp(void) +{ + /* + PIP 1 Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x11); + temp = LCD_DataRead(); + temp &= cClrb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Select_PIP2_Window_16bpp(void) +{ + /* + PIP 1 Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x11); + temp = LCD_DataRead(); + temp &= cClrb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Select_PIP2_Window_24bpp(void) +{ + /* + PIP 1 Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x11); + temp = LCD_DataRead(); + temp |= cSetb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Select_PIP1_Window_8bpp(void) +{ + /* + PIP 2 Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x11); + temp = LCD_DataRead(); + temp &= cClrb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Select_PIP1_Window_16bpp(void) +{ + /* + PIP 2 Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x11); + temp = LCD_DataRead(); + temp &= cClrb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Select_PIP1_Window_24bpp(void) +{ + /* + PIP 2 Window Color Depth Setting + 00b: 8-bpp generic TFT, i.e. 256 colors. + 01b: 16-bpp generic TFT, i.e. 65K colors. + 1xb: 24-bpp generic TFT, i.e. 1.67M colors. + */ + unsigned char temp; + LCD_CmdWrite(0x11); + temp = LCD_DataRead(); + temp |= cSetb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} + +//[12h]========================================================================= +void PCLK_Rising(void) +{ + /* + PCLK Inversion + 0: PDAT, DE, HSYNC etc. Drive(/ change) at PCLK falling edge. + 1: PDAT, DE, HSYNC etc. Drive(/ change) at PCLK rising edge. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void PCLK_Falling(void) +{ + /* + PCLK Inversion + 0: PDAT, DE, HSYNC etc. Drive(/ change) at PCLK falling edge. + 1: PDAT, DE, HSYNC etc. Drive(/ change) at PCLK rising edge. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Display_ON(void) +{ + /* + Display ON/OFF + 0b: Display Off. + 1b: Display On. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + syslog(LOG_NOTICE, "Display_ON.pre_read=%02x\n", temp); + temp |= cSetb6; + LCD_DataWrite(temp); + temp = LCD_DataRead(); + syslog(LOG_NOTICE, "Display_ON.write_read=%02x\n", temp); +} + +void Display_OFF(void) +{ + /* + Display ON/OFF + 0b: Display Off. + 1b: Display On. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Color_Bar_ON(void) +{ + /* + Display Test Color Bar + 0b: Disable. + 1b: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Color_Bar_OFF(void) +{ + /* + Display Test Color Bar + 0b: Disable. + 1b: Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void HSCAN_L_to_R(void) +{ + /* + Horizontal Scan Direction + 0 : From Left to Right + 1 : From Right to Left + PIP window will be disabled when HDIR set as 1. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void HSCAN_R_to_L(void) +{ + /* + Horizontal Scan Direction + 0 : From Left to Right + 1 : From Right to Left + PIP window will be disabled when HDIR set as 1. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void VSCAN_T_to_B(void) +{ + /* + Vertical Scan direction + 0 : From Top to Bottom + 1 : From bottom to Top + PIP window will be disabled when VDIR set as 1. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void VSCAN_B_to_T(void) +{ + /* + Vertical Scan direction + 0 : From Top to Bottom + 1 : From bottom to Top + PIP window will be disabled when VDIR set as 1. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void PDATA_Set_RGB(void) +{ + /* + parallel PDATA[23:0] Output Sequence + 000b : RGB. + 001b : RBG. + 010b : GRB. + 011b : GBR. + 100b : BRG. + 101b : BGR. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &=0xf8; + LCD_DataWrite(temp); +} +void PDATA_Set_RBG(void) +{ + /* + parallel PDATA[23:0] Output Sequence + 000b : RGB. + 001b : RBG. + 010b : GRB. + 011b : GBR. + 100b : BRG. + 101b : BGR. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &=0xf8; + temp |= cSetb0; + LCD_DataWrite(temp); +} +void PDATA_Set_GRB(void) +{ + /* + parallel PDATA[23:0] Output Sequence + 000b : RGB. + 001b : RBG. + 010b : GRB. + 011b : GBR. + 100b : BRG. + 101b : BGR. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &=0xf8; + temp |= cSetb1; + LCD_DataWrite(temp); +} +void PDATA_Set_GBR(void) +{ + /* + parallel PDATA[23:0] Output Sequence + 000b : RGB. + 001b : RBG. + 010b : GRB. + 011b : GBR. + 100b : BRG. + 101b : BGR. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &=0xf8; + temp |= cSetb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +void PDATA_Set_BRG(void) +{ + /* + parallel PDATA[23:0] Output Sequence + 000b : RGB. + 001b : RBG. + 010b : GRB. + 011b : GBR. + 100b : BRG. + 101b : BGR. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &=0xf8; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void PDATA_Set_BGR(void) +{ + /* + parallel PDATA[23:0] Output Sequence + 000b : RGB. + 001b : RBG. + 010b : GRB. + 011b : GBR. + 100b : BRG. + 101b : BGR. + */ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp &=0xf8; + temp |= cSetb2; + temp |= cSetb0; + LCD_DataWrite(temp); +} + +void PDATA_IDLE_STATE(void) +{ + unsigned char temp; + LCD_CmdWrite(0x12); + temp = LCD_DataRead(); + temp |=0x07; + LCD_DataWrite(temp); +} + + +//[13h]========================================================================= +void HSYNC_Low_Active(void) +{ + /* + HSYNC Polarity + 0 : Low active. + 1 : High active. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void HSYNC_High_Active(void) +{ + /* + HSYNC Polarity + 0 : Low active. + 1 : High active. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void VSYNC_Low_Active(void) +{ + /* + VSYNC Polarity + 0 : Low active. + 1 : High active. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void VSYNC_High_Active(void) +{ + /* + VSYNC Polarity + 0 : Low active. + 1 : High active. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void DE_Low_Active(void) +{ + /* + DE Polarity + 0 : High active. + 1 : Low active. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void DE_High_Active(void) +{ + /* + DE Polarity + 0 : High active. + 1 : Low active. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void Idle_DE_Low(void) +{ + /* + DE IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨DE〃 output is low. + 1 : Pin ¨DE〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Idle_DE_High(void) +{ + /* + DE IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨DE〃 output is low. + 1 : Pin ¨DE〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Idle_PCLK_Low(void) +{ + /* + PCLK IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨PCLK〃 output is low. + 1 : Pin ¨PCLK〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Idle_PCLK_High(void) +{ + /* + PCLK IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨PCLK〃 output is low. + 1 : Pin ¨PCLK〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Idle_PDAT_Low(void) +{ + /* + PDAT IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pins ¨PDAT[23:0]〃 output is low. + 1 : Pins ¨PCLK[23:0]〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Idle_PDAT_High(void) +{ + /* + PDAT IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pins ¨PDAT[23:0]〃 output is low. + 1 : Pins ¨PCLK[23:0]〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Idle_HSYNC_Low(void) +{ + /* + HSYNC IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨HSYNC〃 output is low. + 1 : Pin ¨HSYNC〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Idle_HSYNC_High(void) +{ + /* + HSYNC IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨HSYNC〃 output is low. + 1 : Pin ¨HSYNC〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Idle_VSYNC_Low(void) +{ + /* + VSYNC IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨VSYNC〃 output is low. + 1 : Pin ¨VSYNC〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Idle_VSYNC_High(void) +{ + /* + VSYNC IDLE STATE(When STANDBY or DISPLAY OFF ) + 0 : Pin ¨VSYNC〃 output is low. + 1 : Pin ¨VSYNC〃 output is high. + */ + unsigned char temp; + LCD_CmdWrite(0x13); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} + +//[14h][15h][1Ah][1Bh]========================================================================= + +void LCD_HorizontalWidth_VerticalHeight(unsigned short WX,unsigned short HY) +{ + /* + [14h] Horizontal Display Width Setting Bit[7:0] + [15h] Horizontal Display Width Fine Tuning (HDWFT) [3:0] + The register specifies the LCD panel horizontal display width in + the unit of 8 pixels resolution. + Horizontal display width(pixels) = (HDWR + 1) * 8 + HDWFTR + + [1Ah] Vertical Display Height Bit[7:0] + Vertical Display Height(Line) = VDHR + 1 + [1Bh] Vertical Display Height Bit[10:8] + Vertical Display Height(Line) = VDHR + 1 + */ + unsigned char temp; + + if(WX<8) + { + LCD_CmdWrite(0x14); + LCD_DataWrite(0x00); + LCD_CmdWrite(0x15); + LCD_DataWrite(WX); + temp=HY-1; + LCD_CmdWrite(0x1A); + LCD_DataWrite(temp); + temp=(HY-1)>>8; + LCD_CmdWrite(0x1B); + LCD_DataWrite(temp); + } + else + { + temp=(WX/8)-1; + LCD_CmdWrite(0x14); + LCD_DataWrite(temp); + temp=WX%8; + LCD_CmdWrite(0x15); + LCD_DataWrite(temp); + temp=HY-1; + LCD_CmdWrite(0x1A); + LCD_DataWrite(temp); + temp=(HY-1)>>8; + LCD_CmdWrite(0x1B); + LCD_DataWrite(temp); + } +} +//[16h][17h]========================================================================= +void LCD_Horizontal_Non_Display(unsigned short WX) +{ + /* + [16h] Horizontal Non-Display Period(HNDR) Bit[4:0] + This register specifies the horizontal non-display period. Also + called back porch. + Horizontal non-display period(pixels) = (HNDR + 1) * 8 + HNDFTR + + [17h] Horizontal Non-Display Period Fine Tuning(HNDFT) [3:0] + This register specifies the fine tuning for horizontal non-display + period; it is used to support the SYNC mode panel. Each level of + this modulation is 1-pixel. + Horizontal non-display period(pixels) = (HNDR + 1) * 8 + HNDFTR + */ + unsigned char temp; + + if(WX<8) + { + LCD_CmdWrite(0x16); + LCD_DataWrite(0x00); + LCD_CmdWrite(0x17); + LCD_DataWrite(WX); + } + else + { + temp=(WX/8)-1; + LCD_CmdWrite(0x16); + LCD_DataWrite(temp); + temp=WX%8; + LCD_CmdWrite(0x17); + LCD_DataWrite(temp); + } +} +//[18h]========================================================================= +void LCD_HSYNC_Start_Position(unsigned short WX) +{ + /* + [18h] HSYNC Start Position[4:0] + The starting position from the end of display area to the + beginning of HSYNC. Each level of this modulation is 8-pixel. + Also called front porch. + HSYNC Start Position(pixels) = (HSTR + 1)x8 + */ + unsigned char temp; + + if(WX<8) + { + LCD_CmdWrite(0x18); + LCD_DataWrite(0x00); + } + else + { + temp=(WX/8)-1; + LCD_CmdWrite(0x18); + LCD_DataWrite(temp); + } +} +//[19h]========================================================================= +void LCD_HSYNC_Pulse_Width(unsigned short WX) +{ + /* + [19h] HSYNC Pulse Width(HPW) [4:0] + The period width of HSYNC. + HSYNC Pulse Width(pixels) = (HPW + 1)x8 + */ + unsigned char temp; + + if(WX<8) + { + LCD_CmdWrite(0x19); + LCD_DataWrite(0x00); + } + else + { + temp=(WX/8)-1; + LCD_CmdWrite(0x19); + LCD_DataWrite(temp); + } +} +//[1Ch][1Dh]========================================================================= +void LCD_Vertical_Non_Display(unsigned short HY) +{ + /* + [1Ch] Vertical Non-Display Period Bit[7:0] + Vertical Non-Display Period(Line) = (VNDR + 1) + + [1Dh] Vertical Non-Display Period Bit[9:8] + Vertical Non-Display Period(Line) = (VNDR + 1) + */ + unsigned char temp; + temp=HY-1; + LCD_CmdWrite(0x1C); + LCD_DataWrite(temp); + LCD_CmdWrite(0x1D); + LCD_DataWrite(temp>>8); +} +//[1Eh]========================================================================= +void LCD_VSYNC_Start_Position(unsigned short HY) +{ + /* + [1Eh] VSYNC Start Position[7:0] + The starting position from the end of display area to the beginning of VSYNC. + VSYNC Start Position(Line) = (VSTR + 1) + */ + unsigned char temp; + temp=HY-1; + LCD_CmdWrite(0x1E); + LCD_DataWrite(temp); +} +//[1Fh]========================================================================= +void LCD_VSYNC_Pulse_Width(unsigned short HY) +{ + /* + [1Fh] VSYNC Pulse Width[5:0] + The pulse width of VSYNC in lines. + VSYNC Pulse Width(Line) = (VPWR + 1) + */ + unsigned char temp; + temp=HY-1; + LCD_CmdWrite(0x1F); + LCD_DataWrite(temp); +} +//[20h][21h][22h][23h]========================================================================= +void Main_Image_Start_Address(unsigned long Addr) +{ + /* + [20h] Main Image Start Address[7:2] + [21h] Main Image Start Address[15:8] + [22h] Main Image Start Address [23:16] + [23h] Main Image Start Address [31:24] + */ + LCD_RegisterWrite(0x20,Addr); + LCD_RegisterWrite(0x21,Addr>>8); + LCD_RegisterWrite(0x22,Addr>>16); + LCD_RegisterWrite(0x23,Addr>>24); +} +//[24h][25h]========================================================================= +void Main_Image_Width(unsigned short WX) +{ + /* + [24h] Main Image Width [7:0] + [25h] Main Image Width [12:8] + Unit: Pixel. + It must be divisible by 4. MIW Bit [1:0] tie to ¨0〃 internally. + The value is physical pixel number. Maximum value is 8188 pixels + */ + LCD_RegisterWrite(0x24,WX); + LCD_RegisterWrite(0x25,WX>>8); +} +//[26h][27h][28h][29h]========================================================================= +void Main_Window_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [26h] Main Window Upper-Left corner X-coordination [7:0] + [27h] Main Window Upper-Left corner X-coordination [12:8] + Reference Main Image coordination. + Unit: Pixel + It must be divisible by 4. MWULX Bit [1:0] tie to ¨0〃 internally. + X-axis coordination plus Horizontal display width cannot large than 8188. + + [28h] Main Window Upper-Left corner Y-coordination [7:0] + [29h] Main Window Upper-Left corner Y-coordination [12:8] + Reference Main Image coordination. + Unit: Pixel + Range is between 0 and 8191. + */ + LCD_RegisterWrite(0x26,WX); + LCD_RegisterWrite(0x27,WX>>8); + LCD_RegisterWrite(0x28,HY); + LCD_RegisterWrite(0x29,HY>>8); +} +//[2Ah][2Bh][2Ch][2Dh]========================================================================= +void PIP_Display_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [2Ah] PIP Window Display Upper-Left corner X-coordination [7:0] + [2Bh] PIP Window Display Upper-Left corner X-coordination [12:8] + Reference Main Window coordination. + Unit: Pixel + It must be divisible by 4. PWDULX Bit [1:0] tie to ¨0〃 internally. + X-axis coordination should less than horizontal display width. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + + [2Ch] PIP Window Display Upper-Left corner Y-coordination [7:0] + [2Dh] PIP Window Display Upper-Left corner Y-coordination [12:8] + Reference Main Window coordination. + Unit: Pixel + Y-axis coordination should less than vertical display height. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + */ + LCD_RegisterWrite(0x2A,WX); + LCD_RegisterWrite(0x2B,WX>>8); + LCD_RegisterWrite(0x2C,HY); + LCD_RegisterWrite(0x2D,HY>>8); +} +//[2Eh][2Fh][30h][31h]========================================================================= +void PIP_Image_Start_Address(unsigned long Addr) +{ + /* + [2Eh] PIP Image Start Address[7:2] + [2Fh] PIP Image Start Address[15:8] + [30h] PIP Image Start Address [23:16] + [31h] PIP Image Start Address [31:24] + */ + LCD_RegisterWrite(0x2E,Addr); + LCD_RegisterWrite(0x2F,Addr>>8); + LCD_RegisterWrite(0x30,Addr>>16); + LCD_RegisterWrite(0x31,Addr>>24); +} +//[32h][33h]========================================================================= +void PIP_Image_Width(unsigned short WX) +{ + /* + [32h] PIP Image Width [7:0] + [33h] PIP Image Width [12:8] + Unit: Pixel. + It must be divisible by 4. PIW Bit [1:0] tie to ¨0〃 internally. + The value is physical pixel number. + This width should less than horizontal display width. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + */ + LCD_RegisterWrite(0x32,WX); + LCD_RegisterWrite(0x33,WX>>8); +} +//[34h][35h][36h][37h]========================================================================= +void PIP_Window_Image_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [34h] PIP 1 or 2 Window Image Upper-Left corner X-coordination [7:0] + [35h] PIP Window Image Upper-Left corner X-coordination [12:8] + Reference PIP Image coordination. + Unit: Pixel + It must be divisible by 4. PWIULX Bit [1:0] tie to ¨0〃 internally. + X-axis coordination plus PIP image width cannot large than 8188. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + + [36h] PIP Windows Display Upper-Left corner Y-coordination [7:0] + [37h] PIP Windows Image Upper-Left corner Y-coordination [12:8] + Reference PIP Image coordination. + Unit: Pixel + Y-axis coordination plus PIP window height should less than 8191. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + */ + LCD_RegisterWrite(0x34,WX); + LCD_RegisterWrite(0x35,WX>>8); + LCD_RegisterWrite(0x36,HY); + LCD_RegisterWrite(0x37,HY>>8); +} +//[38h][39h][3Ah][3Bh]========================================================================= +void PIP_Window_Width_Height(unsigned short WX,unsigned short HY) +{ + /* + [38h] PIP Window Width [7:0] + [39h] PIP Window Width [10:8] + Unit: Pixel. + It must be divisible by 4. The value is physical pixel number. + Maximum value is 8188 pixels. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + + [3Ah] PIP Window Height [7:0] + [3Bh] PIP Window Height [10:8] + Unit: Pixel + The value is physical pixel number. Maximum value is 8191 pixels. + According to bit of Select Configure PIP 1 or 2 Windowˇs parameters. + Function bit will be configured for relative PIP window. + */ + LCD_RegisterWrite(0x38,WX); + LCD_RegisterWrite(0x39,WX>>8); + LCD_RegisterWrite(0x3A,HY); + LCD_RegisterWrite(0x3B,HY>>8); +} + +//[3Ch]========================================================================= +void Enable_Graphic_Cursor(void) +{ + /* + Graphic Cursor Enable + 0 : Graphic Cursor disable. + 1 : Graphic Cursor enable. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Disable_Graphic_Cursor(void) +{ + /* + Graphic Cursor Enable + 0 : Graphic Cursor disable. + 1 : Graphic Cursor enable. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +// +void Select_Graphic_Cursor_1(void) +{ + /* + Graphic Cursor Selection Bit + Select one from four graphic cursor types. (00b to 11b) + 00b : Graphic Cursor Set 1. + 01b : Graphic Cursor Set 2. + 10b : Graphic Cursor Set 3. + 11b : Graphic Cursor Set 4. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp &= cClrb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Select_Graphic_Cursor_2(void) +{ + /* + Graphic Cursor Selection Bit + Select one from four graphic cursor types. (00b to 11b) + 00b : Graphic Cursor Set 1. + 01b : Graphic Cursor Set 2. + 10b : Graphic Cursor Set 3. + 11b : Graphic Cursor Set 4. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp &= cClrb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Select_Graphic_Cursor_3(void) +{ + /* + Graphic Cursor Selection Bit + Select one from four graphic cursor types. (00b to 11b) + 00b : Graphic Cursor Set 1. + 01b : Graphic Cursor Set 2. + 10b : Graphic Cursor Set 3. + 11b : Graphic Cursor Set 4. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp |= cSetb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Select_Graphic_Cursor_4(void) +{ + /* + Graphic Cursor Selection Bit + Select one from four graphic cursor types. (00b to 11b) + 00b : Graphic Cursor Set 1. + 01b : Graphic Cursor Set 2. + 10b : Graphic Cursor Set 3. + 11b : Graphic Cursor Set 4. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp |= cSetb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +// +void Enable_Text_Cursor(void) +{ + /* + Text Cursor Enable + 0 : Disable. + 1 : Enable. + Text cursor & Graphic cursor cannot enable simultaneously. + Graphic cursor has higher priority then Text cursor if enabled simultaneously. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Disable_Text_Cursor(void) +{ + /* + Text Cursor Enable + 0 : Disable. + 1 : Enable. + Text cursor & Graphic cursor cannot enable simultaneously. + Graphic cursor has higher priority then Text cursor if enabled simultaneously. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +// +void Enable_Text_Cursor_Blinking(void) +{ + /* + Text Cursor Blinking Enable + 0 : Disable. + 1 : Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Disable_Text_Cursor_Blinking(void) +{ + /* + Text Cursor Blinking Enable + 0 : Disable. + 1 : Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x3C); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} +//[3Dh]========================================================================= +void Blinking_Time_Frames(unsigned char temp) +{ + /* + Text Cursor Blink Time Setting (Unit: Frame) + 00h : 1 frame time. + 01h : 2 frames time. + 02h : 3 frames time. + : + FFh : 256 frames time. + */ + LCD_CmdWrite(0x3D); + LCD_DataWrite(temp); +} +//[3Eh]========================================================================= +void Text_Cursor_H_V(unsigned short WX,unsigned short HY) +{ + /* + [3Eh] + Text Cursor Horizontal Size Setting[4:0] + Unit : Pixel + Zero-based number. Value ¨0〃 means 1 pixel. + Note : When font is enlarged, the cursor setting will multiply the + same times as the font enlargement. + [3Fh] + Text Cursor Vertical Size Setting[4:0] + Unit : Pixel + Zero-based number. Value ¨0〃 means 1 pixel. + Note : When font is enlarged, the cursor setting will multiply the + same times as the font enlargement. + */ + LCD_CmdWrite(0x3E); + LCD_DataWrite(WX); + LCD_CmdWrite(0x3F); + LCD_DataWrite(HY); +} +//[40h][41h][42h][43h]========================================================================= +void Graphic_Cursor_XY(unsigned short WX,unsigned short HY) +{ + /* + [40h] Graphic Cursor Horizontal Location[7:0] + [41h] Graphic Cursor Horizontal Location[12:8] + [42h] Graphic Cursor Vertical Location[7:0] + [43h] Graphic Cursor Vertical Location[12:8] + Reference main Window coordination. + */ + LCD_RegisterWrite(0x40,WX); + LCD_RegisterWrite(0x41,WX>>8); + LCD_RegisterWrite(0x42,HY); + LCD_RegisterWrite(0x43,HY>>8); +} +//[44h]========================================================================= +void Set_Graphic_Cursor_Color_1(unsigned char temp) +{ + /* + [44h] Graphic Cursor Color 0 with 256 Colors + RGB Format [7:0] = RRRGGGBB. + */ + LCD_RegisterWrite(0x44,temp); +} +//[45h]========================================================================= +void Set_Graphic_Cursor_Color_2(unsigned char temp) +{ + /* + [45h] Graphic Cursor Color 1 with 256 Colors + RGB Format [7:0] = RRRGGGBB. + */ + LCD_RegisterWrite(0x45,temp); +} +//[50h][51h][52h][53h]========================================================================= +void Canvas_Image_Start_address(unsigned long Addr) +{ + /* + [50h] Start address of Canvas [7:0] + [51h] Start address of Canvas [15:8] + [52h] Start address of Canvas [23:16] + [53h] Start address of Canvas [31:24] + */ + LCD_RegisterWrite(0x50,Addr); + LCD_RegisterWrite(0x51,Addr>>8); + LCD_RegisterWrite(0x52,Addr>>16); + LCD_RegisterWrite(0x53,Addr>>24); +} +//[54h][55h]========================================================================= +void Canvas_image_width(unsigned short WX) +{ + /* + [54h] Canvas image width [7:2] + [55h] Canvas image width [12:8] + */ + LCD_RegisterWrite(0x54,WX); + LCD_RegisterWrite(0x55,WX>>8); +} +//[56h][57h][58h][59h]========================================================================= +void Active_Window_XY(unsigned short WX,unsigned short HY) +{ + /* + [56h] Active Window Upper-Left corner X-coordination [7:0] + [57h] Active Window Upper-Left corner X-coordination [12:8] + [58h] Active Window Upper-Left corner Y-coordination [7:0] + [59h] Active Window Upper-Left corner Y-coordination [12:8] + */ + LCD_RegisterWrite(0x56,WX); + LCD_RegisterWrite(0x57,WX>>8); + LCD_RegisterWrite(0x58,HY); + LCD_RegisterWrite(0x59,HY>>8); +} +//[5Ah][5Bh][5Ch][5Dh]========================================================================= +void Active_Window_WH(unsigned short WX,unsigned short HY) +{ + /* + [5Ah] Width of Active Window [7:0] + [5Bh] Width of Active Window [12:8] + [5Ch] Height of Active Window [7:0] + [5Dh] Height of Active Window [12:8] + */ + LCD_RegisterWrite(0x5A,WX); + LCD_RegisterWrite(0x5B,WX>>8); + LCD_RegisterWrite(0x5C,HY); + LCD_RegisterWrite(0x5D,HY>>8); +} +//[5Eh]========================================================================= +void Select_Write_Data_Position(void) +{ + /* + Select to read back Graphic Read/Write position + 0: read back Graphic Write position + 1: read back Graphic Read position + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Select_Read_Data_Position(void) +{ + /* + Select to read back Graphic Read/Write position + 0: read back Graphic Write position + 1: read back Graphic Read position + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Memory_XY_Mode(void) +{ + /* + Canvas addressing mode + 0: Block mode (X-Y coordination addressing) + 1: linear mode + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Memory_Linear_Mode(void) +{ + /* + Canvas addressing mode + 0: Block mode (X-Y coordination addressing) + 1: linear mode + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Memory_8bpp_Mode(void) +{ + /* + Canvas imageˇs color depth & memory R/W data width + In Block Mode: + 00: 8bpp + 01: 16bpp + 1x: 24bpp + In Linear Mode: + X0: 8-bits memory data read/write. + X1: 16-bits memory data read/write + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp &= cClrb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Memory_16bpp_Mode(void) +{ + /* + Canvas imageˇs color depth & memory R/W data width + In Block Mode: + 00: 8bpp + 01: 16bpp + 1x: 24bpp + In Linear Mode: + X0: 8-bits memory data read/write. + X1: 16-bits memory data read/write + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp &= cClrb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Memory_24bpp_Mode(void) +{ + /* + Canvas imageˇs color depth & memory R/W data width + In Block Mode: + 00: 8bpp + 01: 16bpp + 1x: 24bpp + In Linear Mode: + X0: 8-bits memory data read/write. + X1: 16-bits memory data read/write + */ + unsigned char temp; + LCD_CmdWrite(0x5E); + temp = LCD_DataRead(); + temp |= cSetb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} + +//[5Fh][60h][61h][62h]========================================================================= +void Goto_Pixel_XY(unsigned short WX,unsigned short HY) +{ + /* + [Write]: Set Graphic Read/Write position + [Read]: Current Graphic Read/Write position + Read back is Read position or Write position depends on + REG[5Eh] bit3, Select to read back Graphic Read/Write position. + When DPRAM Linear mode:Graphic Read/Write Position [31:24][23:16][15:8][7:0] + When DPRAM Active window mode:Graphic Read/Write + Horizontal Position [12:8][7:0], + Vertical Position [12:8][7:0]. + Reference Canvas image coordination. Unit: Pixel + */ + LCD_RegisterWrite(0x5F,WX); + LCD_RegisterWrite(0x60,WX>>8); + LCD_RegisterWrite(0x61,HY); + LCD_RegisterWrite(0x62,HY>>8); +} +void Goto_Linear_Addr(unsigned long Addr) +{ + LCD_RegisterWrite(0x5F,Addr); + LCD_RegisterWrite(0x60,Addr>>8); + LCD_RegisterWrite(0x61,Addr>>16); + LCD_RegisterWrite(0x62,Addr>>24); +} + + +//[63h][64h][65h][66h]========================================================================= +void Goto_Text_XY(unsigned short WX,unsigned short HY) +{ + /* + Write: Set Text Write position + Read: Current Text Write position + Text Write X-coordination [12:8][7:0] + Text Write Y-coordination [12:8][7:0] + Reference Canvas image coordination. + Unit: Pixel + */ + LCD_RegisterWrite(0x63,WX); + LCD_RegisterWrite(0x64,WX>>8); + LCD_RegisterWrite(0x65,HY); + LCD_RegisterWrite(0x66,HY>>8); +} +//[67h]========================================================================= +/* +[bit7]Draw Line / Triangle Start Signal +Write Function +0 : Stop the drawing function. +1 : Start the drawing function. +Read Function +0 : Drawing function complete. +1 : Drawing function is processing. +[bit5]Fill function for Triangle Signal +0 : Non fill. +1 : Fill. +[bit1]Draw Triangle or Line Select Signal +0 : Draw Line +1 : Draw Triangle +*/ +void Start_Line(void) +{ + LCD_CmdWrite(0x67); + LCD_DataWrite(0x80); + Check_Busy_Draw(); +} +void Start_Triangle(void) +{ + LCD_CmdWrite(0x67); + LCD_DataWrite(0x82);//B1000_0010 + Check_Busy_Draw(); +} +void Start_Triangle_Fill(void) +{ + LCD_CmdWrite(0x67); + LCD_DataWrite(0xA2);//B1010_0010 + Check_Busy_Draw(); +} +//[68h][69h][6Ah][6Bh]========================================================================= +//线起点 +void Line_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [68h] Draw Line/Square/Triangle Start X-coordination [7:0] + [69h] Draw Line/Square/Triangle Start X-coordination [12:8] + [6Ah] Draw Line/Square/Triangle Start Y-coordination [7:0] + [6Bh] Draw Line/Square/Triangle Start Y-coordination [12:8] + */ + LCD_CmdWrite(0x68); + LCD_DataWrite(WX); + LCD_CmdWrite(0x69); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x6A); + LCD_DataWrite(HY); + LCD_CmdWrite(0x6B); + LCD_DataWrite(HY>>8); +} +//[6Ch][6Dh][6Eh][6Fh]========================================================================= +//线终点 +void Line_End_XY(unsigned short WX,unsigned short HY) +{ + /* + [6Ch] Draw Line/Square/Triangle End X-coordination [7:0] + [6Dh] Draw Line/Square/Triangle End X-coordination [12:8] + [6Eh] Draw Line/Square/Triangle End Y-coordination [7:0] + [6Fh] Draw Line/Square/Triangle End Y-coordination [12:8] + */ + LCD_CmdWrite(0x6C); + LCD_DataWrite(WX); + LCD_CmdWrite(0x6D); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x6E); + LCD_DataWrite(HY); + LCD_CmdWrite(0x6F); + LCD_DataWrite(HY>>8); +} +//[68h]~[73h]========================================================================= +//à-翴1 +void Triangle_Point1_XY(unsigned short WX,unsigned short HY) +{ + /* + [68h] Draw Line/Square/Triangle Start X-coordination [7:0] + [69h] Draw Line/Square/Triangle Start X-coordination [12:8] + [6Ah] Draw Line/Square/Triangle Start Y-coordination [7:0] + [6Bh] Draw Line/Square/Triangle Start Y-coordination [12:8] + */ + LCD_CmdWrite(0x68); + LCD_DataWrite(WX); + LCD_CmdWrite(0x69); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x6A); + LCD_DataWrite(HY); + LCD_CmdWrite(0x6B); + LCD_DataWrite(HY>>8); +} +//à-翴2 +void Triangle_Point2_XY(unsigned short WX,unsigned short HY) +{ + /* + [6Ch] Draw Line/Square/Triangle End X-coordination [7:0] + [6Dh] Draw Line/Square/Triangle End X-coordination [12:8] + [6Eh] Draw Line/Square/Triangle End Y-coordination [7:0] + [6Fh] Draw Line/Square/Triangle End Y-coordination [12:8] + */ + LCD_CmdWrite(0x6C); + LCD_DataWrite(WX); + LCD_CmdWrite(0x6D); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x6E); + LCD_DataWrite(HY); + LCD_CmdWrite(0x6F); + LCD_DataWrite(HY>>8); +} +//à-翴3 +void Triangle_Point3_XY(unsigned short WX,unsigned short HY) +{ + /* + [70h] Draw Triangle Point 3 X-coordination [7:0] + [71h] Draw Triangle Point 3 X-coordination [12:8] + [72h] Draw Triangle Point 3 Y-coordination [7:0] + [73h] Draw Triangle Point 3 Y-coordination [12:8] + */ + LCD_CmdWrite(0x70); + LCD_DataWrite(WX); + LCD_CmdWrite(0x71); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x72); + LCD_DataWrite(HY); + LCD_CmdWrite(0x73); + LCD_DataWrite(HY>>8); +} +//よ癬翴 +void Square_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [68h] Draw Line/Square/Triangle Start X-coordination [7:0] + [69h] Draw Line/Square/Triangle Start X-coordination [12:8] + [6Ah] Draw Line/Square/Triangle Start Y-coordination [7:0] + [6Bh] Draw Line/Square/Triangle Start Y-coordination [12:8] + */ + LCD_CmdWrite(0x68); + LCD_DataWrite(WX); + LCD_CmdWrite(0x69); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x6A); + LCD_DataWrite(HY); + LCD_CmdWrite(0x6B); + LCD_DataWrite(HY>>8); +} +//よ沧翴 +void Square_End_XY(unsigned short WX,unsigned short HY) +{ + /* + [6Ch] Draw Line/Square/Triangle End X-coordination [7:0] + [6Dh] Draw Line/Square/Triangle End X-coordination [12:8] + [6Eh] Draw Line/Square/Triangle End Y-coordination [7:0] + [6Fh] Draw Line/Square/Triangle End Y-coordination [12:8] + */ + LCD_CmdWrite(0x6C); + LCD_DataWrite(WX); + LCD_CmdWrite(0x6D); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x6E); + LCD_DataWrite(HY); + LCD_CmdWrite(0x6F); + LCD_DataWrite(HY>>8); +} +//[76h]========================================================================= +/* +[bit7] +Draw Circle / Ellipse / Square /Circle Square Start Signal +Write Function +0 : Stop the drawing function. +1 : Start the drawing function. +Read Function +0 : Drawing function complete. +1 : Drawing function is processing. +[bit6] +Fill the Circle / Ellipse / Square / Circle Square Signal +0 : Non fill. +1 : fill. +[bit5 bit4] +Draw Circle / Ellipse / Square / Ellipse Curve / Circle Square Select +00 : Draw Circle / Ellipse +01 : Draw Circle / Ellipse Curve +10 : Draw Square. +11 : Draw Circle Square. +[bit1 bit0] +Draw Circle / Ellipse Curve Part Select +00 : +01 : +10 : +11 : +*/ +void Start_Circle_or_Ellipse(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0x80);//B1000_XXXX + Check_Busy_Draw(); +} +void Start_Circle_or_Ellipse_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xC0);//B1100_XXXX + Check_Busy_Draw(); +} +// +void Start_Left_Down_Curve(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0x90);//B1001_XX00 + Check_Busy_Draw(); +} +void Start_Left_Up_Curve(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0x91);//B1001_XX01 + Check_Busy_Draw(); +} +void Start_Right_Up_Curve(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0x92);//B1001_XX10 + Check_Busy_Draw(); +} +void Start_Right_Down_Curve(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0x93);//B1001_XX11 + Check_Busy_Draw(); +} +// +void Start_Left_Down_Curve_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xD0);//B1101_XX00 + Check_Busy_Draw(); +} +void Start_Left_Up_Curve_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xD1);//B1101_XX01 + Check_Busy_Draw(); +} +void Start_Right_Up_Curve_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xD2);//B1101_XX10 + Check_Busy_Draw(); +} +void Start_Right_Down_Curve_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xD3);//B1101_XX11 + Check_Busy_Draw(); +} +// +void Start_Square(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xA0);//B1010_XXXX + Check_Busy_Draw(); +} +void Start_Square_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xE0);//B1110_XXXX + Check_Busy_Draw(); +} +void Start_Circle_Square(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xB0);//B1011_XXXX + Check_Busy_Draw(); +} +void Start_Circle_Square_Fill(void) +{ + LCD_CmdWrite(0x76); + LCD_DataWrite(0xF0);//B1111_XXXX + Check_Busy_Draw(); +} +//[77h]~[7Eh]========================================================================= +//蛾いみ +void Circle_Center_XY(unsigned short WX,unsigned short HY) +{ + /* + [7Bh] Draw Circle/Ellipse/Circle Square Center X-coordination [7:0] + [7Ch] Draw Circle/Ellipse/Circle Square Center X-coordination [12:8] + [7Dh] Draw Circle/Ellipse/Circle Square Center Y-coordination [7:0] + [7Eh] Draw Circle/Ellipse/Circle Square Center Y-coordination [12:8] + */ + LCD_CmdWrite(0x7B); + LCD_DataWrite(WX); + LCD_CmdWrite(0x7C); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x7D); + LCD_DataWrite(HY); + LCD_CmdWrite(0x7E); + LCD_DataWrite(HY>>8); +} +//掘蛾いみ +void Ellipse_Center_XY(unsigned short WX,unsigned short HY) +{ + /* + [7Bh] Draw Circle/Ellipse/Circle Square Center X-coordination [7:0] + [7Ch] Draw Circle/Ellipse/Circle Square Center X-coordination [12:8] + [7Dh] Draw Circle/Ellipse/Circle Square Center Y-coordination [7:0] + [7Eh] Draw Circle/Ellipse/Circle Square Center Y-coordination [12:8] + */ + LCD_CmdWrite(0x7B); + LCD_DataWrite(WX); + LCD_CmdWrite(0x7C); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x7D); + LCD_DataWrite(HY); + LCD_CmdWrite(0x7E); + LCD_DataWrite(HY>>8); +} +//蛾畖 +void Circle_Radius_R(unsigned short WX) +{ + /* + [77h] Draw Circle/Ellipse/Circle Square Major radius [7:0] + [78h] Draw Circle/Ellipse/Circle Square Major radius [12:8] + [79h] Draw Circle/Ellipse/Circle Square Minor radius [7:0] + [7Ah] Draw Circle/Ellipse/Circle Square Minor radius [12:8] + */ + LCD_CmdWrite(0x77); + LCD_DataWrite(WX); + LCD_CmdWrite(0x78); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x79); + LCD_DataWrite(WX); + LCD_CmdWrite(0x7A); + LCD_DataWrite(WX>>8); +} + +//掘蛾畖 +void Ellipse_Radius_RxRy(unsigned short WX,unsigned short HY) +{ + /* + [77h] Draw Circle/Ellipse/Circle Square Major radius [7:0] + [78h] Draw Circle/Ellipse/Circle Square Major radius [12:8] + [79h] Draw Circle/Ellipse/Circle Square Minor radius [7:0] + [7Ah] Draw Circle/Ellipse/Circle Square Minor radius [12:8] + */ + LCD_CmdWrite(0x77); + LCD_DataWrite(WX); + LCD_CmdWrite(0x78); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x79); + LCD_DataWrite(HY); + LCD_CmdWrite(0x7A); + LCD_DataWrite(HY>>8); +} + +//よ锣à畖 +void Circle_Square_Radius_RxRy(unsigned short WX,unsigned short HY) +{ + /* + [77h] Draw Circle/Ellipse/Circle Square Major radius [7:0] + [78h] Draw Circle/Ellipse/Circle Square Major radius [12:8] + [79h] Draw Circle/Ellipse/Circle Square Minor radius [7:0] + [7Ah] Draw Circle/Ellipse/Circle Square Minor radius [12:8] + */ + LCD_CmdWrite(0x77); + LCD_DataWrite(WX); + LCD_CmdWrite(0x78); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0x79); + LCD_DataWrite(HY); + LCD_CmdWrite(0x7A); + LCD_DataWrite(HY>>8); +} + +//[84h]========================================================================= +void Set_PWM_Prescaler_1_to_256(unsigned short WX) +{ + /* + PWM Prescaler Register + These 8 bits determine prescaler value for Timer 0 and 1. + Time base is ¨Core_Freq / (Prescaler + 1)〃 + */ + WX=WX-1; + LCD_CmdWrite(0x84); + LCD_DataWrite(WX); +} +//[85h]========================================================================= +void Select_PWM1_Clock_Divided_By_1(void) +{ + /* + Select MUX input for PWM Timer 1. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Select_PWM1_Clock_Divided_By_2(void) +{ + /* + Select MUX input for PWM Timer 1. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp &= cClrb7; + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Select_PWM1_Clock_Divided_By_4(void) +{ + /* + Select MUX input for PWM Timer 1. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Select_PWM1_Clock_Divided_By_8(void) +{ + /* + Select MUX input for PWM Timer 1. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb7; + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Select_PWM0_Clock_Divided_By_1(void) +{ + /* + Select MUX input for PWM Timer 0. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp &= cClrb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Select_PWM0_Clock_Divided_By_2(void) +{ + /* + Select MUX input for PWM Timer 0. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp &= cClrb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Select_PWM0_Clock_Divided_By_4(void) +{ + /* + Select MUX input for PWM Timer 0. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Select_PWM0_Clock_Divided_By_8(void) +{ + /* + Select MUX input for PWM Timer 0. + 00 = 1; 01 = 1/2; 10 = 1/4 ; 11 = 1/8; + */ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +//[85h].[bit3][bit2]========================================================================= +/* +XPWM[1] pin function control +0X: XPWM[1] output system error flag (REG[00h] bit[1:0], Scan bandwidth insufficient + Memory access out of range) +10: XPWM[1] enabled and controlled by PWM timer 1 +11: XPWM[1] output oscillator clock +//If XTEST[0] set high, then XPWM[1] will become panel scan clock input. +*/ +void Select_PWM1_is_ErrorFlag(void) +{ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Select_PWM1(void) +{ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Select_PWM1_is_Osc_Clock(void) +{ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +//[85h].[bit1][bit0]========================================================================= +/* +XPWM[0] pin function control +0X: XPWM[0] becomes GPIO-C[7] +10: XPWM[0] enabled and controlled by PWM timer 0 +11: XPWM[0] output core clock +*/ +void Select_PWM0_is_GPIO_C7(void) +{ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Select_PWM0(void) +{ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Select_PWM0_is_Core_Clock(void) +{ + unsigned char temp; + LCD_CmdWrite(0x85); + temp = LCD_DataRead(); + temp |= cSetb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +//[86h]========================================================================= +//[86h]PWM1 +void Enable_PWM1_Inverter(void) +{ + /* + PWM Timer 1 output inverter on/off. + Determine the output inverter on/off for Timer 1. + 0 = Inverter off + 1 = Inverter on for PWM1 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Disable_PWM1_Inverter(void) +{ + /* + PWM Timer 1 output inverter on/off. + Determine the output inverter on/off for Timer 1. + 0 = Inverter off + 1 = Inverter on for PWM1 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Auto_Reload_PWM1(void) +{ + /* + PWM Timer 1 auto reload on/off + Determine auto reload on/off for Timer 1. + 0 = One-shot + 1 = Interval mode(auto reload) + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void One_Shot_PWM1(void) +{ + /* + PWM Timer 1 auto reload on/off + Determine auto reload on/off for Timer 1. + 0 = One-shot + 1 = Interval mode(auto reload) + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void Start_PWM1(void) +{ + /* + PWM Timer 1 start/stop + Determine start/stop for Timer 1. + 0 = Stop + 1 = Start for Timer 1 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Stop_PWM1(void) +{ + /* + PWM Timer 1 start/stop + Determine start/stop for Timer 1. + 0 = Stop + 1 = Start for Timer 1 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +//[86h]PWM0 +void Enable_PWM0_Dead_Zone(void) +{ + /* + PWM Timer 0 Dead zone enable + Determine the dead zone operation. 0 = Disable. 1 = Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Disable_PWM0_Dead_Zone(void) +{ + /* + PWM Timer 0 Dead zone enable + Determine the dead zone operation. 0 = Disable. 1 = Enable. + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb3; + LCD_DataWrite(temp); +} +void Enable_PWM0_Inverter(void) +{ + /* + PWM Timer 0 output inverter on/off + Determine the output inverter on/off for Timer 0. + 0 = Inverter off + 1 = Inverter on for PWM0 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Disable_PWM0_Inverter(void) +{ + /* + PWM Timer 0 output inverter on/off + Determine the output inverter on/off for Timer 0. + 0 = Inverter off + 1 = Inverter on for PWM0 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Auto_Reload_PWM0(void) +{ + /* + PWM Timer 0 auto reload on/off + Determine auto reload on/off for Timer 0. + 0 = One-shot + 1 = Interval mode(auto reload) + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} +void One_Shot_PWM0(void) +{ + /* + PWM Timer 1 auto reload on/off + Determine auto reload on/off for Timer 1. + 0 = One-shot + 1 = Interval mode(auto reload) + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} +void Start_PWM0(void) +{ + /* + PWM Timer 0 start/stop + Determine start/stop for Timer 0. + 0 = Stop + 1 = Start for Timer 0 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Stop_PWM0(void) +{ + /* + PWM Timer 0 start/stop + Determine start/stop for Timer 0. + 0 = Stop + 1 = Start for Timer 0 + */ + unsigned char temp; + LCD_CmdWrite(0x86); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} +//[87h]========================================================================= +void Set_Timer0_Dead_Zone_Length(unsigned char temp) +{ + /* + Timer 0 Dead zone length register + These 8 bits determine the dead zone length. The 1 unit time of + the dead zone length is equal to that of timer 0. + */ + LCD_CmdWrite(0x87); + LCD_DataWrite(temp); +} +//[88h][89h]========================================================================= +void Set_Timer0_Compare_Buffer(unsigned short WX) +{ + /* + Timer 0 compare buffer register + Compare buffer register total has 16 bits. + When timer counter equal or less than compare buffer register will cause PWM out + high level if inv_on bit is off. + */ + LCD_CmdWrite(0x88); + LCD_DataWrite(WX); + LCD_CmdWrite(0x89); + LCD_DataWrite(WX>>8); +} +//[8Ah][8Bh]========================================================================= +void Set_Timer0_Count_Buffer(unsigned short WX) +{ + /* + Timer 0 count buffer register + Count buffer register total has 16 bits. + When timer counter equal to 0 will cause PWM timer reload Count buffer register if reload_en bit set as enable. + It may read back timer counterˇs real time value when PWM timer start. + */ + LCD_CmdWrite(0x8A); + LCD_DataWrite(WX); + LCD_CmdWrite(0x8B); + LCD_DataWrite(WX>>8); +} +//[8Ch][8Dh]========================================================================= +void Set_Timer1_Compare_Buffer(unsigned short WX) +{ + /* + Timer 0 compare buffer register + Compare buffer register total has 16 bits. + When timer counter equal or less than compare buffer register will cause PWM out + high level if inv_on bit is off. + */ + LCD_CmdWrite(0x8C); + LCD_DataWrite(WX); + LCD_CmdWrite(0x8D); + LCD_DataWrite(WX>>8); +} +//[8Eh][8Fh]========================================================================= +void Set_Timer1_Count_Buffer(unsigned short WX) +{ + /* + Timer 0 count buffer register + Count buffer register total has 16 bits. + When timer counter equal to 0 will cause PWM timer reload Count buffer register if reload_en bit set as enable. + It may read back timer counterˇs real time value when PWM timer start. + */ + LCD_CmdWrite(0x8E); + LCD_DataWrite(WX); + LCD_CmdWrite(0x8F); + LCD_DataWrite(WX>>8); +} + + +//[90h]~[B5h]========================================================================= + +//[90h]========================================================================= +void BTE_Enable(void) +{ + /* + BTE Function Enable + 0 : BTE Function disable. + 1 : BTE Function enable. + */ + unsigned char temp; + LCD_CmdWrite(0x90); + temp = LCD_DataRead(); + temp |= cSetb4 ; + LCD_DataWrite(temp); +} + +//[90h]========================================================================= +void BTE_Disable(void) +{ + /* + BTE Function Enable + 0 : BTE Function disable. + 1 : BTE Function enable. + */ + unsigned char temp; + LCD_CmdWrite(0x90); + temp = LCD_DataRead(); + temp &= cClrb4 ; + LCD_DataWrite(temp); +} + +//[90h]========================================================================= +void Check_BTE_Busy(void) +{ + /* + BTE Function Status + 0 : BTE Function is idle. + 1 : BTE Function is busy. + */ + unsigned char temp; + + do + { + temp=LCD_StatusRead(); + } + while(temp&0x08); +} +//[90h]========================================================================= +void Pattern_Format_8X8(void) +{ + /* + Pattern Format + 0 : 8X8 + 1 : 16X16 + */ + unsigned char temp; + LCD_CmdWrite(0x90); + temp = LCD_DataRead(); + temp &= cClrb0 ; + LCD_DataWrite(temp); +} +//[90h]========================================================================= +void Pattern_Format_16X16(void) +{ + /* + Pattern Format + 0 : 8X8 + 1 : 16X16 + */ + unsigned char temp; + LCD_CmdWrite(0x90); + temp = LCD_DataRead(); + temp |= cSetb0 ; + LCD_DataWrite(temp); +} + +//[91h]========================================================================= +void BTE_ROP_Code(unsigned char setx) +{ + /* + BTE ROP Code[Bit7:4] + + 0000 : 0(Blackness) + 0001 : ~S0.~S1 or ~ ( S0+S1 ) + 0010 : ~S0.S1 + 0011 : ~S0 + 0100 : S0.~S1 + 0101 : ~S1 + 0110 : S0^S1 + 0111 : ~S0+~S1 or ~ ( S0.S1 ) + 1000 : S0.S1 + 1001 : ~ ( S0^S1 ) + 1010 : S1 + 1011 : ~S0+S1 + 1100 : S0 + 1101 : S0+~S1 + 1110 : S0+S1 + 1111 : 1 ( Whiteness ) + */ + unsigned char temp; + LCD_CmdWrite(0x91); + temp = LCD_DataRead(); + temp &= 0x0f ; + temp |= (setx<<4); + LCD_DataWrite(temp); +} + +//[91h]========================================================================= +void BTE_Operation_Code(unsigned char setx) +{ + /* + BTE Operation Code[Bit3:0] + + 0000 : MPU Write BTE with ROP. + 0001 : MPU Read BTE w/o ROP. + 0010 : Memory copy (move) BTE in positive direction with ROP. + 0011 : Memory copy (move) BTE in negative direction with ROP. + 0100 : MPU Transparent Write BTE. (w/o ROP.) + 0101 : Transparent Memory copy (move) BTE in positive direction (w/o ROP.) + 0110 : Pattern Fill with ROP. + 0111 : Pattern Fill with key-chroma + 1000 : Color Expansion + 1001 : Color Expansion with transparency + 1010 : Move BTE in positive direction with Alpha blending + 1011 : MPU Write BTE with Alpha blending + 1100 : Solid Fill + 1101 : Reserved + 1110 : Reserved + 1111 : Reserved + */ + unsigned char temp; + LCD_CmdWrite(0x91); + temp = LCD_DataRead(); + temp &= 0xf0 ; + temp |= setx ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_S0_Color_8bpp(void) +{ + /* + S0 Color Depth + 00 : 256 Color + 01 : 64k Color + 1x : 16M Color + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb6 ; + temp &= cClrb5 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_S0_Color_16bpp(void) +{ + /* + S0 Color Depth + 00 : 256 Color + 01 : 64k Color + 1x : 16M Color + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb6 ; + temp |= cSetb5 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_S0_Color_24bpp(void) +{ + /* + S0 Color Depth + 00 : 256 Color + 01 : 64k Color + 1x : 16M Color + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp |= cSetb6 ; + //temp |= cSetb5 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_S1_Color_8bpp(void) +{ + /* + S1 Color Depth + 000 : 256 Color + 001 : 64k Color + 010 : 16M Color + 011 : Constant Color + 100 : 8 bit pixel alpha blending + 101 : 16 bit pixel alpha blending + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb4 ; + temp &= cClrb3 ; + temp &= cClrb2 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_S1_Color_16bpp(void) +{ + /* + S1 Color Depth + 000 : 256 Color + 001 : 64k Color + 010 : 16M Color + 011 : Constant Color + 100 : 8 bit pixel alpha blending + 101 : 16 bit pixel alpha blending + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb4 ; + temp &= cClrb3 ; + temp |= cSetb2 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_S1_Color_24bpp(void) +{ + /* + S1 Color Depth + 000 : 256 Color + 001 : 64k Color + 010 : 16M Color + 011 : Constant Color + 100 : 8 bit pixel alpha blending + 101 : 16 bit pixel alpha blending + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb4 ; + temp |= cSetb3 ; + temp &= cClrb2 ; + LCD_DataWrite(temp); +} + +//[92h]========================================================================= +void BTE_S1_Color_Constant(void) +{ + /* + S1 Color Depth + 000 : 256 Color + 001 : 64k Color + 010 : 16M Color + 011 : Constant Color + 100 : 8 bit pixel alpha blending + 101 : 16 bit pixel alpha blending + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb4 ; + temp |= cSetb3 ; + temp |= cSetb2 ; + LCD_DataWrite(temp); +} + + + +//[92h]========================================================================= +void BTE_S1_Color_8bit_Alpha(void) +{ + /* + S1 Color Depth + 000 : 256 Color + 001 : 64k Color + 010 : 16M Color + 011 : Constant Color + 100 : 8 bit pixel alpha blending + 101 : 16 bit pixel alpha blending + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp |= cSetb4 ; + temp &= cClrb3 ; + temp &= cClrb2 ; + LCD_DataWrite(temp); +} + +//[92h]========================================================================= +void BTE_S1_Color_16bit_Alpha(void) +{ + /* + S1 Color Depth + 000 : 256 Color + 001 : 64k Color + 010 : 16M Color + 011 : Constant Color + 100 : 8 bit pixel alpha blending + 101 : 16 bit pixel alpha blending + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp |= cSetb4 ; + temp &= cClrb3 ; + temp |= cSetb2 ; + LCD_DataWrite(temp); +} + +//[92h]========================================================================= +void BTE_Destination_Color_8bpp(void) +{ + /* + Destination Color Depth + 00 : 256 Color + 01 : 64k Color + 1x : 16M Color + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb1 ; + temp &= cClrb0 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_Destination_Color_16bpp(void) +{ + /* + Destination Color Depth + 00 : 256 Color + 01 : 64k Color + 1x : 16M Color + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp &= cClrb1 ; + temp |= cSetb0 ; + LCD_DataWrite(temp); +} +//[92h]========================================================================= +void BTE_Destination_Color_24bpp(void) +{ + /* + Destination Color Depth + 00 : 256 Color + 10 : 64k Color + 1x : 16M Color + */ + unsigned char temp; + LCD_CmdWrite(0x92); + temp = LCD_DataRead(); + temp |= cSetb1 ; + //temp |= cSetb0 ; + LCD_DataWrite(temp); +} + + +//[93h][94h][95h][96h]========================================================================= +void BTE_S0_Memory_Start_Address(unsigned long Addr) +{ + /* + [93h] BTE S0 Memory Start Address [7:0] + [94h] BTE S0 Memory Start Address [15:8] + [95h] BTE S0 Memory Start Address [23:16] + [96h] BTE S0 Memory Start Address [31:24] + Bit [1:0] tie to ¨0〃 internally. + */ + LCD_RegisterWrite(0x93,Addr); + LCD_RegisterWrite(0x94,Addr>>8); + LCD_RegisterWrite(0x95,Addr>>16); + LCD_RegisterWrite(0x96,Addr>>24); +} + + +//[97h][98h]========================================================================= +void BTE_S0_Image_Width(unsigned short WX) +{ + /* + [97h] BTE S0 Image Width [7:0] + [98h] BTE S0 Image Width [12:8] + Unit: Pixel. + Bit [1:0] tie to ¨0〃 internally. + */ + LCD_RegisterWrite(0x97,WX); + LCD_RegisterWrite(0x98,WX>>8); +} + + +//[99h][9Ah][9Bh][9Ch]========================================================================= +void BTE_S0_Window_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [99h] BTE S0 Window Upper-Left corner X-coordination [7:0] + [9Ah] BTE S0 Window Upper-Left corner X-coordination [12:8] + [9Bh] BTE S0 Window Upper-Left corner Y-coordination [7:0] + [9Ch] BTE S0 Window Upper-Left corner Y-coordination [12:8] + */ + LCD_RegisterWrite(0x99,WX); + LCD_RegisterWrite(0x9A,WX>>8); + LCD_RegisterWrite(0x9B,HY); + LCD_RegisterWrite(0x9C,HY>>8); +} + + + + +//[9Dh][9Eh][9Fh][A0h]========================================================================= +void BTE_S1_Memory_Start_Address(unsigned long Addr) +{ + /* + [9Dh] BTE S1 Memory Start Address [7:0] + [9Eh] BTE S1 Memory Start Address [15:8] + [9Fh] BTE S1 Memory Start Address [23:16] + [A0h] BTE S1 Memory Start Address [31:24] + Bit [1:0] tie to ¨0〃 internally. + */ + LCD_RegisterWrite(0x9D,Addr); + LCD_RegisterWrite(0x9E,Addr>>8); + LCD_RegisterWrite(0x9F,Addr>>16); + LCD_RegisterWrite(0xA0,Addr>>24); +} + + +//Input data format:R3G3B2 +void S1_Constant_color_256(unsigned char temp) +{ + LCD_CmdWrite(0x9D); + LCD_DataWrite(temp); + LCD_CmdWrite(0x9E); + LCD_DataWrite(temp<<3); + LCD_CmdWrite(0x9F); + LCD_DataWrite(temp<<6); +} + +//Input data format:R5G6B6 +void S1_Constant_color_65k(unsigned short temp) +{ + LCD_CmdWrite(0x9D); + LCD_DataWrite(temp>>8); + LCD_CmdWrite(0x9E); + LCD_DataWrite(temp>>3); + LCD_CmdWrite(0x9F); + LCD_DataWrite(temp<<3); +} + +//Input data format:R8G8B8 +void S1_Constant_color_16M(unsigned long temp) +{ + LCD_CmdWrite(0x9D); + LCD_DataWrite(temp>>16); + LCD_CmdWrite(0x9E); + LCD_DataWrite(temp>>8); + LCD_CmdWrite(0x9F); + LCD_DataWrite(temp); +} + + + + +//[A1h][A2h]========================================================================= +void BTE_S1_Image_Width(unsigned short WX) +{ + /* + [A1h] BTE S1 Image Width [7:0] + [A2h] BTE S1 Image Width [12:8] + Unit: Pixel. + Bit [1:0] tie to ¨0〃 internally. + */ + LCD_RegisterWrite(0xA1,WX); + LCD_RegisterWrite(0xA2,WX>>8); +} + + +//[A3h][A4h][A5h][A6h]========================================================================= +void BTE_S1_Window_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [A3h] BTE S1 Window Upper-Left corner X-coordination [7:0] + [A4h] BTE S1 Window Upper-Left corner X-coordination [12:8] + [A5h] BTE S1 Window Upper-Left corner Y-coordination [7:0] + [A6h] BTE S1 Window Upper-Left corner Y-coordination [12:8] + */ + LCD_RegisterWrite(0xA3,WX); + LCD_RegisterWrite(0xA4,WX>>8); + LCD_RegisterWrite(0xA5,HY); + LCD_RegisterWrite(0xA6,HY>>8); +} + + + + +//[A7h][A8h][A9h][AAh]========================================================================= +void BTE_Destination_Memory_Start_Address(unsigned long Addr) +{ + /* + [A7h] BTE Destination Memory Start Address [7:0] + [A8h] BTE Destination Memory Start Address [15:8] + [A9h] BTE Destination Memory Start Address [23:16] + [AAh] BTE Destination Memory Start Address [31:24] + Bit [1:0] tie to ¨0〃 internally. + */ + LCD_RegisterWrite(0xA7,Addr); + LCD_RegisterWrite(0xA8,Addr>>8); + LCD_RegisterWrite(0xA9,Addr>>16); + LCD_RegisterWrite(0xAA,Addr>>24); +} + + +//[ABh][ACh]========================================================================= +void BTE_Destination_Image_Width(unsigned short WX) +{ + /* + [ABh] BTE Destination Image Width [7:0] + [ACh] BTE Destination Image Width [12:8] + Unit: Pixel. + Bit [1:0] tie to ¨0〃 internally. + */ + LCD_RegisterWrite(0xAB,WX); + LCD_RegisterWrite(0xAC,WX>>8); +} + + +//[ADh][AEh][AFh][B0h]========================================================================= +void BTE_Destination_Window_Start_XY(unsigned short WX,unsigned short HY) +{ + /* + [ADh] BTE Destination Window Upper-Left corner X-coordination [7:0] + [AEh] BTE Destination Window Upper-Left corner X-coordination [12:8] + [AFh] BTE Destination Window Upper-Left corner Y-coordination [7:0] + [B0h] BTE Destination Window Upper-Left corner Y-coordination [12:8] + */ + LCD_RegisterWrite(0xAD,WX); + LCD_RegisterWrite(0xAE,WX>>8); + LCD_RegisterWrite(0xAF,HY); + LCD_RegisterWrite(0xB0,HY>>8); +} + + +//[B1h][B2h][B3h][B4h]=============================================================== + +void BTE_Window_Size(unsigned short WX, unsigned short WY) + +{ + /* + [B1h] BTE Window Width [7:0] + [B2h] BTE Window Width [12:8] + + [B3h] BTE Window Height [7:0] + [B4h] BTE Window Height [12:8] + */ + LCD_RegisterWrite(0xB1,WX); + LCD_RegisterWrite(0xB2,WX>>8); + LCD_RegisterWrite(0xB3,WY); + LCD_RegisterWrite(0xB4,WY>>8); +} + +//[B5h]========================================================================= +void BTE_Alpha_Blending_Effect(unsigned char temp) +{ + /* + Window Alpha Blending effect for S0 & S1 + The value of alpha in the color code ranges from 0.0 to 1.0, + where 0.0 represents a fully transparent color, and 1.0 + represents a fully opaque color. + 00h: 0 + 01h: 1/32 + 02h: 2/32 + : + 1Eh: 30/32 + 1Fh: 31/32 + 2Xh: 1 + Output Effect = (S0 image x (1 - alpha setting value)) + (S1 image x alpha setting value) + */ + LCD_CmdWrite(0xB5); + LCD_DataWrite(temp); +} + + +//[B6h]========================================================================= +void Start_SFI_DMA(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB6); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} + +void Check_Busy_SFI_DMA(void) +{ + LCD_CmdWrite(0xB6); + + do + { + } + while((LCD_DataRead()&0x01)==0x01); +} + + +//[B7h]========================================================================= +void Select_SFI_0(void) +{ + /*[bit7] + Serial Flash/ROM I/F # Select + 0: Serial Flash/ROM 0 I/F is selected. + 1: Serial Flash/ROM 1 I/F is selected. + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void Select_SFI_1(void) +{ + /*[bit7] + Serial Flash/ROM I/F # Select + 0: Serial Flash/ROM 0 I/F is selected. + 1: Serial Flash/ROM 1 I/F is selected. + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Select_SFI_Font_Mode(void) +{ + /*[bit6] + Serial Flash /ROM Access Mode + 0: Font mode  for external cgrom + 1: DMA mode  for cgram , pattern , bootstart image or osd + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Select_SFI_DMA_Mode(void) +{ + /*[bit6] + Serial Flash /ROM Access Mode + 0: Font mode  for external cgrom + 1: DMA mode  for cgram , pattern , bootstart image or osd + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Select_SFI_24bit_Address(void) +{ + /*[bit5] + Serial Flash/ROM Address Mode + 0: 24 bits address mode + 1: 32 bits address mode + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} +void Select_SFI_32bit_Address(void) +{ + /*[bit5] + Serial Flash/ROM Address Mode + 0: 24 bits address mode + 1: 32 bits address mode + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} +void Select_SFI_Waveform_Mode_0(void) +{ + /*[bit4] + Serial Flash/ROM Waveform Mode + Mode 0. + Mode 3. + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Select_SFI_Waveform_Mode_3(void) +{ + /*[bit4] + Serial Flash/ROM Waveform Mode + Mode 0. + Mode 3. + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Select_SFI_0_DummyRead(void) +{ + /*[bit3][bit2] + Serial Flash /ROM Read Cycle 0 RW + 00b: no dummy cycle mode + 01b: 1 dummy cycle mode + 10b: 2 dummy cycle mode + 11b: 4 dummy cycle mode + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= 0xF3; + LCD_DataWrite(temp); +} +void Select_SFI_8_DummyRead(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= 0xF3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Select_SFI_16_DummyRead(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= 0xF3; + temp |= cSetb3; + LCD_DataWrite(temp); +} +void Select_SFI_24_DummyRead(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp |= 0x0c; + LCD_DataWrite(temp); +} +void Select_SFI_Single_Mode(void) +{ + /*[bit1][bit0] + Serial Flash /ROM I/F Data Latch Mode Select + 0Xb: Single Mode + 10b: Dual Mode 0. + 11b: Dual Mode 1. + */ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= 0xFC; + LCD_DataWrite(temp); +} +void Select_SFI_Dual_Mode0(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp &= 0xFC; + temp |= cSetb1; + LCD_DataWrite(temp); +} +void Select_SFI_Dual_Mode1(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB7); + temp = LCD_DataRead(); + temp |= 0x03; + LCD_DataWrite(temp); +} + +//REG[B8h] SPI master Tx /Rx FIFO Data Register (SPIDR) +unsigned char SPI_Master_FIFO_Data_Put(unsigned char Data) +{ + unsigned char temp; + LCD_CmdWrite(0xB8); + LCD_DataWrite(Data); + + while(Tx_FIFO_Empty_Flag()==0); + + temp = SPI_Master_FIFO_Data_Get(); + return temp; +} + +unsigned char SPI_Master_FIFO_Data_Get(void) +{ + unsigned char temp; + + while(Rx_FIFO_Empty_Flag()==1); + + LCD_CmdWrite(0xB8); + temp=LCD_DataRead(); + //while(Rx_FIFO_full_flag()); + return temp; +} + +//REG[B9h] SPI master Control Register (SPIMCR2) +void Mask_SPI_Master_Interrupt_Flag(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} + +void Select_nSS_drive_on_xnsfcs0(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp &= cClrb5; + LCD_DataWrite(temp); +} + +void Select_nSS_drive_on_xnsfcs1(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb5; + LCD_DataWrite(temp); +} + +//0: inactive (nSS port will goes high) +void nSS_Inactive(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +//1: active (nSS port will goes low) +void nSS_Active(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} + +//Interrupt enable for FIFO overflow error [OVFIRQEN] +void OVFIRQEN_Enable(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} +//Interrupt enable for while Tx FIFO empty & SPI engine/FSM idle +void EMTIRQEN_Enable(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} + + +//At CPOL=0 the base value of the clock is zero +//o For CPHA=0, data are read on the clock's rising edge (low->high transition) and +//data are changed on a falling edge (high->low clock transition). +//o For CPHA=1, data are read on the clock's falling edge and data are changed on a +//rising edge. + +//At CPOL=1 the base value of the clock is one (inversion of CPOL=0) +//o For CPHA=0, data are read on clock's falling edge and data are changed on a +//rising edge. +//o For CPHA=1, data are read on clock's rising edge and data are changed on a +//falling edge. + +void Reset_CPOL(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp &= cClrb1; + LCD_DataWrite(temp); +} + +void Set_CPOL(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb1; + LCD_DataWrite(temp); +} + + +void Reset_CPHA(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp &= cClrb0; + LCD_DataWrite(temp); +} + +void Set_CPHA(void) +{ + unsigned char temp; + LCD_CmdWrite(0xB9); + temp = LCD_DataRead(); + temp |= cSetb0; + LCD_DataWrite(temp); +} + + +//REG[BAh] SPI master Status Register (SPIMSR) +unsigned char Tx_FIFO_Empty_Flag(void) +{ + LCD_CmdWrite(0xBA); + + if((LCD_DataRead()&0x80)==0x80) + { + return 1; + } + else + { + return 0; + } +} + +unsigned char Tx_FIFO_Full_Flag(void) +{ + LCD_CmdWrite(0xBA); + + if((LCD_DataRead()&0x40)==0x40) + { + return 1; + } + else + { + return 0; + } +} + +unsigned char Rx_FIFO_Empty_Flag(void) +{ + LCD_CmdWrite(0xBA); + + if((LCD_DataRead()&0x20)==0x20) + { + return 1; + } + else + { + return 0; + } +} + +unsigned char Rx_FIFO_full_flag(void) +{ + LCD_CmdWrite(0xBA); + + if((LCD_DataRead()&0x10)==0x10) + { + return 1; + } + else + { + return 0; + } +} + +unsigned char OVFI_Flag(void) +{ + LCD_CmdWrite(0xBA); + + if((LCD_DataRead()&0x08)==0x08) + { + return 1; + } + else + { + return 0; + } +} + +void Clear_OVFI_Flag(void) +{ + unsigned char temp; + LCD_CmdWrite(0xBA); + temp = LCD_DataRead(); + temp |= cSetb3; + LCD_DataWrite(temp); +} + +unsigned char EMTI_Flag(void) +{ + LCD_CmdWrite(0xBA); + + if((LCD_DataRead()&0x04)==0x04) + { + return 1; + } + else + { + return 0; + } +} + +void Clear_EMTI_Flag(void) +{ + unsigned char temp; + LCD_CmdWrite(0xBA); + temp = LCD_DataRead(); + temp |= cSetb2; + LCD_DataWrite(temp); +} + + +//REG[BB] SPI Clock period (SPIDIV) +void SPI_Clock_Period(unsigned char temp) +{ + LCD_CmdWrite(0xBB); + LCD_DataWrite(temp); +} + +//[BCh][BDh][BEh][BFh]========================================================================= +void SFI_DMA_Source_Start_Address(unsigned long Addr) +{ + /* + DMA Source START ADDRESS + This bits index serial flash address [7:0][15:8][23:16][31:24] + */ + LCD_CmdWrite(0xBC); + LCD_DataWrite(Addr); + LCD_CmdWrite(0xBD); + LCD_DataWrite(Addr>>8); + LCD_CmdWrite(0xBE); + LCD_DataWrite(Addr>>16); + LCD_CmdWrite(0xBF); + LCD_DataWrite(Addr>>24); +} +//[C0h][C1h][C2h][C3h]========================================================================= +void SFI_DMA_Destination_Start_Address(unsigned long Addr) +{ + /* + DMA Destination START ADDRESS + [1:0]Fix at 0 + This bits index SDRAM address [7:0][15:8][23:16][31:24] + */ + LCD_CmdWrite(0xC0); + LCD_DataWrite(Addr); + LCD_CmdWrite(0xC1); + LCD_DataWrite(Addr>>8); + LCD_CmdWrite(0xC2); + LCD_DataWrite(Addr>>16); + LCD_CmdWrite(0xC3); + LCD_DataWrite(Addr>>24); +} +//[C0h][C1h][C2h][C3h]========================================================================= +void SFI_DMA_Destination_Upper_Left_Corner(unsigned short WX,unsigned short HY) +{ + /* + C0h + This register defines DMA Destination Window Upper-Left corner + X-coordination [7:0] on Canvas area. + When REG DMACR bit 1 = 1 (Block Mode) + This register defines Destination address [7:2] in SDRAM. + C1h + When REG DMACR bit 1 = 0 (Linear Mode) + This register defines DMA Destination Window Upper-Left corner + X-coordination [12:8] on Canvas area. + When REG DMACR bit 1 = 1 (Block Mode) + This register defines Destination address [15:8] in SDRAM. + C2h + When REG DMACR bit 1 = 0 (Linear Mode) + This register defines DMA Destination Window Upper-Left corner + Y-coordination [7:0] on Canvas area. + When REG DMACR bit 1 = 1 (Block Mode) + This register defines Destination address [23:16] in SDRAM. + C3h + When REG DMACR bit 1 = 0 (Linear Mode) + This register defines DMA Destination Window Upper-Left corner + Y-coordination [12:8] on Canvas area. + When REG DMACR bit 1 = 1 (Block Mode) + This register defines Destination address [31:24] in SDRAM. + */ + LCD_CmdWrite(0xC0); + LCD_DataWrite(WX); + LCD_CmdWrite(0xC1); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0xC2); + LCD_DataWrite(HY); + LCD_CmdWrite(0xC3); + LCD_DataWrite(HY>>8); +} + + + +//[C6h][C7h][C8h][C9h]========================================================================= +void SFI_DMA_Transfer_Number(unsigned long Addr) +{ + /* + Unit : Pixel + When REG DMACR bit 1 = 0 (Linear Mode) + DMA Transfer Number [7:0][15:8][23:16][31:24] + + When REG DMACR bit 1 = 1 (Block Mode) + DMA Block Width [7:0][15:8] + DMA Block HIGH[7:0][15:8] + */ + LCD_CmdWrite(0xC6); + LCD_DataWrite(Addr); + LCD_CmdWrite(0xC7); + LCD_DataWrite(Addr>>8); + LCD_CmdWrite(0xC8); + LCD_DataWrite(Addr>>16); + LCD_CmdWrite(0xC9); + LCD_DataWrite(Addr>>24); +} +void SFI_DMA_Transfer_Width_Height(unsigned short WX,unsigned short HY) +{ + /* + When REG DMACR bit 1 = 0 (Linear Mode) + DMA Transfer Number [7:0][15:8][23:16][31:24] + + When REG DMACR bit 1 = 1 (Block Mode) + DMA Block Width [7:0][15:8] + DMA Block HIGH[7:0][15:8] + */ + LCD_CmdWrite(0xC6); + LCD_DataWrite(WX); + LCD_CmdWrite(0xC7); + LCD_DataWrite(WX>>8); + LCD_CmdWrite(0xC8); + LCD_DataWrite(HY); + LCD_CmdWrite(0xC9); + LCD_DataWrite(HY>>8); +} +//[CAh][CBh]========================================================================= +void SFI_DMA_Source_Width(unsigned short WX) +{ + /* + DMA Source Picture Width [7:0][12:8] + Unit: pixel + */ + LCD_CmdWrite(0xCA); + LCD_DataWrite(WX); + LCD_CmdWrite(0xCB); + LCD_DataWrite(WX>>8); +} + +//[CCh]========================================================================= + +void Font_Select_UserDefine_Mode(void) +{ + /*[bit7-6] + User-defined Font /CGROM Font Selection Bit in Text Mode + 00 : Internal CGROM + 01 : Genitop serial flash + 10 : User-defined Font + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp |= cSetb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void CGROM_Select_Internal_CGROM(void) +{ + /*[bit7-6] + User-defined Font /CGROM Font Selection Bit in Text Mode + 00 : Internal CGROM + 01 : Genitop serial flash + 10 : User-defined Font + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + LCD_DataWrite(temp); +} +void CGROM_Select_Genitop_FontROM(void) +{ + /*[bit7-6] + User-defined Font /CGROM Font Selection Bit in Text Mode + 00 : Internal CGROM + 01 : Genitop serial flash + 10 : User-defined Font + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp &= cClrb7; + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Font_Select_8x16_16x16(void) +{ + /*[bit5-4] + Font Height Setting + 00b : 8x16 / 16x16. + 01b : 12x24 / 24x24. + 10b : 16x32 / 32x32. + *** User-defined Font width is decided by font code. Genitop + serial flashˇs font width is decided by font code or GT Font ROM + control register. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp &= cClrb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Font_Select_12x24_24x24(void) +{ + /*[bit5-4] + Font Height Setting + 00b : 8x16 / 16x16. + 01b : 12x24 / 24x24. + 10b : 16x32 / 32x32. + *** User-defined Font width is decided by font code. Genitop + serial flashˇs font width is decided by font code or GT Font ROM + control register. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp &= cClrb5; + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Font_Select_16x32_32x32(void) +{ + /*[bit5-4] + Font Height Setting + 00b : 8x16 / 16x16. + 01b : 12x24 / 24x24. + 10b : 16x32 / 32x32. + *** User-defined Font width is decided by font code. Genitop + serial flashˇs font width is decided by font code or GT Font ROM + control register. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp |= cSetb5; + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Internal_CGROM_Select_ISOIEC8859_1(void) +{ + /* + Font Selection for internal CGROM + When FNCR0 B7 = 0 and B5 = 0, Internal CGROM supports the + 8x16 character sets with the standard coding of ISO/IEC 8859-1~4, + which supports English and most of European country languages. + 00b : ISO/IEC 8859-1. + 01b : ISO/IEC 8859-2. + 10b : ISO/IEC 8859-3. + 11b : ISO/IEC 8859-4. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp &= cClrb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Internal_CGROM_Select_ISOIEC8859_2(void) +{ + /* + Font Selection for internal CGROM + When FNCR0 B7 = 0 and B5 = 0, Internal CGROM supports the + 8x16 character sets with the standard coding of ISO/IEC 8859-1~4, + which supports English and most of European country languages. + 00b : ISO/IEC 8859-1. + 01b : ISO/IEC 8859-2. + 10b : ISO/IEC 8859-3. + 11b : ISO/IEC 8859-4. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp &= cClrb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Internal_CGROM_Select_ISOIEC8859_3(void) +{ + /* + Font Selection for internal CGROM + When FNCR0 B7 = 0 and B5 = 0, Internal CGROM supports the + 8x16 character sets with the standard coding of ISO/IEC 8859-1~4, + which supports English and most of European country languages. + 00b : ISO/IEC 8859-1. + 01b : ISO/IEC 8859-2. + 10b : ISO/IEC 8859-3. + 11b : ISO/IEC 8859-4. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp |= cSetb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Internal_CGROM_Select_ISOIEC8859_4(void) +{ + /* + Font Selection for internal CGROM + When FNCR0 B7 = 0 and B5 = 0, Internal CGROM supports the + 8x16 character sets with the standard coding of ISO/IEC 8859-1~4, + which supports English and most of European country languages. + 00b : ISO/IEC 8859-1. + 01b : ISO/IEC 8859-2. + 10b : ISO/IEC 8859-3. + 11b : ISO/IEC 8859-4. + */ + unsigned char temp; + LCD_CmdWrite(0xCC); + temp = LCD_DataRead(); + temp |= cSetb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +//[CDh]========================================================================= +void Enable_Font_Alignment(void) +{ + /* + Full Alignment Selection Bit + 0 : Full alignment disable. + 1 : Full alignment enable. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} +void Disable_Font_Alignment(void) +{ + /* + Full Alignment Selection Bit + 0 : Full alignment disable. + 1 : Full alignment enable. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb7; + LCD_DataWrite(temp); +} +void Font_Background_select_Transparency(void) +{ + /* + Font Transparency + 0 : Font with background color. + 1 : Font with background transparency. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} +void Font_Background_select_Color(void) +{ + /* + Font Transparency + 0 : Font with background color. + 1 : Font with background transparency. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb6; + LCD_DataWrite(temp); +} +void Font_0_degree(void) +{ + /* + Font Rotation + 0 : Normal + Text direction from left to right then from top to bottom + 1 : Counterclockwise 90 degree & horizontal flip + Text direction from top to bottom then from left to right + (it should accommodate with set VDIR as 1) + This attribute can be changed only when previous font write + finished (core_busy = 0) + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb4; + LCD_DataWrite(temp); +} +void Font_90_degree(void) +{ + /* + Font Rotation + 0 : Normal + Text direction from left to right then from top to bottom + 1 : Counterclockwise 90 degree & horizontal flip + Text direction from top to bottom then from left to right + (it should accommodate with set VDIR as 1) + This attribute can be changed only when previous font write + finished (core_busy = 0) + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb4; + LCD_DataWrite(temp); +} +void Font_Width_X1(void) +{ + /* + Horizontal Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Font_Width_X2(void) +{ + /* + Horizontal Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Font_Width_X3(void) +{ + /* + Horizontal Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb3; + temp &= cClrb2; + LCD_DataWrite(temp); +} +void Font_Width_X4(void) +{ + /* + Horizontal Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb3; + temp |= cSetb2; + LCD_DataWrite(temp); +} +void Font_Height_X1(void) +{ + /* + Vertical Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Font_Height_X2(void) +{ + /* + Vertical Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp &= cClrb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} +void Font_Height_X3(void) +{ + /* + Vertical Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb1; + temp &= cClrb0; + LCD_DataWrite(temp); +} +void Font_Height_X4(void) +{ + /* + Vertical Font Enlargement + 00b : X1. + 01b : X2. + 10b : X3. + 11b : X4. + */ + unsigned char temp; + LCD_CmdWrite(0xCD); + temp = LCD_DataRead(); + temp |= cSetb1; + temp |= cSetb0; + LCD_DataWrite(temp); +} + +//[CEh]========================================================================= +void GTFont_Select_GT21L16TW_GT21H16T1W(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + temp &= cClrb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT23L16U2W(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp &= cClrb7; + temp &= cClrb6; + temp |= cSetb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT23L24T3Y_GT23H24T3Y(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp &= cClrb7; + temp |= cSetb6; + temp &= cClrb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT23L24M1Z(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp &= cClrb7; + temp |= cSetb6; + temp |= cSetb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT23L32S4W_GT23H32S4W(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp |= cSetb7; + temp &= cClrb6; + temp &= cClrb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT20L24F6Y(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp |= cSetb7; + temp &= cClrb6; + temp |= cSetb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT21L24S1W(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp |= cSetb7; + temp |= cSetb6; + temp &= cClrb5; + LCD_DataWrite(temp); +} +void GTFont_Select_GT22L16A1Y(void) +{ + /* + GT Serial Font ROM Select + 000b: GT21L16TW / GT21H16T1W + 001b: GT23L16U2W + 010b: GT23L24T3Y / GT23H24T3Y + 011b: GT23L24M1Z + 100b: GT23L32S4W / GT23H32S4W + 101b: GT20L24F6Y + 110b: GT21L24S1W + 111b: GT22L16A1Y + */ + unsigned char temp; + LCD_CmdWrite(0xCE); + temp = LCD_DataRead(); + temp |= cSetb7; + temp |= cSetb6; + temp |= cSetb5; + LCD_DataWrite(temp); +} + +//[CFh]========================================================================= +void Set_GTFont_Decoder(unsigned char temp) +{ + /* + [bit7-3] + FONT ROM Coding Setting + For specific GT serial Font ROM, the coding method must be set for decoding. + 00000b: GB2312 + 00001b: GB12345/GB18030 + 00010b: BIG5 + 00011b: UNICODE + 00100b: ASCII + 00101b: UNI-Japanese + 00110b: JIS0208 + 00111b: Latin/Greek/ Cyrillic / Arabic/Thai/Hebrew + 01000b: Korea + 10001b: ISO-8859-1 + 10010b: ISO-8859-2 + 10011b: ISO-8859-3 + 10100b: ISO-8859-4 + 10101b: ISO-8859-5 + 10110b: ISO-8859-6 + 10111b: ISO-8859-7 + 11000b: ISO-8859-8 + 11001b: ISO-8859-9 + 11010b: ISO-8859-10 + 11011b: ISO-8859-11 + 11100b: ISO-8859-12 + 11101b: ISO-8859-13 + 11110b: ISO-8859-14 + 11111b: ISO-8859-15 + + [bit1-0] + ASCII / Latin/Greek/ Cyrillic / Arabic + (ASCII) (Latin/Greek/Cyrillic) (Arabic) + 00b Normal Normal NA + 01b Arial Variable Width Presentation Forms-A + 10b Roman NA Presentation Forms-B + 11b Bold NA NA + */ + LCD_CmdWrite(0xCF); + LCD_DataWrite(temp); +} +//[D0h]========================================================================= +void Font_Line_Distance(unsigned char temp) +{ + /*[bit4-0] + Font Line Distance Setting + Setting the font character line distance when setting memory font + write cursor auto move. (Unit: pixel) + */ + LCD_CmdWrite(0xD0); + LCD_DataWrite(temp); +} +//[D1h]========================================================================= +void Set_Font_to_Font_Width(unsigned char temp) +{ + /*[bit5-0] + Font to Font Width Setting (Unit: pixel) + */ + LCD_CmdWrite(0xD1); + LCD_DataWrite(temp); +} +//[D2h]~[D4h]========================================================================= +void Foreground_RGB(unsigned char RED,unsigned char GREEN,unsigned char BLUE) +{ + /* + [D2h] Foreground Color - Red, for draw, text or color expansion + [D3h] Foreground Color - Green, for draw, text or color expansion + [D4h] Foreground Color - Blue, for draw, text or color expansion + */ + LCD_CmdWrite(0xD2); + LCD_DataWrite(RED); + LCD_CmdWrite(0xD3); + LCD_DataWrite(GREEN); + LCD_CmdWrite(0xD4); + LCD_DataWrite(BLUE); +} + +//Input data format:R3G3B2 +void Foreground_color_256(unsigned char temp) +{ + LCD_CmdWrite(0xD2); + LCD_DataWrite(temp); + LCD_CmdWrite(0xD3); + LCD_DataWrite(temp<<3); + LCD_CmdWrite(0xD4); + LCD_DataWrite(temp<<6); +} + +//Input data format:R5G6B5 +void Foreground_color_65k(unsigned short temp) +{ + LCD_CmdWrite(0xD2); + LCD_DataWrite(temp>>8); + LCD_CmdWrite(0xD3); + LCD_DataWrite(temp>>3); + LCD_CmdWrite(0xD4); + LCD_DataWrite(temp<<3); +} + +//Input data format:R8G8B8 +void Foreground_color_16M(unsigned long temp) +{ + LCD_CmdWrite(0xD2); + LCD_DataWrite(temp>>16); + LCD_CmdWrite(0xD3); + LCD_DataWrite(temp>>8); + LCD_CmdWrite(0xD4); + LCD_DataWrite(temp); +} + + + +//[D5h]~[D7h]========================================================================= +/* +[D5h] Background Color - Red, for Text or color expansion +[D6h] Background Color - Green, for Text or color expansion +[D7h] Background Color - Blue, for Text or color expansion +*/ +void Background_RGB(unsigned char RED,unsigned char GREEN,unsigned char BLUE) +{ + LCD_CmdWrite(0xD5); + LCD_DataWrite(RED); + LCD_CmdWrite(0xD6); + LCD_DataWrite(GREEN); + LCD_CmdWrite(0xD7); + LCD_DataWrite(BLUE); +} + +//Input data format:R3G3B2 +void Background_color_256(unsigned char temp) +{ + LCD_CmdWrite(0xD5); + LCD_DataWrite(temp); + LCD_CmdWrite(0xD6); + LCD_DataWrite(temp<<3); + LCD_CmdWrite(0xD7); + LCD_DataWrite(temp<<6); +} + +//Input data format:R5G6B6 +void Background_color_65k(unsigned short temp) +{ + LCD_CmdWrite(0xD5); + LCD_DataWrite(temp>>8); + LCD_CmdWrite(0xD6); + LCD_DataWrite(temp>>3); + LCD_CmdWrite(0xD7); + LCD_DataWrite(temp<<3); +} + +//Input data format:R8G8B8 +void Background_color_16M(unsigned long temp) +{ + LCD_CmdWrite(0xD5); + LCD_DataWrite(temp>>16); + LCD_CmdWrite(0xD6); + LCD_DataWrite(temp>>8); + LCD_CmdWrite(0xD7); + LCD_DataWrite(temp); +} + +//[DBh]~[DEh]========================================================================= +void CGRAM_Start_address(unsigned long Addr) +{ + /* + CGRAM START ADDRESS [31:0] + */ + LCD_CmdWrite(0xDB); + LCD_DataWrite(Addr); + LCD_CmdWrite(0xDC); + LCD_DataWrite(Addr>>8); + LCD_CmdWrite(0xDD); + LCD_DataWrite(Addr>>16); + LCD_CmdWrite(0xDE); + LCD_DataWrite(Addr>>24); +} + +//[DFh]========================================================================= +/* +[bit7] Enter Power saving state +0: Normal state. +1: Enter power saving state. +[bit1][bit0] Power saving Mode definition +00: NA +01: Standby Mode +10: Suspend Mode +11: Sleep Mode +*/ +void Power_Normal_Mode(void) +{ + LCD_CmdWrite(0xDF); + LCD_DataWrite(0x00); +} +void Power_Saving_Standby_Mode(void) +{ + LCD_CmdWrite(0xDF); + LCD_DataWrite(0x01); + LCD_CmdWrite(0xDF); + LCD_DataWrite(0x81); +} +void Power_Saving_Suspend_Mode(void) +{ + LCD_CmdWrite(0xDF); +// LCD_DataWrite(0x02); +// LCD_CmdWrite(0xDF); + LCD_DataWrite(0x82); +} +void Power_Saving_Sleep_Mode(void) +{ + LCD_CmdWrite(0xDF); +// LCD_DataWrite(0x03); +// LCD_CmdWrite(0xDF); + LCD_DataWrite(0x83); +} + + +//[E5h]~[E6h]========================================================================= +void LT768_I2CM_Clock_Prescale(unsigned short WX) +{ + /* + I2C Master Clock Pre-scale [7:0] + I2C Master Clock Pre-scale [15:8] + */ + LCD_CmdWrite(0xE5); + LCD_DataWrite(WX); + LCD_CmdWrite(0xE6); + LCD_DataWrite(WX>>8); +} +//[E7h]========================================================================= +void LT768_I2CM_Transmit_Data(unsigned char temp) +{ + /* + I2C Master Transmit[7:0] + */ + LCD_CmdWrite(0xE7); + LCD_DataWrite(temp); +} +//[E8h]========================================================================= +unsigned char LT768_I2CM_Receiver_Data(void) +{ + /* + I2C Master Receiver [7:0] + */ + unsigned char temp; + LCD_CmdWrite(0xE8); + temp=LCD_DataRead(); + return temp; +} +//[E9h]========================================================================= +/* +[bit7] START +Generate (repeated) start condition and be cleared by hardware automatically +Note : This bit is always read as 0. +[bit6] STOP +Generate stop condition and be cleared by hardware automatically +Note : This bit is always read as 0. +[bit5] +READ(READ and WRITE canˇt be used simultaneously) +Read form slave and be cleared by hardware automatically +Note : This bit is always read as 0. +[bit4] +WRITE(READ and WRITE canˇt be used simultaneously) +Write to slave and be cleared by hardware automatically +Note : This bit is always read as 0. +[bit3] ACKNOWLEDGE +When as a I2C master receiver +0 : Sent ACK. +1 : Sent NACK. +Note : This bit is always read as 0. +[bit0] Noise Filter +0 : Enable. +1 : Disable. +*/ + +#define Disable_I2CM_Noise_Filter + +void LT768_I2CM_Stop(void) +{ + LCD_CmdWrite(0xE9); +#ifdef Disable_I2CM_Noise_Filter + LCD_DataWrite(0x40); +#endif +#ifdef Enable_I2CM_Noise_Filter + LCD_DataWrite(0x41); +#endif +} +void LT768_I2CM_Read_With_Ack(void) +{ + LCD_CmdWrite(0xE9); +#ifdef Disable_I2CM_Noise_Filter + LCD_DataWrite(0x20); +#endif +#ifdef Enable_I2CM_Noise_Filter + LCD_DataWrite(0x21); +#endif +} + +void LT768_I2CM_Read_With_Nack(void) +{ + LCD_CmdWrite(0xE9); +#ifdef Disable_I2CM_Noise_Filter + LCD_DataWrite(0x68); +#endif +#ifdef Enable_I2CM_Noise_Filter + LCD_DataWrite(0x69); +#endif +} + +void LT768_I2CM_Write_With_Start(void) +{ + LCD_CmdWrite(0xE9); +#ifdef Disable_I2CM_Noise_Filter + LCD_DataWrite(0x90); +#endif +#ifdef Enable_I2CM_Noise_Filter + LCD_DataWrite(0x91); +#endif +} + +void LT768_I2CM_Write(void) +{ + LCD_CmdWrite(0xE9); +#ifdef Disable_I2CM_Noise_Filter + LCD_DataWrite(0x10); +#endif +#ifdef Enable_I2CM_Noise_Filter + LCD_DataWrite(0x11); +#endif +} + + + +//[EAh]========================================================================= +/* + 0=Ack + 1=Nack +*/ +unsigned char LT768_I2CM_Check_Slave_ACK(void) +{ + unsigned char temp; + /*[bit7] + Received acknowledge from slave + 0 : Acknowledge received. + 1 : No Acknowledge received. + */ + LCD_CmdWrite(0xEA); + temp=LCD_DataRead(); + + if((temp&0x80)==0x80) + { + return 1; + } + else + { + return 0; + } +} + + +/* + 0=Idle + 1=Busy +*/ +unsigned char LT768_I2CM_Bus_Busy(void) +{ + unsigned char temp; + /*[bit6] + I2C Bus is Busy + 0 : Idle. + 1 : Busy. + */ + LCD_CmdWrite(0xEA); + temp=LCD_DataRead(); + + if((temp&0x40)==0x40) + { + return 1; + } + else + { + return 0; + } +} + +/* + 0=Complete + 1=Transferring +*/ +unsigned char LT768_I2CM_transmit_Progress(void) +{ + unsigned char temp; + /*[bit6] + 0=Complete + 1=Transferring + */ + LCD_CmdWrite(0xEA); + temp=LCD_DataRead(); + + if((temp&0x02)==0x02) + { + return 1; + } + else + { + return 0; + } +} + +/* +0= Arbitration win +1= Arbitration lost +*/ +unsigned char LT768_I2CM_Arbitration(void) +{ + unsigned char temp; + /*[bit6] + I2C Bus is Busy + 0 : Idle. + 1 : Busy. + */ + LCD_CmdWrite(0xEA); + temp=LCD_DataRead(); + temp&=0x01; + return temp; +} + + +//[F0h]========================================================================= +void Set_GPIO_A_In_Out(unsigned char temp) +{ + /* + GPO-A_dir[7:0] : General Purpose I/O direction control. + 0: Output + 1: Input + */ + LCD_CmdWrite(0xF0); + LCD_DataWrite(temp); +} +//[F1h]========================================================================= +void Write_GPIO_A_7_0(unsigned char temp) +{ + /* + GPI-A[7:0] : General Purpose Input, share with DB[15:8] + GPO-A[7:0] : General Purpose Output, share with DB[15:8] + */ + LCD_CmdWrite(0xF1); + LCD_DataWrite(temp); +} +unsigned char Read_GPIO_A_7_0(void) +{ + /* + GPI-A[7:0] : General Purpose Input, share with DB[15:8] + GPO-A[7:0] : General Purpose Output, share with DB[15:8] + */ + unsigned char temp; + LCD_CmdWrite(0xF1); + temp=LCD_DataRead(); + return temp; +} +//[F2h]========================================================================= +void Write_GPIO_B_7_4(unsigned char temp) +{ + /* + GPI-B[7:0] : General Purpose Input ; share with {XKIN[3:0], XA0, XnWR, XnRD, XnCS} + GPO-B[7:4] : General Purpose Output ; share with XKOUT[3:0] ; + */ + LCD_CmdWrite(0xF2); + LCD_DataWrite(temp); +} +unsigned char Read_GPIO_B_7_0(void) +{ + /* + GPI-B[7:0] : General Purpose Input ; share with {XKIN[3:0], XA0, XnWR, XnRD, XnCS} + GPO-B[7:4] : General Purpose Output ; share with XKOUT[3:0] ; + */ + unsigned char temp; + LCD_CmdWrite(0xF2); + temp=LCD_DataRead(); + return temp; +} + +//[F3h]========================================================================= +void Set_GPIO_C_In_Out(unsigned char temp) +{ + /* + GPIO-C_dir[7:0] : General Purpose I/O direction control. + 0: Output + 1: Input + */ + LCD_CmdWrite(0xF3); + LCD_DataWrite(temp); +} +//[F4h]========================================================================= +void Write_GPIO_C_7_0(unsigned char temp) +{ + /* + GPIO-C[7:0] : General Purpose Input / Output + share with {XPWM0, XI2CSDA, XI2CSCL, XnSFCS1, XnSFCS0,XMISO, XMOSI, XSCLK} + */ + LCD_CmdWrite(0xF4); + LCD_DataWrite(temp); +} +unsigned char Read_GPIO_C_7_0(void) +{ + /* + GPIO-C[7:0] : General Purpose Input / Output + share with {XPWM0, XI2CSDA, XI2CSCL, XnSFCS1, XnSFCS0,XMISO, XMOSI, XSCLK} + */ + unsigned char temp; + LCD_CmdWrite(0xF4); + temp=LCD_DataRead(); + return temp; +} +//[F5h]========================================================================= +void Set_GPIO_D_In_Out(unsigned char temp) +{ + /* + GPIO-D_dir[7:0] : General Purpose I/O direction control. + 0: Output + 1: Input + */ + LCD_CmdWrite(0xF5); + LCD_DataWrite(temp); +} +//[F6h]========================================================================= +void Write_GPIO_D_7_0(unsigned char temp) +{ + /* + GPIO-D[7:0] : General Purpose Input/Output + */ + LCD_CmdWrite(0xF6); + LCD_DataWrite(temp); +} +unsigned char Read_GPIO_D_7_0(void) +{ + /* + GPIO-D[7:0] : General Purpose Input/Output + */ + unsigned char temp; + LCD_CmdWrite(0xF6); + temp=LCD_DataRead(); + return temp; +} +//[F7h]========================================================================= +void Set_GPIO_E_In_Out(unsigned char temp) +{ + /* + GPIO-E_dir[7:0] : General Purpose I/O direction control. + 0: Output + 1: Input + */ + LCD_CmdWrite(0xF7); + LCD_DataWrite(temp); +} +//[F8h]========================================================================= +void Write_GPIO_E_7_0(unsigned char temp) +{ + /* + GPIO-E[7:0] : General Purpose Input/Output. + share with {PDAT[23:19], PDAT[15:13]} + */ + LCD_CmdWrite(0xF8); + LCD_DataWrite(temp); +} +unsigned char Read_GPIO_E_7_0(void) +{ + /* + GPIO-E[7:0] : General Purpose Input/Output. + share with {PDAT[23:19], PDAT[15:13]} + */ + unsigned char temp; + LCD_CmdWrite(0xF8); + temp=LCD_DataRead(); + return temp; +} +//[F9h]========================================================================= +void Set_GPIO_F_In_Out(unsigned char temp) +{ + /* + GPIO-F_dir[7:0] : General Purpose I/O direction control. + 0: Output + 1: Input + */ + LCD_CmdWrite(0xF9); + LCD_DataWrite(temp); +} +//[FAh]========================================================================= +void Write_GPIO_F_7_0(unsigned char temp) +{ + /* + GPIO-F[7:0] : General Purpose Input/Output. + share with {XPDAT[12:10], XPDAT[7:3]} + */ + LCD_CmdWrite(0xFA); + LCD_DataWrite(temp); +} +unsigned char Read_GPIO_F_7_0(void) +{ + /* + GPIO-F[7:0] : General Purpose Input/Output. + share with {XPDAT[12:10], XPDAT[7:3]} + */ + unsigned char temp; + LCD_CmdWrite(0xFA); + temp=LCD_DataRead(); + return temp; +} + +//[FBh]========================================================================= + + +void Long_Key_enable(void) +{ + /* + Key-Scan Control Register 1 + [bit6] LongKey Enable Bit + 1 : Enable. Long key period is set by KSCR2 bit4-2. + 0 : Disable. + */ + unsigned char temp; + LCD_CmdWrite(0xFB); + temp=LCD_DataRead(); + temp |= cSetb6; + LCD_DataWrite(temp); +} + + +void Key_Scan_Freg(unsigned char setx) +{ + /*KF2-0: Key-Scan Frequency */ + unsigned char temp; + LCD_CmdWrite(0xFB); + temp = LCD_DataRead(); + temp &= 0xf0; + temp|= (setx&0x07); + LCD_DataWrite(temp); +} + + +//[FCh]========================================================================= + +void Key_Scan_Wakeup_Function_Enable(void) +{ + /* + Key-Scan Controller Register 2 + [bit7] + Key-Scan Wakeup Function Enable Bit + 0: Key-Scan Wakeup function is disabled. + 1: Key-Scan Wakeup function is enabled. + */ + unsigned char temp; + LCD_CmdWrite(0xFC); + temp=LCD_DataRead(); + temp |= cSetb7; + LCD_DataWrite(temp); +} + + +void Long_Key_Timing_Adjustment(unsigned char setx) +{ + /*Long Key Timing Adjustment*/ + unsigned char temp,temp1; + temp = setx & 0x1c; + LCD_CmdWrite(0xFC); + temp1 = LCD_DataRead(); + temp1|=temp; + LCD_DataWrite(temp1); +} + +unsigned char Numbers_of_Key_Hit(void) +{ + unsigned char temp; + LCD_CmdWrite(0xFC); + temp = LCD_DataRead(); //read key touch number + temp = temp & 0x03; // + return temp; +} + +//[FDh][FEh][FFh]========================================================================= +unsigned char Read_Key_Strobe_Data_0(void) +{ + /* + Key Strobe Data 0 + The corresponding key code 0 that is pressed. + */ + unsigned char temp; + LCD_CmdWrite(0xFD); + temp=LCD_DataRead(); + return temp; +} +unsigned char Read_Key_Strobe_Data_1(void) +{ + /* + Key Strobe Data 1 + The corresponding key code 1 that is pressed. + */ + unsigned char temp; + LCD_CmdWrite(0xFE); + temp=LCD_DataRead(); + return temp; +} +unsigned char Read_Key_Strobe_Data_2(void) +{ + /* + Key Strobe Data 2 + The corresponding key code 2 that is pressed. + */ + unsigned char temp; + LCD_CmdWrite(0xFF); + temp=LCD_DataRead(); + return temp; +} + +void Show_String(char *str) +{ + Text_Mode(); //文本模式 + LCD_CmdWrite(0x04); + + while(*str != '\0') + { + LCD_DataWrite(*str); + Check_Mem_WR_FIFO_not_Full(); + ++str; + } + + Check_2D_Busy(); + Graphic_Mode(); //back to graphic mode;图形模式 +} + + +void Show_picture(unsigned long numbers,const unsigned short *datap) +{ + unsigned long i; + LCD_CmdWrite(0x04); + + for(i=0; i5) + { + temp = temp / 1000000 + 1; + } + else + { + temp = temp / 1000000; + } + + lt768_sclk = temp; + temp = temp * 3; + lt768_mclk = temp; + lt768_cclk = temp; + + if(lt768_cclk > 100) + { + lt768_cclk = 100; + } + + if(lt768_mclk > 100) + { + lt768_mclk = 100; + } + + if(lt768_sclk > 65) + { + lt768_sclk = 65; + } + +#if XI_4M + lpllOD_sclk = 3; + lpllOD_cclk = 2; + lpllOD_mclk = 2; + lpllR_sclk = 2; + lpllR_cclk = 2; + lpllR_mclk = 2; + lpllN_mclk = lt768_mclk; + lpllN_cclk = lt768_cclk; + lpllN_sclk = 2*lt768_sclk; +#endif +#if XI_8M + lpllOD_sclk = 3; + lpllOD_cclk = 2; + lpllOD_mclk = 2; + lpllR_sclk = 2; + lpllR_cclk = 4; + lpllR_mclk = 4; + lpllN_mclk = lt768_mclk; + lpllN_cclk = lt768_cclk; + lpllN_sclk = lt768_sclk; +#endif +#if XI_10M + lpllOD_sclk = 3; + lpllOD_cclk = 2; + lpllOD_mclk = 2; + lpllR_sclk = 5; + lpllR_cclk = 5; + lpllR_mclk = 5; + lpllN_mclk = lt768_mclk; + lpllN_cclk = lt768_cclk; + lpllN_sclk = 2*lt768_sclk; +#endif +#if XI_12M + lpllOD_sclk = 3; + lpllOD_cclk = 2; + lpllOD_mclk = 2; + lpllR_sclk = 3; + lpllR_cclk = 6; + lpllR_mclk = 6; + lpllN_mclk = lt768_mclk; + lpllN_cclk = lt768_cclk; + lpllN_sclk = lt768_sclk; +#endif + LCD_CmdWrite(0x05); + LCD_DataWrite((lpllOD_sclk<<6) | (lpllR_sclk<<1) | ((lpllN_sclk>>8)&0x1)); + LCD_CmdWrite(0x07); + LCD_DataWrite((lpllOD_mclk<<6) | (lpllR_mclk<<1) | ((lpllN_mclk>>8)&0x1)); + LCD_CmdWrite(0x09); + LCD_DataWrite((lpllOD_cclk<<6) | (lpllR_cclk<<1) | ((lpllN_cclk>>8)&0x1)); + LCD_CmdWrite(0x06); + LCD_DataWrite(lpllN_sclk); + LCD_CmdWrite(0x08); + LCD_DataWrite(lpllN_mclk); + LCD_CmdWrite(0x0a); + LCD_DataWrite(lpllN_cclk); + LCD_CmdWrite(0x00); + up_udelay(1); + LCD_DataWrite(0x80); + up_mdelay(1); +} + +void lt768_sdram_init(uint8_t mclk) +{ + uint16_t sdram_itv; + LCD_RegisterWrite(0xe0,0x29); + LCD_RegisterWrite(0xe1,0x03); //CAS:2=0x02?CAS:3=0x03 + sdram_itv = (64000000 / 8192) / (1000 / mclk) ; + sdram_itv-=2; + LCD_RegisterWrite(0xe2,sdram_itv); + LCD_RegisterWrite(0xe3,sdram_itv >>8); + LCD_RegisterWrite(0xe4,0x01); +// Check_SDRAM_Ready(); + up_mdelay(1); +} + +void lt768_set_panel(void) +{ + //**[01h]**// + TFT_16bit(); + //TFT_18bit(); + //TFT_24bit(); +#if STM32_FSMC_8 + Host_Bus_8bit(); //主机总线8bit +#else + Host_Bus_16bit(); //主机总线16bit +#endif + //**[02h]**// + RGB_16b_16bpp(); + //RGB_16b_24bpp_mode1(); + MemWrite_Left_Right_Top_Down(); + //MemWrite_Down_Top_Left_Right(); + //**[03h]**// + Graphic_Mode(); + Memory_Select_SDRAM(); +// PCLK_Falling(); //REG[12h]:下降沿 + PCLK_Rising(); + VSCAN_T_to_B(); //REG[12h]:从上到下 + //VSCAN_B_to_T(); //从下到上 + PDATA_Set_RGB(); //REG[12h]:Select RGB output + //PDATA_Set_RBG(); + //PDATA_Set_GRB(); + //PDATA_Set_GBR(); + //PDATA_Set_BRG(); + //PDATA_Set_BGR(); + HSYNC_Low_Active(); //REG[13h]: + //HSYNC_High_Active(); + VSYNC_Low_Active(); //REG[13h]: + //VSYNC_High_Active(); + DE_High_Active(); //REG[13h]: + //DE_Low_Active(); + LCD_HorizontalWidth_VerticalHeight(LCD_XSIZE_TFT,LCD_YSIZE_TFT); + LCD_Horizontal_Non_Display(LCD_HBPD); + LCD_HSYNC_Start_Position(LCD_HFPD); + LCD_HSYNC_Pulse_Width(LCD_HSPW); + LCD_Vertical_Non_Display(LCD_VBPD); + LCD_VSYNC_Start_Position(LCD_VFPD); + LCD_VSYNC_Pulse_Width(LCD_VSPW); + Memory_XY_Mode(); //Block mode (X-Y coordination addressing);块模式 + Memory_16bpp_Mode(); +} + +void lt768_init(void) +{ + lt768_hw_reset(); + //delay for LT768 power on + up_mdelay(100); + + // check reset ok? + lt768_sys_check(); + + //Initial_Display_test and set SW2 pin2 = 1 + while(LCD_StatusRead() & 0x02); + + lt768_pll_init(); + lt768_sdram_init(lt768_mclk); + lt768_set_panel(); +} + +/*----------------------------------------------------------------------------*/ + +void MPU8_8bpp_Memory_Write +( + uint16_t x // x坐标 + ,uint16_t y // y坐标 + ,uint16_t w // 宽度 + ,uint16_t h // 高度 + ,const uint8_t *data // 数据首地址 +) +{ + uint16_t i,j; + Graphic_Mode(); + Active_Window_XY(x,y); + Active_Window_WH(w,h); + Goto_Pixel_XY(x,y); + LCD_CmdWrite(0x04); + + for(i=0; i< h; i++) + { + for(j=0; j< w; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); +} + + +void MPU8_16bpp_Memory_Write +( + uint16_t x // x坐标 + ,uint16_t y // y坐标 + ,uint16_t w // 宽度 + ,uint16_t h // 高度 + ,const uint8_t *data // 数据首地址 +) +{ + uint16_t i,j; + Graphic_Mode(); + Active_Window_XY(x,y); + Active_Window_WH(w,h); + Goto_Pixel_XY(x,y); + LCD_CmdWrite(0x04); + + for(i=0; i< h; i++) + { + for(j=0; j< w; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(*data); + data++; + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); +} + + +void MPU8_24bpp_Memory_Write +( + uint16_t x // x坐标 + ,uint16_t y // y坐标 + ,uint16_t w // 宽度 + ,uint16_t h // 高度 + ,const uint8_t *data // 数据首地址 +) +{ + uint16_t i,j; + Graphic_Mode(); + Active_Window_XY(x,y); + Active_Window_WH(w,h); + Goto_Pixel_XY(x,y); + LCD_CmdWrite(0x04); + + for(i=0; i< h; i++) + { + for(j=0; j< w; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(*data); + data++; + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(*data); + data++; + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); +} + + + +void MPuint16_t_16bpp_Memory_Write +( + uint16_t x // x坐标 + ,uint16_t y // y坐标 + ,uint16_t w // 宽度 + ,uint16_t h // 高度 + ,const uint16_t *data // 数据首地址 +) +{ + uint16_t i,j; + Graphic_Mode(); + Active_Window_XY(x,y); + Active_Window_WH(w,h); + Goto_Pixel_XY(x,y); + LCD_CmdWrite(0x04); + + for(i=0; i< h; i++) + { + for(j=0; j< w; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); +} + +void MPuint16_t_24bpp_Mode1_Memory_Write +( + uint16_t x // x坐标 + ,uint16_t y // y坐标 + ,uint16_t w // 宽度 + ,uint16_t h // 高度 + ,const uint16_t *data // 数据首地址 +) +{ + uint16_t i,j; + Graphic_Mode(); + Active_Window_XY(x,y); + Active_Window_WH(w,h); + Goto_Pixel_XY(x,y); + LCD_CmdWrite(0x04); + + for(i=0; i< h; i++) + { + for(j=0; j< w/2; j++) + { + LCD_DataWrite_Pixel(*data); + Check_Mem_WR_FIFO_not_Full(); + data++; + LCD_DataWrite_Pixel(*data); + Check_Mem_WR_FIFO_not_Full(); + data++; + LCD_DataWrite_Pixel(*data); + Check_Mem_WR_FIFO_not_Full(); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); +} + + +void MPuint16_t_24bpp_Mode2_Memory_Write +( + uint16_t x // x坐标 + ,uint16_t y // y坐标 + ,uint16_t w // 宽度 + ,uint16_t h // 高度 + ,const uint16_t *data // 数据首地址 +) +{ + uint16_t i,j; + Graphic_Mode(); + Active_Window_XY(x,y); + Active_Window_WH(w,h); + Goto_Pixel_XY(x,y); + LCD_CmdWrite(0x04); + + for(i=0; i< h; i++) + { + for(j=0; j< w; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel(*data); + data++; + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); +} +/*----------------------------------------------------------------------------*/ + +//------------------------------------- 线段 ----------------------------------------- +void LT768_DrawLine +( + uint16_t X1 // X1坐标 + ,uint16_t Y1 // Y1坐标 + ,uint16_t X2 // X2坐标 + ,uint16_t Y2 // Y2坐标 + ,unsigned long LineColor // 线段颜色 +) +{ + Foreground_color_65k(LineColor); + Line_Start_XY(X1,Y1); + Line_End_XY(X2,Y2); + Start_Line(); + Check_2D_Busy(); +} + +void LT768_DrawLine_Width +( + uint16_t X1 // X1坐标 + ,uint16_t Y1 // Y1坐标 + ,uint16_t X2 // X2坐标 + ,uint16_t Y2 // Y2坐标 + ,unsigned long LineColor // 线段颜色 + ,uint16_t Width // 线段宽度 +) +{ + uint16_t i = 0; + signed short x = 0, y = 0; + double temp = 0; + x = X2 - X1; + y = Y2 - Y1; + + if(x == 0) + { + temp = 2; + } + else + { + temp = -((double)y/(double)x); + } + + if(temp>=-1&&temp<=1) + { + while(Width--) + { + LT768_DrawLine(X1,Y1+i,X2,Y2+i,LineColor); + i++; + } + } + else + { + while(Width--) + { + LT768_DrawLine(X1+i,Y1,X2+i,Y2,LineColor); + i++; + } + } +} + +//------------------------------------- 圆 ----------------------------------------- +void LT768_DrawCircle +( + uint16_t XCenter // 圆心X位置 + ,uint16_t YCenter // 圆心Y位置 + ,uint16_t R // 半径 + ,unsigned long CircleColor // 画线颜色 +) +{ + Foreground_color_65k(CircleColor); + Circle_Center_XY(XCenter,YCenter); + Circle_Radius_R(R); + Start_Circle_or_Ellipse(); + Check_2D_Busy(); +} + +void LT768_DrawCircle_Fill +( + uint16_t XCenter // 圆心X位置 + ,uint16_t YCenter // 圆心Y位置 + ,uint16_t R // 半径 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Circle_Center_XY(XCenter,YCenter); + Circle_Radius_R(R); + Start_Circle_or_Ellipse_Fill(); + Check_2D_Busy(); +} + +void LT768_DrawCircle_Width +( + uint16_t XCenter // 圆心X位置 + ,uint16_t YCenter // 圆心Y位置 + ,uint16_t R // 半径 + ,unsigned long CircleColor // 画线颜色 + ,unsigned long ForegroundColor // 背景颜色 + ,uint16_t Width // 线宽 +) +{ + LT768_DrawCircle_Fill(XCenter,YCenter,R+Width,CircleColor); + LT768_DrawCircle_Fill(XCenter,YCenter,R,ForegroundColor); +} + +//------------------------------------- 椭圆 ----------------------------------------- +void LT768_DrawEllipse +( + uint16_t XCenter // 椭圆心X位置 + ,uint16_t YCenter // 椭圆心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long EllipseColor // 画线颜色 +) +{ + Foreground_color_65k(EllipseColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Circle_or_Ellipse(); + Check_2D_Busy(); +} + +void LT768_DrawEllipse_Fill +( + uint16_t XCenter // 椭圆心X位置 + ,uint16_t YCenter // 椭圆心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Circle_or_Ellipse_Fill(); + Check_2D_Busy(); +} + +void LT768_DrawEllipse_Width +( + uint16_t XCenter // 椭圆心X位置 + ,uint16_t YCenter // 椭圆心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long EllipseColor // 画线颜色 + ,unsigned long ForegroundColor // 背景颜色 + ,uint16_t Width // 线宽 +) +{ + LT768_DrawEllipse_Fill(XCenter,YCenter,X_R+Width,Y_R+Width,EllipseColor); + LT768_DrawEllipse_Fill(XCenter,YCenter,X_R,Y_R,ForegroundColor); +} + +//------------------------------------- 矩形 ----------------------------------------- +void LT768_DrawSquare +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,unsigned long SquareColor // 画线颜色 +) +{ + Foreground_color_65k(SquareColor); + Square_Start_XY(X1,Y1); + Square_End_XY(X2,Y2); + Start_Square(); + Check_2D_Busy(); +} + +void LT768_DrawSquare_Fill +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Square_Start_XY(X1,Y1); + Square_End_XY(X2,Y2); + Start_Square_Fill(); + Check_2D_Busy(); +} + +void LT768_DrawSquare_Width +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,unsigned long SquareColor // 画线颜色 + ,unsigned long ForegroundColor // 背景颜色 + ,uint16_t Width // 线宽 +) +{ + LT768_DrawSquare_Fill(X1-Width,Y1-Width,X2+Width,Y2+Width,SquareColor); + LT768_DrawSquare_Fill(X1,Y1,X2,Y2,ForegroundColor); +} + +//------------------------------------- 圆角矩形 ----------------------------------------- +void LT768_DrawCircleSquare +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CircleSquareColor // 画线颜色 +) +{ + Foreground_color_65k(CircleSquareColor); + Square_Start_XY(X1,Y1); + Square_End_XY(X2,Y2); + Circle_Square_Radius_RxRy(X_R,Y_R); + Start_Circle_Square(); + Check_2D_Busy(); +} + +void LT768_DrawCircleSquare_Fill +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long ForegroundColor // 画线颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Square_Start_XY(X1,Y1); + Square_End_XY(X2,Y2); + Circle_Square_Radius_RxRy(X_R,Y_R); + Start_Circle_Square_Fill(); + Check_2D_Busy(); +} + +void LT768_DrawCircleSquare_Width +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CircleSquareColor // 画线颜色 + ,unsigned long ForegroundColor // 画线颜色 + ,uint16_t Width // 宽度 +) +{ + LT768_DrawCircleSquare_Fill(X1-Width,Y1-Width,X2+Width,Y2+Width,X_R,Y_R,CircleSquareColor); + LT768_DrawCircleSquare_Fill(X1,Y1,X2,Y2,X_R,Y_R,ForegroundColor); +} + +//------------------------------------- 三角形 ----------------------------------------- +void LT768_DrawTriangle +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,unsigned long TriangleColor // 画线颜色 +) +{ + Foreground_color_65k(TriangleColor); + Triangle_Point1_XY(X1,Y1); + Triangle_Point2_XY(X2,Y2); + Triangle_Point3_XY(X3,Y3); + Start_Triangle(); + Check_2D_Busy(); +} + + + +void LT768_DrawTriangle_Fill +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,unsigned long ForegroundColor // 画线颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Triangle_Point1_XY(X1,Y1); + Triangle_Point2_XY(X2,Y2); + Triangle_Point3_XY(X3,Y3); + Start_Triangle_Fill(); + Check_2D_Busy(); +} + +void LT768_DrawTriangle_Frame +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,unsigned long TriangleColor // 画线颜色 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + LT768_DrawTriangle_Fill(X1,Y1,X2,Y2,X3,Y3,ForegroundColor); + LT768_DrawTriangle(X1,Y1,X2,Y2,X3,Y3,TriangleColor); +} + + + +//------------------------------------- 曲线 ----------------------------------------- +void LT768_DrawLeftUpCurve +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CurveColor // 画线颜色 +) +{ + Foreground_color_65k(CurveColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Left_Up_Curve(); + Check_2D_Busy(); +} + + +void LT768_DrawLeftDownCurve +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CurveColor // 画线颜色 +) +{ + Foreground_color_65k(CurveColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Left_Down_Curve(); + Check_2D_Busy(); +} + + +void LT768_DrawRightUpCurve +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CurveColor // 画线颜色 +) +{ + Foreground_color_65k(CurveColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Right_Up_Curve(); + Check_2D_Busy(); +} + + +void LT768_DrawRightDownCurve +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CurveColor // 画线颜色 +) +{ + Foreground_color_65k(CurveColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Right_Down_Curve(); + Check_2D_Busy(); +} + + +void LT768_SelectDrawCurve +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CurveColor // 画线颜色 + ,uint16_t Dir // 方向 +) +{ + switch(Dir) + { + case 0: + LT768_DrawLeftDownCurve(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + case 1: + LT768_DrawLeftUpCurve(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + case 2: + LT768_DrawRightUpCurve(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + case 3: + LT768_DrawRightDownCurve(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + default: + break; + } +} + + +//------------------------------------- 1/4实心椭圆 ----------------------------------------- +void LT768_DrawLeftUpCurve_Fill +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Left_Up_Curve_Fill(); + Check_2D_Busy(); +} + + +void LT768_DrawLeftDownCurve_Fill +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Left_Down_Curve_Fill(); + Check_2D_Busy(); +} + + +void LT768_DrawRightUpCurve_Fill +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Right_Up_Curve_Fill(); + Check_2D_Busy(); +} + + +void LT768_DrawRightDownCurve_Fill +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Ellipse_Center_XY(XCenter,YCenter); + Ellipse_Radius_RxRy(X_R,Y_R); + Start_Right_Down_Curve_Fill(); + Check_2D_Busy(); +} + + +void LT768_SelectDrawCurve_Fill +( + uint16_t XCenter // 曲心X位置 + ,uint16_t YCenter // 曲心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,unsigned long CurveColor // 画线颜色 + ,uint16_t Dir // 方向 +) +{ + switch(Dir) + { + case 0: + LT768_DrawLeftDownCurve_Fill(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + case 1: + LT768_DrawLeftUpCurve_Fill(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + case 2: + LT768_DrawRightUpCurve_Fill(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + case 3: + LT768_DrawRightDownCurve_Fill(XCenter,YCenter,X_R,Y_R,CurveColor); + break; + + default: + break; + } +} + + + +//------------------------------------- 四边形 ----------------------------------------- + +void LT768_DrawQuadrilateral +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,uint16_t X4 // X4位置 + ,uint16_t Y4 // Y4位置 + ,unsigned long ForegroundColor // 画线颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Triangle_Point1_XY(X1,Y1); + Triangle_Point2_XY(X2,Y2); + Triangle_Point3_XY(X3,Y3); + Ellipse_Radius_RxRy(X4,Y4); + LCD_CmdWrite(0x67); + LCD_DataWrite(0x8d); + Check_Busy_Draw(); + Check_2D_Busy(); +} + + +void LT768_DrawQuadrilateral_Fill +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,uint16_t X4 // X4位置 + ,uint16_t Y4 // Y4位置 + ,unsigned long ForegroundColor // 画线颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Triangle_Point1_XY(X1,Y1); + Triangle_Point2_XY(X2,Y2); + Triangle_Point3_XY(X3,Y3); + Ellipse_Radius_RxRy(X4,Y4); + LCD_CmdWrite(0x67); + LCD_DataWrite(0xa7); + Check_Busy_Draw(); + Check_2D_Busy(); +} + + + +//------------------------------------- 五边形 ----------------------------------------- + +void LT768_DrawPentagon +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,uint16_t X4 // X4位置 + ,uint16_t Y4 // Y4位置 + ,uint16_t X5 // X5位置 + ,uint16_t Y5 // Y5位置 + ,unsigned long ForegroundColor // 画线颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Triangle_Point1_XY(X1,Y1); + Triangle_Point2_XY(X2,Y2); + Triangle_Point3_XY(X3,Y3); + Ellipse_Radius_RxRy(X4,Y4); + Ellipse_Center_XY(X5,Y5); + LCD_CmdWrite(0x67); + LCD_DataWrite(0x8F); + Check_Busy_Draw(); + Check_2D_Busy(); +} + + +void LT768_DrawPentagon_Fill +( + uint16_t X1 // X1位置 + ,uint16_t Y1 // Y1位置 + ,uint16_t X2 // X2位置 + ,uint16_t Y2 // Y2位置 + ,uint16_t X3 // X3位置 + ,uint16_t Y3 // Y3位置 + ,uint16_t X4 // X4位置 + ,uint16_t Y4 // Y4位置 + ,uint16_t X5 // X5位置 + ,uint16_t Y5 // Y5位置 + ,unsigned long ForegroundColor // 画线颜色 +) +{ + Foreground_color_65k(ForegroundColor); + Triangle_Point1_XY(X1,Y1); + Triangle_Point2_XY(X2,Y2); + Triangle_Point3_XY(X3,Y3); + Ellipse_Radius_RxRy(X4,Y4); + Ellipse_Center_XY(X5,Y5); + LCD_CmdWrite(0x67); + LCD_DataWrite(0xa9); + Check_Busy_Draw(); + Check_2D_Busy(); +} + + +//------------------------------------- 圆柱 ----------------------------------------- +uint8_t LT768_DrawCylinder +( + uint16_t XCenter // 椭圆心X位置 + ,uint16_t YCenter // 椭圆心Y位置 + ,uint16_t X_R // 宽半径 + ,uint16_t Y_R // 长半径 + ,uint16_t H // 高度 + ,unsigned long CylinderColor // 画线颜色 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + if(YCenter < H) + { + return 1; + } + + //底面椭圆 + LT768_DrawEllipse_Fill(XCenter,YCenter,X_R,Y_R,ForegroundColor); + LT768_DrawEllipse(XCenter,YCenter,X_R,Y_R,CylinderColor); + //中间矩形 + LT768_DrawSquare_Fill(XCenter-X_R,YCenter-H,XCenter+X_R,YCenter,ForegroundColor); + //顶面椭圆 + LT768_DrawEllipse_Fill(XCenter,YCenter-H,X_R,Y_R,ForegroundColor); + LT768_DrawEllipse(XCenter,YCenter-H,X_R,Y_R,CylinderColor); + LT768_DrawLine(XCenter-X_R,YCenter,XCenter-X_R,YCenter-H,CylinderColor); + LT768_DrawLine(XCenter+X_R,YCenter,XCenter+X_R,YCenter-H,CylinderColor); + return 0; +} + + +//------------------------------------- 四棱柱 ----------------------------------------- +void LT768_DrawQuadrangular +( + uint16_t X1 + ,uint16_t Y1 + ,uint16_t X2 + ,uint16_t Y2 + ,uint16_t X3 + ,uint16_t Y3 + ,uint16_t X4 + ,uint16_t Y4 + ,uint16_t X5 + ,uint16_t Y5 + ,uint16_t X6 + ,uint16_t Y6 + ,unsigned long QuadrangularColor // 画线颜色 + ,unsigned long ForegroundColor // 背景颜色 +) +{ + LT768_DrawSquare_Fill(X1,Y1,X5,Y5,ForegroundColor); + LT768_DrawSquare(X1,Y1,X5,Y5,QuadrangularColor); + LT768_DrawQuadrilateral_Fill(X1,Y1,X2,Y2,X3,Y3,X4,Y4,ForegroundColor); + LT768_DrawQuadrilateral(X1,Y1,X2,Y2,X3,Y3,X4,Y4,QuadrangularColor); + LT768_DrawQuadrilateral_Fill(X3,Y3,X4,Y4,X5,Y5,X6,Y6,ForegroundColor); + LT768_DrawQuadrilateral(X3,Y3,X4,Y4,X5,Y5,X6,Y6,QuadrangularColor); +} + + +//--------------------------------------表格------------------------------------ +void LT768_MakeTable +( + uint16_t X1, // 起始位置X1 + uint16_t Y1, // 起始位置X2 + uint16_t W, // 宽度 + uint16_t H, // 高度 + uint16_t Line, // 行数 + uint16_t Row, // 列数 + unsigned long TableColor, // 线框颜色C1 + unsigned long ItemColor, // 项目拦背景色C2 + unsigned long ForegroundColor, // 内部窗口背景色C3 + uint16_t width1, // 内框宽度 + uint16_t width2, // 外框宽度 + uint8_t mode // 0：项目栏纵向 1：项目栏横向 +) +{ + uint16_t i = 0; + uint16_t x2,y2; + x2 = X1 + W * Row; + y2 = Y1 + H * Line; + LT768_DrawSquare_Width(X1,Y1,x2,y2,TableColor,ForegroundColor,width2); + + if(mode == 0) + { + LT768_DrawSquare_Fill(X1,Y1,X1+W,y2,ItemColor); + } + else if(mode == 1) + { + LT768_DrawSquare_Fill(X1,Y1,x2,Y1+H,ItemColor); + } + + for(i = 0 ; i < Line ; i++) + { + LT768_DrawLine_Width(X1,Y1+i*H,x2,Y1+i*H,TableColor,width1); + } + + for(i = 0 ; i < Row ; i++) + { + LT768_DrawLine_Width(X1+i*W,Y1,X1+i*W,y2,TableColor,width1); + } +} + +/*----------------------------------------------------------------------------*/ + +void LT768_Color_Bar_ON(void) +{ + Color_Bar_ON(); +} + +void LT768_Color_Bar_OFF(void) +{ + Color_Bar_OFF(); +} + +/*----------------------------------------------------------------------------*/ + +/*--Flash-->DMA-->SDRAM--*/ +/*address：24bit or 32bit*/ + +void LT768_DMA_24bit_Linear +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long flash_addr // 要从flash读取数据的起始地址 + ,unsigned long memory_addr // 数据要传输到SDRAM的起始地址 + ,unsigned long data_num // 传输的数据量 +) +{ + Enable_SFlash_SPI(); // 使能SPI功能 + + if(SCS == 0) + { + Select_SFI_0(); // 选择外挂的SPI0 + } + + if(SCS == 1) + { + Select_SFI_1(); // 选择外挂的SPI1 + } + + Memory_Linear_Mode(); + Select_SFI_DMA_Mode(); // 设置SPI的DMA模式 + SPI_Clock_Period(Clk); // SPI速率 + SFI_DMA_Destination_Start_Address(memory_addr); // 指定的内存的开始地址 + SFI_DMA_Transfer_Number(data_num); // DMA传输的数量 + SFI_DMA_Source_Start_Address(flash_addr); // flash地址 + Check_Busy_SFI_DMA(); + Start_SFI_DMA(); + Check_Busy_SFI_DMA(); + Memory_XY_Mode(); +} + +void LT768_DMA_32bit_Linear +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long flash_addr // 要从flash读取数据的起始地址 + ,unsigned long memory_addr // 数据要传输到SDRAM的起始地址 + ,unsigned long data_num // 传输的数据量 +) +{ + Enable_SFlash_SPI(); // 使能SPI功能 + + if(SCS == 0) + { + Select_SFI_0(); // 选择外挂的SPI0 + } + + if(SCS == 1) + { + Select_SFI_1(); // 选择外挂的SPI1 + } + + Memory_Linear_Mode(); + Select_SFI_DMA_Mode(); // 设置SPI的DMA模式 + Select_SFI_32bit_Address(); + SPI_Clock_Period(Clk); // SPI速率 + SFI_DMA_Destination_Start_Address(memory_addr); // 指定的内存的开始地址 + SFI_DMA_Transfer_Number(data_num); // DMA传输的数量 + SFI_DMA_Source_Start_Address(flash_addr); // flash地址 + Check_Busy_SFI_DMA(); + Start_SFI_DMA(); + Check_Busy_SFI_DMA(); + Memory_XY_Mode(); +} + +void LT768_DMA_24bit_Block +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,uint16_t X1 // 传输到内存X1的位置 + ,uint16_t Y1 // 传输到内存Y1的位置 + ,uint16_t X_W // DMA传输数据的宽度 + ,uint16_t Y_H // DMA传输数据的高度 + ,uint16_t P_W // 图片的宽度 + ,unsigned long Addr // Flash的地址 +) +{ + Enable_SFlash_SPI(); // 使能SPI功能 + + if(SCS == 0) + { + Select_SFI_0(); // 选择外挂的SPI0 + } + + if(SCS == 1) + { + Select_SFI_1(); // 选择外挂的SPI1 + } + + Select_SFI_DMA_Mode(); // 设置SPI的DMA模式 + SPI_Clock_Period(Clk); // 设置SPI的分频系数 + Goto_Pixel_XY(X1,Y1); // 在图形模式中设置内存的位置 + SFI_DMA_Destination_Upper_Left_Corner(X1,Y1); // DMA传输的目的地（内存的位置） + SFI_DMA_Transfer_Width_Height(X_W,Y_H); // 设置块数据的宽度和高度 + SFI_DMA_Source_Width(P_W); // 设置源数据的宽度 + SFI_DMA_Source_Start_Address(Addr); // 设置源数据在Flash的地址 + Start_SFI_DMA(); // 开始DMA传输 + Check_Busy_SFI_DMA(); // 检测DMA是否传输完成 +} + + + +void LT768_DMA_32bit_Block +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,uint16_t X1 // 内存X1的位置 + ,uint16_t Y1 // 内存Y1的位置 + ,uint16_t X_W // DMA传输数据的宽度 + ,uint16_t Y_H // DMA传输数据的高度 + ,uint16_t P_W // 图片的宽度 + ,unsigned long Addr // Flash的地址 +) +{ + Enable_SFlash_SPI(); + + if(SCS == 0) + { + Select_SFI_0(); + } + + if(SCS == 1) + { + Select_SFI_1(); + } + + Select_SFI_DMA_Mode(); + SPI_Clock_Period(Clk); + Select_SFI_32bit_Address(); + Goto_Pixel_XY(X1,Y1); + SFI_DMA_Destination_Upper_Left_Corner(X1,Y1); + SFI_DMA_Transfer_Width_Height(X_W,Y_H); + SFI_DMA_Source_Width(P_W); + SFI_DMA_Source_Start_Address(Addr); + Start_SFI_DMA(); + Check_Busy_SFI_DMA(); + Select_SFI_24bit_Address(); +} + +/*----------------------------------------------------------------------------*/ +/* 选择内部集成字库初始化 */ +void LT768_Select_Internal_Font_Init +( + uint8_t Size // 设置字体大小 16：16*16 24:24*24 32:32*32 + ,uint8_t XxN // 字体的宽度放大倍数：1~4 + ,uint8_t YxN // 字体的高度放大倍数：1~4 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint8_t Alignment // 0：不字体不对齐 1：字体对齐 +) +{ + if(Size==16) + { + Font_Select_8x16_16x16(); + } + + if(Size==24) + { + Font_Select_12x24_24x24(); + } + + if(Size==32) + { + Font_Select_16x32_32x32(); + } + + //(*) + if(XxN==1) + { + Font_Width_X1(); + } + + if(XxN==2) + { + Font_Width_X2(); + } + + if(XxN==3) + { + Font_Width_X3(); + } + + if(XxN==4) + { + Font_Width_X4(); + } + + //(*) + if(YxN==1) + { + Font_Height_X1(); + } + + if(YxN==2) + { + Font_Height_X2(); + } + + if(YxN==3) + { + Font_Height_X3(); + } + + if(YxN==4) + { + Font_Height_X4(); + } + + //(*) + if(ChromaKey==0) + { + Font_Background_select_Color(); + } + + if(ChromaKey==1) + { + Font_Background_select_Transparency(); + } + + //(*) + if(Alignment==0) + { + Disable_Font_Alignment(); + } + + if(Alignment==1) + { + Enable_Font_Alignment(); + } +} + + +/* 显示内部集成字体 */ +void LT768_Print_Internal_Font_String +( + uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,char *c // 数据缓冲的首地址 +) +{ + Text_Mode(); + CGROM_Select_Internal_CGROM(); + Foreground_color_65k(FontColor); + Background_color_65k(BackGroundColor); + Goto_Text_XY(x,y); + Show_String(c); +} + + +/* 选择外部集成字库初始化 */ +void LT768_Select_Outside_Font_Init +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 源地址(Flash) + ,unsigned long MemoryAddr // 目的地址(SDRAM) + ,unsigned long Num // 字库的数据量大小 + ,uint8_t Size // 设置字体大小 16：16*16 24:24*24 32:32*32 + ,uint8_t XxN // 字体的宽度放大倍数：1~4 + ,uint8_t YxN // 字体的高度放大倍数：1~4 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint8_t Alignment // 0：不字体不对齐 1：字体对齐 +) +{ + if(Size==16) + { + Font_Select_8x16_16x16(); + } + + if(Size==24) + { + Font_Select_12x24_24x24(); + } + + if(Size==32) + { + Font_Select_16x32_32x32(); + } + + //(*) + if(XxN==1) + { + Font_Width_X1(); + } + + if(XxN==2) + { + Font_Width_X2(); + } + + if(XxN==3) + { + Font_Width_X3(); + } + + if(XxN==4) + { + Font_Width_X4(); + } + + //(*) + if(YxN==1) + { + Font_Height_X1(); + } + + if(YxN==2) + { + Font_Height_X2(); + } + + if(YxN==3) + { + Font_Height_X3(); + } + + if(YxN==4) + { + Font_Height_X4(); + } + + //(*) + if(ChromaKey==0) + { + Font_Background_select_Color(); + } + + if(ChromaKey==1) + { + Font_Background_select_Transparency(); + } + + //(*) + if(Alignment==0) + { + Disable_Font_Alignment(); + } + + if(Alignment==1) + { + Enable_Font_Alignment(); + } + + LT768_DMA_24bit_Linear(SCS,Clk,FlashAddr,MemoryAddr,Num); + CGRAM_Start_address(MemoryAddr); +} + +/* 显示外部及内部集成字体 */ +void LT768_Print_Outside_Font_String +( + uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + Text_Mode(); + Font_Select_UserDefine_Mode(); + Foreground_color_65k(FontColor); + Background_color_65k(BackGroundColor); + Goto_Text_XY(x,y); + + while(c[i] != '\0') + { + if(c[i] < 0xa1) + { + CGROM_Select_Internal_CGROM(); // 内部CGROM为字符来源 + LCD_CmdWrite(0x04); + LCD_DataWrite(c[i]); + Check_Mem_WR_FIFO_not_Full(); + i += 1; + } + else + { + Font_Select_UserDefine_Mode(); // 自定义字库 + LCD_CmdWrite(0x04); + temp_H = ((c[i] - 0xa1) & 0x00ff) * 94; + temp_L = c[i+1] - 0xa1; + temp = temp_H + temp_L + 0x8000; + LCD_DataWrite((temp>>8)&0xff); + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(temp&0xff); + Check_Mem_WR_FIFO_not_Full(); + i += 2; + } + } + + Check_2D_Busy(); + Graphic_Mode(); //back to graphic mode;图形模式 +} + +/* 显示外部GBK及内部集成字体 */ +void LT768_Print_Outside_Font_GBK_String +( + uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + Text_Mode(); + Font_Select_UserDefine_Mode(); + Foreground_color_65k(FontColor); + Background_color_65k(BackGroundColor); + Goto_Text_XY(x,y); + + while(c[i] != '\0') + { + if(c[i] < 0x81) + { + CGROM_Select_Internal_CGROM(); // 内部CGROM为字符来源 + LCD_CmdWrite(0x04); + LCD_DataWrite(c[i]); + Check_Mem_WR_FIFO_not_Full(); + i += 1; + } + else + { + Font_Select_UserDefine_Mode(); // 自定义字库 + LCD_CmdWrite(0x04); + temp_H = ((c[i] - 0x81) & 0x00ff) * 191; + temp_L = c[i+1] - 0x40; + temp = temp_H + temp_L + 0x8000; + LCD_DataWrite((temp>>8)&0xff); + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite(temp&0xff); + Check_Mem_WR_FIFO_not_Full(); + i += 2; + } + } + + Check_2D_Busy(); + Graphic_Mode(); //back to graphic mode;图形模式 +} + +/*显示48*48、72*72字库*/ +void LT768_BTE_Memory_Copy_ColorExpansion_8 +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标(显示窗口的起始x坐标) + ,uint16_t YDes // 目的图像的左上方Y坐标(显示窗口的起始y坐标) + ,uint16_t X_W // 显示窗口的宽度 + ,uint16_t Y_H // 显示窗口的长度 + ,unsigned long Foreground_color + ,unsigned long Background_color +) +{ + Foreground_color_256(Foreground_color); + Background_color_256(Background_color); + BTE_ROP_Code(7); + BTE_S0_Color_8bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(Des_W); + BTE_S0_Window_Start_XY(YS0,0); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Operation_Code(0x0e); //BTE Operation: Memory copy (move) with chroma keying (w/o ROP) + BTE_Window_Size(X_W,Y_H); + BTE_Enable(); + Check_BTE_Busy(); +} + +void LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8 +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标(显示窗口的起始x坐标) + ,uint16_t YDes // 目的图像的左上方Y坐标(显示窗口的起始y坐标) + ,uint16_t X_W // 显示窗口的宽度 + ,uint16_t Y_H // 显示窗口的长度 + ,unsigned long Foreground_color +) +{ + Foreground_color_256(Foreground_color); + BTE_ROP_Code(7); + BTE_S0_Color_8bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(Des_W); + BTE_S0_Window_Start_XY(YS0,0); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Operation_Code(0x0f); //BTE Operation: Memory copy (move) with chroma keying (w/o ROP) + BTE_Window_Size(X_W,Y_H); + BTE_Enable(); + Check_BTE_Busy(); +} + +void LT768_Print_Outside_Font_GB2312_48_72 +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr // 目的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + h = x; + k = y; + Memory_8bpp_Mode();//使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr); + Canvas_image_width(width); + + while(c[i] != '\0') + { + temp_H = (c[i] - 0xa1) * 94; + temp_L = c[i+1] - 0xa1; + temp = temp_H + temp_L; + LT768_DMA_24bit_Block(SCS,Clk,Size*j/8,0,Size/8,Size,Size/8,FlashAddr+temp*((Size*Size)/8)); + i+=2; + j++; + } + + Memory_16bpp_Mode(); + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + if(w>2) + { + w = 2; + } + + for(g=0; g(width*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((width*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor + ); + } + + i+=2; + j++; + } + + ChromaKey=0; + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} + + +void LT768_Print_Outside_Font_BIG5_48_72 +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr // 目的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + h = x; + k = y; + Memory_8bpp_Mode();//使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr); + Canvas_image_width(width); + + while(c[i] != '\0') + { + temp_H = (c[i] - 0xa1) * 160; + + if(c[i+1]<0x7f) + { + temp_L = c[i+1] - 0x40; + } + else + { + temp_L = c[i+1] - 0xa0 + 0x40; + } + + temp = temp_H + temp_L; + LT768_DMA_24bit_Block(SCS,Clk,Size*j/8,0,Size/8,Size,Size/8,FlashAddr+temp*((Size*Size)/8)); + i+=2; + j++; + } + + Memory_16bpp_Mode(); // 因为显示是16位的色深，所以需要转为16位色深 + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + for(g=0; g(1024*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((1024*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr,Size*j/8, + ShowAddr,LCD_XSIZE_TFT,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr,Size*j/8, + ShowAddr,LCD_XSIZE_TFT,x+Size*j,y, + Size,Size,FontColor + ); + } + + i+=2; + j++; + } + + ChromaKey=0; + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} + +void LT768_Print_Outside_Font_GBK_48_72 +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr // 目的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + h = x; + k = y; + Memory_8bpp_Mode();//使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr); + Canvas_image_width(width); + + while(c[i] != '\0') + { + temp_H = (c[i] - 0x81) * 191; + temp_L = c[i+1] - 0x40; + temp = temp_H + temp_L; + LT768_DMA_24bit_Block(SCS,Clk,Size*j/8,0,Size/8,Size,Size/8,FlashAddr+temp*((Size*Size)/8)); + i+=2; + j++; + } + + Memory_16bpp_Mode(); + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + if(w>2) + { + w = 2; + } + + for(g=0; g(width*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((width*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor + ); + } + + i+=2; + j++; + } + + ChromaKey=0; + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} + +/*自定义字库*/ +//只能输入中文字 +#define Font_size 200//定义字库大小，200：最多200个字 +#define Font_BYTE Font_size*2 +uint8_t Font_1[Font_BYTE]; + +void clear_Font_1(void) +{ + uint16_t i; + + for(i = 0; i < Font_BYTE; i++) + { + Font_1[i] = 0; + } +} + +int Get_User_Font_P(char chH,char chL) +{ + int i; + + for(i=0; i<(sizeof(Font_1)/2); i++) + { + if((chH == Font_1[i*2])&&(chL == Font_1[i*2+1])) + { + return i; + } + } + + return -1; +} + +void LT768_Print_Outside_UserDefineFont_GB2312 +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr // 目的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + short temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + uint8_t temp1[2] = {0}; + uint32_t fontNum = 0; + clear_Font_1(); + LT768_SPI_Init(SCS,1); + LT_W25QXX_Read(temp1,FlashAddr+8,2); + fontNum = (temp1[0]<<8)+temp1[1]; + LT_W25QXX_Read(Font_1,FlashAddr + 0xc,fontNum * 2); + h = x; + k = y; + Memory_8bpp_Mode();//使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr); + Canvas_image_width(width); + + while(c[i] != '\0') + { + temp = Get_User_Font_P(c[i],c[i+1]); + + if(temp>-1) + { + LT768_DMA_24bit_Block(SCS,Clk,Size*j/8,0,Size/8,Size,Size/8,FlashAddr+temp*((Size*Size)/8)+0x0c+fontNum*2); + } + + i+=2; + j++; + } + + Memory_16bpp_Mode(); + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + if(w>2) + { + w = 2; + } + + for(g=0; g(width*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((width*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor + ); + } + + i+=2; + j++; + } + + ChromaKey=0; + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} + +/*----------------------------------------------------------------------------*/ + +void LT768_Text_cursor_Init +( + uint8_t On_Off_Blinking // 0：禁止光标闪烁 1：使能光标闪烁 + ,uint16_t Blinking_Time // 设置文字光标闪烁时间 + ,uint16_t X_W // 文字光标水平大小 + ,uint16_t Y_W // 文字光标垂直大小 +) +{ + if(On_Off_Blinking == 0) + { + Disable_Text_Cursor_Blinking(); + } + + if(On_Off_Blinking == 1) + { + Enable_Text_Cursor_Blinking(); + } + + Blinking_Time_Frames(Blinking_Time); + //[3E][3Fh] + Text_Cursor_H_V(X_W,Y_W); + Enable_Text_Cursor(); +} + + +void LT768_Enable_Text_Cursor(void) +{ + Enable_Text_Cursor(); +} + + +void LT768_Disable_Text_Cursor(void) +{ + Disable_Text_Cursor(); +} + + +void LT768_Graphic_cursor_Init +( + uint8_t Cursor_N // 选择光标 1:光标1 2:光标2 3:光标3 4:光标4 + ,uint8_t Color1 // 颜色1 + ,uint8_t Color2 // 颜色2 + ,uint16_t X_Pos // 显示坐标X + ,uint16_t Y_Pos // 显示坐标Y + ,uint8_t *Cursor_Buf // 光标数据的缓冲首地址 +) +{ + uint32_t i ; + Memory_Select_Graphic_Cursor_RAM(); + Graphic_Mode(); + + switch(Cursor_N) + { + case 1: + Select_Graphic_Cursor_1(); + break; + + case 2: + Select_Graphic_Cursor_2(); + break; + + case 3: + Select_Graphic_Cursor_3(); + break; + + case 4: + Select_Graphic_Cursor_4(); + break; + + default: + break; + } + + LCD_CmdWrite(0x04); + + for(i=0; i<256; i++) + { + LCD_DataWrite(Cursor_Buf[i]); + } + + Memory_Select_SDRAM();//写完后切回SDRAM + Set_Graphic_Cursor_Color_1(Color1); + Set_Graphic_Cursor_Color_2(Color2); + Graphic_Cursor_XY(X_Pos,Y_Pos); + Enable_Graphic_Cursor(); +} + + +void LT768_Set_Graphic_cursor_Pos +( + uint8_t Cursor_N // 选择光标 1:光标1 2:光标2 3:光标3 4:光标4 + ,uint16_t X_Pos // 显示坐标X + ,uint16_t Y_Pos // 显示坐标Y +) +{ + Graphic_Cursor_XY(X_Pos,Y_Pos); + + switch(Cursor_N) + { + case 1: + Select_Graphic_Cursor_1(); + break; + + case 2: + Select_Graphic_Cursor_2(); + break; + + case 3: + Select_Graphic_Cursor_3(); + break; + + case 4: + Select_Graphic_Cursor_4(); + break; + + default: + break; + } +} + + +void LT768_Enable_Graphic_Cursor(void) +{ + Enable_Graphic_Cursor(); +} + + +void LT768_Disable_Graphic_Cursor(void) +{ + Disable_Graphic_Cursor(); +} + +/*----------------------------------------------------------------------------*/ + +void LT768_PIP_Init +( + uint8_t On_Off // 0 : 禁止 PIP 1 : 使能 PIP 2 : 保持原来的状态 + ,uint8_t Select_PIP // 1 : 使用 PIP1 2 : 使用 PIP2 + ,unsigned long PAddr // PIP的开始地址 + ,uint16_t XP // PIP窗口的X坐标,必须被4整除 + ,uint16_t YP // PIP窗口的Y坐标,必须被4整除 + ,unsigned long ImageWidth // 底图的宽度 + ,uint16_t X_Dis // 显示窗口的X坐标 + ,uint16_t Y_Dis // 显示窗口的Y坐标 + ,uint16_t X_W // 显示窗口的宽度，必须被4整除 + ,uint16_t Y_H // 显示窗口的长度，必须被4整除 +) +{ + if(Select_PIP == 1) + { + Select_PIP1_Window_16bpp(); + Select_PIP1_Parameter(); + } + + if(Select_PIP == 2) + { + Select_PIP2_Window_16bpp(); + Select_PIP2_Parameter(); + } + + PIP_Display_Start_XY(X_Dis,Y_Dis); + PIP_Image_Start_Address(PAddr); + PIP_Image_Width(ImageWidth); + PIP_Window_Image_Start_XY(XP,YP); + PIP_Window_Width_Height(X_W,Y_H); + + if(On_Off == 0) + { + if(Select_PIP == 1) + { + Disable_PIP1(); + } + + if(Select_PIP == 2) + { + Disable_PIP2(); + } + } + + if(On_Off == 1) + { + if(Select_PIP == 1) + { + Enable_PIP1(); + } + + if(Select_PIP == 2) + { + Enable_PIP2(); + } + } +} + + +void LT768_Set_DisWindowPos +( + uint8_t On_Off // 0 : 禁止 PIP, 1 : 使能 PIP, 2 : 保持原来的状态 + ,uint8_t Select_PIP // 1 : 使用 PIP1 , 2 : 使用 PIP2 + ,uint16_t X_Dis // 显示窗口的X坐标 + ,uint16_t Y_Dis // 显示窗口的Y坐标 +) +{ + if(Select_PIP == 1) + { + Select_PIP1_Parameter(); + } + + if(Select_PIP == 2) + { + Select_PIP2_Parameter(); + } + + if(On_Off == 0) + { + if(Select_PIP == 1) + { + Disable_PIP1(); + } + + if(Select_PIP == 2) + { + Disable_PIP2(); + } + } + + if(On_Off == 1) + { + if(Select_PIP == 1) + { + Enable_PIP1(); + } + + if(Select_PIP == 2) + { + Enable_PIP2(); + } + } + + PIP_Display_Start_XY(X_Dis,Y_Dis); +} + +/*----------------------------------------------------------------------------*/ + +void BTE_Solid_Fill +( + unsigned long Des_Addr // 填充的目的地址 + ,uint16_t Des_W // 目的地址图片宽度 + ,uint16_t XDes // x坐标 + ,uint16_t YDes // y坐标 + ,uint16_t color // 填充的颜色 + ,uint16_t X_W // 填充的长度 + ,uint16_t Y_H // 填充的宽度 +) +{ + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + Foreground_color_65k(color); + BTE_Operation_Code(0x0c); + BTE_Enable(); + Check_BTE_Busy(); +} + +/* 结合光栅操作的BTE内存复制 */ +void LT768_BTE_Memory_Copy +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long S1_Addr // S1图像的内存起始地址 + ,uint16_t S1_W // S1图像的宽度 + ,uint16_t XS1 // S1图像的左上方X坐标 + ,uint16_t YS1 // S1图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方Y坐标 + ,uint32_t ROP_Code // 光栅操作模式 + /*ROP_Code : + 0000b 0(Blackness) + 0001b ~S0!E~S1 or ~(S0+S1) + 0010b ~S0!ES1 + 0011b ~S0 + 0100b S0!E~S1 + 0101b ~S1 + 0110b S0^S1 + 0111b ~S0 + ~S1 or ~(S0 + S1) + 1000b S0!ES1 + 1001b ~(S0^S1) + 1010b S1 + 1011b ~S0+S1 + 1100b S0 + 1101b S0+~S1 + 1110b S0+S1 + 1111b 1(whiteness)*/ + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 +) +{ + BTE_S0_Color_16bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_S1_Color_16bpp(); + BTE_S1_Memory_Start_Address(S1_Addr); + BTE_S1_Image_Width(S1_W); + BTE_S1_Window_Start_XY(XS1,YS1); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_ROP_Code(ROP_Code); + BTE_Operation_Code(0x02); //BTE Operation: Memory copy (move) with ROP. + BTE_Window_Size(X_W,Y_H); + BTE_Enable(); + Check_BTE_Busy(); +} + + +/* 结合 Chroma Key 的内存复制（不含 ROP） */ +void LT768_BTE_Memory_Copy_Chroma_key +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方X坐标 + ,unsigned long Background_color // 透明色 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 +) +{ + Background_color_65k(Background_color); + BTE_S0_Color_16bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Operation_Code(0x05); //BTE Operation: Memory copy (move) with chroma keying (w/o ROP) + BTE_Window_Size(X_W,Y_H); + BTE_Enable(); + Check_BTE_Busy(); +} + + +void LT768_BTE_Pattern_Fill +( + uint8_t P_8x8_or_16x16 // 0 : use 8x8 Icon , 1 : use 16x16 Icon. + ,unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + , uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方X坐标 + ,uint32_t ROP_Code // 光栅操作模式 + /*ROP_Code : + 0000b 0(Blackness) + 0001b ~S0!E~S1 or ~(S0+S1) + 0010b ~S0!ES1 + 0011b ~S0 + 0100b S0!E~S1 + 0101b ~S1 + 0110b S0^S1 + 0111b ~S0 + ~S1 or ~(S0 + S1) + 1000b S0!ES1 + 1001b ~(S0^S1) + 1010b S1 + 1011b ~S0+S1 + 1100b S0 + 1101b S0+~S1 + 1110b S0+S1 + 1111b 1(whiteness)*/ + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 +) +{ + if(P_8x8_or_16x16 == 0) + { + Pattern_Format_8X8(); + } + + if(P_8x8_or_16x16 == 1) + { + Pattern_Format_16X16(); + } + + BTE_S0_Color_16bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_ROP_Code(ROP_Code); + BTE_Operation_Code(0x06); //BTE Operation: Pattern Fill with ROP. + BTE_Window_Size(X_W,Y_H); + BTE_Enable(); + Check_BTE_Busy(); +} + + + +void LT768_BTE_Pattern_Fill_With_Chroma_key +( + uint8_t P_8x8_or_16x16 // 0 : use 8x8 Icon , 1 : use 16x16 Icon. + ,unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方Y坐标 + ,uint32_t ROP_Code // 光栅操作模式 + /*ROP_Code : + 0000b 0(Blackness) + 0001b ~S0!E~S1 or ~(S0+S1) + 0010b ~S0!ES1 + 0011b ~S0 + 0100b S0!E~S1 + 0101b ~S1 + 0110b S0^S1 + 0111b ~S0 + ~S1 or ~(S0 + S1) + 1000b S0!ES1 + 1001b ~(S0^S1) + 1010b S1 + 1011b ~S0+S1 + 1100b S0 + 1101b S0+~S1 + 1110b S0+S1 + 1111b 1(whiteness)*/ + ,unsigned long Background_color // 透明色 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 +) +{ + Background_color_65k(Background_color); + + if(P_8x8_or_16x16 == 0) + { + Pattern_Format_8X8(); + } + + if(P_8x8_or_16x16 == 1) + { + Pattern_Format_16X16(); + } + + BTE_S0_Color_16bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_ROP_Code(ROP_Code); + BTE_Operation_Code(0x07); //BTE Operation: Pattern Fill with Chroma key. + BTE_Window_Size(X_W,Y_H); + BTE_Enable(); + Check_BTE_Busy(); +} + + + +void LT768_BTE_MCU_Write_MCU_16bit +( + unsigned long S1_Addr // S1图像的内存起始地址 + ,uint16_t S1_W // S1图像的宽度 + ,uint16_t XS1 // S1图像的左上方X坐标 + ,uint16_t YS1 // S1图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方Y坐标 + ,uint32_t ROP_Code // 光栅操作模式 + /*ROP_Code : + 0000b 0(Blackness) + 0001b ~S0!E~S1 or ~(S0+S1) + 0010b ~S0!ES1 + 0011b ~S0 + 0100b S0!E~S1 + 0101b ~S1 + 0110b S0^S1 + 0111b ~S0 + ~S1 or ~(S0 + S1) + 1000b S0!ES1 + 1001b ~(S0^S1) + 1010b S1 + 1011b ~S0+S1 + 1100b S0 + 1101b S0+~S1 + 1110b S0+S1 + 1111b 1(whiteness)*/ + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 + ,const uint16_t *data // S0的数据首地址 +) +{ + uint16_t i,j; + BTE_S1_Color_16bpp(); + BTE_S1_Memory_Start_Address(S1_Addr); + BTE_S1_Image_Width(S1_W); + BTE_S1_Window_Start_XY(XS1,YS1); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_ROP_Code(ROP_Code); + BTE_Operation_Code(0x00); //BTE Operation: MPU Write with ROP. + BTE_Enable(); + BTE_S0_Color_16bpp(); + LCD_CmdWrite(0x04); //Memory Data Read/Write Port + + //MCU_16bit_ColorDepth_16bpp + for(i=0; i< Y_H; i++) + { + for(j=0; j< (X_W); j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel((*data)); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); + Check_BTE_Busy(); +} + + + +void LT768_BTE_MCU_Write_Chroma_key_MCU_16bit +( + unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方Y坐标 + ,unsigned long Background_color // 透明色 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 + ,const uint16_t *data // S0的数据收地址 +) +{ + uint32_t i,j; + Background_color_65k(Background_color); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_Operation_Code(0x04); //BTE Operation: MPU Write with chroma keying (w/o ROP) + BTE_Enable(); + BTE_S0_Color_16bpp(); + LCD_CmdWrite(0x04); //Memory Data Read/Write Port + + //MCU_16bit_ColorDepth_16bpp + for(i=0; i< Y_H; i++) + { + for(j=0; j< (X_W); j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel((*data)); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); + Check_BTE_Busy(); +} + + +/* 结合扩展色彩的 MPU 寫入 */ +void LT768_BTE_MCU_Write_ColorExpansion_MCU_16bit +( + unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方Y坐标 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 + ,unsigned long Foreground_color // 前景色 + /*Foreground_color : The source (1bit map picture) map data 1 translate to Foreground color by color expansion*/ + ,unsigned long Background_color // 背景色 + /*Background_color : The source (1bit map picture) map data 0 translate to Background color by color expansion*/ + ,const uint16_t *data // 数据缓存首地址 +) +{ + uint16_t i,j; + RGB_16b_16bpp(); + Foreground_color_65k(Foreground_color); + Background_color_65k(Background_color); + BTE_ROP_Code(15); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_Operation_Code(0x8); //BTE Operation: MPU Write with Color Expansion (w/o ROP) + BTE_Enable(); + LCD_CmdWrite(0x04); //Memory Data Read/Write Port + + for(i=0; i< Y_H; i++) + { + for(j=0; j< X_W/16; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); + Check_BTE_Busy(); +} + +/* 结合扩展色彩与 Chroma key 的 MPU 寫入 */ +void LT768_BTE_MCU_Write_ColorExpansion_Chroma_key_MCU_16bit +( + unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方Y坐标 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 + ,unsigned long Foreground_color // 前景色 + /*Foreground_color : The source (1bit map picture) map data 1 translate to Foreground color by color expansion*/ + ,const uint16_t *data // 数据缓存首地址 +) +{ + uint16_t i,j; + RGB_16b_16bpp(); + Foreground_color_65k(Foreground_color); + BTE_ROP_Code(15); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_Operation_Code(0x9); //BTE Operation: MPU Write with Color Expansion and chroma keying (w/o ROP) + BTE_Enable(); + LCD_CmdWrite(0x04); //Memory Data Read/Write Port + + for(i=0; i< Y_H; i++) + { + for(j=0; j< X_W/16; j++) + { + Check_Mem_WR_FIFO_not_Full(); + LCD_DataWrite_Pixel(*data); + data++; + } + } + + Check_Mem_WR_FIFO_Empty(); + Check_BTE_Busy(); +} + +/* 结合透明度的内存复制 */ +void BTE_Alpha_Blending +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long S1_Addr // S1图像的内存起始地址 + ,uint16_t S1_W // S1图像的宽度 + ,uint16_t XS1 // S1图像的左上方X坐标 + ,uint16_t YS1 // S1图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方X坐标 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 + ,uint8_t alpha // 透明度等级（32等级） +) +{ + BTE_S0_Color_16bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_S1_Color_16bpp(); + BTE_S1_Memory_Start_Address(S1_Addr); + BTE_S1_Image_Width(S1_W); + BTE_S1_Window_Start_XY(XS1,YS1); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_Operation_Code(0x0A); //BTE Operation: Memory write with opacity (w/o ROP) + BTE_Alpha_Blending_Effect(alpha); + BTE_Enable(); + Check_BTE_Busy(); +} + +void BTE_Pixel_8bpp_Alpha_Blending +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long S1_Addr // S1图像的内存起始地址 + ,uint16_t S1_W // S1图像的宽度 + ,uint16_t XS1 // S1图像的左上方X坐标 + ,uint16_t YS1 // S1图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方X坐标 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 +) +{ + BTE_S0_Color_8bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_S1_Color_8bit_Alpha(); + BTE_S1_Memory_Start_Address(S1_Addr); + BTE_S1_Image_Width(S1_W); + BTE_S1_Window_Start_XY(XS1,YS1); + BTE_Destination_Color_8bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_Operation_Code(0x0A); //BTE Operation: Memory write with opacity (w/o ROP) + BTE_Enable(); + Check_BTE_Busy(); +} + +void BTE_Pixel_16bpp_Alpha_Blending +( + unsigned long S0_Addr // SO图像的内存起始地址 + ,uint16_t S0_W // S0图像的宽度 + ,uint16_t XS0 // S0图像的左上方X坐标 + ,uint16_t YS0 // S0图像的左上方Y坐标 + ,unsigned long S1_Addr // S1图像的内存起始地址 + ,uint16_t S1_W // S1图像的宽度 + ,uint16_t XS1 // S1图像的左上方X坐标 + ,uint16_t YS1 // S1图像的左上方Y坐标 + ,unsigned long Des_Addr // 目的图像的内存起始地址 + ,uint16_t Des_W // 目的图像的宽度 + ,uint16_t XDes // 目的图像的左上方X坐标 + ,uint16_t YDes // 目的图像的左上方X坐标 + ,uint16_t X_W // 活动窗口的宽度 + ,uint16_t Y_H // 活动窗口的长度 +) +{ + BTE_S0_Color_16bpp(); + BTE_S0_Memory_Start_Address(S0_Addr); + BTE_S0_Image_Width(S0_W); + BTE_S0_Window_Start_XY(XS0,YS0); + BTE_S1_Color_16bit_Alpha(); + BTE_S1_Memory_Start_Address(S1_Addr); + BTE_S1_Image_Width(S1_W); + BTE_S1_Window_Start_XY(XS1,YS1); + BTE_Destination_Color_16bpp(); + BTE_Destination_Memory_Start_Address(Des_Addr); + BTE_Destination_Image_Width(Des_W); + BTE_Destination_Window_Start_XY(XDes,YDes); + BTE_Window_Size(X_W,Y_H); + BTE_Operation_Code(0x0A); //BTE Operation: Memory write with opacity (w/o ROP) + BTE_Enable(); + Check_BTE_Busy(); +} + +/*----------------------------------------------------------------------------*/ + +void LT768_PWM0_Init +( + uint8_t on_off // 0：禁止PWM0 1：使能PWM0 + ,uint8_t Clock_Divided // PWM时钟分频 取值范围 0~3(1,1/2,1/4,1/8) + ,uint8_t Prescalar // 时钟分频 取值范围 1~256 + ,uint16_t Count_Buffer // 设置PWM的输出周期 + ,uint16_t Compare_Buffer // 设置占空比 +) +{ + Select_PWM0(); + Set_PWM_Prescaler_1_to_256(Prescalar); + + if(Clock_Divided ==0) + { + Select_PWM0_Clock_Divided_By_1(); + } + + if(Clock_Divided ==1) + { + Select_PWM0_Clock_Divided_By_2(); + } + + if(Clock_Divided ==2) + { + Select_PWM0_Clock_Divided_By_4(); + } + + if(Clock_Divided ==3) + { + Select_PWM0_Clock_Divided_By_8(); + } + + Set_Timer0_Count_Buffer(Count_Buffer); + Set_Timer0_Compare_Buffer(Compare_Buffer); + + if(on_off == 1) + { + Start_PWM0(); + } + + if(on_off == 0) + { + Stop_PWM0(); + } +} + + +void LT768_PWM0_Duty(uint16_t Compare_Buffer) +{ + Set_Timer0_Compare_Buffer(Compare_Buffer); +} + +void LT768_PWM1_Init +( + uint8_t on_off // 0：禁止PWM0 1：使能PWM0 + ,uint8_t Clock_Divided // PWM时钟分频 取值范围 0~3(1,1/2,1/4,1/8) + ,uint8_t Prescalar // 时钟分频 取值范围 1~256 + ,uint16_t Count_Buffer // 设置PWM的输出周期 + ,uint16_t Compare_Buffer // 设置占空比 +) +{ + Select_PWM1(); + Set_PWM_Prescaler_1_to_256(Prescalar); + + if(Clock_Divided ==0) + { + Select_PWM1_Clock_Divided_By_1(); + } + + if(Clock_Divided ==1) + { + Select_PWM1_Clock_Divided_By_2(); + } + + if(Clock_Divided ==2) + { + Select_PWM1_Clock_Divided_By_4(); + } + + if(Clock_Divided ==3) + { + Select_PWM1_Clock_Divided_By_8(); + } + + Set_Timer1_Count_Buffer(Count_Buffer); + Set_Timer1_Compare_Buffer(Compare_Buffer); + + if(on_off == 1) + { + Start_PWM1(); + } + + if(on_off == 0) + { + Stop_PWM1(); + } +} + + +void LT768_PWM1_Duty(uint16_t Compare_Buffer) +{ + Set_Timer1_Compare_Buffer(Compare_Buffer); +} + +/*----------------------------------------------------------------------------*/ + +// LT768进入待命模式 +void LT768_Standby(void) +{ + Power_Saving_Standby_Mode(); + Check_Power_is_Saving(); +} +// 从待命模式中唤醒 +void LT768_Wkup_Standby(void) +{ + Power_Normal_Mode(); + Check_Power_is_Normal(); +} + + +// LT768进入暂停模式 +void LT768_Suspend(void) +{ + lt768_sdram_init(10); + Power_Saving_Suspend_Mode(); + Check_Power_is_Saving(); +} +// 从暂停模式中唤醒 +void LT768_Wkup_Suspend(void) +{ + Power_Normal_Mode(); + Check_Power_is_Normal(); + lt768_sdram_init(lt768_mclk); +} + + +// LT768进入休眠模式 +void LT768_SleepMode(void) +{ + Power_Saving_Sleep_Mode(); + Check_Power_is_Saving(); +} +// 从休眠模式中唤醒 +void LT768_Wkup_Sleep(void) +{ + Power_Normal_Mode(); + Check_Power_is_Normal(); +} + +/*----------------------------------------------------------------------------*/ + +void LT768_SPI_Init(uint8_t cs,uint8_t div) +{ + if(cs == 0) + { + Select_SFI_0(); + Select_nSS_drive_on_xnsfcs0(); + } + else + { + Select_SFI_1(); + Select_nSS_drive_on_xnsfcs1(); + } + + SPI_Clock_Period(div); + Enable_SFlash_SPI(); +} + +void W25QXX_Enter_4Byte_AddressMode(void)//val:选择外挂的SPI: SCS：0 SCS：1 +{ + nSS_Active(); + SPI_Master_FIFO_Data_Put(0xB7); + nSS_Inactive(); +} + +void LT_W25QXX_Read(uint8_t *pBuffer,uint32_t ReadAddr,uint16_t NumByteToRead) +{ + uint16_t i; + nSS_Active(); + SPI_Master_FIFO_Data_Put(0x03); + SPI_Master_FIFO_Data_Put((uint8_t)((ReadAddr)>>16)); + SPI_Master_FIFO_Data_Put((uint8_t)((ReadAddr)>>8)); + SPI_Master_FIFO_Data_Put((uint8_t)ReadAddr); + + for(i=0; i>8)); + SPI_Master_FIFO_Data_Put((uint8_t)page); + nSS_Inactive(); + W25N01GV_Wait_Busy(); +} + +void W25N01GV_ReadPageAddr_Data(uint8_t *pBuffer,uint32_t PageNum,uint32_t PageAddr,uint16_t NumByteToRead) +{ + uint16_t i; + //------从flash读数据到BUFF----- + nSS_Active(); //使能器件 + SPI_Master_FIFO_Data_Put(0x13); + SPI_Master_FIFO_Data_Put(0x00); + SPI_Master_FIFO_Data_Put((uint8_t)((PageNum)>>8)); //发送16bit地址 + SPI_Master_FIFO_Data_Put((uint8_t)(PageNum)); + nSS_Inactive(); + W25N01GV_Wait_Busy(); + W25N01GV_Write_SR(0xb0,W25N01GV_ReadSR(0xb0) | 0x08); //设定从BUFF的哪个位置开始读 + //------再从BUFF读数据到单片机内----- + nSS_Active(); + SPI_Master_FIFO_Data_Put(0x03); + SPI_Master_FIFO_Data_Put((PageAddr)>>8); + SPI_Master_FIFO_Data_Put(PageAddr); + SPI_Master_FIFO_Data_Put(0x00); + + for(i=0; iLCD_XSIZE_TFT) + { + x1 = x1-LCD_XSIZE_TFT; + y1++; + } + } +} + +void LT768_Print_Outside_Font_GB2312_48_72_Nand +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr1 // 缓冲层1的地址(SDRAM) + ,unsigned long MemoryAddr2 // 缓冲层1的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + h = x; + k = y; + Memory_8bpp_Mode(); //使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr1); + Canvas_image_width(width); + + while((c[i] != '\0')&&(c[i]>=0xa0)) // 遇见不是汉字编码的自动退出 + { + temp_H = (c[i] - 0xa1) * 94; + temp_L = c[i+1] - 0xa1; + temp = temp_H + temp_L; + LT768_Nand_8bpp_font(1,0,Size*j/8,0,Size/8,Size,FlashAddr+temp*((Size*Size)/8),MemoryAddr1,MemoryAddr2); //2019 + i+=2; + j++; + } + + Memory_16bpp_Mode(); + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + if(w>2) + { + w = 2; + } + + for(g=0; g=0xa0)) // 遇见不是汉字编码的自动退出 + { + if((f == m)&&((x+Size*j+Size)>(width*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((width*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr2,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr2,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor); + } + + i+=2; + j++; + } + + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} + +void LT768_Print_Outside_Font_GBK_48_72_Nand +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr1 // 缓冲层1的地址(SDRAM) + ,unsigned long MemoryAddr2 // 缓冲层1的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + uint16_t temp_H = 0; + uint16_t temp_L = 0; + uint16_t temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + h = x; + k = y; + Memory_8bpp_Mode(); //使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr1); + Canvas_image_width(width); + + while((c[i] != '\0')&&(c[i]>=0xa0)) // 遇见不是汉字编码的自动退出 + { + temp_H = (c[i] - 0x81) * 191; + temp_L = c[i+1] - 0x40; + temp = temp_H + temp_L; + LT768_Nand_8bpp_font(1,0,Size*j/8,0,Size/8,Size,FlashAddr+temp*((Size*Size)/8),MemoryAddr1,MemoryAddr2); //2019 + i+=2; + j++; + } + + Memory_16bpp_Mode(); + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + if(w>2) + { + w = 2; + } + + for(g=0; g=0xa0)) // 遇见不是汉字编码的自动退出 + { + if((f == m)&&((x+Size*j+Size)>(width*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((width*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr2,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr2,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor); + } + + i+=2; + j++; + } + + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} + +void LT768_Print_Outside_UserDefineFont_GB2312_Nand +( + uint8_t SCS // 选择外挂的SPI : SCS：0 SCS：1 + ,uint8_t Clk // SPI时钟分频参数 : SPI Clock = System Clock /{(Clk+1)*2} + ,unsigned long FlashAddr // 字库源地址(Flash) + ,unsigned long MemoryAddr1 // 缓冲层1的地址(SDRAM) + ,unsigned long MemoryAddr2 // 缓冲层1的地址(SDRAM) + ,unsigned long ShowAddr // 显示层的地址 + ,uint16_t width // 显示层的宽度 + ,uint8_t Size // 设置字体大小 48：48*48 72:72*72 + ,uint8_t ChromaKey // 0：字体背景色透明 1：可以设置字体的背景色 + ,uint16_t x // 字体开始显示的x位置 + ,uint16_t y // 字体开始显示的y位置 + ,unsigned long FontColor // 字体的颜色 + ,unsigned long BackGroundColor // 字体的背景色（注意：当字体背景初始化成透明时，设置该值无效） + ,uint16_t w // 字体粗细：0：不加粗 1：加粗1级 2：加粗2级 + ,uint16_t s // 行距 + ,uint8_t *c // 数据缓冲的首地址 +) +{ + short temp = 0; + unsigned long i = 0; + uint16_t j = 0; + uint16_t k = 0; + uint16_t h = 0; + uint16_t n = 0; + uint16_t m = 0; + uint16_t g = 0; + uint16_t f = 0; + uint8_t temp1[2] = {0}; + uint32_t fontNum = 0; + clear_Font_1(); + LT768_SPI_Init(SCS,1); + LT_W25N01GV_Read(temp1,FlashAddr+8,2); + fontNum = (temp1[0]<<8)+temp1[1]; + LT_W25N01GV_Read(Font_1,FlashAddr + 0xc,fontNum * 2); + h = x; + k = y; + Memory_8bpp_Mode();//使用8位色深来存储图片 + Canvas_Image_Start_address(MemoryAddr1); + Canvas_image_width(width); + + while(c[i + 1] != '\0') + { + temp = Get_User_Font_P(c[i],c[i+1]); + + if(temp != -1) + { + LT768_Nand_8bpp_font(SCS,Clk,Size*j/8,0,Size/8,Size,FlashAddr+temp*((Size*Size)/8)+0x0c+fontNum*2,MemoryAddr1,MemoryAddr2); //2019 + } + else + { + break; + } + + i+=2; + j++; + } + + Memory_16bpp_Mode(); + Canvas_Image_Start_address(ShowAddr); + Canvas_image_width(width); + j = 0; + i = 0; + + if(w>2) + { + w = 2; + } + + for(g=0; g(width*(n+1)))) + { + m++; + n++; + y=y+Size-1+s; + x = x+((width*n)-(x+Size*j))+g; + f=n; + } + + if(ChromaKey==1) + { + LT768_BTE_Memory_Copy_ColorExpansion_8(MemoryAddr2,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor,BackGroundColor + ); + } + + if(ChromaKey==0) + { + LT768_BTE_Memory_Copy_ColorExpansion_Chroma_key_8(MemoryAddr2,Size*j/8, + ShowAddr,width,x+Size*j,y, + Size,Size,FontColor + ); + } + + i+=2; + j++; + } + + ChromaKey=0; + i=0; + j=0; + m=0; + n=0; + f=0; + x=h+g+1; + y=k+g+1; + } +} +