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Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into xidatong

This commit is contained in:
Liu_Weichao 2022-09-06 14:26:36 +08:00
parent 6fc09a8864 5f42111c38
commit b5495f108a
171 changed files with 258892 additions and 4005 deletions
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8
APP_Framework/Framework/connection/4g/adapter_4g.c
View File

@ -110,7 +110,9 @@ int Adapter4GTest(void)
return 0;
}
// SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, Adapter4GTest, Adapter4GTest, show adapter 4G information);
#ifdef ADD_RTTHREAD_FETURES
MSH_CMD_EXPORT(Adapter4GTestRTThread,a 4G adpter sample);
#ifdef ADD_RTTHREAD_FETURES
MSH_CMD_EXPORT(Adapter4GTest,a EC200T adpter sample);
#else
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, Adapter4GTest, Adapter4GTest, show adapter 4G information);
#endif

19
APP_Framework/Framework/connection/4g/ec200t/Kconfig
View File

@ -3,13 +3,19 @@ config ADAPTER_4G_EC200T
default "ec200t"
if ADD_XIZI_FETURES
config ADAPTER_EC200T_PWRKEY
int "EC200T PWRKEY pin number"
default "97"
config ADAPTER_EC200T_USING_PWRKEY
bool "EC200T using PWRKEY pin number"
default n
config ADAPTER_EC200T_PIN_DRIVER
string "EC200T device pin driver path"
default "/dev/pin_dev"
if ADAPTER_EC200T_USING_PWRKEY
config ADAPTER_EC200T_PWRKEY
int "EC200T PWRKEY pin number"
default "97"
config ADAPTER_EC200T_PIN_DRIVER
string "EC200T device pin driver path"
default "/dev/pin_dev"
endif
config ADAPTER_EC200T_DRIVER_EXTUART
bool "Using extra uart to support 4G"
@ -35,7 +41,6 @@ if ADD_NUTTX_FETURES
config ADAPTER_EC200T_DRIVER
string "EC200T device uart driver path"
default "/dev/ttyS8"
endif
if ADD_RTTHREAD_FETURES

17
APP_Framework/Framework/connection/4g/ec200t/ec200t.c
View File

@ -38,14 +38,9 @@
#define TRY_TIMES 10
#ifdef ADD_NUTTX_FETURES
static void Ec200tPowerSet(void){ return; }
#else
#ifdef ADD_RTTHREAD_FETURES
static void Ec200tPowerSet(void){ return; }
#else
static void Ec200tPowerSet(void)
{
static void Ec200tPowerSet(void)
{
#ifdef ADAPTER_EC200T_USING_PWRKEY
int pin_fd;
pin_fd = PrivOpen(ADAPTER_EC200T_PIN_DRIVER, O_RDWR);
if (pin_fd < 0) {
@ -76,9 +71,8 @@ static void Ec200tPowerSet(void){ return; }
PrivClose(pin_fd);
PrivTaskDelay(10000);
}
#endif
#endif
}
static int Ec200tOpen(struct Adapter *adapter)
{
@ -148,7 +142,6 @@ out:
return ret;
}
#ifdef ADD_NUTTX_FETURES
static int Ec200tIoctl(struct Adapter *adapter, int cmd, void *args){ return 0;}
#else
@ -174,6 +167,7 @@ static int Ec200tIoctl(struct Adapter *adapter, int cmd, void *args)
serial_cfg.serial_bit_order = STOP_BITS_1;
serial_cfg.serial_invert_mode = NRZ_NORMAL;
#ifdef ADAPTER_EC200T_DRIVER_EXT_PORT
serial_cfg.is_ext_uart = 1;
serial_cfg.ext_uart_no = ADAPTER_EC200T_DRIVER_EXT_PORT;
serial_cfg.port_configure = PORT_CFG_INIT;
#endif
@ -183,7 +177,6 @@ static int Ec200tIoctl(struct Adapter *adapter, int cmd, void *args)
ioctl_cfg.args = &serial_cfg;
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
Ec200tPowerSet();
return 0;

5
APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c
View File

@ -82,7 +82,7 @@ int AdapterBlueToothInit(void)
int AdapterBlueToothTest(void)
{
const char *bluetooth_msg = "BT Adapter Test";
char bluetooth_recv_msg[128];
char bluetooth_recv_msg[128]={0};
int len;
int baud_rate = BAUD_RATE_9600;
@ -92,7 +92,7 @@ int AdapterBlueToothTest(void)
AdapterDeviceOpen(adapter);
//if bluetooth master and slave have already match, no need to AdapterDeviceControl and AdapterDeviceConnect
AdapterDeviceControl(adapter, OPE_INT, &baud_rate);
AdapterDeviceControl(adapter, OPE_INT, &baud_rate);
//AdapterDeviceConnect(adapter, adapter->net_role, NULL, NULL, 0);
len = strlen(bluetooth_msg);
@ -100,6 +100,7 @@ int AdapterBlueToothTest(void)
while (1) {
AdapterDeviceRecv(adapter, bluetooth_recv_msg, 8);
printf("bluetooth_recv_msg %s\n", bluetooth_recv_msg);
AdapterDeviceSend(adapter, bluetooth_msg, len);
printf("send %s after recv\n", bluetooth_msg);
PrivTaskDelay(1000);

27
APP_Framework/Framework/connection/bluetooth/hc08/Kconfig
View File

@ -55,9 +55,30 @@ if ADD_NUTTX_FETURES
endif
if ADD_RTTHREAD_FETURES
config ADAPTER_HC08_DRIVER
string "HC08 device uart driver path"
default "/dev/uart4"
config ADAPTER_HC08_RECV_BUFFER_SIZE
int "HC08 recv data buffer size"
default "128"
config ADAPTER_HC08_WORK_ROLE
string "HC08 work role M(MASTER) or S(SLAVER)"
default "M"
config ADAPTER_HC08_DRIVER_EXTUART
bool "Using extra uart to support bluetooth"
default n
config ADAPTER_HC08_DRIVER
string "HC08 device uart driver path"
default "/dev/dev2"
depends on !ADAPTER_HC08_DRIVER_EXTUART
if ADAPTER_HC08_DRIVER_EXTUART
config ADAPTER_HC08_DRIVER
string "HC08 device extra uart driver path"
default "/dev/dev2"
config ADAPTER_HC08_DRIVER_EXT_PORT
int "if HC08 device using extuart, choose port"
default "2"
endif
endif

101
APP_Framework/Framework/connection/bluetooth/hc08/hc08.c
View File

@ -21,32 +21,32 @@
#include <adapter.h>
#include <at_agent.h>
#define HC08_DETECT_CMD "AT"
#define HC08_DEFAULT_CMD "AT+DEFAULT"
#define HC08_RESET_CMD "AT+RESET"
#define HC08_CLEAR_CMD "AT+CLEAR"
#define HC08_DETECT_CMD "AT"
#define HC08_DEFAULT_CMD "AT+DEFAULT"
#define HC08_RESET_CMD "AT+RESET"
#define HC08_CLEAR_CMD "AT+CLEAR"
#define HC08_GET_DEVICE_INFO "AT+RX"
#define HC08_GET_BAUDRATE_CMD "AT+BAUD=?"
#define HC08_SET_BAUDRATE_CMD "AT+BAUD=%u"
#define HC08_GET_BAUDRATE_CMD "AT+BAUD=?"
#define HC08_SET_BAUDRATE_CMD "AT+BAUD=%u"
#define HC08_GET_CONNECTABLE "AT+CONT=?"
#define HC08_SET_CONNECTABLE "AT+CONT=%s"
#define HC08_GET_ROLE_CMD "AT+ROLE=?"
#define HC08_SET_ROLE_CMD "AT+ROLE=%s"
#define HC08_GET_ADDR_CMD "AT+ADDR=?"
#define HC08_SET_ADDR_CMD "AT+ADDR=%s"
#define HC08_GET_NAME_CMD "AT+NAME=%s"
#define HC08_SET_NAME_CMD "AT+NAME=?"
#define HC08_GET_LUUID_CMD "AT+LUUID=?"
#define HC08_SET_LUUID_CMD "AT+LUUID=%u"
#define HC08_GET_SUUID_CMD "AT+SUUID=?"
#define HC08_SET_SUUID_CMD "AT+SUUID=%u"
#define HC08_GET_TUUID_CMD "AT+TUUID=?"
#define HC08_SET_TUUID_CMD "AT+TUUID=%u"
#define HC08_GET_ROLE_CMD "AT+ROLE=?"
#define HC08_SET_ROLE_CMD "AT+ROLE=%s"
#define HC08_GET_ADDR_CMD "AT+ADDR=?"
#define HC08_SET_ADDR_CMD "AT+ADDR=%s"
#define HC08_GET_NAME_CMD "AT+NAME=%s"
#define HC08_SET_NAME_CMD "AT+NAME=?"
#define HC08_GET_LUUID_CMD "AT+LUUID=?"
#define HC08_SET_LUUID_CMD "AT+LUUID=%u"
#define HC08_GET_SUUID_CMD "AT+SUUID=?"
#define HC08_SET_SUUID_CMD "AT+SUUID=%u"
#define HC08_GET_TUUID_CMD "AT+TUUID=?"
#define HC08_SET_TUUID_CMD "AT+TUUID=%u"
#define HC08_OK_RESP "OK"
#define HC08_OK_RESP "OK"
#define HC08_CMD_STR_DEFAULT_SIZE 64
#define HC08_CMD_STR_DEFAULT_SIZE 64
#define HC08_RESP_DEFAULT_SIZE 64
enum Hc08AtCmd
@ -189,6 +189,30 @@ static int Hc08AtConfigure(ATAgentType agent, enum Hc08AtCmd hc08_at_cmd, void *
AtSetReplyCharNum(agent, 13);
ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd_str);
reply_ok_flag = 0;
break;
case HC08_AT_CMD_GET_SUUID:
AtSetReplyCharNum(agent, 13);
ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_SUUID_CMD);
reply_ok_flag = 0;
break;
case HC08_AT_CMD_SET_SUUID:
luuid = *(unsigned int *)param;
sprintf(cmd_str, HC08_SET_SUUID_CMD, luuid);
AtSetReplyCharNum(agent, 13);
ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd_str);
reply_ok_flag = 0;
break;
case HC08_AT_CMD_GET_TUUID:
AtSetReplyCharNum(agent, 13);
ATOrderSend(agent, REPLY_TIME_OUT, reply, HC08_GET_TUUID_CMD);
reply_ok_flag = 0;
break;
case HC08_AT_CMD_SET_TUUID:
luuid = *(unsigned int *)param;
sprintf(cmd_str, HC08_SET_TUUID_CMD, luuid);
AtSetReplyCharNum(agent, 13);
ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd_str);
reply_ok_flag = 0;
break;
default:
printf("hc08 do not support no.%d cmd\n", hc08_at_cmd);
@ -239,6 +263,7 @@ static int Hc08Open(struct Adapter *adapter)
serial_cfg.serial_bit_order = STOP_BITS_1;
serial_cfg.serial_invert_mode = NRZ_NORMAL;
#ifdef ADAPTER_HC08_DRIVER_EXT_PORT
serial_cfg.is_ext_uart = 1;
serial_cfg.ext_uart_no = ADAPTER_HC08_DRIVER_EXT_PORT;
serial_cfg.port_configure = PORT_CFG_INIT;
#endif
@ -309,7 +334,8 @@ static int Hc08Ioctl(struct Adapter *adapter, int cmd, void *args)
return 0;
}
#else
#else
static int Hc08Ioctl(struct Adapter *adapter, int cmd, void *args)
{
if (OPE_INT != cmd) {
@ -330,6 +356,7 @@ static int Hc08Ioctl(struct Adapter *adapter, int cmd, void *args)
serial_cfg.serial_bit_order = STOP_BITS_1;
serial_cfg.serial_invert_mode = NRZ_NORMAL;
#ifdef ADAPTER_HC08_DRIVER_EXT_PORT
serial_cfg.is_ext_uart = 1;
serial_cfg.ext_uart_no = ADAPTER_HC08_DRIVER_EXT_PORT;
serial_cfg.port_configure = PORT_CFG_INIT;
#endif
@ -360,27 +387,45 @@ static int Hc08Ioctl(struct Adapter *adapter, int cmd, void *args)
}
PrivTaskDelay(500);
#ifdef ADD_RTTHREAD_FETURES
//Step3 : show hc08 device info, hc08_get send "AT+RX" response device info
// char device_info[HC08_RESP_DEFAULT_SIZE * 2] = {0};
// if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_DEVICE_INFO, NULL, device_info) < 0) {
// return -1;
// }
char device_info[HC08_RESP_DEFAULT_SIZE * 2] = {0};
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_DEVICE_INFO, NULL, device_info) < 0) {
return -1;
}
#endif
//Step4 : set LUUID、SUUID、TUUID, slave and master need to have same uuid param
luuid = 1234;
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_LUUID, &luuid, NULL) < 0) {
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_LUUID, &luuid, NULL) < 0) {
return -1;
}
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_LUUID, NULL, NULL) < 0) {
return -1;
}
#ifdef ADD_RTTHREAD_FETURES
uint32_t suuid=1234;
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_SUUID, &luuid, NULL) < 0) {
return -1;
}
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_SUUID, NULL, NULL) < 0) {
return -1;
}
uint32_t tuuid=1234;
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_SET_TUUID, &tuuid, NULL) < 0) {
return -1;
}
if (Hc08AtConfigure(adapter->agent, HC08_AT_CMD_GET_TUUID, NULL, NULL) < 0) {
return -1;
}
#endif
ADAPTER_DEBUG("Hc08 ioctl done\n");
return 0;
}
#endif
static int Hc08SetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask)

1
APP_Framework/Framework/connection/ethernet/hfa21_ethernet/hfa21_ethernet.c
View File

@ -402,6 +402,7 @@ static int Hfa21EthernetIoctl(struct Adapter *adapter, int cmd, void *args)
serial_cfg.serial_bit_order = BIT_ORDER_LSB;
serial_cfg.serial_invert_mode = NRZ_NORMAL;
#ifdef ADAPTER_HFA21_DRIVER_EXT_PORT
serial_cfg.is_ext_uart = 1;
serial_cfg.ext_uart_no = ADAPTER_HFA21_DRIVER_EXT_PORT;
serial_cfg.port_configure = PORT_CFG_INIT;
#endif

7
APP_Framework/Framework/connection/lora/adapter_lora.c
View File

@ -924,8 +924,8 @@ static pthread_t lora_client_data_task;
int AdapterLoraTest(void)
{
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME);
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME);
AdapterDeviceOpen(adapter);
//create lora gateway task
@ -979,6 +979,9 @@ int AdapterLoraTest(void)
return 0;
}
#ifdef ADD_RTTHREAD_FETURES
MSH_CMD_EXPORT(AdapterLoraTest,a Lora adpter sample);
#endif
#ifdef ADD_XIZI_FETURES
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, AdapterLoraTest, AdapterLoraTest, show adapter lora information);
#endif

29
APP_Framework/Framework/connection/lora/e220/Kconfig
View File

@ -64,5 +64,34 @@ if ADD_NUTTX_FETURES
endif
if ADD_RTTHREAD_FETURES
config ADAPTER_E220_M0
int "E220 M0 pin number"
default "11"
config ADAPTER_E220_M1
int "E220 M1 pin number"
default "9"
config ADAPTER_E220_PIN_DRIVER
string "E220 device pin driver path"
default "/dev/dev3"
config ADAPTER_E220_DRIVER_EXTUART
bool "Using extra uart to support lora"
default y
config ADAPTER_E220_DRIVER
string "E220 device uart driver path"
default "/dev/dev3"
depends on !ADAPTER_E220_DRIVER_EXTUART
if ADAPTER_E220_DRIVER_EXTUART
config ADAPTER_E220_DRIVER
string "E220 device extra uart driver path"
default "/dev/dev3"
config ADAPTER_E220_DRIVER_EXT_PORT
int "if E220 device using extuart, choose port"
default "3"
endif
endif

10
APP_Framework/Framework/connection/lora/e220/SConscript Normal file
View File

@ -0,0 +1,10 @@
from building import *
import os
cwd = GetCurrentDir()
src = []
if GetDepend(['ADAPTER_E220']):
src += ['e220.c']
group = DefineGroup('connection lora e220', src, depend = [], CPPPATH = [cwd])
Return('group')

153
APP_Framework/Framework/connection/lora/e220/e220.c
View File

@ -21,7 +21,11 @@
#include <adapter.h>
#define E220_GATEWAY_ADDRESS 0xFFFF
#ifdef ADD_RTTHREAD_FETURES
#define E220_CHANNEL 0x02
#else
#define E220_CHANNEL 0x05
#endif
#ifdef AS_LORA_GATEWAY_ROLE
#define E220_ADDRESS E220_GATEWAY_ADDRESS
@ -31,7 +35,11 @@
#define E220_ADDRESS ADAPTER_LORA_NET_ROLE_ID
#endif
#ifdef ADD_RTTHREAD_FETURES
#define E220_UART_BAUD_RATE 9600
#else
#define E220_UART_BAUD_RATE 115200
#endif
enum E220LoraMode
{
@ -265,13 +273,16 @@ static int E220SetRegisterParam(struct Adapter *adapter, uint16 address, uint8 c
buffer[10] = 0; //low-cipher
ret = PrivWrite(adapter->fd, (void *)buffer, 11);
if(ret < 0){
printf("E220SetRegisterParam send failed %d!\n", ret);
}
PrivRead(adapter->fd, buffer, 11);
E220LoraModeConfig(DATA_TRANSFER_MODE);
PrivRead(adapter->fd, buffer, 11);
E220LoraModeConfig(DATA_TRANSFER_MODE);
PrivTaskDelay(1000);
return 0;
@ -337,9 +348,10 @@ static int E220Open(struct Adapter *adapter)
return 0;
}
#else
#ifdef ADD_RTTHREAD_FETURES
static int E220Open(struct Adapter *adapter)
{
/*step1: open e220 uart port*/
/*step1: open e220 uart port*/
adapter->fd = PrivOpen(ADAPTER_E220_DRIVER, O_RDWR);
if (adapter->fd < 0) {
printf("E220Open get uart %s fd error\n", ADAPTER_E220_DRIVER);
@ -368,6 +380,59 @@ static int E220Open(struct Adapter *adapter)
cfg.serial_timeout = 10000;
#endif
#ifdef AS_LORA_CLIENT_ROLE
//serial receive wait forever
cfg.serial_timeout = -1;
#endif
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = &cfg;
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
cfg.serial_baud_rate = E220_UART_BAUD_RATE;
ioctl_cfg.args = &cfg;
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
ADAPTER_DEBUG("E220Open done\n");
return 0;
}
#else
static int E220Open(struct Adapter *adapter)
{
/*step1: open e220 uart port*/
adapter->fd = PrivOpen(ADAPTER_E220_DRIVER, O_RDWR);
if (adapter->fd < 0) {
printf("E220Open get uart %s fd error\n", ADAPTER_E220_DRIVER);
return -1;
}
struct SerialDataCfg cfg;
memset(&cfg, 0 ,sizeof(struct SerialDataCfg));
cfg.serial_baud_rate = BAUD_RATE_9600;
cfg.serial_data_bits = DATA_BITS_8;
cfg.serial_stop_bits = STOP_BITS_1;
cfg.serial_parity_mode = PARITY_NONE;
cfg.serial_bit_order = BIT_ORDER_LSB;
cfg.serial_invert_mode = NRZ_NORMAL;
cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
/*aiit board use ch438, so it needs more serial configuration*/
#ifdef ADAPTER_E220_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_E220_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif
#ifdef AS_LORA_GATEWAY_ROLE
//serial receive timeout 10s
cfg.serial_timeout = 10000;
#endif
#ifdef AS_LORA_CLIENT_ROLE
//serial receive wait forever
cfg.serial_timeout = -1;
@ -391,6 +456,7 @@ static int E220Open(struct Adapter *adapter)
return 0;
}
#endif
#endif
/**
* @description: Close E220 uart function
@ -472,7 +538,7 @@ static int E220Send(struct Adapter *adapter, const void *buf, size_t len)
*/
static int E220Recv(struct Adapter *adapter, void *buf, size_t len)
{
int recv_len, recv_len_continue;
int recv_len=0, recv_len_continue=0;
uint8 *recv_buf = PrivMalloc(len);
@ -558,7 +624,46 @@ static void LoraOpen(void)
E220Open(adapter);
}
MSH_CMD_EXPORT(LoraOpen,Lora open test sample);
#ifdef ADD_RTTHREAD_FETURES
static void LoraRead(void *parameter)
{
int RevLen;
int i, cnt = 0;
uint8 buffer[256];
memset(buffer, 0, 256);
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME);
if (NULL == adapter) {
printf("LoraRead find lora adapter error\n");
return;
}
while (1)
{
printf("ready to read lora data\n");
RevLen = E220Recv(adapter, buffer, 6);
if (RevLen) {
printf("lora get data %u\n", RevLen);
for (i = 0; i < RevLen; i ++) {
printf("i %u data 0x%x\n", i, buffer[i]);
}
memset(buffer, 0, 256);
PrivTaskDelay(1000);
cnt ++;
E220Send(adapter, &cnt, 1);
}
}
}
MSH_CMD_EXPORT(LoraRead,Lora read test sample);
#else
static void LoraRead(void *parameter)
{
int RevLen;
@ -594,6 +699,8 @@ static void LoraRead(void *parameter)
}
}
}
#endif
#ifdef ADD_XIZI_FETURES
static void LoraTest(void)
@ -667,3 +774,41 @@ void E220LoraSend(int argc, char *argv[])
}
}
#endif
#ifdef ADD_RTTHREAD_FETURES
static void LoraReadStart(void)
{
int ret;
LoraOpen();
rt_thread_t tid= rt_thread_create("LoraReadStart", LoraRead, RT_NULL,2048,10,5);
if(tid!=RT_NULL){
rt_thread_startup(tid);
}else{
rt_kprintf("LoraReadStart task_lora_read failed \r\n");
return;
}
}
MSH_CMD_EXPORT(LoraReadStart,Lora read task start sample);
#define E22400T_M1_PIN (11U)
#define E22400T_M0_PIN (9U)
static void LoraSend(int argc, char *argv[])
{
int8_t cmd[10]={0xFF,0xFF,0x02,0xAA,0XBB,0xCC}; //sned AA BB CC to address 01 channel05
LoraOpen();
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_LORA_NAME);
if (NULL == adapter) {
printf("LoraRead find lora adapter error\n");
return;
}
rt_pin_mode (E22400T_M1_PIN, PIN_MODE_OUTPUT);
rt_pin_mode (E22400T_M0_PIN, PIN_MODE_OUTPUT);
rt_pin_write(E22400T_M1_PIN, PIN_LOW);
rt_pin_write(E22400T_M0_PIN, PIN_HIGH);
E220Send(adapter, cmd, 6);
}
MSH_CMD_EXPORT(LoraSend,Lora send sample);
#endif

1
APP_Framework/Framework/connection/nbiot/bc28/bc28.c
View File

@ -59,6 +59,7 @@ static int BC28UartOpen(struct Adapter *adapter)
/*aiit board use ch438, so it needs more serial configuration*/
#ifdef ADAPTER_BC28_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_BC28_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

2
APP_Framework/Framework/connection/wifi/esp07s_wifi/esp07s_wifi.c
View File

@ -82,6 +82,7 @@ static int Esp07sUartOpen(struct Adapter *adapter)
cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
#ifdef ADAPTER_ESP07S_DRIVER_EXT_PORT
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_ESP07S_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif
@ -512,6 +513,7 @@ static int Esp07sWifiIoctl(struct Adapter *adapter, int cmd, void *args)
cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
#ifdef ADAPTER_ESP07S_DRIVER_EXT_PORT
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_ESP07S_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/connection/wifi/hfa21_wifi/hfa21_wifi.c
View File

@ -474,6 +474,7 @@ static int Hfa21WifiIoctl(struct Adapter *adapter, int cmd, void *args)
serial_cfg.serial_bit_order = BIT_ORDER_LSB;
serial_cfg.serial_invert_mode = NRZ_NORMAL;
#ifdef ADAPTER_HFA21_DRIVER_EXT_PORT
serial_cfg.is_ext_uart = 1;
serial_cfg.ext_uart_no = ADAPTER_HFA21_DRIVER_EXT_PORT;
serial_cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/connection/zigbee/e18/e18.c
View File

@ -108,6 +108,7 @@ static int E18UartOpen(struct Adapter *adapter)
/*aiit board use ch438, so it needs more serial configuration*/
#ifdef ADAPTER_E18_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_E18_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/ch4/as830/as830.c
View File

@ -65,6 +65,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_AS830_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_AS830_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/co2/g8s/g8s.c
View File

@ -70,6 +70,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_G8S_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_G8S_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/co2/zg09/zg09.c
View File

@ -76,6 +76,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_ZG09_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_ZG09_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/tb600b_wq_hcho1os.c
View File

@ -66,6 +66,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/iaq/tb600b_iaq10/tb600b_iaq10.c
View File

@ -73,6 +73,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_TB600B_IAQ10_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_TB600B_IAQ10_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/pm/ps5308/ps5308.c
View File

@ -98,6 +98,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_PS5308_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_PS5308_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/tvoc/tb600b_tvoc10/tb600b_tvoc10.c
View File

@ -66,6 +66,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_TB600B_TVOC10_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_TB600B_TVOC10_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/voice/d124/d124.c
View File

@ -102,6 +102,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_D124_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_D124_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

1
APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c
View File

@ -66,6 +66,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_QS_FX_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_QS_FX_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

3
APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c
View File

@ -64,7 +64,8 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
cfg.serial_parity_mode = PARITY_NONE;
cfg.serial_bit_order = 0;
cfg.serial_invert_mode = 0;
#ifdef SENSOR_QS_FS_DRIVER_EXTUART
#ifdef SENSOR_QS_FS_DRIVER_EXTUART
cfg.is_ext_uart = 1;
cfg.ext_uart_no = SENSOR_DEVICE_QS_FS_DEV_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif

3
APP_Framework/Framework/transform_layer/nuttx/transform.h
View File

@ -142,7 +142,8 @@ struct SerialDataCfg
uint8_t serial_invert_mode;
uint16_t serial_buffer_size;
uint8 ext_uart_no;
uint8_t is_ext_uart;
uint8_t ext_uart_no;
enum ExtSerialPortConfigure port_configure;
};

1
APP_Framework/Framework/transform_layer/rtthread/transform.h
View File

@ -145,6 +145,7 @@ struct SerialDataCfg
uint8_t serial_invert_mode;
uint16_t serial_buffer_size;
uint8_t is_ext_uart;
uint8_t ext_uart_no;
enum ExtSerialPortConfigure port_configure;
};

1
APP_Framework/Framework/transform_layer/xizi/transform.h
View File

@ -133,6 +133,7 @@ struct SerialDataCfg
uint16_t serial_buffer_size;
int32 serial_timeout;
uint8_t is_ext_uart;
uint8_t ext_uart_no;
enum ExtSerialPortConfigure port_configure;
};

19
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-arm32/applications/main.c
View File

@ -13,22 +13,21 @@
#include <rtthread.h>
#include "drv_gpio.h"
#include <board.h>
#include "fsl_gpio.h"
#include "board/hardware/ch438/ch438.h"
/* defined the LED pin: GPIO1_IO9 */
#define LED0_PIN GET_PIN(1,9)
extern int FrameworkInit(void);
int main(void)
{
{
/* set LED0 pin mode to output */
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
rt_kprintf("XIUOS xidatong build %s %s\n",__DATE__,__TIME__);
while (1)
{
rt_pin_write(LED0_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
FrameworkInit();
while (1)
{
rt_thread_mdelay(5000);
}
}
#ifdef BSP_USING_SDRAM

37
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-arm32/board/Kconfig
View File

@ -229,7 +229,44 @@ menu "Onboard Peripheral Drivers"
config BSP_USB1_HOST
bool "Enable USB1 Host"
default n
config BSP_USING_RT_THREAD_HC08
bool "Enable Bluetooth"
default n
menuconfig BSP_USING_CH438
bool "Enable CH438"
if BSP_USING_CH438
config CONFIG_CH438_EXTUART0
bool "Enable CH438_EXTUART0"
default n
config CONFIG_CH438_EXTUART1
bool "Enable CH438_EXTUART1"
default n
config CONFIG_CH438_EXTUART2
bool "Enable CH438_EXTUART2"
default n
config CONFIG_CH438_EXTUART3
bool "Enable CH438_EXTUART3"
default n
config CONFIG_CH438_EXTUART4
bool "Enable CH438_EXTUART4"
default n
config CONFIG_CH438_EXTUART5
bool "Enable CH438_EXTUART5"
default n
config CONFIG_CH438_EXTUART6
bool "Enable CH438_EXTUART6"
default n
config CONFIG_CH438_EXTUART7
bool "Enable CH438_EXTUART7"
default n
config CH438_INT_PORT
int "ch438 Interrupt Port deafult 3"
range 0 7
default 3
endif
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_NETDEV

10
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-arm32/board/board.c
View File

@ -1091,7 +1091,15 @@ void rt_hw_board_init()
void rt_hw_us_delay(rt_uint32_t usec)
{
;
rt_uint32_t start, now, delta, reload, us_tick;
start = SysTick->VAL;
reload = SysTick->LOAD;
us_tick = SystemCoreClock / 1000000UL;
do {
now = SysTick->VAL;
delta = start > now ? start - now : reload + start - now;
} while(delta < us_tick * usec);
}
static int reboot(void)

1323
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-arm32/board/hardware/ch438/ch438.c Normal file
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File diff suppressed because it is too large Load Diff

413
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-arm32/board/hardware/ch438/ch438.h Normal file
View File

@ -0,0 +1,413 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_ch438.h
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.26
*/
#ifndef __CH438_H
#define __CH438_H
#undef FAR
#undef NEAR
#define FAR
#define NEAR
/****************************************************************************
* Included Files
****************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <errno.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <sched.h>
#include <assert.h>
#include <unistd.h>
#include <stdbool.h>
#include <string.h>
#include <stdlib.h>
#include <fcntl.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <board.h>
#include "fsl_gpio.h"
#include "drv_gpio.h"
#include "MIMXRT1052.h"
/*self define*/
/* output pin */
#define CH438_D_GPIO GPIO1
#define ZIGBEE_GPIO GPIO2
#define CH438_CTL_GPIO GPIO3
#define CH438_INT_IRQ GPIO3_Combined_0_15_IRQn
#define CH438_INT_IRQ_HANDLER GPIO3_Combined_0_15_IRQHandler
/* ch438 ctl pin */
#define CH438_NWR 68
#define CH438_NRD 69
#define CH438_ALE 66
#define CH438_INT 67
/* ch438 r/w pin*/
#define CH438_D0 25
#define CH438_D1 24
#define CH438_D2 20
#define CH438_D3 21
#define CH438_D4 31
#define CH438_D5 28
#define CH438_D6 30
#define CH438_D7 29
#ifdef CONFIG_CH438_EXTUART0
#define EXTU_UART_0 "dev0"
#endif
#ifdef CONFIG_CH438_EXTUART1
#define EXTU_UART_1 "dev1"
#endif
#ifdef CONFIG_CH438_EXTUART2
#define EXTU_UART_2 "dev2"
#endif
#ifdef CONFIG_CH438_EXTUART3
#define EXTU_UART_3 "dev3"
#endif
#ifdef CONFIG_CH438_EXTUART4
#define EXTU_UART_4 "dev4"
#endif
#ifdef CONFIG_CH438_EXTUART5
#define EXTU_UART_5 "dev5"
#endif
#ifdef CONFIG_CH438_EXTUART6
#define EXTU_UART_6 "dev6"
#endif
#ifdef CONFIG_CH438_EXTUART7
#define EXTU_UART_7 "dev7"
#endif
#define ZIGBEE_MODE_PIN (11U)
#define CH438_D0_PIN (25U)
#define CH438_D1_PIN (24U)
#define CH438_D2_PIN (20U)
#define CH438_D3_PIN (21U)
#define CH438_D4_PIN (31U)
#define CH438_D5_PIN (28U)
#define CH438_D6_PIN (30U)
#define CH438_D7_PIN (29U)
#define CH438_NWR_PIN (4U)
#define CH438_NRD_PIN (5U)
#define CH438_ALE_PIN (2U)
#define CH438_INT_PIN (3U)
#define EXAMPLE_DELAY_COUNT 5000
#define CH438PORTNUM 8
#define CH438_BUFFSIZE 256
#define CH438_INCREMENT MSEC2TICK(33)
#define CONFIG_CH438_EXTUART0_BAUD 115200
#define CONFIG_CH438_EXTUART1_BAUD 115200
#define CONFIG_CH438_EXTUART2_BAUD 9600
#define CONFIG_CH438_EXTUART3_BAUD 9600
#define CONFIG_CH438_EXTUART4_BAUD 115200
#define CONFIG_CH438_EXTUART5_BAUD 115200
#define CONFIG_CH438_EXTUART6_BAUD 115200
#define CONFIG_CH438_EXTUART7_BAUD 9600
#define OK 0
#define ERROR 1
/* chip definition */
/* CH438serial port0 register address */
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port3 register address */
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port5 register address */
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
#define BIT_IIR_FIFOENS1 0x80
#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */
/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */
#define BIT_LCR_WORDSZ0 0x01
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
#define Fpclk 1843200 /* Define the internal clock frequency*/
/* For Interrupt */
unsigned char CH438_CheckIIR(uint32_t iiraddr); /* Config serial port1interrupt identifies register function */
void CH438_INTConfig(uint32_t ieraddr,uint32_t iiraddr,uint32_t mcraddr); /* Serial interrupt enable function */
void Disable_Interrupt(void); /* Disable EXTI interrupt*/
void Config_Interrupt(void); /* Config EXTI interrupt*/
/* For RT-Thread Config */
static void Ch438Irq(void *parameter);
static rt_err_t rt_ch438_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
static rt_err_t rt_ch438_control(struct rt_serial_device *serial, int cmd, void *arg);
static int rt_ch438_putc(struct rt_serial_device *serial, char c);
static int rt_ch438_getc(struct rt_serial_device *serial);
int rt_hw_ch438_init(void);
int semaphoreChInit(void);
/* Delay */
void up_udelay(void);
void up_mdelay(uint32_t time);
void udelay(unsigned long usecs);
/* CH438 Config */
static void CH438SetOutput(void);
static void CH438SetInput(void);
static uint8_t ReadCH438Data(uint8_t addr);
static void WriteCH438Data(uint8_t addr, const uint8_t dat);
static void WriteCH438Block(uint8_t mAddr, uint8_t mLen, const uint8_t *mBuf);
static void Ch438UartSend(uint8_t ext_uart_no, const uint8_t *Data, uint16_t Num);
uint8_t CH438UARTRcv(uint8_t ext_uart_no, uint8_t *buf, size_t size);
static void ImxrtCH438Init(void);
static void CH438PortInit(uint8_t ext_uart_no, uint32_t baud_rate);
static int ImxrtCh438WriteData(uint8_t ext_uart_no, const uint8_t *write_buffer, size_t size);
static size_t ImxrtCh438ReadData(uint8_t ext_uart_no, size_t size);
static void Ch438InitDefault(void);
static int getCh438InterruptStatus(void );
/* CH438 Test Function */
void CH438Test(void);
void HC08Test(void);
void ZigBeeTest(void);
void CH438Init(void);
#endif

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61
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config
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@ -28,7 +28,9 @@ CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
#
# kservice optimization
@ -231,12 +233,23 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
# CONFIG_SAL_USING_POSIX is not set
CONFIG_SAL_SOCKETS_NUM=16
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
@ -280,25 +293,20 @@ CONFIG_BSP_USING_UART_HS=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI1 is not set
CONFIG_BSP_USING_SPI1=y
CONFIG_BSP_SPI1_CLK_PIN=9
CONFIG_BSP_SPI1_D0_PIN=11
CONFIG_BSP_SPI1_D1_PIN=10
CONFIG_BSP_SPI1_USING_SS0=y
CONFIG_BSP_SPI1_SS0_PIN=12
# CONFIG_BSP_SPI1_USING_SS1 is not set
# CONFIG_BSP_SPI1_USING_SS2 is not set
# CONFIG_BSP_SPI1_USING_SS3 is not set
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_LCD=y
CONFIG_BSP_LCD_CS_PIN=41
CONFIG_BSP_LCD_WR_PIN=38
CONFIG_BSP_LCD_DC_PIN=39
CONFIG_BSP_LCD_RST_PIN=37
CONFIG_BSP_LCD_BACKLIGHT_PIN=-1
CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set
CONFIG_BSP_LCD_CLK_FREQ=15000000
# CONFIG_BSP_BOARD_KD233 is not set
CONFIG_BSP_BOARD_K210_OPENMV_TEST=y
# CONFIG_BSP_BOARD_USER is not set
CONFIG_BSP_LCD_X_MAX=480
CONFIG_BSP_LCD_Y_MAX=272
# CONFIG_BSP_USING_LCD is not set
# CONFIG_BSP_USING_CH438 is not set
#
@ -318,6 +326,23 @@ CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
# CONFIG_DRV_USING_OV2640 is not set
# CONFIG_DRV_USING_HS300X is not set
# CONFIG_DRV_USING_SX1278 is not set
CONFIG_PKG_USING_WIZNET=y
CONFIG_PKG_WIZNET_PATH="/packages/iot/wiznet"
CONFIG_WIZ_USING_W5500=y
# CONFIG_WIZNET_DEVICE_EXTERN_CONFIG is not set
#
# WIZnet device configure
#
CONFIG_WIZ_SPI_DEVICE="spi10"
CONFIG_WIZ_RST_PIN=13
CONFIG_WIZ_IRQ_PIN=14
CONFIG_WIZ_USING_DHCP=y
CONFIG_WIZ_USING_PING=y
# CONFIG_WIZ_DEBUG is not set
# CONFIG_PKG_USING_WIZNET_V200 is not set
CONFIG_PKG_USING_WIZNET_LATEST_VERSION=y
CONFIG_PKG_WIZNET_VER="latest"
#
# APP_Framework

16
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/SConscript
View File

@ -1,9 +1,23 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
src = [
'main.c'
]
CPPPATH = [cwd]
## 设置 lcd_test.c 的依赖宏
if GetDepend('BSP_USING_LCD'):
src += ['lcd_test.c']
## 设置 tcp_client.c 和 tcp_server.c 的依赖宏
if GetDepend('PKG_USING_WIZNET'):
src += ['tcp_client.c']
src += ['tcp_server.c']
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

10
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/main.c
View File

@ -21,11 +21,11 @@
#include <rtthread.h>
#include <rtdevice.h>
#include <stdio.h>
#define LED_G 12
//#define LED_G 12
int main(void)
{
rt_pin_mode(LED_G, PIN_MODE_OUTPUT);
//rt_pin_mode(LED_G, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
char info1[25] ={0};
char info2[25] ={0};
@ -39,10 +39,10 @@ int main(void)
#endif
while(1)
{
rt_pin_write(LED_G, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_G, PIN_LOW);
//rt_pin_write(LED_G, PIN_HIGH);
rt_thread_mdelay(500);
//rt_pin_write(LED_G, PIN_LOW);
//rt_thread_mdelay(500);
}
return 0;
}

144
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/tcp_client.c Normal file
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@ -0,0 +1,144 @@
/*
* 程序清单：tcp 客户端
*
* 这是一个 tcp 客户端的例程
* 导出 tcpclient 命令到控制终端
* 命令调用格式：tcpclient URL PORT
* URL：服务器地址 PORT:：端口号
* 程序功能：接收并显示从服务端发送过来的信息，接收到开头是 'q' 或 'Q' 的信息退出程序
* Created by Ybeichen on 2022/7/28.
*/
#include "tcp_client.h"
#include <rtthread.h>
#include <wiz_socket.h> /* 使用BSD socket，需要包含socket.h头文件 */
#include <netdb.h>
#include <stdlib.h>
#define BUFSZ 1024
static const char send_data[] = "This is TCP Client from RT-Thread."; /* 发送用到的数据 */
static void tcp_client(int argc, char **argv)
{
int ret;
char *recv_data;
struct hostent *host;
int sock, bytes_received;
struct sockaddr_in server_addr;
const char *url;
int port;
if (argc < 3)
{
rt_kprintf("Usage: tcp_client URL PORT\n");
rt_kprintf("Like: tcp_client 192.168.12.44 5000\n");
return ;
}
url = argv[1];
port = strtoul(argv[2], 0, 10);
/* 通过函数入口参数url获得host地址（如果是域名，会做域名解析） */
host = gethostbyname(url);
/* 分配用于存放接收数据的缓冲 */
recv_data = rt_malloc(BUFSZ);
if (recv_data == RT_NULL)
{
rt_kprintf("No memory\n");
return;
}
/* 创建一个socket，类型是SOCKET_STREAM，TCP类型 */
if ((sock = socket(AF_WIZ, SOCK_STREAM, 0)) == -1)
{
/* 创建socket失败 */
rt_kprintf("Socket error\n");
/* 释放已分配的接收缓冲 */
rt_free(recv_data);
return;
}
/* 初始化预连接的服务端地址 */
server_addr.sin_family = AF_WIZ;
server_addr.sin_port = htons(port);
server_addr.sin_addr = *((struct in_addr *)host->h_addr);
rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
/* 连接到服务端 */
if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1)
{
/* 连接失败 */
rt_kprintf("Connect fail!\n");
closesocket(sock);
/*释放接收缓冲 */
rt_free(recv_data);
return;
}
while (1)
{
/* 从sock连接中接收最大BUFSZ - 1字节数据 */
bytes_received = recv(sock, recv_data, BUFSZ - 1, 0);
if (bytes_received < 0)
{
/* 接收失败，关闭这个连接 */
closesocket(sock);
rt_kprintf("\nreceived error,close the socket.\r\n");
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
else if (bytes_received == 0)
{
/* 默认 recv 为阻塞模式，此时收到0认为连接出错，关闭这个连接 */
closesocket(sock);
rt_kprintf("\nreceived error,close the socket.\r\n");
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
/* 有接收到数据，把末端清零 */
recv_data[bytes_received] = '\0';
if (strncmp(recv_data, "q", 1) == 0 || strncmp(recv_data, "Q", 1) == 0)
{
/* 如果是首字母是q或Q，关闭这个连接 */
closesocket(sock);
rt_kprintf("\n got a 'q' or 'Q',close the socket.\r\n");
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
else
{
/* 在控制终端显示收到的数据 */
rt_kprintf("\nReceived data = %s ", recv_data);
}
/* 发送数据到sock连接 */
ret = send(sock, send_data, strlen(send_data), 0);
if (ret < 0)
{
/* 接收失败，关闭这个连接 */
closesocket(sock);
rt_kprintf("\nsend error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (ret == 0)
{
/* 打印send函数返回值为0的警告信息 */
rt_kprintf("\n Send warning,send function return 0.\r\n");
}
}
return;
}
MSH_CMD_EXPORT(tcp_client, a tcp client sample);

11
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/tcp_client.h Normal file
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@ -0,0 +1,11 @@
//
// Created by Y北辰 on 2022/7/28.
//
#ifndef RT_THREAD_FUSION_XIUOS_TCP_CLIENT_H
#define RT_THREAD_FUSION_XIUOS_TCP_CLIENT_H
static void tcpclient(int argc, char **argv);
#endif //RT_THREAD_FUSION_XIUOS_TCP_CLIENT_H

174
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/tcp_server.c Normal file
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@ -0,0 +1,174 @@
/*
* 程序清单：tcp 服务端
*
* 这是一个 tcp 服务端的例程
* 导出 tcp_server 命令到控制终端
* 命令调用格式：tcp_server
* 无参数
* 程序功能：作为一个服务端，接收并显示客户端发来的数据 ，接收到 exit 退出程序
* Created by Ybeichen on 2022/7/28.
*/
#include "tcp_server.h"
#include <rtthread.h>
#include <wiz_socket.h> /* 使用BSD socket，需要包含socket.h头文件 */
#include "netdb.h"
#include <rtdef.h>
#include <errno.h>
#define BUFSZ (2048)
static int port = 5000;
static int is_running = 0; /* 停止标志 */
static const char send_data[] = "This is TCP Server from RT-Thread."; /* 发送用到的数据 */
static void tcp_server(void *argr)
{
char *recv_data; /* 用于接收的指针，后面会做一次动态分配以请求可用内存 */
socklen_t sin_size;
int sock, connected, bytes_received;
struct sockaddr_in server_addr, client_addr;
int ret;
recv_data = rt_malloc(BUFSZ + 1); /* 分配接收用的数据缓冲 */
if (recv_data == RT_NULL)
{
rt_kprintf("No memory\n");
return;
}
/* 创建一个socket，类型是SOCKET_STREAM，TCP类型 */
if ((sock = socket(AF_WIZ, SOCK_STREAM, IPPROTO_TCP)) == -1)
{
/* 创建socket失败 */
rt_kprintf("Socket error\n");
/* 释放已分配的接收缓冲 */
rt_free(recv_data);
return;
}
/* 初始化本地服务端地址 */
server_addr.sin_family = AF_WIZ;
server_addr.sin_port = htons(port); /* 服务端工作的端口 */
server_addr.sin_addr.s_addr = INADDR_ANY;
rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
/* 绑定socket到服务端地址 */
if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1)
{
/* 绑定失败 */
rt_kprintf("Unable to bind\n");
/* 释放已分配的接收缓冲 */
rt_free(recv_data);
return;
}
/* 在socket上进行监听 */
if (listen(sock, 5) == -1)
{
rt_kprintf("Listen error\n");
/* release recv buffer */
rt_free(recv_data);
return;
}
rt_kprintf("\nTCPServer Waiting for client on port %d...\n", port);
is_running=1;
while (is_running)
{
/* 接受一个客户端连接socket的请求，这个函数调用是阻塞式的 */
connected = accept(sock, (struct sockaddr *)&client_addr, (socklen_t *)sizeof(struct sockaddr_in));
/* 返回的是连接成功的socket */
if (connected < 0)
{
rt_kprintf("accept connection failed! errno = %d\n", errno);
/* release recv buffer */
rt_free(recv_data);
continue;
}
/* 接受返回的client_addr指向了客户端的地址信息 */
rt_kprintf("I got a connection from (%s , %d)\n",
inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port));
/* 客户端连接的处理 */
while (is_running)
{
/* 发送数据到connected socket */
ret = send(connected, send_data, strlen(send_data), 0);
if (ret < 0)
{
/* 发送失败，关闭这个连接 */
rt_kprintf("\nsend error,close the socket.\r\n");
closesocket(connected);
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
else if (ret == 0)
{
/* 打印send函数返回值为0的警告信息 */
rt_kprintf("\n Send warning,send function return 0.\r\n");
}
/* 从connected socket中接收数据，接收buffer是1024大小，但并不一定能够收到1024大小的数据 */
bytes_received = recv(connected, recv_data, BUFSZ, 0);
if (bytes_received < 0)
{
/* 接收失败，关闭这个connected socket */
rt_kprintf("\nReceived error, close the connect.\r\n");
closesocket(connected);
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
else if (bytes_received == 0)
{
/* 打印recv函数返回值为0的警告信息 */
rt_kprintf("\nReceived warning,recv function return 0.\r\n");
closesocket(connected);
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
/* 有接收到数据，把末端清零 */
recv_data[bytes_received] = '\0';
if (strncmp(recv_data, "q", 1) == 0 || strncmp(recv_data, "Q", 1) == 0)
{
/* 如果是首字母是q或Q，关闭这个连接 */
rt_kprintf("\nGot a 'q' or 'Q', close the connect.\r\n");
closesocket(connected);
/* 释放接收缓冲 */
rt_free(recv_data);
break;
}
else if (strcmp(recv_data, "exit") == 0)
{
/* 如果接收的是exit，则关闭整个服务端 */
closesocket(connected);
is_running=0;
break;
}
else
{
/* 在控制终端显示收到的数据 */
rt_kprintf("RECEIVED DATA = %s \n", recv_data);
}
}
}
/* 退出服务 */
closesocket(sock);
/* 释放接收缓冲 */
rt_free(recv_data);
return;
}
MSH_CMD_EXPORT(tcp_server, a tcp server sample);

11
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/tcp_server.h Normal file
View File

@ -0,0 +1,11 @@
//
// Created by Y北辰 on 2022/7/28.
//
#ifndef RT_THREAD_FUSION_XIUOS_TCP_SERVER_H
#define RT_THREAD_FUSION_XIUOS_TCP_SERVER_H
static void tcp_server(void *argr);
#endif //RT_THREAD_FUSION_XIUOS_TCP_SERVER_H

41
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h
View File

@ -25,6 +25,9 @@
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 2048
/* kservice optimization */
@ -143,9 +146,19 @@
/* Socket abstraction layer */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
#define SAL_SOCKETS_NUM 16
/* Network interface device */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* light weight TCP/IP stack */
@ -168,20 +181,15 @@
#define __STACKSIZE__ 4096
#define BSP_USING_UART_HS
#define BSP_USING_SPI1
#define BSP_SPI1_CLK_PIN 9
#define BSP_SPI1_D0_PIN 11
#define BSP_SPI1_D1_PIN 10
#define BSP_SPI1_USING_SS0
#define BSP_SPI1_SS0_PIN 12
/* Onboard Peripheral Drivers */
#define BSP_USING_LCD
#define BSP_LCD_CS_PIN 41
#define BSP_LCD_WR_PIN 38
#define BSP_LCD_DC_PIN 39
#define BSP_LCD_RST_PIN 37
#define BSP_LCD_BACKLIGHT_PIN -1
#define BSP_LCD_BACKLIGHT_ACTIVE_LOW
#define BSP_LCD_CLK_FREQ 15000000
#define BSP_BOARD_K210_OPENMV_TEST
#define BSP_LCD_X_MAX 272
#define BSP_LCD_Y_MAX 480
/* Kendryte SDK Config */
@ -192,6 +200,17 @@
/* More Drivers */
#define PKG_USING_WIZNET
#define WIZ_USING_W5500
/* WIZnet device configure */
#define WIZ_SPI_DEVICE "spi10"
#define WIZ_RST_PIN 13
#define WIZ_IRQ_PIN 14
#define WIZ_USING_DHCP
#define WIZ_USING_PING
#define PKG_USING_WIZNET_LATEST_VERSION
/* APP_Framework */

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1
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@ -4,4 +4,5 @@ source "$RT_Thread_DIR/app_match_rt-thread/rw007/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/ov2640/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/hs300x/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/sx1278/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/wiznet/Kconfig"
endmenu

112
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@ -0,0 +1,112 @@
# Kconfig file for package wiznet
menuconfig PKG_USING_WIZNET
bool "WIZnet: WIZnet TCP/IP chips SAL framework implement"
default n
select RT_USING_PIN
select RT_USING_SPI
select RT_USING_LIBC if RT_VER_NUM < 0x40100
select RT_USING_SAL
select RT_USING_TIMER_SOFT
if PKG_USING_WIZNET
config PKG_WIZNET_PATH
string
default "/packages/iot/wiznet"
choice
prompt "WIZnet device type"
default WIZ_USING_W5500
help
Select the wiznet type
config WIZ_USING_W5500
bool "W5500"
endchoice
config WIZNET_DEVICE_EXTERN_CONFIG
bool
default n
if !WIZNET_DEVICE_EXTERN_CONFIG
menu "WIZnet device configure"
config WIZ_SPI_DEVICE
string "SPI device name"
default "spi10"
config WIZ_RST_PIN
int "Reset PIN number"
default 10
config WIZ_IRQ_PIN
int "IRQ PIN number"
default 11
endmenu
endif
config WIZ_USING_DHCP
bool "Enable alloc IP address through DHCP"
default y
if !WIZ_USING_DHCP
menu "WIZnet network configure"
config WIZ_IPADDR
string "IPv4: IP address"
default 192.168.1.10
config WIZ_GWADDR
string "IPv4: Gateway address"
default 192.168.1.1
config WIZ_MSKADDR
string "IPv4: Mask address"
default 255.255.255.0
endmenu
endif
config WIZ_USING_PING
bool "Enable Ping utility"
default y
config WIZ_DEBUG
bool "Enable debug log output"
default n
choice
prompt "Version"
default PKG_USING_WIZNET_V110 if ((RT_VER_NUM < 0x30103) || (RT_VER_NUM = 0x40000))
default PKG_USING_WIZNET_LATEST_VERSION
help
Select the wiznet version
config PKG_USING_WIZNET_V200
bool "v2.0.0"
if ((RT_VER_NUM < 0x30103) || (RT_VER_NUM = 0x40000))
config PKG_USING_WIZNET_V110
bool "v1.1.0"
config PKG_USING_WIZNET_V100
bool "v1.0.0"
endif
config PKG_USING_WIZNET_LATEST_VERSION
bool "latest"
endchoice
config PKG_WIZNET_VER
string
default "v2.0.0" if PKG_USING_WIZNET_V200
default "v1.1.0" if PKG_USING_WIZNET_V110
default "v1.0.0" if PKG_USING_WIZNET_V100
default "latest" if PKG_USING_WIZNET_LATEST_VERSION
endif

201
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@ -0,0 +1,201 @@
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164
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@ -0,0 +1,164 @@
# WIZnet
[中文页](README_ZH.md) | English
## 1. Introduction
The WIZnet software package is a porting implementation of RT-Thread based on the WIZnet official website [ioLibrary_Driver](https://github.com/Wiznet/ioLibrary_Driver) code base, and currently only supports W5500 devices. On the basis of the original code library function, this software package docks with the RT-Thread SAL socket abstraction layer, realizes the support for standard BSD Socket APIs, is perfectly compatible with a variety of software packages and network functions, and improves the compatibility of WIZnet devices.
### 1.1 Directory structure
The WIZnet software package directory structure is as follows:
```
wiznet
├───inc // RT_Thread transplant header file
├───iolibrary // WIZnet official library file
│ └───Ethernet // WIZnet official Socket APIs and WIZCHIP driver
│ │ └───W5500 // WIZCHIP driver
│ │ wizchip_conf.c // Socket configuration file
│ │ wizchip_socket.c // Socket APIs file
│ └───Internet // WIZnet official network function realization
│ │ └───DHCP // DHCP function implementation
│ └───────DNS // DNS function realization
├───src // RT_Thread transplant source code file
│ └───wiz_af_inet.c // WIZnet BSD Socket registered to SAL
│ │ wiz_device.c // WIZnet device initialization
│ │ wiz_ping.c // WIZnet device Ping command realization
│ │ wiz_socket.c // WIZnet BSD Socket APIs implementation
│ └───wiz.c // WIZnet initialization (device initialization, network initialization)
│ LICENSE // package license
│ README.md // Software package instructions
└───SConscript // RT-Thread default build script
```
### 1.2 License
The WIZnet software package complies with the Apache-2.0 license, see the LICENSE file for details.
### 1.3 Dependency
- RT-Thread 4.0.1+
- SAL component
- netdev component
- SPI driver: WIZnet devices use SPI for data communication, which requires the support of the system SPI driver framework;
- PIN driver: used to handle device reset and interrupt pins;
## 2. Get the software package
To use the WIZnet software package, you need to select it in the RT-Thread package management. The specific path is as follows:
```shell
WIZnet: WIZnet TCP/IP chips SAL framework implement
WIZnet device type (W5500) --->
WIZnet device configure --->
(spi30) SPI device name
(10) Reset PIN number
(11) IRQ PIN number
[] Enable alloc IP address through DHCP
WIZnet network configure --->
(192.168.1.10) IPv4: IP address
(192.168.1.1) IPv4: Gateway address
(255.255.255.0) IPv4: Mask address
[] Enable Ping utility
[] Enable debug log output
Version (latest) --->
```
**WIZnet device type**: Configure the supported device type (currently only supports W5500 devices)
**WIZnet device configure**: configure the parameters of the device used
- **SPI device name**: Configure the name of the device using SPI (note that it needs to be set to **non-SPI bus device**)
- **Reset PIN number**: Configure the reset pin number connected to the device (modified according to the actual pin number used)
- **IRQ PIN number**: Configure the interrupt pin number of the device connection (same as above)
**Enable alloc IP address through DHCP**: Configure whether to use DHCP to allocate IP addresses (enabled by default)
**WIZnet network configure**: If you do not enable the DHCP function, you need to configure the statically connected IP address, gateway and subnet mask
**Enable Ping utility**: Configure to enable Ping command (enabled by default)
**Enable debug log output**: Configure to enable debug log display
**Version**: software package version selection
## 3. Use the software package
The initialization function of WIZnet software package is as follows:
```c
int wiz_init(void);
```
This function supports component initialization. If the automatic component initialization function is enabled, the application layer does not need to call this function. The main functions of the function are:
- Set the default MAC address;
- Device configuration and initialization (configure SPI device, configure reset and interrupt pins);
- Network configuration and initialization (DHCP allocation of IP address, configuration of socket parameters);
- Register the implemented BSD Socket APIs to the SAL socket abstraction layer to complete WIZnet device adaptation;
Each WIZnet device needs a unique MAC address. The user can call the following function in the application layer program to set the MAC address of the WIZnet device. If this function is not called, the device will use the default MAC address. The default MAC address is `00-E0-81 -DC-53-1A` (Note: If there are devices with the same MAC address in the same LAN, it may cause the device network to be abnormal).
```c
int wiz_set_mac(const char *mac);
```
After the device is powered on and initialized, the device's MAC address is successfully set, and then you can enter the command `wiz_ifconfig` in FinSH to view the device's IP address, MAC address and other network information, as shown below:
```shell
msh />ifconfig
network interface device: W5500 (Default) ## Device name
MTU: 1472 ## Network maximum transmission unit
MAC: 00 e0 81 dc 53 1a ## Device MAC address
FLAGS: UP LINK_UP INTERNET_UP ## Device flag
ip address: 192.168.12.26 ## Device IP address
gw address: 192.168.10.1 ## Device gateway address
net mask: 255.255.0.0 ## Device subnet mask
dns server #0: 192.168.10.1 ## DNS server address 0
dns server #1: 0.0.0.0 ## DNS server address 1
```
After obtaining the IP address successfully, if the Ping command function is enabled, you can enter the command `ping + domain name address` in FinSH to test the network connection status, as shown below:
```shell
msh />wiz_ping baidu.com
32 bytes from 220.181.57.216 icmp_seq=0 ttl=128 time=31 ticks
32 bytes from 220.181.57.216 icmp_seq=1 ttl=128 time=31 ticks
32 bytes from 220.181.57.216 icmp_seq=2 ttl=128 time=32 ticks
32 bytes from 220.181.57.216 icmp_seq=3 ttl=128 time=32 ticks
```
The normal test of the `ping` command indicates that the WIZnet device is successfully connected to the network, and then you can use the standard BSD Socket APIs abstracted by SAL (Socket Abstraction Layer) for network development (MQTT, HTTP, MbedTLS, NTP, Iperf, etc.), WIZnet software package The supported protocol cluster types are: the primary protocol cluster is **AF_WIZ**, and the secondary protocol cluster is **AF_INET** (for specific differences and usage, please refer to [SAL Programming Guide](https://www.rt-thread.org/document/site/submodules/rtthread-manual-doc/zh/1chapters/13-chapter_sal/) ).
## 4. Common problems
- Assertion problem during SPI device initialization
```shell
(wiz_device->parent.type == RT_Device_Class_SPIDevice) assertion failed at function:wiz_spi_init, line number:126
```
The above assertion problem occurs. The possible reason is that the name of the SPI device used by WIZnet in ENV is incorrectly filled. Please distinguish the relationship between SPI DEVICE and SPI BUS. If there is no SPI device or only SPI bus device in the BSP project, you need to manually mount the SPI device to the SPI bus in the driver and correctly configure the SPI device name used in the WIZnet software package.
- The latest version of WIZnet software package has been supported as a server server mode (not supported before V1.1.0).
- WIZNet software package initialization error ```[E/wiz.dev] You should attach [wiznet] into SPI bus firstly.``` error is caused by not mounting the winzet device to the SPI bus; please refer to the wiz_init function Note to solve the problem of package initialization failure.
- When using the previous code in the RT-Thread repository, please compare ```[components/net/sal_socket/src/sal_socket.c]```, especially about the content of [PR](https://github.com/RT-Thread/rt-thread/pull/3534/files), pay attention to the content of sal_closesocket . When you always fail to apply for socket(-1), please make sure that the RT-Thread code you are using is the same as the [PR](https://github.com/RT-Thread/rt-thread/pull/3534 /files).
- When applying for a socket, the error is ```0x22```. Note that the development branch of wiznet is in the master version or a version greater than V1.1.0. Please pay attention to the execution order of ```wiz_socket_init()```, because the ```sal_check_netdev_internet_up``` networking detection function will actively apply for a socket to determine whether the w5500 has network capabilities, and network status changes will cause ```sal_check_netdev_internet_up``` was called, causing ```0x22``` error.
## 5. Matters needing attention
- When obtaining the software package, you need to pay attention to the correct configuration of the SPI device name, reset pin number and interrupt pin number used;
- After the initialization is complete, it is recommended to use the `wiz_set_mac()` function to set the device MAC address to prevent conflicts with the default MAC address;
## 6. Contact & Thanks
- Maintenance: RT-Thread development team
- Homepage: https://github.com/RT-Thread-packages/wiznet

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# WIZnet
中文页 | [English](README.md)
## 1、介绍
WIZnet 软件包是 RT-Thread 基于 WIZnet 官网 [ioLibrary_Driver](https://github.com/Wiznet/ioLibrary_Driver) 代码库的移植实现，目前只支持 W5500 设备。该软件包在原代码库功能的基础上，对接 RT-Thread SAL 套接字抽象层，实现对标准 BSD Socket APIs 的支持，完美的兼容多种软件包和网络功能实现，提高 WIZnet 设备兼容性。
### 1.1 目录结构
WIZnet 软件包目录结构如下所示：
```
wiznet
├───inc // RT_Thread 移植头文件
├───iolibrary // WIZnet 官方库文件
│ └───Ethernet // WIZnet 官方 Socket APIs 和 WIZCHIP 驱动
│ │ └───W5500 // WIZCHIP 驱动
│ │ wizchip_conf.c // Socket 配置文件
│ │ wizchip_socket.c // Socket APIs 文件
│ └───Internet // WIZnet 官方网络功能实现
│ │ └───DHCP // DHCP 功能实现
│ └───────DNS // DNS 功能实现
├───src // RT_Thread 移植源码文件
│ └───wiz_af_inet.c // WIZnet BSD Socket 注册到 SAL
│ │ wiz_device.c // WIZnet 设备初始化
│ │ wiz_ping.c // WIZnet 设备 Ping 命令实现
│ │ wiz_socket.c // WIZnet BSD Socket APIs 实现
│ └───wiz.c // WIZnet 初始化（设备初始化、网络初始化）
│ LICENSE // 软件包许可证
│ README.md // 软件包使用说明
└───SConscript // RT-Thread 默认的构建脚本
```
### 1.2 许可证
WIZnet 软件包遵循 Apache-2.0 许可，详见 LICENSE 文件。
### 1.3 依赖
- RT-Thread 4.0.1+
- SAL 组件
- netdev 组件
- SPI 驱动：WIZnet 设备使用 SPI 进行数据通讯，需要系统 SPI 驱动框架支持；
- PIN 驱动：用于处理设备复位和中断引脚；
## 2、获取软件包
使用 WIZnet 软件包需要在 RT-Thread 的包管理中选中它，具体路径如下：
```shell
WIZnet: WIZnet TCP/IP chips SAL framework implement
WIZnet device type (W5500) --->
WIZnet device configure --->
(spi30) SPI device name
(10) Reset PIN number
(11) IRQ PIN number
[ ] Enable alloc IP address through DHCP
WIZnet network configure --->
(192.168.1.10) IPv4: IP address
(192.168.1.1) IPv4: Gateway address
(255.255.255.0) IPv4: Mask address
[ ] Enable Ping utility
[ ] Enable debug log output
Version (latest) --->
```
**WIZnet device type** ：配置支持的设备类型（目前只支持 W5500 设备 ）
**WIZnet device configure** ：配置使用设备的参数
- **SPI device name**：配置使用 SPI 的设备名称（注意需设置为**非 SPI 总线设备**）
- **Reset PIN number**：配置设备连接的复位引脚号（根据实际使用引脚号修改）
- **IRQ PIN number**：配置设备连接的中断引脚号（同上）
**Enable alloc IP address through DHCP**： 配置是否使用 DHCP 分配 IP 地址（默认开启）
**WIZnet network configure**：如果不开启 DHCP 功能，需要配置静态连接的 IP 地址、网关和子网掩码
**Enable Ping utility**： 配置开启 Ping 命令 （默认开启）
**Enable debug log output**：配置开启调试日志显示
**Version**：软件包版本选择
## 3、使用软件包
WIZnet 软件包初始化函数如下所示：
```c
int wiz_init（void）；
```
该函数支持组件初始化，如果开启组件自动初始化功能，则应用层无需在调用该函数 ，函数主要完成功能有，
- 设置默认 MAC 地址；
- 设备配置和初始化（配置 SPI 设备，配置复位和中断引脚）；
- 网络配置和初始化（DHCP 分配 IP 地址，配置 socket 参数 ）；
- 注册实现的 BSD Socket APIs 到 SAL 套接字抽象层中，完成 WIZnet 设备适配；
每个 WIZnet 设备需要唯一的 MAC 地址，用户可以在应用层程序中调用如下函数设置 WIZnet 设备 MAC 地址，如果不调用该函数，设备将使用默认的 MAC 地址，默认 MAC 地址为 `00-E0-81-DC-53-1A`（注意：同一个局域网中如果存在相同 MAC 地址的设备，可能导致设备网络异常） 。
```c
int wiz_set_mac(const char *mac);
```
设备上电初始化完成，设置设备 MAC 地址成功，然后可以在 FinSH 中输入命令 `wiz_ifconfig` 查看设备 IP 地址、MAC 地址等网络信息，如下所示：
```shell
msh />ifconfig
network interface device: W5500 (Default) ## 设备名称
MTU: 1472 ## 网络最大传输单元
MAC: 00 e0 81 dc 53 1a ## 设备 MAC 地址
FLAGS: UP LINK_UP INTERNET_UP ## 设备标志
ip address: 192.168.12.26 ## 设备 IP 地址
gw address: 192.168.10.1 ## 设备网关地址
net mask : 255.255.0.0 ## 设备子网掩码
dns server #0: 192.168.10.1 ## 域名解析服务器地址0
dns server #1: 0.0.0.0 ## 域名解析服务器地址1
```
获取 IP 地址成功之后，如果开启 Ping 命令功能，可以在 FinSH 中输入命令 `ping + 域名地址` 测试网络连接状态， 如下所示：
```shell
msh />wiz_ping baidu.com
32 bytes from 220.181.57.216 icmp_seq=0 ttl=128 time=31 ticks
32 bytes from 220.181.57.216 icmp_seq=1 ttl=128 time=31 ticks
32 bytes from 220.181.57.216 icmp_seq=2 ttl=128 time=32 ticks
32 bytes from 220.181.57.216 icmp_seq=3 ttl=128 time=32 ticks
```
`ping` 命令测试正常说明 WIZnet 设备网络连接成功，之后可以使用 SAL（套接字抽象层） 抽象出来的标准 BSD Socket APIs 进行网络开发（MQTT、HTTP、MbedTLS、NTP、Iperf 等），WIZnet 软件包支持的协议簇类型为：主协议簇为 **AF_WIZ**、次协议簇为 **AF_INET**（具体区别和使用方式可查看 [SAL 编程指南](https://www.rt-thread.org/document/site/submodules/rtthread-manual-doc/zh/1chapters/13-chapter_sal/) ）。
## 4、常见问题
- SPI 设备初始化时断言问题
```shell
(wiz_device->parent.type == RT_Device_Class_SPIDevice) assertion failed at function:wiz_spi_init, line number:126
```
出现上述断言问题，可能原因是 ENV 中配置 WIZnet 使用的 SPI 设备名称填写不正确，请区分 SPI DEVICE 与 SPI BUS 的关系。如果 BSP 工程中没有 SPI 设备或者只有 SPI 总线设备，需要手动在驱动中挂载 SPI 设备到 SPI 总线，并正确配置 WIZnet 软件包中使用的 SPI 设备名称。
- WIZnet 软件包最新版本已支持作为 server 服务器模式（V1.1.0 版本之前不支持）。
- WIZNet 软件包初始化出现 ```[E/wiz.dev] You should attach [wiznet] into SPI bus firstly.```错误，是因为没有挂载 winzet 设备到 SPI 总线导致的；请参考 wiz_init 函数中的注释，解决软件包初始化失败的问题。
- 在使用 RT-Thread 仓库的既往代码时，请比对 ```[components/net/sal_socket/src/sal_socket.c]```的内容，尤其是关于此处 [PR](https://github.com/RT-Thread/rt-thread/pull/3534/files) 的内容，注意 sal_closesocket 的内容。当你总是申请 socket(-1) 失败时，请确保你所使用的 RT-Thread 的代码是与该 [PR](https://github.com/RT-Thread/rt-thread/pull/3534/files) 的意图相符合的。
- 当出现申请 socket 时错误为 ```0x22``` 错误，注意 wiznet 的开发分支处于 master 版本或者大于 V1.1.0 的版本。请留意 ```wiz_socket_init()``` 的执行顺序，因为 ```sal_check_netdev_internet_up``` 联网检测函数，会主动申请 socket 以判断 w5500 是否具有网络能力，而网络状态变更会导致 ```sal_check_netdev_internet_up``` 被调用，造成 ```0x22``` 错误。
## 5、注意事项
- 获取软件包时，需要注意正确配置使用的 SPI 设备名称、复位引脚号和中断引脚号；
- 初始化完成之后，建议使用 `wiz_set_mac()` 函数设置设备 MAC 地址，防止使用默认 MAC 地址产生冲突；
## 6、联系方式 & 感谢
- 维护：RT-Thread 开发团队
- 主页：https://github.com/RT-Thread-packages/wiznet

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from building import *
cwd = GetCurrentDir()
src = Split('''
src/wiz_af_inet.c
src/wiz_device.c
src/wiz_socket.c
src/wiz.c
''')
if GetDepend(['WIZ_USING_PING']):
src += Glob('src/wiz_ping.c')
src += Glob('ioLibrary/Ethernet/*.c')
src += Glob('ioLibrary/Internet/DNS/*.c')
if GetDepend(['WIZ_USING_DHCP']):
src += Glob('ioLibrary/Internet/DHCP/*.c')
if GetDepend(['WIZ_USING_W5500']):
src += Glob('ioLibrary/Ethernet/W5500/*.c')
CPPPATH = [
cwd + '/inc',
cwd + '/ioLibrary',
cwd + '/ioLibrary/Ethernet',
cwd + '/ioLibrary/Ethernet/W5500',
cwd + '/ioLibrary/Internet',
]
group = DefineGroup('WIZnet', src, depend = ['PKG_USING_WIZNET'], CPPPATH = CPPPATH)
Return('group')

40
Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/inc/wiz.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-26 chenyong first version
*/
#ifndef __WIZ_H__
#define __WIZ_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <rtthread.h>
#define WIZ_SW_VERSION "2.1.0"
#define WIZ_SW_VERSION_NUM 0x020100
#ifndef WIZ_SOCKETS_NUM
#define WIZ_SOCKETS_NUM 8
#endif
#ifndef WIZ_RX_MBOX_NUM
#define WIZ_RX_MBOX_NUM 10
#endif
/* WIZnet set chip MAC address */
void wiz_user_config_mac(char *mac_buf, rt_uint8_t buf_len);
/* WIZnet initialize device and network */
int wiz_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __WIZ_H__ */

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-26 chenyong first version
*/
#ifndef __WIZ_SOCKET_H__
#define __WIZ_SOCKET_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include <netdb.h>
#include <sys/socket.h>
#ifdef __cplusplus
extern "C" {
#endif
/* WIZnet socket magic word */
#define WIZ_SOCKET_MAGIC 0x3120
/* WIZnet Socket address family */
#ifndef AF_WIZ
#define AF_WIZ 46
#endif
struct wiz_socket;
/* A callback prototype to inform about events for wiznet socket */
typedef void (* wiz_socket_callback)(struct wiz_socket *conn, int event, uint16_t len);
struct wiz_clnt_info
{
int socket;
int state;
rt_slist_t list;
};
struct wiz_svr_info
{
int backlog;
rt_timer_t conn_tmr;
rt_mailbox_t conn_mbox;
rt_slist_t clnt_list;
};
struct wiz_socket
{
/* WIZnet socket magic word */
uint32_t magic;
int socket;
uint16_t port;
/* type of the WIZnet socket (TCP, UDP or RAW) */
uint8_t type;
/* current state of the WIZnet socket */
uint8_t state;
/* receive semaphore, received data release semaphore */
rt_sem_t recv_notice;
rt_mutex_t recv_lock;
/* timeout to wait for send or receive data in milliseconds */
int32_t recv_timeout;
int32_t send_timeout;
/* A callback function that is informed about events for this AT socket */
wiz_socket_callback callback;
struct sockaddr *remote_addr;
/* number of times data was received, set by event_callback() */
uint16_t rcvevent;
/* number of times data was ACKed (free send buffer), set by event_callback() */
uint16_t sendevent;
/* error happened for this socket, set by event_callback() */
uint16_t errevent;
/* server socket information */
struct wiz_svr_info *svr_info;
#ifdef SAL_USING_POSIX
rt_wqueue_t wait_head;
#endif
};
int wiz_socket(int domain, int type, int protocol);
int wiz_closesocket(int socket);
int wiz_shutdown(int socket, int how);
int wiz_listen(int socket, int backlog);
int wiz_bind(int socket, const struct sockaddr *name, socklen_t namelen);
int wiz_connect(int socket, const struct sockaddr *name, socklen_t namelen);
int wiz_accept(int socket, struct sockaddr *addr, socklen_t *addrlen);
int wiz_sendto(int socket, const void *dwiza, size_t size, int flags, const struct sockaddr *to, socklen_t tolen);
int wiz_send(int socket, const void *dwiza, size_t size, int flags);
int wiz_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *from, socklen_t *fromlen);
int wiz_recv(int socket, void *mem, size_t len, int flags);
int wiz_getsockopt(int socket, int level, int optname, void *optval, socklen_t *optlen);
int wiz_setsockopt(int socket, int level, int optname, const void *optval, socklen_t optlen);
struct hostent *wiz_gethostbyname(const char *name);
int wiz_getaddrinfo(const char *nodename, const char *servname, const struct addrinfo *hints, struct addrinfo **res);
void wiz_freeaddrinfo(struct addrinfo *ai);
/* get WIZnet socket object */
struct wiz_socket *wiz_get_socket(int socket);
/* WIZnet chip TCP/IP protocol register */
int wiz_inet_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __WIZ_SOCKET_H__ */

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//*****************************************************************************
//
//! \file w5500.c
//! \brief W5500 HAL Interface.
//! \version 1.0.2
//! \date 2013/10/21
//! \par Revision history
//! <2015/02/05> Notice
//! The version history is not updated after this point.
//! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
//! >> https://github.com/Wiznet/ioLibrary_Driver
//! <2014/05/01> V1.0.2
//! 1. Implicit type casting -> Explicit type casting. Refer to M20140501
//! Fixed the problem on porting into under 32bit MCU
//! Issued by Mathias ClauBen, wizwiki forum ID Think01 and bobh
//! Thank for your interesting and serious advices.
//! <2013/12/20> V1.0.1
//! 1. Remove warning
//! 2. WIZCHIP_READ_BUF WIZCHIP_WRITE_BUF in case _WIZCHIP_IO_MODE_SPI_FDM_
//! for loop optimized(removed). refer to M20131220
//! <2013/10/21> 1st Release
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
//#include <stdio.h>
#include "w5500.h"
#define _W5500_SPI_VDM_OP_ 0x00
#define _W5500_SPI_FDM_OP_LEN1_ 0x01
#define _W5500_SPI_FDM_OP_LEN2_ 0x02
#define _W5500_SPI_FDM_OP_LEN4_ 0x03
#if (_WIZCHIP_ == 5500)
////////////////////////////////////////////////////
uint8_t WIZCHIP_READ(uint32_t AddrSel)
{
uint8_t ret;
uint8_t spi_data[3];
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_VDM_OP_);
if(!WIZCHIP.IF.SPI._read_burst || !WIZCHIP.IF.SPI._write_burst) // byte operation
{
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
}
else // burst operation
{
spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
spi_data[2] = (AddrSel & 0x000000FF) >> 0;
WIZCHIP.IF.SPI._write_burst(spi_data, 3);
}
ret = WIZCHIP.IF.SPI._read_byte();
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
return ret;
}
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb )
{
uint8_t spi_data[4];
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_VDM_OP_);
//if(!WIZCHIP.IF.SPI._read_burst || !WIZCHIP.IF.SPI._write_burst) // byte operation
if(!WIZCHIP.IF.SPI._write_burst) // byte operation
{
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
WIZCHIP.IF.SPI._write_byte(wb);
}
else // burst operation
{
spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
spi_data[2] = (AddrSel & 0x000000FF) >> 0;
spi_data[3] = wb;
WIZCHIP.IF.SPI._write_burst(spi_data, 4);
}
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
}
void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
{
uint8_t spi_data[3];
uint16_t i;
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_VDM_OP_);
if(!WIZCHIP.IF.SPI._read_burst || !WIZCHIP.IF.SPI._write_burst) // byte operation
{
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
for(i = 0; i < len; i++)
pBuf[i] = WIZCHIP.IF.SPI._read_byte();
}
else // burst operation
{
spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
spi_data[2] = (AddrSel & 0x000000FF) >> 0;
WIZCHIP.IF.SPI._write_burst(spi_data, 3);
WIZCHIP.IF.SPI._read_burst(pBuf, len);
}
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
}
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
{
uint8_t spi_data[3];
uint16_t i;
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_VDM_OP_);
if(!WIZCHIP.IF.SPI._write_burst) // byte operation
{
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
for(i = 0; i < len; i++)
WIZCHIP.IF.SPI._write_byte(pBuf[i]);
}
else // burst operation
{
spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
spi_data[2] = (AddrSel & 0x000000FF) >> 0;
WIZCHIP.IF.SPI._write_burst(spi_data, 3);
WIZCHIP.IF.SPI._write_burst(pBuf, len);
}
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
}
uint16_t getSn_TX_FSR(uint8_t sn)
{
uint16_t val=0,val1=0;
do
{
val1 = WIZCHIP_READ(Sn_TX_FSR(sn));
val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
if (val1 != 0)
{
val = WIZCHIP_READ(Sn_TX_FSR(sn));
val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
}
}while (val != val1);
return val;
}
uint16_t getSn_RX_RSR(uint8_t sn)
{
uint16_t val=0,val1=0;
do
{
val1 = WIZCHIP_READ(Sn_RX_RSR(sn));
val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
if (val1 != 0)
{
val = WIZCHIP_READ(Sn_RX_RSR(sn));
val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
}
}while (val != val1);
return val;
}
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
{
uint16_t ptr = 0;
uint32_t addrsel = 0;
if(len == 0) return;
ptr = getSn_TX_WR(sn);
//M20140501 : implict type casting -> explict type casting
//addrsel = (ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
addrsel = ((uint32_t)ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
//
WIZCHIP_WRITE_BUF(addrsel,wizdata, len);
ptr += len;
setSn_TX_WR(sn,ptr);
}
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
{
uint16_t ptr = 0;
uint32_t addrsel = 0;
if(len == 0) return;
ptr = getSn_RX_RD(sn);
//M20140501 : implict type casting -> explict type casting
//addrsel = ((ptr << 8) + (WIZCHIP_RXBUF_BLOCK(sn) << 3);
addrsel = ((uint32_t)ptr << 8) + (WIZCHIP_RXBUF_BLOCK(sn) << 3);
//
WIZCHIP_READ_BUF(addrsel, wizdata, len);
ptr += len;
setSn_RX_RD(sn,ptr);
}
void wiz_recv_ignore(uint8_t sn, uint16_t len)
{
uint16_t ptr = 0;
ptr = getSn_RX_RD(sn);
ptr += len;
setSn_RX_RD(sn,ptr);
}
#endif

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//****************************************************************************/
//!
//! \file wizchip_conf.c
//! \brief WIZCHIP Config Header File.
//! \version 1.0.1
//! \date 2013/10/21
//! \par Revision history
//! <2015/02/05> Notice
//! The version history is not updated after this point.
//! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
//! >> https://github.com/Wiznet/ioLibrary_Driver
//! <2014/05/01> V1.0.1 Refer to M20140501
//! 1. Explicit type casting in wizchip_bus_readdata() & wizchip_bus_writedata()
// Issued by Mathias ClauBen.
//! uint32_t type converts into ptrdiff_t first. And then recoverting it into uint8_t*
//! For remove the warning when pointer type size is not 32bit.
//! If ptrdiff_t doesn't support in your complier, You should must replace ptrdiff_t into your suitable pointer type.
//! <2013/10/21> 1st Release
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************/
//A20140501 : for use the type - ptrdiff_t
#include <stddef.h>
//
#include "wizchip_conf.h"
/////////////
//M20150401 : Remove ; in the default callback function such as wizchip_cris_enter(), wizchip_cs_select() and etc.
/////////////
/**
* @brief Default function to enable interrupt.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_cris_enter(void) {};
void wizchip_cris_enter(void) {}
/**
* @brief Default function to disable interrupt.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_cris_exit(void) {};
void wizchip_cris_exit(void) {}
/**
* @brief Default function to select chip.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_cs_select(void) {};
void wizchip_cs_select(void) {}
/**
* @brief Default function to deselect chip.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_cs_deselect(void) {};
void wizchip_cs_deselect(void) {}
/**
* @brief Default function to read in direct or indirect interface.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//M20150601 : Rename the function for integrating with W5300
//uint8_t wizchip_bus_readbyte(uint32_t AddrSel) { return * ((volatile uint8_t *)((ptrdiff_t) AddrSel)); }
iodata_t wizchip_bus_readdata(uint32_t AddrSel) { return * ((volatile iodata_t *)((ptrdiff_t) AddrSel)); }
/**
* @brief Default function to write in direct or indirect interface.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//M20150601 : Rename the function for integrating with W5300
//void wizchip_bus_writebyte(uint32_t AddrSel, uint8_t wb) { *((volatile uint8_t*)((ptrdiff_t)AddrSel)) = wb; }
void wizchip_bus_writedata(uint32_t AddrSel, iodata_t wb) { *((volatile iodata_t*)((ptrdiff_t)AddrSel)) = wb; }
/**
* @brief Default function to read in SPI interface.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//uint8_t wizchip_spi_readbyte(void) {return 0;};
uint8_t wizchip_spi_readbyte(void) {return 0;}
/**
* @brief Default function to write in SPI interface.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_spi_writebyte(uint8_t wb) {};
void wizchip_spi_writebyte(uint8_t wb) {}
/**
* @brief Default function to burst read in SPI interface.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {};
void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {}
/**
* @brief Default function to burst write in SPI interface.
* @note This function help not to access wrong address. If you do not describe this function or register any functions,
* null function is called.
*/
//void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {};
void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {}
/**
* @\ref _WIZCHIP instance
*/
//
//M20150401 : For a compiler didnot support a member of structure
// Replace the assignment of struct members with the assingment of array
//
/*
_WIZCHIP WIZCHIP =
{
.id = _WIZCHIP_ID_,
.if_mode = _WIZCHIP_IO_MODE_,
.CRIS._enter = wizchip_cris_enter,
.CRIS._exit = wizchip_cris_exit,
.CS._select = wizchip_cs_select,
.CS._deselect = wizchip_cs_deselect,
.IF.BUS._read_byte = wizchip_bus_readbyte,
.IF.BUS._write_byte = wizchip_bus_writebyte
// .IF.SPI._read_byte = wizchip_spi_readbyte,
// .IF.SPI._write_byte = wizchip_spi_writebyte
};
*/
_WIZCHIP WIZCHIP =
{
_WIZCHIP_IO_MODE_,
_WIZCHIP_ID_ ,
{
wizchip_cris_enter,
wizchip_cris_exit
},
{
wizchip_cs_select,
wizchip_cs_deselect
},
{
{
//M20150601 : Rename the function
//wizchip_bus_readbyte,
//wizchip_bus_writebyte
wizchip_bus_readdata,
wizchip_bus_writedata
},
}
};
static uint8_t _DNS_[4]; // DNS server ip address
static dhcp_mode _DHCP_; // DHCP mode
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void))
{
if(!cris_en || !cris_ex)
{
WIZCHIP.CRIS._enter = wizchip_cris_enter;
WIZCHIP.CRIS._exit = wizchip_cris_exit;
}
else
{
WIZCHIP.CRIS._enter = cris_en;
WIZCHIP.CRIS._exit = cris_ex;
}
}
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void))
{
if(!cs_sel || !cs_desel)
{
WIZCHIP.CS._select = wizchip_cs_select;
WIZCHIP.CS._deselect = wizchip_cs_deselect;
}
else
{
WIZCHIP.CS._select = cs_sel;
WIZCHIP.CS._deselect = cs_desel;
}
}
//M20150515 : For integrating with W5300
//void reg_wizchip_bus_cbfunc(uint8_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, uint8_t wb))
void reg_wizchip_bus_cbfunc(iodata_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb))
{
while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_BUS_));
//M20150601 : Rename call back function for integrating with W5300
/*
if(!bus_rb || !bus_wb)
{
WIZCHIP.IF.BUS._read_byte = wizchip_bus_readbyte;
WIZCHIP.IF.BUS._write_byte = wizchip_bus_writebyte;
}
else
{
WIZCHIP.IF.BUS._read_byte = bus_rb;
WIZCHIP.IF.BUS._write_byte = bus_wb;
}
*/
if(!bus_rb || !bus_wb)
{
WIZCHIP.IF.BUS._read_data = wizchip_bus_readdata;
WIZCHIP.IF.BUS._write_data = wizchip_bus_writedata;
}
else
{
WIZCHIP.IF.BUS._read_data = bus_rb;
WIZCHIP.IF.BUS._write_data = bus_wb;
}
}
void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb))
{
while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
if(!spi_rb || !spi_wb)
{
WIZCHIP.IF.SPI._read_byte = wizchip_spi_readbyte;
WIZCHIP.IF.SPI._write_byte = wizchip_spi_writebyte;
}
else
{
WIZCHIP.IF.SPI._read_byte = spi_rb;
WIZCHIP.IF.SPI._write_byte = spi_wb;
}
}
// 20140626 Eric Added for SPI burst operations
void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len))
{
while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
if(!spi_rb || !spi_wb)
{
WIZCHIP.IF.SPI._read_burst = wizchip_spi_readburst;
WIZCHIP.IF.SPI._write_burst = wizchip_spi_writeburst;
}
else
{
WIZCHIP.IF.SPI._read_burst = spi_rb;
WIZCHIP.IF.SPI._write_burst = spi_wb;
}
}
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg)
{
#if _WIZCHIP_ == W5100S || _WIZCHIP_ == W5200 || _WIZCHIP_ == W5500
uint8_t tmp = 0;
#endif
uint8_t* ptmp[2] = {0,0};
switch(cwtype)
{
case CW_RESET_WIZCHIP:
wizchip_sw_reset();
break;
case CW_INIT_WIZCHIP:
if(arg != 0)
{
ptmp[0] = (uint8_t*)arg;
ptmp[1] = ptmp[0] + _WIZCHIP_SOCK_NUM_;
}
return wizchip_init(ptmp[0], ptmp[1]);
case CW_CLR_INTERRUPT:
wizchip_clrinterrupt(*((intr_kind*)arg));
break;
case CW_GET_INTERRUPT:
*((intr_kind*)arg) = wizchip_getinterrupt();
break;
case CW_SET_INTRMASK:
wizchip_setinterruptmask(*((intr_kind*)arg));
break;
case CW_GET_INTRMASK:
*((intr_kind*)arg) = wizchip_getinterruptmask();
break;
//M20150601 : This can be supported by W5200, W5500
//#if _WIZCHIP_ > W5100
#if (_WIZCHIP_ == W5200 || _WIZCHIP_ == W5500)
case CW_SET_INTRTIME:
setINTLEVEL(*(uint16_t*)arg);
break;
case CW_GET_INTRTIME:
*(uint16_t*)arg = getINTLEVEL();
break;
#endif
case CW_GET_ID:
((uint8_t*)arg)[0] = WIZCHIP.id[0];
((uint8_t*)arg)[1] = WIZCHIP.id[1];
((uint8_t*)arg)[2] = WIZCHIP.id[2];
((uint8_t*)arg)[3] = WIZCHIP.id[3];
((uint8_t*)arg)[4] = WIZCHIP.id[4];
((uint8_t*)arg)[5] = 0;
break;
#if _WIZCHIP_ == W5100S || _WIZCHIP_ == W5500
case CW_RESET_PHY:
wizphy_reset();
break;
case CW_SET_PHYCONF:
wizphy_setphyconf((wiz_PhyConf*)arg);
break;
case CW_GET_PHYCONF:
wizphy_getphyconf((wiz_PhyConf*)arg);
break;
case CW_GET_PHYSTATUS:
break;
case CW_SET_PHYPOWMODE:
return wizphy_setphypmode(*(uint8_t*)arg);
#endif
#if _WIZCHIP_ == W5100S || _WIZCHIP_ == W5200 || _WIZCHIP_ == W5500
case CW_GET_PHYPOWMODE:
tmp = wizphy_getphypmode();
if((int8_t)tmp == -1) return -1;
*(uint8_t*)arg = tmp;
break;
case CW_GET_PHYLINK:
tmp = wizphy_getphylink();
if((int8_t)tmp == -1) return -1;
*(uint8_t*)arg = tmp;
break;
#endif
default:
return -1;
}
return 0;
}
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg)
{
switch(cntype)
{
case CN_SET_NETINFO:
wizchip_setnetinfo((wiz_NetInfo*)arg);
break;
case CN_GET_NETINFO:
wizchip_getnetinfo((wiz_NetInfo*)arg);
break;
case CN_SET_NETMODE:
return wizchip_setnetmode(*(netmode_type*)arg);
case CN_GET_NETMODE:
*(netmode_type*)arg = wizchip_getnetmode();
break;
case CN_SET_TIMEOUT:
wizchip_settimeout((wiz_NetTimeout*)arg);
break;
case CN_GET_TIMEOUT:
wizchip_gettimeout((wiz_NetTimeout*)arg);
break;
default:
return -1;
}
return 0;
}
void wizchip_sw_reset(void)
{
uint8_t gw[4], sn[4], sip[4];
uint8_t mac[6];
//A20150601
#if _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_
uint16_t mr = (uint16_t)getMR();
setMR(mr | MR_IND);
#endif
//
getSHAR(mac);
getGAR(gw); getSUBR(sn); getSIPR(sip);
setMR(MR_RST);
getMR(); // for delay
//A2015051 : For indirect bus mode
#if _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_
setMR(mr | MR_IND);
#endif
//
setSHAR(mac);
setGAR(gw);
setSUBR(sn);
setSIPR(sip);
}
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize)
{
int8_t i;
#if _WIZCHIP_ < W5200
int8_t j;
#endif
int8_t tmp = 0;
wizchip_sw_reset();
if(txsize)
{
tmp = 0;
//M20150601 : For integrating with W5300
#if _WIZCHIP_ == W5300
for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
{
if(txsize[i] >= 64) return -1; //No use 64KB even if W5300 support max 64KB memory allocation
tmp += txsize[i];
if(tmp > 128) return -1;
}
if(tmp % 8) return -1;
#else
for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
{
tmp += txsize[i];
#if _WIZCHIP_ < W5200 //2016.10.28 peter add condition for w5100 and w5100s
if(tmp > 8) return -1;
#else
if(tmp > 16) return -1;
#endif
}
for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
{
#if _WIZCHIP_ < W5200 //2016.10.28 peter add condition for w5100
j = 0;
while((txsize[i] >> j != 1)&&(txsize[i] !=0)){j++;}
setSn_TXBUF_SIZE(i, j);
#else
setSn_TXBUF_SIZE(i, txsize[i]);
#endif
}
#endif
}
if(rxsize)
{
tmp = 0;
#if _WIZCHIP_ == W5300
for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
{
if(rxsize[i] >= 64) return -1; //No use 64KB even if W5300 support max 64KB memory allocation
tmp += rxsize[i];
if(tmp > 128) return -1;
}
if(tmp % 8) return -1;
#else
for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
{
tmp += rxsize[i];
#if _WIZCHIP_ < W5200 //2016.10.28 peter add condition for w5100 and w5100s
if(tmp > 8) return -1;
#else
if(tmp > 16) return -1;
#endif
}
for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
{
#if _WIZCHIP_ < W5200 // add condition for w5100
j = 0;
while((rxsize[i] >> j != 1)&&(txsize[i] !=0)){j++;}
setSn_RXBUF_SIZE(i, j);
#else
setSn_RXBUF_SIZE(i, rxsize[i]);
#endif
}
#endif
}
return 0;
}
void wizchip_clrinterrupt(intr_kind intr)
{
uint8_t ir = (uint8_t)intr;
uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
#if _WIZCHIP_ < W5500
ir |= (1<<4); // IK_WOL
#endif
#if _WIZCHIP_ == W5200
ir |= (1 << 6);
#endif
#if _WIZCHIP_ < W5200
sir &= 0x0F;
#endif
#if _WIZCHIP_ <= W5100S
ir |= sir;
setIR(ir);
//A20150601 : For integrating with W5300
#elif _WIZCHIP_ == W5300
setIR( ((((uint16_t)ir) << 8) | (((uint16_t)sir) & 0x00FF)) );
#else
setIR(ir);
//M20200227 : For clear
//setSIR(sir);
for(ir=0; ir<8; ir++){
if(sir & (0x01 <<ir) ) setSn_IR(ir, 0xff);
}
#endif
}
intr_kind wizchip_getinterrupt(void)
{
uint8_t ir = 0;
uint8_t sir = 0;
uint16_t ret = 0;
#if _WIZCHIP_ <= W5100S
ir = getIR();
sir = ir & 0x0F;
//A20150601 : For integrating with W5300
#elif _WIZCHIP_ == W5300
ret = getIR();
ir = (uint8_t)(ret >> 8);
sir = (uint8_t)ret;
#else
ir = getIR();
sir = getSIR();
#endif
//M20150601 : For Integrating with W5300
//#if _WIZCHIP_ < W5500
#if _WIZCHIP_ < W5200
ir &= ~(1<<4); // IK_WOL
#endif
#if _WIZCHIP_ == W5200
ir &= ~(1 << 6);
#endif
ret = sir;
ret = (ret << 8) + ir;
return (intr_kind)ret;
}
void wizchip_setinterruptmask(intr_kind intr)
{
uint8_t imr = (uint8_t)intr;
uint8_t simr = (uint8_t)((uint16_t)intr >> 8);
#if _WIZCHIP_ < W5500
imr &= ~(1<<4); // IK_WOL
#endif
#if _WIZCHIP_ == W5200
imr &= ~(1 << 6);
#endif
#if _WIZCHIP_ < W5200
simr &= 0x0F;
imr |= simr;
setIMR(imr);
//A20150601 : For integrating with W5300
#elif _WIZCHIP_ == W5300
setIMR( ((((uint16_t)imr) << 8) | (((uint16_t)simr) & 0x00FF)) );
#else
setIMR(imr);
setSIMR(simr);
#endif
}
intr_kind wizchip_getinterruptmask(void)
{
uint8_t imr = 0;
uint8_t simr = 0;
uint16_t ret = 0;
#if _WIZCHIP_ < W5200
imr = getIMR();
simr = imr & 0x0F;
//A20150601 : For integrating with W5300
#elif _WIZCHIP_ == W5300
ret = getIMR();
imr = (uint8_t)(ret >> 8);
simr = (uint8_t)ret;
#else
imr = getIMR();
simr = getSIMR();
#endif
#if _WIZCHIP_ < W5500
imr &= ~(1<<4); // IK_WOL
#endif
#if _WIZCHIP_ == W5200
imr &= ~(1 << 6); // IK_DEST_UNREACH
#endif
ret = simr;
ret = (ret << 8) + imr;
return (intr_kind)ret;
}
int8_t wizphy_getphylink(void)
{
int8_t tmp = PHY_LINK_OFF;
#if _WIZCHIP_ == W5100S
if(getPHYSR() & PHYSR_LNK)
tmp = PHY_LINK_ON;
#elif _WIZCHIP_ == W5200
if(getPHYSTATUS() & PHYSTATUS_LINK)
tmp = PHY_LINK_ON;
#elif _WIZCHIP_ == W5500
if(getPHYCFGR() & PHYCFGR_LNK_ON)
tmp = PHY_LINK_ON;
#else
tmp = -1;
#endif
return tmp;
}
#if _WIZCHIP_ > W5100
int8_t wizphy_getphypmode(void)
{
int8_t tmp = 0;
#if _WIZCHIP_ == W5200
if(getPHYSTATUS() & PHYSTATUS_POWERDOWN)
tmp = PHY_POWER_DOWN;
else
tmp = PHY_POWER_NORM;
#elif _WIZCHIP_ == 5500
if((getPHYCFGR() & PHYCFGR_OPMDC_ALLA) == PHYCFGR_OPMDC_PDOWN)
tmp = PHY_POWER_DOWN;
else
tmp = PHY_POWER_NORM;
#else
tmp = -1;
#endif
return tmp;
}
#endif
#if _WIZCHIP_ == W5100S
void wizphy_reset(void)
{
uint16_t tmp = wiz_mdio_read(PHYMDIO_BMCR);
tmp |= BMCR_RESET;
wiz_mdio_write(PHYMDIO_BMCR, tmp);
while(wiz_mdio_read(PHYMDIO_BMCR)&BMCR_RESET){}
}
void wizphy_setphyconf(wiz_PhyConf* phyconf)
{
uint16_t tmp = wiz_mdio_read(PHYMDIO_BMCR);
if(phyconf->mode == PHY_MODE_AUTONEGO)
tmp |= BMCR_AUTONEGO;
else
{
tmp &= ~BMCR_AUTONEGO;
if(phyconf->duplex == PHY_DUPLEX_FULL)
{
tmp |= BMCR_DUP;
}
else
{
tmp &= ~BMCR_DUP;
}
if(phyconf->speed == PHY_SPEED_100)
{
tmp |= BMCR_SPEED;
}
else
{
tmp &= ~BMCR_SPEED;
}
}
wiz_mdio_write(PHYMDIO_BMCR, tmp);
}
void wizphy_getphyconf(wiz_PhyConf* phyconf)
{
uint16_t tmp = 0;
tmp = wiz_mdio_read(PHYMDIO_BMCR);
phyconf->by = PHY_CONFBY_SW;
if(tmp & BMCR_AUTONEGO)
{
phyconf->mode = PHY_MODE_AUTONEGO;
}
else
{
phyconf->mode = PHY_MODE_MANUAL;
if(tmp&BMCR_DUP) phyconf->duplex = PHY_DUPLEX_FULL;
else phyconf->duplex = PHY_DUPLEX_HALF;
if(tmp&BMCR_SPEED) phyconf->speed = PHY_SPEED_100;
else phyconf->speed = PHY_SPEED_10;
}
}
int8_t wizphy_setphypmode(uint8_t pmode)
{
uint16_t tmp = 0;
tmp = wiz_mdio_read(PHYMDIO_BMCR);
if( pmode == PHY_POWER_DOWN)
{
tmp |= BMCR_PWDN;
}
else
{
tmp &= ~BMCR_PWDN;
}
wiz_mdio_write(PHYMDIO_BMCR, tmp);
tmp = wiz_mdio_read(PHYMDIO_BMCR);
if( pmode == PHY_POWER_DOWN)
{
if(tmp & BMCR_PWDN) return 0;
}
else
{
if((tmp & BMCR_PWDN) != BMCR_PWDN) return 0;
}
return -1;
}
#endif
#if _WIZCHIP_ == W5500
void wizphy_reset(void)
{
uint8_t tmp = getPHYCFGR();
tmp &= PHYCFGR_RST;
setPHYCFGR(tmp);
tmp = getPHYCFGR();
tmp |= ~PHYCFGR_RST;
setPHYCFGR(tmp);
}
void wizphy_setphyconf(wiz_PhyConf* phyconf)
{
uint8_t tmp = 0;
if(phyconf->by == PHY_CONFBY_SW)
tmp |= PHYCFGR_OPMD;
else
tmp &= ~PHYCFGR_OPMD;
if(phyconf->mode == PHY_MODE_AUTONEGO)
tmp |= PHYCFGR_OPMDC_ALLA;
else
{
if(phyconf->duplex == PHY_DUPLEX_FULL)
{
if(phyconf->speed == PHY_SPEED_100)
tmp |= PHYCFGR_OPMDC_100F;
else
tmp |= PHYCFGR_OPMDC_10F;
}
else
{
if(phyconf->speed == PHY_SPEED_100)
tmp |= PHYCFGR_OPMDC_100H;
else
tmp |= PHYCFGR_OPMDC_10H;
}
}
setPHYCFGR(tmp);
wizphy_reset();
}
void wizphy_getphyconf(wiz_PhyConf* phyconf)
{
uint8_t tmp = 0;
tmp = getPHYCFGR();
phyconf->by = (tmp & PHYCFGR_OPMD) ? PHY_CONFBY_SW : PHY_CONFBY_HW;
switch(tmp & PHYCFGR_OPMDC_ALLA)
{
case PHYCFGR_OPMDC_ALLA:
case PHYCFGR_OPMDC_100FA:
phyconf->mode = PHY_MODE_AUTONEGO;
break;
default:
phyconf->mode = PHY_MODE_MANUAL;
break;
}
switch(tmp & PHYCFGR_OPMDC_ALLA)
{
case PHYCFGR_OPMDC_100FA:
case PHYCFGR_OPMDC_100F:
case PHYCFGR_OPMDC_100H:
phyconf->speed = PHY_SPEED_100;
break;
default:
phyconf->speed = PHY_SPEED_10;
break;
}
switch(tmp & PHYCFGR_OPMDC_ALLA)
{
case PHYCFGR_OPMDC_100FA:
case PHYCFGR_OPMDC_100F:
case PHYCFGR_OPMDC_10F:
phyconf->duplex = PHY_DUPLEX_FULL;
break;
default:
phyconf->duplex = PHY_DUPLEX_HALF;
break;
}
}
void wizphy_getphystat(wiz_PhyConf* phyconf)
{
uint8_t tmp = getPHYCFGR();
phyconf->duplex = (tmp & PHYCFGR_DPX_FULL) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
phyconf->speed = (tmp & PHYCFGR_SPD_100) ? PHY_SPEED_100 : PHY_SPEED_10;
}
int8_t wizphy_setphypmode(uint8_t pmode)
{
uint8_t tmp = 0;
tmp = getPHYCFGR();
if((tmp & PHYCFGR_OPMD)== 0) return -1;
tmp &= ~PHYCFGR_OPMDC_ALLA;
if( pmode == PHY_POWER_DOWN)
tmp |= PHYCFGR_OPMDC_PDOWN;
else
tmp |= PHYCFGR_OPMDC_ALLA;
setPHYCFGR(tmp);
wizphy_reset();
tmp = getPHYCFGR();
if( pmode == PHY_POWER_DOWN)
{
if(tmp & PHYCFGR_OPMDC_PDOWN) return 0;
}
else
{
if(tmp & PHYCFGR_OPMDC_ALLA) return 0;
}
return -1;
}
#endif
void wizchip_setnetinfo(wiz_NetInfo* pnetinfo)
{
setSHAR(pnetinfo->mac);
setGAR(pnetinfo->gw);
setSUBR(pnetinfo->sn);
setSIPR(pnetinfo->ip);
_DNS_[0] = pnetinfo->dns[0];
_DNS_[1] = pnetinfo->dns[1];
_DNS_[2] = pnetinfo->dns[2];
_DNS_[3] = pnetinfo->dns[3];
_DHCP_ = pnetinfo->dhcp;
}
void wizchip_getnetinfo(wiz_NetInfo* pnetinfo)
{
getSHAR(pnetinfo->mac);
getGAR(pnetinfo->gw);
getSUBR(pnetinfo->sn);
getSIPR(pnetinfo->ip);
pnetinfo->dns[0]= _DNS_[0];
pnetinfo->dns[1]= _DNS_[1];
pnetinfo->dns[2]= _DNS_[2];
pnetinfo->dns[3]= _DNS_[3];
pnetinfo->dhcp = _DHCP_;
}
int8_t wizchip_setnetmode(netmode_type netmode)
{
uint8_t tmp = 0;
#if _WIZCHIP_ != W5500
if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK)) return -1;
#else
if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK | NM_FORCEARP)) return -1;
#endif
tmp = getMR();
tmp |= (uint8_t)netmode;
setMR(tmp);
return 0;
}
netmode_type wizchip_getnetmode(void)
{
return (netmode_type) getMR();
}
void wizchip_settimeout(wiz_NetTimeout* nettime)
{
setRCR(nettime->retry_cnt);
setRTR(nettime->time_100us);
}
void wizchip_gettimeout(wiz_NetTimeout* nettime)
{
nettime->retry_cnt = getRCR();
nettime->time_100us = getRTR();
}

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//*****************************************************************************
//
//! \file wizchip_conf.h
//! \brief WIZCHIP Config Header File.
//! \version 1.0.0
//! \date 2013/10/21
//! \par Revision history
//! <2015/02/05> Notice
//! The version history is not updated after this point.
//! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
//! >> https://github.com/Wiznet/ioLibrary_Driver
//! <2013/10/21> 1st Release
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
/**
* @defgroup extra_functions 2. WIZnet Extra Functions
*
* @brief These functions is optional function. It could be replaced at WIZCHIP I/O function because they were made by WIZCHIP I/O functions.
* @details There are functions of configuring WIZCHIP, network, interrupt, phy, network information and timer. \n
*
*/
#ifndef _WIZCHIP_CONF_H_
#define _WIZCHIP_CONF_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief Select WIZCHIP.
* @todo You should select one, \b W5100, \b W5100S, \b W5200, \b W5300, \b W5500 or etc. \n\n
* ex> <code> #define \_WIZCHIP_ W5500 </code>
*/
#define W5100 5100
#define W5100S 5100+5
#define W5200 5200
#define W5300 5300
#define W5500 5500
#ifndef _WIZCHIP_
#define _WIZCHIP_ W5500 // W5100, W5100S, W5200, W5300, W5500
#endif
#define _WIZCHIP_IO_MODE_NONE_ 0x0000
#define _WIZCHIP_IO_MODE_BUS_ 0x0100 /**< Bus interface mode */
#define _WIZCHIP_IO_MODE_SPI_ 0x0200 /**< SPI interface mode */
//#define _WIZCHIP_IO_MODE_IIC_ 0x0400
//#define _WIZCHIP_IO_MODE_SDIO_ 0x0800
// Add to
//
#define _WIZCHIP_IO_MODE_BUS_DIR_ (_WIZCHIP_IO_MODE_BUS_ + 1) /**< BUS interface mode for direct */
#define _WIZCHIP_IO_MODE_BUS_INDIR_ (_WIZCHIP_IO_MODE_BUS_ + 2) /**< BUS interface mode for indirect */
#define _WIZCHIP_IO_MODE_SPI_VDM_ (_WIZCHIP_IO_MODE_SPI_ + 1) /**< SPI interface mode for variable length data*/
#define _WIZCHIP_IO_MODE_SPI_FDM_ (_WIZCHIP_IO_MODE_SPI_ + 2) /**< SPI interface mode for fixed length data mode*/
#define _WIZCHIP_IO_MODE_SPI_5500_ (_WIZCHIP_IO_MODE_SPI_ + 3) /**< SPI interface mode for fixed length data mode*/
#if (_WIZCHIP_ == W5100)
#define _WIZCHIP_ID_ "W5100\0"
/**
* @brief Define interface mode.
* @todo you should select interface mode as chip. Select one of @ref \_WIZCHIP_IO_MODE_SPI_ , @ref \_WIZCHIP_IO_MODE_BUS_DIR_ or @ref \_WIZCHIP_IO_MODE_BUS_INDIR_
*/
// #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_DIR_
// #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_INDIR_
#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_
//A20150601 : Define the unit of IO DATA.
typedef uint8_t iodata_t;
//A20150401 : Indclude W5100.h file
#include "W5100/w5100.h"
#elif (_WIZCHIP_ == W5100S)
#define _WIZCHIP_ID_ "W5100S\0"
/**
* @brief Define interface mode.
* @todo you should select interface mode as chip. Select one of @ref \_WIZCHIP_IO_MODE_SPI_ , @ref \_WIZCHIP_IO_MODE_BUS_DIR_ or @ref \_WIZCHIP_IO_MODE_BUS_INDIR_
*/
// #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_INDIR_
//#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_5500_
#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_
//A20150601 : Define the unit of IO DATA.
typedef uint8_t iodata_t;
//A20150401 : Indclude W5100.h file
#include "W5100S/w5100s.h"
#elif (_WIZCHIP_ == W5200)
#define _WIZCHIP_ID_ "W5200\0"
/**
* @brief Define interface mode.
* @todo you should select interface mode as chip. Select one of @ref \_WIZCHIP_IO_MODE_SPI_ or @ref \ _WIZCHIP_IO_MODE_BUS_INDIR_
*/
#ifndef _WIZCHIP_IO_MODE_
// #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_INDIR_
#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_
#endif
//A20150601 : Define the unit of IO DATA.
typedef uint8_t iodata_t;
#include "W5200/w5200.h"
#elif (_WIZCHIP_ == W5500)
#define _WIZCHIP_ID_ "W5500\0"
/**
* @brief Define interface mode. \n
* @todo Should select interface mode as chip.
* - @ref \_WIZCHIP_IO_MODE_SPI_ \n
* -@ref \_WIZCHIP_IO_MODE_SPI_VDM_ : Valid only in @ref \_WIZCHIP_ == W5500 \n
* -@ref \_WIZCHIP_IO_MODE_SPI_FDM_ : Valid only in @ref \_WIZCHIP_ == W5500 \n
* - @ref \_WIZCHIP_IO_MODE_BUS_ \n
* - @ref \_WIZCHIP_IO_MODE_BUS_DIR_ \n
* - @ref \_WIZCHIP_IO_MODE_BUS_INDIR_ \n
* - Others will be defined in future. \n\n
* ex> <code> #define \_WIZCHIP_IO_MODE_ \_WIZCHIP_IO_MODE_SPI_VDM_ </code>
*
*/
#ifndef _WIZCHIP_IO_MODE_
//#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_FDM_
#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_VDM_
#endif
//A20150601 : Define the unit of IO DATA.
typedef uint8_t iodata_t;
#include "W5500/w5500.h"
#elif ( _WIZCHIP_ == W5300)
#define _WIZCHIP_ID_ "W5300\0"
/**
* @brief Define interface mode.
* @todo you should select interface mode as chip. Select one of @ref \_WIZCHIP_IO_MODE_SPI_ , @ref \_WIZCHIP_IO_MODE_BUS_DIR_ or @ref \_WIZCHIP_IO_MODE_BUS_INDIR_
*/
#ifndef _WIZCHIP_IO_MODE_
// #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_DIR_
#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_INDIR_
#endif
//A20150601 : Define the unit and bus width of IO DATA.
/**
* @brief Select the data width 8 or 16 bits.
* @todo you should select the bus width. Select one of 8 or 16.
*/
#ifndef _WIZCHIP_IO_BUS_WIDTH_
#define _WIZCHIP_IO_BUS_WIDTH_ 8 // 16
#endif
#if _WIZCHIP_IO_BUS_WIDTH_ == 8
typedef uint8_t iodata_t;
#elif _WIZCHIP_IO_BUS_WIDTH_ == 16
typedef uint16_t iodata_t;
#else
#error "Unknown _WIZCHIP_IO_BUS_WIDTH_. It should be 8 or 16."
#endif
//
#include "W5300/w5300.h"
#else
#error "Unknown defined _WIZCHIP_. You should define one of 5100, 5200, and 5500 !!!"
#endif
#ifndef _WIZCHIP_IO_MODE_
#error "Undefined _WIZCHIP_IO_MODE_. You should define it !!!"
#endif
/**
* @brief Define I/O base address when BUS IF mode.
* @todo Should re-define it to fit your system when BUS IF Mode (@ref \_WIZCHIP_IO_MODE_BUS_,
* @ref \_WIZCHIP_IO_MODE_BUS_DIR_, @ref \_WIZCHIP_IO_MODE_BUS_INDIR_). \n\n
* ex> <code> #define \_WIZCHIP_IO_BASE_ 0x00008000 </code>
*/
#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_
#define _WIZCHIP_IO_BASE_ 0x60000000 // for 5100S IND
#elif _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_
#define _WIZCHIP_IO_BASE_ 0x00000000 // for 5100S SPI
#endif
#ifndef _WIZCHIP_IO_BASE_
#define _WIZCHIP_IO_BASE_ 0x00000000 // 0x8000
#endif
//M20150401 : Typing Error
//#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS
#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_
#ifndef _WIZCHIP_IO_BASE_
#error "You should be define _WIZCHIP_IO_BASE to fit your system memory map."
#endif
#endif
#if _WIZCHIP_ >= W5200
#define _WIZCHIP_SOCK_NUM_ 8 ///< The count of independant socket of @b WIZCHIP
#else
#define _WIZCHIP_SOCK_NUM_ 4 ///< The count of independant socket of @b WIZCHIP
#endif
/********************************************************
* WIZCHIP BASIC IF functions for SPI, SDIO, I2C , ETC.
*********************************************************/
/**
* @ingroup DATA_TYPE
* @brief The set of callback functions for W5500:@ref WIZCHIP_IO_Functions W5200:@ref WIZCHIP_IO_Functions_W5200
*/
typedef struct __WIZCHIP
{
uint16_t if_mode; ///< host interface mode
uint8_t id[7]; ///< @b WIZCHIP ID such as @b 5100, @b 5200, @b 5500, and so on.
/**
* The set of critical section callback func.
*/
struct _CRIS
{
void (*_enter) (void); ///< crtical section enter
void (*_exit) (void); ///< critial section exit
}CRIS;
/**
* The set of @ref \_WIZCHIP_ select control callback func.
*/
struct _CS
{
void (*_select) (void); ///< @ref \_WIZCHIP_ selected
void (*_deselect)(void); ///< @ref \_WIZCHIP_ deselected
}CS;
/**
* The set of interface IO callback func.
*/
union _IF
{
/**
* For BUS interface IO
*/
//M20156501 : Modify the function name for integrating with W5300
//struct
//{
// uint8_t (*_read_byte) (uint32_t AddrSel);
// void (*_write_byte) (uint32_t AddrSel, uint8_t wb);
//}BUS;
struct
{
iodata_t (*_read_data) (uint32_t AddrSel);
void (*_write_data) (uint32_t AddrSel, iodata_t wb);
}BUS;
/**
* For SPI interface IO
*/
struct
{
uint8_t (*_read_byte) (void);
void (*_write_byte) (uint8_t wb);
void (*_read_burst) (uint8_t* pBuf, uint16_t len);
void (*_write_burst) (uint8_t* pBuf, uint16_t len);
}SPI;
// To be added
//
}IF;
}_WIZCHIP;
extern _WIZCHIP WIZCHIP;
/**
* @ingroup DATA_TYPE
* WIZCHIP control type enumration used in @ref ctlwizchip().
*/
typedef enum
{
CW_RESET_WIZCHIP, ///< Resets WIZCHIP by softly
CW_INIT_WIZCHIP, ///< Initializes to WIZCHIP with SOCKET buffer size 2 or 1 dimension array typed uint8_t.
CW_GET_INTERRUPT, ///< Get Interrupt status of WIZCHIP
CW_CLR_INTERRUPT, ///< Clears interrupt
CW_SET_INTRMASK, ///< Masks interrupt
CW_GET_INTRMASK, ///< Get interrupt mask
CW_SET_INTRTIME, ///< Set interval time between the current and next interrupt.
CW_GET_INTRTIME, ///< Set interval time between the current and next interrupt.
CW_GET_ID, ///< Gets WIZCHIP name.
//D20150601 : For no modification your application code
//#if _WIZCHIP_ == W5500
CW_RESET_PHY, ///< Resets internal PHY. Valid Only W5500
CW_SET_PHYCONF, ///< When PHY configured by internal register, PHY operation mode (Manual/Auto, 10/100, Half/Full). Valid Only W5000
CW_GET_PHYCONF, ///< Get PHY operation mode in internal register. Valid Only W5500
CW_GET_PHYSTATUS, ///< Get real PHY status on operating. Valid Only W5500
CW_SET_PHYPOWMODE, ///< Set PHY power mode as normal and down when PHYSTATUS.OPMD == 1. Valid Only W5500
//#endif
//D20150601 : For no modification your application code
//#if _WIZCHIP_ == W5200 || _WIZCHIP_ == W5500
CW_GET_PHYPOWMODE, ///< Get PHY Power mode as down or normal, Valid Only W5100, W5200
CW_GET_PHYLINK ///< Get PHY Link status, Valid Only W5100, W5200
//#endif
}ctlwizchip_type;
/**
* @ingroup DATA_TYPE
* Network control type enumration used in @ref ctlnetwork().
*/
typedef enum
{
CN_SET_NETINFO, ///< Set Network with @ref wiz_NetInfo
CN_GET_NETINFO, ///< Get Network with @ref wiz_NetInfo
CN_SET_NETMODE, ///< Set network mode as WOL, PPPoE, Ping Block, and Force ARP mode
CN_GET_NETMODE, ///< Get network mode as WOL, PPPoE, Ping Block, and Force ARP mode
CN_SET_TIMEOUT, ///< Set network timeout as retry count and time.
CN_GET_TIMEOUT, ///< Get network timeout as retry count and time.
}ctlnetwork_type;
/**
* @ingroup DATA_TYPE
* Interrupt kind when CW_SET_INTRRUPT, CW_GET_INTERRUPT, CW_SET_INTRMASK
* and CW_GET_INTRMASK is used in @ref ctlnetwork().
* It can be used with OR operation.
*/
typedef enum
{
#if _WIZCHIP_ == W5500
IK_WOL = (1 << 4), ///< Wake On Lan by receiving the magic packet. Valid in W500.
#elif _WIZCHIP_ == W5300
IK_FMTU = (1 << 4), ///< Received a ICMP message (Fragment MTU)
#endif
IK_PPPOE_TERMINATED = (1 << 5), ///< PPPoE Disconnected
#if _WIZCHIP_ != W5200
IK_DEST_UNREACH = (1 << 6), ///< Destination IP & Port Unreachable, No use in W5200
#endif
IK_IP_CONFLICT = (1 << 7), ///< IP conflict occurred
IK_SOCK_0 = (1 << 8), ///< Socket 0 interrupt
IK_SOCK_1 = (1 << 9), ///< Socket 1 interrupt
IK_SOCK_2 = (1 << 10), ///< Socket 2 interrupt
IK_SOCK_3 = (1 << 11), ///< Socket 3 interrupt
#if _WIZCHIP_ > W5100S
IK_SOCK_4 = (1 << 12), ///< Socket 4 interrupt, No use in 5100
IK_SOCK_5 = (1 << 13), ///< Socket 5 interrupt, No use in 5100
IK_SOCK_6 = (1 << 14), ///< Socket 6 interrupt, No use in 5100
IK_SOCK_7 = (1 << 15), ///< Socket 7 interrupt, No use in 5100
#endif
#if _WIZCHIP_ > W5100S
IK_SOCK_ALL = (0xFF << 8) ///< All Socket interrupt
#else
IK_SOCK_ALL = (0x0F << 8) ///< All Socket interrupt
#endif
}intr_kind;
#define PHY_CONFBY_HW 0 ///< Configured PHY operation mode by HW pin
#define PHY_CONFBY_SW 1 ///< Configured PHY operation mode by SW register
#define PHY_MODE_MANUAL 0 ///< Configured PHY operation mode with user setting.
#define PHY_MODE_AUTONEGO 1 ///< Configured PHY operation mode with auto-negotiation
#define PHY_SPEED_10 0 ///< Link Speed 10
#define PHY_SPEED_100 1 ///< Link Speed 100
#define PHY_DUPLEX_HALF 0 ///< Link Half-Duplex
#define PHY_DUPLEX_FULL 1 ///< Link Full-Duplex
#define PHY_LINK_OFF 0 ///< Link Off
#define PHY_LINK_ON 1 ///< Link On
#define PHY_POWER_NORM 0 ///< PHY power normal mode
#define PHY_POWER_DOWN 1 ///< PHY power down mode
#if _WIZCHIP_ == W5100S || _WIZCHIP_ == W5500
/**
* @ingroup DATA_TYPE
* It configures PHY configuration when CW_SET PHYCONF or CW_GET_PHYCONF in W5500,
* and it indicates the real PHY status configured by HW or SW in all WIZCHIP. \n
* Valid only in W5500.
*/
typedef struct wiz_PhyConf_t
{
uint8_t by; ///< set by @ref PHY_CONFBY_HW or @ref PHY_CONFBY_SW
uint8_t mode; ///< set by @ref PHY_MODE_MANUAL or @ref PHY_MODE_AUTONEGO
uint8_t speed; ///< set by @ref PHY_SPEED_10 or @ref PHY_SPEED_100
uint8_t duplex; ///< set by @ref PHY_DUPLEX_HALF @ref PHY_DUPLEX_FULL
//uint8_t power; ///< set by @ref PHY_POWER_NORM or @ref PHY_POWER_DOWN
//uint8_t link; ///< Valid only in CW_GET_PHYSTATUS. set by @ref PHY_LINK_ON or PHY_DUPLEX_OFF
}wiz_PhyConf;
#endif
/**
* @ingroup DATA_TYPE
* It used in setting dhcp_mode of @ref wiz_NetInfo.
*/
typedef enum
{
NETINFO_STATIC = 1, ///< Static IP configuration by manually.
NETINFO_DHCP ///< Dynamic IP configruation from a DHCP sever
}dhcp_mode;
/**
* @ingroup DATA_TYPE
* Network Information for WIZCHIP
*/
typedef struct wiz_NetInfo_t
{
uint8_t mac[6]; ///< Source Mac Address
uint8_t _pad[2]; ///< avoid 'non-aligned exception' in some cpu. @20201109
uint8_t ip[4]; ///< Source IP Address
uint8_t sn[4]; ///< Subnet Mask
uint8_t gw[4]; ///< Gateway IP Address
uint8_t dns[4]; ///< DNS server IP Address
dhcp_mode dhcp; ///< 1 - Static, 2 - DHCP
}wiz_NetInfo;
/**
* @ingroup DATA_TYPE
* Network mode
*/
typedef enum
{
#if _WIZCHIP_ == W5500
NM_FORCEARP = (1<<1), ///< Force to APP send whenever udp data is sent. Valid only in W5500
#endif
NM_WAKEONLAN = (1<<5), ///< Wake On Lan
NM_PINGBLOCK = (1<<4), ///< Block ping-request
NM_PPPOE = (1<<3), ///< PPPoE mode
}netmode_type;
/**
* @ingroup DATA_TYPE
* Used in CN_SET_TIMEOUT or CN_GET_TIMEOUT of @ref ctlwizchip() for timeout configruation.
*/
typedef struct wiz_NetTimeout_t
{
uint8_t retry_cnt; ///< retry count
uint16_t time_100us; ///< time unit 100us
}wiz_NetTimeout;
/**
*@brief Registers call back function for critical section of I/O functions such as
*\ref WIZCHIP_READ, @ref WIZCHIP_WRITE, @ref WIZCHIP_READ_BUF and @ref WIZCHIP_WRITE_BUF.
*@param cris_en : callback function for critical section enter.
*@param cris_ex : callback function for critical section exit.
*@todo Describe @ref WIZCHIP_CRITICAL_ENTER and @ref WIZCHIP_CRITICAL_EXIT marco or register your functions.
*@note If you do not describe or register, default functions(@ref wizchip_cris_enter & @ref wizchip_cris_exit) is called.
*/
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void));
/**
*@brief Registers call back function for WIZCHIP select & deselect.
*@param cs_sel : callback function for WIZCHIP select
*@param cs_desel : callback fucntion for WIZCHIP deselect
*@todo Describe @ref wizchip_cs_select and @ref wizchip_cs_deselect function or register your functions.
*@note If you do not describe or register, null function is called.
*/
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void));
/**
*@brief Registers call back function for bus interface.
*@param bus_rb : callback function to read byte data using system bus
*@param bus_wb : callback function to write byte data using system bus
*@todo Describe @ref wizchip_bus_readbyte and @ref wizchip_bus_writebyte function
*or register your functions.
*@note If you do not describe or register, null function is called.
*/
//M20150601 : For integrating with W5300
//void reg_wizchip_bus_cbfunc(uint8_t (*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, uint8_t wb));
void reg_wizchip_bus_cbfunc(iodata_t (*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb));
/**
*@brief Registers call back function for SPI interface.
*@param spi_rb : callback function to read byte using SPI
*@param spi_wb : callback function to write byte using SPI
*@todo Describe \ref wizchip_spi_readbyte and \ref wizchip_spi_writebyte function
*or register your functions.
*@note If you do not describe or register, null function is called.
*/
void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb));
/**
*@brief Registers call back function for SPI interface.
*@param spi_rb : callback function to burst read using SPI
*@param spi_wb : callback function to burst write using SPI
*@todo Describe \ref wizchip_spi_readbyte and \ref wizchip_spi_writebyte function
*or register your functions.
*@note If you do not describe or register, null function is called.
*/
void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len));
/**
* @ingroup extra_functions
* @brief Controls to the WIZCHIP.
* @details Resets WIZCHIP & internal PHY, Configures PHY mode, Monitor PHY(Link,Speed,Half/Full/Auto),
* controls interrupt & mask and so on.
* @param cwtype : Decides to the control type
* @param arg : arg type is dependent on cwtype.
* @return 0 : Success \n
* -1 : Fail because of invalid \ref ctlwizchip_type or unsupported \ref ctlwizchip_type in WIZCHIP
*/
int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg);
/**
* @ingroup extra_functions
* @brief Controls to network.
* @details Controls to network environment, mode, timeout and so on.
* @param cntype : Input. Decides to the control type
* @param arg : Inout. arg type is dependent on cntype.
* @return -1 : Fail because of invalid \ref ctlnetwork_type or unsupported \ref ctlnetwork_type in WIZCHIP \n
* 0 : Success
*/
int8_t ctlnetwork(ctlnetwork_type cntype, void* arg);
/*
* The following functions are implemented for internal use.
* but You can call these functions for code size reduction instead of ctlwizchip() and ctlnetwork().
*/
/**
* @ingroup extra_functions
* @brief Reset WIZCHIP by softly.
*/
void wizchip_sw_reset(void);
/**
* @ingroup extra_functions
* @brief Initializes WIZCHIP with socket buffer size
* @param txsize Socket tx buffer sizes. If null, initialized the default size 2KB.
* @param rxsize Socket rx buffer sizes. If null, initialized the default size 2KB.
* @return 0 : succcess \n
* -1 : fail. Invalid buffer size
*/
int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize);
/**
* @ingroup extra_functions
* @brief Clear Interrupt of WIZCHIP.
* @param intr : @ref intr_kind value operated OR. It can type-cast to uint16_t.
*/
void wizchip_clrinterrupt(intr_kind intr);
/**
* @ingroup extra_functions
* @brief Get Interrupt of WIZCHIP.
* @return @ref intr_kind value operated OR. It can type-cast to uint16_t.
*/
intr_kind wizchip_getinterrupt(void);
/**
* @ingroup extra_functions
* @brief Mask or Unmask Interrupt of WIZCHIP.
* @param intr : @ref intr_kind value operated OR. It can type-cast to uint16_t.
*/
void wizchip_setinterruptmask(intr_kind intr);
/**
* @ingroup extra_functions
* @brief Get Interrupt mask of WIZCHIP.
* @return : The operated OR vaule of @ref intr_kind. It can type-cast to uint16_t.
*/
intr_kind wizchip_getinterruptmask(void);
//todo
#if _WIZCHIP_ > W5100
int8_t wizphy_getphylink(void); ///< get the link status of phy in WIZCHIP. No use in W5100
int8_t wizphy_getphypmode(void); ///< get the power mode of PHY in WIZCHIP. No use in W5100
#endif
#if _WIZCHIP_ == W5100S || _WIZCHIP_ == W5500
void wizphy_reset(void); ///< Reset phy. Vailid only in W5500
/**
* @ingroup extra_functions
* @brief Set the phy information for WIZCHIP without power mode
* @param phyconf : @ref wiz_PhyConf
*/
void wizphy_setphyconf(wiz_PhyConf* phyconf);
/**
* @ingroup extra_functions
* @brief Get phy configuration information.
* @param phyconf : @ref wiz_PhyConf
*/
void wizphy_getphyconf(wiz_PhyConf* phyconf);
/**
* @ingroup extra_functions
* @brief Get phy status.
* @param phyconf : @ref wiz_PhyConf
*/
void wizphy_getphystat(wiz_PhyConf* phyconf);
/**
* @ingroup extra_functions
* @brief set the power mode of phy inside WIZCHIP. Refer to @ref PHYCFGR in W5500, @ref PHYSTATUS in W5200
* @param pmode Settig value of power down mode.
*/
int8_t wizphy_setphypmode(uint8_t pmode);
#endif
/**
* @ingroup extra_functions
* @brief Set the network information for WIZCHIP
* @param pnetinfo : @ref wizNetInfo
*/
void wizchip_setnetinfo(wiz_NetInfo* pnetinfo);
/**
* @ingroup extra_functions
* @brief Get the network information for WIZCHIP
* @param pnetinfo : @ref wizNetInfo
*/
void wizchip_getnetinfo(wiz_NetInfo* pnetinfo);
/**
* @ingroup extra_functions
* @brief Set the network mode such WOL, PPPoE, Ping Block, and etc.
* @param pnetinfo Value of network mode. Refer to @ref netmode_type.
*/
int8_t wizchip_setnetmode(netmode_type netmode);
/**
* @ingroup extra_functions
* @brief Get the network mode such WOL, PPPoE, Ping Block, and etc.
* @return Value of network mode. Refer to @ref netmode_type.
*/
netmode_type wizchip_getnetmode(void);
/**
* @ingroup extra_functions
* @brief Set retry time value(@ref _RTR_) and retry count(@ref _RCR_).
* @details @ref _RTR_ configures the retransmission timeout period and @ref _RCR_ configures the number of time of retransmission.
* @param nettime @ref _RTR_ value and @ref _RCR_ value. Refer to @ref wiz_NetTimeout.
*/
void wizchip_settimeout(wiz_NetTimeout* nettime);
/**
* @ingroup extra_functions
* @brief Get retry time value(@ref _RTR_) and retry count(@ref _RCR_).
* @details @ref _RTR_ configures the retransmission timeout period and @ref _RCR_ configures the number of time of retransmission.
* @param nettime @ref _RTR_ value and @ref _RCR_ value. Refer to @ref wiz_NetTimeout.
*/
void wizchip_gettimeout(wiz_NetTimeout* nettime);
#ifdef __cplusplus
}
#endif
#endif // _WIZCHIP_CONF_H_

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@ -0,0 +1,931 @@
//*****************************************************************************
//
//! \file wizchip_socket.c
//! \brief SOCKET APIs Implements file.
//! \details SOCKET APIs like as Berkeley Socket APIs.
//! \version 1.0.3
//! \date 2013/10/21
//! \par Revision history
//! <2015/02/05> Notice
//! The version history is not updated after this point.
//! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
//! >> https://github.com/Wiznet/ioLibrary_Driver
//! <2014/05/01> V1.0.3. Refer to M20140501
//! 1. Implicit type casting -> Explicit type casting.
//! 2. replace 0x01 with PACK_REMAINED in recvfrom()
//! 3. Validation a destination ip in connect() & sendto():
//! It occurs a fatal error on converting unint32 address if uint8* addr parameter is not aligned by 4byte address.
//! Copy 4 byte addr value into temporary uint32 variable and then compares it.
//! <2013/12/20> V1.0.2 Refer to M20131220
//! Remove Warning.
//! <2013/11/04> V1.0.1 2nd Release. Refer to "20131104".
//! In sendto(), Add to clear timeout interrupt status (Sn_IR_TIMEOUT)
//! <2013/10/21> 1st Release
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include "wizchip_socket.h"
//M20150401 : Typing Error
//#define SOCK_ANY_PORT_NUM 0xC000;
#define SOCK_ANY_PORT_NUM 0xC000
static uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
static uint16_t sock_io_mode = 0;
static uint16_t sock_is_sending = 0;
static uint16_t sock_remained_size[_WIZCHIP_SOCK_NUM_] = {0,0,};
//M20150601 : For extern decleation
//static uint8_t sock_pack_info[_WIZCHIP_SOCK_NUM_] = {0,};
uint8_t sock_pack_info[_WIZCHIP_SOCK_NUM_] = {0,};
//
#if _WIZCHIP_ == 5200
static uint16_t sock_next_rd[_WIZCHIP_SOCK_NUM_] ={0,};
#endif
//A20150601 : For integrating with W5300
#if _WIZCHIP_ == 5300
uint8_t sock_remained_byte[_WIZCHIP_SOCK_NUM_] = {0,}; // set by wiz_recv_data()
#endif
#define CHECK_SOCKNUM() \
do{ \
if(sn > _WIZCHIP_SOCK_NUM_) return SOCKERR_SOCKNUM; \
}while(0); \
#define CHECK_SOCKMODE(mode) \
do{ \
if((getSn_MR(sn) & 0x0F) != mode) return SOCKERR_SOCKMODE; \
}while(0); \
#define CHECK_SOCKINIT() \
do{ \
if((getSn_SR(sn) != SOCK_INIT)) return SOCKERR_SOCKINIT; \
}while(0); \
#define CHECK_SOCKDATA() \
do{ \
if(len == 0) return SOCKERR_DATALEN; \
}while(0); \
int8_t wizchip_socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag)
{
CHECK_SOCKNUM();
switch(protocol)
{
case Sn_MR_TCP :
{
//M20150601 : Fixed the warning - taddr will never be NULL
/*
uint8_t taddr[4];
getSIPR(taddr);
*/
uint32_t taddr;
getSIPR((uint8_t*)&taddr);
if(taddr == 0) return SOCKERR_SOCKINIT;
break;
}
case Sn_MR_UDP :
case Sn_MR_MACRAW :
case Sn_MR_IPRAW :
break;
#if ( _WIZCHIP_ < 5200 )
case Sn_MR_PPPoE :
break;
#endif
default :
return SOCKERR_SOCKMODE;
}
//M20150601 : For SF_TCP_ALIGN & W5300
//if((flag & 0x06) != 0) return SOCKERR_SOCKFLAG;
if((flag & 0x04) != 0) return SOCKERR_SOCKFLAG;
#if _WIZCHIP_ == 5200
if(flag & 0x10) return SOCKERR_SOCKFLAG;
#endif
if(flag != 0)
{
switch(protocol)
{
case Sn_MR_TCP:
//M20150601 : For SF_TCP_ALIGN & W5300
#if _WIZCHIP_ == 5300
if((flag & (SF_TCP_NODELAY|SF_IO_NONBLOCK|SF_TCP_ALIGN))==0) return SOCKERR_SOCKFLAG;
#else
if((flag & (SF_TCP_NODELAY|SF_IO_NONBLOCK))==0) return SOCKERR_SOCKFLAG;
#endif
break;
case Sn_MR_UDP:
if(flag & SF_IGMP_VER2)
{
if((flag & SF_MULTI_ENABLE)==0) return SOCKERR_SOCKFLAG;
}
#if _WIZCHIP_ == 5500
if(flag & SF_UNI_BLOCK)
{
if((flag & SF_MULTI_ENABLE) == 0) return SOCKERR_SOCKFLAG;
}
#endif
break;
default:
break;
}
}
wizchip_close(sn);
//M20150601
#if _WIZCHIP_ == 5300
setSn_MR(sn, ((uint16_t)(protocol | (flag & 0xF0))) | (((uint16_t)(flag & 0x02)) << 7) );
#else
setSn_MR(sn, (protocol | (flag & 0xF0)));
#endif
if(!port)
{
port = sock_any_port++;
if(sock_any_port == 0xFFF0) sock_any_port = SOCK_ANY_PORT_NUM;
}
setSn_PORT(sn,port);
setSn_CR(sn,Sn_CR_OPEN);
while(getSn_CR(sn));
//A20150401 : For release the previous sock_io_mode
sock_io_mode &= ~(1 <<sn);
//
sock_io_mode |= ((flag & SF_IO_NONBLOCK) << sn);
sock_is_sending &= ~(1<<sn);
sock_remained_size[sn] = 0;
//M20150601 : repalce 0 with PACK_COMPLETED
//sock_pack_info[sn] = 0;
sock_pack_info[sn] = PACK_COMPLETED;
//
while(getSn_SR(sn) == SOCK_CLOSED);
return (int8_t)sn;
}
int8_t wizchip_close(uint8_t sn)
{
CHECK_SOCKNUM();
//A20160426 : Applied the erratum 1 of W5300
#if (_WIZCHIP_ == 5300)
//M20160503 : Wrong socket parameter. s -> sn
//if( ((getSn_MR(s)& 0x0F) == Sn_MR_TCP) && (getSn_TX_FSR(s) != getSn_TxMAX(s)) )
if( ((getSn_MR(sn)& 0x0F) == Sn_MR_TCP) && (getSn_TX_FSR(sn) != getSn_TxMAX(sn)) )
{
uint8_t destip[4] = {0, 0, 0, 1};
// TODO
// You can wait for completing to sending data;
// wait about 1 second;
// if you have completed to send data, skip the code of erratum 1
// ex> wait_1s();
// if (getSn_TX_FSR(s) == getSn_TxMAX(s)) continue;
//
//M20160503 : The socket() of close() calls close() itself again. It occures a infinite loop - close()->socket()->close()->socket()-> ~
//socket(s,Sn_MR_UDP,0x3000,0);
//sendto(s,destip,1,destip,0x3000); // send the dummy data to an unknown destination(0.0.0.1).
setSn_MR(sn,Sn_MR_UDP);
setSn_PORTR(sn, 0x3000);
setSn_CR(sn,Sn_CR_OPEN);
while(getSn_CR(sn) != 0);
while(getSn_SR(sn) != SOCK_UDP);
sendto(sn,destip,1,destip,0x3000); // send the dummy data to an unknown destination(0.0.0.1).
};
#endif
setSn_CR(sn,Sn_CR_CLOSE);
/* wait to process the command... */
while( getSn_CR(sn) );
/* clear all interrupt of the socket. */
setSn_IR(sn, 0xFF);
//A20150401 : Release the sock_io_mode of socket n.
sock_io_mode &= ~(1<<sn);
//
sock_is_sending &= ~(1<<sn);
sock_remained_size[sn] = 0;
sock_pack_info[sn] = 0;
while(getSn_SR(sn) != SOCK_CLOSED);
return SOCK_OK;
}
int8_t wizchip_listen(uint8_t sn)
{
CHECK_SOCKNUM();
CHECK_SOCKMODE(Sn_MR_TCP);
CHECK_SOCKINIT();
setSn_CR(sn,Sn_CR_LISTEN);
while(getSn_CR(sn));
while(getSn_SR(sn) != SOCK_LISTEN)
{
wizchip_close(sn);
return SOCKERR_SOCKCLOSED;
}
return SOCK_OK;
}
int8_t wizchip_connect(uint8_t sn, uint8_t * addr, uint16_t port)
{
CHECK_SOCKNUM();
CHECK_SOCKMODE(Sn_MR_TCP);
CHECK_SOCKINIT();
//M20140501 : For avoiding fatal error on memory align mismatched
//if( *((uint32_t*)addr) == 0xFFFFFFFF || *((uint32_t*)addr) == 0) return SOCKERR_IPINVALID;
{
uint32_t taddr;
taddr = ((uint32_t)addr[0] & 0x000000FF);
taddr = (taddr << 8) + ((uint32_t)addr[1] & 0x000000FF);
taddr = (taddr << 8) + ((uint32_t)addr[2] & 0x000000FF);
taddr = (taddr << 8) + ((uint32_t)addr[3] & 0x000000FF);
if( taddr == 0xFFFFFFFF || taddr == 0) return SOCKERR_IPINVALID;
}
//
if(port == 0) return SOCKERR_PORTZERO;
setSn_DIPR(sn,addr);
setSn_DPORT(sn,port);
setSn_CR(sn,Sn_CR_CONNECT);
while(getSn_CR(sn));
if(sock_io_mode & (1<<sn)) return SOCK_BUSY;
while(getSn_SR(sn) != SOCK_ESTABLISHED)
{
if (getSn_IR(sn) & Sn_IR_TIMEOUT)
{
setSn_IR(sn, Sn_IR_TIMEOUT);
return SOCKERR_TIMEOUT;
}
if (getSn_SR(sn) == SOCK_CLOSED)
{
return SOCKERR_SOCKCLOSED;
}
}
return SOCK_OK;
}
int8_t wizchip_disconnect(uint8_t sn)
{
CHECK_SOCKNUM();
CHECK_SOCKMODE(Sn_MR_TCP);
setSn_CR(sn,Sn_CR_DISCON);
/* wait to process the command... */
while(getSn_CR(sn));
sock_is_sending &= ~(1<<sn);
if(sock_io_mode & (1<<sn)) return SOCK_BUSY;
while(getSn_SR(sn) != SOCK_CLOSED)
{
if(getSn_IR(sn) & Sn_IR_TIMEOUT)
{
wizchip_close(sn);
return SOCKERR_TIMEOUT;
}
}
return SOCK_OK;
}
int32_t wizchip_send(uint8_t sn, uint8_t * buf, uint16_t len)
{
uint8_t tmp=0;
uint16_t freesize=0;
CHECK_SOCKNUM();
CHECK_SOCKMODE(Sn_MR_TCP);
CHECK_SOCKDATA();
tmp = getSn_SR(sn);
if(tmp != SOCK_ESTABLISHED && tmp != SOCK_CLOSE_WAIT) return SOCKERR_SOCKSTATUS;
if( sock_is_sending & (1<<sn) )
{
tmp = getSn_IR(sn);
if(tmp & Sn_IR_SENDOK)
{
setSn_IR(sn, Sn_IR_SENDOK);
//M20150401 : Typing Error
//#if _WZICHIP_ == 5200
#if _WIZCHIP_ == 5200
if(getSn_TX_RD(sn) != sock_next_rd[sn])
{
setSn_CR(sn,Sn_CR_SEND);
while(getSn_CR(sn));
return SOCK_BUSY;
}
#endif
sock_is_sending &= ~(1<<sn);
}
else if(tmp & Sn_IR_TIMEOUT)
{
wizchip_close(sn);
return SOCKERR_TIMEOUT;
}
else return SOCK_BUSY;
}
freesize = getSn_TxMAX(sn);
if (len > freesize) len = freesize; // check size not to exceed MAX size.
while(1)
{
freesize = getSn_TX_FSR(sn);
tmp = getSn_SR(sn);
if ((tmp != SOCK_ESTABLISHED) && (tmp != SOCK_CLOSE_WAIT))
{
wizchip_close(sn);
return SOCKERR_SOCKSTATUS;
}
if( (sock_io_mode & (1<<sn)) && (len > freesize) ) return SOCK_BUSY;
if(len <= freesize) break;
}
wiz_send_data(sn, buf, len);
#if _WIZCHIP_ == 5200
sock_next_rd[sn] = getSn_TX_RD(sn) + len;
#endif
#if _WIZCHIP_ == 5300
setSn_TX_WRSR(sn,len);
#endif
setSn_CR(sn,Sn_CR_SEND);
/* wait to process the command... */
while(getSn_CR(sn));
sock_is_sending |= (1 << sn);
//M20150409 : Explicit Type Casting
//return len;
return (int32_t)len;
}
int32_t wizchip_recv(uint8_t sn, uint8_t * buf, uint16_t len)
{
uint8_t tmp = 0;
uint16_t recvsize = 0;
//A20150601 : For integarating with W5300
#if _WIZCHIP_ == 5300
uint8_t head[2];
uint16_t mr;
#endif
//
CHECK_SOCKNUM();
CHECK_SOCKMODE(Sn_MR_TCP);
CHECK_SOCKDATA();
recvsize = getSn_RxMAX(sn);
if(recvsize < len) len = recvsize;
//A20150601 : For Integrating with W5300
#if _WIZCHIP_ == 5300
//sock_pack_info[sn] = PACK_COMPLETED; // for clear
if(sock_remained_size[sn] == 0)
{
#endif
//
while(1)
{
recvsize = getSn_RX_RSR(sn);
tmp = getSn_SR(sn);
if (tmp != SOCK_ESTABLISHED)
{
if(tmp == SOCK_CLOSE_WAIT)
{
if(recvsize != 0) break;
else if(getSn_TX_FSR(sn) == getSn_TxMAX(sn))
{
wizchip_close(sn);
return SOCKERR_SOCKSTATUS;
}
}
else
{
wizchip_close(sn);
return SOCKERR_SOCKSTATUS;
}
}
if((sock_io_mode & (1<<sn)) && (recvsize == 0)) return SOCK_BUSY;
if(recvsize != 0) break;
};
#if _WIZCHIP_ == 5300
}
#endif
//A20150601 : For integrating with W5300
#if _WIZCHIP_ == 5300
if((sock_remained_size[sn] == 0) || (getSn_MR(sn) & Sn_MR_ALIGN))
{
mr = getMR();
if((getSn_MR(sn) & Sn_MR_ALIGN)==0)
{
wiz_recv_data(sn,head,2);
if(mr & MR_FS)
recvsize = (((uint16_t)head[1]) << 8) | ((uint16_t)head[0]);
else
recvsize = (((uint16_t)head[0]) << 8) | ((uint16_t)head[1]);
sock_pack_info[sn] = PACK_FIRST;
}
sock_remained_size[sn] = recvsize;
}
if(len > sock_remained_size[sn]) len = sock_remained_size[sn];
recvsize = len;
if(sock_pack_info[sn] & PACK_FIFOBYTE)
{
*buf = sock_remained_byte[sn];
buf++;
sock_pack_info[sn] &= ~(PACK_FIFOBYTE);
recvsize -= 1;
sock_remained_size[sn] -= 1;
}
if(recvsize != 0)
{
wiz_recv_data(sn, buf, recvsize);
setSn_CR(sn,Sn_CR_RECV);
while(getSn_CR(sn));
}
sock_remained_size[sn] -= recvsize;
if(sock_remained_size[sn] != 0)
{
sock_pack_info[sn] |= PACK_REMAINED;
if(recvsize & 0x1) sock_pack_info[sn] |= PACK_FIFOBYTE;
}
else sock_pack_info[sn] = PACK_COMPLETED;
if(getSn_MR(sn) & Sn_MR_ALIGN) sock_remained_size[sn] = 0;
//len = recvsize;
#else
if(recvsize < len) len = recvsize;
wiz_recv_data(sn, buf, len);
setSn_CR(sn,Sn_CR_RECV);
while(getSn_CR(sn));
#endif
//M20150409 : Explicit Type Casting
//return len;
return (int32_t)len;
}
int32_t wizchip_sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port)
{
uint8_t tmp = 0;
uint16_t freesize = 0;
uint32_t taddr;
CHECK_SOCKNUM();
switch(getSn_MR(sn) & 0x0F)
{
case Sn_MR_UDP:
case Sn_MR_MACRAW:
// break;
// #if ( _WIZCHIP_ < 5200 )
case Sn_MR_IPRAW:
break;
// #endif
default:
return SOCKERR_SOCKMODE;
}
CHECK_SOCKDATA();
//M20140501 : For avoiding fatal error on memory align mismatched
//if(*((uint32_t*)addr) == 0) return SOCKERR_IPINVALID;
//{
//uint32_t taddr;
taddr = ((uint32_t)addr[0]) & 0x000000FF;
taddr = (taddr << 8) + ((uint32_t)addr[1] & 0x000000FF);
taddr = (taddr << 8) + ((uint32_t)addr[2] & 0x000000FF);
taddr = (taddr << 8) + ((uint32_t)addr[3] & 0x000000FF);
//}
//
//if(*((uint32_t*)addr) == 0) return SOCKERR_IPINVALID;
if((taddr == 0) && ((getSn_MR(sn)&Sn_MR_MACRAW) != Sn_MR_MACRAW)) return SOCKERR_IPINVALID;
if((port == 0) && ((getSn_MR(sn)&Sn_MR_MACRAW) != Sn_MR_MACRAW)) return SOCKERR_PORTZERO;
tmp = getSn_SR(sn);
//#if ( _WIZCHIP_ < 5200 )
if((tmp != SOCK_MACRAW) && (tmp != SOCK_UDP) && (tmp != SOCK_IPRAW)) return SOCKERR_SOCKSTATUS;
//#else
// if(tmp != SOCK_MACRAW && tmp != SOCK_UDP) return SOCKERR_SOCKSTATUS;
//#endif
setSn_DIPR(sn,addr);
setSn_DPORT(sn,port);
freesize = getSn_TxMAX(sn);
if (len > freesize) len = freesize; // check size not to exceed MAX size.
while(1)
{
freesize = getSn_TX_FSR(sn);
if(getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
if( (sock_io_mode & (1<<sn)) && (len > freesize) ) return SOCK_BUSY;
if(len <= freesize) break;
};
wiz_send_data(sn, buf, len);
#if _WIZCHIP_ < 5500 //M20150401 : for WIZCHIP Errata #4, #5 (ARP errata)
getSIPR((uint8_t*)&taddr);
if(taddr == 0)
{
getSUBR((uint8_t*)&taddr);
setSUBR((uint8_t*)"\x00\x00\x00\x00");
}
else taddr = 0;
#endif
//A20150601 : For W5300
#if _WIZCHIP_ == 5300
setSn_TX_WRSR(sn, len);
#endif
//
setSn_CR(sn,Sn_CR_SEND);
/* wait to process the command... */
while(getSn_CR(sn));
while(1)
{
tmp = getSn_IR(sn);
if(tmp & Sn_IR_SENDOK)
{
setSn_IR(sn, Sn_IR_SENDOK);
break;
}
//M:20131104
//else if(tmp & Sn_IR_TIMEOUT) return SOCKERR_TIMEOUT;
else if(tmp & Sn_IR_TIMEOUT)
{
setSn_IR(sn, Sn_IR_TIMEOUT);
//M20150409 : Fixed the lost of sign bits by type casting.
//len = (uint16_t)SOCKERR_TIMEOUT;
//break;
#if _WIZCHIP_ < 5500 //M20150401 : for WIZCHIP Errata #4, #5 (ARP errata)
if(taddr) setSUBR((uint8_t*)&taddr);
#endif
return SOCKERR_TIMEOUT;
}
////////////
}
#if _WIZCHIP_ < 5500 //M20150401 : for WIZCHIP Errata #4, #5 (ARP errata)
if(taddr) setSUBR((uint8_t*)&taddr);
#endif
//M20150409 : Explicit Type Casting
//return len;
return (int32_t)len;
}
int32_t wizchip_recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port)
{
//M20150601 : For W5300
#if _WIZCHIP_ == 5300
uint16_t mr;
uint16_t mr1;
#else
uint8_t mr;
#endif
//
uint8_t head[8];
uint16_t pack_len=0;
CHECK_SOCKNUM();
//CHECK_SOCKMODE(Sn_MR_UDP);
//A20150601
#if _WIZCHIP_ == 5300
mr1 = getMR();
#endif
switch((mr=getSn_MR(sn)) & 0x0F)
{
case Sn_MR_UDP:
case Sn_MR_IPRAW:
case Sn_MR_MACRAW:
break;
#if ( _WIZCHIP_ < 5200 )
case Sn_MR_PPPoE:
break;
#endif
default:
return SOCKERR_SOCKMODE;
}
CHECK_SOCKDATA();
if(sock_remained_size[sn] == 0)
{
while(1)
{
pack_len = getSn_RX_RSR(sn);
if(getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
if( (sock_io_mode & (1<<sn)) && (pack_len == 0) ) return SOCK_BUSY;
if(pack_len != 0) break;
};
}
//D20150601 : Move it to bottom
// sock_pack_info[sn] = PACK_COMPLETED;
switch (mr & 0x07)
{
case Sn_MR_UDP :
if(sock_remained_size[sn] == 0)
{
wiz_recv_data(sn, head, 8);
setSn_CR(sn,Sn_CR_RECV);
while(getSn_CR(sn));
// read peer's IP address, port number & packet length
//A20150601 : For W5300
#if _WIZCHIP_ == 5300
if(mr1 & MR_FS)
{
addr[0] = head[1];
addr[1] = head[0];
addr[2] = head[3];
addr[3] = head[2];
*port = head[5];
*port = (*port << 8) + head[4];
sock_remained_size[sn] = head[7];
sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[6];
}
else
{
#endif
addr[0] = head[0];
addr[1] = head[1];
addr[2] = head[2];
addr[3] = head[3];
*port = head[4];
*port = (*port << 8) + head[5];
sock_remained_size[sn] = head[6];
sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[7];
#if _WIZCHIP_ == 5300
}
#endif
sock_pack_info[sn] = PACK_FIRST;
}
if(len < sock_remained_size[sn]) pack_len = len;
else pack_len = sock_remained_size[sn];
//A20150601 : For W5300
len = pack_len;
#if _WIZCHIP_ == 5300
if(sock_pack_info[sn] & PACK_FIFOBYTE)
{
*buf++ = sock_remained_byte[sn];
pack_len -= 1;
sock_remained_size[sn] -= 1;
sock_pack_info[sn] &= ~PACK_FIFOBYTE;
}
#endif
//
// Need to packet length check (default 1472)
//
wiz_recv_data(sn, buf, pack_len); // data copy.
break;
case Sn_MR_MACRAW :
if(sock_remained_size[sn] == 0)
{
wiz_recv_data(sn, head, 2);
setSn_CR(sn,Sn_CR_RECV);
while(getSn_CR(sn));
// read peer's IP address, port number & packet length
sock_remained_size[sn] = head[0];
sock_remained_size[sn] = (sock_remained_size[sn] <<8) + head[1] -2;
#if _WIZCHIP_ == W5300
if(sock_remained_size[sn] & 0x01)
sock_remained_size[sn] = sock_remained_size[sn] + 1 - 4;
else
sock_remained_size[sn] -= 4;
#endif
if(sock_remained_size[sn] > 1514)
{
wizchip_close(sn);
return SOCKFATAL_PACKLEN;
}
sock_pack_info[sn] = PACK_FIRST;
}
if(len < sock_remained_size[sn]) pack_len = len;
else pack_len = sock_remained_size[sn];
wiz_recv_data(sn,buf,pack_len);
break;
//#if ( _WIZCHIP_ < 5200 )
case Sn_MR_IPRAW:
if(sock_remained_size[sn] == 0)
{
wiz_recv_data(sn, head, 6);
setSn_CR(sn,Sn_CR_RECV);
while(getSn_CR(sn));
addr[0] = head[0];
addr[1] = head[1];
addr[2] = head[2];
addr[3] = head[3];
sock_remained_size[sn] = head[4];
//M20150401 : For Typing Error
//sock_remaiend_size[sn] = (sock_remained_size[sn] << 8) + head[5];
sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[5];
sock_pack_info[sn] = PACK_FIRST;
}
//
// Need to packet length check
//
if(len < sock_remained_size[sn]) pack_len = len;
else pack_len = sock_remained_size[sn];
wiz_recv_data(sn, buf, pack_len); // data copy.
break;
//#endif
default:
wiz_recv_ignore(sn, pack_len); // data copy.
sock_remained_size[sn] = pack_len;
break;
}
setSn_CR(sn,Sn_CR_RECV);
/* wait to process the command... */
while(getSn_CR(sn)) ;
sock_remained_size[sn] -= pack_len;
//M20150601 :
//if(sock_remained_size[sn] != 0) sock_pack_info[sn] |= 0x01;
if(sock_remained_size[sn] != 0)
{
sock_pack_info[sn] |= PACK_REMAINED;
#if _WIZCHIP_ == 5300
if(pack_len & 0x01) sock_pack_info[sn] |= PACK_FIFOBYTE;
#endif
}
else sock_pack_info[sn] = PACK_COMPLETED;
#if _WIZCHIP_ == 5300
pack_len = len;
#endif
//
//M20150409 : Explicit Type Casting
//return pack_len;
return (int32_t)pack_len;
}
int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg)
{
uint8_t tmp = 0;
CHECK_SOCKNUM();
switch(cstype)
{
case CS_SET_IOMODE:
tmp = *((uint8_t*)arg);
if(tmp == SOCK_IO_NONBLOCK) sock_io_mode |= (1<<sn);
else if(tmp == SOCK_IO_BLOCK) sock_io_mode &= ~(1<<sn);
else return SOCKERR_ARG;
break;
case CS_GET_IOMODE:
//M20140501 : implict type casting -> explict type casting
//*((uint8_t*)arg) = (sock_io_mode >> sn) & 0x0001;
*((uint8_t*)arg) = (uint8_t)((sock_io_mode >> sn) & 0x0001);
//
break;
case CS_GET_MAXTXBUF:
*((uint16_t*)arg) = getSn_TxMAX(sn);
break;
case CS_GET_MAXRXBUF:
*((uint16_t*)arg) = getSn_RxMAX(sn);
break;
case CS_CLR_INTERRUPT:
if( (*(uint8_t*)arg) > SIK_ALL) return SOCKERR_ARG;
setSn_IR(sn,*(uint8_t*)arg);
break;
case CS_GET_INTERRUPT:
*((uint8_t*)arg) = getSn_IR(sn);
break;
#if _WIZCHIP_ != 5100
case CS_SET_INTMASK:
if( (*(uint8_t*)arg) > SIK_ALL) return SOCKERR_ARG;
setSn_IMR(sn,*(uint8_t*)arg);
break;
case CS_GET_INTMASK:
*((uint8_t*)arg) = getSn_IMR(sn);
break;
#endif
default:
return SOCKERR_ARG;
}
return SOCK_OK;
}
int8_t wizchip_setsockopt(uint8_t sn, sockopt_type sotype, void* arg)
{
// M20131220 : Remove warning
//uint8_t tmp;
CHECK_SOCKNUM();
switch(sotype)
{
case SO_TTL:
setSn_TTL(sn,*(uint8_t*)arg);
break;
case SO_TOS:
setSn_TOS(sn,*(uint8_t*)arg);
break;
case SO_MSS:
setSn_MSSR(sn,*(uint16_t*)arg);
break;
case SO_DESTIP:
setSn_DIPR(sn, (uint8_t*)arg);
break;
case SO_DESTPORT:
setSn_DPORT(sn, *(uint16_t*)arg);
break;
#if _WIZCHIP_ != 5100
case SO_KEEPALIVESEND:
CHECK_SOCKMODE(Sn_MR_TCP);
#if _WIZCHIP_ > 5200
if(getSn_KPALVTR(sn) != 0) return SOCKERR_SOCKOPT;
#endif
setSn_CR(sn,Sn_CR_SEND_KEEP);
while(getSn_CR(sn) != 0)
{
// M20131220
//if ((tmp = getSn_IR(sn)) & Sn_IR_TIMEOUT)
if (getSn_IR(sn) & Sn_IR_TIMEOUT)
{
setSn_IR(sn, Sn_IR_TIMEOUT);
return SOCKERR_TIMEOUT;
}
}
break;
#if !( (_WIZCHIP_ == 5100) || (_WIZCHIP_ == 5200) )
case SO_KEEPALIVEAUTO:
CHECK_SOCKMODE(Sn_MR_TCP);
setSn_KPALVTR(sn,*(uint8_t*)arg);
break;
#endif
#endif
default:
return SOCKERR_ARG;
}
return SOCK_OK;
}
int8_t wizchip_getsockopt(uint8_t sn, sockopt_type sotype, void* arg)
{
CHECK_SOCKNUM();
switch(sotype)
{
case SO_FLAG:
*(uint8_t*)arg = getSn_MR(sn) & 0xF0;
break;
case SO_TTL:
*(uint8_t*) arg = getSn_TTL(sn);
break;
case SO_TOS:
*(uint8_t*) arg = getSn_TOS(sn);
break;
case SO_MSS:
*(uint16_t*) arg = getSn_MSSR(sn);
break;
case SO_DESTIP:
getSn_DIPR(sn, (uint8_t*)arg);
break;
case SO_DESTPORT:
*(uint16_t*) arg = getSn_DPORT(sn);
break;
#if _WIZCHIP_ > 5200
case SO_KEEPALIVEAUTO:
CHECK_SOCKMODE(Sn_MR_TCP);
*(uint16_t*) arg = getSn_KPALVTR(sn);
break;
#endif
case SO_SENDBUF:
*(uint16_t*) arg = getSn_TX_FSR(sn);
break;
case SO_RECVBUF:
*(uint16_t*) arg = getSn_RX_RSR(sn);
break;
case SO_STATUS:
*(uint8_t*) arg = getSn_SR(sn);
break;
case SO_REMAINSIZE:
if(getSn_MR(sn) & Sn_MR_TCP)
*(uint16_t*)arg = getSn_RX_RSR(sn);
else
*(uint16_t*)arg = sock_remained_size[sn];
break;
case SO_PACKINFO:
//CHECK_SOCKMODE(Sn_MR_TCP);
#if _WIZCHIP_ != 5300
if((getSn_MR(sn) == Sn_MR_TCP))
return SOCKERR_SOCKMODE;
#endif
*(uint8_t*)arg = sock_pack_info[sn];
break;
default:
return SOCKERR_SOCKOPT;
}
return SOCK_OK;
}

489
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@ -0,0 +1,489 @@
//*****************************************************************************
//
//! \file wizchip_socket.h
//! \brief SOCKET APIs Header file.
//! \details SOCKET APIs like as berkeley socket api.
//! \version 1.0.2
//! \date 2013/10/21
//! \par Revision history
//! <2015/02/05> Notice
//! The version history is not updated after this point.
//! Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary.
//! >> https://github.com/Wiznet/ioLibrary_Driver
//! <2014/05/01> V1.0.2. Refer to M20140501
//! 1. Modify the comment : SO_REMAINED -> PACK_REMAINED
//! 2. Add the comment as zero byte udp data reception in getsockopt().
//! <2013/10/21> 1st Release
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
/**
* @defgroup WIZnet_socket_APIs 1. WIZnet socket APIs
* @brief WIZnet socket APIs are based on Berkeley socket APIs, thus it has much similar name and interface.
* But there is a little bit of difference.
* @details
* <b> Comparison between WIZnet and Berkeley SOCKET APIs </b>
* <table>
* <tr> <td><b>API</b></td> <td><b>WIZnet</b></td> <td><b>Berkeley</b></td> </tr>
* <tr> <td>socket()</td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>bind()</b></td> <td>X</td> <td>O</td> </tr>
* <tr> <td><b>listen()</b></td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>connect()</b></td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>accept()</b></td> <td>X</td> <td>O</td> </tr>
* <tr> <td><b>recv()</b></td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>send()</b></td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>recvfrom()</b></td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>sendto()</b></td> <td>O</td> <td>O</td> </tr>
* <tr> <td><b>closesocket()</b></td> <td>O<br>close() & disconnect()</td> <td>O</td> </tr>
* </table>
* There are @b bind() and @b accept() functions in @b Berkeley SOCKET API but,
* not in @b WIZnet SOCKET API. Because socket() of WIZnet is not only creating a SOCKET but also binding a local port number,
* and listen() of WIZnet is not only listening to connection request from client but also accepting the connection request. \n
* When you program "TCP SERVER" with Berkeley SOCKET API, you can use only one listen port.
* When the listen SOCKET accepts a connection request from a client, it keeps listening.
* After accepting the connection request, a new SOCKET is created and the new SOCKET is used in communication with the client. \n
* Following figure shows network flow diagram by Berkeley SOCKET API.
* @image html Berkeley_SOCKET.jpg "<Berkeley SOCKET API>"
* But, When you program "TCP SERVER" with WIZnet SOCKET API, you can use as many as 8 listen SOCKET with same port number. \n
* Because there's no accept() in WIZnet SOCKET APIs, when the listen SOCKET accepts a connection request from a client,
* it is changed in order to communicate with the client.
* And the changed SOCKET is not listening any more and is dedicated for communicating with the client. \n
* If there're many listen SOCKET with same listen port number and a client requests a connection,
* the SOCKET which has the smallest SOCKET number accepts the request and is changed as communication SOCKET. \n
* Following figure shows network flow diagram by WIZnet SOCKET API.
* @image html WIZnet_SOCKET.jpg "<WIZnet SOCKET API>"
*/
#ifndef _WIZCHIP_SOCKET_H_
#define _WIZCHIP_SOCKET_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "wizchip_conf.h"
#define SOCKET uint8_t ///< SOCKET type define for legacy driver
#define SOCK_OK 1 ///< Result is OK about socket process.
#define SOCK_BUSY 0 ///< Socket is busy on processing the operation. Valid only Non-block IO Mode.
#define SOCK_FATAL -1000 ///< Result is fatal error about socket process.
#define SOCK_ERROR 0
#define SOCKERR_SOCKNUM (SOCK_ERROR - 1) ///< Invalid socket number
#define SOCKERR_SOCKOPT (SOCK_ERROR - 2) ///< Invalid socket option
#define SOCKERR_SOCKINIT (SOCK_ERROR - 3) ///< Socket is not initialized or SIPR is Zero IP address when Sn_MR_TCP
#define SOCKERR_SOCKCLOSED (SOCK_ERROR - 4) ///< Socket unexpectedly closed.
#define SOCKERR_SOCKMODE (SOCK_ERROR - 5) ///< Invalid socket mode for socket operation.
#define SOCKERR_SOCKFLAG (SOCK_ERROR - 6) ///< Invalid socket flag
#define SOCKERR_SOCKSTATUS (SOCK_ERROR - 7) ///< Invalid socket status for socket operation.
#define SOCKERR_ARG (SOCK_ERROR - 10) ///< Invalid argument.
#define SOCKERR_PORTZERO (SOCK_ERROR - 11) ///< Port number is zero
#define SOCKERR_IPINVALID (SOCK_ERROR - 12) ///< Invalid IP address
#define SOCKERR_TIMEOUT (SOCK_ERROR - 13) ///< Timeout occurred
#define SOCKERR_DATALEN (SOCK_ERROR - 14) ///< Data length is zero or greater than buffer max size.
#define SOCKERR_BUFFER (SOCK_ERROR - 15) ///< Socket buffer is not enough for data communication.
#define SOCKFATAL_PACKLEN (SOCK_FATAL - 1) ///< Invalid packet length. Fatal Error.
/*
* SOCKET FLAG
*/
#define SF_ETHER_OWN (Sn_MR_MFEN) ///< In @ref Sn_MR_MACRAW, Receive only the packet as broadcast, multicast and own packet
#define SF_IGMP_VER2 (Sn_MR_MC) ///< In @ref Sn_MR_UDP with \ref SF_MULTI_ENABLE, Select IGMP version 2.
#define SF_TCP_NODELAY (Sn_MR_ND) ///< In @ref Sn_MR_TCP, Use to nodelayed ack.
#define SF_MULTI_ENABLE (Sn_MR_MULTI) ///< In @ref Sn_MR_UDP, Enable multicast mode.
#if _WIZCHIP_ == 5500
#define SF_BROAD_BLOCK (Sn_MR_BCASTB) ///< In @ref Sn_MR_UDP or @ref Sn_MR_MACRAW, Block broadcast packet. Valid only in W5500
#define SF_MULTI_BLOCK (Sn_MR_MMB) ///< In @ref Sn_MR_MACRAW, Block multicast packet. Valid only in W5500
#define SF_IPv6_BLOCK (Sn_MR_MIP6B) ///< In @ref Sn_MR_MACRAW, Block IPv6 packet. Valid only in W5500
#define SF_UNI_BLOCK (Sn_MR_UCASTB) ///< In @ref Sn_MR_UDP with \ref SF_MULTI_ENABLE. Valid only in W5500
#endif
//A201505 : For W5300
#if _WIZCHIP_ == 5300
#define SF_TCP_ALIGN 0x02 ///< Valid only \ref Sn_MR_TCP and W5300, refer to \ref Sn_MR_ALIGN
#endif
#define SF_IO_NONBLOCK 0x01 ///< Socket nonblock io mode. It used parameter in \ref socket().
/*
* UDP & MACRAW Packet Infomation
*/
#define PACK_FIRST 0x80 ///< In Non-TCP packet, It indicates to start receiving a packet. (When W5300, This flag can be applied)
#define PACK_REMAINED 0x01 ///< In Non-TCP packet, It indicates to remain a packet to be received. (When W5300, This flag can be applied)
#define PACK_COMPLETED 0x00 ///< In Non-TCP packet, It indicates to complete to receive a packet. (When W5300, This flag can be applied)
//A20150601 : For Integrating with W5300
#define PACK_FIFOBYTE 0x02 ///< Valid only W5300, It indicate to have read already the Sn_RX_FIFOR.
//
/**
* @ingroup WIZnet_socket_APIs
* @brief Open a socket.
* @details Initializes the socket with 'sn' passed as parameter and open.
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @param protocol Protocol type to operate such as TCP, UDP and MACRAW.
* @param port Port number to be bined.
* @param flag Socket flags as \ref SF_ETHER_OWN, \ref SF_IGMP_VER2, \ref SF_TCP_NODELAY, \ref SF_MULTI_ENABLE, \ref SF_IO_NONBLOCK and so on.\n
* Valid flags only in W5500 : @ref SF_BROAD_BLOCK, @ref SF_MULTI_BLOCK, @ref SF_IPv6_BLOCK, and @ref SF_UNI_BLOCK.
* @sa Sn_MR
*
* @return @b Success : The socket number @b 'sn' passed as parameter\n
* @b Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number\n
* @ref SOCKERR_SOCKMODE - Not support socket mode as TCP, UDP, and so on. \n
* @ref SOCKERR_SOCKFLAG - Invaild socket flag.
*/
int8_t wizchip_socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag);
/**
* @ingroup WIZnet_socket_APIs
* @brief Close a socket.
* @details It closes the socket with @b'sn' passed as parameter.
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
*
* @return @b Success : @ref SOCK_OK \n
* @b Fail : @ref SOCKERR_SOCKNUM - Invalid socket number
*/
int8_t wizchip_close(uint8_t sn);
/**
* @ingroup WIZnet_socket_APIs
* @brief Listen to a connection request from a client.
* @details It is listening to a connection request from a client.
* If connection request is accepted successfully, the connection is established. Socket sn is used in passive(server) mode.
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @return @b Success : @ref SOCK_OK \n
* @b Fail :\n @ref SOCKERR_SOCKINIT - Socket is not initialized \n
* @ref SOCKERR_SOCKCLOSED - Socket closed unexpectedly.
*/
int8_t wizchip_listen(uint8_t sn);
/**
* @ingroup WIZnet_socket_APIs
* @brief Try to connect a server.
* @details It requests connection to the server with destination IP address and port number passed as parameter.\n
* @note It is valid only in TCP client mode.
* In block io mode, it does not return until connection is completed.
* In Non-block io mode, it return @ref SOCK_BUSY immediately.
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @param addr Pointer variable of destination IP address. It should be allocated 4 bytes.
* @param port Destination port number.
*
* @return @b Success : @ref SOCK_OK \n
* @b Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number\n
* @ref SOCKERR_SOCKMODE - Invalid socket mode\n
* @ref SOCKERR_SOCKINIT - Socket is not initialized\n
* @ref SOCKERR_IPINVALID - Wrong server IP address\n
* @ref SOCKERR_PORTZERO - Server port zero\n
* @ref SOCKERR_TIMEOUT - Timeout occurred during request connection\n
* @ref SOCK_BUSY - In non-block io mode, it returned immediately\n
*/
int8_t wizchip_connect(uint8_t sn, uint8_t * addr, uint16_t port);
/**
* @ingroup WIZnet_socket_APIs
* @brief Try to disconnect a connection socket.
* @details It sends request message to disconnect the TCP socket 'sn' passed as parameter to the server or client.
* @note It is valid only in TCP server or client mode. \n
* In block io mode, it does not return until disconnection is completed. \n
* In Non-block io mode, it return @ref SOCK_BUSY immediately. \n
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @return @b Success : @ref SOCK_OK \n
* @b Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number \n
* @ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
* @ref SOCKERR_TIMEOUT - Timeout occurred \n
* @ref SOCK_BUSY - Socket is busy.
*/
int8_t wizchip_disconnect(uint8_t sn);
/**
* @ingroup WIZnet_socket_APIs
* @brief Send data to the connected peer in TCP socket.
* @details It is used to send outgoing data to the connected socket.
* @note It is valid only in TCP server or client mode. It can't send data greater than socket buffer size. \n
* In block io mode, It doesn't return until data send is completed - socket buffer size is greater than data. \n
* In non-block io mode, It return @ref SOCK_BUSY immediately when socket buffer is not enough. \n
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @param buf Pointer buffer containing data to be sent.
* @param len The byte length of data in buf.
* @return @b Success : The sent data size \n
* @b Fail : \n @ref SOCKERR_SOCKSTATUS - Invalid socket status for socket operation \n
* @ref SOCKERR_TIMEOUT - Timeout occurred \n
* @ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
* @ref SOCKERR_SOCKNUM - Invalid socket number \n
* @ref SOCKERR_DATALEN - zero data length \n
* @ref SOCK_BUSY - Socket is busy.
*/
int32_t wizchip_send(uint8_t sn, uint8_t * buf, uint16_t len);
/**
* @ingroup WIZnet_socket_APIs
* @brief Receive data from the connected peer.
* @details It is used to read incoming data from the connected socket.\n
* It waits for data as much as the application wants to receive.
* @note It is valid only in TCP server or client mode. It can't receive data greater than socket buffer size. \n
* In block io mode, it doesn't return until data reception is completed - data is filled as <I>len</I> in socket buffer. \n
* In non-block io mode, it return @ref SOCK_BUSY immediately when <I>len</I> is greater than data size in socket buffer. \n
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @param buf Pointer buffer to read incoming data.
* @param len The max data length of data in buf.
* @return @b Success : The real received data size \n
* @b Fail :\n
* @ref SOCKERR_SOCKSTATUS - Invalid socket status for socket operation \n
* @ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
* @ref SOCKERR_SOCKNUM - Invalid socket number \n
* @ref SOCKERR_DATALEN - zero data length \n
* @ref SOCK_BUSY - Socket is busy.
*/
int32_t wizchip_recv(uint8_t sn, uint8_t * buf, uint16_t len);
/**
* @ingroup WIZnet_socket_APIs
* @brief Sends datagram to the peer with destination IP address and port number passed as parameter.
* @details It sends datagram of UDP or MACRAW to the peer with destination IP address and port number passed as parameter.\n
* Even if the connectionless socket has been previously connected to a specific address,
* the address and port number parameters override the destination address for that particular datagram only.
* @note In block io mode, It doesn't return until data send is completed - socket buffer size is greater than <I>len</I>.
* In non-block io mode, It return @ref SOCK_BUSY immediately when socket buffer is not enough.
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @param buf Pointer buffer to send outgoing data.
* @param len The byte length of data in buf.
* @param addr Pointer variable of destination IP address. It should be allocated 4 bytes.
* @param port Destination port number.
*
* @return @b Success : The sent data size \n
* @b Fail :\n @ref SOCKERR_SOCKNUM - Invalid socket number \n
* @ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
* @ref SOCKERR_SOCKSTATUS - Invalid socket status for socket operation \n
* @ref SOCKERR_DATALEN - zero data length \n
* @ref SOCKERR_IPINVALID - Wrong server IP address\n
* @ref SOCKERR_PORTZERO - Server port zero\n
* @ref SOCKERR_SOCKCLOSED - Socket unexpectedly closed \n
* @ref SOCKERR_TIMEOUT - Timeout occurred \n
* @ref SOCK_BUSY - Socket is busy.
*/
int32_t wizchip_sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port);
/**
* @ingroup WIZnet_socket_APIs
* @brief Receive datagram of UDP or MACRAW
* @details This function is an application I/F function which is used to receive the data in other then TCP mode. \n
* This function is used to receive UDP and MAC_RAW mode, and handle the header as well.
* This function can divide to received the packet data.
* On the MACRAW SOCKET, the addr and port parameters are ignored.
* @note In block io mode, it doesn't return until data reception is completed - data is filled as <I>len</I> in socket buffer
* In non-block io mode, it return @ref SOCK_BUSY immediately when <I>len</I> is greater than data size in socket buffer.
*
* @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
* @param buf Pointer buffer to read incoming data.
* @param len The max data length of data in buf.
* When the received packet size <= len, receives data as packet sized.
* When others, receives data as len.
* @param addr Pointer variable of destination IP address. It should be allocated 4 bytes.
* It is valid only when the first call recvfrom for receiving the packet.
* When it is valid, @ref packinfo[7] should be set as '1' after call @ref getsockopt(sn, SO_PACKINFO, &packinfo).
* @param port Pointer variable of destination port number.
* It is valid only when the first call recvform for receiving the packet.
* When it is valid, @ref packinfo[7] should be set as '1' after call @ref getsockopt(sn, SO_PACKINFO, &packinfo).
*
* @return @b Success : This function return real received data size for success.\n
* @b Fail : @ref SOCKERR_DATALEN - zero data length \n
* @ref SOCKERR_SOCKMODE - Invalid operation in the socket \n
* @ref SOCKERR_SOCKNUM - Invalid socket number \n
* @ref SOCKBUSY - Socket is busy.
*/
int32_t wizchip_recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port);
/////////////////////////////
// SOCKET CONTROL & OPTION //
/////////////////////////////
#define SOCK_IO_BLOCK 0 ///< Socket Block IO Mode in @ref setsockopt().
#define SOCK_IO_NONBLOCK 1 ///< Socket Non-block IO Mode in @ref setsockopt().
/**
* @defgroup DATA_TYPE DATA TYPE
*/
/**
* @ingroup DATA_TYPE
* @brief The kind of Socket Interrupt.
* @sa Sn_IR, Sn_IMR, setSn_IR(), getSn_IR(), setSn_IMR(), getSn_IMR()
*/
typedef enum
{
SIK_CONNECTED = (1 << 0), ///< connected
SIK_DISCONNECTED = (1 << 1), ///< disconnected
SIK_RECEIVED = (1 << 2), ///< data received
SIK_TIMEOUT = (1 << 3), ///< timeout occurred
SIK_SENT = (1 << 4), ///< send ok
//M20150410 : Remove the comma of last member
//SIK_ALL = 0x1F, ///< all interrupt
SIK_ALL = 0x1F ///< all interrupt
}sockint_kind;
/**
* @ingroup DATA_TYPE
* @brief The type of @ref ctlsocket().
*/
typedef enum
{
CS_SET_IOMODE, ///< set socket IO mode with @ref SOCK_IO_BLOCK or @ref SOCK_IO_NONBLOCK
CS_GET_IOMODE, ///< get socket IO mode
CS_GET_MAXTXBUF, ///< get the size of socket buffer allocated in TX memory
CS_GET_MAXRXBUF, ///< get the size of socket buffer allocated in RX memory
CS_CLR_INTERRUPT, ///< clear the interrupt of socket with @ref sockint_kind
CS_GET_INTERRUPT, ///< get the socket interrupt. refer to @ref sockint_kind
#if _WIZCHIP_ > 5100
CS_SET_INTMASK, ///< set the interrupt mask of socket with @ref sockint_kind, Not supported in W5100
CS_GET_INTMASK ///< get the masked interrupt of socket. refer to @ref sockint_kind, Not supported in W5100
#endif
}ctlsock_type;
/**
* @ingroup DATA_TYPE
* @brief The type of socket option in @ref setsockopt() or @ref getsockopt()
*/
typedef enum
{
SO_FLAG, ///< Valid only in getsockopt(), For set flag of socket refer to <I>flag</I> in @ref socket().
SO_TTL, ///< Set TTL. @ref Sn_TTL ( @ref setSn_TTL(), @ref getSn_TTL() )
SO_TOS, ///< Set TOS. @ref Sn_TOS ( @ref setSn_TOS(), @ref getSn_TOS() )
SO_MSS, ///< Set MSS. @ref Sn_MSSR ( @ref setSn_MSSR(), @ref getSn_MSSR() )
SO_DESTIP, ///< Set the destination IP address. @ref Sn_DIPR ( @ref setSn_DIPR(), @ref getSn_DIPR() )
SO_DESTPORT, ///< Set the destination Port number. @ref Sn_DPORT ( @ref setSn_DPORT(), @ref getSn_DPORT() )
#if _WIZCHIP_ != 5100
SO_KEEPALIVESEND, ///< Valid only in setsockopt. Manually send keep-alive packet in TCP mode, Not supported in W5100
#if !( (_WIZCHIP_ == 5100) || (_WIZCHIP_ == 5200) )
SO_KEEPALIVEAUTO, ///< Set/Get keep-alive auto transmission timer in TCP mode, Not supported in W5100, W5200
#endif
#endif
SO_SENDBUF, ///< Valid only in getsockopt. Get the free data size of Socekt TX buffer. @ref Sn_TX_FSR, @ref getSn_TX_FSR()
SO_RECVBUF, ///< Valid only in getsockopt. Get the received data size in socket RX buffer. @ref Sn_RX_RSR, @ref getSn_RX_RSR()
SO_STATUS, ///< Valid only in getsockopt. Get the socket status. @ref Sn_SR, @ref getSn_SR()
SO_REMAINSIZE, ///< Valid only in getsockopt. Get the remained packet size in other then TCP mode.
SO_PACKINFO ///< Valid only in getsockopt. Get the packet information as @ref PACK_FIRST, @ref PACK_REMAINED, and @ref PACK_COMPLETED in other then TCP mode.
}sockopt_type;
/**
* @ingroup WIZnet_socket_APIs
* @brief Control socket.
* @details Control IO mode, Interrupt & Mask of socket and get the socket buffer information.
* Refer to @ref ctlsock_type.
* @param sn socket number
* @param cstype type of control socket. refer to @ref ctlsock_type.
* @param arg Data type and value is determined according to @ref ctlsock_type. \n
* <table>
* <tr> <td> @b cstype </td> <td> @b data type</td><td>@b value</td></tr>
* <tr> <td> @ref CS_SET_IOMODE \n @ref CS_GET_IOMODE </td> <td> uint8_t </td><td>@ref SOCK_IO_BLOCK @ref SOCK_IO_NONBLOCK</td></tr>
* <tr> <td> @ref CS_GET_MAXTXBUF \n @ref CS_GET_MAXRXBUF </td> <td> uint16_t </td><td> 0 ~ 16K </td></tr>
* <tr> <td> @ref CS_CLR_INTERRUPT \n @ref CS_GET_INTERRUPT \n @ref CS_SET_INTMASK \n @ref CS_GET_INTMASK </td> <td> @ref sockint_kind </td><td> @ref SIK_CONNECTED, etc. </td></tr>
* </table>
* @return @b Success @ref SOCK_OK \n
* @b fail @ref SOCKERR_ARG - Invalid argument\n
*/
int8_t wizchip_ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg);
/**
* @ingroup WIZnet_socket_APIs
* @brief set socket options
* @details Set socket option like as TTL, MSS, TOS, and so on. Refer to @ref sockopt_type.
*
* @param sn socket number
* @param sotype socket option type. refer to @ref sockopt_type
* @param arg Data type and value is determined according to <I>sotype</I>. \n
* <table>
* <tr> <td> @b sotype </td> <td> @b data type</td><td>@b value</td></tr>
* <tr> <td> @ref SO_TTL </td> <td> uint8_t </td><td> 0 ~ 255 </td> </tr>
* <tr> <td> @ref SO_TOS </td> <td> uint8_t </td><td> 0 ~ 255 </td> </tr>
* <tr> <td> @ref SO_MSS </td> <td> uint16_t </td><td> 0 ~ 65535 </td> </tr>
* <tr> <td> @ref SO_DESTIP </td> <td> uint8_t[4] </td><td> </td></tr>
* <tr> <td> @ref SO_DESTPORT </td> <td> uint16_t </td><td> 0 ~ 65535 </td></tr>
* <tr> <td> @ref SO_KEEPALIVESEND </td> <td> null </td><td> null </td></tr>
* <tr> <td> @ref SO_KEEPALIVEAUTO </td> <td> uint8_t </td><td> 0 ~ 255 </td></tr>
* </table>
* @return
* - @b Success : @ref SOCK_OK \n
* - @b Fail
* - @ref SOCKERR_SOCKNUM - Invalid Socket number \n
* - @ref SOCKERR_SOCKMODE - Invalid socket mode \n
* - @ref SOCKERR_SOCKOPT - Invalid socket option or its value \n
* - @ref SOCKERR_TIMEOUT - Timeout occurred when sending keep-alive packet \n
*/
int8_t wizchip_setsockopt(uint8_t sn, sockopt_type sotype, void* arg);
/**
* @ingroup WIZnet_socket_APIs
* @brief get socket options
* @details Get socket option like as FLAG, TTL, MSS, and so on. Refer to @ref sockopt_type
* @param sn socket number
* @param sotype socket option type. refer to @ref sockopt_type
* @param arg Data type and value is determined according to <I>sotype</I>. \n
* <table>
* <tr> <td> @b sotype </td> <td>@b data type</td><td>@b value</td></tr>
* <tr> <td> @ref SO_FLAG </td> <td> uint8_t </td><td> @ref SF_ETHER_OWN, etc... </td> </tr>
* <tr> <td> @ref SO_TOS </td> <td> uint8_t </td><td> 0 ~ 255 </td> </tr>
* <tr> <td> @ref SO_MSS </td> <td> uint16_t </td><td> 0 ~ 65535 </td> </tr>
* <tr> <td> @ref SO_DESTIP </td> <td> uint8_t[4] </td><td> </td></tr>
* <tr> <td> @ref SO_DESTPORT </td> <td> uint16_t </td><td> </td></tr>
* <tr> <td> @ref SO_KEEPALIVEAUTO </td> <td> uint8_t </td><td> 0 ~ 255 </td></tr>
* <tr> <td> @ref SO_SENDBUF </td> <td> uint16_t </td><td> 0 ~ 65535 </td></tr>
* <tr> <td> @ref SO_RECVBUF </td> <td> uint16_t </td><td> 0 ~ 65535 </td></tr>
* <tr> <td> @ref SO_STATUS </td> <td> uint8_t </td><td> @ref SOCK_ESTABLISHED, etc.. </td></tr>
* <tr> <td> @ref SO_REMAINSIZE </td> <td> uint16_t </td><td> 0~ 65535 </td></tr>
* <tr> <td> @ref SO_PACKINFO </td> <td> uint8_t </td><td> @ref PACK_FIRST, etc... </td></tr>
* </table>
* @return
* - @b Success : @ref SOCK_OK \n
* - @b Fail
* - @ref SOCKERR_SOCKNUM - Invalid Socket number \n
* - @ref SOCKERR_SOCKOPT - Invalid socket option or its value \n
* - @ref SOCKERR_SOCKMODE - Invalid socket mode \n
* @note
* The option as PACK_REMAINED and SO_PACKINFO is valid only in NON-TCP mode and after call @ref recvfrom(). \n
* When SO_PACKINFO value is PACK_FIRST and the return value of recvfrom() is zero,
* This means the zero byte UDP data(UDP Header only) received.
*/
int8_t wizchip_getsockopt(uint8_t sn, sockopt_type sotype, void* arg);
#ifdef __cplusplus
}
#endif
#endif // _WIZCHIP_SOCKET_H_

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//*****************************************************************************
//
//! \file wizchip_dhcp.h
//! \brief DHCP APIs Header file.
//! \details Processig DHCP protocol as DISCOVER, OFFER, REQUEST, ACK, NACK and DECLINE.
//! \version 1.1.1
//! \date 2019/10/08
//! \par Revision history
//! <2019/10/08> compare DHCP server ip address
//! <2013/11/18> 1st Release
//! <2012/12/20> V1.1.0
//! 1. Move unreferenced DEFINE to dhcp.c
//! <2012/12/26> V1.1.1
//! \author Eric Jung & MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#ifndef _WIZCHIP_DHCP_H_
#define _WIZCHIP_DHCP_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* @brief
* @details If you want to display debug & processing message, Define _DHCP_DEBUG_
* @note If defined, it depends on <stdio.h>
*/
//#define _DHCP_DEBUG_
/* Retry to processing DHCP */
#define MAX_DHCP_RETRY 2 ///< Maximum retry count
#define DHCP_WAIT_TIME 10 ///< Wait Time 10s
/* UDP port numbers for DHCP */
#define DHCP_SERVER_PORT 67 ///< DHCP server port number
#define DHCP_CLIENT_PORT 68 ///< DHCP client port number
#define MAGIC_COOKIE 0x63825363 ///< You should not modify it number.
#define DCHP_HOST_NAME "WIZnet\0"
/*
* @brief return value of @ref DHCP_run()
*/
enum
{
DHCP_FAILED = 0, ///< Processing Fail
DHCP_RUNNING, ///< Processing DHCP protocol
DHCP_IP_ASSIGN, ///< First Occupy IP from DHPC server (if cbfunc == null, act as default default_ip_assign)
DHCP_IP_CHANGED, ///< Change IP address by new ip from DHCP (if cbfunc == null, act as default default_ip_update)
DHCP_IP_LEASED, ///< Stand by
DHCP_STOPPED ///< Stop processing DHCP protocol
};
/*
* @brief DHCP client initialization (outside of the main loop)
* @param s - socket number
* @param buf - buffer for processing DHCP message
*/
void DHCP_init(uint8_t s, uint8_t * buf);
/*
* @brief DHCP 1s Tick Timer handler
* @note SHOULD BE register to your system 1s Tick timer handler
*/
void DHCP_time_handler(void);
/*
* @brief Register call back function
* @param ip_assign - callback func when IP is assigned from DHCP server first
* @param ip_update - callback func when IP is changed
* @param ip_conflict - callback func when the assigned IP is conflict with others.
*/
void reg_dhcp_cbfunc(void(*ip_assign)(void), void(*ip_update)(void), void(*ip_conflict)(void));
/*
* @brief DHCP client in the main loop
* @return The value is as the follow \n
* @ref DHCP_FAILED \n
* @ref DHCP_RUNNING \n
* @ref DHCP_IP_ASSIGN \n
* @ref DHCP_IP_CHANGED \n
* @ref DHCP_IP_LEASED \n
* @ref DHCP_STOPPED \n
*
* @note This function is always called by you main task.
*/
uint8_t DHCP_run(void);
/*
* @brief Stop DHCP processing
* @note If you want to restart. call DHCP_init() and DHCP_run()
*/
void DHCP_stop(void);
/* Get Network information assigned from DHCP server */
/*
* @brief Get IP address
* @param ip - IP address to be returned
*/
void getIPfromDHCP(uint8_t* ip);
/*
* @brief Get Gateway address
* @param ip - Gateway address to be returned
*/
void getGWfromDHCP(uint8_t* ip);
/*
* @brief Get Subnet mask value
* @param ip - Subnet mask to be returned
*/
void getSNfromDHCP(uint8_t* ip);
/*
* @brief Get DNS address
* @param ip - DNS address to be returned
*/
void getDNSfromDHCP(uint8_t* ip);
/*
* @brief Get the leased time by DHCP sever
* @return unit 1s
*/
uint32_t getDHCPLeasetime(void);
uint32_t getDHCPTick1s(void);
#ifdef __cplusplus
}
#endif
#endif /* _WIZCHIP_DHCP_H_ */

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//*****************************************************************************
//
//! \file wizchip_dns.c
//! \brief DNS APIs Implement file.
//! \details Send DNS query & Receive DNS reponse. \n
//! It depends on stdlib.h & string.h in ansi-c library
//! \version 1.1.0
//! \date 2013/11/18
//! \par Revision history
//! <2013/10/21> 1st Release
//! <2013/12/20> V1.1.0
//! 1. Remove secondary DNS server in DNS_run
//! If 1st DNS_run failed, call DNS_run with 2nd DNS again
//! 2. DNS_timerHandler -> DNS_time_handler
//! 3. Remove the unused define
//! 4. Integrated dns.h dns.c & dns_parse.h dns_parse.c into dns.h & dns.c
//! <2013/12/20> V1.1.0
//!
//! \author Eric Jung & MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include <string.h>
#include <stdlib.h>
#include <wizchip_socket.h>
#include "DNS/wizchip_dns.h"
#ifdef _DNS_DEBUG_
#include <stdio.h>
#endif
#define INITRTT 2000L /* Initial smoothed response time */
#define MAXCNAME (MAX_DOMAIN_NAME + (MAX_DOMAIN_NAME>>1)) /* Maximum amount of cname recursion */
#define TYPE_A 1 /* Host address */
#define TYPE_NS 2 /* Name server */
#define TYPE_MD 3 /* Mail destination (obsolete) */
#define TYPE_MF 4 /* Mail forwarder (obsolete) */
#define TYPE_CNAME 5 /* Canonical name */
#define TYPE_SOA 6 /* Start of Authority */
#define TYPE_MB 7 /* Mailbox name (experimental) */
#define TYPE_MG 8 /* Mail group member (experimental) */
#define TYPE_MR 9 /* Mail rename name (experimental) */
#define TYPE_NULL 10 /* Null (experimental) */
#define TYPE_WKS 11 /* Well-known sockets */
#define TYPE_PTR 12 /* Pointer record */
#define TYPE_HINFO 13 /* Host information */
#define TYPE_MINFO 14 /* Mailbox information (experimental)*/
#define TYPE_MX 15 /* Mail exchanger */
#define TYPE_TXT 16 /* Text strings */
#define TYPE_ANY 255 /* Matches any type */
#define CLASS_IN 1 /* The ARPA Internet */
/* Round trip timing parameters */
#define AGAIN 8 /* Average RTT gain = 1/8 */
#define LAGAIN 3 /* Log2(AGAIN) */
#define DGAIN 4 /* Mean deviation gain = 1/4 */
#define LDGAIN 2 /* log2(DGAIN) */
/* Header for all domain messages */
struct dhdr
{
uint16_t id; /* Identification */
uint8_t qr; /* Query/Response */
#define QUERY 0
#define RESPONSE 1
uint8_t opcode;
#define IQUERY 1
uint8_t aa; /* Authoratative answer */
uint8_t tc; /* Truncation */
uint8_t rd; /* Recursion desired */
uint8_t ra; /* Recursion available */
uint8_t rcode; /* Response code */
#define NO_ERROR 0
#define FORMAT_ERROR 1
#define SERVER_FAIL 2
#define NAME_ERROR 3
#define NOT_IMPL 4
#define REFUSED 5
uint16_t qdcount; /* Question count */
uint16_t ancount; /* Answer count */
uint16_t nscount; /* Authority (name server) count */
uint16_t arcount; /* Additional record count */
};
uint8_t* pDNSMSG; // DNS message buffer
uint8_t DNS_SOCKET; // SOCKET number for DNS
uint16_t DNS_MSGID; // DNS message ID
uint32_t dns_1s_tick; // for timout of DNS processing
static uint8_t retry_count;
/* converts uint16_t from network buffer to a host byte order integer. */
uint16_t get16(uint8_t * s)
{
uint16_t i;
i = *s++ << 8;
i = i + *s;
return i;
}
/* copies uint16_t to the network buffer with network byte order. */
uint8_t * put16(uint8_t * s, uint16_t i)
{
*s++ = i >> 8;
*s++ = i;
return s;
}
/*
* CONVERT A DOMAIN NAME TO THE HUMAN-READABLE FORM
*
* Description : This function converts a compressed domain name to the human-readable form
* Arguments : msg - is a pointer to the reply message
* compressed - is a pointer to the domain name in reply message.
* buf - is a pointer to the buffer for the human-readable form name.
* len - is the MAX. size of buffer.
* Returns : the length of compressed message
*/
int parse_name(uint8_t * msg, uint8_t * compressed, char * buf, int16_t len)
{
uint16_t slen; /* Length of current segment */
uint8_t * cp;
int clen = 0; /* Total length of compressed name */
int indirect = 0; /* Set if indirection encountered */
int nseg = 0; /* Total number of segments in name */
cp = compressed;
for (;;)
{
slen = *cp++; /* Length of this segment */
if (!indirect) clen++;
if ((slen & 0xc0) == 0xc0)
{
if (!indirect)
clen++;
indirect = 1;
/* Follow indirection */
cp = &msg[((slen & 0x3f)<<8) + *cp];
slen = *cp++;
}
if (slen == 0) /* zero length == all done */
break;
len -= slen + 1;
if (len < 0) return -1;
if (!indirect) clen += slen;
while (slen-- != 0) *buf++ = (char)*cp++;
*buf++ = '.';
nseg++;
}
if (nseg == 0)
{
/* Root name; represent as single dot */
*buf++ = '.';
len--;
}
*buf++ = '\0';
len--;
return clen; /* Length of compressed message */
}
/*
* PARSE QUESTION SECTION
*
* Description : This function parses the qeustion record of the reply message.
* Arguments : msg - is a pointer to the reply message
* cp - is a pointer to the qeustion record.
* Returns : a pointer the to next record.
*/
uint8_t * dns_question(uint8_t * msg, uint8_t * cp)
{
int len;
char name[MAXCNAME];
len = parse_name(msg, cp, name, MAXCNAME);
if (len == -1) return 0;
cp += len;
cp += 2; /* type */
cp += 2; /* class */
return cp;
}
/*
* PARSE ANSER SECTION
*
* Description : This function parses the answer record of the reply message.
* Arguments : msg - is a pointer to the reply message
* cp - is a pointer to the answer record.
* Returns : a pointer the to next record.
*/
uint8_t * dns_answer(uint8_t * msg, uint8_t * cp, uint8_t * ip_from_dns)
{
int len, type;
char name[MAXCNAME];
len = parse_name(msg, cp, name, MAXCNAME);
if (len == -1) return 0;
cp += len;
type = get16(cp);
cp += 2; /* type */
cp += 2; /* class */
cp += 4; /* ttl */
cp += 2; /* len */
switch (type)
{
case TYPE_A:
/* Just read the address directly into the structure */
ip_from_dns[0] = *cp++;
ip_from_dns[1] = *cp++;
ip_from_dns[2] = *cp++;
ip_from_dns[3] = *cp++;
break;
case TYPE_CNAME:
case TYPE_MB:
case TYPE_MG:
case TYPE_MR:
case TYPE_NS:
case TYPE_PTR:
/* These types all consist of a single domain name */
/* convert it to ascii format */
len = parse_name(msg, cp, name, MAXCNAME);
if (len == -1) return 0;
cp += len;
break;
case TYPE_HINFO:
len = *cp++;
cp += len;
len = *cp++;
cp += len;
break;
case TYPE_MX:
cp += 2;
/* Get domain name of exchanger */
len = parse_name(msg, cp, name, MAXCNAME);
if (len == -1) return 0;
cp += len;
break;
case TYPE_SOA:
/* Get domain name of name server */
len = parse_name(msg, cp, name, MAXCNAME);
if (len == -1) return 0;
cp += len;
/* Get domain name of responsible person */
len = parse_name(msg, cp, name, MAXCNAME);
if (len == -1) return 0;
cp += len;
cp += 4;
cp += 4;
cp += 4;
cp += 4;
cp += 4;
break;
case TYPE_TXT:
/* Just stash */
break;
default:
/* Ignore */
break;
}
return cp;
}
/*
* PARSE THE DNS REPLY
*
* Description : This function parses the reply message from DNS server.
* Arguments : dhdr - is a pointer to the header for DNS message
* buf - is a pointer to the reply message.
* len - is the size of reply message.
* Returns : -1 - Domain name lenght is too big
* 0 - Fail (Timout or parse error)
* 1 - Success,
*/
int8_t parseDNSMSG(struct dhdr * pdhdr, uint8_t * pbuf, uint8_t * ip_from_dns)
{
uint16_t tmp;
uint16_t i;
uint8_t * msg;
uint8_t * cp;
msg = pbuf;
memset(pdhdr, 0, sizeof(*pdhdr));
pdhdr->id = get16(&msg[0]);
tmp = get16(&msg[2]);
if (tmp & 0x8000) pdhdr->qr = 1;
pdhdr->opcode = (tmp >> 11) & 0xf;
if (tmp & 0x0400) pdhdr->aa = 1;
if (tmp & 0x0200) pdhdr->tc = 1;
if (tmp & 0x0100) pdhdr->rd = 1;
if (tmp & 0x0080) pdhdr->ra = 1;
pdhdr->rcode = tmp & 0xf;
pdhdr->qdcount = get16(&msg[4]);
pdhdr->ancount = get16(&msg[6]);
pdhdr->nscount = get16(&msg[8]);
pdhdr->arcount = get16(&msg[10]);
/* Now parse the variable length sections */
cp = &msg[12];
/* Question section */
for (i = 0; i < pdhdr->qdcount; i++)
{
cp = dns_question(msg, cp);
#ifdef _DNS_DEUBG_
printf("MAX_DOMAIN_NAME is too small, it should be redfine in dns.h");
#endif
if(!cp) return -1;
}
/* Answer section */
for (i = 0; i < pdhdr->ancount; i++)
{
cp = dns_answer(msg, cp, ip_from_dns);
#ifdef _DNS_DEUBG_
printf("MAX_DOMAIN_NAME is too small, it should be redfine in dns.h");
#endif
if(!cp) return -1;
}
/* Name server (authority) section */
for (i = 0; i < pdhdr->nscount; i++)
{
;
}
/* Additional section */
for (i = 0; i < pdhdr->arcount; i++)
{
;
}
if(pdhdr->rcode == 0) return 1; // No error
else return 0;
}
/*
* MAKE DNS QUERY MESSAGE
*
* Description : This function makes DNS query message.
* Arguments : op - Recursion desired
* name - is a pointer to the domain name.
* buf - is a pointer to the buffer for DNS message.
* len - is the MAX. size of buffer.
* Returns : the pointer to the DNS message.
*/
int16_t dns_makequery(uint16_t op, char * name, uint8_t * buf, uint16_t len)
{
uint8_t *cp;
char *cp1;
char sname[MAXCNAME];
char *dname;
uint16_t p;
uint16_t dlen;
cp = buf;
DNS_MSGID++;
cp = put16(cp, DNS_MSGID);
p = (op << 11) | 0x0100; /* Recursion desired */
cp = put16(cp, p);
cp = put16(cp, 1);
cp = put16(cp, 0);
cp = put16(cp, 0);
cp = put16(cp, 0);
strcpy(sname, name);
dname = sname;
dlen = strlen(dname);
for (;;)
{
/* Look for next dot */
cp1 = strchr(dname, '.');
if (cp1 != NULL) len = cp1 - dname; /* More to come */
else len = dlen; /* Last component */
*cp++ = len; /* Write length of component */
if (len == 0) break;
/* Copy component up to (but not including) dot */
strncpy((char *)cp, dname, len);
cp += len;
if (cp1 == NULL)
{
*cp++ = 0; /* Last one; write null and finish */
break;
}
dname += len+1;
dlen -= len+1;
}
cp = put16(cp, 0x0001); /* type */
cp = put16(cp, 0x0001); /* class */
return ((int16_t)((uint32_t)(cp) - (uint32_t)(buf)));
}
/*
* CHECK DNS TIMEOUT
*
* Description : This function check the DNS timeout
* Arguments : None.
* Returns : -1 - timeout occurred, 0 - timer over, but no timeout, 1 - no timer over, no timeout occur
* Note : timeout : retry count and timer both over.
*/
int8_t check_DNS_timeout(void)
{
if(dns_1s_tick >= DNS_WAIT_TIME)
{
dns_1s_tick = 0;
if(retry_count >= MAX_DNS_RETRY) {
retry_count = 0;
return -1; // timeout occurred
}
retry_count++;
return 0; // timer over, but no timeout
}
return 1; // no timer over, no timeout occur
}
/* DNS CLIENT INIT */
void DNS_init(uint8_t s, uint8_t * buf)
{
DNS_SOCKET = s; // SOCK_DNS
pDNSMSG = buf; // User's shared buffer
DNS_MSGID = DNS_MSG_ID;
}
/* DNS CLIENT RUN */
int8_t DNS_run(uint8_t * dns_ip, uint8_t * name, uint8_t * ip_from_dns)
{
int8_t ret;
struct dhdr dhp;
uint8_t ip[4];
uint16_t len, port;
int8_t ret_check_timeout;
retry_count = 0;
dns_1s_tick = 0;
// Socket open
wizchip_socket(DNS_SOCKET, Sn_MR_UDP, 0, 0);
#ifdef _DNS_DEBUG_
printf("> DNS Query to DNS Server : %d.%d.%d.%d\r\n", dns_ip[0], dns_ip[1], dns_ip[2], dns_ip[3]);
#endif
len = dns_makequery(0, (char *)name, pDNSMSG, MAX_DNS_BUF_SIZE);
wizchip_sendto(DNS_SOCKET, pDNSMSG, len, dns_ip, IPPORT_DOMAIN);
while (1)
{
if ((len = getSn_RX_RSR(DNS_SOCKET)) > 0)
{
if (len > MAX_DNS_BUF_SIZE) len = MAX_DNS_BUF_SIZE;
len = wizchip_recvfrom(DNS_SOCKET, pDNSMSG, len, ip, &port);
#ifdef _DNS_DEBUG_
printf("> Receive DNS message from %d.%d.%d.%d(%d). len = %d\r\n", ip[0], ip[1], ip[2], ip[3],port,len);
#endif
ret = parseDNSMSG(&dhp, pDNSMSG, ip_from_dns);
break;
}
// Check Timeout
ret_check_timeout = check_DNS_timeout();
if (ret_check_timeout < 0) {
#ifdef _DNS_DEBUG_
printf("> DNS Server is not responding : %d.%d.%d.%d\r\n", dns_ip[0], dns_ip[1], dns_ip[2], dns_ip[3]);
#endif
wizchip_close(DNS_SOCKET);
return 0; // timeout occurred
}
else if (ret_check_timeout == 0) {
#ifdef _DNS_DEBUG_
printf("> DNS Timeout\r\n");
#endif
wizchip_sendto(DNS_SOCKET, pDNSMSG, len, dns_ip, IPPORT_DOMAIN);
}
}
wizchip_close(DNS_SOCKET);
// Return value
// 0 > : failed / 1 - success
return ret;
}
/* DNS TIMER HANDLER */
void DNS_time_handler(void)
{
dns_1s_tick++;
}

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//*****************************************************************************
//
//! \file wizchip_dns.h
//! \brief DNS APIs Header file.
//! \details Send DNS query & Receive DNS reponse.
//! \version 1.1.0
//! \date 2013/11/18
//! \par Revision history
//! <2013/10/21> 1st Release
//! <2013/12/20> V1.1.0
//! 1. Remove secondary DNS server in DNS_run
//! If 1st DNS_run failed, call DNS_run with 2nd DNS again
//! 2. DNS_timerHandler -> DNS_time_handler
//! 3. Move the no reference define to dns.c
//! 4. Integrated dns.h dns.c & dns_parse.h dns_parse.c into dns.h & dns.c
//! <2013/12/20> V1.1.0
//!
//! \author Eric Jung & MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#ifndef _WIZCHIP_DNS_H_
#define _WIZCHIP_DNS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*
* @brief Define it for Debug & Monitor DNS processing.
* @note If defined, it dependens on <stdio.h>
*/
//#define _DNS_DEBUG_
#define MAX_DNS_BUF_SIZE 256 ///< maximum size of DNS buffer. */
/*
* @brief Maxium length of your queried Domain name
* @todo SHOULD BE defined it equal as or greater than your Domain name lenght + null character(1)
* @note SHOULD BE careful to stack overflow because it is allocated 1.5 times as MAX_DOMAIN_NAME in stack.
*/
#define MAX_DOMAIN_NAME 16 // for example "www.google.com"
#define MAX_DNS_RETRY 2 ///< Requery Count
#define DNS_WAIT_TIME 3 ///< Wait response time. unit 1s.
#define IPPORT_DOMAIN 53 ///< DNS server port number
#define DNS_MSG_ID 0x1122 ///< ID for DNS message. You can be modifyed it any number
/*
* @brief DNS process initialize
* @param s : Socket number for DNS
* @param buf : Buffer for DNS message
*/
void DNS_init(uint8_t s, uint8_t * buf);
/*
* @brief DNS process
* @details Send DNS query and receive DNS response
* @param dns_ip : DNS server ip
* @param name : Domain name to be queryed
* @param ip_from_dns : IP address from DNS server
* @return -1 : failed. @ref MAX_DOMIN_NAME is too small \n
* 0 : failed (Timeout or Parse error)\n
* 1 : success
* @note This funtion blocks until success or fail. max time = @ref MAX_DNS_RETRY * @ref DNS_WAIT_TIME
*/
int8_t DNS_run(uint8_t * dns_ip, uint8_t * name, uint8_t * ip_from_dns);
/*
* @brief DNS 1s Tick Timer handler
* @note SHOULD BE register to your system 1s Tick timer handler
*/
void DNS_time_handler(void);
#ifdef __cplusplus
}
#endif
#endif /* _WIZCHIP_DNS_H_ */

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-26 chenyong first version
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wiz.h>
#include <wiz_socket.h>
//h此处为添加内容
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_spi.h"
#ifdef __cplusplus
}
#endif
//添加内容结束
#include <W5500/w5500.h>
#ifdef WIZ_USING_DHCP
#include <DHCP/wizchip_dhcp.h>
#endif
#include <arpa/inet.h>
#include <netdev.h>
#if !defined(WIZ_SPI_DEVICE) || !defined(WIZ_RST_PIN) || !defined(WIZ_IRQ_PIN)
#error "please config SPI device name, reset pin and irq pin in menuconfig."
#endif
#define DBG_ENABLE
#define DBG_SECTION_NAME "wiz"
#ifdef WIZ_DEBUG
#define DBG_LEVEL DBG_LOG
#else
#define DBG_LEVEL DBG_INFO
#endif /* WIZ_DEBUG */
#define DBG_COLOR
#include <rtdbg.h>
#define IMR_SENDOK 0x10
#define IMR_TIMEOUT 0x08
#define IMR_RECV 0x04
#define IMR_DISCON 0x02
#define IMR_CON 0x01
#define WIZ_DEFAULT_MAC "00-E0-81-DC-53-1A"
#define WIZ_ID_LEN 6
static char wiz_netdev_name[WIZ_ID_LEN];
#define WIZ_DHCP_SOCKET 7
extern struct rt_spi_device *wiz_device;
extern int wiz_device_init(const char *spi_dev_name);
extern int wiz_inet_init(void);
static int wiz_netdev_info_update(struct netdev *netdev, rt_bool_t reset);
rt_bool_t wiz_init_ok = RT_FALSE;
static wiz_NetInfo wiz_net_info;
static rt_timer_t dns_tick_timer;
#ifdef WIZ_USING_DHCP
static rt_timer_t dhcp_timer;
#endif
static struct rt_work *dhcp_work = RT_NULL;
extern int wiz_recv_notice_cb(int socket);
extern int wiz_closed_notice_cb(int socket);
static rt_mailbox_t wiz_rx_mb = RT_NULL;
static void wiz_isr(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_mb_send(wiz_rx_mb, (rt_ubase_t) wiz_device);
/* leave interrupt */
rt_interrupt_leave();
}
static void wiz_data_thread_entry(void *parameter)
{
#define IR_SOCK(ch) (0x01 << ch) /**< check socket interrupt */
struct rt_spi_device* dev;
while (1)
{
if (rt_mb_recv(wiz_rx_mb, (rt_ubase_t*) &dev, RT_WAITING_FOREVER) == RT_EOK)
{
uint8_t ir, sir, sn_ir;
int8_t socket = -1;
/* get IR data than clean IR */
ir = getIR();
setIR(ir);
if ((ir & IR_CONFLICT) == IR_CONFLICT)
{
setIR(IR_CONFLICT);
}
if ((ir & IR_UNREACH) == IR_UNREACH)
{
setIR(IR_UNREACH);
}
/* get and process socket interrupt register */
sir = getSIR();
for (socket = 0; socket < 8; socket++)
{
sn_ir = 0;
if (sir & IR_SOCK(socket))
{
/* save interrupt value*/
sn_ir = getSn_IR(socket);
if (sn_ir & Sn_IR_CON)
{
setSn_IR(socket, Sn_IR_CON);
}
if (sn_ir & Sn_IR_DISCON)
{
wiz_closed_notice_cb(socket);
setSn_IR(socket, Sn_IR_DISCON);
}
if (sn_ir & Sn_IR_RECV)
{
wiz_recv_notice_cb(socket);
setSn_IR(socket, Sn_IR_RECV);
}
if (sn_ir & Sn_IR_TIMEOUT)
{
/* deal with timeout event in the wiznet ioLibrary */
//setSn_IR(socket, Sn_IR_TIMEOUT);
}
}
}
}
}
}
static void spi_write_byte(uint8_t data)
{
struct rt_spi_message spi_msg;
rt_memset(&spi_msg, 0x00, sizeof(spi_msg));
spi_msg.send_buf = &data;
spi_msg.length = 1;
rt_spi_transfer_message(wiz_device, &spi_msg);
}
static uint8_t spi_read_byte(void)
{
struct rt_spi_message spi_msg;
uint8_t data;
rt_memset(&spi_msg, 0x00, sizeof(spi_msg));
spi_msg.recv_buf = &data;
spi_msg.length = 1;
rt_spi_transfer_message(wiz_device, &spi_msg);
return data;
}
static void spi_write_burst(uint8_t *pbuf, uint16_t len)
{
struct rt_spi_message spi_msg;
rt_memset(&spi_msg, 0x00, sizeof(spi_msg));
spi_msg.send_buf = pbuf;
spi_msg.length = len;
rt_spi_transfer_message(wiz_device, &spi_msg);
}
static void spi_read_burst(uint8_t *pbuf, uint16_t len)
{
struct rt_spi_message spi_msg;
rt_memset(&spi_msg, 0x00, sizeof(spi_msg));
spi_msg.recv_buf = pbuf;
spi_msg.length = len;
rt_spi_transfer_message(wiz_device, &spi_msg);
}
static void spi_cris_enter(void)
{
rt_spi_take_bus(wiz_device);
}
static void spi_cris_exit(void)
{
rt_spi_release_bus(wiz_device);
}
static void spi_cs_select(void)
{
rt_spi_take(wiz_device);
}
static void spi_cs_deselect(void)
{
rt_spi_release(wiz_device);
}
/* register TCP communication related callback function */
static int wiz_callback_register(void)
{
/* register critical section callback function */
reg_wizchip_cris_cbfunc(spi_cris_enter, spi_cris_exit);
#if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_VDM_) || (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_FDM_)
/* register SPI device CS select callback function */
reg_wizchip_cs_cbfunc(spi_cs_select, spi_cs_deselect);
#else
#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SIP_) != _WIZCHIP_IO_MODE_SIP_
#error "Unknown _WIZCHIP_IO_MODE_"
#else
reg_wizchip_cs_cbfunc(wizchip_select, wizchip_deselect);
#endif
#endif
/* register SPI device read/write data callback function */
reg_wizchip_spi_cbfunc(spi_read_byte, spi_write_byte);
reg_wizchip_spiburst_cbfunc(spi_read_burst, spi_write_burst);
return RT_EOK;
}
/* initialize WIZnet chip configures */
static int wiz_chip_cfg_init(void)
{
#define CW_INIT_MODE 2
#define CW_INIT_SOCKETS 8
#define CW_INIT_TIMEOUT (2 * RT_TICK_PER_SECOND)
uint8_t memsize[CW_INIT_MODE][CW_INIT_SOCKETS] = { 0 };
/* reset WIZnet chip internal PHY, configures PHY mode. */
if (ctlwizchip(CW_INIT_WIZCHIP, (void*) memsize) == -1)
{
LOG_E("WIZCHIP initialize failed.");
return -RT_ERROR;
}
struct wiz_NetTimeout_t net_timeout;
net_timeout.retry_cnt=5;
net_timeout.time_100us=20000;
ctlnetwork(CN_SET_TIMEOUT, (void*) &net_timeout);
return RT_EOK;
}
/* WIZnet chip hardware reset */
static void wiz_reset(void)
{
rt_pin_write(WIZ_RST_PIN, PIN_LOW);
rt_thread_mdelay(2);
rt_pin_write(WIZ_RST_PIN, PIN_HIGH);
rt_thread_mdelay(2);
}
#ifdef WIZ_USING_DHCP
static void wiz_ip_assign(void)
{
/* get the assigned IP address and reconfigure the IP address of the chip */
getIPfromDHCP(wiz_net_info.ip);
getGWfromDHCP(wiz_net_info.gw);
getSNfromDHCP(wiz_net_info.sn);
getDNSfromDHCP(wiz_net_info.dns);
wiz_net_info.dhcp = NETINFO_DHCP;
ctlnetwork(CN_SET_NETINFO, (void*) &wiz_net_info);
}
static void wiz_ip_conflict(void)
{
/* deal with conflict IP for WIZnet DHCP */
LOG_D("conflict IP from DHCP.");
RT_ASSERT(0);
}
static void wiz_dhcp_timer_entry(void *parameter)
{
DHCP_time_handler();
}
#endif /* WIZ_USING_DHCP */
static int wiz_netstr_to_array(const char *net_str, uint8_t *net_array)
{
int ret;
unsigned int idx;
RT_ASSERT(net_str);
RT_ASSERT(net_array);
if (strstr(net_str, "."))
{
int ip_addr[4];
/* resolve IP address, gateway address or subnet mask */
ret = sscanf(net_str, "%d.%d.%d.%d", ip_addr + 0, ip_addr + 1, ip_addr + 2, ip_addr + 3);
if (ret != 4)
{
LOG_E("input address(%s) resolve error.", net_str);
return -RT_ERROR;
}
for (idx = 0; idx < sizeof(ip_addr)/sizeof(ip_addr[0]); idx++)
{
net_array[idx] = ip_addr[idx];
}
}
else
{
int mac_addr[6];
/* resolve MAC address */
if (strstr(net_str, ":"))
{
ret = sscanf(net_str, "%02x:%02x:%02x:%02x:%02x:%02x", mac_addr + 0, mac_addr + 1, mac_addr + 2,
mac_addr + 3, mac_addr + 4, mac_addr + 5);
}
else if (strstr(net_str, "-"))
{
ret = sscanf(net_str, "%02x-%02x-%02x-%02x-%02x-%02x", mac_addr + 0, mac_addr + 1, mac_addr + 2,
mac_addr + 3, mac_addr + 4, mac_addr + 5);
}
else
{
LOG_E("input MAC address(%s) format error.", net_str);
return -RT_ERROR;
}
if (ret != 6)
{
LOG_E("input MAC address(%s) resolve error.", net_str);
return -RT_ERROR;
}
for (idx = 0; idx < sizeof(mac_addr)/sizeof(mac_addr[0]); idx++)
{
net_array[idx] = mac_addr[idx];
}
}
return RT_EOK;
}
/* set WIZnet device MAC address */
RT_WEAK void wiz_user_config_mac(char *mac_buf, rt_uint8_t buf_len)
{
RT_ASSERT(mac_buf != RT_NULL);
RT_ASSERT(buf_len > 0);
rt_memset(mac_buf, 0x0, buf_len);
rt_strncpy(mac_buf, WIZ_DEFAULT_MAC, buf_len);
}
static void wiz_set_mac(void)
{
char mac_str[32];
wiz_user_config_mac(mac_str, sizeof(mac_str));
if (wiz_netstr_to_array(mac_str, wiz_net_info.mac) != RT_EOK)
{
wiz_netstr_to_array(WIZ_DEFAULT_MAC, wiz_net_info.mac);
}
}
#ifdef WIZ_USING_DHCP
static int wiz_network_dhcp(struct netdev *netdev);
#endif
/* initialize WIZnet network configures */
static int wiz_network_init(rt_bool_t b_config)
{
struct netdev * netdev;
netdev = netdev_get_by_name(wiz_netdev_name);
if (netdev == RT_NULL)
{
LOG_E("don`t find device(%s)", wiz_netdev_name);
return -RT_ERROR;
}
#ifndef WIZ_USING_DHCP
if(wiz_netstr_to_array(WIZ_IPADDR, wiz_net_info.ip) != RT_EOK ||
wiz_netstr_to_array(WIZ_MSKADDR, wiz_net_info.sn) != RT_EOK ||
wiz_netstr_to_array(WIZ_GWADDR, wiz_net_info.dns) != RT_EOK ||
wiz_netstr_to_array(WIZ_GWADDR, wiz_net_info.gw) != RT_EOK)
{
netdev_low_level_set_status(netdev, RT_FALSE);
netdev_low_level_set_link_status(netdev, RT_FALSE);
return -RT_ERROR;
}
wiz_net_info.dhcp = NETINFO_STATIC;
#endif
int result = RT_EOK;
rt_bool_t b_status = b_config;
/* set mac information */
wiz_set_mac();
/* set static WIZnet network information */
ctlnetwork(CN_SET_NETINFO, (void*) &wiz_net_info);
#ifdef WIZ_USING_DHCP
/* alloc IP address through DHCP */
{
result = wiz_network_dhcp(netdev);
if (result != RT_EOK)
{
b_status = RT_FALSE;
LOG_E("WIZnet network initialize failed, DHCP timeout.");
}
else
{
b_status = RT_TRUE;
LOG_D("WIZnet network initialize success.");
}
}
#endif
netdev_low_level_set_status(netdev, b_status);
wiz_netdev_info_update(netdev, RT_FALSE);
netdev_low_level_set_link_status(netdev, b_status);
return result;
}
/* wizenet socket initialize */
static int wiz_socket_init(void)
{
int idx = 0;
/* socket(0-7) initialize */
setSIMR(0xff);
/* set socket receive/send buffer size */
for (idx = 0; idx < WIZ_SOCKETS_NUM; idx++)
{
setSn_RXBUF_SIZE(idx, 0x02);
setSn_TXBUF_SIZE(idx, 0x02);
}
/* set socket ISR state support */
for (idx = 0; idx < WIZ_SOCKETS_NUM; idx++)
{
setSn_IMR(idx, (IMR_TIMEOUT | IMR_RECV | IMR_DISCON));
}
return RT_EOK;
}
static void wiz_dns_time_handler(void *arg)
{
extern void DNS_time_handler(void);
DNS_time_handler();
}
static int wiz_netdev_info_update(struct netdev *netdev, rt_bool_t reset)
{
wiz_NetInfo net_info;
rt_memset(&net_info, 0, sizeof(net_info));
if(reset == RT_FALSE)
{
ctlnetwork(CN_GET_NETINFO, (void *)&net_info);
}
else
{
/* clean dns server information */
netdev->dns_servers->addr = 0;
ctlnetwork(CN_SET_NETINFO, (void *)&net_info);
}
netdev_low_level_set_ipaddr(netdev, (const ip_addr_t *)&net_info.ip);
netdev_low_level_set_gw(netdev, (const ip_addr_t *)&net_info.gw);
netdev_low_level_set_netmask(netdev, (const ip_addr_t *)&net_info.sn);
netdev_low_level_set_dns_server(netdev, 0, (const ip_addr_t *)&net_info.dns);
memcpy(netdev->hwaddr, (const void *)&net_info.mac, netdev->hwaddr_len);
/* 1 - Static, 2 - DHCP */
netdev_low_level_set_dhcp_status(netdev, net_info.dhcp - 1);
return RT_EOK;
}
static int wiz_netdev_set_up(struct netdev *netdev)
{
netdev_low_level_set_status(netdev, RT_TRUE);
return RT_EOK;
}
static int wiz_netdev_set_down(struct netdev *netdev)
{
netdev_low_level_set_status(netdev, RT_FALSE);
return RT_EOK;
}
static int wiz_netdev_set_addr_info(struct netdev *netdev, ip_addr_t *ip_addr, ip_addr_t *netmask, ip_addr_t *gw)
{
rt_err_t result = RT_EOK;
RT_ASSERT(netdev);
RT_ASSERT(ip_addr || netmask || gw);
ctlnetwork(CN_GET_NETINFO, (void *)&wiz_net_info);
if (ip_addr)
rt_memcpy(wiz_net_info.ip, &ip_addr->addr, sizeof(wiz_net_info.ip));
if (netmask)
rt_memcpy(wiz_net_info.sn, &netmask->addr, sizeof(wiz_net_info.sn));
if (gw)
rt_memcpy(wiz_net_info.gw, &gw->addr, sizeof(wiz_net_info.gw));
if (ctlnetwork(CN_SET_NETINFO, (void *)&wiz_net_info) == RT_EOK)
{
if (ip_addr)
netdev_low_level_set_ipaddr(netdev, ip_addr);
if (netmask)
netdev_low_level_set_netmask(netdev, netmask);
if (gw)
netdev_low_level_set_gw(netdev, gw);
result = RT_EOK;
}
else
{
LOG_E("%s set addr info failed!", wiz_netdev_name);
result = -RT_ERROR;
}
return result;
}
static int wiz_netdev_set_dns_server(struct netdev *netdev, uint8_t dns_num, ip_addr_t *dns_server)
{
rt_err_t result = RT_EOK;
RT_ASSERT(netdev);
RT_ASSERT(dns_server);
ctlnetwork(CN_GET_NETINFO, (void *)&wiz_net_info);
rt_memcpy(wiz_net_info.dns, &dns_server->addr, sizeof(wiz_net_info.dns));
if (ctlnetwork(CN_SET_NETINFO, (void *)&wiz_net_info) == RT_EOK)
{
netdev_low_level_set_dns_server(netdev, dns_num, (const ip_addr_t *)dns_server);
result = RT_EOK;
}
else
{
LOG_E("%s set dns server failed!", wiz_netdev_name);
result = -RT_ERROR;
}
return result;
}
static int wiz_netdev_set_dhcp(struct netdev *netdev, rt_bool_t is_enabled)
{
rt_err_t result = RT_EOK;
RT_ASSERT(netdev);
ctlnetwork(CN_GET_NETINFO, (void *)&wiz_net_info);
/* 1 - Static, 2 - DHCP */
wiz_net_info.dhcp = (dhcp_mode)(is_enabled + 1);
if (ctlnetwork(CN_SET_NETINFO, (void *)&wiz_net_info) == RT_EOK)
{
netdev_low_level_set_dhcp_status(netdev, is_enabled);
result = RT_EOK;
if(is_enabled == RT_FALSE)
{
if(dhcp_work != RT_NULL)
{
rt_work_cancel(dhcp_work);
}
LOG_D("wiznet(w5500) dhcp status is disable.");
}
else
{
#ifndef WIZ_USING_DHCP
LOG_W("wiznet(w5500) dhcp function haven't compiled.");
result = -RT_ERROR;
#else
if(dhcp_work != RT_NULL)
{
rt_work_submit(dhcp_work, RT_WAITING_NO);
LOG_D("wiznet(w5500) dhcp status is enable.");
}
#endif
}
}
else
{
LOG_E("%s set dhcp info failed!", wiz_netdev_name);
result = -RT_ERROR;
}
return result;
}
#ifdef RT_USING_FINSH
static int wiz_netdev_ping(struct netdev *netdev, const char *host, size_t data_len, uint32_t timeout, struct netdev_ping_resp *ping_resp)
{
RT_ASSERT(netdev);
RT_ASSERT(host);
RT_ASSERT(ping_resp);
extern int wiz_ping(struct netdev *netdev, const char *host, size_t data_len, uint32_t times, struct netdev_ping_resp *ping_resp);
return wiz_ping(netdev, host, data_len, timeout, ping_resp);
}
#endif
void wiz_netdev_netstat(struct netdev *netdev)
{
// TODO
return;
}
const struct netdev_ops wiz_netdev_ops =
{
wiz_netdev_set_up,
wiz_netdev_set_down,
wiz_netdev_set_addr_info,
wiz_netdev_set_dns_server,
wiz_netdev_set_dhcp,
#ifdef RT_USING_FINSH
wiz_netdev_ping,
wiz_netdev_netstat,
#endif
};
static struct netdev *wiz_netdev_add(const char *netdev_name)
{
#define ETHERNET_MTU 1472
#define HWADDR_LEN 6
struct netdev *netdev = RT_NULL;
netdev = (struct netdev *)rt_calloc(1, sizeof(struct netdev));
if (netdev == RT_NULL)
{
return RT_NULL;
}
netdev->flags = 0;
netdev->mtu = ETHERNET_MTU;
netdev->ops = &wiz_netdev_ops;
netdev->hwaddr_len = HWADDR_LEN;
#ifdef PKG_USING_WIZNET
extern int sal_wiz_netdev_set_pf_info(struct netdev *netdev);
/* set the network interface socket/netdb operations */
sal_wiz_netdev_set_pf_info(netdev);
#endif
netdev_register(netdev, netdev_name, RT_NULL);
return netdev;
}
#ifdef WIZ_USING_DHCP
static void wiz_dhcp_work(struct rt_work *dhcp_work, void *dhcp_work_data)
{
#define WIZ_DHCP_WORK_RETRY 3 /* DHCP will have 3 times handshake */
#define WIZ_DHCP_WORK_RETRY_TIME (2 * RT_TICK_PER_SECOND)
static int wiz_dhcp_retry_times = WIZ_DHCP_WORK_RETRY * 20;
RT_ASSERT(dhcp_work_data != RT_NULL);
struct netdev *netdev = (struct netdev *)dhcp_work_data;
uint8_t dhcp_times = 0;
uint32_t dhcp_work_times;
static uint8_t data_buffer[1024];
static uint32_t dhcp_status = DHCP_FAILED;
if(dhcp_status == DHCP_FAILED)
{
DHCP_init(WIZ_DHCP_SOCKET, data_buffer);
rt_timer_start(dhcp_timer);
}
while (1)
{
/* DHCP start, return DHCP_IP_LEASED is success. */
dhcp_status = DHCP_run();
switch (dhcp_status)
{
case DHCP_IP_ASSIGN:
case DHCP_IP_CHANGED:
{
/* to update netdev information */
wiz_netdev_info_update(netdev, RT_FALSE);
break;
}
case DHCP_IP_LEASED:
{
int hour, min;
/* to update netdev information */
wiz_netdev_info_update(netdev, RT_FALSE);
/* reset the previous work configure */
rt_work_cancel(dhcp_work);
dhcp_work_times = (getDHCPTick1s() > getDHCPLeasetime() / 2) ?
0 : getDHCPLeasetime() / 2 - getDHCPTick1s();
/* according to the DHCP leaset time, config next DHCP produce */
rt_work_submit(dhcp_work, (dhcp_work_times+1) * RT_TICK_PER_SECOND);
hour = getDHCPLeasetime() / 3600;
min = (getDHCPLeasetime() % 3600) / 60;
LOG_D("DHCP countdown to lease renewal [%dH: %dMin], retry time[%04d]", hour, min, dhcp_times);
wiz_dhcp_retry_times = WIZ_DHCP_WORK_RETRY * 20;
return;
}
case DHCP_STOPPED:
dhcp_times = wiz_dhcp_retry_times;
break;
case DHCP_FAILED:
{
dhcp_times = wiz_dhcp_retry_times;
LOG_E("dhcp handshake failed!");
break;
}
default:
{
dhcp_times++;
/* DHCP_RUNNING status, include don't receive data */
rt_thread_mdelay(10);
break;
}
}
if (dhcp_times >= wiz_dhcp_retry_times)
{
LOG_D("DHCP work in %d seconds, [%03d|%03d]", WIZ_DHCP_WORK_RETRY_TIME / RT_TICK_PER_SECOND, dhcp_times, wiz_dhcp_retry_times);
/* if dhcp service is too busy to manger IP, increase retry times */
wiz_dhcp_retry_times = wiz_dhcp_retry_times + WIZ_DHCP_WORK_RETRY;
DHCP_stop();
dhcp_status = DHCP_FAILED;
rt_timer_stop(dhcp_timer);
rt_work_cancel(dhcp_work);
/* according to WIZ_DHCP_WORK_RETRY_TIME, reconfigure in 2 seconds */
rt_work_submit(dhcp_work, WIZ_DHCP_WORK_RETRY_TIME);
break;
}
}
}
static int wiz_network_dhcp(struct netdev *netdev)
{
if (netdev == RT_NULL)
return -RT_EINVAL;
/* set default MAC address for DHCP */
setSHAR(wiz_net_info.mac);
/* DHCP configure initialize, clear information other than MAC address */
setSn_RXBUF_SIZE(WIZ_DHCP_SOCKET, 0x02);
setSn_TXBUF_SIZE(WIZ_DHCP_SOCKET, 0x02);
/* register to assign IP address and conflict callback */
reg_dhcp_cbfunc(wiz_ip_assign, wiz_ip_assign, wiz_ip_conflict);
dhcp_timer = rt_timer_create("wiz_dhcp", wiz_dhcp_timer_entry, RT_NULL, 1 * RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
if (dhcp_timer == RT_NULL)
return -RT_ERROR;
dhcp_work = (struct rt_work *)rt_calloc(1, sizeof(struct rt_work));
if (dhcp_work == RT_NULL)
return -RT_ENOMEM;
rt_work_init(dhcp_work, wiz_dhcp_work, (void *)netdev);
rt_work_submit(dhcp_work, WIZ_DHCP_WORK_RETRY_TIME);
return RT_EOK;
}
#endif /* WIZ_USING_DHCP */
static void wiz_link_status_thread_entry(void *parameter)
{
#define WIZ_PHYCFGR_LINK_STATUS 0x01
uint8_t phycfgr = 0;
struct netdev *netdev = RT_NULL;
netdev = netdev_get_by_name(wiz_netdev_name);
if (netdev == RT_NULL)
{
LOG_E("don`t find device(%s)", wiz_netdev_name);
return;
}
while (1)
{
/* Get PHYCFGR data */
phycfgr = getPHYCFGR();
/* If the register contents are different from the struct contents, the struct needs to be updated */
if ((phycfgr & WIZ_PHYCFGR_LINK_STATUS) != ((netdev->flags & NETDEV_FLAG_LINK_UP) ? RT_TRUE : RT_FALSE))
{
if (phycfgr & WIZ_PHYCFGR_LINK_STATUS)
{
wiz_socket_init();
#ifdef WIZ_USING_DHCP
if(dhcp_work)
{
DHCP_stop();
rt_work_submit(dhcp_work, RT_WAITING_NO);
}
#else
wiz_network_init(RT_TRUE);
#endif
netdev_low_level_set_link_status(netdev, phycfgr & WIZ_PHYCFGR_LINK_STATUS);
wiz_netdev_info_update(netdev, RT_FALSE);
LOG_I("%s netdev link status becomes link up", wiz_netdev_name);
}
else
{
netdev_low_level_set_link_status(netdev, phycfgr & WIZ_PHYCFGR_LINK_STATUS);
if(dhcp_work)
{
rt_work_cancel(dhcp_work);
}
wiz_netdev_info_update(netdev, RT_TRUE);
LOG_I("%s netdev link status becomes link down", wiz_netdev_name);
}
}
rt_thread_mdelay(1000);
}
}
static int wiz_interrupt_init(rt_base_t isr_pin)
{
rt_thread_t tid;
/* initialize RX mailbox */
wiz_rx_mb = rt_mb_create("wiz_mb", WIZ_RX_MBOX_NUM, RT_IPC_FLAG_FIFO);
if (wiz_rx_mb == RT_NULL)
{
LOG_E("WIZnet create receive data mailbox error.");
return -RT_ENOMEM;
}
/* create WIZnet SPI RX thread */
tid = rt_thread_create("wiz", wiz_data_thread_entry, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX / 6, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
/* initialize interrupt pin */
rt_pin_mode(isr_pin, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(isr_pin, PIN_IRQ_MODE_FALLING, (void (*)(void*)) wiz_isr, RT_NULL);
rt_pin_irq_enable(isr_pin, PIN_IRQ_ENABLE);
return 0;
}
static int wiz_is_exist(void)
{
wiz_NetInfo ni;
int ret;
wiz_set_mac();
ctlnetwork(CN_SET_NETINFO, (void *)&wiz_net_info);
ctlnetwork(CN_GET_NETINFO, (void *)&ni);
ret = rt_memcmp(wiz_net_info.mac, ni.mac, sizeof(ni.mac));
return (ret == 0);
}
/* #include "stm32f4xx_hal.h" */
/* WIZnet initialize device and network */
int wiz_init(void)
{
int result = RT_EOK;
rt_thread_t tid;
if (wiz_init_ok == RT_TRUE)
{
LOG_I("RT-Thread WIZnet package is already initialized.");
return RT_EOK;
}
/* initialize reset pin */
rt_pin_mode(WIZ_RST_PIN, PIN_MODE_OUTPUT);
/* I think you can attach w5500 into spi bus at here. You can use this function to realize.*/
/* extern rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin); */
//rt_hw_spi_device_attach("spi1", "spi10", GPIOD, GPIO_PIN_2);//此处为添加的功能函数
//rt_spi_bus_attach_device(&wiz_device, "spi10", "spi1",(void *)NULL);
/* WIZnet SPI device and pin initialize */
result = wiz_device_init(WIZ_SPI_DEVICE);
if (result != RT_EOK)
{
goto __exit;
}
/* WIZnet SPI device reset */
wiz_reset();
/* set WIZnet device read/write data callback */
wiz_callback_register();
if (!wiz_is_exist())
{
result = -1;
LOG_E("Wiznet chip not detected");
goto __exit;
}
/* Add wiz to the netdev list */
ctlwizchip(CW_GET_ID, (void *)wiz_netdev_name);
wiz_netdev_add(wiz_netdev_name);
/* WIZnet chip configure initialize */
wiz_chip_cfg_init();
/* WIZnet socket initialize */
wiz_socket_init();
/* WIZnet network initialize */
result = wiz_network_init(RT_FALSE);
if (result != RT_EOK)
{
goto __exit;
}
dns_tick_timer = rt_timer_create("dns_tick", wiz_dns_time_handler, RT_NULL, 1 * RT_TICK_PER_SECOND, RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_PERIODIC);
rt_timer_start(dns_tick_timer);
/* create WIZnet link status Polling thread */
tid = rt_thread_create("wiz_stat", wiz_link_status_thread_entry, RT_NULL, 2048, RT_THREAD_PRIORITY_MAX - 4, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
wiz_interrupt_init(WIZ_IRQ_PIN);
__exit:
if (result == RT_EOK)
{
wiz_init_ok = RT_TRUE;
LOG_I("RT-Thread WIZnet package (V%s) initialize success.", WIZ_SW_VERSION);
}
else
{
LOG_E("RT-Thread WIZnet package (V%s) initialize failed(%d).", WIZ_SW_VERSION, result);
}
return result;
}
INIT_ENV_EXPORT(wiz_init);

110
Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz_af_inet.c Normal file
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@ -0,0 +1,110 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-26 chenyong first version
*/
#include <rtthread.h>
#include <rthw.h>
#include <netdb.h>
#include <sal.h>
#include <netdev.h>
#include <wiz.h>
#include <wiz_socket.h>
#ifdef SAL_USING_POSIX
#include <poll.h>
#endif
#ifdef SAL_USING_POSIX
static int wiz_poll(struct dfs_fd *file, struct rt_pollreq *req)
{
int mask = 0;
struct wiz_socket *sock;
struct sal_socket *sal_sock;
sal_sock = sal_get_socket((int) file->data);
if(!sal_sock)
{
return -1;
}
sock = wiz_get_socket((int)sal_sock->user_data);
if (sock != NULL)
{
rt_base_t level;
rt_poll_add(&sock->wait_head, req);
level = rt_hw_interrupt_disable();
if (sock->rcvevent)
{
mask |= POLLIN;
}
if (sock->sendevent)
{
mask |= POLLOUT;
}
if (sock->errevent)
{
mask |= POLLERR;
}
rt_hw_interrupt_enable(level);
}
return mask;
}
#endif
static const struct sal_socket_ops wiz_socket_ops =
{
wiz_socket,
wiz_closesocket,
wiz_bind,
wiz_listen,
wiz_connect,
wiz_accept,
wiz_sendto,
wiz_recvfrom,
wiz_getsockopt,
wiz_setsockopt,
wiz_shutdown,
NULL,
NULL,
NULL,
#ifdef SAL_USING_POSIX
wiz_poll,
#endif /* SAL_USING_POSIX */
};
static const struct sal_netdb_ops wiz_netdb_ops =
{
wiz_gethostbyname,
NULL,
wiz_getaddrinfo,
wiz_freeaddrinfo,
};
static const struct sal_proto_family wiz_inet_family =
{
AF_WIZ,
AF_INET,
&wiz_socket_ops,
&wiz_netdb_ops,
};
/* Set wiz network interface device protocol family information */
int sal_wiz_netdev_set_pf_info(struct netdev *netdev)
{
RT_ASSERT(netdev);
netdev->sal_user_data = (void *) &wiz_inet_family;
return 0;
}

83
Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz_device.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-26 chenyong first version
*/
#include <stdlib.h>
#include <wiz.h>
#include <wiz_socket.h>
#include <W5500/w5500.h>
#define DBG_ENABLE
#define DBG_SECTION_NAME "wiz.dev"
#ifdef WIZ_DEBUG
#define DBG_LEVEL DBG_LOG
#else
#define DBG_LEVEL DBG_INFO
#endif /* WIZ_DEBUG */
#define DBG_COLOR
#include <rtdbg.h>
struct rt_spi_device *wiz_device = RT_NULL;
#ifndef WIZ_SPI_FREQ_MAX
#define WIZ_SPI_FREQ_MAX 10000000
#endif
static int wiz_spi_init(const char *spi_dev_name)
{
RT_ASSERT(spi_dev_name);
if (wiz_device != RT_NULL)
{
return 0;
}
wiz_device = (struct rt_spi_device *) rt_device_find(spi_dev_name);
if (wiz_device == RT_NULL)
{
LOG_E("You should attach [%s] into SPI bus firstly.", spi_dev_name);
return -RT_ENOSYS;
}
/* check SPI device type */
RT_ASSERT(wiz_device->parent.type == RT_Device_Class_SPIDevice);
/* configure SPI device*/
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */
cfg.max_hz = WIZ_SPI_FREQ_MAX; /* SPI Interface with Clock Speeds Up to 40 MHz */
rt_spi_configure(wiz_device, &cfg);
}
if (rt_device_open((rt_device_t) wiz_device, RT_DEVICE_OFLAG_RDWR) != RT_EOK)
{
LOG_E("open WIZnet SPI device %s error.", spi_dev_name);
return -RT_ERROR;
}
return RT_EOK;
}
int wiz_device_init(const char *spi_dev_name)
{
int result = RT_EOK;
/* WIZnet SPI device initialize */
result = wiz_spi_init(spi_dev_name);
if (result != RT_EOK)
{
LOG_E("WIZnet SPI device initialize failed.");
return result;
}
return RT_EOK;
}

259
Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz_ping.c Normal file
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@ -0,0 +1,259 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-26 chenyong first version
*/
#include <stdlib.h>
#include <rtthread.h>
#include <sys/time.h>
#include <wiz_socket.h>
#include <W5500/w5500.h>
#include <sal.h>
#include <netdev.h>
#define Sn_PROTO(ch) (0x001408 + (ch<<5))
#define WIZ_PING_DATA_LEN 32
#define WIZ_PING_HEAD_LEN 8
#define WIZ_PING_PORT 3000
#define WIZ_PING_REQUEST 8
#define WIZ_PING_REPLY 0
#define WIZ_PING_CODE 0
#define WIZ_PING_DELAY (1 * RT_TICK_PER_SECOND)
#define WIZ_PING_TIMEOUT (2 * RT_TICK_PER_SECOND)
struct wiz_ping_msg
{
uint8_t type; // 0 - Ping Reply, 8 - Ping Request
uint8_t code; // Always 0
uint16_t check_sum; // Check sum
uint16_t id; // Identification
uint16_t seq_num; // Sequence Number
int8_t data[WIZ_PING_DATA_LEN]; // Ping Data : 1452 = IP RAW MTU - sizeof(type+code+check_sum+id+seq_num)
};
/* calculate string check value */
static uint16_t wiz_checksum( uint8_t *src, uint32_t len )
{
uint16_t sum, tsum, i, j;
uint32_t lsum;
j = len >> 1;
lsum = 0;
for (i = 0; i < j; i++)
{
tsum = src[i * 2];
tsum = tsum << 8;
tsum += src[i * 2 + 1];
lsum += tsum;
}
if (len % 2)
{
tsum = src[i * 2];
lsum += (tsum << 8);
}
sum = lsum;
sum = ~(sum + (lsum >> 16));
return (uint16_t) sum;
}
static int wiz_ping_request(int socket)
{
int idx, send_len;
uint16_t tmp_checksum;
struct wiz_ping_msg ping_req;
/* set request ping message object */
ping_req.type = WIZ_PING_REQUEST;
ping_req.code = WIZ_PING_CODE;
ping_req.id = htons(rand() % 0xffff);
ping_req.seq_num = htons(rand() % 0xffff);
for (idx = 0; idx < WIZ_PING_DATA_LEN; idx++)
{
ping_req.data[idx] = (idx) % 8;
}
ping_req.check_sum = 0;
/* calculate request ping message check value */
tmp_checksum = wiz_checksum((uint8_t *) &ping_req, sizeof(ping_req));
ping_req.check_sum = htons(tmp_checksum);
/* send request ping message */
send_len = wiz_send(socket, &ping_req, sizeof(ping_req), 0);
if (send_len != sizeof(ping_req))
{
return -1;
}
return send_len - WIZ_PING_HEAD_LEN;
}
static int wiz_ping_reply(int socket, struct sockaddr *from)
{
uint16_t tmp_checksum;
uint8_t recv_buf[WIZ_PING_HEAD_LEN + WIZ_PING_DATA_LEN + 1];
struct wiz_ping_msg ping_rep;
rt_tick_t start_tick;
int recv_len;
int idx;
start_tick = rt_tick_get();
while(1)
{
if (rt_tick_get() - start_tick > WIZ_PING_TIMEOUT)
{
return -1;
}
if (getSn_RX_RSR(socket) <= 0)
{
rt_thread_mdelay(1);
continue;
}
else
{
struct sockaddr *sin = (struct sockaddr *)from;
socklen_t addr_len = sizeof(struct sockaddr_in);
recv_len = wiz_recvfrom(socket, recv_buf, WIZ_PING_HEAD_LEN + WIZ_PING_DATA_LEN, 0, sin, &addr_len);
if (recv_len < 0)
{
return -1;
}
break;
}
}
if (recv_buf[0] == WIZ_PING_REPLY)
{
ping_rep.type = recv_buf[0];
ping_rep.code = recv_buf[1];
ping_rep.check_sum = (recv_buf[3] << 8) + recv_buf[2];
ping_rep.id = (recv_buf[5] << 8) + recv_buf[4];
ping_rep.seq_num = (recv_buf[7] << 8) + recv_buf[6];
for (idx = 0; idx < recv_len - 8; idx++)
{
ping_rep.data[idx] = recv_buf[8 + idx];
}
tmp_checksum = ~wiz_checksum(recv_buf, recv_len);
if (tmp_checksum != 0xffff)
{
return -2;
}
}
else if (recv_buf[0] == WIZ_PING_REQUEST)
{
ping_rep.code = recv_buf[1];
ping_rep.type = recv_buf[2];
ping_rep.check_sum = (recv_buf[3] << 8) + recv_buf[2];
ping_rep.id = (recv_buf[5] << 8) + recv_buf[4];
ping_rep.seq_num = (recv_buf[7] << 8) + recv_buf[6];
for (idx = 0; idx < recv_len - 8; idx++)
{
ping_rep.data[idx] = recv_buf[8 + idx];
}
tmp_checksum = ping_rep.check_sum;
ping_rep.check_sum = 0;
if (tmp_checksum != ping_rep.check_sum)
{
return -2;
}
}
else
{
rt_kprintf("wiz_ping: unknown ping receive message.\n");
return -1;
}
return recv_len - WIZ_PING_HEAD_LEN;
}
int wiz_ping(struct netdev *netdev, const char *host, size_t data_len, uint32_t times, struct netdev_ping_resp *ping_resp)
{
int result = RT_EOK, socket;
struct sockaddr_in server_addr;
struct timeval timeout;
struct in_addr ina;
struct hostent *hostent;
rt_tick_t recv_start_tick;
struct sal_proto_family *pf = (struct sal_proto_family *) netdev->sal_user_data;
/* get network interface socket operations */
if (pf == RT_NULL || pf->skt_ops == RT_NULL)
{
rt_kprintf("wiz_ping: pf or pf->skt_ops is RT_NULL.\n");
return -RT_FALSE;
}
hostent = (struct hostent *) pf->netdb_ops->gethostbyname(host);
if (hostent == RT_NULL)
{
rt_kprintf("wiz_ping: hostent is RT_NULL.\n");
return -RT_FALSE;
}
socket = -1;
socket = wiz_socket(AF_WIZ, SOCK_RAW, 0);
if (socket < 0)
{
rt_kprintf("wiz_ping: create ping socket(%d) failed.\n",socket);
return -1;
}
/* set socket ICMP protocol */
IINCHIP_WRITE(Sn_PROTO(socket), IPPROTO_ICMP);
/* Check socket register */
while(getSn_SR(socket) != SOCK_IPRAW);
timeout.tv_sec = times / RT_TICK_PER_SECOND;
timeout.tv_usec = (times % RT_TICK_PER_SECOND) * 1000 / RT_TICK_PER_SECOND;
/* set receive and send timeout option */
wiz_setsockopt(socket, SOL_SOCKET, SO_RCVTIMEO, (void *) &timeout,
sizeof(timeout));
wiz_setsockopt(socket, SOL_SOCKET, SO_SNDTIMEO, (void *) &timeout,
sizeof(timeout));
server_addr.sin_family = AF_WIZ;
server_addr.sin_port = htons(WIZ_PING_PORT);
server_addr.sin_addr = *((struct in_addr *)hostent->h_addr);
rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
rt_memcpy(&ina, &server_addr.sin_addr, sizeof(ina));
if (wiz_connect(socket, (struct sockaddr *) &server_addr, sizeof(struct sockaddr)) < 0)
{
wiz_closesocket(socket);
return -1;
}
if ((result = wiz_ping_request(socket)) > 0)
{
recv_start_tick = rt_tick_get();
result = wiz_ping_reply(socket, (struct sockaddr *) &server_addr);
}
if(result > 0)
{
ping_resp->ip_addr.addr = ((struct in_addr *)hostent->h_addr)->s_addr;
ping_resp->ticks = rt_tick_get() - recv_start_tick;
ping_resp->data_len = data_len;
ping_resp->ttl = getSn_TTL(socket);
}
wiz_closesocket(socket);
return result;
}

1739
Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz_socket.c Normal file
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File diff suppressed because it is too large Load Diff

11
Ubiquitous/XiZi/Makefile
View File

@ -5,8 +5,10 @@ MAKEFLAGS += --no-print-directory
.PHONY:COMPILE_APP COMPILE_KERNEL
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103-rvstar cortex-m0-emulator rv32m1-vega nuvoton-m2354
support += xidatong-arm32 xidatong-riscv64 xiwangtong-arm32
riscv_support := kd233 maix-go hifive1-rev-B gapuino gd32vf103-rvstar rv32m1-vega aiit-riscv64-board xidatong-riscv64
arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32
emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator
support := $(riscv_support) $(arm_support) $(emulator_support)
SRC_DIR :=
export BOARD ?=kd233
@ -16,7 +18,10 @@ export KCONFIG_CONFIG ?= .config
ifeq ($(filter $(BOARD),$(support)),)
$(warning "You should choose board like this:make BOARD=kd233")
$(warning "This is what we support:")
$(warning "$(support)")
$(warning "RISCV EVB: $(riscv_support)")
$(warning "ARM EVB: $(arm_support)")
$(warning "EMULATORS: $(emulator_support)")
# $(warning "$(support)")
$(error "break" )
endif

5
Ubiquitous/XiZi/arch/arm/Makefile
View File

@ -30,6 +30,11 @@ SRC_DIR := shared
SRC_DIR += cortex-m7
endif
ifeq ($(CONFIG_BOARD_IMXRT1176_SBC_EVB),y)
SRC_DIR := shared
SRC_DIR += cortex-m7
endif
# cortex-m0 is ARMv6-m
ifeq ($(CONFIG_BOARD_CORTEX_M0_EVB),y)

28
Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Makefile
View File

@ -1,13 +1,5 @@
SRC_FILES := sleep.c
ifeq ($(CONFIG_BSP_USING_AUDIO),y)
SRC_DIR += audio
endif
ifeq ($(CONFIG_BSP_USING_CAMERA),y)
SRC_DIR += camera
endif
ifeq ($(CONFIG_BSP_USING_CH376),y)
SRC_DIR += ch376
endif
@ -32,14 +24,6 @@ ifeq ($(CONFIG_BSP_USING_I2C),y)
SRC_DIR += i2c
endif
ifeq ($(CONFIG_BSP_USING_I2S),y)
SRC_DIR += i2s
endif
ifeq ($(CONFIG_BSP_USING_KPU),y)
SRC_DIR += kpu
endif
ifeq ($(CONFIG_BSP_USING_LCD),y)
SRC_DIR += lcd
endif
@ -48,18 +32,10 @@ ifeq ($(CONFIG_BSP_USING_PLIC),y)
SRC_DIR += plic
endif
ifeq ($(CONFIG_BSP_USING_PWM),y)
SRC_DIR += pwm
endif
ifeq ($(CONFIG_BSP_USING_RTC),y)
SRC_DIR += rtc
endif
ifeq ($(CONFIG_BSP_USING_SECURITY),y)
SRC_DIR += security
endif
ifeq ($(CONFIG_BSP_USING_SPI),y)
SRC_DIR += spi
endif
@ -80,10 +56,6 @@ ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += uart
endif
ifeq ($(CONFIG_BSP_USING_VIDEO),y)
SRC_DIR += video
endif
ifeq ($(CONFIG_BSP_USING_WDT),y)
SRC_DIR += watchdog
endif

58
Ubiquitous/XiZi/board/imxrt1176-sbc/Kconfig Normal file
View File

@ -0,0 +1,58 @@
mainmenu "XiZi Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_IMXRT1176_SBC_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "imxrt1176-sbc feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_imxrt1176_sbc_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x2007F0000
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
menu "config board peripheral"
config MOUNT_SDCARD
bool "mount cd card"
default n
endmenu
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

5
Ubiquitous/XiZi/board/imxrt1176-sbc/Makefile Normal file
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@ -0,0 +1,5 @@
SRC_DIR := third_party_driver xip
SRC_FILES := board.c
include $(KERNEL_ROOT)/compiler.mk

172
Ubiquitous/XiZi/board/imxrt1176-sbc/README.md Normal file
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@ -0,0 +1,172 @@
# 从零开始构建矽璓工业物联操作系统：使用ARM架构的imxrt1176-sbc
# imxrt1176-sbc
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
## 1. 简介
| 硬件 | 描述 |
| -- | -- |
|芯片型号| MIMXRT1176 |
|架构| cortex-m7 + cortex-m4 |
|主频| M7@1GHz m4@400MHz |
|片内SRAM| M7:512KB / M4:256KB shared with TCM |
|外设支持| UART GPIO I2C RTC SDIO SEMC SPI USB ADC|
XiUOS板级当前支持使用UART。
## 2. 开发环境搭建
### 推荐使用：
**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
第一步:打开sources.list文件
```c
sudo vim /etc/apt/sources.list
```
第二步:将以下内容复制到sources.list文件
```c
deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
```
第三步:更新源和系统软件
```c
sudo apt-get update
sudo apt-get upgrade
```
**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
### 依赖包安装：
```
$ sudo apt install build-essential pkg-config git
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
```
**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
```c
mkdir test && cd test
git clone https://gitlink.org.cn/xuos/xiuos.git
```
1、打开XiUOS源码文件包可以看到以下目录：
| 名称 | 说明 |
| -- | -- |
| APP_Framework | 应用代码 |
| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
2、打开XiZi内核源码文件包可以看到以下目录：
| 名称 | 说明 |
| -- | -- |
| arch | 架构代码 |
| board | 板级支持包 |
| fs | 文件系统 |
| kernel | 内核源码 |
| lib | 第三方库源码 |
| resources | 驱动文件 |
| tool | 系统工具 |
使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
<div align= "center">
<img src = ./img/vscode.jpg width =1000>
</div>
### 裁减配置工具的下载
裁减配置工具：
**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：
```c
mkdir kfrontends && cd kfrontends
git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
```
下载源码后按以下步骤执行软件安装：
```c
cd kconfig-frontends
./xs_build.sh
```
### 编译工具链：
ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
```shell
$ sudo apt install gcc-arm-none-eabi
```
## 编译说明
### 编辑环境：`Ubuntu18.04`
### 编译工具链：`arm-none-eabi-gcc`
使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
编译步骤：
1.在VScode命令终端中执行以下命令，生成配置文件
```c
cd ./Ubiquitous/XiZi
make BOARD=imxrt1176-sbc distclean
make BOARD=imxrt1176-sbc menuconfig
```
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
![menuconfig](./img/menuconfig.png)
退出时选择`yes`保存上面所配置的内容，如下图所示：
![menuconfig1](./img/menuconfig1.png)
3.继续执行以下命令，进行编译
```
make BOARD=imxrt1176-sbc
```
4.如果编译正确无误，会产生XiZi-imxrt1176-sbc.elf、XiZi-imxrt1176-sbc.bin文件。
## 3. 烧写及运行
### 3.1 烧写
1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility)
2、imxrt1176-sbc开发板支持串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT117x，开发板上电，使用usb线将开发板和PC连接，使用串口调试小板连接开发板调试串口的发送和接收管脚，启动管脚连接“serial download”，并按下复位管脚使得MCU进入下载模式。如下图所示：
![download](./img/download.png)
3、同时需要匹配imxrt1176-sbc开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择ISSI_IS26KSxxxS_IS26KLxxxS，然后点击ok。点击connect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。选择编译生成的XiZi-imxrt1176-sbc.elf,点击ALL-In-One-Action按钮烧写，等待烧写完成
如下图所示：
![NXPBootUtility_1](./img/NXPBootUtility_1.png)
### 3.2 运行结果
1、烧写完成后，启动管脚连接“Interal Boot”，按下复位键后，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示：
![terminal](./img/terminal.png)

420
Ubiquitous/XiZi/board/imxrt1176-sbc/board.c Normal file
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@ -0,0 +1,420 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file board.c
* @brief relative configure for xidatong-arm32
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022.03.15
*/
/*************************************************
File name: board.c
Description: support imxrt1176-board init function
Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
History:
1. Date: 2022-08-19
Author: AIIT XUOS Lab
Modification:
1. support imxrt1176-board MPU、clock、memory init
2. support imxrt1176-board uart、sdio driver init
*************************************************/
#include <board.h>
#ifdef BSP_USING_GPIO
#include <connect_gpio.h>
#endif
#ifdef BSP_USING_LPUART
#include <connect_uart.h>
#endif
#if __CORTEX_M == 7
void BOARD_ConfigMPU(void)
{
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
0 :
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
#if defined(__USE_SHMEM)
extern uint32_t __base_rpmsg_sh_mem;
extern uint32_t __top_rpmsg_sh_mem;
uint32_t nonCacheStart = (uint32_t)(&__base_rpmsg_sh_mem);
uint32_t size = (uint32_t)(&__top_rpmsg_sh_mem) - nonCacheStart;
#else
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
#endif
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START;
extern uint32_t __NCACHE_REGION_END;
uint32_t nonCacheStart = (uint32_t)(&__NCACHE_REGION_START);
uint32_t size = (uint32_t)(&__NCACHE_REGION_END) - nonCacheStart;
#endif
volatile uint32_t i = 0;
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
SCB_DisableICache();
}
#endif
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
{
SCB_DisableDCache();
}
#endif
/* Disable MPU */
ARM_MPU_Disable();
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/
/*
* Add default region to deny access to whole address space to workaround speculative prefetch.
* Refer to Arm errata 1013783-B for more details.
*
*/
/* Region 0 setting: Instruction access disabled, No data access permission. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
#endif
#ifdef USE_SDRAM
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
#endif
while ((size >> i) > 0x1U)
{
i++;
}
if (i != 0)
{
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t)(1 << i));
assert(i >= 5);
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}
/* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
/* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
/* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
SCB_EnableDCache();
#endif
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
SCB_EnableICache();
#endif
}
#elif __CORTEX_M == 4
void BOARD_ConfigMPU(void)
{
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
0 :
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
#endif
#if defined(__USE_SHMEM)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
/* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
#elif defined(__MCUXPRESSO)
extern uint32_t __base_rpmsg_sh_mem;
extern uint32_t __top_rpmsg_sh_mem;
uint32_t rpmsgShmemStart = (uint32_t)(&__base_rpmsg_sh_mem);
uint32_t rpmsgShmemSize = (uint32_t)(&__top_rpmsg_sh_mem) - rpmsgShmemStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __RPMSG_SH_MEM_START[];
extern uint32_t __RPMSG_SH_MEM_SIZE[];
uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
#endif
#endif
uint32_t i = 0;
/* Only config non-cacheable region on system bus */
assert(nonCacheStart >= 0x20000000);
/* Disable code bus cache */
if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR))
{
/* Enable the processor code bus to push all modified lines. */
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
/* Now disable the cache. */
LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
}
/* Disable system bus cache */
if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR))
{
/* Enable the processor system bus to push all modified lines. */
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
/* Now disable the cache. */
LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
}
/* Disable MPU */
ARM_MPU_Disable();
while ((nonCacheSize >> i) > 0x1U)
{
i++;
}
if (i != 0)
{
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % nonCacheSize));
assert(nonCacheSize == (uint32_t)(1 << i));
assert(i >= 5);
/* Region 0 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#if defined(__USE_SHMEM)
i = 0;
while ((rpmsgShmemSize >> i) > 0x1U)
{
i++;
}
if (i != 0)
{
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(rpmsgShmemStart % rpmsgShmemSize));
assert(rpmsgShmemSize == (uint32_t)(1 << i));
assert(i >= 5);
/* Region 1 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#endif
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enables the processor system bus to invalidate all lines in both ways.
and Initiate the processor system bus cache command. */
LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the cache command completes */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
/* Now enable the system bus cache. */
LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
/* Enables the processor code bus to invalidate all lines in both ways.
and Initiate the processor code bus code cache command. */
LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
/* Now enable the code bus cache. */
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
}
#endif
/* This is the timer interrupt service routine. */
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
struct InitSequenceDesc _board_init[] =
{
#ifdef BSP_USING_GPIO
// { "hw_pin", Imxrt1052HwGpioInit },
#endif
{ " NONE ",NONE },
};
/**
* This function will initial imxrt1050 board.
*/
void InitBoardHardware()
{
int i = 0;
int ret = 0;
BOARD_ConfigMPU();
BOARD_InitPins();
BOARD_BootClockRUN();
// NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
#ifdef BSP_USING_LPUART
Imxrt1176HwUartInit();
#endif
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
for(i = 0; _board_init[i].fn != NONE; i++) {
ret = _board_init[i].fn();
KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed");
}
KPrintf("board init done.\n");
KPrintf("start kernel...\n");
}

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export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
export CFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
export AFLAGS := -c -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-imxrt1176-sbc.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g
# export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export DEFINES := -DHAVE_CCONFIG_H -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS
export ARCH = arm
export MCU = cortex-m7

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/**
* @file board.h
* @brief define imxrt1176-sbc-board init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: board.h
Description: define imxrt1176-sbc board init function and struct
Others:
History:
1. Date: 2022-08-19
Author: AIIT XUOS Lab
Modification:
1. define imxrt-board InitBoardHardware
2. define imxrt-board heap struct
*************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "fsl_common.h"
#include "fsl_gpio.h"
#include "fsl_clock.h"
// #include "fsl_enet.h"
#include "clock_config.h"
#include <xizi.h>
#include <arch_interrupt.h>
extern int heap_start;
extern int heap_end;
#define HEAP_BEGIN (&heap_start)
#define HEAP_END (&heap_end)
#define BOARD_FLASH_SIZE (0x1000000U)
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
void InitBoardHardware(void);
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "IMXRT1050"
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/
/*! @brief The ENET PHY address. */
#define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
void BOARD_ConfigMPU(void);
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */

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/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file clock_config.c
* @brief support imxrt1176-sbc clock configure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-08-19
*/
/*************************************************
File name: clock_config.c
Description: support imxrt1176-sbc clock configure
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
History:
1. Date: 2022-08-19
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#if __CORTEX_M == 7
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
#else
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
#endif
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/**
* @file dcd.h
* @brief support imxrt1176-sbc dcd
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-08-19
*/
/*************************************************
File name: dcd.h
Description: support imxrt1176-sbc dcd
Others: take SDK_2_11_1_MIMXRT1170-EVK for references
History:
1. Date: 2022-08-19
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef __DCD__
#define __DCD__
#include <stdint.h>
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.1. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_ARRAY_SIZE 1
#endif /* __DCD__ */

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Ubiquitous/XiZi/board/imxrt1176-sbc/link.lds Normal file
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/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/**
* @file link.lds
* @brief ok1052-c board Linker script
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: link.lds
Description: ok1052-c board Linker script
Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. add shell cmd table and g_service_table
*************************************************/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
/* Specify the memory areas */
MEMORY
{
/* define flash 32MB */
m_boot_data (RX) : ORIGIN = 0x30000000, LENGTH = 0x00001000
m_image_vertor_table (RX) : ORIGIN = 0x30001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x30002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x30002400, LENGTH = 0x01FFDC00
/* define itcm 256KB */
sram_itcm_cm7 (rwx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias RAM2) */
/* define dtcm 256KB */
sram_dtcm_cm7 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 /* 256K bytes (alias RAM) */
/* define ocram1 512KB */
sram_oc1 (rwx) : ORIGIN = 0x20240000, LENGTH = 0x80000 /* 512K bytes (alias RAM3) */
/* define ocram2 256KB */
sram_oc2 (rwx) : ORIGIN = 0x202c0000, LENGTH = 0x40000 /* 256K bytes (alias RAM4) */
/* define nocache regin 256KB */
NCACHE_REGION (rwx) : ORIGIN = 0x20300000, LENGTH = 0x40000 /* 256K bytes (alias RAM5) */
/* define ocram ecc1 and ecc2 64KB */
sram_oc_ecc1 (rwx) : ORIGIN = 0x20340000, LENGTH = 0x10000 /* 64K bytes (alias RAM6) */
sram_oc_ecc2 (rwx) : ORIGIN = 0x20350000, LENGTH = 0x10000 /* 64K bytes (alias RAM7) */
/* define extern sdram 32MB*/
board_sdram (rwx) : ORIGIN = 0x80000000, LENGTH = 0x2000000 /* 64M bytes (alias RAM8) */
}
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.boot_hdr.conf))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
__VECTOR_RAM = __VECTOR_TABLE;
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
/* section information for shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP (*(shellCommand))
_shell_command_end = .;
. = ALIGN(4);
__isrtbl_idx_start = .;
KEEP(*(.isrtbl.idx))
__isrtbl_start = .;
KEEP(*(.isrtbl))
__isrtbl_end = .;
. = ALIGN(4);
PROVIDE(g_service_table_start = ABSOLUTE(.));
KEEP(*(.g_service_table))
PROVIDE(g_service_table_end = ABSOLUTE(.));
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > sram_dtcm_cm7
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
__NCACHE_REGION_START = .;
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > sram_dtcm_cm7
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
__NCACHE_REGION_END = .;
} > sram_dtcm_cm7
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > sram_dtcm_cm7
.stack :
{
. = ALIGN(8);
stack_start = .;
. += STACK_SIZE;
stack_end = .;
__StackTop = .;
heap_start = .;
} > sram_oc1
PROVIDE(heap_end = ORIGIN(sram_oc1) + LENGTH(sram_oc2) + LENGTH(NCACHE_REGION));
.ARM.attributes 0 : { *(.ARM.attributes) }
}

894
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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