forked from xuos/xiuos
Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into wgz
This commit is contained in:
wgzAIIT
commit
ad9b7492ae
|
|
@ -0,0 +1,339 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# RT-Thread Configuration
|
||||
#
|
||||
CONFIG_ROOT_DIR="../../../.."
|
||||
CONFIG_BSP_DIR="."
|
||||
CONFIG_RT_Thread_DIR="../.."
|
||||
CONFIG_RTT_DIR="../../rt-thread"
|
||||
|
||||
#
|
||||
# RT-Thread Kernel
|
||||
#
|
||||
CONFIG_RT_NAME_MAX=8
|
||||
# CONFIG_RT_USING_BIG_ENDIAN is not set
|
||||
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
|
||||
# CONFIG_RT_USING_SMP is not set
|
||||
CONFIG_RT_ALIGN_SIZE=4
|
||||
# CONFIG_RT_THREAD_PRIORITY_8 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_32=y
|
||||
# CONFIG_RT_THREAD_PRIORITY_256 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_MAX=32
|
||||
CONFIG_RT_TICK_PER_SECOND=100
|
||||
CONFIG_RT_USING_OVERFLOW_CHECK=y
|
||||
CONFIG_RT_USING_HOOK=y
|
||||
CONFIG_RT_USING_IDLE_HOOK=y
|
||||
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_THREAD_STACK_SIZE=256
|
||||
# CONFIG_RT_USING_TIMER_SOFT is not set
|
||||
|
||||
#
|
||||
# kservice optimization
|
||||
#
|
||||
CONFIG_RT_KSERVICE_USING_STDLIB=y
|
||||
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
|
||||
# CONFIG_RT_USING_ASM_MEMCPY is not set
|
||||
CONFIG_RT_DEBUG=y
|
||||
CONFIG_RT_DEBUG_COLOR=y
|
||||
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
|
||||
|
||||
#
|
||||
# Inter-Thread communication
|
||||
#
|
||||
CONFIG_RT_USING_SEMAPHORE=y
|
||||
CONFIG_RT_USING_MUTEX=y
|
||||
CONFIG_RT_USING_EVENT=y
|
||||
CONFIG_RT_USING_MAILBOX=y
|
||||
CONFIG_RT_USING_MESSAGEQUEUE=y
|
||||
# CONFIG_RT_USING_SIGNALS is not set
|
||||
|
||||
#
|
||||
# Memory Management
|
||||
#
|
||||
CONFIG_RT_USING_MEMPOOL=y
|
||||
CONFIG_RT_USING_MEMHEAP=y
|
||||
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
|
||||
# CONFIG_RT_USING_NOHEAP is not set
|
||||
# CONFIG_RT_USING_SMALL_MEM is not set
|
||||
# CONFIG_RT_USING_SLAB is not set
|
||||
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
|
||||
# CONFIG_RT_USING_USERHEAP is not set
|
||||
# CONFIG_RT_USING_MEMTRACE is not set
|
||||
CONFIG_RT_USING_HEAP=y
|
||||
|
||||
#
|
||||
# Kernel Device Object
|
||||
#
|
||||
CONFIG_RT_USING_DEVICE=y
|
||||
# CONFIG_RT_USING_DEVICE_OPS is not set
|
||||
# CONFIG_RT_USING_INTERRUPT_INFO is not set
|
||||
CONFIG_RT_USING_CONSOLE=y
|
||||
CONFIG_RT_CONSOLEBUF_SIZE=128
|
||||
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
|
||||
# CONFIG_RT_PRINTF_LONGLONG is not set
|
||||
CONFIG_RT_VER_NUM=0x40004
|
||||
# CONFIG_RT_USING_CPU_FFS is not set
|
||||
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
|
||||
|
||||
#
|
||||
# RT-Thread Components
|
||||
#
|
||||
CONFIG_RT_USING_COMPONENTS_INIT=y
|
||||
CONFIG_RT_USING_USER_MAIN=y
|
||||
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
|
||||
CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
|
||||
#
|
||||
# C++ features
|
||||
#
|
||||
# CONFIG_RT_USING_CPLUSPLUS is not set
|
||||
|
||||
#
|
||||
# Command shell
|
||||
#
|
||||
CONFIG_RT_USING_FINSH=y
|
||||
CONFIG_RT_USING_MSH=y
|
||||
CONFIG_FINSH_USING_MSH=y
|
||||
CONFIG_FINSH_THREAD_NAME="tshell"
|
||||
CONFIG_FINSH_THREAD_PRIORITY=20
|
||||
CONFIG_FINSH_THREAD_STACK_SIZE=4096
|
||||
CONFIG_FINSH_USING_HISTORY=y
|
||||
CONFIG_FINSH_HISTORY_LINES=5
|
||||
CONFIG_FINSH_USING_SYMTAB=y
|
||||
CONFIG_FINSH_CMD_SIZE=80
|
||||
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
|
||||
CONFIG_FINSH_USING_DESCRIPTION=y
|
||||
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||
# CONFIG_FINSH_USING_AUTH is not set
|
||||
CONFIG_FINSH_ARG_MAX=10
|
||||
|
||||
#
|
||||
# Device virtual file system
|
||||
#
|
||||
CONFIG_RT_USING_DFS=y
|
||||
CONFIG_DFS_USING_WORKDIR=y
|
||||
CONFIG_DFS_FILESYSTEMS_MAX=4
|
||||
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
|
||||
CONFIG_DFS_FD_MAX=16
|
||||
# CONFIG_RT_USING_DFS_MNTTABLE is not set
|
||||
# CONFIG_RT_USING_DFS_ELMFAT is not set
|
||||
CONFIG_RT_USING_DFS_DEVFS=y
|
||||
# CONFIG_RT_USING_DFS_ROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_RAMFS is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
CONFIG_RT_USING_DEVICE_IPC=y
|
||||
CONFIG_RT_PIPE_BUFSZ=512
|
||||
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
|
||||
CONFIG_RT_USING_SERIAL=y
|
||||
CONFIG_RT_USING_SERIAL_V1=y
|
||||
# CONFIG_RT_USING_SERIAL_V2 is not set
|
||||
CONFIG_RT_SERIAL_USING_DMA=y
|
||||
CONFIG_RT_SERIAL_RB_BUFSZ=64
|
||||
# CONFIG_RT_USING_CAN is not set
|
||||
# CONFIG_RT_USING_HWTIMER is not set
|
||||
CONFIG_RT_USING_CPUTIME=y
|
||||
# CONFIG_RT_USING_I2C is not set
|
||||
# CONFIG_RT_USING_PHY is not set
|
||||
CONFIG_RT_USING_PIN=y
|
||||
# CONFIG_RT_USING_ADC is not set
|
||||
# CONFIG_RT_USING_DAC is not set
|
||||
# CONFIG_RT_USING_PWM is not set
|
||||
# CONFIG_RT_USING_MTD_NOR is not set
|
||||
# CONFIG_RT_USING_MTD_NAND is not set
|
||||
# CONFIG_RT_USING_PM is not set
|
||||
# CONFIG_RT_USING_RTC is not set
|
||||
# CONFIG_RT_USING_SDIO is not set
|
||||
# CONFIG_RT_USING_SPI is not set
|
||||
# CONFIG_RT_USING_WDT is not set
|
||||
# CONFIG_RT_USING_AUDIO is not set
|
||||
# CONFIG_RT_USING_SENSOR is not set
|
||||
# CONFIG_RT_USING_TOUCH is not set
|
||||
# CONFIG_RT_USING_HWCRYPTO is not set
|
||||
# CONFIG_RT_USING_PULSE_ENCODER is not set
|
||||
# CONFIG_RT_USING_INPUT_CAPTURE is not set
|
||||
# CONFIG_RT_USING_WIFI is not set
|
||||
|
||||
#
|
||||
# Using USB
|
||||
#
|
||||
# CONFIG_RT_USING_USB_HOST is not set
|
||||
# CONFIG_RT_USING_USB_DEVICE is not set
|
||||
|
||||
#
|
||||
# POSIX layer and C standard library
|
||||
#
|
||||
CONFIG_RT_USING_LIBC=y
|
||||
CONFIG_RT_USING_PTHREADS=y
|
||||
CONFIG_PTHREAD_NUM_MAX=8
|
||||
CONFIG_RT_USING_POSIX=y
|
||||
# CONFIG_RT_USING_POSIX_MMAP is not set
|
||||
# CONFIG_RT_USING_POSIX_TERMIOS is not set
|
||||
# CONFIG_RT_USING_POSIX_GETLINE is not set
|
||||
# CONFIG_RT_USING_POSIX_AIO is not set
|
||||
CONFIG_RT_LIBC_USING_TIME=y
|
||||
# CONFIG_RT_USING_MODULE is not set
|
||||
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||
|
||||
#
|
||||
# Network
|
||||
#
|
||||
|
||||
#
|
||||
# Socket abstraction layer
|
||||
#
|
||||
# CONFIG_RT_USING_SAL is not set
|
||||
|
||||
#
|
||||
# Network interface device
|
||||
#
|
||||
# CONFIG_RT_USING_NETDEV is not set
|
||||
|
||||
#
|
||||
# light weight TCP/IP stack
|
||||
#
|
||||
# CONFIG_RT_USING_LWIP is not set
|
||||
|
||||
#
|
||||
# AT commands
|
||||
#
|
||||
# CONFIG_RT_USING_AT is not set
|
||||
|
||||
#
|
||||
# VBUS(Virtual Software BUS)
|
||||
#
|
||||
# CONFIG_RT_USING_VBUS is not set
|
||||
|
||||
#
|
||||
# Utilities
|
||||
#
|
||||
# CONFIG_RT_USING_RYM is not set
|
||||
# CONFIG_RT_USING_ULOG is not set
|
||||
# CONFIG_RT_USING_UTEST is not set
|
||||
# CONFIG_RT_USING_VAR_EXPORT is not set
|
||||
# CONFIG_RT_USING_RT_LINK is not set
|
||||
|
||||
#
|
||||
# RT-Thread Utestcases
|
||||
#
|
||||
# CONFIG_RT_USING_UTESTCASES is not set
|
||||
|
||||
#
|
||||
# Hardware Drivers Config
|
||||
#
|
||||
CONFIG_SOC_IMXRT1052CVL5B=y
|
||||
|
||||
#
|
||||
# On-chip Peripheral Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_BOOT_IMAGE=y
|
||||
# CONFIG_BSP_USING_DMA is not set
|
||||
CONFIG_BSP_USING_GPIO=y
|
||||
CONFIG_BSP_USING_LPUART=y
|
||||
CONFIG_BSP_USING_LPUART1=y
|
||||
# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
|
||||
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
|
||||
# CONFIG_BSP_USING_LPUART2 is not set
|
||||
# CONFIG_BSP_USING_LPUART3 is not set
|
||||
# CONFIG_BSP_USING_LPUART4 is not set
|
||||
# CONFIG_BSP_USING_LPUART8 is not set
|
||||
# CONFIG_BSP_USING_I2C is not set
|
||||
# CONFIG_BSP_USING_CAN is not set
|
||||
# CONFIG_BSP_USING_RTC is not set
|
||||
|
||||
#
|
||||
# Onboard Peripheral Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_SDRAM=y
|
||||
|
||||
#
|
||||
# MicroPython
|
||||
#
|
||||
# CONFIG_PKG_USING_MICROPYTHON is not set
|
||||
|
||||
#
|
||||
# More Drivers
|
||||
#
|
||||
# CONFIG_PKG_USING_RW007 is not set
|
||||
# CONFIG_DRV_USING_OV2640 is not set
|
||||
|
||||
#
|
||||
# APP_Framework
|
||||
#
|
||||
|
||||
#
|
||||
# Framework
|
||||
#
|
||||
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
|
||||
# CONFIG_ADD_XIZI_FETURES is not set
|
||||
# CONFIG_ADD_NUTTX_FETURES is not set
|
||||
CONFIG_ADD_RTTHREAD_FETURES=y
|
||||
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
|
||||
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
|
||||
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
|
||||
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Applications
|
||||
#
|
||||
|
||||
#
|
||||
# config stack size and priority of main task
|
||||
#
|
||||
CONFIG_MAIN_KTASK_STACK_SIZE=1024
|
||||
|
||||
#
|
||||
# ota app
|
||||
#
|
||||
# CONFIG_APPLICATION_OTA is not set
|
||||
|
||||
#
|
||||
# test app
|
||||
#
|
||||
# CONFIG_USER_TEST is not set
|
||||
|
||||
#
|
||||
# connection app
|
||||
#
|
||||
# CONFIG_APPLICATION_CONNECTION is not set
|
||||
|
||||
#
|
||||
# control app
|
||||
#
|
||||
|
||||
#
|
||||
# knowing app
|
||||
#
|
||||
# CONFIG_APPLICATION_KNOWING is not set
|
||||
|
||||
#
|
||||
# sensor app
|
||||
#
|
||||
# CONFIG_APPLICATION_SENSOR is not set
|
||||
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
|
||||
|
||||
#
|
||||
# lib
|
||||
#
|
||||
CONFIG_APP_SELECT_NEWLIB=y
|
||||
# CONFIG_APP_SELECT_OTHER_LIB is not set
|
||||
# CONFIG_LIB_USING_CJSON is not set
|
||||
# CONFIG_LIB_USING_QUEUE is not set
|
||||
# CONFIG_LIB_LV is not set
|
||||
# CONFIG_USING_EMBEDDED_DATABASE is not set
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config ROOT_DIR
|
||||
string
|
||||
default "../../../.."
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
default "."
|
||||
|
||||
config RT_Thread_DIR
|
||||
string
|
||||
default "../.."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
default "../../rt-thread"
|
||||
|
||||
config APP_DIR
|
||||
string
|
||||
default "../../../../APP_Framework"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$RTT_DIR/bsp/imxrt/libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
source "$RT_Thread_DIR/micropython/Kconfig"
|
||||
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
|
||||
source "$ROOT_DIR/APP_Framework/Kconfig"
|
||||
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
# XiDaTong_ARM_Reference_Resource
|
||||
|
||||
## 1. 矽达通介绍
|
||||
|
||||
矽达通外观图:
|
||||
|
||||
|
||||
|
||||
拆开后盖:
|
||||
|
||||
|
||||
|
||||
矽达通烧录这里介绍两种方式，分别是 NXP-MCUBootUtility 和 Keil MDK5
|
||||
|
||||
## 2. NXP-MCUBootUtility 方式烧录
|
||||
|
||||
**[NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility/tree/v3.4.0)** 是一款开源免费的专为 NXP MCU 安全启动而设计的 GUI 工具。目前主要支持 i.MXRT、LPC、Kinetis 系列 MCU 芯片
|
||||
|
||||
> ### 测试环境
|
||||
|
||||
- Windows
|
||||
|
||||
- NXP-MCUBootUtility v3.4.0
|
||||
|
||||
> ### 烧录流程
|
||||
|
||||
将矽达通串口1通过 usb 转串口连接至电脑，并在电脑端查看到相应端口，如下图，com15
|
||||
|
||||
|
||||
|
||||
打开 NXP-MCUBootUtility.exe
|
||||
|
||||
确保一下配置选项正确，COM Port记得选择上述对应的串口
|
||||
|
||||
|
||||
|
||||
将拨码开关拨到 1 on 2 on 3 off 4 off 进入 Serial Download Programming(SDP) 模式, 重新连接电源
|
||||
|
||||
先点击 Connect to ROM，若连接成功按钮会变蓝
|
||||
|
||||
|
||||
|
||||
在 Application Image File 一栏中选择要烧录的 elf 文件，文件格式选择 .out(elf) from GCC ARM，然后点击 All-In-One Action 烧录即可
|
||||
|
||||
|
||||
|
||||
烧录完后后，将拨码开关拨回 1 off 2 off 3 off 4 off 进入 nor-flash 启动模式，重新上电，即可从 QSPI Flash 启动程序，此时可以从串口看到调试信息
|
||||
|
||||
`注：由于采用串口烧录，在连接和烧录的时候记得先关闭串口调试工具`
|
||||
|
||||
## 2. Keil MDK 方式烧录
|
||||
|
||||
Keil MDK 是一系列基于 Arm Cortex-M 的微控制器设备的完整软件开发环境，可以自行去官网 **[购买下载](https://www.keil.com/download/product/)** ，需要注意的是请选择使用 Keil MDK5.24a 及以上版本
|
||||
|
||||
开发板连接 CMSIS-DAP 调试器，如下图所示，连接 DIO/CLK/GND 对应的三个引脚即可
|
||||
|
||||
|
||||
|
||||
> ### 芯片支持包导入
|
||||
|
||||
去keil官网 [http://www.keil.com/dd2/pack/#/eula-container](http://www.keil.com/dd2/pack/#/eula-container) 下载对应的板级安装包
|
||||
|
||||
|
||||
|
||||
注意： 安装包可能随时间推移，版本有所改动，可选择最新版本下载。
|
||||
|
||||
下载完成，安装即可。
|
||||
|
||||
> ### 烧写固件安装
|
||||
|
||||
将开发板烧写固件复制到 Keil5 安装目录 Keil_v5\ARM\Flash\MIMXRT_QSPIFLASH.FLM，该固件可以兼容32M以下nor Flash烧写。
|
||||
|
||||
例如： c:\Keil_v5\ARM\Flash\MIMXRT_QSPIFLASH.FLM
|
||||
|
||||
> ### Keil 环境配置
|
||||
|
||||
查看仿真器是否连接成功：
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
> ### 添加烧写固件
|
||||
|
||||
选择 Flash Download，删除原来的烧写配置
|
||||
|
||||
|
||||
|
||||
添加该烧写固件，size 大小为 32MB
|
||||
|
||||
|
||||
|
||||
下载的一些设置记得勾上：
|
||||
|
||||
|
||||
|
||||
然后编译烧录即可，keil下载不需要进入 SDP 模式，无需拨拨码开关。
|
||||
|
||||
|
||||
|
||||
## 3.矽达通硬件资源
|
||||
|
||||
| 端口 | 功能 |
|
||||
| :------------: | :----------------: |
|
||||
| uart1 | shell |
|
||||
| uart3 | 485CH1（外围接口） |
|
||||
| uart4 | 485CH2（外围接口） |
|
||||
| uart8 | ec200t 4G 通讯 |
|
||||
| uart2 | wifi esp07 |
|
||||
| ch438 EXTU2 | Bluetooth HC08 |
|
||||
| ch438 EXTU3 | Lora E220-400T22S |
|
||||
| ch438 EXTU1 | zigbee E18-MS1PA1 |
|
||||
| SD | sd卡 |
|
||||
| usb1 | ec200t 4G通讯 |
|
||||
| usb2 | 外围usb接口 |
|
||||
| can | can外围接口 |
|
||||
| IIC | 屏幕 |
|
||||
| 其他CH438 EXTU | 外围接口 |
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# for module compiling
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
DefaultEnvironment(tools=[])
|
||||
if rtconfig.PLATFORM == 'armcc':
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
# overwrite cflags, because cflags has '--C99'
|
||||
CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
else:
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
#if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
# libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
#else:
|
||||
# libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
libraries_path_prefix = RTT_ROOT + '/bsp/imxrt/libraries'
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
imxrt_library = 'MIMXRT1050'
|
||||
rtconfig.BSP_LIBRARY_TYPE = imxrt_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
||||
|
||||
# include more drivers
|
||||
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
|
||||
|
||||
# include APP_Framework/Framework
|
||||
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
|
||||
|
||||
# include APP_Framework/Applications
|
||||
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
|
||||
|
||||
# include APP_Framework/lib
|
||||
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
|
||||
|
||||
# include Ubiquitous/RT-Thread/micropython
|
||||
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
CPPDEFINES = ['__START=entry']
|
||||
else:
|
||||
CPPDEFINES = []
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-04-29 tyustli first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include <rtthread.h>
|
||||
#include "drv_gpio.h"
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED pin: GPIO1_IO9 */
|
||||
#define LED0_PIN GET_PIN(1,9)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED0 pin mode to output */
|
||||
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
|
||||
rt_kprintf("XIUOS xidatong build %s %s\n",__DATE__,__TIME__);
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED0_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED0_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_SDRAM
|
||||
static void sram_test2(void)
|
||||
{
|
||||
char *p =NULL;
|
||||
p = rt_malloc(1024*1024*8);
|
||||
if(p == NULL)
|
||||
{
|
||||
rt_kprintf("apply for 8MB memory fail ~!!!");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("appyle for 8MB memory success!!!");
|
||||
}
|
||||
rt_free(p);
|
||||
}
|
||||
MSH_CMD_EXPORT(sram_test2, sram test2);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_IMXRT1052CVL5B
|
||||
bool
|
||||
select SOC_MIMXRT1050_SERIES
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_BOOT_IMAGE
|
||||
bool "Enable boot image"
|
||||
default y
|
||||
config BSP_USING_DMA
|
||||
bool "Enable DMA"
|
||||
default n
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
menuconfig BSP_USING_LPUART
|
||||
bool "Enable UART"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
if BSP_USING_LPUART
|
||||
config BSP_USING_LPUART1
|
||||
bool "Enable LPUART1"
|
||||
default y
|
||||
|
||||
config BSP_LPUART1_RX_USING_DMA
|
||||
bool "Enable LPUART1 RX DMA"
|
||||
depends on BSP_USING_LPUART1
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART1_RX_USING_DMA
|
||||
int "Set LPUART1 RX DMA channel (0-32)"
|
||||
default 0
|
||||
|
||||
config BSP_LPUART1_TX_USING_DMA
|
||||
bool "Enable LPUART1 TX DMA"
|
||||
depends on BSP_USING_LPUART1
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART1_TX_USING_DMA
|
||||
int "Set LPUART1 TX DMA channel (0-32)"
|
||||
default 1
|
||||
|
||||
config BSP_USING_LPUART2
|
||||
bool "Enable LPUART2"
|
||||
default y
|
||||
|
||||
config BSP_LPUART2_RX_USING_DMA
|
||||
bool "Enable LPUART2 RX DMA"
|
||||
depends on BSP_USING_LPUART2
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART2_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART2_RX_USING_DMA
|
||||
int "Set LPUART2 RX DMA channel (0-32)"
|
||||
default 2
|
||||
|
||||
config BSP_LPUART2_TX_USING_DMA
|
||||
bool "Enable LPUART2 TX DMA"
|
||||
depends on BSP_USING_LPUART2
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART2_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART2_TX_USING_DMA
|
||||
int "Set LPUART2 TX DMA channel (0-32)"
|
||||
default 3
|
||||
|
||||
config BSP_USING_LPUART3
|
||||
bool "Enable LPUART3"
|
||||
default y
|
||||
|
||||
config BSP_LPUART3_RX_USING_DMA
|
||||
bool "Enable LPUART3 RX DMA"
|
||||
depends on BSP_USING_LPUART3
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART3_RX_USING_DMA
|
||||
int "Set LPUART3 RX DMA channel (0-32)"
|
||||
default 4
|
||||
|
||||
config BSP_LPUART3_TX_USING_DMA
|
||||
bool "Enable LPUART3 TX DMA"
|
||||
depends on BSP_USING_LPUART3
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART3_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART3_TX_USING_DMA
|
||||
int "Set LPUART3 TX DMA channel (0-32)"
|
||||
default 5
|
||||
|
||||
config BSP_USING_LPUART4
|
||||
bool "Enable LPUART4"
|
||||
default n
|
||||
|
||||
config BSP_LPUART4_RX_USING_DMA
|
||||
bool "Enable LPUART4 RX DMA"
|
||||
depends on BSP_USING_LPUART4
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART4_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART4_RX_USING_DMA
|
||||
int "Set LPUART4 RX DMA channel (0-32)"
|
||||
default 6
|
||||
|
||||
config BSP_LPUART4_TX_USING_DMA
|
||||
bool "Enable LPUART4 TX DMA"
|
||||
depends on BSP_USING_LPUART4
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART4_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART4_TX_USING_DMA
|
||||
int "Set LPUART4 TX DMA channel (0-32)"
|
||||
default 7
|
||||
|
||||
|
||||
config BSP_USING_LPUART8
|
||||
bool "Enable LPUART8"
|
||||
default y
|
||||
|
||||
config BSP_LPUART8_RX_USING_DMA
|
||||
bool "Enable LPUART8 RX DMA"
|
||||
depends on BSP_USING_LPUART8
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART8_RX_DMA_CHANNEL
|
||||
depends on BSP_LPUART8_RX_USING_DMA
|
||||
int "Set LPUART8 RX DMA channel (0-32)"
|
||||
default 8
|
||||
|
||||
config BSP_LPUART8_TX_USING_DMA
|
||||
bool "Enable LPUART8 TX DMA"
|
||||
depends on BSP_USING_LPUART8
|
||||
select BSP_USING_DMA
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_LPUART8_TX_DMA_CHANNEL
|
||||
depends on BSP_LPUART8_TX_USING_DMA
|
||||
int "Set LPUART8 TX DMA channel (0-32)"
|
||||
default 9
|
||||
|
||||
endif
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Enable I2C"
|
||||
select RT_USING_I2C
|
||||
default n
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_I2C1
|
||||
bool "Enable I2C1"
|
||||
default n
|
||||
choice
|
||||
prompt "Select I2C1 badurate"
|
||||
default HW_I2C1_BADURATE_100kHZ
|
||||
|
||||
config HW_I2C1_BADURATE_100kHZ
|
||||
bool "Badurate 100kHZ"
|
||||
|
||||
config HW_I2C1_BADURATE_400kHZ
|
||||
bool "Badurate 400kHZ"
|
||||
endchoice
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Enable CAN"
|
||||
select RT_USING_CAN
|
||||
default n
|
||||
|
||||
if BSP_USING_CAN
|
||||
config BSP_USING_CAN1
|
||||
bool "Enable CAN1"
|
||||
default y
|
||||
endif
|
||||
|
||||
config BSP_USING_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
default n
|
||||
endmenu
|
||||
|
||||
|
||||
endmenu
|
||||
|
|
@ -0,0 +1,468 @@
|
|||
<?xml version="1.0" encoding= "UTF-8" ?>
|
||||
<configuration name="IMXRT1050-EVKB" version="1.5" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.5 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.5.xsd" uuid="789fd1d3-821c-40a6-b04d-44ccc5a5d158" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<common>
|
||||
<processor>MIMXRT1052xxxxB</processor>
|
||||
<package>MIMXRT1052DVL6B</package>
|
||||
<board>IMXRT1050-EVKB</board>
|
||||
<board_revision>A</board_revision>
|
||||
<mcu_data>ksdk2_0</mcu_data>
|
||||
<cores selected="core0">
|
||||
<core name="Cortex-M7F" id="core0" description="M7 core"/>
|
||||
</cores>
|
||||
<description></description>
|
||||
</common>
|
||||
<preferences>
|
||||
<validate_boot_init_only>false</validate_boot_init_only>
|
||||
<generate_extended_information>false</generate_extended_information>
|
||||
</preferences>
|
||||
<tools>
|
||||
<pins name="Pins" version="5.0" enabled="true" update_project_code="true">
|
||||
<pins_profile>
|
||||
<processor_version>5.0.2</processor_version>
|
||||
<power_domains/>
|
||||
<pin_labels>
|
||||
<pin_label pin_num="G11" pin_signal="GPIO_AD_B0_03" label="BSP_BEEP"/>
|
||||
<pin_label pin_num="L13" pin_signal="GPIO_AD_B1_10" label="BSP_RS485_RE" identifier="CSI_D7"/>
|
||||
<pin_label pin_num="J13" pin_signal="GPIO_AD_B1_11" label="BSP_DS18B20" identifier="CSI_D6"/>
|
||||
<pin_label pin_num="K12" pin_signal="GPIO_AD_B1_05" label="BSP_AP3216C_INT" identifier="CSI_MCLK"/>
|
||||
</pin_labels>
|
||||
</pins_profile>
|
||||
<functions_list>
|
||||
<function name="BOARD_InitPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>false</callFromInitBoot>
|
||||
<coreID>core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART2" description="Peripheral LPUART2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART5" description="Peripheral LPUART5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="Peripheral" resourceId="PWM4" description="Peripheral PWM4 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="Peripheral" resourceId="PWM1" description="Peripheral PWM1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"/>
|
||||
<pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"/>
|
||||
<pin peripheral="LPUART2" signal="TX" pin_num="L11" pin_signal="GPIO_AD_B1_02"/>
|
||||
<pin peripheral="LPUART2" signal="RX" pin_num="M12" pin_signal="GPIO_AD_B1_03"/>
|
||||
<pin peripheral="LPUART5" signal="TX" pin_num="D13" pin_signal="GPIO_B1_12"/>
|
||||
<pin peripheral="LPUART5" signal="RX" pin_num="D14" pin_signal="GPIO_B1_13"/>
|
||||
<pin peripheral="PWM4" signal="A, 0" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
|
||||
<pin peripheral="PWM4" signal="A, 1" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
|
||||
<pin peripheral="PWM1" signal="A, 3" pin_num="G13" pin_signal="GPIO_AD_B0_10"/>
|
||||
<pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
|
||||
<pin_features>
|
||||
<pin_feature name="software_input_on" value="Enable"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
|
||||
<pin_features>
|
||||
<pin_feature name="software_input_on" value="Enable"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO1" signal="gpio_io, 26" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
|
||||
<pin peripheral="GPIO1" signal="gpio_io, 03" pin_num="G11" pin_signal="GPIO_AD_B0_03"/>
|
||||
<pin peripheral="GPIO1" signal="gpio_io, 27" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
|
||||
<pin peripheral="GPIO1" signal="gpio_io, 21" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
|
||||
</pins>
|
||||
</function>
|
||||
</functions_list>
|
||||
</pins>
|
||||
<clocks name="Clocks" version="5.0" enabled="true" update_project_code="true">
|
||||
<clocks_profile>
|
||||
<processor_version>5.0.2</processor_version>
|
||||
</clocks_profile>
|
||||
<clock_configurations>
|
||||
<clock_configuration name="BOARD_BootClockRUN">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks.BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources>
|
||||
<clock_source id="XTALOSC24M.OSC.outFreq" value="24 MHz" locked="false" enabled="true"/>
|
||||
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
|
||||
</clock_sources>
|
||||
<clock_outputs>
|
||||
<clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET1_TX_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2880/11 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5/7 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="PLL7_MAIN_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_CLK_ROOT.outFreq" value="352/3 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
|
||||
<setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.FLEXSPI_PODF.scale" value="1" locked="true"/>
|
||||
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
|
||||
<setting id="CCM.LCDIF_PODF.scale" value="8" locked="true"/>
|
||||
<setting id="CCM.LCDIF_PRED.scale" value="7" locked="true"/>
|
||||
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
|
||||
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
|
||||
<setting id="CCM.TRACE_PODF.scale" value="3" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5.div" value="40" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>true</called_from_default_init>
|
||||
</clock_configuration>
|
||||
</clock_configurations>
|
||||
</clocks>
|
||||
<periphs name="Peripherals" version="5.0" enabled="true" update_project_code="true">
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="在工具链/IDE工程中未发现LPUART Driver。" problem_level="2" source="Peripherals">
|
||||
<feature name="enabled" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="工具链/IDE工程中LPUART Driver不被支持的版本。需要：${required_value}，实际：${actual_value}。" problem_level="1" source="Peripherals">
|
||||
<feature name="version" evaluation="equivalent">
|
||||
<data type="Version">2.2.4</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpi2c" description="在工具链/IDE工程中未发现LPI2C Driver。" problem_level="2" source="Peripherals">
|
||||
<feature name="enabled" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpi2c" description="工具链/IDE工程中LPI2C Driver不被支持的版本。需要：${required_value}，实际：${actual_value}。" problem_level="1" source="Peripherals">
|
||||
<feature name="version" evaluation="equivalent">
|
||||
<data type="Version">2.1.5</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<peripherals_profile>
|
||||
<processor_version>5.0.2</processor_version>
|
||||
</peripherals_profile>
|
||||
<functional_groups>
|
||||
<functional_group name="BOARD_InitPeripherals" uuid="a7525270-2da6-4556-8d91-4ab9d0edc0e2" called_from_default_init="true" id_prefix="" core="core0">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="frequency" evaluation="greaterThan">
|
||||
<data type="Frequency" unit="Hz">0</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX of the peripheral LPUART1 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX of the peripheral LPUART1 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="ClockOutput" resourceId="LPI2C_CLK_ROOT" description="LPI2C_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="frequency" evaluation="greaterThan">
|
||||
<data type="Frequency" unit="Hz">0</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPI2C1.lpi2c_scl" description="Signal serial clock of the peripheral LPI2C1 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPI2C1.lpi2c_sda" description="Signal serial data of the peripheral LPI2C1 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="frequency" evaluation="greaterThan">
|
||||
<data type="Frequency" unit="Hz">0</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART2.uart_tx" description="Signal TX of the peripheral LPUART2 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART2.uart_rx" description="Signal RX of the peripheral LPUART2 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="frequency" evaluation="greaterThan">
|
||||
<data type="Frequency" unit="Hz">0</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART5.uart_tx" description="Signal TX of the peripheral LPUART5 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART5.uart_rx" description="Signal RX of the peripheral LPUART5 is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<instances>
|
||||
<instance name="LPUART_1" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART1" enabled="true">
|
||||
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
|
||||
<struct name="lpuartConfig">
|
||||
<setting name="clockSource" value="LpuartClock"/>
|
||||
<setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
|
||||
<setting name="baudRate_Bps" value="115200"/>
|
||||
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
|
||||
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
|
||||
<setting name="isMsb" value="false"/>
|
||||
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
|
||||
<setting name="txFifoWatermark" value="0"/>
|
||||
<setting name="rxFifoWatermark" value="1"/>
|
||||
<setting name="enableRxRTS" value="false"/>
|
||||
<setting name="enableTxCTS" value="false"/>
|
||||
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
|
||||
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
|
||||
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
|
||||
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
|
||||
<setting name="enableTx" value="true"/>
|
||||
<setting name="enableRx" value="true"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="LPI2C_1" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="true">
|
||||
<config_set name="main" quick_selection="qs_interrupt">
|
||||
<setting name="clockSource" value="Lpi2cClock"/>
|
||||
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
|
||||
<struct name="interrupt">
|
||||
<setting name="IRQn" value="LPI2C1_IRQn"/>
|
||||
<setting name="enable_priority" value="false"/>
|
||||
<setting name="enable_custom_name" value="false"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
<config_set name="master" quick_selection="qs_master_transfer">
|
||||
<setting name="mode" value="transfer"/>
|
||||
<struct name="config">
|
||||
<setting name="enableMaster" value="true"/>
|
||||
<setting name="enableDoze" value="true"/>
|
||||
<setting name="debugEnable" value="false"/>
|
||||
<setting name="ignoreAck" value="false"/>
|
||||
<setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
|
||||
<setting name="baudRate_Hz" value="100000"/>
|
||||
<setting name="busIdleTimeout_ns" value="0"/>
|
||||
<setting name="pinLowTimeout_ns" value="0"/>
|
||||
<setting name="sdaGlitchFilterWidth_ns" value="0"/>
|
||||
<setting name="sclGlitchFilterWidth_ns" value="0"/>
|
||||
<struct name="hostRequest">
|
||||
<setting name="enable" value="false"/>
|
||||
<setting name="source" value="kLPI2C_HostRequestExternalPin"/>
|
||||
<setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
|
||||
</struct>
|
||||
</struct>
|
||||
<struct name="transfer">
|
||||
<setting name="blocking" value="false"/>
|
||||
<set name="flags">
|
||||
<selected/>
|
||||
</set>
|
||||
<setting name="slaveAddress" value="0"/>
|
||||
<setting name="direction" value="kLPI2C_Write"/>
|
||||
<setting name="subaddress" value="0"/>
|
||||
<setting name="subaddressSize" value="1"/>
|
||||
<setting name="dataSize" value="1"/>
|
||||
<struct name="callback">
|
||||
<setting name="name" value=""/>
|
||||
<setting name="userData" value=""/>
|
||||
</struct>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="LPUART_2" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART2" enabled="true">
|
||||
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
|
||||
<struct name="lpuartConfig">
|
||||
<setting name="clockSource" value="LpuartClock"/>
|
||||
<setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
|
||||
<setting name="baudRate_Bps" value="115200"/>
|
||||
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
|
||||
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
|
||||
<setting name="isMsb" value="false"/>
|
||||
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
|
||||
<setting name="txFifoWatermark" value="0"/>
|
||||
<setting name="rxFifoWatermark" value="1"/>
|
||||
<setting name="enableRxRTS" value="false"/>
|
||||
<setting name="enableTxCTS" value="false"/>
|
||||
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
|
||||
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
|
||||
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
|
||||
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
|
||||
<setting name="enableTx" value="true"/>
|
||||
<setting name="enableRx" value="true"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="LPUART_3" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART5" enabled="true">
|
||||
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
|
||||
<struct name="lpuartConfig">
|
||||
<setting name="clockSource" value="LpuartClock"/>
|
||||
<setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
|
||||
<setting name="baudRate_Bps" value="115200"/>
|
||||
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
|
||||
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
|
||||
<setting name="isMsb" value="false"/>
|
||||
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
|
||||
<setting name="txFifoWatermark" value="0"/>
|
||||
<setting name="rxFifoWatermark" value="1"/>
|
||||
<setting name="enableRxRTS" value="false"/>
|
||||
<setting name="enableTxCTS" value="false"/>
|
||||
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
|
||||
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
|
||||
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
|
||||
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
|
||||
<setting name="enableTx" value="true"/>
|
||||
<setting name="enableRx" value="true"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
</instances>
|
||||
</functional_group>
|
||||
</functional_groups>
|
||||
<components>
|
||||
<component name="system" type_id="system_54b53072540eeeb8f8e9343e71f28176">
|
||||
<config_set_global name="global_system_definitions"/>
|
||||
</component>
|
||||
</components>
|
||||
</periphs>
|
||||
<common name="common" version="1.0" enabled="true" update_project_code="true">
|
||||
<core name="core0" role="primary" project_name="Project"/>
|
||||
</common>
|
||||
</tools>
|
||||
</configuration>
|
||||
|
|
@ -0,0 +1,465 @@
|
|||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||
*
|
||||
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||
*
|
||||
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||
*
|
||||
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||
*
|
||||
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||
*
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v5.0
|
||||
processor: MIMXRT1052xxxxB
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 5.0.2
|
||||
board: IMXRT1050-EVKB
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 20 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.CAN_CLK_PODF.scale, value: '4', locked: true}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
|
||||
- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true}
|
||||
- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '40'}
|
||||
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar3);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Disable USDHC2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
|
||||
#endif
|
||||
/* Disable CSI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Csi);
|
||||
/* Set CSI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
|
||||
/* Set Csi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CsiMux, 0);
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable CAN clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Can1);
|
||||
CLOCK_DisableClock(kCLOCK_Can2);
|
||||
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 3);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable LCDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_LcdPixel);
|
||||
/* Set LCDIF_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6);
|
||||
/* Set LCDIF_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifDiv, 7);
|
||||
/* Set Lcdif pre clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Disable Flexio2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio2);
|
||||
/* Set FLEXIO2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||||
/* Set FLEXIO2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||||
/* Set Flexio2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* Init ARM PLL. */
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||
/* Init System pfd2. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
|
||||
/* Disable pfd offset. */
|
||||
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
|
||||
/* Disable Usb1 PLL output for USBPHY1. */
|
||||
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* DeInit Video PLL. */
|
||||
CLOCK_DeinitVideoPll();
|
||||
/* Bypass Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
|
||||
/* Set divider for Video PLL. */
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
|
||||
/* Enable Video PLL output. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* DeInit Enet PLL. */
|
||||
CLOCK_DeinitEnetPll();
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* Set Enet output divider. */
|
||||
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
/* Enable Enet output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
/* Enable Enet25M output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
/* DeInit Usb2 PLL. */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
/* Bypass Usb2 PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
|
||||
/* Enable Usb2 PLL output. */
|
||||
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set lvds1 clock source. */
|
||||
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Tx clock source. */
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,691 @@
|
|||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v5.0
|
||||
processor: MIMXRT1052xxxxB
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 5.0.2
|
||||
board: IMXRT1050-EVKB
|
||||
pin_labels:
|
||||
- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BSP_BEEP}
|
||||
- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: BSP_RS485_RE, identifier: CSI_D7}
|
||||
- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: BSP_DS18B20, identifier: CSI_D6}
|
||||
- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: BSP_AP3216C_INT, identifier: CSI_MCLK}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
|
||||
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
|
||||
- {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02}
|
||||
- {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03}
|
||||
- {pin_num: D13, peripheral: LPUART5, signal: TX, pin_signal: GPIO_B1_12}
|
||||
- {pin_num: D14, peripheral: LPUART5, signal: RX, pin_signal: GPIO_B1_13}
|
||||
- {pin_num: H13, peripheral: PWM4, signal: 'A, 0', pin_signal: GPIO_AD_B1_08}
|
||||
- {pin_num: M13, peripheral: PWM4, signal: 'A, 1', pin_signal: GPIO_AD_B1_09}
|
||||
- {pin_num: G13, peripheral: PWM1, signal: 'A, 3', pin_signal: GPIO_AD_B0_10}
|
||||
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, software_input_on: Enable}
|
||||
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, software_input_on: Enable}
|
||||
- {pin_num: L13, peripheral: GPIO1, signal: 'gpio_io, 26', pin_signal: GPIO_AD_B1_10}
|
||||
- {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03}
|
||||
- {pin_num: J13, peripheral: GPIO1, signal: 'gpio_io, 27', pin_signal: GPIO_AD_B1_11}
|
||||
- {pin_num: K12, peripheral: GPIO1, signal: 'gpio_io, 21', pin_signal: GPIO_AD_B1_05}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
|
||||
|
||||
/*CH438 IO initialize
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD
|
||||
0U);*/
|
||||
|
||||
/* uart 1 2 3 4 8 io initialize */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate*/
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
|
||||
0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
|
||||
0U);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
|
||||
0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
|
||||
0U);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_B1_00_LPUART4_TX,
|
||||
0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_B1_01_LPUART4_RX,
|
||||
0U);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_B1_00_LPUART4_TX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_B1_01_LPUART4_RX,
|
||||
0x10B0u);
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
|
||||
0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
|
||||
0U);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
|
||||
0x10B0u);
|
||||
|
||||
/* Semc io initialize sdram can used*/
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 is configured as SEMC_CS0 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 is configured as SEMC_DQS */
|
||||
1U); /* Software Input On Field: Force input path of pad GPIO_EMC_39 */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 is configured as SEMC_RDY */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_29_SEMC_CS0, /* GPIO_EMC_29 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_39_SEMC_DQS, /* GPIO_EMC_39 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_40_SEMC_RDY, /* GPIO_EMC_40 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 PAD functional properties : */
|
||||
0x0110F9u); /* Slew Rate Field: Fast Slew Rate
|
||||
Drive Strength Field: R0/7
|
||||
Speed Field: max(200MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Enabled */
|
||||
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
|
||||
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
|
||||
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
|
||||
|
||||
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
|
||||
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
|
||||
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */
|
||||
|
||||
/* GPIO_AD_B1_02 (coord L11), SPDIF_OUT/J22[7] */
|
||||
#define BOARD_INITPINS_SPDIF_OUT_PERIPHERAL LPUART2 /*!< Device name: LPUART2 */
|
||||
#define BOARD_INITPINS_SPDIF_OUT_SIGNAL TX /*!< LPUART2 signal: TX */
|
||||
|
||||
/* GPIO_AD_B1_03 (coord M12), SPDIF_IN/J22[8] */
|
||||
#define BOARD_INITPINS_SPDIF_IN_PERIPHERAL LPUART2 /*!< Device name: LPUART2 */
|
||||
#define BOARD_INITPINS_SPDIF_IN_SIGNAL RX /*!< LPUART2 signal: RX */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
Binary file not shown.
|
|
@ -0,0 +1,17 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
board.c
|
||||
MCUX_Config/clock_config.c
|
||||
MCUX_Config/pin_mux.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
|
||||
CPPDEFINES = ['CPU_MIMXRT1052CVL5B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-01-05 Bernard first implementation
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
#ifdef BSP_USING_DMA
|
||||
#include "fsl_dmamux.h"
|
||||
#include "fsl_edma.h"
|
||||
#endif
|
||||
|
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
/* MPU configuration. */
|
||||
static void BOARD_ConfigMPU(void)
|
||||
{
|
||||
/* Disable I cache and D cache */
|
||||
SCB_DisableICache();
|
||||
SCB_DisableDCache();
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* Region 0 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 1 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 2 setting */
|
||||
// spi flash: normal type, cacheable, no bufferable, no shareable
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 3 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 4 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 5 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 6 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
#if defined(BSP_USING_SDRAM)
|
||||
/* Region 7 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
|
||||
/* Region 8 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||
#endif
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_DMA
|
||||
void imxrt_dma_init(void)
|
||||
{
|
||||
edma_config_t config;
|
||||
|
||||
DMAMUX_Init(DMAMUX);
|
||||
EDMA_GetDefaultConfig(&config);
|
||||
EDMA_Init(DMA0, &config);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
|
||||
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
|
||||
#ifdef BSP_USING_DMA
|
||||
imxrt_dma_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_us_delay(rt_uint32_t usec)
|
||||
{
|
||||
;
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-09-22 Bernard add board.h to this bsp
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RTT_HEAP$$ZI$$Base;
|
||||
extern int Image$$RTT_HEAP$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base)
|
||||
#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit)
|
||||
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
extern void __RTT_HEAP_END;
|
||||
#define HEAP_END (&__RTT_HEAP_END)
|
||||
|
||||
#else
|
||||
extern int heap_start;
|
||||
extern int heap_end;
|
||||
#define HEAP_BEGIN (&heap_start)
|
||||
#define HEAP_END (&heap_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol m_interrupts_start = 0x60002000;
|
||||
define symbol m_interrupts_end = 0x600023FF;
|
||||
|
||||
define symbol m_text_start = 0x60002400;
|
||||
define symbol m_text_end = 0x61FFFFFF;
|
||||
|
||||
define symbol m_data_start = 0x20000000;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x2023FFFF;
|
||||
|
||||
define exported symbol m_boot_hdr_conf_start = 0x60000000;
|
||||
define symbol m_boot_hdr_ivt_start = 0x60001000;
|
||||
define symbol m_boot_hdr_boot_data_start = 0x60001020;
|
||||
define symbol m_boot_hdr_dcd_data_start = 0x60001030;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
|
||||
define exported symbol __RTT_HEAP_END = m_data2_end;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
|
||||
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
|
||||
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
|
||||
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
|
||||
|
||||
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in DATA_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
|
||||
|
|
@ -0,0 +1,276 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVL5A
|
||||
** MIMXRT1052DVL6A
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.C, 08/2017
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b170927
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2017 NXP
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** 3. Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
|
||||
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
|
||||
|
||||
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00
|
||||
|
||||
m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000
|
||||
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
|
||||
|
||||
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
|
||||
m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
.boot_data :
|
||||
{
|
||||
KEEP(*(.boot_hdr.conf))
|
||||
} > m_boot_data
|
||||
|
||||
.image_vertor_table :
|
||||
{
|
||||
KEEP(*(.boot_hdr.ivt))
|
||||
KEEP(*(.boot_hdr.boot_data))
|
||||
KEEP(*(.boot_hdr.dcd_data))
|
||||
} > m_image_vertor_table
|
||||
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
__VECTOR_RAM = __VECTOR_TABLE;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
/* __CTOR_LIST__ = .; */
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
/* __CTOR_END__ = .; */
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
/* __DTOR_LIST__ = .; */
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* __DTOR_END__ = .; */
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_dtcm
|
||||
|
||||
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_nocache
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_nocache
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_dtcm
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
stack_start = .;
|
||||
. += STACK_SIZE;
|
||||
stack_end = .;
|
||||
__StackTop = .;
|
||||
} > m_dtcm
|
||||
|
||||
.RTT_HEAP :
|
||||
{
|
||||
heap_start = .;
|
||||
. = ALIGN(8);
|
||||
} > m_dtcm
|
||||
|
||||
PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVL5A
|
||||
** MIMXRT1052DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.C, 08/2017
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b170927
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2017 NXP
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** 3. Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_text_start 0x60002000
|
||||
#define m_text_size 0x1F7FE000
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x1000
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if 1
|
||||
LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
|
||||
{
|
||||
RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
|
||||
{
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
|
||||
{
|
||||
RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
|
||||
{
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
|
||||
|
||||
; load region size_region
|
||||
LR_IROM1 m_text_start m_text_size
|
||||
{
|
||||
ER_IROM1 m_text_start m_text_size ; load address = execution address
|
||||
{
|
||||
* (RESET,+FIRST)
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
|
||||
{
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
|
||||
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
|
||||
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
|
||||
|
||||
; ncache RW data
|
||||
RW_m_ncache m_ncache_start m_ncache_size
|
||||
{
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ITCM 0x400 0xFBFF {
|
||||
;drv_flexspi_hyper.o(+RO)
|
||||
;fsl_flexspi.o(+RO)
|
||||
* (*CLOCK_DisableClock)
|
||||
* (*CLOCK_ControlGate)
|
||||
* (*CLOCK_EnableClock)
|
||||
* (*CLOCK_SetDiv)
|
||||
* (itcm)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-05 zylx The first version for STM32F4xx
|
||||
* 2019-4-25 misonyo port to IMXRT
|
||||
*/
|
||||
|
||||
#ifndef SDRAM_PORT_H__
|
||||
#define SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
|
||||
#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
|
||||
/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
|
||||
#define SDRAM_REGION kSEMC_SDRAM_CS0
|
||||
/* CS pin: kSEMC_MUXCSX0/1/2/3 */
|
||||
#define SDRAM_CS_PIN kSEMC_MUXCSX0
|
||||
/* size(kbyte):32MB = 32*1024*1KBytes */
|
||||
#define SDRAM_SIZE ((uint32_t)0x8000)
|
||||
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
|
||||
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
|
||||
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
|
||||
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
|
||||
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
|
||||
#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
|
||||
|
||||
/* Timing configuration for W9825G6KH */
|
||||
/* TRP:precharge to active command time (ns) */
|
||||
#define SDRAM_TRP 18
|
||||
/* TRCD:active to read/write command delay time (ns) */
|
||||
#define SDRAM_TRCD 18
|
||||
/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
|
||||
#define SDRAM_REFRESH_RECOVERY 67
|
||||
/* TWR:write recovery time (ns). */
|
||||
#define SDRAM_TWR 12
|
||||
/* TRAS:active to precharge command time (ns). */
|
||||
#define SDRAM_TRAS 42
|
||||
/* TRC time (ns). */
|
||||
#define SDRAM_TRC 60
|
||||
/* active to active time (ns). */
|
||||
#define SDRAM_ACT2ACT 60
|
||||
/* refresh time (ns). 64ms */
|
||||
#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
|
||||
|
||||
#endif /* SDRAM_PORT_H__ */
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rtthread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>8</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>.\flexspi_nor.ini</tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"CMSIS-DAP-v1-MuseLab" -U0700000105dcff343730534243072257 -O974 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT_QSPIFLASH -FS060000000 -FL02000000</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,987 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rtthread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MIMXRT1052DVL6B</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>NXP.MIMXRT1052_DFP.10.0.1</PackID>
|
||||
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) XRAM(0x20200000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec />
|
||||
<StartupFile />
|
||||
<FlashDriverDll />
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:MIMXRT1052DVL6B$fsl_device_registers.h</RegisterFile>
|
||||
<MemoryEnv />
|
||||
<Cmp />
|
||||
<Asm />
|
||||
<Linker />
|
||||
<OHString />
|
||||
<InfinionOptionDll />
|
||||
<SLE66CMisc />
|
||||
<SLE66AMisc />
|
||||
<SLE66LinkerMisc />
|
||||
<SFDFile>$$Device:MIMXRT1052DVL6B$MIMXRT1052.xml</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath />
|
||||
<IncludePath />
|
||||
<LibPath />
|
||||
<RegisterFilePath />
|
||||
<DBRegisterFilePath />
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name />
|
||||
<UserProg2Name />
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name />
|
||||
<UserProg2Name />
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name />
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString />
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument />
|
||||
<IncludeLibraryModules />
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments />
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3 />
|
||||
<Flash4 />
|
||||
<pFcarmOut />
|
||||
<pFcarmGrp />
|
||||
<pFcArmRoot />
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M7"</AdsCpuType>
|
||||
<RvctDeviceName />
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>1</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>3</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector />
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
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|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_cond.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_cond.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>semaphore.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\semaphore.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_barrier.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_barrier.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>sched.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\sched.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_rwlock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_rwlock.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_attr.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_attr.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_spin.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_spin.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_mutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_mutex.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread_tls.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread_tls.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pthread.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\components\libc\posix\pthreads\pthread.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Libraries</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_MIMXRT1052.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\system_MIMXRT1052.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_gpio.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_lpuart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_lpuart.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_semc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_semc.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_clock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_clock.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_cache.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_cache.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_common.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\drivers\fsl_common.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_MIMXRT1052.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\rt-thread\bsp\imxrt\libraries\MIMXRT1050\MIMXRT1052\arm\startup_MIMXRT1052.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>list</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>double_list.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\APP_Framework\Applications\general_functions\list\double_list.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>single_list.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\APP_Framework\Applications\general_functions\list\single_list.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>sensor</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>framework_init.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\APP_Framework\Applications\framework_init.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>transform</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>transform.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\APP_Framework\Framework\transform_layer\rtthread\transform.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>xip</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_flexspi_nor_boot.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>xip\fsl_flexspi_nor_boot.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_flexspi_nor_flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>xip\fsl_flexspi_nor_flash.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
<RTE>
|
||||
<apis />
|
||||
<components />
|
||||
<files />
|
||||
</RTE>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
#define ROOT_DIR "../../../.."
|
||||
#define BSP_DIR "."
|
||||
#define RT_Thread_DIR "../.."
|
||||
#define RTT_DIR "../../rt-thread"
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_KSERVICE_USING_STDLIB
|
||||
#define RT_DEBUG
|
||||
#define RT_DEBUG_COLOR
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_USING_MEMHEAP_AUTO_BINDING
|
||||
#define RT_USING_MEMHEAP_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40004
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define RT_USING_MSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_DEVFS
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_CPUTIME
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_USING_PTHREADS
|
||||
#define PTHREAD_NUM_MAX 8
|
||||
#define RT_USING_POSIX
|
||||
#define RT_LIBC_USING_TIME
|
||||
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* AT commands */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_IMXRT1052CVL5B
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_BOOT_IMAGE
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_LPUART
|
||||
#define BSP_USING_LPUART1
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_SDRAM
|
||||
|
||||
/* MicroPython */
|
||||
|
||||
|
||||
/* More Drivers */
|
||||
|
||||
|
||||
/* APP_Framework */
|
||||
|
||||
/* Framework */
|
||||
|
||||
#define TRANSFORM_LAYER_ATTRIUBUTE
|
||||
#define ADD_RTTHREAD_FETURES
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 1024
|
||||
|
||||
/* ota app */
|
||||
|
||||
|
||||
/* test app */
|
||||
|
||||
|
||||
/* connection app */
|
||||
|
||||
|
||||
/* control app */
|
||||
|
||||
/* knowing app */
|
||||
|
||||
|
||||
/* sensor app */
|
||||
|
||||
|
||||
/* lib */
|
||||
|
||||
#define APP_SELECT_NEWLIB
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m7'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
#BUILD = 'debug'
|
||||
BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
|
||||
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Os'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
|
||||
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
|
||||
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
|
||||
' -shared -fPIC -nostartfiles -static-libgcc'
|
||||
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU + '.fp.sp'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
|
||||
|
||||
CFLAGS += ' --diag_suppress=66,1296,186,6134'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' --c99'
|
||||
|
||||
POST_ACTION = 'fromelf -z $TARGET'
|
||||
# POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' -D__FPU_PRESENT'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=' + CPU
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=None'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' -Ol'
|
||||
CFLAGS += ' --use_c++_inline'
|
||||
|
||||
AFLAGS = ''
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu ' + CPU
|
||||
AFLAGS += ' --fpu None'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --redirect _Printf=_PrintfTiny'
|
||||
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rtthread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>8</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>.\flexspi_nor.ini</tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"CMSIS-DAP-v1-MuseLab" -U0700000105dcff343730534243072257 -O974 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT_QSPIFLASH -FS060000000 -FL02000000</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,391 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rtthread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MIMXRT1052DVL6B</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>NXP.MIMXRT1052_DFP.10.0.1</PackID>
|
||||
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) XRAM(0x20200000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll></FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:MIMXRT1052DVL6B$fsl_device_registers.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:MIMXRT1052DVL6B$MIMXRT1052.xml</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M7"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>1</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>3</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>--library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186</MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x10000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings>6314</DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
cwd = GetCurrentDir()
|
||||
SOURCES = []
|
||||
CPPPATH = [cwd]
|
||||
if GetDepend('BSP_USING_BOOT_IMAGE'):
|
||||
SOURCES = Glob('*.c')
|
||||
if rtconfig.CROSS_TOOL == 'keil':
|
||||
LINKFLAGS = '--keep=*(.boot_hdr.ivt)'
|
||||
LINKFLAGS += '--keep=*(.boot_hdr.boot_data)'
|
||||
LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)'
|
||||
LINKFLAGS += '--keep=*(.boot_hdr.conf)'
|
||||
else:
|
||||
SOURCES = Glob('*.c')
|
||||
LINKFLAGS = ''
|
||||
else:
|
||||
LINKFLAGS = ''
|
||||
group = DefineGroup('xip', src= SOURCES, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS)
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_flexspi_nor_boot.h
|
||||
* @brief support to register flexspi image vector table
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-22
|
||||
*/
|
||||
|
||||
#ifndef _QUADSPI_BOOT_H_
|
||||
#define _QUADSPI_BOOT_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
typedef struct _ivt_ {
|
||||
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
|
||||
* (see @ref data)
|
||||
*/
|
||||
uint32_t hdr;
|
||||
/** Absolute address of the first instruction to execute from the
|
||||
* image
|
||||
*/
|
||||
uint32_t entry;
|
||||
/** Reserved in this version of HAB: should be NULL. */
|
||||
uint32_t reserved1;
|
||||
/** Absolute address of the image DCD: may be NULL. */
|
||||
uint32_t dcd;
|
||||
/** Absolute address of the Boot Data: may be NULL, but not interpreted
|
||||
* any further by HAB
|
||||
*/
|
||||
uint32_t boot_data;
|
||||
/** Absolute address of the IVT.*/
|
||||
uint32_t self;
|
||||
/** Absolute address of the image CSF.*/
|
||||
uint32_t csf;
|
||||
/** Reserved in this version of HAB: should be zero. */
|
||||
uint32_t reserved2;
|
||||
} ivt;
|
||||
|
||||
#define IVT_MAJOR_VERSION 0x4
|
||||
#define IVT_MAJOR_VERSION_SHIFT 0x4
|
||||
#define IVT_MAJOR_VERSION_MASK 0xF
|
||||
#define IVT_MINOR_VERSION 0x1
|
||||
#define IVT_MINOR_VERSION_SHIFT 0x0
|
||||
#define IVT_MINOR_VERSION_MASK 0xF
|
||||
|
||||
#define IVT_VERSION(major, minor) \
|
||||
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
|
||||
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
|
||||
|
||||
#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */
|
||||
#define IVT_SIZE 0x2000
|
||||
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
|
||||
|
||||
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
|
||||
#define IVT_RSVD (uint32_t)(0x00000000)
|
||||
|
||||
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
typedef struct _boot_data_ {
|
||||
uint32_t start; /* boot start location */
|
||||
uint32_t size; /* size */
|
||||
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
|
||||
uint32_t placeholder; /* placehoder to make even 0x10 size */
|
||||
}BOOT_DATA_T;
|
||||
|
||||
|
||||
/*************************************
|
||||
* DCD Data
|
||||
*************************************/
|
||||
#define DCD_TAG_HEADER (0xD2)
|
||||
#define DCD_TAG_HEADER_SHIFT (24)
|
||||
#define DCD_VERSION (0x40)
|
||||
#define DCD_ARRAY_SIZE 1
|
||||
|
||||
#define FLASH_BASE 0x60000000
|
||||
#define FLASH_END 0x7F7FFFFF
|
||||
#define SCLK 1
|
||||
|
||||
#define DCD_ADDRESS dcd_sdram
|
||||
#define BOOT_DATA_ADDRESS &boot_data
|
||||
#define CSF_ADDRESS 0
|
||||
#define PLUGIN_FLAG (uint32_t)0
|
||||
|
||||
/* External Variables */
|
||||
//extern const uint8_t dcd_sdram[1044];
|
||||
extern const uint8_t dcd_sdram[1072];
|
||||
extern const BOOT_DATA_T boot_data;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_flexspi_nor_flash.c
|
||||
* @brief support to define flexspi flash config
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-22
|
||||
*/
|
||||
|
||||
#include "fsl_flexspi_nor_flash.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(__CC_ARM) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location=".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t Qspiflash_config =
|
||||
{
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.deviceModeCfgEnable = true,
|
||||
.deviceModeType = 1,//Quad Enable command
|
||||
.deviceModeSeq.seqNum = 1,
|
||||
.deviceModeSeq.seqId = 4,
|
||||
.deviceModeArg = 0x000200,//Set QE
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI
|
||||
.sflashA1Size = 16u * 1024u * 1024u,//4MBytes
|
||||
.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
// //Fast Read Sequence
|
||||
// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08),
|
||||
// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0),
|
||||
//Quad Input/output read sequence
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
[2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
|
||||
//Read Status
|
||||
[1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
//Write Enable
|
||||
[3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
|
||||
//Write status
|
||||
[4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
};
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this
|
||||
* list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_flexspi_nor_flash.h
|
||||
* @brief support to define flexspi flash config
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-22
|
||||
*/
|
||||
|
||||
#ifndef __FLEXSPI_NOR_FLASH_H__
|
||||
#define __FLEXSPI_NOR_FLASH_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
|
||||
//!@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __FLEXSPI_NOR_FLASH_H__
|
||||
|
|
@ -412,7 +412,6 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
|
|||
|
||||
struct PinIndex pin_index;
|
||||
|
||||
KPrintf("Imxrt1052PinConfigure\n");
|
||||
if (GetPin(&pin_index, param->pin) < 0) {
|
||||
return ERROR;
|
||||
}
|
||||
|
|
@ -420,7 +419,6 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
|
|||
switch(param->cmd)
|
||||
{
|
||||
case GPIO_CONFIG_MODE:
|
||||
KPrintf("GpioConfigMode %u\n", param->pin);
|
||||
GpioConfigMode(param->mode, &pin_index, param->pin);
|
||||
break;
|
||||
case GPIO_IRQ_REGISTER:
|
||||
|
|
@ -583,6 +581,9 @@ static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Ty
|
|||
|
||||
if (isr_status & (1 << i)) {
|
||||
GPIO_PortClearInterruptFlags(gpio, (1 << i));
|
||||
|
||||
__DSB();
|
||||
|
||||
pin = index_offset + i;
|
||||
if (pin_irq_hdr_tab[pin].hdr) {
|
||||
pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args);
|
||||
|
|
|
|||
|
|
@ -70,6 +70,13 @@ int MountSDCard(void)
|
|||
#include <connect_sdio.h>
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SEMC
|
||||
extern status_t BOARD_InitSEMC(void);
|
||||
#ifdef BSP_USING_EXTSRAM
|
||||
extern int ExtSramInit(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
|
||||
{
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
|
||||
|
|
@ -302,6 +309,22 @@ void InitBoardHardware()
|
|||
|
||||
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
|
||||
#ifdef BSP_USING_SEMC
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
|
||||
/* Set semc clock to 163.86 MHz */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 1);
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
|
||||
|
||||
if (BOARD_InitSEMC() != kStatus_Success) {
|
||||
KPrintf("\r\n SEMC Init Failed\r\n");
|
||||
}
|
||||
#ifdef MEM_EXTERN_SRAM
|
||||
else {
|
||||
ExtSramInit();
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
Imxrt1052HwUartInit();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -21,6 +21,18 @@ menuconfig BSP_USING_GPIO
|
|||
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_LWIP
|
||||
bool "Using LwIP device"
|
||||
default n
|
||||
select RESOURCES_LWIP
|
||||
|
||||
menuconfig BSP_USING_SEMC
|
||||
bool "Using SEMC device"
|
||||
default n
|
||||
if BSP_USING_SEMC
|
||||
source "$BSP_DIR/third_party_driver/semc/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SDIO
|
||||
bool "Using SD card device"
|
||||
default n
|
||||
|
|
|
|||
|
|
@ -1,5 +1,13 @@
|
|||
SRC_DIR := common gpio
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_LWIP),y)
|
||||
SRC_DIR += ethernet
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SEMC),y)
|
||||
SRC_DIR += semc
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_LPUART),y)
|
||||
SRC_DIR += uart
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -611,7 +611,7 @@ void WriteCH438Data(uint8 addr, uint8 dat)
|
|||
********************************************************************************************************/
|
||||
void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)
|
||||
{
|
||||
while (mlen--) {
|
||||
while (mlen--) {
|
||||
WriteCH438Data(maddr, *mbuf++);
|
||||
}
|
||||
}
|
||||
|
|
@ -742,7 +742,7 @@ static void Timeout438Proc(void *parameter)
|
|||
}
|
||||
}
|
||||
|
||||
void Ch438PortInit( uint8 ext_uart_no,uint32 BaudRate )
|
||||
void Ch438PortInit(uint8 ext_uart_no, uint32 BaudRate )
|
||||
{
|
||||
uint32 div;
|
||||
uint8 DLL,DLM,dlab;
|
||||
|
|
@ -767,7 +767,8 @@ void Ch438PortInit( uint8 ext_uart_no,uint32 BaudRate )
|
|||
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
|
||||
|
||||
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */
|
||||
MdelayKTask(50);
|
||||
//MdelayKTask(50);
|
||||
ImxrtUdelay(50000);
|
||||
|
||||
dlab = ReadCH438Data(REG_IER_ADDR);
|
||||
dlab &= 0xDF;
|
||||
|
|
@ -818,7 +819,8 @@ void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate)
|
|||
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
|
||||
|
||||
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */
|
||||
MdelayKTask(50);
|
||||
//MdelayKTask(50);
|
||||
ImxrtUdelay(50000);
|
||||
|
||||
dlab = ReadCH438Data(REG_IER_ADDR);
|
||||
dlab &= 0xDF;
|
||||
|
|
@ -896,14 +898,12 @@ static uint32 ImxrtCh438Init(struct SerialDriver *serial_drv, struct SerialCfgP
|
|||
}
|
||||
|
||||
/* config NRD pin as output*/
|
||||
KPrintf("####TEST CH438_NRD_PIN %u start####\n", CH438_NRD_PIN);
|
||||
pin_cfg.pin = CH438_NRD_PIN;
|
||||
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("config NRD pin %d failed!\n", CH438_NRD_PIN);
|
||||
return ERROR;
|
||||
}
|
||||
KPrintf("####TEST CH438_NRD_PIN %u done####\n", CH438_NRD_PIN);
|
||||
|
||||
/* config ALE pin as output*/
|
||||
pin_cfg.pin = CH438_ALE_PIN;
|
||||
|
|
@ -1027,7 +1027,7 @@ static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param
|
|||
case INT_THR_EMPTY: /* THR EMPTY INTERRUPT*/
|
||||
break;
|
||||
case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT*/
|
||||
case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/
|
||||
case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/
|
||||
rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
|
||||
read_param->read_length = rcv_num;
|
||||
break;
|
||||
|
|
@ -1056,14 +1056,14 @@ static const struct SerialDevDone dev_done =
|
|||
|
||||
static void Ch438InitDefault(struct SerialDriver *serial_drv)
|
||||
{
|
||||
struct PinParam PinCfg;
|
||||
struct PinParam pin_cfg;
|
||||
BusType ch438_pin;
|
||||
|
||||
struct BusConfigureInfo configure_info;
|
||||
|
||||
int ret = 0;
|
||||
configure_info.configure_cmd = OPE_CFG;
|
||||
configure_info.private_data = (void *)&PinCfg;
|
||||
configure_info.private_data = (void *)&pin_cfg;
|
||||
|
||||
ch438_sem = KSemaphoreCreate(0);
|
||||
if (ch438_sem < 0) {
|
||||
|
|
@ -1073,72 +1073,43 @@ static void Ch438InitDefault(struct SerialDriver *serial_drv)
|
|||
|
||||
ch438_pin = PinBusInitGet();
|
||||
|
||||
PinCfg.cmd = GPIO_CONFIG_MODE;
|
||||
PinCfg.pin = CH438_INT_PIN;
|
||||
PinCfg.mode = GPIO_CFG_INPUT_PULLUP;
|
||||
pin_cfg.cmd = GPIO_CONFIG_MODE;
|
||||
pin_cfg.pin = CH438_INT_PIN;
|
||||
pin_cfg.mode = GPIO_CFG_INPUT_PULLUP;
|
||||
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", CH438_INT_PIN);
|
||||
return;
|
||||
}
|
||||
|
||||
PinCfg.cmd = GPIO_IRQ_REGISTER;
|
||||
PinCfg.pin = CH438_INT_PIN;
|
||||
PinCfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING;
|
||||
PinCfg.irq_set.hdr = Ch438Irq;
|
||||
PinCfg.irq_set.args = NONE;
|
||||
pin_cfg.cmd = GPIO_IRQ_REGISTER;
|
||||
pin_cfg.pin = CH438_INT_PIN;
|
||||
pin_cfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING;
|
||||
pin_cfg.irq_set.hdr = Ch438Irq;
|
||||
pin_cfg.irq_set.args = NONE;
|
||||
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("config BSP_CH438_INT_PIN %d failed!\n", CH438_INT_PIN);
|
||||
KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_REGISTER %d failed!\n", CH438_INT_PIN);
|
||||
return;
|
||||
}
|
||||
|
||||
PinCfg.cmd = GPIO_IRQ_ENABLE;
|
||||
PinCfg.pin = CH438_INT_PIN;
|
||||
//disable ch438 int gpio irq
|
||||
pin_cfg.cmd = GPIO_IRQ_DISABLE;
|
||||
pin_cfg.pin = CH438_INT_PIN;
|
||||
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("config BSP_CH438_INT_PIN %d failed!\n", CH438_INT_PIN);
|
||||
KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_DISABLE %d failed!\n", CH438_INT_PIN);
|
||||
return;
|
||||
}
|
||||
|
||||
struct SerialCfgParam serial_cfg;
|
||||
memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
|
||||
configure_info.configure_cmd = OPE_INT;
|
||||
configure_info.private_data = (void *)&serial_cfg;
|
||||
|
||||
serial_cfg.data_cfg.port_configure = PORT_CFG_INIT;
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 0;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_115200;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 1;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 2;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 3;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 4;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 5;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 6;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 7;
|
||||
serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
|
||||
BusDrvConfigure(&serial_drv->driver, &configure_info);
|
||||
//enable ch438 int gpio irq
|
||||
pin_cfg.cmd = GPIO_IRQ_ENABLE;
|
||||
pin_cfg.pin = CH438_INT_PIN;
|
||||
ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("config BSP_CH438_INT_PIN GPIO_IRQ_ENABLE %d failed!\n", CH438_INT_PIN);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32 ImxrtCh438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name)
|
||||
|
|
@ -1272,25 +1243,108 @@ int Imxrt1052HwCh438Init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
void CH438RegTest(unsigned char num)//for test
|
||||
#ifdef CH438_EXTUART_TEST
|
||||
static void CH438RegTest(unsigned char num)//for test
|
||||
{
|
||||
uint8 dat;
|
||||
|
||||
KPrintf("current test serilnum: %02x \r\n",offset_addr[num]);
|
||||
KPrintf("IER: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//?IER
|
||||
KPrintf("IIR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//?IIR
|
||||
KPrintf("LCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//?LCR
|
||||
KPrintf("MCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//?MCR
|
||||
KPrintf("LSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//?LSR
|
||||
KPrintf("MSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//?MSR
|
||||
KPrintf("FCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//?FCR
|
||||
KPrintf("SSR: %02x\r\n",ReadCH438Data( offset_addr[num] | REG_SSR_ADDR ));//?SSR
|
||||
KPrintf("current test serial num: %02x \r\n",offset_addr[num]);
|
||||
KPrintf("IER: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//IER
|
||||
KPrintf("IIR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//IIR
|
||||
KPrintf("LCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//LCR
|
||||
KPrintf("MCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//MCR
|
||||
KPrintf("LSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//LSR
|
||||
KPrintf("MSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//MSR
|
||||
KPrintf("FCR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//FCR
|
||||
KPrintf("SSR: 0x%02x\r\n",ReadCH438Data(offset_addr[num] | REG_SSR_ADDR ));//SSR
|
||||
|
||||
KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
|
||||
KPrintf("SCR0: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR
|
||||
dat = 0x55;
|
||||
WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
|
||||
KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
|
||||
KPrintf("SCR55: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR
|
||||
dat = 0xAA;
|
||||
WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
|
||||
KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
|
||||
KPrintf("SCRAA: 0x%02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//SCR
|
||||
}
|
||||
|
||||
static struct Bus *bus;
|
||||
static struct HardwareDev *dev;
|
||||
static struct Driver *drv;
|
||||
|
||||
static void Ch438Read(void *parameter)
|
||||
{
|
||||
uint8 RevLen;
|
||||
uint8 ext_uart_no = 0;
|
||||
uint8 i, cnt = 0;
|
||||
|
||||
struct BusBlockReadParam read_param;
|
||||
static uint8 Ch438Buff[8][256];
|
||||
|
||||
struct BusBlockWriteParam write_param;
|
||||
|
||||
while (1)
|
||||
{
|
||||
KPrintf("ready to read test_ch438 data\n");
|
||||
|
||||
read_param.buffer = Ch438Buff[ext_uart_no];
|
||||
RevLen = BusDevReadData(dev, &read_param);
|
||||
|
||||
KPrintf("test_ch438 get data %u\n", RevLen);
|
||||
|
||||
if (RevLen) {
|
||||
for(i = 0 ; i < RevLen; i ++) {
|
||||
KPrintf("i %u data 0x%x\n", i, Ch438Buff[ext_uart_no][i]);
|
||||
Ch438Buff[ext_uart_no][i] = 0;
|
||||
}
|
||||
|
||||
cnt ++;
|
||||
write_param.buffer = &cnt;
|
||||
write_param.size = 1;
|
||||
BusDevWriteData(dev, &write_param);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void TestCh438Init(void)
|
||||
{
|
||||
x_err_t flag;
|
||||
|
||||
struct BusConfigureInfo configure_info;
|
||||
|
||||
bus = BusFind(CH438_BUS_NAME);
|
||||
drv = BusFindDriver(bus, CH438_DRIVER_NAME);
|
||||
|
||||
dev = BusFindDevice(bus, CH438_DEVICE_NAME_0);
|
||||
|
||||
struct SerialCfgParam serial_cfg;
|
||||
memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
|
||||
configure_info.configure_cmd = OPE_INT;
|
||||
configure_info.private_data = (void *)&serial_cfg;
|
||||
|
||||
serial_cfg.data_cfg.port_configure = PORT_CFG_INIT;
|
||||
|
||||
serial_cfg.data_cfg.ext_uart_no = 0;
|
||||
serial_cfg.data_cfg.serial_baud_rate = 115200;
|
||||
BusDrvConfigure(drv, &configure_info);
|
||||
|
||||
KPrintf("ready to create test_ch438 task\n");
|
||||
|
||||
int32 task_CH438_read = KTaskCreate("task_CH438_read", Ch438Read, NONE, 2048, 10);
|
||||
flag = StartupKTask(task_CH438_read);
|
||||
if (flag != EOK) {
|
||||
KPrintf("StartupKTask task_CH438_read failed .\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void TestCh438(void)
|
||||
{
|
||||
TestCh438Init();
|
||||
|
||||
CH438RegTest(0);
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
|
||||
TestCh438, TestCh438, TestCh438 );
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := enet_ethernetif.c enet_ethernetif_kinetis.c fsl_enet.c
|
||||
SRC_DIR := lan8720
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,313 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file enet_ethernetif.c
|
||||
* @brief ethernet drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/def.h"
|
||||
#include "lwip/mem.h"
|
||||
#include "lwip/pbuf.h"
|
||||
#include "lwip/stats.h"
|
||||
#include "lwip/snmp.h"
|
||||
#include "lwip/ethip6.h"
|
||||
#include "netif/etharp.h"
|
||||
#include "netif/ppp/pppoe.h"
|
||||
#include "lwip/igmp.h"
|
||||
#include "lwip/mld6.h"
|
||||
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
//#include "FreeRTOS.h"
|
||||
//#include "event_groups.h"
|
||||
#endif
|
||||
|
||||
#include "netif/ethernet.h"
|
||||
#include "enet_ethernetif.h"
|
||||
#include "enet_ethernetif_priv.h"
|
||||
|
||||
#include "fsl_enet.h"
|
||||
#include "fsl_phy.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
#include "sys_arch.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void enet_delay(void)
|
||||
{
|
||||
volatile uint32_t i = 0;
|
||||
for (i = 0; i < 1000000; ++i)
|
||||
{
|
||||
__asm("NOP"); /* delay */
|
||||
}
|
||||
}
|
||||
|
||||
void Time_Update_LwIP(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ethernetif_clk_init(void)
|
||||
{
|
||||
const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1};
|
||||
CLOCK_InitEnetPll(&config);
|
||||
SysTick_Config(USEC_TO_COUNT(1000U, CLOCK_GetFreq(kCLOCK_CoreSysClk)));
|
||||
}
|
||||
|
||||
void ethernetif_gpio_init(void)
|
||||
{
|
||||
gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
|
||||
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
|
||||
|
||||
GPIO_PinInit(GPIO1, 3, &gpio_config);
|
||||
GPIO_PinInit(GPIO1, 10, &gpio_config);
|
||||
/* pull up the ENET_INT before RESET. */
|
||||
GPIO_WritePinOutput(GPIO1, 10, 1);
|
||||
GPIO_WritePinOutput(GPIO1, 3, 0);
|
||||
enet_delay();
|
||||
GPIO_WritePinOutput(GPIO1, 3, 1);
|
||||
}
|
||||
|
||||
void ETH_BSP_Config(void)
|
||||
{
|
||||
static int flag = 0;
|
||||
if(flag == 0)
|
||||
{
|
||||
ethernetif_clk_init();
|
||||
ethernetif_gpio_init();
|
||||
flag = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void ethernetif_phy_init(struct ethernetif *ethernetif,
|
||||
const ethernetif_config_t *ethernetifConfig,
|
||||
enet_config_t *config)
|
||||
{
|
||||
uint32_t sysClock;
|
||||
status_t status;
|
||||
bool link = false;
|
||||
uint32_t count = 0;
|
||||
phy_speed_t speed;
|
||||
phy_duplex_t duplex;
|
||||
|
||||
sysClock = CLOCK_GetFreq(ethernetifConfig->clockName);
|
||||
|
||||
LWIP_PLATFORM_DIAG(("Initializing PHY...\r\n"));
|
||||
|
||||
while ((count < ENET_ATONEGOTIATION_TIMEOUT) && (!link))
|
||||
{
|
||||
status = PHY_Init(*ethernetif_enet_ptr(ethernetif), ethernetifConfig->phyAddress, sysClock);
|
||||
|
||||
if (kStatus_Success == status)
|
||||
{
|
||||
PHY_GetLinkStatus(*ethernetif_enet_ptr(ethernetif), ethernetifConfig->phyAddress, &link);
|
||||
}
|
||||
else if (kStatus_PHY_AutoNegotiateFail == status)
|
||||
{
|
||||
LWIP_PLATFORM_DIAG(("PHY Auto-negotiation failed. Please check the ENET cable connection and link partner setting."));
|
||||
}
|
||||
else
|
||||
{
|
||||
LWIP_ASSERT("\r\nCannot initialize PHY.\r\n", 0);
|
||||
}
|
||||
|
||||
count++;
|
||||
}
|
||||
|
||||
if (link)
|
||||
{
|
||||
/* Get the actual PHY link speed. */
|
||||
PHY_GetLinkSpeedDuplex(*ethernetif_enet_ptr(ethernetif), ethernetifConfig->phyAddress, &speed, &duplex);
|
||||
/* Change the MII speed and duplex for actual link status. */
|
||||
config->miiSpeed = (enet_mii_speed_t)speed;
|
||||
config->miiDuplex = (enet_mii_duplex_t)duplex;
|
||||
}
|
||||
#if 0 /* Disable assert. If initial auto-negation is timeout, \ \
|
||||
the ENET is set to default (100Mbs and full-duplex). */
|
||||
else
|
||||
{
|
||||
LWIP_ASSERT("\r\nGiving up PHY initialization. Please check the ENET cable connection and link partner setting and reset the board.\r\n", 0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* This function should be called when a packet is ready to be read
|
||||
* from the interface. It uses the function ethernetif_linkinput() that
|
||||
* should handle the actual reception of bytes from the network
|
||||
* interface. Then the type of the received packet is determined and
|
||||
* the appropriate input function is called.
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
*/
|
||||
|
||||
void ethernetif_input(struct netif *netif)
|
||||
{
|
||||
struct pbuf *p;
|
||||
err_t ret = 0;
|
||||
|
||||
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
||||
|
||||
/* move received packet into a new pbuf */
|
||||
while ((p = ethernetif_linkinput(netif)) != NULL)
|
||||
{
|
||||
/* pass all packets to ethernet_input, which decides what packets it supports */
|
||||
if ((ret = netif->input(p, netif)) != ERR_OK)
|
||||
{
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
|
||||
lw_print("lw: [%s] ret %d p %p\n", __func__, ret, p);
|
||||
pbuf_free(p);
|
||||
p = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static ENET_Type *ethernetif_get_enet_base(const uint8_t enetIdx)
|
||||
{
|
||||
ENET_Type* enets[] = ENET_BASE_PTRS;
|
||||
int arrayIdx;
|
||||
int enetCount;
|
||||
|
||||
for (arrayIdx = 0, enetCount = 0; arrayIdx < ARRAY_SIZE(enets); arrayIdx++)
|
||||
{
|
||||
if (enets[arrayIdx] != 0U) /* process only defined positions */
|
||||
{ /* (some SOC headers count ENETs from 1 instead of 0) */
|
||||
if (enetCount == enetIdx)
|
||||
{
|
||||
return enets[arrayIdx];
|
||||
}
|
||||
enetCount++;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
err_t ethernetif_init(struct netif *netif, struct ethernetif *ethernetif,
|
||||
const uint8_t enetIdx,
|
||||
const ethernetif_config_t *ethernetifConfig)
|
||||
{
|
||||
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
||||
LWIP_ASSERT("ethernetifConfig != NULL", (ethernetifConfig != NULL));
|
||||
|
||||
#if LWIP_NETIF_HOSTNAME
|
||||
/* Initialize interface hostname */
|
||||
netif->hostname = "lwip";
|
||||
#endif /* LWIP_NETIF_HOSTNAME */
|
||||
|
||||
/*
|
||||
* Initialize the snmp variables and counters inside the struct netif.
|
||||
* The last argument should be replaced with your link speed, in units
|
||||
* of bits per second.
|
||||
*/
|
||||
MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
|
||||
|
||||
netif->state = ethernetif;
|
||||
netif->name[0] = IFNAME0;
|
||||
netif->name[1] = IFNAME1;
|
||||
/* We directly use etharp_output() here to save a function call.
|
||||
* You can instead declare your own function an call etharp_output()
|
||||
* from it if you have to do some checks before sending (e.g. if link
|
||||
* is available...) */
|
||||
#if LWIP_IPV4
|
||||
netif->output = etharp_output;
|
||||
#endif
|
||||
#if LWIP_IPV6
|
||||
netif->output_ip6 = ethip6_output;
|
||||
#endif /* LWIP_IPV6 */
|
||||
netif->linkoutput = ethernetif_linkoutput;
|
||||
|
||||
#if LWIP_IPV4 && LWIP_IGMP
|
||||
netif_set_igmp_mac_filter(netif, ethernetif_igmp_mac_filter);
|
||||
netif->flags |= NETIF_FLAG_IGMP;
|
||||
#endif
|
||||
#if LWIP_IPV6 && LWIP_IPV6_MLD
|
||||
netif_set_mld_mac_filter(netif, ethernetif_mld_mac_filter);
|
||||
netif->flags |= NETIF_FLAG_MLD6;
|
||||
#endif
|
||||
|
||||
/* Init ethernetif parameters.*/
|
||||
*ethernetif_enet_ptr(ethernetif) = ethernetif_get_enet_base(enetIdx);
|
||||
LWIP_ASSERT("*ethernetif_enet_ptr(ethernetif) != NULL", (*ethernetif_enet_ptr(ethernetif) != NULL));
|
||||
|
||||
/* set MAC hardware address length */
|
||||
netif->hwaddr_len = ETH_HWADDR_LEN;
|
||||
|
||||
/* set MAC hardware address */
|
||||
memcpy(netif->hwaddr, ethernetifConfig->macAddress, NETIF_MAX_HWADDR_LEN);
|
||||
|
||||
/* maximum transfer unit */
|
||||
netif->mtu = 1500; /* TODO: define a config */
|
||||
|
||||
/* device capabilities */
|
||||
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
|
||||
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
|
||||
|
||||
/* ENET driver initialization.*/
|
||||
ethernetif_enet_init(netif, ethernetif, ethernetifConfig);
|
||||
|
||||
#if LWIP_IPV6 && LWIP_IPV6_MLD
|
||||
/*
|
||||
* For hardware/netifs that implement MAC filtering.
|
||||
* All-nodes link-local is handled by default, so we must let the hardware know
|
||||
* to allow multicast packets in.
|
||||
* Should set mld_mac_filter previously. */
|
||||
if (netif->mld_mac_filter != NULL)
|
||||
{
|
||||
ip6_addr_t ip6_allnodes_ll;
|
||||
ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll);
|
||||
netif->mld_mac_filter(netif, &ip6_allnodes_ll, NETIF_ADD_MAC_FILTER);
|
||||
}
|
||||
#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,674 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file enet_ethernetif_kinetis.c
|
||||
* @brief ethernet drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#include "sys_arch.h"
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/def.h"
|
||||
#include "lwip/mem.h"
|
||||
#include "lwip/pbuf.h"
|
||||
#include "lwip/stats.h"
|
||||
#include "lwip/snmp.h"
|
||||
#include "lwip/ethip6.h"
|
||||
#include "netif/etharp.h"
|
||||
#include "netif/ppp/pppoe.h"
|
||||
#include "lwip/igmp.h"
|
||||
#include "lwip/mld6.h"
|
||||
|
||||
#ifdef FSL_RTOS_XIUOS
|
||||
#define USE_RTOS 1
|
||||
#define FSL_RTOS_FREE_RTOS
|
||||
#endif
|
||||
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
|
||||
#ifdef FSL_RTOS_XIUOS
|
||||
#include "xs_sem.h"
|
||||
|
||||
#else
|
||||
#include "FreeRTOS.h"
|
||||
#include "event_groups.h"
|
||||
#include "list.h"
|
||||
#endif
|
||||
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
typedef TickType_t EventBits_t;
|
||||
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#define portBASE_TYPE long
|
||||
|
||||
#define pdFALSE ( ( BaseType_t ) 0 )
|
||||
#define pdTRUE ( ( BaseType_t ) 1 )
|
||||
|
||||
#define pdPASS ( pdTRUE )
|
||||
#define pdFAIL ( pdFALSE )
|
||||
|
||||
#ifndef FSL_RTOS_XIUOS
|
||||
typedef struct EventGroupDef_t
|
||||
{
|
||||
EventBits_t uxEventBits;
|
||||
List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
|
||||
|
||||
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||
UBaseType_t uxEventGroupNumber;
|
||||
#endif
|
||||
|
||||
#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
||||
uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
|
||||
#endif
|
||||
} EventGroup_t;
|
||||
|
||||
struct EventGroupDef_t;
|
||||
typedef struct EventGroupDef_t * EventGroupHandle_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "enet_ethernetif.h"
|
||||
#include "enet_ethernetif_priv.h"
|
||||
|
||||
#include "fsl_enet.h"
|
||||
#include "fsl_phy.h"
|
||||
|
||||
#include "sys_arch.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* Helper struct to hold private data used to operate your ethernet interface.
|
||||
*/
|
||||
struct ethernetif
|
||||
{
|
||||
ENET_Type *base;
|
||||
#if (defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)) || \
|
||||
(USE_RTOS && defined(FSL_RTOS_FREE_RTOS))
|
||||
enet_handle_t handle;
|
||||
#endif
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
|
||||
#ifdef FSL_RTOS_XIUOS
|
||||
int enetSemaphore;
|
||||
#else
|
||||
EventGroupHandle_t enetTransmitAccessEvent;
|
||||
#endif
|
||||
EventBits_t txFlag;
|
||||
#endif
|
||||
enet_rx_bd_struct_t *RxBuffDescrip;
|
||||
enet_tx_bd_struct_t *TxBuffDescrip;
|
||||
rx_buffer_t *RxDataBuff;
|
||||
tx_buffer_t *TxDataBuff;
|
||||
};
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
|
||||
int32 lwip_obtain_semaphore(struct netif *netif)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
return (KSemaphoreObtain(ethernetif->enetSemaphore, WAITING_FOREVER) == EOK);
|
||||
}
|
||||
|
||||
#if FSL_FEATURE_ENET_QUEUE > 1
|
||||
static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, uint32_t ringId, enet_event_t event, void *param)
|
||||
#else
|
||||
static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param)
|
||||
#endif /* FSL_FEATURE_ENET_QUEUE */
|
||||
{
|
||||
struct netif *netif = (struct netif *)param;
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
BaseType_t xResult;
|
||||
|
||||
switch (event)
|
||||
{
|
||||
case kENET_RxEvent:
|
||||
ethernetif_input(netif);
|
||||
break;
|
||||
case kENET_TxEvent:
|
||||
#ifndef FSL_RTOS_XIUOS
|
||||
{
|
||||
portBASE_TYPE taskToWake = pdFALSE;
|
||||
|
||||
#ifdef __CA7_REV
|
||||
if (SystemGetIRQNestingLevel())
|
||||
#else
|
||||
if (__get_IPSR())
|
||||
#endif
|
||||
{
|
||||
xResult = xEventGroupSetBitsFromISR(ethernetif->enetTransmitAccessEvent, ethernetif->txFlag, &taskToWake);
|
||||
if ((pdPASS == xResult) && (pdTRUE == taskToWake))
|
||||
{
|
||||
portYIELD_FROM_ISR(taskToWake);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xEventGroupSetBits(ethernetif->enetTransmitAccessEvent, ethernetif->txFlag);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
KSemaphoreAbandon(ethernetif->enetSemaphore);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if LWIP_IPV4 && LWIP_IGMP
|
||||
err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group,
|
||||
enum netif_mac_filter_action action)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
uint8_t multicastMacAddr[6];
|
||||
err_t result;
|
||||
|
||||
multicastMacAddr[0] = 0x01U;
|
||||
multicastMacAddr[1] = 0x00U;
|
||||
multicastMacAddr[2] = 0x5EU;
|
||||
multicastMacAddr[3] = (group->addr >> 8) & 0x7FU;
|
||||
multicastMacAddr[4] = (group->addr >> 16) & 0xFFU;
|
||||
multicastMacAddr[5] = (group->addr >> 24) & 0xFFU;
|
||||
|
||||
switch (action)
|
||||
{
|
||||
case IGMP_ADD_MAC_FILTER:
|
||||
/* Adds the ENET device to a multicast group.*/
|
||||
ENET_AddMulticastGroup(ethernetif->base, multicastMacAddr);
|
||||
result = ERR_OK;
|
||||
break;
|
||||
case IGMP_DEL_MAC_FILTER:
|
||||
/*
|
||||
* Moves the ENET device from a multicast group.
|
||||
* Since the ENET_LeaveMulticastGroup() could filter out also other
|
||||
* group addresses having the same hash, the call is commented out.
|
||||
*/
|
||||
/* ENET_LeaveMulticastGroup(ethernetif->base, multicastMacAddr); */
|
||||
result = ERR_OK;
|
||||
break;
|
||||
default:
|
||||
result = ERR_IF;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if LWIP_IPV6 && LWIP_IPV6_MLD
|
||||
err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group,
|
||||
enum netif_mac_filter_action action)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
uint8_t multicastMacAddr[6];
|
||||
err_t result;
|
||||
|
||||
multicastMacAddr[0] = 0x33U;
|
||||
multicastMacAddr[1] = 0x33U;
|
||||
multicastMacAddr[2] = (group->addr[3]) & 0xFFU;
|
||||
multicastMacAddr[3] = (group->addr[3] >> 8) & 0xFFU;
|
||||
multicastMacAddr[4] = (group->addr[3] >> 16) & 0xFFU;
|
||||
multicastMacAddr[5] = (group->addr[3] >> 24) & 0xFFU;
|
||||
|
||||
switch (action)
|
||||
{
|
||||
case NETIF_ADD_MAC_FILTER:
|
||||
/* Adds the ENET device to a multicast group.*/
|
||||
ENET_AddMulticastGroup(ethernetif->base, multicastMacAddr);
|
||||
result = ERR_OK;
|
||||
break;
|
||||
case NETIF_DEL_MAC_FILTER:
|
||||
/*
|
||||
* Moves the ENET device from a multicast group.
|
||||
* Since the ENET_LeaveMulticastGroup() could filter out also other
|
||||
* group addresses having the same hash, the call is commented out.
|
||||
*/
|
||||
/* ENET_LeaveMulticastGroup(ethernetif->base, multicastMacAddr); */
|
||||
result = ERR_OK;
|
||||
break;
|
||||
default:
|
||||
result = ERR_IF;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Initializes ENET driver.
|
||||
*/
|
||||
void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif,
|
||||
const ethernetif_config_t *ethernetifConfig)
|
||||
{
|
||||
enet_config_t config;
|
||||
uint32_t sysClock;
|
||||
enet_buffer_config_t buffCfg[ENET_RING_NUM];
|
||||
|
||||
/* prepare the buffer configuration. */
|
||||
buffCfg[0].rxBdNumber = ENET_RXBD_NUM; /* Receive buffer descriptor number. */
|
||||
buffCfg[0].txBdNumber = ENET_TXBD_NUM; /* Transmit buffer descriptor number. */
|
||||
buffCfg[0].rxBuffSizeAlign = sizeof(rx_buffer_t); /* Aligned receive data buffer size. */
|
||||
buffCfg[0].txBuffSizeAlign = sizeof(tx_buffer_t); /* Aligned transmit data buffer size. */
|
||||
buffCfg[0].rxBdStartAddrAlign = &(ethernetif->RxBuffDescrip[0]); /* Aligned receive buffer descriptor start address. */
|
||||
buffCfg[0].txBdStartAddrAlign = &(ethernetif->TxBuffDescrip[0]); /* Aligned transmit buffer descriptor start address. */
|
||||
buffCfg[0].rxBufferAlign = &(ethernetif->RxDataBuff[0][0]); /* Receive data buffer start address. */
|
||||
buffCfg[0].txBufferAlign = &(ethernetif->TxDataBuff[0][0]); /* Transmit data buffer start address. */
|
||||
|
||||
sysClock = CLOCK_GetFreq(ethernetifConfig->clockName);
|
||||
|
||||
ENET_GetDefaultConfig(&config);
|
||||
config.ringNum = ENET_RING_NUM;
|
||||
|
||||
ethernetif_phy_init(ethernetif, ethernetifConfig, &config);
|
||||
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
uint32_t instance;
|
||||
static ENET_Type *const enetBases[] = ENET_BASE_PTRS;
|
||||
static const IRQn_Type enetTxIrqId[] = ENET_Transmit_IRQS;
|
||||
/*! @brief Pointers to enet receive IRQ number for each instance. */
|
||||
static const IRQn_Type enetRxIrqId[] = ENET_Receive_IRQS;
|
||||
#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
|
||||
/*! @brief Pointers to enet timestamp IRQ number for each instance. */
|
||||
static const IRQn_Type enetTsIrqId[] = ENET_1588_Timer_IRQS;
|
||||
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
|
||||
|
||||
/* Create the Event for transmit busy release trigger. */
|
||||
#ifdef FSL_RTOS_XIUOS
|
||||
if(ethernetif->enetSemaphore < 0)
|
||||
{
|
||||
ethernetif->enetSemaphore = KSemaphoreCreate(0);
|
||||
}
|
||||
#else
|
||||
ethernetif->enetTransmitAccessEvent = xEventGroupCreate();
|
||||
#endif
|
||||
ethernetif->txFlag = 0x1;
|
||||
|
||||
config.interrupt |= kENET_RxFrameInterrupt | kENET_TxFrameInterrupt | kENET_TxBufferInterrupt;
|
||||
|
||||
for (instance = 0; instance < ARRAY_SIZE(enetBases); instance++)
|
||||
{
|
||||
if (enetBases[instance] == ethernetif->base)
|
||||
{
|
||||
#ifdef __CA7_REV
|
||||
GIC_SetPriority(enetRxIrqId[instance], ENET_PRIORITY);
|
||||
GIC_SetPriority(enetTxIrqId[instance], ENET_PRIORITY);
|
||||
#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
|
||||
GIC_SetPriority(enetTsIrqId[instance], ENET_1588_PRIORITY);
|
||||
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
|
||||
#else
|
||||
NVIC_SetPriority(enetRxIrqId[instance], ENET_PRIORITY);
|
||||
NVIC_SetPriority(enetTxIrqId[instance], ENET_PRIORITY);
|
||||
#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
|
||||
NVIC_SetPriority(enetTsIrqId[instance], ENET_1588_PRIORITY);
|
||||
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
|
||||
#endif /* __CA7_REV */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
LWIP_ASSERT("Input Ethernet base error!", (instance != ARRAY_SIZE(enetBases)));
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
/* Initialize the ENET module.*/
|
||||
ENET_Init(ethernetif->base, ðernetif->handle, &config, &buffCfg[0], netif->hwaddr, sysClock);
|
||||
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
ENET_SetCallback(ðernetif->handle, ethernet_callback, netif);
|
||||
#endif
|
||||
|
||||
ENET_ActiveRead(ethernetif->base);
|
||||
// low_level_init();
|
||||
}
|
||||
|
||||
ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif)
|
||||
{
|
||||
return &(ethernetif->base);
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns next buffer for TX.
|
||||
* Can wait if no buffer available.
|
||||
*/
|
||||
static unsigned char *enet_get_tx_buffer(struct ethernetif *ethernetif)
|
||||
{
|
||||
static unsigned char ucBuffer[ENET_FRAME_MAX_FRAMELEN];
|
||||
return ucBuffer;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sends frame via ENET.
|
||||
*/
|
||||
static err_t enet_send_frame(struct ethernetif *ethernetif, unsigned char *data, const uint32_t length)
|
||||
{
|
||||
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
|
||||
{
|
||||
status_t result;
|
||||
|
||||
lw_print("lw: [%s] len %d\n", __func__, length);
|
||||
|
||||
do
|
||||
{
|
||||
result = ENET_SendFrame(ethernetif->base, ðernetif->handle, data, length);
|
||||
|
||||
if (result == kStatus_ENET_TxFrameBusy)
|
||||
{
|
||||
#ifdef FSL_RTOS_XIUOS
|
||||
KSemaphoreObtain(ethernetif->enetSemaphore, portMAX_DELAY);
|
||||
#else
|
||||
xEventGroupWaitBits(ethernetif->enetTransmitAccessEvent, ethernetif->txFlag, pdTRUE, (BaseType_t) false,
|
||||
portMAX_DELAY);
|
||||
#endif
|
||||
}
|
||||
|
||||
} while (result == kStatus_ENET_TxFrameBusy);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
#else
|
||||
{
|
||||
uint32_t counter;
|
||||
|
||||
for (counter = ENET_TIMEOUT; counter != 0U; counter--)
|
||||
{
|
||||
if (ENET_SendFrame(ethernetif->base, ðernetif->handle, data, length) != kStatus_ENET_TxFrameBusy)
|
||||
{
|
||||
return ERR_OK;
|
||||
}
|
||||
}
|
||||
|
||||
return ERR_TIMEOUT;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
struct pbuf *ethernetif_linkinput(struct netif *netif)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
struct pbuf *p = NULL;
|
||||
struct pbuf *q;
|
||||
uint32_t len;
|
||||
status_t status;
|
||||
|
||||
/* Obtain the size of the packet and put it into the "len"
|
||||
variable. */
|
||||
status = ENET_GetRxFrameSize(ðernetif->handle, &len);
|
||||
|
||||
if (kStatus_ENET_RxFrameEmpty != status)
|
||||
{
|
||||
/* Call ENET_ReadFrame when there is a received frame. */
|
||||
if (len != 0)
|
||||
{
|
||||
#if ETH_PAD_SIZE
|
||||
len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
|
||||
#endif
|
||||
|
||||
/* We allocate a pbuf chain of pbufs from the pool. */
|
||||
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
|
||||
|
||||
if (p != NULL)
|
||||
{
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
|
||||
#endif
|
||||
if (p->next == 0) /* One-chain buffer.*/
|
||||
{
|
||||
ENET_ReadFrame(ethernetif->base, ðernetif->handle, p->payload, p->len);
|
||||
}
|
||||
else /* Multi-chain buffer.*/
|
||||
{
|
||||
uint8_t data_tmp[ENET_FRAME_MAX_FRAMELEN];
|
||||
uint32_t data_tmp_len = 0;
|
||||
|
||||
ENET_ReadFrame(ethernetif->base, ðernetif->handle, data_tmp, p->tot_len);
|
||||
|
||||
/* We iterate over the pbuf chain until we have read the entire
|
||||
* packet into the pbuf. */
|
||||
for (q = p; (q != NULL) && ((data_tmp_len + q->len) <= sizeof(data_tmp)); q = q->next)
|
||||
{
|
||||
/* Read enough bytes to fill this pbuf in the chain. The
|
||||
* available data in the pbuf is given by the q->len
|
||||
* variable. */
|
||||
memcpy(q->payload, &data_tmp[data_tmp_len], q->len);
|
||||
data_tmp_len += q->len;
|
||||
}
|
||||
}
|
||||
|
||||
MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len);
|
||||
if (((u8_t *)p->payload)[0] & 1)
|
||||
{
|
||||
/* broadcast or multicast packet*/
|
||||
MIB2_STATS_NETIF_INC(netif, ifinnucastpkts);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* unicast packet*/
|
||||
MIB2_STATS_NETIF_INC(netif, ifinucastpkts);
|
||||
}
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||||
#endif
|
||||
|
||||
LINK_STATS_INC(link.recv);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* drop packet*/
|
||||
ENET_ReadFrame(ethernetif->base, ðernetif->handle, NULL, 0U);
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_linkinput: Fail to allocate new memory space\n"));
|
||||
|
||||
LINK_STATS_INC(link.memerr);
|
||||
LINK_STATS_INC(link.drop);
|
||||
MIB2_STATS_NETIF_INC(netif, ifindiscards);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the received buffer when error happened. */
|
||||
if (status == kStatus_ENET_RxFrameError)
|
||||
{
|
||||
#if 0 && defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0) /* Error statisctics */
|
||||
enet_data_error_stats_t eErrStatic;
|
||||
/* Get the error information of the received g_frame. */
|
||||
ENET_GetRxErrBeforeReadFrame(ðernetif->handle, &eErrStatic);
|
||||
#endif
|
||||
/* Update the receive buffer. */
|
||||
ENET_ReadFrame(ethernetif->base, ðernetif->handle, NULL, 0U);
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_linkinput: RxFrameError\n"));
|
||||
|
||||
LINK_STATS_INC(link.drop);
|
||||
MIB2_STATS_NETIF_INC(netif, ifindiscards);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p)
|
||||
{
|
||||
err_t result;
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
struct pbuf *q;
|
||||
unsigned char *pucBuffer;
|
||||
unsigned char *pucChar;
|
||||
|
||||
LWIP_ASSERT("Output packet buffer empty", p);
|
||||
|
||||
pucBuffer = enet_get_tx_buffer(ethernetif);
|
||||
if (pucBuffer == NULL)
|
||||
{
|
||||
return ERR_BUF;
|
||||
}
|
||||
|
||||
/* Initiate transfer. */
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
|
||||
#endif
|
||||
|
||||
if (p->len == p->tot_len)
|
||||
{
|
||||
/* No pbuf chain, don't have to copy -> faster. */
|
||||
pucBuffer = (unsigned char *)p->payload;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* pbuf chain, copy into contiguous ucBuffer. */
|
||||
if (p->tot_len > ENET_FRAME_MAX_FRAMELEN)
|
||||
{
|
||||
return ERR_BUF;
|
||||
}
|
||||
else
|
||||
{
|
||||
pucChar = pucBuffer;
|
||||
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
/* Send the data from the pbuf to the interface, one pbuf at a
|
||||
time. The size of the data in each pbuf is kept in the ->len
|
||||
variable. */
|
||||
/* send data from(q->payload, q->len); */
|
||||
memcpy(pucChar, q->payload, q->len);
|
||||
pucChar += q->len;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Send frame. */
|
||||
result = enet_send_frame(ethernetif, pucBuffer, p->tot_len);
|
||||
|
||||
MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len);
|
||||
if (((u8_t *)p->payload)[0] & 1)
|
||||
{
|
||||
/* broadcast or multicast packet*/
|
||||
MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* unicast packet */
|
||||
MIB2_STATS_NETIF_INC(netif, ifoutucastpkts);
|
||||
}
|
||||
/* increase ifoutdiscards or ifouterrors on error */
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||||
#endif
|
||||
|
||||
LINK_STATS_INC(link.xmit);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* Should be called at the beginning of the program to set up the
|
||||
* first network interface. It calls the function ethernetif_init() to do the
|
||||
* actual setup of the hardware.
|
||||
*
|
||||
* This function should be passed as a parameter to netif_add().
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @return ERR_OK if the loopif is initialized
|
||||
* ERR_MEM if private data couldn't be allocated
|
||||
* any other err_t on error
|
||||
*/
|
||||
err_t ethernetif0_init(struct netif *netif)
|
||||
{
|
||||
static struct ethernetif ethernetif_0;
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
SDK_ALIGN(static rx_buffer_t rxDataBuff_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
SDK_ALIGN(static tx_buffer_t txDataBuff_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
|
||||
ethernetif_0.RxBuffDescrip = &(rxBuffDescrip_0[0]);
|
||||
ethernetif_0.TxBuffDescrip = &(txBuffDescrip_0[0]);
|
||||
ethernetif_0.RxDataBuff = &(rxDataBuff_0[0]);
|
||||
ethernetif_0.TxDataBuff = &(txDataBuff_0[0]);
|
||||
|
||||
return ethernetif_init(netif, ðernetif_0, 0U, (ethernetif_config_t *)netif->state);
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 1)
|
||||
/**
|
||||
* Should be called at the beginning of the program to set up the
|
||||
* second network interface. It calls the function ethernetif_init() to do the
|
||||
* actual setup of the hardware.
|
||||
*
|
||||
* This function should be passed as a parameter to netif_add().
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @return ERR_OK if the loopif is initialized
|
||||
* ERR_MEM if private data couldn't be allocated
|
||||
* any other err_t on error
|
||||
*/
|
||||
err_t ethernetif1_init(struct netif *netif)
|
||||
{
|
||||
static struct ethernetif ethernetif_1;
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_1[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
SDK_ALIGN(static rx_buffer_t rxDataBuff_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
SDK_ALIGN(static tx_buffer_t txDataBuff_1[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
|
||||
ethernetif_1.RxBuffDescrip = &(rxBuffDescrip_1[0]);
|
||||
ethernetif_1.TxBuffDescrip = &(txBuffDescrip_1[0]);
|
||||
ethernetif_1.RxDataBuff = &(rxDataBuff_1[0]);
|
||||
ethernetif_1.TxDataBuff = &(txDataBuff_1[0]);
|
||||
|
||||
return ethernetif_init(netif, ðernetif_1, 1U, (ethernetif_config_t *)netif->state);
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */
|
||||
960
Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_lpc.c
Executable file
960
Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/enet_ethernetif_lpc.c
Executable file
|
|
@ -0,0 +1,960 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file enet_ethernetif_lpc.c
|
||||
* @brief ethernet drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/def.h"
|
||||
#include "lwip/mem.h"
|
||||
#include "lwip/pbuf.h"
|
||||
#include "lwip/stats.h"
|
||||
#include "lwip/snmp.h"
|
||||
#include "lwip/sys.h"
|
||||
#include "lwip/ethip6.h"
|
||||
#include "netif/etharp.h"
|
||||
#include "netif/ppp/pppoe.h"
|
||||
#include "lwip/igmp.h"
|
||||
#include "lwip/mld6.h"
|
||||
|
||||
//#if !NO_SYS
|
||||
//#include "FreeRTOS.h"
|
||||
//#include "event_groups.h"
|
||||
//#include "lwip/tcpip.h"
|
||||
//#endif /* !NO_SYS */
|
||||
|
||||
#include "enet_ethernetif.h"
|
||||
#include "enet_ethernetif_priv.h"
|
||||
|
||||
#include "fsl_enet.h"
|
||||
#include "fsl_phy.h"
|
||||
|
||||
//#if MEM_ALIGNMENT != FSL_ENET_BUFF_ALIGNMENT
|
||||
///* These two has to match for zero-copy functionality */
|
||||
//#error "MEM_ALIGNMENT != FSL_ENET_BUFF_ALIGNMENT"
|
||||
//#endif /* MEM_ALIGNMENT != FSL_ENET_BUFF_ALIGNMENT */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Used to wrap received data in a pbuf to be passed into lwIP
|
||||
* without copying.
|
||||
* Once last reference is released, RX descriptor will be returned to DMA.
|
||||
*/
|
||||
typedef struct rx_pbuf_wrapper
|
||||
{
|
||||
struct pbuf_custom p; /*!< Pbuf wrapper. Has to be first. */
|
||||
enet_rx_bd_struct_t* rxDesc; /*!< Descriptor holding the data. */
|
||||
struct ethernetif *ethernetif; /*!< Ethernet interface context data. */
|
||||
volatile bool ownedByLwip; /*!< If true, descriptor cannot be reused by DMA yet. */
|
||||
} rx_pbuf_wrapper_t;
|
||||
|
||||
/*!
|
||||
* @brief Helper struct to hold private data used to operate
|
||||
* your ethernet interface.
|
||||
*/
|
||||
struct ethernetif
|
||||
{
|
||||
ENET_Type *base;
|
||||
enet_handle_t handle;
|
||||
#if !NO_SYS
|
||||
EventGroupHandle_t enetTransmitAccessEvent;
|
||||
EventBits_t txFlag;
|
||||
#endif /* !NO_SYS */
|
||||
enet_rx_bd_struct_t *RxBuffDescrip;
|
||||
enet_tx_bd_struct_t *TxBuffDescrip;
|
||||
rx_buffer_t *RxDataBuff;
|
||||
volatile struct pbuf *txPbufs[ENET_TXBD_NUM];
|
||||
volatile uint8_t txIdx;
|
||||
volatile uint8_t txReleaseIdx;
|
||||
rx_pbuf_wrapper_t rxPbufs[ENET_RXBD_NUM];
|
||||
uint8_t rxIdx;
|
||||
const mem_range_t *non_dma_memory;
|
||||
};
|
||||
|
||||
static void ethernetif_tx_release(struct ethernetif *ethernetif);
|
||||
static void ethernetif_rx_release(struct pbuf *p);
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* Called from ENET ISR.
|
||||
*/
|
||||
static void ethernet_callback(ENET_Type *base, enet_handle_t *handle,
|
||||
enet_event_t event, uint8_t channel, void *param)
|
||||
#if NO_SYS
|
||||
{
|
||||
struct netif *netif = (struct netif *)param;
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
|
||||
if (event == kENET_TxIntEvent)
|
||||
{
|
||||
ethernetif_tx_release(ethernetif);
|
||||
}
|
||||
}
|
||||
#else
|
||||
{
|
||||
struct netif *netif = (struct netif *)param;
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
BaseType_t xResult;
|
||||
|
||||
switch (event)
|
||||
{
|
||||
case kENET_RxIntEvent:
|
||||
ethernetif_input(netif);
|
||||
break;
|
||||
case kENET_TxIntEvent:
|
||||
{
|
||||
portBASE_TYPE taskToWake = pdFALSE;
|
||||
|
||||
ethernetif_tx_release(ethernetif);
|
||||
|
||||
#ifdef __CA7_REV
|
||||
if (SystemGetIRQNestingLevel())
|
||||
#else
|
||||
if (__get_IPSR())
|
||||
#endif
|
||||
{
|
||||
xResult = xEventGroupSetBitsFromISR(
|
||||
ethernetif->enetTransmitAccessEvent,
|
||||
ethernetif->txFlag, &taskToWake);
|
||||
if ((pdPASS == xResult) && (pdTRUE == taskToWake))
|
||||
{
|
||||
portYIELD_FROM_ISR(taskToWake);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xEventGroupSetBits(ethernetif->enetTransmitAccessEvent,
|
||||
ethernetif->txFlag);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* NO_SYS */
|
||||
|
||||
#if LWIP_IPV4 && LWIP_IGMP
|
||||
err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group,
|
||||
enum netif_mac_filter_action action)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
err_t result;
|
||||
|
||||
switch (action)
|
||||
{
|
||||
case IGMP_ADD_MAC_FILTER:
|
||||
/* LPC ENET does not accept multicast selectively,
|
||||
* so all multicast has to be passed through. */
|
||||
ENET_AcceptAllMulticast(ethernetif->base);
|
||||
result = ERR_OK;
|
||||
break;
|
||||
case IGMP_DEL_MAC_FILTER:
|
||||
/*
|
||||
* Moves the ENET device from a multicast group.
|
||||
* Since we don't keep track of which multicast groups
|
||||
* are still to enabled, the call is commented out.
|
||||
*/
|
||||
/* ENET_RejectAllMulticast(ethernetif->base); */
|
||||
result = ERR_OK;
|
||||
break;
|
||||
default:
|
||||
result = ERR_IF;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if LWIP_IPV6 && LWIP_IPV6_MLD
|
||||
err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group,
|
||||
enum netif_mac_filter_action action)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
err_t result;
|
||||
|
||||
switch (action)
|
||||
{
|
||||
case NETIF_ADD_MAC_FILTER:
|
||||
/* LPC ENET does not accept multicast selectively,
|
||||
* so all multicast has to be passed through. */
|
||||
ENET_AcceptAllMulticast(ethernetif->base);
|
||||
result = ERR_OK;
|
||||
break;
|
||||
case NETIF_DEL_MAC_FILTER:
|
||||
/*
|
||||
* Moves the ENET device from a multicast group.
|
||||
* Since we don't keep track of which multicast groups
|
||||
* are still to enabled, the call is commented out.
|
||||
*/
|
||||
/* ENET_RejectAllMulticast(ethernetif->base); */
|
||||
result = ERR_OK;
|
||||
break;
|
||||
default:
|
||||
result = ERR_IF;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Gets the RX descriptor by its index.
|
||||
*/
|
||||
static inline enet_rx_bd_struct_t *ethernetif_get_rx_desc(
|
||||
struct ethernetif *ethernetif,
|
||||
uint32_t index)
|
||||
{
|
||||
return &(ethernetif->RxBuffDescrip[index]);
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the TX descriptor by its index.
|
||||
*/
|
||||
static inline enet_tx_bd_struct_t *ethernetif_get_tx_desc(
|
||||
struct ethernetif *ethernetif,
|
||||
uint32_t index)
|
||||
{
|
||||
return &(ethernetif->TxBuffDescrip[index]);
|
||||
}
|
||||
|
||||
/**
|
||||
* Initializes ENET driver.
|
||||
*/
|
||||
void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif,
|
||||
const ethernetif_config_t *ethernetifConfig)
|
||||
{
|
||||
enet_config_t config;
|
||||
uint32_t sysClock;
|
||||
enet_buffer_config_t buffCfg[ENET_RING_NUM];
|
||||
uint32_t rxBufferStartAddr[ENET_RXBD_NUM];
|
||||
uint32_t i;
|
||||
|
||||
/* calculate start addresses of all rx buffers */
|
||||
for (i = 0; i < ENET_RXBD_NUM; i++)
|
||||
{
|
||||
rxBufferStartAddr[i] = (uint32_t)&(ethernetif->RxDataBuff[i][ETH_PAD_SIZE]);
|
||||
}
|
||||
|
||||
/* prepare the buffer configuration. */
|
||||
buffCfg[0].rxRingLen = ENET_RXBD_NUM; /* The length of receive buffer descriptor ring. */
|
||||
buffCfg[0].txRingLen = ENET_TXBD_NUM; /* The length of transmit buffer descriptor ring. */
|
||||
buffCfg[0].txDescStartAddrAlign = ethernetif_get_tx_desc(ethernetif, 0U); /* Aligned transmit descriptor start address. */
|
||||
buffCfg[0].txDescTailAddrAlign = ethernetif_get_tx_desc(ethernetif, 0U); /* Aligned transmit descriptor tail address. */
|
||||
buffCfg[0].rxDescStartAddrAlign = ethernetif_get_rx_desc(ethernetif, 0U); /* Aligned receive descriptor start address. */
|
||||
buffCfg[0].rxDescTailAddrAlign = ethernetif_get_rx_desc(ethernetif, ENET_RXBD_NUM); /* Aligned receive descriptor tail address. */
|
||||
buffCfg[0].rxBufferStartAddr = rxBufferStartAddr; /* Start addresses of the rx buffers. */
|
||||
buffCfg[0].rxBuffSizeAlign = sizeof(rx_buffer_t); /* Aligned receive data buffer size. */
|
||||
|
||||
sysClock = CLOCK_GetFreq(ethernetifConfig->clockName);
|
||||
|
||||
LWIP_ASSERT("ethernetifConfig->non_dma_memory == NULL", (ethernetifConfig->non_dma_memory != NULL));
|
||||
ethernetif->non_dma_memory = ethernetifConfig->non_dma_memory;
|
||||
|
||||
ENET_GetDefaultConfig(&config);
|
||||
config.multiqueueCfg = NULL;
|
||||
|
||||
ethernetif_phy_init(ethernetif, ethernetifConfig, &config);
|
||||
|
||||
#if !NO_SYS
|
||||
/* Create the Event for transmit busy release trigger. */
|
||||
ethernetif->enetTransmitAccessEvent = xEventGroupCreate();
|
||||
ethernetif->txFlag = 0x1;
|
||||
#endif /* !NO_SYS */
|
||||
NVIC_SetPriority(ETHERNET_IRQn, ENET_PRIORITY);
|
||||
|
||||
ethernetif->txIdx = 0U;
|
||||
ethernetif->rxIdx = 0U;
|
||||
ethernetif->txReleaseIdx = 0U;
|
||||
|
||||
for (i = 0; i < ENET_RXBD_NUM; i++)
|
||||
{
|
||||
ethernetif->rxPbufs[i].p.custom_free_function = ethernetif_rx_release;
|
||||
ethernetif->rxPbufs[i].rxDesc = ðernetif->RxBuffDescrip[i];
|
||||
ethernetif->rxPbufs[i].ethernetif = ethernetif;
|
||||
ethernetif->rxPbufs[i].ownedByLwip = false;
|
||||
}
|
||||
|
||||
ENET_Init(ethernetif->base, &config, netif->hwaddr, sysClock);
|
||||
|
||||
#if defined(LPC54018_SERIES)
|
||||
/* Workaround for receive issue on lpc54018 */
|
||||
ethernetif->base->MAC_FRAME_FILTER |= ENET_MAC_FRAME_FILTER_RA_MASK;
|
||||
#endif
|
||||
|
||||
/* Create the handler. */
|
||||
#if NO_SYS
|
||||
ENET_EnableInterrupts(ethernetif->base, kENET_DmaTx);
|
||||
#else
|
||||
ENET_EnableInterrupts(ethernetif->base, kENET_DmaTx | kENET_DmaRx);
|
||||
#endif /* NO_SYS */
|
||||
ENET_CreateHandler(ethernetif->base, ðernetif->handle, &config,
|
||||
&buffCfg[0], ethernet_callback, netif);
|
||||
|
||||
ENET_DescriptorInit(ethernetif->base, &config, &buffCfg[0]);
|
||||
|
||||
/* Active TX/RX. */
|
||||
ENET_StartRxTx(ethernetif->base, 1, 1);
|
||||
}
|
||||
|
||||
ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif)
|
||||
{
|
||||
return &(ethernetif->base);
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the ENET instance index from its base address.
|
||||
*/
|
||||
static uint32_t ethernetif_get_enet_idx(ENET_Type *base)
|
||||
{
|
||||
static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
|
||||
uint32_t instance;
|
||||
|
||||
for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++)
|
||||
{
|
||||
if (s_enetBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
LWIP_ASSERT("Cannot find ENET instance index from its base address.",
|
||||
instance < FSL_FEATURE_SOC_LPC_ENET_COUNT);
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sends (part of) a frame via ENET.
|
||||
* TODO: Since ENET_SendFrame() could not be used, some functionality it does
|
||||
* is missing here for now (channel selection depending on AVB content,
|
||||
* timestamping.
|
||||
*/
|
||||
static void ethernetif_send_buffer(struct ethernetif *ethernetif,
|
||||
unsigned char *data,
|
||||
const uint32_t length,
|
||||
struct pbuf *p_to_release,
|
||||
enet_desc_flag flag)
|
||||
{
|
||||
static const IRQn_Type s_enetIrqId[] = ENET_IRQS;
|
||||
enet_tx_bd_struct_t *txDesc = ethernetif_get_tx_desc(ethernetif,
|
||||
ethernetif->txIdx);
|
||||
ethernetif->txPbufs[ethernetif->txIdx] = p_to_release;
|
||||
ethernetif->txIdx = (ethernetif->txIdx + 1) % ENET_TXBD_NUM;
|
||||
|
||||
/* Prepare the descriptor for transmit. */
|
||||
txDesc->buff1Addr = (uint32_t)data;
|
||||
txDesc->buff2Addr = (uint32_t)NULL;
|
||||
txDesc->buffLen =
|
||||
ENET_TXDESCRIP_RD_BL1(length) | ENET_TXDESCRIP_RD_IOC_MASK;
|
||||
|
||||
txDesc->controlStat =
|
||||
ENET_TXDESCRIP_RD_FL(length) | ENET_TXDESCRIP_RD_LDFD(flag);
|
||||
if ((flag & kENET_FirstFlagOnly) == 0)
|
||||
{
|
||||
/*
|
||||
* Submit to DMA if not the first descriptor in chain.
|
||||
* All the descriptors have to be prepared before the first one
|
||||
* is flagged for DMA and transfer starts. ENET could output invalid
|
||||
* frames otherwise (the exception is Store and Forward mode, where
|
||||
* delays between preparing of descriptors does not matter).
|
||||
*/
|
||||
txDesc->controlStat |= ENET_TXDESCRIP_RD_OWN_MASK;
|
||||
}
|
||||
|
||||
enet_tx_bd_ring_t *txBdRing = (enet_tx_bd_ring_t *)
|
||||
ðernetif->handle.txBdRing[0];
|
||||
|
||||
/*
|
||||
* Increment txDescUsed.
|
||||
* Without this, callback would not fire from ENET ISR on finished TX.
|
||||
* This is kind of a hack. Alternative could be to define
|
||||
* void ETHERNET_DriverIRQHandler(void) and handle IRQs completely
|
||||
* in this file.
|
||||
*/
|
||||
DisableIRQ(s_enetIrqId[ethernetif_get_enet_idx(ethernetif->base)]);
|
||||
txBdRing->txDescUsed++;
|
||||
EnableIRQ(s_enetIrqId[ethernetif_get_enet_idx(ethernetif->base)]);
|
||||
}
|
||||
|
||||
/**
|
||||
* Reclaims exactly one TX descriptor after its data has been sent out.
|
||||
* Then the descriptor can be used by application to prepare next data to send.
|
||||
*/
|
||||
static void ethernetif_tx_release(struct ethernetif *ethernetif)
|
||||
{
|
||||
LWIP_ASSERT("Attempt to release more TX buffers than acquired.",
|
||||
ethernetif->txIdx != ethernetif->txReleaseIdx);
|
||||
enet_tx_bd_struct_t *txDesc
|
||||
= ðernetif->TxBuffDescrip[ethernetif->txReleaseIdx];
|
||||
LWIP_ASSERT("TX buffer still owned by DMA.",
|
||||
!ENET_IsTxDescriptorDmaOwn(txDesc));
|
||||
|
||||
struct pbuf *p = (struct pbuf *)
|
||||
ethernetif->txPbufs[ethernetif->txReleaseIdx];
|
||||
if (p != NULL)
|
||||
{
|
||||
#if ETH_PAD_SIZE
|
||||
/* Reclaim the padding, force because it may be REF pbuf. */
|
||||
pbuf_header_force(p, ETH_PAD_SIZE);
|
||||
#endif
|
||||
|
||||
#if NO_SYS
|
||||
#if defined(LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT) && LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
|
||||
pbuf_free(p);
|
||||
#else
|
||||
#error "Bare metal requires LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT=1 because pbuf_free() is being called from an ISR"
|
||||
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
||||
#else
|
||||
if (pbuf_free_callback(p) != ERR_OK)
|
||||
{
|
||||
#if defined(LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT) && LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
|
||||
pbuf_free(p);
|
||||
#else
|
||||
LWIP_ASSERT("Failed to enqueue pbuf deallocation on tcpip_thread",
|
||||
0);
|
||||
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
||||
}
|
||||
#endif /* NO_SYS */
|
||||
|
||||
ethernetif->txPbufs[ethernetif->txReleaseIdx] = NULL;
|
||||
}
|
||||
|
||||
ethernetif->txReleaseIdx = (ethernetif->txReleaseIdx + 1) % ENET_TXBD_NUM;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reclaims RX descriptor which holds the p's buffer after p is no longer used
|
||||
* by the application / lwIP. The DMA can receive new data into
|
||||
* the descriptor's buffer then.
|
||||
* Note that RX buffers may be freed by lwIP out of the order in which they were
|
||||
* passed to lwIP. Therefore there may be spaces between the RX descriptors
|
||||
* flagged as owned by DMA and DMA could still wait until it's actual position
|
||||
* is released.
|
||||
*/
|
||||
static void ethernetif_rx_release(struct pbuf *p)
|
||||
{
|
||||
SYS_ARCH_DECL_PROTECT(old_level);
|
||||
rx_pbuf_wrapper_t *wrapper = (rx_pbuf_wrapper_t *)p;
|
||||
#if NO_SYS
|
||||
bool intEnable = false;
|
||||
#else
|
||||
bool intEnable = true;
|
||||
#endif /* NO_SYS */
|
||||
|
||||
SYS_ARCH_PROTECT(old_level);
|
||||
|
||||
wrapper->ownedByLwip = false;
|
||||
|
||||
/* Update the receive buffer descriptor. */
|
||||
ENET_UpdateRxDescriptor(wrapper->rxDesc, NULL, NULL, intEnable, false);
|
||||
ENET_UpdateRxDescriptorTail(wrapper->ethernetif->base, 0U,
|
||||
(uint32_t)ethernetif_get_rx_desc(wrapper->ethernetif, ENET_RXBD_NUM));
|
||||
|
||||
SYS_ARCH_UNPROTECT(old_level);
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the length of a received frame (if there is some).
|
||||
*/
|
||||
static status_t ethernetif_get_rx_frame_size(struct ethernetif *ethernetif,
|
||||
uint32_t *length)
|
||||
{
|
||||
uint8_t index = ethernetif->rxIdx;
|
||||
enet_rx_bd_struct_t *rxDesc;
|
||||
uint32_t rxControl;
|
||||
|
||||
/* Reset the length to zero. */
|
||||
*length = 0;
|
||||
|
||||
do
|
||||
{
|
||||
rxDesc = ethernetif_get_rx_desc(ethernetif, index);
|
||||
rxControl = ENET_GetRxDescriptor(rxDesc);
|
||||
|
||||
if ((rxControl & ENET_RXDESCRIP_WR_OWN_MASK)
|
||||
|| (ethernetif->rxPbufs[index].ownedByLwip))
|
||||
{
|
||||
/*
|
||||
* Buffer descriptor is owned by DMA or lwIP.
|
||||
* We haven't received any complete frame yet.
|
||||
*/
|
||||
return kStatus_ENET_RxFrameEmpty;
|
||||
}
|
||||
|
||||
/* Application owns the buffer descriptor. */
|
||||
if (rxControl & ENET_RXDESCRIP_WR_LD_MASK)
|
||||
{
|
||||
/* It's last descriptor of a frame, get its status or length. */
|
||||
if (rxControl & ENET_RXDESCRIP_WR_ERRSUM_MASK)
|
||||
{
|
||||
return kStatus_ENET_RxFrameError;
|
||||
}
|
||||
else
|
||||
{
|
||||
*length = rxControl & ENET_RXDESCRIP_WR_PACKETLEN_MASK;
|
||||
return kStatus_Success;
|
||||
}
|
||||
}
|
||||
|
||||
index = (index + 1U) % ENET_RXBD_NUM;
|
||||
} while (index != ethernetif->rxIdx);
|
||||
|
||||
/*
|
||||
* All descriptors have data but the end of the frame not detected.
|
||||
*/
|
||||
return kStatus_ENET_RxFrameError;
|
||||
}
|
||||
|
||||
/**
|
||||
* Drops (releases) receive descriptors until the last one of a frame is reached
|
||||
* or drops entire descriptor ring when all descriptors have data but end
|
||||
* of the frame not detected among them.
|
||||
* Function can be called only after ethernetif_get_rx_frame_size() indicates
|
||||
* that there actually is a frame error or a received frame.
|
||||
*/
|
||||
static void ethernetif_drop_frame(struct ethernetif *ethernetif)
|
||||
{
|
||||
#if NO_SYS
|
||||
bool intEnable = false;
|
||||
#else
|
||||
bool intEnable = true;
|
||||
#endif /* NO_SYS */
|
||||
|
||||
enet_rx_bd_struct_t *rxDesc;
|
||||
uint8_t index = ethernetif->rxIdx;
|
||||
uint32_t rxControl;
|
||||
|
||||
do
|
||||
{
|
||||
rxDesc = ethernetif_get_rx_desc(ethernetif, ethernetif->rxIdx);
|
||||
ethernetif->rxIdx = (ethernetif->rxIdx + 1U) % ENET_RXBD_NUM;
|
||||
rxControl = ENET_GetRxDescriptor(rxDesc);
|
||||
|
||||
/* Update the receive buffer descriptor. */
|
||||
ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, intEnable, false);
|
||||
|
||||
/* Find the last buffer descriptor for the frame. */
|
||||
if (rxControl & ENET_RXDESCRIP_WR_LD_MASK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
} while (ethernetif->rxIdx != index);
|
||||
|
||||
ENET_UpdateRxDescriptorTail(ethernetif->base, 0U,
|
||||
(uint32_t)ethernetif_get_rx_desc(ethernetif, ENET_RXBD_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* Reads a received frame - wraps its descriptor buffer(s) into a pbuf
|
||||
* or a pbuf chain, flag descriptors as owned by lwIP and returns the pbuf.
|
||||
* The descriptors are returned to DMA only after the returned pbuf is released.
|
||||
* Function can be called only after ethernetif_get_rx_frame_size() indicates
|
||||
* that there actually is a received frame.
|
||||
*/
|
||||
static struct pbuf *ethernetif_read_frame(struct ethernetif *ethernetif,
|
||||
uint32_t length)
|
||||
{
|
||||
rx_pbuf_wrapper_t *wrapper;
|
||||
enet_rx_bd_struct_t *rxDesc;
|
||||
uint32_t rxControl;
|
||||
uint32_t len = 0;
|
||||
struct pbuf *p = NULL;
|
||||
struct pbuf *q = NULL;
|
||||
|
||||
do
|
||||
{
|
||||
wrapper = ðernetif->rxPbufs[ethernetif->rxIdx];
|
||||
wrapper->ownedByLwip = true;
|
||||
ethernetif->rxIdx = (ethernetif->rxIdx + 1U) % ENET_RXBD_NUM;
|
||||
|
||||
rxDesc = wrapper->rxDesc;
|
||||
rxControl = ENET_GetRxDescriptor(rxDesc);
|
||||
|
||||
len = (rxControl & ENET_RXDESCRIP_WR_PACKETLEN_MASK);
|
||||
|
||||
/* Wrap the receive buffer in pbuf. */
|
||||
if (p == NULL)
|
||||
{
|
||||
p = pbuf_alloced_custom(PBUF_RAW, len, PBUF_REF, &wrapper->p,
|
||||
(void *)rxDesc->buff1Addr, len);
|
||||
LWIP_ASSERT("pbuf_alloced_custom() failed", p);
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
/* Add the padding header, force because it is a REF type buffer. */
|
||||
pbuf_header_force(p, ETH_PAD_SIZE);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
q = pbuf_alloced_custom(PBUF_RAW, len, PBUF_REF, &wrapper->p,
|
||||
(void *)rxDesc->buff1Addr, len);
|
||||
LWIP_ASSERT("pbuf_alloced_custom() failed", q);
|
||||
|
||||
pbuf_cat(p, q);
|
||||
}
|
||||
} while (((rxControl & ENET_RXDESCRIP_WR_LD_MASK) == 0U)
|
||||
&& (p->tot_len < length));
|
||||
|
||||
MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len);
|
||||
if (((u8_t *)p->payload)[0] & 1)
|
||||
{
|
||||
/* broadcast or multicast packet */
|
||||
MIB2_STATS_NETIF_INC(netif, ifinnucastpkts);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* unicast packet */
|
||||
MIB2_STATS_NETIF_INC(netif, ifinucastpkts);
|
||||
}
|
||||
|
||||
LINK_STATS_INC(link.recv);
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
/**
|
||||
* Attempts to read a frame from ENET and returns it wrapped in a pbuf
|
||||
* or returns NULL when no frame is received. Discards invalid frames.
|
||||
*/
|
||||
struct pbuf *ethernetif_linkinput(struct netif *netif)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
struct pbuf *p = NULL;
|
||||
uint32_t len;
|
||||
status_t status;
|
||||
|
||||
/* Obtain the size of the packet and put it into the "len" variable. */
|
||||
status = ethernetif_get_rx_frame_size(ethernetif, &len);
|
||||
|
||||
if (status == kStatus_Success)
|
||||
{
|
||||
p = ethernetif_read_frame(ethernetif, len);
|
||||
|
||||
if (p == NULL)
|
||||
{
|
||||
/* Could not initialise wrapper pbuf(s) - drop the frame. */
|
||||
ethernetif_drop_frame(ethernetif);
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG,
|
||||
("ethernetif_linkinput: Fail to allocate new memory space\n"));
|
||||
|
||||
LINK_STATS_INC(link.memerr);
|
||||
LINK_STATS_INC(link.drop);
|
||||
MIB2_STATS_NETIF_INC(netif, ifindiscards);
|
||||
}
|
||||
}
|
||||
else if (status == kStatus_ENET_RxFrameError)
|
||||
{
|
||||
/* Update the received buffer when error happened. */
|
||||
ethernetif_drop_frame(ethernetif);
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_linkinput: RxFrameError\n"));
|
||||
|
||||
LINK_STATS_INC(link.drop);
|
||||
MIB2_STATS_NETIF_INC(netif, ifindiscards);
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns the number of TX descriptors which could be used by lwIP/application
|
||||
* to put new TX data into.
|
||||
*
|
||||
* The max number of free descriptors is (ENET_TXBD_NUM - 1), that is when
|
||||
* ethernetif->txReleaseIdx == ethernetif->txIdx. Having the capacity decreased
|
||||
* by one allows to avoid locking: txReleaseIdx is advanced only from ISR
|
||||
* and txIdx from tcpip_thread/main loop. Should we use full capacity and have
|
||||
* some variable to indicate between the "all buffers are free" vs. "all buffers
|
||||
* are used" situation, it would be manipulated from two contexts hence locking
|
||||
* would be needed.
|
||||
*/
|
||||
static inline int ethernetif_avail_tx_descs(struct ethernetif *ethernetif)
|
||||
{
|
||||
return (ethernetif->txReleaseIdx + ENET_TXBD_NUM - 1 - ethernetif->txIdx)
|
||||
% ENET_TXBD_NUM;
|
||||
}
|
||||
|
||||
/**
|
||||
* Attempts to output a frame from ENET. The function avoids copying of
|
||||
* p's payload when possible. In such situation it increases p's reference count
|
||||
* and decreases it (and possibly releases p) after the payload is sent.
|
||||
*/
|
||||
err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p)
|
||||
{
|
||||
struct ethernetif *ethernetif = netif->state;
|
||||
struct pbuf *q;
|
||||
struct pbuf *pbuf_to_free = NULL;
|
||||
struct pbuf *p_copy;
|
||||
uint16_t clen;
|
||||
bool copy = false;
|
||||
const mem_range_t *non_dma_memory;
|
||||
uint8_t *dst;
|
||||
uint32_t cnt = 0;
|
||||
uint8_t first_idx;
|
||||
uint32_t tail_address;
|
||||
|
||||
LWIP_ASSERT("Output packet buffer empty", p);
|
||||
|
||||
if ((p->tot_len - ETH_PAD_SIZE) > ENET_FRAME_MAX_FRAMELEN)
|
||||
{
|
||||
return ERR_BUF;
|
||||
}
|
||||
|
||||
clen = pbuf_clen(p);
|
||||
|
||||
/* Check if relocation is needed */
|
||||
|
||||
if (clen > (ENET_TXBD_NUM - 1))
|
||||
{
|
||||
/* Pbuf chain is too long to be prepared for DMA at once. */
|
||||
copy = true;
|
||||
}
|
||||
|
||||
for (q = p; (q != NULL) && !copy; q = q->next)
|
||||
{
|
||||
/*
|
||||
* Check if payload is aligned is not desired: lwIP creates RAM pbufs
|
||||
* in a way that the data coming after the headers are aligned, but not
|
||||
* the beginning of the ethernet header. LPC ENET DMA will read from
|
||||
* the aligned address, which is ok, because there is additional space
|
||||
* before the headers to make up for alignment - so DMA will not read
|
||||
* from invalid address or unrelated data.
|
||||
*/
|
||||
|
||||
/* Check payload address is usable by ENET DMA */
|
||||
for (non_dma_memory = ethernetif->non_dma_memory;
|
||||
(non_dma_memory->start != 0U)
|
||||
|| (non_dma_memory->end != 0U); non_dma_memory++)
|
||||
{
|
||||
if ((q->payload >= (void *) non_dma_memory->start)
|
||||
&& (q->payload < (void *) non_dma_memory->end))
|
||||
{
|
||||
copy = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (copy)
|
||||
{
|
||||
/* Pbuf needs to be copied. */
|
||||
|
||||
p_copy = pbuf_alloc(PBUF_RAW, (uint16_t) p->tot_len, PBUF_POOL);
|
||||
if (p_copy == NULL)
|
||||
{
|
||||
return ERR_MEM;
|
||||
}
|
||||
|
||||
dst = (uint8_t *) p_copy->payload;
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
LWIP_ASSERT("Copied bytes would exceed p->tot_len",
|
||||
(q->len + dst - (uint8_t *) p_copy->payload) <= p->tot_len);
|
||||
memcpy(dst, (uint8_t *)q->payload, q->len);
|
||||
dst += q->len;
|
||||
}
|
||||
LWIP_ASSERT("Copied bytes != p->tot_len",
|
||||
(dst - (uint8_t *) p_copy->payload) == p->tot_len);
|
||||
p_copy->len = p_copy->tot_len = p->tot_len;
|
||||
|
||||
p = p_copy;
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* Increase reference count so p is released only after it is sent.
|
||||
* For copied pbuf, ref is already 1 after pbuf_alloc().
|
||||
*/
|
||||
pbuf_ref(p);
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait until the sufficient number of descriptors are available,
|
||||
* as we have to start the transfer of the first buffer only
|
||||
* after all buffers in chain are prepared.
|
||||
*/
|
||||
while (ethernetif_avail_tx_descs(ethernetif) < clen)
|
||||
{
|
||||
#if !NO_SYS
|
||||
xEventGroupWaitBits(ethernetif->enetTransmitAccessEvent,
|
||||
ethernetif->txFlag, pdTRUE, (BaseType_t) false,
|
||||
portMAX_DELAY);
|
||||
#endif /* !NO_SYS */
|
||||
cnt++;
|
||||
if (cnt >= ENET_TIMEOUT)
|
||||
{
|
||||
return ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
/* Drop the padding. */
|
||||
pbuf_header(p, -ETH_PAD_SIZE);
|
||||
#endif
|
||||
|
||||
/* Initiate transfer. */
|
||||
|
||||
first_idx = ethernetif->txIdx;
|
||||
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
enet_desc_flag flag = kENET_MiddleFlag;
|
||||
pbuf_to_free = NULL;
|
||||
|
||||
if (q == p)
|
||||
{
|
||||
flag |= kENET_FirstFlagOnly;
|
||||
}
|
||||
|
||||
if (q->next == NULL)
|
||||
{
|
||||
flag |= kENET_LastFlagOnly;
|
||||
|
||||
/* On last TX interrupt, free pbuf chain. */
|
||||
pbuf_to_free = p;
|
||||
}
|
||||
|
||||
ethernetif_send_buffer(ethernetif, q->payload, q->len, pbuf_to_free,
|
||||
flag);
|
||||
}
|
||||
|
||||
/* All pbufs from chain are prepared, allow DMA to access the first one. */
|
||||
ethernetif_get_tx_desc(ethernetif, first_idx)->controlStat |=
|
||||
ENET_TXDESCRIP_RD_OWN_MASK;
|
||||
|
||||
/* Update the transmit tail address. */
|
||||
if (ethernetif->txIdx == 0U)
|
||||
{
|
||||
tail_address = (uint32_t)ethernetif_get_tx_desc(ethernetif,
|
||||
ENET_TXBD_NUM);
|
||||
}
|
||||
else
|
||||
{
|
||||
tail_address = (uint32_t)ethernetif_get_tx_desc(ethernetif,
|
||||
ethernetif->txIdx);
|
||||
}
|
||||
ENET_UpdateTxDescriptorTail(ethernetif->base, 0, tail_address);
|
||||
|
||||
MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len);
|
||||
if (((uint8_t *)p->payload)[0] & 1)
|
||||
{
|
||||
/* broadcast or multicast packet */
|
||||
MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* unicast packet */
|
||||
MIB2_STATS_NETIF_INC(netif, ifoutucastpkts);
|
||||
}
|
||||
LINK_STATS_INC(link.xmit);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Should be called at the beginning of the program to set up the
|
||||
* first network interface. It calls the function ethernetif_init() to do the
|
||||
* actual setup of the hardware.
|
||||
*
|
||||
* This function should be passed as a parameter to netif_add().
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @return ERR_OK if the loopif is initialized
|
||||
* ERR_MEM if private data couldn't be allocated
|
||||
* any other err_t on error
|
||||
*/
|
||||
err_t ethernetif0_init(struct netif *netif)
|
||||
{
|
||||
static struct ethernetif ethernetif_0;
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_0[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
SDK_ALIGN(static rx_buffer_t rxDataBuff_0[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
|
||||
ethernetif_0.RxBuffDescrip = &(rxBuffDescrip_0[0]);
|
||||
ethernetif_0.TxBuffDescrip = &(txBuffDescrip_0[0]);
|
||||
ethernetif_0.RxDataBuff = &(rxDataBuff_0[0]);
|
||||
|
||||
return ethernetif_init(netif, ðernetif_0, 0U, (ethernetif_config_t *)netif->state);
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 1)
|
||||
/**
|
||||
* Should be called at the beginning of the program to set up the
|
||||
* second network interface. It calls the function ethernetif_init() to do the
|
||||
* actual setup of the hardware.
|
||||
*
|
||||
* This function should be passed as a parameter to netif_add().
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @return ERR_OK if the loopif is initialized
|
||||
* ERR_MEM if private data couldn't be allocated
|
||||
* any other err_t on error
|
||||
*/
|
||||
err_t ethernetif1_init(struct netif *netif)
|
||||
{
|
||||
static struct ethernetif ethernetif_1;
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip_1[ENET_TXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
SDK_ALIGN(static rx_buffer_t rxDataBuff_1[ENET_RXBD_NUM], FSL_ENET_BUFF_ALIGNMENT);
|
||||
|
||||
ethernetif_1.RxBuffDescrip = &(rxBuffDescrip_1[0]);
|
||||
ethernetif_1.TxBuffDescrip = &(txBuffDescrip_1[0]);
|
||||
ethernetif_1.RxDataBuff = &(rxDataBuff_1[0]);
|
||||
|
||||
return ethernetif_init(netif, ðernetif_1, 1U, (ethernetif_config_t *)netif->state);
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,2 @@
|
|||
SRC_FILES := fsl_phy.c
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_phy.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Defines the timeout macro. */
|
||||
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Get the ENET instance from peripheral base address.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @return ENET instance.
|
||||
*/
|
||||
extern uint32_t ENET_GetInstance(ENET_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to enet clocks for each instance. */
|
||||
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
|
||||
{
|
||||
uint32_t bssReg;
|
||||
uint32_t counter = PHY_TIMEOUT_COUNT;
|
||||
uint32_t idReg = 0;
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t instance = ENET_GetInstance(base);
|
||||
uint32_t timeDelay;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Set SMI first. */
|
||||
CLOCK_EnableClock(s_enetClock[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
ENET_SetSMI(base, srcClock_Hz, false);
|
||||
|
||||
/* Initialization after PHY stars to work. */
|
||||
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
|
||||
{
|
||||
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
|
||||
counter --;
|
||||
}
|
||||
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Reset PHY. */
|
||||
counter = PHY_TIMEOUT_COUNT;
|
||||
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
|
||||
/* Set the negotiation. */
|
||||
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
|
||||
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
|
||||
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
|
||||
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
/* Check auto negotiation complete. */
|
||||
while (counter --)
|
||||
{
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
|
||||
if ( result == kStatus_Success)
|
||||
{
|
||||
if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
|
||||
{
|
||||
/* Wait a moment for Phy status stable. */
|
||||
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
|
||||
{
|
||||
__ASM("nop");
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_PHY_AutoNegotiateFail;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
|
||||
{
|
||||
uint32_t counter;
|
||||
|
||||
/* Clear the SMI interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
/* Starts a SMI write command. */
|
||||
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
|
||||
|
||||
/* Wait for SMI complete. */
|
||||
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
|
||||
{
|
||||
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for timeout. */
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_PHY_SMIVisitTimeout;
|
||||
}
|
||||
|
||||
/* Clear MII interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
|
||||
{
|
||||
assert(dataPtr);
|
||||
|
||||
uint32_t counter;
|
||||
|
||||
/* Clear the MII interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
/* Starts a SMI read command operation. */
|
||||
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
|
||||
|
||||
/* Wait for MII complete. */
|
||||
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
|
||||
{
|
||||
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for timeout. */
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_PHY_SMIVisitTimeout;
|
||||
}
|
||||
|
||||
/* Get data from MII register. */
|
||||
*dataPtr = ENET_ReadSMIData(base);
|
||||
|
||||
/* Clear MII interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
|
||||
{
|
||||
status_t result;
|
||||
uint32_t data = 0;
|
||||
|
||||
/* Set the loop mode. */
|
||||
if (enable)
|
||||
{
|
||||
if (mode == kPHY_LocalLoop)
|
||||
{
|
||||
if (speed == kPHY_Speed100M)
|
||||
{
|
||||
data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
|
||||
}
|
||||
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* First read the current status in control register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data | PHY_CTL1_REMOTELOOP_MASK));
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the loop mode. */
|
||||
if (mode == kPHY_LocalLoop)
|
||||
{
|
||||
/* First read the current status in control register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
data &= ~PHY_BCTL_LOOP_MASK;
|
||||
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* First read the current status in control one register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data & ~PHY_CTL1_REMOTELOOP_MASK));
|
||||
}
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
|
||||
{
|
||||
assert(status);
|
||||
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t data;
|
||||
|
||||
/* Read the basic status register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
|
||||
{
|
||||
/* link down. */
|
||||
*status = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* link up. */
|
||||
*status = true;
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
|
||||
{
|
||||
assert(duplex);
|
||||
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t data, ctlReg;
|
||||
|
||||
/* Read the control two register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
|
||||
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
|
||||
{
|
||||
/* Full duplex. */
|
||||
*duplex = kPHY_FullDuplex;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half duplex. */
|
||||
*duplex = kPHY_HalfDuplex;
|
||||
}
|
||||
|
||||
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
|
||||
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
|
||||
{
|
||||
/* 100M speed. */
|
||||
*speed = kPHY_Speed100M;
|
||||
}
|
||||
else
|
||||
{ /* 10M speed. */
|
||||
*speed = kPHY_Speed10M;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_PHY_H_
|
||||
#define _FSL_PHY_H_
|
||||
|
||||
#include "fsl_enet.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup phy_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief PHY driver version */
|
||||
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
|
||||
/*! @brief Defines the PHY registers. */
|
||||
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
|
||||
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
|
||||
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
|
||||
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
|
||||
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
|
||||
#define PHY_CONTROL1_REG 0x1FU /*!< The PHY control one register. */
|
||||
|
||||
#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
|
||||
|
||||
/*! @brief Defines the mask flag in basic control register. */
|
||||
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
|
||||
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
|
||||
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
|
||||
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
|
||||
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
|
||||
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
|
||||
#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
|
||||
|
||||
/*!@brief Defines the mask flag of operation mode in control two register*/
|
||||
#define PHY_CTL1_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
|
||||
//#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
|
||||
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */
|
||||
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */
|
||||
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */
|
||||
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */
|
||||
#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */
|
||||
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
|
||||
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
|
||||
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
|
||||
|
||||
/*! @brief Defines the mask flag in basic status register. */
|
||||
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
|
||||
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
|
||||
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
|
||||
|
||||
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
|
||||
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
|
||||
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
|
||||
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
|
||||
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
|
||||
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
|
||||
|
||||
/*! @brief Defines the PHY status. */
|
||||
enum _phy_status
|
||||
{
|
||||
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
|
||||
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
|
||||
};
|
||||
|
||||
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
|
||||
typedef enum _phy_speed
|
||||
{
|
||||
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
|
||||
kPHY_Speed100M /*!< ENET PHY 100M speed. */
|
||||
} phy_speed_t;
|
||||
|
||||
/*! @brief Defines the PHY link duplex. */
|
||||
typedef enum _phy_duplex
|
||||
{
|
||||
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
|
||||
kPHY_FullDuplex /*!< ENET PHY full duplex. */
|
||||
} phy_duplex_t;
|
||||
|
||||
/*! @brief Defines the PHY loopback mode. */
|
||||
typedef enum _phy_loop
|
||||
{
|
||||
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
|
||||
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
|
||||
} phy_loop_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name PHY Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes PHY.
|
||||
*
|
||||
* This function initialize the SMI interface and initialize PHY.
|
||||
* The SMI is the MII management interface between PHY and MAC, which should be
|
||||
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
|
||||
* @retval kStatus_Success PHY initialize success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
|
||||
*/
|
||||
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief PHY Write function. This function write data over the SMI to
|
||||
* the specified PHY register. This function is called by all PHY interfaces.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param phyReg The PHY register.
|
||||
* @param data The data written to the PHY register.
|
||||
* @retval kStatus_Success PHY write success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
|
||||
|
||||
/*!
|
||||
* @brief PHY Read function. This interface read data over the SMI from the
|
||||
* specified PHY register. This function is called by all PHY interfaces.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param phyReg The PHY register.
|
||||
* @param dataPtr The address to store the data read from the PHY register.
|
||||
* @retval kStatus_Success PHY read success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables PHY loopback.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
|
||||
* the two loopback mode should not be both set. when one loopback mode is set
|
||||
* the other one should be disabled.
|
||||
* @param speed PHY speed for loopback mode.
|
||||
* @param enable True to enable, false to disable.
|
||||
* @retval kStatus_Success PHY loopback success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief Gets the PHY link status.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param status The link up or down status of the PHY.
|
||||
* - true the link is up.
|
||||
* - false the link is down.
|
||||
* @retval kStatus_Success PHY get link status success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
|
||||
|
||||
/*!
|
||||
* @brief Gets the PHY link speed and duplex.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param speed The address of PHY link speed.
|
||||
* @param duplex The link duplex of PHY.
|
||||
* @retval kStatus_Success PHY get link speed and duplex success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_PHY_H_ */
|
||||
|
|
@ -78,6 +78,7 @@ const struct PinMask pin_mask[] =
|
|||
struct PinIrqHdr pin_irq_hdr_tab[] =
|
||||
{
|
||||
/* GPIO1 */
|
||||
{-1, 0, NONE, NONE},//1
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
|
|
@ -108,9 +109,9 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
|
|||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},//32
|
||||
/* GPIO2 */
|
||||
{-1, 0, NONE, NONE},//33
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
|
|
@ -141,9 +142,9 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
|
|||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},//64
|
||||
/* GPIO3 */
|
||||
{-1, 0, NONE, NONE},//65
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
|
|
@ -174,8 +175,7 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
|
|||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},//96
|
||||
/* GPIO4 */
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
|
|
@ -208,9 +208,9 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
|
|||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},//128
|
||||
/* GPIO5 */
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},//129
|
||||
{-1, 0, NONE, NONE},
|
||||
{-1, 0, NONE, NONE},
|
||||
};
|
||||
|
|
@ -412,7 +412,6 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
|
|||
|
||||
struct PinIndex pin_index;
|
||||
|
||||
KPrintf("Imxrt1052PinConfigure\n");
|
||||
if (GetPin(&pin_index, param->pin) < 0) {
|
||||
return ERROR;
|
||||
}
|
||||
|
|
@ -420,7 +419,6 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
|
|||
switch(param->cmd)
|
||||
{
|
||||
case GPIO_CONFIG_MODE:
|
||||
KPrintf("GpioConfigMode %u\n", param->pin);
|
||||
GpioConfigMode(param->mode, &pin_index, param->pin);
|
||||
break;
|
||||
case GPIO_IRQ_REGISTER:
|
||||
|
|
@ -583,6 +581,9 @@ static __inline void PinIrqHdr(uint32_t index_offset, uint8_t pin_start, GPIO_Ty
|
|||
|
||||
if (isr_status & (1 << i)) {
|
||||
GPIO_PortClearInterruptFlags(gpio, (1 << i));
|
||||
|
||||
__DSB();
|
||||
|
||||
pin = index_offset + i;
|
||||
if (pin_irq_hdr_tab[pin].hdr) {
|
||||
pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args);
|
||||
|
|
|
|||
|
|
@ -266,11 +266,7 @@
|
|||
#define CH438_NWR_PIN IMXRT_GET_PIN(3, 4)
|
||||
#define CH438_NRD_PIN IMXRT_GET_PIN(3, 5)
|
||||
#define CH438_ALE_PIN IMXRT_GET_PIN(3, 2)
|
||||
#define CH438_INT_PIN IMXRT_GET_PIN(3, 3)
|
||||
// #define DIR_485CH1_PIN
|
||||
// #define DIR_485CH2_PIN
|
||||
|
||||
void CH438RegTest(unsigned char num);
|
||||
#define CH438_INT_PIN IMXRT_GET_PIN(3, 3)
|
||||
|
||||
int Imxrt1052HwCh438Init(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2021 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_ethernet.h
|
||||
* @brief Adapted network software protocol stack and hardware operation functions
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-12-7
|
||||
*/
|
||||
|
||||
#ifndef __CONNECT_ETHERNET_H_
|
||||
#define __CONNECT_ETHERNET_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef sourceClock
|
||||
#define sourceClock CLOCK_GetFreq(kCLOCK_CoreSysClk)
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file enet_ethernetif.h
|
||||
* @brief ethernet drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ENET_ETHERNETIF_H
|
||||
#define ENET_ETHERNETIF_H
|
||||
|
||||
#include "lwip/err.h"
|
||||
#include "lwip/netif.h"
|
||||
#include "fsl_enet.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifndef ENET_RXBD_NUM
|
||||
#define ENET_RXBD_NUM (5)
|
||||
#endif
|
||||
#ifndef ENET_TXBD_NUM
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
|
||||
#define ENET_TXBD_NUM (5)
|
||||
#else
|
||||
#define ENET_TXBD_NUM (3)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef ENET_RXBUFF_SIZE
|
||||
#if defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
|
||||
#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN + ETH_PAD_SIZE)
|
||||
#else
|
||||
#define ENET_RXBUFF_SIZE ENET_FRAME_MAX_FRAMELEN
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef ENET_TXBUFF_SIZE
|
||||
#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
|
||||
#endif
|
||||
|
||||
#define ENET_TIMEOUT (0xFFFU)
|
||||
|
||||
/* ENET IRQ priority. Used in FreeRTOS. */
|
||||
/* Interrupt priorities. */
|
||||
#ifdef __CA7_REV
|
||||
#ifndef ENET_PRIORITY
|
||||
#define ENET_PRIORITY (21U)
|
||||
#endif
|
||||
#ifndef ENET_1588_PRIORITY
|
||||
#define ENET_1588_PRIORITY (20U)
|
||||
#endif
|
||||
#else
|
||||
#ifndef ENET_PRIORITY
|
||||
#define ENET_PRIORITY (15U)//(6U)
|
||||
#endif
|
||||
#ifndef ENET_1588_PRIORITY
|
||||
#define ENET_1588_PRIORITY (5U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Defines Ethernet Autonegotiation Timeout during initialization.
|
||||
* Set it to 0 to disable the waiting. */
|
||||
#ifndef ENET_ATONEGOTIATION_TIMEOUT
|
||||
#define ENET_ATONEGOTIATION_TIMEOUT (0xFFFU)
|
||||
#endif
|
||||
|
||||
/* Define those to better describe your network interface. */
|
||||
#define IFNAME0 'e'
|
||||
#define IFNAME1 'n'
|
||||
|
||||
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) \
|
||||
&& ((!defined(FSL_SDK_DISBLE_L2CACHE_PRESENT)) || (FSL_SDK_DISBLE_L2CACHE_PRESENT == 0))
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define FSL_CACHE_LINESIZE_MAX MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_CACHE_LINESIZE_MAX)
|
||||
#else
|
||||
#define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#endif
|
||||
#elif defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define FSL_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#else
|
||||
#define FSL_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT
|
||||
#endif
|
||||
#else
|
||||
#define FSL_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT
|
||||
#endif
|
||||
|
||||
#define ENET_RING_NUM 1U
|
||||
|
||||
typedef uint8_t rx_buffer_t[SDK_SIZEALIGN(ENET_RXBUFF_SIZE, FSL_ENET_BUFF_ALIGNMENT)];
|
||||
typedef uint8_t tx_buffer_t[SDK_SIZEALIGN(ENET_TXBUFF_SIZE, FSL_ENET_BUFF_ALIGNMENT)];
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0))
|
||||
typedef struct mem_range
|
||||
{
|
||||
uint32_t start;
|
||||
uint32_t end;
|
||||
} mem_range_t;
|
||||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
|
||||
/**
|
||||
* Helper struct to hold data for configuration of ethernet interface.
|
||||
*/
|
||||
typedef struct ethernetif_config
|
||||
{
|
||||
uint32_t phyAddress;
|
||||
clock_name_t clockName;
|
||||
uint8_t macAddress[NETIF_MAX_HWADDR_LEN];
|
||||
#if (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0))
|
||||
const mem_range_t *non_dma_memory;
|
||||
#endif /* FSL_FEATURE_SOC_LPC_ENET_COUNT */
|
||||
} ethernetif_config_t;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* This function should be passed as a parameter to netif_add()
|
||||
* if you initialize the first ENET interface.
|
||||
*/
|
||||
err_t ethernetif0_init(struct netif *netif);
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 1)) \
|
||||
|| (defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 1))
|
||||
/**
|
||||
* This function should be passed as a parameter to netif_add()
|
||||
* if you initialize the second ENET interface.
|
||||
*/
|
||||
err_t ethernetif1_init(struct netif *netif);
|
||||
#endif /* FSL_FEATURE_SOC_*_ENET_COUNT */
|
||||
|
||||
/**
|
||||
* This function should be called when a packet is ready to be read
|
||||
* from the interface.
|
||||
* It is used by bare-metal applications.
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
*/
|
||||
void ethernetif_input( struct netif *netif);
|
||||
|
||||
void ETH_BSP_Config(void);
|
||||
|
||||
int32 lwip_obtain_semaphore(struct netif *netif);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ENET_ETHERNETIF_H */
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file enet_ethernetif_priv.h
|
||||
* @brief ethernet drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ENET_ETHERNETIF_PRIV_H
|
||||
#define ENET_ETHERNETIF_PRIV_H
|
||||
|
||||
#include "lwip/err.h"
|
||||
|
||||
struct ethernetif;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
err_t ethernetif_init(struct netif *netif, struct ethernetif *ethernetif,
|
||||
const uint8_t enetIdx,
|
||||
const ethernetif_config_t *ethernetifConfig);
|
||||
|
||||
void ethernetif_enet_init(struct netif *netif, struct ethernetif *ethernetif,
|
||||
const ethernetif_config_t *ethernetifConfig);
|
||||
|
||||
void ethernetif_phy_init(struct ethernetif *ethernetif,
|
||||
const ethernetif_config_t *ethernetifConfig,
|
||||
enet_config_t *config);
|
||||
|
||||
ENET_Type **ethernetif_enet_ptr(struct ethernetif *ethernetif);
|
||||
|
||||
#if LWIP_IPV4 && LWIP_IGMP
|
||||
err_t ethernetif_igmp_mac_filter(struct netif *netif, const ip4_addr_t *group,
|
||||
enum netif_mac_filter_action action);
|
||||
#endif
|
||||
|
||||
#if LWIP_IPV6 && LWIP_IPV6_MLD
|
||||
err_t ethernetif_mld_mac_filter(struct netif *netif, const ip6_addr_t *group,
|
||||
enum netif_mac_filter_action action);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Should allocate a pbuf and transfer the bytes of the incoming
|
||||
* packet from the interface into the pbuf.
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @return a pbuf filled with the received packet (including MAC header)
|
||||
* NULL on memory error
|
||||
*/
|
||||
struct pbuf *ethernetif_linkinput(struct netif *netif);
|
||||
|
||||
/**
|
||||
* This function should do the actual transmission of the packet. The packet is
|
||||
* contained in the pbuf that is passed to the function. This pbuf
|
||||
* might be chained.
|
||||
*
|
||||
* @param netif the lwip network interface structure for this ethernetif
|
||||
* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
|
||||
* @return ERR_OK if the packet could be sent
|
||||
* an err_t value if the packet couldn't be sent
|
||||
*
|
||||
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
|
||||
* strange results. You might consider waiting for space in the DMA queue
|
||||
* to become available since the stack doesn't retry to send a packet
|
||||
* dropped because of memory failure (except for the TCP timers).
|
||||
*/
|
||||
err_t ethernetif_linkoutput(struct netif *netif, struct pbuf *p);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ENET_ETHERNETIF_PRIV_H */
|
||||
|
|
@ -0,0 +1,830 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_SEMC_H_
|
||||
#define _FSL_SEMC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup semc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief SEMC driver version 2.0.4. */
|
||||
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief SEMC status. */
|
||||
enum _semc_status
|
||||
{
|
||||
kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0),
|
||||
kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1),
|
||||
kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2),
|
||||
kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3),
|
||||
kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4),
|
||||
kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5),
|
||||
kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6),
|
||||
kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7),
|
||||
kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8),
|
||||
kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
|
||||
kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10),
|
||||
kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11),
|
||||
};
|
||||
|
||||
/*! @brief SEMC memory device type. */
|
||||
typedef enum _semc_mem_type
|
||||
{
|
||||
kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
|
||||
kSEMC_MemType_SRAM, /*!< SRAM */
|
||||
kSEMC_MemType_NOR, /*!< NOR */
|
||||
kSEMC_MemType_NAND, /*!< NAND */
|
||||
kSEMC_MemType_8080 /*!< 8080. */
|
||||
} semc_mem_type_t;
|
||||
|
||||
/*! @brief SEMC WAIT/RDY polarity. */
|
||||
typedef enum _semc_waitready_polarity
|
||||
{
|
||||
kSEMC_LowActive = 0, /*!< Low active. */
|
||||
kSEMC_HighActive, /*!< High active. */
|
||||
} semc_waitready_polarity_t;
|
||||
|
||||
/*! @brief SEMC SDRAM Chip selection . */
|
||||
typedef enum _semc_sdram_cs
|
||||
{
|
||||
kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
|
||||
kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
|
||||
kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
|
||||
kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
|
||||
} semc_sdram_cs_t;
|
||||
|
||||
/*! @brief SEMC NAND device type. */
|
||||
typedef enum _semc_nand_access_type
|
||||
{
|
||||
kSEMC_NAND_ACCESS_BY_AXI = 0,
|
||||
kSEMC_NAND_ACCESS_BY_IPCMD,
|
||||
} semc_nand_access_type_t;
|
||||
|
||||
/*! @brief SEMC interrupts . */
|
||||
typedef enum _semc_interrupt_enable
|
||||
{
|
||||
kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
|
||||
kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
|
||||
kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
|
||||
kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
|
||||
} semc_interrupt_enable_t;
|
||||
|
||||
/*! @brief SEMC IP command data size in bytes. */
|
||||
typedef enum _semc_ipcmd_datasize
|
||||
{
|
||||
kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
|
||||
kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
|
||||
kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
|
||||
kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
|
||||
} semc_ipcmd_datasize_t;
|
||||
|
||||
/*! @brief SEMC auto-refresh timing. */
|
||||
typedef enum _semc_refresh_time
|
||||
{
|
||||
kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
|
||||
kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
|
||||
kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
|
||||
} semc_refresh_time_t;
|
||||
|
||||
/*! @brief CAS latency */
|
||||
typedef enum _semc_caslatency
|
||||
{
|
||||
kSEMC_LatencyOne = 1, /*!< Latency 1. */
|
||||
kSEMC_LatencyTwo, /*!< Latency 2. */
|
||||
kSEMC_LatencyThree, /*!< Latency 3. */
|
||||
} semc_caslatency_t;
|
||||
|
||||
/*! @brief SEMC sdram column address bit number. */
|
||||
typedef enum _semc_sdram_column_bit_num
|
||||
{
|
||||
kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_SdramColunm_11bit, /*!< 11 bit. */
|
||||
kSEMC_SdramColunm_10bit, /*!< 10 bit. */
|
||||
kSEMC_SdramColunm_9bit, /*!< 9 bit. */
|
||||
} semc_sdram_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC sdram burst length. */
|
||||
typedef enum _semc_sdram_burst_len
|
||||
{
|
||||
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
|
||||
} sem_sdram_burst_len_t;
|
||||
|
||||
/*! @brief SEMC nand column address bit number. */
|
||||
typedef enum _semc_nand_column_bit_num
|
||||
{
|
||||
kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
|
||||
kSEMC_NandColum_15bit, /*!< 15 bit. */
|
||||
kSEMC_NandColum_14bit, /*!< 14 bit. */
|
||||
kSEMC_NandColum_13bit, /*!< 13 bit. */
|
||||
kSEMC_NandColum_12bit, /*!< 12 bit. */
|
||||
kSEMC_NandColum_11bit, /*!< 11 bit. */
|
||||
kSEMC_NandColum_10bit, /*!< 10 bit. */
|
||||
kSEMC_NandColum_9bit, /*!< 9 bit. */
|
||||
} semc_nand_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC nand burst length. */
|
||||
typedef enum _semc_nand_burst_len
|
||||
{
|
||||
kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_nand_burst_len_t;
|
||||
|
||||
/*! @brief SEMC nor/sram column address bit number. */
|
||||
typedef enum _semc_norsram_column_bit_num
|
||||
{
|
||||
kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_NorColum_11bit, /*!< 11 bit. */
|
||||
kSEMC_NorColum_10bit, /*!< 10 bit. */
|
||||
kSEMC_NorColum_9bit, /*!< 9 bit. */
|
||||
kSEMC_NorColum_8bit, /*!< 8 bit. */
|
||||
kSEMC_NorColum_7bit, /*!< 7 bit. */
|
||||
kSEMC_NorColum_6bit, /*!< 6 bit. */
|
||||
kSEMC_NorColum_5bit, /*!< 5 bit. */
|
||||
kSEMC_NorColum_4bit, /*!< 4 bit. */
|
||||
kSEMC_NorColum_3bit, /*!< 3 bit. */
|
||||
kSEMC_NorColum_2bit /*!< 2 bit. */
|
||||
} semc_norsram_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC nor/sram burst length. */
|
||||
typedef enum _semc_norsram_burst_len
|
||||
{
|
||||
kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_norsram_burst_len_t;
|
||||
|
||||
/*! @brief SEMC dbi column address bit number. */
|
||||
typedef enum _semc_dbi_column_bit_num
|
||||
{
|
||||
kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
|
||||
kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
|
||||
kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
|
||||
kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
|
||||
kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
|
||||
kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
|
||||
kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
|
||||
kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
|
||||
kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
|
||||
kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
|
||||
} semc_dbi_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC dbi burst length. */
|
||||
typedef enum _semc_dbi_burst_len
|
||||
{
|
||||
kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_dbi_burst_len_t;
|
||||
|
||||
/*! @brief SEMC IOMUXC. */
|
||||
typedef enum _semc_iomux_pin
|
||||
{
|
||||
kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
|
||||
kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
|
||||
kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
|
||||
kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
|
||||
kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
|
||||
kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
|
||||
} semc_iomux_pin;
|
||||
|
||||
/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
|
||||
typedef enum _semc_iomux_nora27_pin
|
||||
{
|
||||
kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
|
||||
kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
|
||||
kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
|
||||
} semc_iomux_nora27_pin;
|
||||
|
||||
/*! @brief SEMC port size. */
|
||||
typedef enum _semc_port_size
|
||||
{
|
||||
kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
|
||||
kSEMC_PortSize16Bit /*!< 16-Bit port size. */
|
||||
} smec_port_size_t;
|
||||
|
||||
/*! @brief SEMC address mode. */
|
||||
typedef enum _semc_addr_mode
|
||||
{
|
||||
kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
|
||||
kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
|
||||
kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
|
||||
} semc_addr_mode_t;
|
||||
|
||||
/*! @brief SEMC DQS read strobe mode. */
|
||||
typedef enum _semc_dqs_mode
|
||||
{
|
||||
kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
|
||||
kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
|
||||
} semc_dqs_mode_t;
|
||||
|
||||
/*! @brief SEMC ADV signal active polarity. */
|
||||
typedef enum _semc_adv_polarity
|
||||
{
|
||||
kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
|
||||
kSEMC_AdvActivehigh, /*!< Adv active low. */
|
||||
} semc_adv_polarity_t;
|
||||
|
||||
/*! @brief SEMC RDY signal active polarity. */
|
||||
typedef enum _semc_rdy_polarity
|
||||
{
|
||||
kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
|
||||
kSEMC_RdyActivehigh, /*!< Adv active low. */
|
||||
} semc_rdy_polarity_t;
|
||||
|
||||
/*! @brief SEMC IP command for NAND: address mode. */
|
||||
typedef enum _semc_ipcmd_nand_addrmode
|
||||
{
|
||||
kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
|
||||
kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
|
||||
kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
|
||||
kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
|
||||
kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
|
||||
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
|
||||
} semc_ipcmd_nand_addrmode_t;
|
||||
|
||||
/*! @brief SEMC IP command for NAND： command mode. */
|
||||
typedef enum _semc_ipcmd_nand_cmdmode
|
||||
{
|
||||
kSEMC_NANDCM_Command = 0x2U, /*!< command. */
|
||||
kSEMC_NANDCM_CommandHold, /*!< Command hold. */
|
||||
kSEMC_NANDCM_CommandAddress, /*!< Command address. */
|
||||
kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
|
||||
kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
|
||||
kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
|
||||
kSEMC_NANDCM_CommandRead, /*!< Command read. */
|
||||
kSEMC_NANDCM_CommandWrite, /*!< Command write. */
|
||||
kSEMC_NANDCM_Read, /*!< Read. */
|
||||
kSEMC_NANDCM_Write /*!< Write. */
|
||||
} semc_ipcmd_nand_cmdmode_t;
|
||||
|
||||
/*! @brief SEMC NAND address option. */
|
||||
typedef enum _semc_nand_address_option
|
||||
{
|
||||
kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
|
||||
kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
|
||||
kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
|
||||
kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
|
||||
kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
|
||||
kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
|
||||
} semc_nand_address_option_t;
|
||||
|
||||
/*! @brief SEMC IP command for NOR. */
|
||||
typedef enum _semc_ipcmd_nor_dbi
|
||||
{
|
||||
kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
|
||||
kSEMC_NORDBICM_Write /*!< NOR write. */
|
||||
} semc_ipcmd_nor_dbi_t;
|
||||
|
||||
/*! @brief SEMC IP command for SRAM. */
|
||||
typedef enum _semc_ipcmd_sram
|
||||
{
|
||||
kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
|
||||
kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
|
||||
kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
|
||||
kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
|
||||
} semc_ipcmd_sram_t;
|
||||
|
||||
/*! @brief SEMC IP command for SDARM. */
|
||||
typedef enum _semc_ipcmd_sdram
|
||||
{
|
||||
kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
|
||||
kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
|
||||
kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
|
||||
kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
|
||||
kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
|
||||
kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
|
||||
kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
|
||||
kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
|
||||
} semc_ipcmd_sdram_t;
|
||||
|
||||
/*! @brief SEMC SDRAM configuration structure.
|
||||
*
|
||||
* 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
|
||||
* should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
|
||||
* Take refer to BR0~BR3 register in RM for details.
|
||||
* 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
|
||||
* it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
|
||||
* The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
|
||||
* idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
|
||||
* similar to prescalePeriod_N16Cycle.
|
||||
*
|
||||
*/
|
||||
typedef struct _semc_sdram_config
|
||||
{
|
||||
semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
sem_sdram_burst_len_t burstLen; /*!< Burst length. */
|
||||
semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_caslatency_t casLatency; /*!< CAS latency. */
|
||||
uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
|
||||
uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
|
||||
uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
|
||||
uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
|
||||
uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
|
||||
uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
|
||||
uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
|
||||
uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
|
||||
uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
|
||||
uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
|
||||
uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
|
||||
uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
|
||||
uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
|
||||
uint8_t refreshBurstLen; /*!< Refresh burst length. */
|
||||
} semc_sdram_config_t;
|
||||
|
||||
/*! @brief SEMC NAND device timing configuration structure. */
|
||||
typedef struct _semc_nand_timing_config
|
||||
{
|
||||
uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
|
||||
uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time: tRP. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
|
||||
uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
|
||||
uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
|
||||
uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
|
||||
uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
|
||||
uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
|
||||
} semc_nand_timing_config_t;
|
||||
|
||||
/*! @brief SEMC NAND configuration structure. */
|
||||
typedef struct _semc_nand_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
|
||||
uint32_t axiAddress; /*!< The base address for AXI nand. */
|
||||
uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
|
||||
uint32_t ipgAddress; /*!< The base address for IPG nand . */
|
||||
uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
|
||||
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
|
||||
bool edoModeEnabled; /*!< EDO mode enabled. */
|
||||
semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
|
||||
sem_nand_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
|
||||
} semc_nand_config_t;
|
||||
|
||||
/*! @brief SEMC NOR configuration structure. */
|
||||
typedef struct _semc_nor_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
|
||||
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
uint8_t addrPortWidth; /*!< The address port width. */
|
||||
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
|
||||
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
|
||||
semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_addr_mode_t addrMode; /*!< Address mode. */
|
||||
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
|
||||
uint8_t tCeHold_Ns; /*!< The CE hold time. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
|
||||
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
|
||||
uint8_t tAddrHold_Ns; /*!< The address hold time. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
|
||||
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
|
||||
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
|
||||
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
|
||||
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
|
||||
#endif
|
||||
uint8_t latencyCount; /*!< Latency count for sync mode. */
|
||||
uint8_t readCycle; /*!< Read cycle time for sync mode. */
|
||||
} semc_nor_config_t;
|
||||
|
||||
/*! @brief SEMC SRAM configuration structure. */
|
||||
typedef struct _semc_sram_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
|
||||
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
uint8_t addrPortWidth; /*!< The address port width. */
|
||||
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
|
||||
semc_addr_mode_t addrMode; /*!< Address mode. */
|
||||
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
|
||||
uint8_t tCeHold_Ns; /*!< The CE hold time. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
|
||||
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
|
||||
uint8_t tAddrHold_Ns; /*!< The address hold time. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
|
||||
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
|
||||
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
|
||||
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
|
||||
uint8_t latencyCount; /*!< Latency count for sync mode. */
|
||||
uint8_t readCycle; /*!< Read cycle time for sync mode. */
|
||||
} semc_sram_config_t;
|
||||
|
||||
/*! @brief SEMC DBI configuration structure. */
|
||||
typedef struct _semc_dbi_config
|
||||
{
|
||||
semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
|
||||
semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
sem_dbi_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
|
||||
uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
|
||||
uint8_t tWexLow_Ns; /*!< WEX low time. */
|
||||
uint8_t tWexHigh_Ns; /*!< WEX high time. */
|
||||
uint8_t tRdxLow_Ns; /*!< RDX low time. */
|
||||
uint8_t tRdxHigh_Ns; /*!< RDX high time. */
|
||||
uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
|
||||
} semc_dbi_config_t;
|
||||
|
||||
/*! @brief SEMC AXI queue a weight setting structure. */
|
||||
typedef struct _semc_queuea_weight_struct
|
||||
{
|
||||
uint32_t qos : 4; /*!< weight of qos for queue 0 . */
|
||||
uint32_t aging : 4; /*!< weight of aging for queue 0.*/
|
||||
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
|
||||
uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
|
||||
} semc_queuea_weight_struct_t;
|
||||
|
||||
/*! @brief SEMC AXI queue a weight setting union. */
|
||||
typedef union _semc_queuea_weight
|
||||
{
|
||||
semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
|
||||
uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
|
||||
} semc_queuea_weight_t;
|
||||
|
||||
/*! @brief SEMC AXI queue b weight setting structure. */
|
||||
typedef struct _semc_queueb_weight_struct
|
||||
{
|
||||
uint32_t qos : 4; /*!< weight of qos for queue 1. */
|
||||
uint32_t aging : 4; /*!< weight of aging for queue 1.*/
|
||||
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
|
||||
uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
|
||||
uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
|
||||
} semc_queueb_weight_struct_t;
|
||||
|
||||
/*! @brief SEMC AXI queue b weight setting union. */
|
||||
typedef union _semc_queueb_weight
|
||||
{
|
||||
semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
|
||||
uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
|
||||
} semc_queueb_weight_t;
|
||||
|
||||
/*! @brief SEMC AXI queue weight setting. */
|
||||
typedef struct _semc_axi_queueweight
|
||||
{
|
||||
semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
|
||||
semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
|
||||
} semc_axi_queueweight_t;
|
||||
|
||||
/*!
|
||||
* @brief SEMC configuration structure.
|
||||
*
|
||||
* busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
|
||||
* 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
|
||||
* cmdTimeoutCycles: is used for command execution timeout cycles. it's
|
||||
* similar to the busTimeoutCycles.
|
||||
*/
|
||||
typedef struct _semc_config_t
|
||||
{
|
||||
semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
|
||||
uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
|
||||
uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
|
||||
semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
|
||||
} semc_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name SEMC Initialization and De-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the SEMC default basic configuration structure.
|
||||
*
|
||||
* The purpose of this API is to get the default SEMC
|
||||
* configure structure for SEMC_Init(). User may use the initialized
|
||||
* structure unchanged in SEMC_Init(), or modify some fields of the
|
||||
* structure before calling SEMC_Init().
|
||||
* Example:
|
||||
@code
|
||||
semc_config_t config;
|
||||
SEMC_GetDefaultConfig(&config);
|
||||
@endcode
|
||||
* @param config The SEMC configuration structure pointer.
|
||||
*/
|
||||
void SEMC_GetDefaultConfig(semc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Initializes SEMC.
|
||||
* This function ungates the SEMC clock and initializes SEMC.
|
||||
* This function must be called before calling any other SEMC driver functions.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param configure The SEMC configuration structure pointer.
|
||||
*/
|
||||
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the SEMC module and gates the clock.
|
||||
*
|
||||
* This function gates the SEMC clock. As a result, the SEMC module doesn't work after
|
||||
* calling this function, for some IDE, calling this API may cause the next downloading
|
||||
* operation failed. so, please call this API cautiously. Additional, users can
|
||||
* using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
|
||||
* operation in drivers.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
*/
|
||||
void SEMC_Deinit(SEMC_Type *base);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Configuration Operation For Each Memory Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configures SDRAM controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param cs The chip selection.
|
||||
* @param config The sdram configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures NAND controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The nand configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures NOR controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The nor configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures SRAM controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The sram configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures DBI controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The dbi configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Interrupt Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the SEMC interrupt.
|
||||
*
|
||||
* This function enables the SEMC interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
|
||||
* For example, to enable the IP command done and error interrupt, do the following.
|
||||
* @code
|
||||
* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
|
||||
* @endcode
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param mask SEMC interrupts to enable. This is a logical OR of the
|
||||
* enumeration :: semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the SEMC interrupt.
|
||||
*
|
||||
* This function disables the SEMC interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
|
||||
* For example, to disable the IP command done and error interrupt, do the following.
|
||||
* @code
|
||||
* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
|
||||
* @endcode
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param mask SEMC interrupts to disable. This is a logical OR of the
|
||||
* enumeration :: semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN &= ~mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the SEMC status.
|
||||
*
|
||||
* This function gets the SEMC interrupts event status.
|
||||
* User can use the a logical OR of enumeration member as a mask.
|
||||
* See @ref semc_interrupt_enable_t.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
|
||||
*/
|
||||
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
|
||||
{
|
||||
return base->INTR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the SEMC status flag state.
|
||||
*
|
||||
* The following status register flags can be cleared SEMC interrupt status.
|
||||
*
|
||||
* @param base SEMC base pointer
|
||||
* @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTR |= mask;
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Memory Access Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Check if SEMC is in idle.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return True SEMC is in idle, false is not in idle.
|
||||
*/
|
||||
static inline bool SEMC_IsInIdle(SEMC_Type *base)
|
||||
{
|
||||
return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SEMC IP command access.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param type SEMC memory type. refer to "semc_mem_type_t"
|
||||
* @param address SEMC device address.
|
||||
* @param command SEMC IP command.
|
||||
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
|
||||
* For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
|
||||
* For SRAM device, take refer to "semc_ipcmd_sram_t".
|
||||
* For SDRAM device, take refer to "semc_ipcmd_sdram_t".
|
||||
* @param write Data for write access.
|
||||
* @param read Data pointer for read data out.
|
||||
*/
|
||||
status_t SEMC_SendIPCommand(
|
||||
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read);
|
||||
|
||||
/*!
|
||||
* @brief Build SEMC IP command for NAND.
|
||||
*
|
||||
* This function build SEMC NAND IP command. The command is build of user command code,
|
||||
* SEMC address mode and SEMC command mode.
|
||||
*
|
||||
* @param userCommand NAND device normal command.
|
||||
* @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
|
||||
* @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
|
||||
*/
|
||||
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
|
||||
semc_ipcmd_nand_addrmode_t addrMode,
|
||||
semc_ipcmd_nand_cmdmode_t cmdMode)
|
||||
{
|
||||
return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Check if the NAND device is ready.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return True NAND is ready, false NAND is not ready.
|
||||
*/
|
||||
static inline bool SEMC_IsNandReady(SEMC_Type *base)
|
||||
{
|
||||
return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SEMC NAND device memory write through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NAND device address.
|
||||
* @param data Data for write access.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NAND device memory read through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NAND device address.
|
||||
* @param data Data pointer for data read out.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NOR device memory write through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NOR device address.
|
||||
* @param data Data for write access.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NOR device memory read through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NOR device address.
|
||||
* @param data Data pointer for data read out.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_SEMC_H_*/
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
config BSP_USING_EXTSRAM
|
||||
bool "config semc extern sram"
|
||||
default n
|
||||
select MEM_EXTERN_SRAM
|
||||
if BSP_USING_EXTSRAM
|
||||
config EXTSRAM_MAX_NUM
|
||||
int "config extsram chip num"
|
||||
default 4
|
||||
endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := connect_semc.c fsl_semc.c semc_externsdram_test.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
#include "fsl_semc.h"
|
||||
#include "clock_config.h"
|
||||
#include <xs_base.h>
|
||||
|
||||
#define EXAMPLE_SEMC SEMC
|
||||
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
|
||||
#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk)
|
||||
#define SEMC_SRAM_SIZE (32 * 1024 * 1024)
|
||||
|
||||
status_t BOARD_InitSEMC(void)
|
||||
{
|
||||
semc_config_t config;
|
||||
semc_sdram_config_t sdramconfig;
|
||||
uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;
|
||||
|
||||
/* Initializes the MAC configure structure to zero. */
|
||||
memset(&config, 0, sizeof(semc_config_t));
|
||||
memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
|
||||
|
||||
/* Initialize SEMC. */
|
||||
SEMC_GetDefaultConfig(&config);
|
||||
config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
|
||||
SEMC_Init(SEMC, &config);
|
||||
|
||||
/* Configure SDRAM. */
|
||||
sdramconfig.csxPinMux = kSEMC_MUXCSX0;
|
||||
sdramconfig.address = 0x80000000;
|
||||
sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/
|
||||
sdramconfig.portSize = kSEMC_PortSize16Bit;
|
||||
sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;
|
||||
sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;
|
||||
sdramconfig.casLatency = kSEMC_LatencyThree;
|
||||
sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */
|
||||
sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */
|
||||
sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
|
||||
sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */
|
||||
sdramconfig.tCkeOff_Ns =
|
||||
42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
|
||||
sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */
|
||||
sdramconfig.tSelfRefRecovery_Ns = 67;
|
||||
sdramconfig.tRefresh2Refresh_Ns = 60;
|
||||
sdramconfig.tAct2Act_Ns = 60;
|
||||
sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
|
||||
sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
|
||||
sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
|
||||
sdramconfig.refreshBurstLen = 1;
|
||||
return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_EXTSRAM
|
||||
int ExtSramInit(void)
|
||||
{
|
||||
extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
|
||||
ExtSramInitBoardMemory((void*)(EXAMPLE_SEMC_START_ADDRESS), (void*)((EXAMPLE_SEMC_START_ADDRESS + SEMC_SRAM_SIZE)), kSEMC_SDRAM_CS0);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include "board.h"
|
||||
|
||||
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
|
||||
|
||||
#define SEMC_EXAMPLE_DATALEN (0x1000U)
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
static void SEMC_SDRAMReadWrite32Bit(void);
|
||||
static void SEMC_SDRAMReadWrite16Bit(void);
|
||||
static void SEMC_SDRAMReadWrite8Bit(void);
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN];
|
||||
uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN];
|
||||
|
||||
/*!
|
||||
* @brief Main function
|
||||
*/
|
||||
int semc_externsram_test(void)
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM Example Start!\r\n");
|
||||
|
||||
/* 32Bit data read and write. */
|
||||
SEMC_SDRAMReadWrite32Bit();
|
||||
/* 16Bit data read and write. */
|
||||
SEMC_SDRAMReadWrite16Bit();
|
||||
/* 8Bit data read and write. */
|
||||
SEMC_SDRAMReadWrite8Bit();
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Example End.\r\n");
|
||||
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),semc_externsram_test, semc_externsram_test, semc_externsram_test );
|
||||
|
||||
void SEMC_SDRAMReadWrite32Bit(void)
|
||||
{
|
||||
uint32_t index;
|
||||
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
|
||||
uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
|
||||
int result = 0;
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
|
||||
/* Prepare data and write to SDRAM. */
|
||||
for (index = 0; index < datalen; index++)
|
||||
{
|
||||
sdram_writeBuffer[index] = index;
|
||||
sdram[index] = sdram_writeBuffer[index];
|
||||
}
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
|
||||
/* Read data from the SDRAM. */
|
||||
for (index = 0; index < datalen; index++)
|
||||
{
|
||||
sdram_readBuffer[index] = sdram[index];
|
||||
}
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n");
|
||||
/* Compare the two buffers. */
|
||||
while (datalen--)
|
||||
{
|
||||
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
|
||||
{
|
||||
result = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (result < 0)
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void SEMC_SDRAMReadWrite16Bit(void)
|
||||
{
|
||||
uint32_t index;
|
||||
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
|
||||
uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
|
||||
int result = 0;
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
|
||||
|
||||
memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
|
||||
memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
|
||||
|
||||
/* Prepare data and write to SDRAM. */
|
||||
for (index = 0; index < datalen; index++)
|
||||
{
|
||||
sdram_writeBuffer[index] = index % 0xFFFF;
|
||||
sdram[index] = sdram_writeBuffer[index];
|
||||
}
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
|
||||
/* Read data from the SDRAM. */
|
||||
for (index = 0; index < datalen; index++)
|
||||
{
|
||||
sdram_readBuffer[index] = sdram[index];
|
||||
}
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n");
|
||||
/* Compare the two buffers. */
|
||||
while (datalen--)
|
||||
{
|
||||
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
|
||||
{
|
||||
result = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (result < 0)
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void SEMC_SDRAMReadWrite8Bit(void)
|
||||
{
|
||||
uint32_t index;
|
||||
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
|
||||
uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
|
||||
int result = 0;
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
|
||||
|
||||
memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
|
||||
memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
|
||||
|
||||
/* Prepare data and write to SDRAM. */
|
||||
for (index = 0; index < datalen; index++)
|
||||
{
|
||||
sdram_writeBuffer[index] = index % 0x100;
|
||||
sdram[index] = sdram_writeBuffer[index];
|
||||
}
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
|
||||
/* Read data from the SDRAM. */
|
||||
for (index = 0; index < datalen; index++)
|
||||
{
|
||||
sdram_readBuffer[index] = sdram[index];
|
||||
}
|
||||
|
||||
KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n");
|
||||
/* Compare the two buffers. */
|
||||
while (datalen--)
|
||||
{
|
||||
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
|
||||
{
|
||||
result = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (result < 0)
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -72,76 +72,6 @@ const BOOT_DATA_T boot_data = {
|
|||
#elif defined(__ICCARM__)
|
||||
#pragma location=".boot_hdr.dcd_data"
|
||||
#endif
|
||||
//const uint8_t dcd_sdram[1044] = {
|
||||
///*0000*/ 0xD2, 0x04, 0x14, 0x41, 0xCC, 0x02, 0xF4, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
///*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
///*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
///*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
///*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
|
||||
///*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x09, 0x83, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||
///*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||
///*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||
///*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00,
|
||||
///*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x00, 0x00, 0xF1,
|
||||
///*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x00, 0x00, 0xF1, 0xCC, 0x00, 0x0C, 0x14, 0x40, 0x2F, 0x00, 0x00,
|
||||
///*0300*/ 0x00, 0x00, 0x00, 0x02, 0xCC, 0x00, 0x9C, 0x04, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||
///*0310*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24,
|
||||
///*0320*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x14, 0x90, 0x00, 0x00, 0x21,
|
||||
///*0330*/ 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0B, 0x27,
|
||||
///*0340*/ 0x40, 0x2F, 0x00, 0x44, 0x00, 0x10, 0x01, 0x00, 0x40, 0x2F, 0x00, 0x48, 0x00, 0x02, 0x02, 0x01,
|
||||
///*0350*/ 0x40, 0x2F, 0x00, 0x4C, 0x08, 0x19, 0x3D, 0x0E, 0x40, 0x2F, 0x00, 0x74, 0x00, 0x65, 0x29, 0x22,
|
||||
///*0360*/ 0x40, 0x2F, 0x00, 0x78, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x7C, 0x50, 0x21, 0x0A, 0x08,
|
||||
///*0370*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||
///*0380*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
///*0390*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||
///*03a0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04,
|
||||
///*03b0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
///*03c0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04,
|
||||
///*03d0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
///*03e0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04,
|
||||
///*03f0*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x22, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
///*0400*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C,
|
||||
///*0410*/ 0x00, 0x00, 0x00, 0x01,
|
||||
//};
|
||||
|
||||
|
||||
|
||||
const uint8_t dcd_sdram[1072] = {
|
||||
/*0000*/ 0xD2,
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
/**
|
||||
* @file TestCh438.c
|
||||
* @brief support to test ch438 function
|
||||
* @brief support to test ch438 function, only support aiit_arm32_board and aiit_riscv64-board
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-24
|
||||
|
|
|
|||
|
|
@ -13,10 +13,21 @@ KERNELPATHS :=-I$(BSP_ROOT) \
|
|||
-I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/include \
|
||||
-I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/osa \
|
||||
-I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/phy \
|
||||
-I$(BSP_ROOT)/third_party_driver/ethernet \
|
||||
-I$(BSP_ROOT)/third_party_driver/ethernet/lan8720 \
|
||||
-I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \
|
||||
-I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \
|
||||
-I$(BSP_ROOT)/third_party_driver/CMSIS/Include \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \
|
||||
-I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \
|
||||
-I$(KERNEL_ROOT)/resources/include \
|
||||
-I$(BSP_ROOT)/include \
|
||||
-I$(BSP_ROOT)/xip #
|
||||
|
|
|
|||
Loading…
Reference in New Issue