From a6b403984e975a91df96285da09cc1d20580c9d4 Mon Sep 17 00:00:00 2001 From: chunyexixiaoyu <834670833@qq.com> Date: Thu, 7 Apr 2022 18:16:58 +0800 Subject: [PATCH] Ubiquitous/RT-Thread_Fusion_XiUOS/:modify the code in xidatong --- .../aiit_board/xidatong/board/MCUX_Config/pin_mux.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong/board/MCUX_Config/pin_mux.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong/board/MCUX_Config/pin_mux.c index 22ec13700..38c3e231b 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong/board/MCUX_Config/pin_mux.c +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong/board/MCUX_Config/pin_mux.c @@ -66,12 +66,7 @@ void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ - /*CH438 IO initialize - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD - 0U);*/ - - /* uart 1 2 3 4 8 io initialize */ + /* uart 1 */ IOMUXC_SetPinMux( IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ 0U); /* Software Input On Field: Input Path is determined by functionality */